From 76848492b01c99720c548f2e2d39b1d942b0df8a Mon Sep 17 00:00:00 2001
From: Gunar Schorcht <gunar@schorcht.net>
Date: Wed, 28 Sep 2022 18:24:37 +0200
Subject: [PATCH] cpu/stm32: add tinyUSB package support

---
 cpu/stm32/include/clk/f2f4f7/cfg_clock_default_100.h | 4 ++--
 cpu/stm32/include/clk/f2f4f7/cfg_clock_default_180.h | 6 +++---
 cpu/stm32/stmclk/stmclk_f2f4f7.c                     | 8 ++++----
 cpu/stm32/stmclk/stmclk_l4wx.c                       | 4 ++--
 4 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_100.h b/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_100.h
index ed1f54755c..6187b671e7 100644
--- a/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_100.h
+++ b/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_100.h
@@ -44,7 +44,7 @@ extern "C" {
 #endif
 #endif
 #ifndef CONFIG_CLOCK_PLL_N
-#if IS_USED(MODULE_PERIPH_USBDEV) && defined(CPU_LINE_STM32F411xE)
+#if IS_USED(MODULE_PERIPH_USBDEV_CLK) && defined(CPU_LINE_STM32F411xE)
 #if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(8))
 #define CONFIG_CLOCK_PLL_N              (96)
 #elif IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE == MHZ(25))
@@ -60,7 +60,7 @@ extern "C" {
 #else
 #define CONFIG_CLOCK_PLL_N              (50)
 #endif
-#endif /* MODULE_PERIPH_USBDEV */
+#endif /* MODULE_PERIPH_USBDEV_CLK */
 #endif
 #ifndef CONFIG_CLOCK_PLL_P
 #define CONFIG_CLOCK_PLL_P              (2)
diff --git a/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_180.h b/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_180.h
index f9cf35c7fb..cc6f137245 100644
--- a/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_180.h
+++ b/cpu/stm32/include/clk/f2f4f7/cfg_clock_default_180.h
@@ -46,7 +46,7 @@ extern "C" {
 #endif
 #endif
 #ifndef CONFIG_CLOCK_PLL_N
-#if IS_USED(MODULE_PERIPH_USBDEV) && \
+#if IS_USED(MODULE_PERIPH_USBDEV_CLK) && \
     (defined(CPU_LINE_STM32F405xx) || defined(CPU_LINE_STM32F407xx) || \
      defined(CPU_LINE_STM32F415xx) || defined(CPU_LINE_STM32F417xx) || \
      defined(CPU_LINE_STM32F427xx) || defined(CPU_LINE_STM32F429xx) || \
@@ -68,13 +68,13 @@ extern "C" {
 #else
 #define CONFIG_CLOCK_PLL_N              (90)
 #endif
-#endif /* MODULE_PERIPH_USBDEV */
+#endif /* MODULE_PERIPH_USBDEV_CLK */
 #endif
 #ifndef CONFIG_CLOCK_PLL_P
 #define CONFIG_CLOCK_PLL_P              (2)
 #endif
 #ifndef CONFIG_CLOCK_PLL_Q
-#if IS_USED(MODULE_PERIPH_USBDEV) && \
+#if IS_USED(MODULE_PERIPH_USBDEV_CLK) && \
     (defined(CPU_LINE_STM32F405xx) || defined(CPU_LINE_STM32F407xx) || \
      defined(CPU_LINE_STM32F415xx) || defined(CPU_LINE_STM32F417xx) || \
      defined(CPU_LINE_STM32F427xx) || defined(CPU_LINE_STM32F429xx) || \
diff --git a/cpu/stm32/stmclk/stmclk_f2f4f7.c b/cpu/stm32/stmclk/stmclk_f2f4f7.c
index 64d05cd607..9459fffcf0 100644
--- a/cpu/stm32/stmclk/stmclk_f2f4f7.c
+++ b/cpu/stm32/stmclk/stmclk_f2f4f7.c
@@ -56,7 +56,7 @@
 /* Determine if PLL is required, even if not used as SYSCLK
    This is the case when USB is used in application and PLLQ is configured to
    output 48MHz */
-#if IS_USED(MODULE_PERIPH_USBDEV) && (CLOCK_PLLQ == MHZ(48))
+#if IS_USED(MODULE_PERIPH_USBDEV_CLK) && (CLOCK_PLLQ == MHZ(48))
 #define CLOCK_REQUIRE_PLLQ          1
 #else
 #define CLOCK_REQUIRE_PLLQ          0
@@ -67,7 +67,7 @@
 #if (defined(CPU_LINE_STM32F412Cx) || defined(CPU_LINE_STM32F412Rx) || \
      defined(CPU_LINE_STM32F412Vx) || defined(CPU_LINE_STM32F412Zx) || \
      defined(CPU_LINE_STM32F413xx) || defined(CPU_LINE_STM32F423xx)) && \
-    IS_USED(MODULE_PERIPH_USBDEV) && !IS_ACTIVE(CLOCK_REQUIRE_PLLQ)
+    IS_USED(MODULE_PERIPH_USBDEV_CLK) && !IS_ACTIVE(CLOCK_REQUIRE_PLLQ)
 #define CLOCK_REQUIRE_PLLI2SR       1
 #else
 /* Disable PLLI2S if USB is not required or is required but PLLQ cannot generate 48MHz clock */
@@ -78,14 +78,14 @@
    PLLSAI is only enabled if no suitable 48MHz clock source can be generated with PLLQ */
 #if (defined(CPU_LINE_STM32F446xx) || defined(CPU_LINE_STM32F469xx) || \
      defined(CPU_LINE_STM32F479xx) || defined(CPU_FAM_STM32F7)) && \
-    IS_USED(MODULE_PERIPH_USBDEV) && !IS_ACTIVE(CLOCK_REQUIRE_PLLQ)
+    IS_USED(MODULE_PERIPH_USBDEV_CLK) && !IS_ACTIVE(CLOCK_REQUIRE_PLLQ)
 #define CLOCK_REQUIRE_PLLSAIP       1
 #else
 /* Disable PLLSAI if USB is not required or is required but PLLQ cannot generate 48MHz clock */
 #define CLOCK_REQUIRE_PLLSAIP       0
 #endif
 
-#if IS_USED(MODULE_PERIPH_USBDEV) && \
+#if IS_USED(MODULE_PERIPH_USBDEV_CLK) && \
     !(IS_ACTIVE(CLOCK_REQUIRE_PLLQ) || \
       IS_ACTIVE(CLOCK_REQUIRE_PLLI2SR) || \
       IS_ACTIVE(CLOCK_REQUIRE_PLLSAIP))
diff --git a/cpu/stm32/stmclk/stmclk_l4wx.c b/cpu/stm32/stmclk/stmclk_l4wx.c
index d511a53f41..b58eaa3b1d 100644
--- a/cpu/stm32/stmclk/stmclk_l4wx.c
+++ b/cpu/stm32/stmclk/stmclk_l4wx.c
@@ -351,7 +351,7 @@
 #endif
 
 /* periph_hwrng and periph_usbdev require a 48MHz clock source */
-#if IS_USED(MODULE_PERIPH_HWRNG) || IS_USED(MODULE_PERIPH_USBDEV)
+#if IS_USED(MODULE_PERIPH_HWRNG) || IS_USED(MODULE_PERIPH_USBDEV_CLK)
 #if !IS_ACTIVE(CLOCK48MHZ_USE_PLLQ) && !IS_ACTIVE(CLOCK48MHZ_USE_MSI) && \
     !IS_ACTIVE(CLOCK48MHZ_USE_HSI48)
 #error "No 48MHz clock source available, HWRNG cannot work"
@@ -663,7 +663,7 @@ void stmclk_init_sysclk(void)
         gpio_init_af(GPIO_PIN(PORT_A, 8), GPIO_AF0);
     }
 
-#if IS_USED(MODULE_PERIPH_USBDEV) && defined(RCC_APB1RSTR1_USBRST)
+#if IS_USED(MODULE_PERIPH_USBDEV_CLK) && defined(RCC_APB1RSTR1_USBRST)
     RCC->APB1RSTR1 |= RCC_APB1RSTR1_USBRST;
     RCC->APB1RSTR1 &= ~RCC_APB1RSTR1_USBRST;
 #endif