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Merge pull request #7420 from MichelRottleuthner/rtc_stm32l4

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periph/rtc: add support for stm32l4
This commit is contained in:
Hauke Petersen 2017-08-21 10:10:26 +02:00 committed by GitHub
commit 768459d6c1
3 changed files with 40 additions and 6 deletions
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3
boards/nucleo-l476/Makefile.features
View File

@ -3,9 +3,10 @@ FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_hwrng
FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_uart
# load the common Makefile.features for Nucleo boards

7
boards/nucleo-l476/include/periph_conf.h
View File

@ -238,6 +238,13 @@ static const spi_conf_t spi_config[] = {
#define RTT_MAX_VALUE (0x0000ffff) /* 16-bit timer */
/** @} */
/**
* @name RTC configuration
* @{
*/
#define RTC_NUMOF (1)
/** @} */
#ifdef __cplusplus
}
#endif

36
cpu/stm32_common/periph/rtc.c
View File

@ -29,7 +29,7 @@
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F2) || \
defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32F4) || \
defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L0) || \
defined(CPU_FAM_STM32L1)
defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32L4)
/* guard file in case no RTC device was specified */
#if RTC_NUMOF
@ -60,8 +60,12 @@ static uint8_t byte2bcd(uint8_t value);
void rtc_init(void)
{
/* Enable write access to RTC registers */
#if defined(CPU_FAM_STM32L4)
periph_clk_en(APB1, RCC_APB1ENR1_PWREN);
#else
periph_clk_en(APB1, RCC_APB1ENR_PWREN);
#if defined(CPU_FAM_STM32F7)
#endif
#if defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L4)
PWR->CR1 |= PWR_CR1_DBP;
#else
PWR->CR |= PWR_CR_DBP;
@ -103,8 +107,13 @@ void rtc_init(void)
int rtc_set_time(struct tm *time)
{
/* Enable write access to RTC registers */
#if defined(CPU_FAM_STM32L4)
periph_clk_en(APB1, RCC_APB1ENR1_PWREN);
#else
periph_clk_en(APB1, RCC_APB1ENR_PWREN);
#if defined(CPU_FAM_STM32F7)
#endif
#if defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L4)
PWR->CR1 |= PWR_CR1_DBP;
#else
PWR->CR |= PWR_CR_DBP;
@ -169,8 +178,13 @@ int rtc_get_time(struct tm *time)
int rtc_set_alarm(struct tm *time, rtc_alarm_cb_t cb, void *arg)
{
/* Enable write access to RTC registers */
#if defined(CPU_FAM_STM32L4)
periph_clk_en(APB1, RCC_APB1ENR1_PWREN);
#else
periph_clk_en(APB1, RCC_APB1ENR_PWREN);
#if defined(CPU_FAM_STM32F7)
#endif
#if defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L4)
PWR->CR1 |= PWR_CR1_DBP;
#else
PWR->CR |= PWR_CR_DBP;
@ -204,11 +218,17 @@ int rtc_set_alarm(struct tm *time, rtc_alarm_cb_t cb, void *arg)
#if defined(CPU_FAM_STM32L0)
EXTI->IMR |= EXTI_IMR_IM17;
#elif defined (CPU_FAM_STM32L4)
EXTI->IMR |= EXTI_IMR1_IM18;
#else
EXTI->IMR |= EXTI_IMR_MR17;
#endif
#if defined (CPU_FAM_STM32L4)
EXTI->RTSR |= EXTI_RTSR1_RT18;
#else
EXTI->RTSR |= EXTI_RTSR_TR17;
#endif
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0)
NVIC_SetPriority(RTC_IRQn, 10);
@ -321,7 +341,13 @@ void isr_rtc_alarm(void)
}
RTC->ISR &= ~RTC_ISR_ALRAF;
}
#if defined(CPU_FAM_STM32L4)
EXTI->PR |= EXTI_PR1_PIF18;
#else
EXTI->PR |= EXTI_PR_PR17;
#endif
cortexm_isr_end();
}
@ -348,4 +374,4 @@ static uint8_t byte2bcd(uint8_t value)
#endif /* defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F2) || \
defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32F4) || \
defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L0) || \
defined(CPU_FAM_STM32L1) */
defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32L4)*/