From 749b2912736751af94c956eead1e79183999f2c7 Mon Sep 17 00:00:00 2001
From: Vincent Dupont <vincent@otakeys.com>
Date: Wed, 27 Mar 2019 16:42:16 +0100
Subject: [PATCH] cpu/stm32_common: fix rtt registers access

---
 cpu/stm32_common/periph/rtt.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/cpu/stm32_common/periph/rtt.c b/cpu/stm32_common/periph/rtt.c
index 8ecd22d63c..e215020ba7 100644
--- a/cpu/stm32_common/periph/rtt.c
+++ b/cpu/stm32_common/periph/rtt.c
@@ -95,14 +95,20 @@ void rtt_init(void)
     /* enable timer */
     LPTIM1->CR = LPTIM_CR_ENABLE;
     /* set auto-reload value (timer needs to be enabled for this) */
+    LPTIM1->ICR = LPTIM_ICR_ARROKCF;
     LPTIM1->ARR = RTT_MAX_VALUE;
+    while (!(LPTIM1->ISR & LPTIM_ISR_ARROK)) {}
     /* start the timer */
     LPTIM1->CR |= LPTIM_CR_CNTSTRT;
 }
 
 uint32_t rtt_get_counter(void)
 {
-    return (uint32_t)LPTIM1->CNT;
+    uint32_t cnt;
+    do {
+        cnt = LPTIM1->CNT;
+    } while (cnt != LPTIM1->CNT);
+    return cnt;
 }
 
 void rtt_set_overflow_cb(rtt_cb_t cb, void *arg)
@@ -125,9 +131,11 @@ void rtt_set_alarm(uint32_t alarm, rtt_cb_t cb, void *arg)
     assert(cb && !(alarm & ~RTT_MAX_VALUE));
 
     unsigned is = irq_disable();
+    LPTIM1->ICR = LPTIM_ICR_CMPOKCF;
     to_cb  = cb;
     to_arg = arg;
     LPTIM1->CMP = (uint16_t)alarm;
+    while (!(LPTIM1->ISR & LPTIM_ISR_CMPOK)) {}
     irq_restore(is);
 }