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cpu/nrf5x_common: share nRF52 PWM driver with nRF53/nRF9160

Signed-off-by: Dylan Laduranty <dylan.laduranty@mesotic.com>
This commit is contained in:
Dylan Laduranty 2023-07-07 09:07:15 +02:00 committed by dylad
parent c19626c525
commit 6ea5081da9
4 changed files with 58 additions and 49 deletions

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@ -153,54 +153,6 @@ typedef struct {
#define i2c_pin_scl(dev) i2c_config[dev].scl
/** @} */
/**
* @name The PWM unit on the nRF52 supports 4 channels per device
*/
#define PWM_CHANNELS (4U)
/**
* @name Generate PWM mode values
*
* To encode the PWM mode, we use two bit:
* - bit 0: select up or up-and-down counting
* - bit 15: select polarity
*/
#define PWM_MODE(ud, pol) (ud | (pol << 15))
/**
* @brief Override the PWM mode definitions
* @{
*/
#define HAVE_PWM_MODE_T
typedef enum {
PWM_LEFT = PWM_MODE(0, 1), /**< left aligned PWM */
PWM_RIGHT = PWM_MODE(0, 0), /**< right aligned PWM */
PWM_CENTER = PWM_MODE(1, 1), /**< not supported */
PWM_CENTER_INV = PWM_MODE(1, 0) /**< not supported */
} pwm_mode_t;
/** @} */
/**
* @brief PWM configuration options
*
* Each device supports up to 4 channels. If you want to use less than 4
* channels, just set the unused pins to GPIO_UNDEF.
*
* @note define unused pins only from right to left, so the defined channels
* always start with channel 0 to x and the undefined ones are from x+1
* to PWM_CHANNELS.
*
* @warning All the channels not in active use must be set to GPIO_UNDEF; just
* initializing fewer members of pin would insert a 0 value, which
* would be interpreted as the P0.00 pin that's then driven.
*/
#if defined(PWM_PRESENT) || DOXYGEN
typedef struct {
NRF_PWM_Type *dev; /**< PWM device descriptor */
gpio_t pin[PWM_CHANNELS]; /**< PWM out pins */
} pwm_conf_t;
#endif
/**
* @brief Size of the UART TX buffer for non-blocking mode.
*/

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@ -312,6 +312,55 @@ typedef struct {
*/
#define USBDEV_CPU_DMA_REQUIREMENTS __attribute__((aligned(USBDEV_CPU_DMA_ALIGNMENT)))
#if !defined(CPU_FAM_NRF51) && !defined(DOXYGEN)
/**
* @brief The PWM unit on the nRF52, nRF53 and nRF9160
* supports 4 channels per device
*/
#define PWM_CHANNELS (4U)
/**
* @brief Generate PWM mode values
*
* To encode the PWM mode, we use two bit:
* - bit 0: select up or up-and-down counting
* - bit 15: select polarity
*/
#define PWM_MODE(ud, pol) (ud | (pol << 15))
/**
* @brief Override the PWM mode definitions
*/
#define HAVE_PWM_MODE_T
typedef enum {
PWM_LEFT = PWM_MODE(0, 1), /**< left aligned PWM */
PWM_RIGHT = PWM_MODE(0, 0), /**< right aligned PWM */
PWM_CENTER = PWM_MODE(1, 1), /**< not supported */
PWM_CENTER_INV = PWM_MODE(1, 0) /**< not supported */
} pwm_mode_t;
/**
* @brief PWM configuration options
*
* Each device supports up to 4 channels. If you want to use less than 4
* channels, just set the unused pins to GPIO_UNDEF.
*
* @note define unused pins only from right to left, so the defined channels
* always start with channel 0 to x and the undefined ones are from x+1
* to PWM_CHANNELS.
*
* @warning All the channels not in active use must be set to GPIO_UNDEF; just
* initializing fewer members of pin would insert a 0 value, which
* would be interpreted as the P0.00 pin that's then driven.
*/
#if defined(PWM_PRESENT)
typedef struct {
NRF_PWM_Type *dev; /**< PWM device descriptor */
gpio_t pin[PWM_CHANNELS]; /**< PWM out pins */
} pwm_conf_t;
#endif
#endif /* ndef CPU_FAM_NRF51 */
#ifdef __cplusplus
}
#endif

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@ -7,6 +7,14 @@ ifneq (,$(filter periph_i2c,$(USEMODULE)))
endif
endif
# Select the specific implementation for `periph_pwm`
# nRF51 has its own PWM driver variant in its periph driver folder
ifneq (,$(filter periph_pwm,$(USEMODULE)))
ifneq (,$(filter $(CPU_FAM),nrf52 nrf53 nrf9160))
SRC += pwm_nrfxx.c
endif
endif
# Select the specific implementation for `periph_spi`
ifneq (,$(filter periph_spi,$(USEMODULE)))
ifneq (,$(filter $(CPU_FAM),nrf52 nrf9160))

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@ -7,7 +7,7 @@
*/
/**
* @ingroup cpu_nrf52
* @ingroup cpu_nrf5x_common
* @{
*
* @file