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https://github.com/RIOT-OS/RIOT.git
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cpu/esp32: replace startup by architecture dependent ESP-IDF startup
This commit is contained in:
Gunar Schorcht
parent
a88cb32a18
commit
6dd2659846
@ -21,6 +21,7 @@ ESP32_SDK_SRC = \
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components/esp_rom/patches/esp_rom_uart.c \
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components/esp_system/esp_err.c \
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components/esp_system/esp_system.c \
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components/esp_system/port/cpu_start.c \
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components/esp_system/port/soc/$(CPU)/cache_err_int.c \
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components/esp_system/port/soc/$(CPU)/clk.c \
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components/esp_system/port/soc/$(CPU)/reset_reason.c \
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@ -45,24 +45,33 @@
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/* ESP-IDF headers */
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#include "driver/periph_ctrl.h"
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#include "esp_attr.h"
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#include "esp_clk_internal.h"
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#include "esp_heap_caps_init.h"
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#include "esp_log.h"
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#include "esp_private/startup_internal.h"
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#include "esp_private/esp_clk.h"
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#include "esp_rom_uart.h"
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#include "esp_sleep.h"
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#include "esp_timer.h"
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#include "hal/interrupt_controller_types.h"
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#include "hal/interrupt_controller_ll.h"
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#include "rom/cache.h"
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#include "rom/ets_sys.h"
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#include "rom/rtc.h"
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#include "rom/uart.h"
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#include "soc/apb_ctrl_reg.h"
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#include "soc/cpu.h"
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#include "soc/dport_reg.h"
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#include "soc/dport_access.h"
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#include "soc/rtc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/rtc_cntl_struct.h"
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#include "soc/timer_group_struct.h"
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#if __xtensa__
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#include "soc/dport_reg.h"
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#include "soc/dport_access.h"
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#include "xtensa/core-macros.h"
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#include "xtensa/xtensa_api.h"
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#endif
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#if IS_USED(MODULE_ESP_SPI_RAM)
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#include "spiram.h"
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@ -101,70 +110,50 @@ extern uint8_t _rtc_bss_rtc_end;
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extern uint8_t _iram_start;
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/* external esp function declarations */
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extern void esp_clk_init(void);
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extern void esp_perip_clk_init(void);
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extern void esp_reent_init(struct _reent* r);
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extern uint32_t hwrand (void);
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extern void bootloader_clock_configure(void);
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/* external RTC function declarations since they are not declared in headers */
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/* components/esp_hw_support/include/esp_private/esp_clk.h */
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extern int esp_clk_apb_freq(void);
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extern int esp_clk_cpu_freq(void);
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extern int esp_clk_xtal_freq(void);
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extern uint32_t esp_clk_slowclk_cal_get(void);
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/* components/esp_hw_support/include/soc/esp32/rtc.h */
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extern uint64_t esp_rtc_get_time_us(void);
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/* components/esp_system/port/include/esp_clk_internal.h */
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extern void IRAM_ATTR rtc_clk_select_rtc_slow_clk(rtc_slow_freq_t slow_clk);
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/* forward declarations */
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static void system_init(void);
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static void intr_matrix_clear(void);
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typedef int32_t esp_err_t;
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static void IRAM system_startup_cpu0(void);
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static void IRAM system_init(void);
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extern void IRAM_ATTR thread_yield_isr(void* arg);
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uint64_t g_startup_time = 0;
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const sys_startup_fn_t g_startup_fn[1] = { system_startup_cpu0 };
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#if CONFIG_ESP_TIMER_IMPL_FRC2
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/* dummy function required if FRC2 (legacy) timer of the ESP32 is used */
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esp_err_t esp_timer_impl_early_init(void)
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{
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return ESP_OK;
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}
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#endif
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/**
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* @brief CPU startup function
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* @brief System startup function
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*
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* This function is the entry point in the user application. It is called
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* after a system reset to startup the system.
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* after a CPU initialization to startup the system.
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*/
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NORETURN void IRAM call_start_cpu0 (void)
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static NORETURN void IRAM system_startup_cpu0(void)
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{
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#if __xtensa__
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register uint32_t *sp __asm__ ("a1"); (void)sp;
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esp_cpu_configure_region_protection();
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/* move exception vectors to IRAM */
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asm volatile ("wsr %0, vecbase\n" ::"r"(&_iram_start));
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RESET_REASON reset_reason = rtc_get_reset_reason(PRO_CPU_NUM);
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/* reset from panic handler by RWDT or TG0WDT */
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if (reset_reason == RTCWDT_SYS_RESET || reset_reason == TG0WDT_SYS_RESET) {
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/* TODO esp_panic_wdt_stop was called here in former versions */
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}
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#endif
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#if __riscv
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register uint32_t *sp __asm__ ("x2"); (void)sp;
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#endif
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#ifdef MODULE_PUF_SRAM
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puf_sram_init((uint8_t *)&_sheap, SEED_RAM_LEN);
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#endif
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/* Clear BSS. Please do not attempt to do any complex stuff */
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/* (like early logging) before this. */
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/* cppcheck-suppress comparePointers */
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memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
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/* initialize stdio */
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esp_rom_uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
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stdio_init();
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/* if we are not waking up from deep sleep, clear RTC bss */
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if (reset_reason != DEEPSLEEP_RESET) {
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/* cppcheck-suppress comparePointers */
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memset(&_rtc_bss_start, 0, (&_rtc_bss_end - &_rtc_bss_start));
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}
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RESET_REASON reset_reason = rtc_get_reset_reason(PRO_CPU_NUM);
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/* initialize RTC data after power on */
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/* initialize RTC data after power on or RTC WDT reset */
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if (reset_reason == POWERON_RESET || reset_reason == RTCWDT_RTC_RESET) {
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/* cppcheck-suppress comparePointers */
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memset(&_rtc_bss_rtc_start, 0, (&_rtc_bss_rtc_end - &_rtc_bss_rtc_start));
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@ -174,8 +163,7 @@ NORETURN void IRAM call_start_cpu0 (void)
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cpuid_get ((void*)cpu_id);
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#if IS_USED(MODULE_ESP_LOG_STARTUP)
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ets_printf("\n");
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LOG_STARTUP("Starting ESP32 with ID: ");
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LOG_STARTUP("\nStarting ESP32x with ID: ");
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for (unsigned i = 0; i < CPUID_LEN; i++) {
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ets_printf("%02x", cpu_id[i]);
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}
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@ -211,134 +199,49 @@ NORETURN void IRAM call_start_cpu0 (void)
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LOG_STARTUP("PRO cpu is up (single core mode, only PRO cpu is used)\n");
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/* disable APP cpu */
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DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
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if (IS_ACTIVE(MODULE_ESP_IDF_HEAP)) {
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#if IS_USED(MODULE_ESP_IDF_HEAP)
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/* init heap */
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heap_caps_init();
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if (IS_ACTIVE(ENABLE_DEBUG)) {
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ets_printf("Heap free: %u byte\n", get_free_heap_size());
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}
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}
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/* init SPI RAM if enabled */
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#if CONFIG_SPIRAM_SUPPORT && CONFIG_SPIRAM_BOOT_INIT
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if (esp_spiram_init() != ESP_OK) {
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LOG_STARTUP("Failed to initialize SPI RAM\n");
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exit(1);
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}
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#endif
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/* init esp_timer implementation */
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esp_timer_early_init();
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LOG_STARTUP("PRO cpu starts user code\n");
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system_init();
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UNREACHABLE();
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}
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static void IRAM system_clk_init (void)
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{
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/* first initialize RTC with default configuration */
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rtc_config_t rtc_cfg = RTC_CONFIG_DEFAULT();
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rtc_init_module(rtc_cfg);
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/* configure main crystal frequency if necessary */
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if (CONFIG_ESP32_XTAL_FREQ != RTC_XTAL_FREQ_AUTO &&
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CONFIG_ESP32_XTAL_FREQ != rtc_clk_xtal_freq_get()) {
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bootloader_clock_configure();
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}
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/* set FAST_CLK to internal low power clock of 8 MHz */
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rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M);
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#if IS_USED(MODULE_ESP_RTC_TIMER_32K)
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/* set SLOW_CLK to external 32.768 kHz crystal clock */
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rtc_clk_select_rtc_slow_clk(RTC_SLOW_FREQ_32K_XTAL);
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#else
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/* set SLOW_CLK to internal low power clock of 150 kHz */
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rtc_clk_32k_enable(false);
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rtc_clk_select_rtc_slow_clk(RTC_SLOW_FREQ_RTC);
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#endif
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LOG_STARTUP("Switching system clocks can lead to some unreadable characters\n");
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/* wait until UART is idle to avoid losing output */
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uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
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/* determine configured CPU clock frequency from sdk_conf.h */
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rtc_cpu_freq_t freq;
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switch (CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ) {
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case 40: freq = RTC_CPU_FREQ_XTAL; /* derived from external crystal */
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break; /* normally 40 MHz */
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case 80: freq = RTC_CPU_FREQ_80M; /* derived from PLL */
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break;
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case 160: freq = RTC_CPU_FREQ_160M; /* derived from PLL */
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break;
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case 240: freq = RTC_CPU_FREQ_240M; /* derived from PLL */
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break;
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default: freq = RTC_CPU_FREQ_2M; /* frequencies <= 8 MHz are
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set to 2 MHz and handled later */
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}
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uint32_t freq_before = esp_clk_cpu_freq() / MHZ;
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if (freq_before != CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ) {
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rtc_cpu_freq_config_t clk_cfg;
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rtc_clk_cpu_freq_to_config(freq, &clk_cfg);
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/* set configured CPU frequency */
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rtc_clk_cpu_freq_set_config(&clk_cfg);
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/* Recalculate the ccount to make time calculation correct. */
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uint32_t freq_after = CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ;
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XTHAL_SET_CCOUNT( XTHAL_GET_CCOUNT() * freq_after / freq_before );
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}
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}
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extern void IRAM_ATTR thread_yield_isr(void* arg);
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static NORETURN void IRAM system_init (void)
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{
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static_assert(MAXTHREADS >= 3,
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"ESP32 requires at least 3 threads, esp_timer, idle, and main");
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#if defined(MCU_ESP32)
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/* enable cached read from flash */
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Cache_Read_Enable(PRO_CPU_NUM);
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#endif
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/* initialize the ISR stack for usage measurements */
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thread_isr_stack_init();
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/* initialize clocks (CPU_CLK, APB_CLK, SLOW and FAST) */
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system_clk_init();
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/* disable clocks of peripherals that are not needed at startup */
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esp_perip_clk_init();
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g_startup_time = esp_rtc_get_time_us();
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/* set configured console UART baudrate */
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const int uart_clk_freq = rtc_clk_apb_freq_get();
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uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
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uart_div_modify(CONFIG_CONSOLE_UART_NUM,
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(uart_clk_freq << 4) / STDIO_UART_BAUDRATE);
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/* initialize system call tables of ESP32 rom and newlib */
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/* initialize system call tables of ESP32x rom and newlib */
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syscalls_init();
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/* install exception handlers */
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init_exceptions();
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/* clear interrupt matrix */
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intr_matrix_clear();
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/* systemwide UART initialization */
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extern void uart_system_init (void);
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uart_system_init();
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/* Disable the hold flag of all RTC GPIO pins */
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RTCCNTL.hold_force.val = 0;
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/* set log levels for SDK library outputs */
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extern void esp_log_level_set(const char* tag, esp_log_level_t level);
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esp_log_level_set("wifi", LOG_DEBUG);
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esp_log_level_set("gpio", LOG_DEBUG);
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/* init watchdogs */
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system_wdt_init();
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@ -361,10 +264,9 @@ static NORETURN void IRAM system_init (void)
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rtc_clk_slow_freq_get_hz());
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LOG_STARTUP("XTAL calibration value: %d\n", esp_clk_slowclk_cal_get());
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LOG_STARTUP("Heap free: %u bytes\n", get_free_heap_size());
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uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
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/* initialize stdio */
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stdio_init();
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/* initialize architecture specific interrupt handling */
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esp_irq_init();
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/* disable buffering in stdio */
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setvbuf(_stdout_r(_REENT), NULL, _IONBF, 0);
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@ -400,8 +302,8 @@ static NORETURN void IRAM system_init (void)
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/* route a software interrupt source to CPU as trigger for thread yields */
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intr_matrix_set(PRO_CPU_NUM, ETS_FROM_CPU_INTR0_SOURCE, CPU_INUM_SOFTWARE);
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/* set thread yield handler and enable the software interrupt */
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xt_set_interrupt_handler(CPU_INUM_SOFTWARE, thread_yield_isr, NULL);
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xt_ints_on(BIT(CPU_INUM_SOFTWARE));
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intr_cntrl_ll_set_int_handler(CPU_INUM_SOFTWARE, thread_yield_isr, NULL);
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intr_cntrl_ll_enable_interrupts(BIT(CPU_INUM_SOFTWARE));
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/* initialize ESP system event loop */
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extern void esp_event_handler_init(void);
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@ -413,19 +315,10 @@ static NORETURN void IRAM system_init (void)
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/* starting RIOT */
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#if IS_USED(MODULE_ESP_LOG_STARTUP)
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LOG_STARTUP("Starting RIOT kernel on PRO cpu\n");
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uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
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esp_rom_uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
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#else
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puts("");
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#endif
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kernel_init();
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UNREACHABLE();
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}
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static void intr_matrix_clear(void)
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{
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/* attach all peripheral interrupt sources (Technical Reference, Table 7) */
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/* to an arbitrary CPU interrupt number (Technical Reference, Table 8) */
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for (int i = ETS_WIFI_MAC_INTR_SOURCE; i <= ETS_CACHE_IA_INTR_SOURCE; i++) {
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intr_matrix_set(PRO_CPU_NUM, i, ETS_INVALID_INUM);
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}
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}
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