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core/c11_atomic.c: Add remaining C11 atomic library helpers for GCC
This commit is contained in:
Joakim Nohlgård
parent
7376419350
commit
6d20ac084b
@ -28,11 +28,17 @@
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* @note This implementation completely ignores the memory model parameter
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*
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* @see https://gcc.gnu.org/wiki/Atomic/GCCMM/LIbrary
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* @see https://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html
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*
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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*/
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#include <stddef.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <stdatomic.h>
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#include <string.h>
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#include "irq.h"
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/* GCC documentation refers to the types as I1, I2, I4, I8, I16 */
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@ -42,16 +48,86 @@ typedef uint32_t I4;
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typedef uint64_t I8;
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/* typedef __uint128_t I16; */ /* No 128 bit integer support yet */
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/**
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* @brief This is a macro that defines a function named __atomic_load_<em>n</em>
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*
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* @param[in] n width of the data, in bytes
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*/
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#define TEMPLATE_ATOMIC_LOAD_N(n) \
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I##n __atomic_load_##n (I##n *ptr, int memorder) \
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{ \
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(void) memorder; \
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unsigned int mask = irq_disable(); \
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I##n old = *ptr; \
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irq_restore(mask); \
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return old; \
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}
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/**
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* @brief This is a macro that defines a function named __atomic_store_<em>n</em>
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*
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* @param[in] n width of the data, in bytes
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*/
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#define TEMPLATE_ATOMIC_STORE_N(n) \
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void __atomic_store_##n (I##n *ptr, I##n val, int memorder) \
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{ \
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(void) memorder; \
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unsigned int mask = irq_disable(); \
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*ptr = val; \
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irq_restore(mask); \
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}
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/**
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* @brief This is a macro that defines a function named __atomic_exchange_<em>n</em>
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*
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* @param[in] n width of the data, in bytes
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*/
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#define TEMPLATE_ATOMIC_EXCHANGE_N(n) \
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I##n __atomic_exchange_##n (I##n *ptr, I##n desired, int memorder) \
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{ \
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(void) memorder; \
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unsigned int mask = irq_disable(); \
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I##n old = *ptr; \
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*ptr = desired; \
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irq_restore(mask); \
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return old; \
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}
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/**
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* @brief This is a macro that defines a function named __atomic_compare_exchange_<em>n</em>
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*
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* @param[in] n width of the data, in bytes
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*/
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#define TEMPLATE_ATOMIC_COMPARE_EXCHANGE_N(n) \
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bool __atomic_compare_exchange_##n (volatile void *ptr, void *expected, I##n desired, \
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bool weak, int success_memorder, int failure_memorder) \
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{ \
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(void) weak; \
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(void) success_memorder; \
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(void) failure_memorder; \
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unsigned int mask = irq_disable(); \
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I##n cur = *((I##n*)ptr); \
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if (cur != *((I##n*)expected)) { \
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*((I##n*)expected) = cur; \
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irq_restore(mask); \
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return false; \
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} \
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\
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*((volatile I##n*)ptr) = desired; \
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irq_restore(mask); \
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return true; \
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}
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/**
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* @brief This is a macro that defines a function named __atomic_fetch_<em>opname</em>_<em>n</em>
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*
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* \param opname operator name that will be used in the function name
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* \param op actual C language operator
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* \param n width of the data, in bytes
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* \param prefixop optional prefix unary operator (use ~ for inverting, NAND, NOR etc)
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* @param[in] opname operator name that will be used in the function name
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* @param[in] op actual C language operator
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* @param[in] n width of the data, in bytes
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* @param[in] prefixop optional prefix unary operator (use ~ for inverting, NAND, NOR etc)
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*/
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#define TEMPLATE_ATOMIC_FETCH_OP_N(opname, op, n, prefixop) \
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I##n __atomic_fetch_##opname##_##n (volatile void *ptr, I##n val, int memmodel) \
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I##n __atomic_fetch_##opname##_##n(volatile void *ptr, I##n val, int memmodel) \
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{ \
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unsigned int mask = irq_disable(); \
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(void)memmodel; \
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@ -61,7 +137,46 @@ typedef uint64_t I8;
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return tmp; \
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}
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/**
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* @brief This is a macro that defines a function named __atomic_<em>opname</em>_fetch_<em>n</em>
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*
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* @param[in] opname operator name that will be used in the function name
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* @param[in] op actual C language operator
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* @param[in] n width of the data, in bytes
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* @param[in] prefixop optional prefix unary operator (use ~ for inverting, NAND, NOR etc)
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*/
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#define TEMPLATE_ATOMIC_OP_FETCH_N(opname, op, n, prefixop) \
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I##n __atomic_##opname##_fetch_##n(volatile void *ptr, I##n val, int memmodel) \
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{ \
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(void)memmodel; \
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unsigned int mask = irq_disable(); \
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*((I##n*)ptr) = prefixop(*((I##n*)ptr) op val); \
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I##n tmp = *((I##n*)ptr); \
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irq_restore(mask); \
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return tmp; \
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}
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/* Template instantiations below */
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TEMPLATE_ATOMIC_LOAD_N(1) /* __atomic_load_1 */
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TEMPLATE_ATOMIC_LOAD_N(2) /* __atomic_load_2 */
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TEMPLATE_ATOMIC_LOAD_N(4) /* __atomic_load_4 */
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TEMPLATE_ATOMIC_LOAD_N(8) /* __atomic_load_8 */
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TEMPLATE_ATOMIC_STORE_N(1) /* __atomic_store_1 */
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TEMPLATE_ATOMIC_STORE_N(2) /* __atomic_store_2 */
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TEMPLATE_ATOMIC_STORE_N(4) /* __atomic_store_4 */
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TEMPLATE_ATOMIC_STORE_N(8) /* __atomic_store_8 */
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TEMPLATE_ATOMIC_EXCHANGE_N(1) /* __atomic_exchange_1 */
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TEMPLATE_ATOMIC_EXCHANGE_N(2) /* __atomic_exchange_2 */
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TEMPLATE_ATOMIC_EXCHANGE_N(4) /* __atomic_exchange_4 */
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TEMPLATE_ATOMIC_EXCHANGE_N(8) /* __atomic_exchange_8 */
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TEMPLATE_ATOMIC_COMPARE_EXCHANGE_N(1) /* __atomic_compare_exchange_1 */
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TEMPLATE_ATOMIC_COMPARE_EXCHANGE_N(2) /* __atomic_compare_exchange_2 */
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TEMPLATE_ATOMIC_COMPARE_EXCHANGE_N(4) /* __atomic_compare_exchange_4 */
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TEMPLATE_ATOMIC_COMPARE_EXCHANGE_N(8) /* __atomic_compare_exchange_8 */
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TEMPLATE_ATOMIC_FETCH_OP_N( add, +, 1, ) /* __atomic_fetch_add_1 */
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TEMPLATE_ATOMIC_FETCH_OP_N( add, +, 2, ) /* __atomic_fetch_add_2 */
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TEMPLATE_ATOMIC_FETCH_OP_N( add, +, 4, ) /* __atomic_fetch_add_4 */
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@ -92,4 +207,157 @@ TEMPLATE_ATOMIC_FETCH_OP_N(nand, &, 2, ~) /* __atomic_fetch_nand_2 */
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TEMPLATE_ATOMIC_FETCH_OP_N(nand, &, 4, ~) /* __atomic_fetch_nand_4 */
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TEMPLATE_ATOMIC_FETCH_OP_N(nand, &, 8, ~) /* __atomic_fetch_nand_8 */
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TEMPLATE_ATOMIC_OP_FETCH_N( add, +, 1, ) /* __atomic_add_fetch_1 */
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TEMPLATE_ATOMIC_OP_FETCH_N( add, +, 2, ) /* __atomic_add_fetch_2 */
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TEMPLATE_ATOMIC_OP_FETCH_N( add, +, 4, ) /* __atomic_add_fetch_4 */
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TEMPLATE_ATOMIC_OP_FETCH_N( add, +, 8, ) /* __atomic_add_fetch_8 */
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TEMPLATE_ATOMIC_OP_FETCH_N( sub, -, 1, ) /* __atomic_sub_fetch_1 */
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TEMPLATE_ATOMIC_OP_FETCH_N( sub, -, 2, ) /* __atomic_sub_fetch_2 */
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TEMPLATE_ATOMIC_OP_FETCH_N( sub, -, 4, ) /* __atomic_sub_fetch_4 */
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TEMPLATE_ATOMIC_OP_FETCH_N( sub, -, 8, ) /* __atomic_sub_fetch_8 */
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TEMPLATE_ATOMIC_OP_FETCH_N( and, &, 1, ) /* __atomic_and_fetch_1 */
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TEMPLATE_ATOMIC_OP_FETCH_N( and, &, 2, ) /* __atomic_and_fetch_2 */
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TEMPLATE_ATOMIC_OP_FETCH_N( and, &, 4, ) /* __atomic_and_fetch_4 */
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TEMPLATE_ATOMIC_OP_FETCH_N( and, &, 8, ) /* __atomic_and_fetch_8 */
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TEMPLATE_ATOMIC_OP_FETCH_N( or, |, 1, ) /* __atomic_or_fetch_1 */
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TEMPLATE_ATOMIC_OP_FETCH_N( or, |, 2, ) /* __atomic_or_fetch_2 */
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TEMPLATE_ATOMIC_OP_FETCH_N( or, |, 4, ) /* __atomic_or_fetch_4 */
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TEMPLATE_ATOMIC_OP_FETCH_N( or, |, 8, ) /* __atomic_or_fetch_8 */
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TEMPLATE_ATOMIC_OP_FETCH_N( xor, ^, 1, ) /* __atomic_xor_fetch_1 */
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TEMPLATE_ATOMIC_OP_FETCH_N( xor, ^, 2, ) /* __atomic_xor_fetch_2 */
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TEMPLATE_ATOMIC_OP_FETCH_N( xor, ^, 4, ) /* __atomic_xor_fetch_4 */
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TEMPLATE_ATOMIC_OP_FETCH_N( xor, ^, 8, ) /* __atomic_xor_fetch_8 */
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TEMPLATE_ATOMIC_OP_FETCH_N(nand, &, 1, ~) /* __atomic_nand_fetch_1 */
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TEMPLATE_ATOMIC_OP_FETCH_N(nand, &, 2, ~) /* __atomic_nand_fetch_2 */
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TEMPLATE_ATOMIC_OP_FETCH_N(nand, &, 4, ~) /* __atomic_nand_fetch_4 */
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TEMPLATE_ATOMIC_OP_FETCH_N(nand, &, 8, ~) /* __atomic_nand_fetch_8 */
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/* ***** Generic versions below ***** */
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/* Clang objects if you redefine a builtin. This little hack allows us to
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* define a function with the same name as an intrinsic. */
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/* Hack origin: http://llvm.org/svn/llvm-project/compiler-rt/trunk/lib/builtins/atomic.c */
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#pragma redefine_extname __atomic_load_c __atomic_load
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#pragma redefine_extname __atomic_store_c __atomic_store
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#pragma redefine_extname __atomic_exchange_c __atomic_exchange
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#pragma redefine_extname __atomic_compare_exchange_c __atomic_compare_exchange
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/**
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* @brief Atomic generic load
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*
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* @param[in] size width of the data, in bytes
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* @param[in] src source address to load from
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* @param[in] dest destination address
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* @param[in] memorder memory ordering, ignored in this implementation
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*/
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void __atomic_load_c(size_t size, const void *src, void *dest, int memorder)
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{
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(void) memorder;
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unsigned int mask = irq_disable();
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memcpy(dest, src, size);
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irq_restore(mask);
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}
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/**
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* @brief Atomic generic store
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*
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* @param[in] size width of the data, in bytes
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* @param[in] dest destination address to store to
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* @param[in] src source address
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* @param[in] memorder memory ordering, ignored in this implementation
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*/
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void __atomic_store_c(size_t size, void *dest, const void *src, int memorder)
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{
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(void) memorder;
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unsigned int mask = irq_disable();
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memcpy(dest, src, size);
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irq_restore(mask);
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}
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/**
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* @brief Atomic generic exchange
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*
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* @param[in] size width of the data, in bytes
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* @param[in] ptr object to swap
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* @param[in] val value to swap to
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* @param[in] ret put the old value from @p ptr in @p ret
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* @param[in] memorder memory ordering, ignored in this implementation
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*/
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void __atomic_exchange_c(size_t size, void *ptr, void *val, void *ret, int memorder)
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{
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(void) memorder;
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unsigned int mask = irq_disable();
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memcpy(ret, ptr, size);
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memcpy(ptr, val, size);
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irq_restore(mask);
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}
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/**
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* @brief Atomic compare-and-swap operation
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*
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* This built-in function implements an atomic compare and exchange operation.
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* This compares the contents of *ptr with the contents of *expected. If equal,
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* the operation is a read-modify-write operation that writes desired into *ptr.
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* If they are not equal, the operation is a read and the current contents of *ptr
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* are written into *expected. weak is true for weak compare_exchange, which may
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* fail spuriously, and false for the strong variation, which never fails
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* spuriously. Many targets only offer the strong variation and ignore the
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* parameter. When in doubt, use the strong variation.
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*
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* If desired is written into *ptr then true is returned and memory is affected
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* according to the memory order specified by success_memorder. There are no
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* restrictions on what memory order can be used here.
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*
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* Otherwise, false is returned and memory is affected according to
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* failure_memorder. This memory order cannot be __ATOMIC_RELEASE nor
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* __ATOMIC_ACQ_REL. It also cannot be a stronger order than that specified by
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* success_memorder.
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*
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* @param[in] len
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* @param[in] ptr
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* @param[in] expected the expected value of ptr
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* @param[in] desired the desired value of ptr
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* @param[in] weak ignored in this implementation
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* @param[in] success_memorder ignored in this implementation
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* @param[in] failure_memorder ignored in this implementation
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*
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* @return true if *ptr had the expected value before the exchange and *ptr was updated
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* @return false otherwise
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*/
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bool __atomic_compare_exchange_c(size_t len, void *ptr, void *expected,
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void *desired, bool weak, int success_memorder, int failure_memorder)
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{
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(void)weak;
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(void)success_memorder;
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(void)failure_memorder;
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unsigned int mask = irq_disable();
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bool ret;
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if (memcmp(ptr, expected, len) == 0) {
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memcpy(ptr, desired, len);
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ret = true;
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}
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else {
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memcpy(expected, ptr, len);
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ret = false;
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}
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irq_restore(mask);
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return ret;
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}
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/* Memory barrier helper function, for platforms without barrier instructions */
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void __sync_synchronize(void) __attribute__((__weak__));
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void __sync_synchronize(void) {
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/* ARMv4, ARMv5 do not have any hardware support for memory barriers,
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* This is a software only barrier and a no-op, and will likely break on SMP
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* systems, but we don't support any multi-CPU ARMv5 or ARMv4 boards in RIOT
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* so I don't care. /JN
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*/
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__asm__ volatile ("" : : : "memory");
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}
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/** @} */
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