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cpu:_stm32_common: #ifdef -> if
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@ -47,6 +47,13 @@
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#define BIT_LSERDY RCC_BDCR_LSERDY
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#endif
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#ifndef CLOCK_HSE
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#define CLOCK_HSE (0U)
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#endif
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#ifndef CLOCK_LSE
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#define CLOCK_LSE (0U)
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#endif
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void stmclk_enable_hsi(void)
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{
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RCC->CR |= RCC_CR_HSION;
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@ -57,36 +64,38 @@ void stmclk_disable_hsi(void)
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{
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/* we only disable the HSI clock if not used as input for the PLL and if
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* not used directly as system clock */
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#if CLOCK_HSE
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if ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {
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RCC->CR &= ~(RCC_CR_HSION);
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if (CLOCK_HSE) {
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if ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {
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RCC->CR &= ~(RCC_CR_HSION);
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}
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}
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#endif
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}
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void stmclk_enable_lfclk(void)
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{
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#if CLOCK_LSE
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stmclk_dbp_unlock();
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RCC->REG_LSE |= BIT_LSEON;
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while (!(RCC->REG_LSE & BIT_LSERDY)) {}
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stmclk_dbp_lock();
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#else
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RCC->CSR |= RCC_CSR_LSION;
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while (!(RCC->CSR & RCC_CSR_LSIRDY)) {}
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#endif
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if (CLOCK_LSE) {
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stmclk_dbp_unlock();
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RCC->REG_LSE |= BIT_LSEON;
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while (!(RCC->REG_LSE & BIT_LSERDY)) {}
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stmclk_dbp_lock();
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}
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else {
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RCC->CSR |= RCC_CSR_LSION;
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while (!(RCC->CSR & RCC_CSR_LSIRDY)) {}
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}
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}
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void stmclk_disable_lfclk(void)
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{
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#if CLOCK_LSE
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stmclk_dbp_unlock();
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RCC->REG_LSE &= ~(BIT_LSEON);
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while (!(RCC->REG_LSE & BIT_LSERDY)) {}
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stmclk_dbp_lock();
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#else
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RCC->CSR &= ~(RCC_CSR_LSION);
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#endif
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if (CLOCK_LSE) {
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stmclk_dbp_unlock();
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RCC->REG_LSE &= ~(BIT_LSEON);
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while (!(RCC->REG_LSE & BIT_LSERDY)) {}
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stmclk_dbp_lock();
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}
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else {
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RCC->CSR &= ~(RCC_CSR_LSION);
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}
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}
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void stmclk_dbp_unlock(void)
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