From 6cd6d5948ffa8cfb60aad1a3230155058fd47c9a Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Thu, 23 Jul 2020 16:50:05 +0200 Subject: [PATCH] cpu/stm32/vectors: remove hand crafted vectors_.c files --- cpu/stm32/vectors/vectors_f0.c | 254 -------------- cpu/stm32/vectors/vectors_f1.c | 152 --------- cpu/stm32/vectors/vectors_f2.c | 203 ----------- cpu/stm32/vectors/vectors_f3.c | 376 -------------------- cpu/stm32/vectors/vectors_f4.c | 608 --------------------------------- cpu/stm32/vectors/vectors_f7.c | 278 --------------- cpu/stm32/vectors/vectors_g0.c | 86 ----- cpu/stm32/vectors/vectors_g4.c | 257 -------------- cpu/stm32/vectors/vectors_l0.c | 136 -------- cpu/stm32/vectors/vectors_l1.c | 158 --------- cpu/stm32/vectors/vectors_l4.c | 292 ---------------- cpu/stm32/vectors/vectors_wb.c | 154 --------- 12 files changed, 2954 deletions(-) delete mode 100644 cpu/stm32/vectors/vectors_f0.c delete mode 100644 cpu/stm32/vectors/vectors_f1.c delete mode 100644 cpu/stm32/vectors/vectors_f2.c delete mode 100644 cpu/stm32/vectors/vectors_f3.c delete mode 100644 cpu/stm32/vectors/vectors_f4.c delete mode 100644 cpu/stm32/vectors/vectors_f7.c delete mode 100644 cpu/stm32/vectors/vectors_g0.c delete mode 100644 cpu/stm32/vectors/vectors_g4.c delete mode 100644 cpu/stm32/vectors/vectors_l0.c delete mode 100644 cpu/stm32/vectors/vectors_l1.c delete mode 100644 cpu/stm32/vectors/vectors_l4.c delete mode 100644 cpu/stm32/vectors/vectors_wb.c diff --git a/cpu/stm32/vectors/vectors_f0.c b/cpu/stm32/vectors/vectors_f0.c deleted file mode 100644 index d739c4cfc0..0000000000 --- a/cpu/stm32/vectors/vectors_f0.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - * Copyright (C) 2014-2017 Freie Universität Berlin - * - * This file is subject to the terms and conditions of the GNU Lesser General - * Public License v2.1. See the file LICENSE in the top level directory for more - * details. - */ - -/** - * @ingroup cpu_stm32 - * @{ - * - * @file - * @brief Interrupt vector definitions for STM32F0 - * - * @author Hauke Petersen - * - * @} - */ - -#include "vectors_cortexm.h" - -/* define a local dummy handler as it needs to be in the same compilation unit - * as the alias definition */ -void dummy_handler(void) { - dummy_handler_default(); -} - -/* STM32F0 specific interrupt vectors */ -WEAK_DEFAULT void isr_adc1(void); -WEAK_DEFAULT void isr_adc1_comp(void); -WEAK_DEFAULT void isr_cec_can(void); -WEAK_DEFAULT void isr_dma1_ch1(void); -WEAK_DEFAULT void isr_dma1_ch2_3_dma2_ch1_2(void); -WEAK_DEFAULT void isr_dma1_ch4_7_dma2_ch3_5(void); -WEAK_DEFAULT void isr_dma1_channel1(void); -WEAK_DEFAULT void isr_dma1_channel2_3(void); -WEAK_DEFAULT void isr_dma1_channel4_5(void); -WEAK_DEFAULT void isr_dma1_channel4_5_6_7(void); -WEAK_DEFAULT void isr_exti(void); -WEAK_DEFAULT void isr_flash(void); -WEAK_DEFAULT void isr_i2c1(void); -WEAK_DEFAULT void isr_i2c2(void); -WEAK_DEFAULT void isr_pvd(void); -WEAK_DEFAULT void isr_pvd_vddio2(void); -WEAK_DEFAULT void isr_rcc(void); -WEAK_DEFAULT void isr_rcc_crs(void); -WEAK_DEFAULT void isr_rtc(void); -WEAK_DEFAULT void isr_spi1(void); -WEAK_DEFAULT void isr_spi2(void); -WEAK_DEFAULT void isr_tim14(void); -WEAK_DEFAULT void isr_tim15(void); -WEAK_DEFAULT void isr_tim16(void); -WEAK_DEFAULT void isr_tim17(void); -WEAK_DEFAULT void isr_tim1_brk_up_trg_com(void); -WEAK_DEFAULT void isr_tim1_cc(void); -WEAK_DEFAULT void isr_tim2(void); -WEAK_DEFAULT void isr_tim3(void); -WEAK_DEFAULT void isr_tim6(void); -WEAK_DEFAULT void isr_tim6_dac(void); -WEAK_DEFAULT void isr_tim7(void); -WEAK_DEFAULT void isr_tsc(void); -WEAK_DEFAULT void isr_usart1(void); -WEAK_DEFAULT void isr_usart2(void); -WEAK_DEFAULT void isr_usart3_4(void); -WEAK_DEFAULT void isr_usart3_6(void); -WEAK_DEFAULT void isr_usart3_8(void); -WEAK_DEFAULT void isr_usb(void); -WEAK_DEFAULT void isr_wwdg(void); - -/* CPU specific interrupt vector table */ -ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = { - /* shared vectors for all family members */ - [ 0] = isr_wwdg, /* [ 0] Window WatchDog Interrupt */ - [ 2] = isr_rtc, /* [ 2] RTC Interrupt through EXTI Lines 17, 19 and 20 */ - [ 3] = isr_flash, /* [ 3] FLASH global Interrupt */ - [14] = isr_tim1_cc, /* [14] TIM1 Capture Compare Interrupt */ - [16] = isr_tim3, /* [16] TIM3 global Interrupt */ - [19] = isr_tim14, /* [19] TIM14 global Interrupt */ - [21] = isr_tim16, /* [21] TIM16 global Interrupt */ - [22] = isr_tim17, /* [22] TIM17 global Interrupt */ - [25] = isr_spi1, /* [25] SPI1 global Interrupt */ - -#if defined(CPU_LINE_STM32F030x4) - [ 4] = isr_rcc, /* [ 4] RCC global Interrupt */ - [ 5] = isr_exti, /* [ 5] EXTI Line 0 and 1 Interrupt */ - [ 6] = isr_exti, /* [ 6] EXTI Line 2 and 3 Interrupt */ - [ 7] = isr_exti, /* [ 7] EXTI Line 4 to 15 Interrupt */ - [ 9] = isr_dma1_channel1, /* [ 9] DMA1 Channel 1 Interrupt */ - [10] = isr_dma1_channel2_3, /* [10] DMA1 Channel 2 and Channel 3 Interrupt */ - [11] = isr_dma1_channel4_5, /* [11] DMA1 Channel 4 and Channel 5 Interrupt */ - [12] = isr_adc1, /* [12] ADC1 Interrupt */ - [13] = isr_tim1_brk_up_trg_com, /* [13] TIM1 Break, Update, Trigger and Commutation Interrupt */ - [23] = isr_i2c1, /* [23] I2C1 Event Interrupt */ - [27] = isr_usart1, /* [27] USART1 global Interrupt */ -#elif defined(CPU_LINE_STM32F030x8) - [ 4] = isr_rcc, /* [ 4] RCC global Interrupt */ - [ 5] = isr_exti, /* [ 5] EXTI Line 0 and 1 Interrupt */ - [ 6] = isr_exti, /* [ 6] EXTI Line 2 and 3 Interrupt */ - [ 7] = isr_exti, /* [ 7] EXTI Line 4 to 15 Interrupt */ - [ 9] = isr_dma1_channel1, /* [ 9] DMA1 Channel 1 Interrupt */ - [10] = isr_dma1_channel2_3, /* [10] DMA1 Channel 2 and Channel 3 Interrupt */ - [11] = isr_dma1_channel4_5, /* [11] DMA1 Channel 4 and Channel 5 Interrupt */ - [12] = isr_adc1, /* [12] ADC1 Interrupt */ - [13] = isr_tim1_brk_up_trg_com, /* [13] TIM1 Break, Update, Trigger and Commutation Interrupt */ - [17] = isr_tim6, /* [17] TIM6 global Interrupt */ - [20] = isr_tim15, /* [20] TIM15 global Interrupt */ - [23] = isr_i2c1, /* [23] I2C1 Event Interrupt */ - [24] = isr_i2c2, /* [24] I2C2 Event Interrupt */ - [26] = isr_spi2, /* [26] SPI2 global Interrupt */ - [27] = isr_usart1, /* [27] USART1 global Interrupt */ - [28] = isr_usart2, /* [28] USART2 global Interrupt */ -#elif defined(CPU_LINE_STM32F031x6) - [ 1] = isr_pvd, /* [ 1] PVD Interrupt through EXTI Lines 16 */ - [ 4] = isr_rcc, /* [ 4] RCC global Interrupt */ - [ 5] = isr_exti, /* [ 5] EXTI Line 0 and 1 Interrupt */ - [ 6] = isr_exti, /* [ 6] EXTI Line 2 and 3 Interrupt */ - [ 7] = isr_exti, /* [ 7] EXTI Line 4 to 15 Interrupt */ - [ 9] = isr_dma1_channel1, /* [ 9] DMA1 Channel 1 Interrupt */ - [10] = isr_dma1_channel2_3, /* [10] DMA1 Channel 2 and Channel 3 Interrupt */ - [11] = isr_dma1_channel4_5, /* [11] DMA1 Channel 4 and Channel 5 Interrupt */ - [12] = isr_adc1, /* [12] ADC1 Interrupt */ - [13] = isr_tim1_brk_up_trg_com, /* [13] TIM1 Break, Update, Trigger and Commutation Interrupt */ - [15] = isr_tim2, /* [15] TIM2 global Interrupt */ - [23] = isr_i2c1, /* [23] I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ - [27] = isr_usart1, /* [27] USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ -#elif defined(CPU_LINE_STM32F042x6) - [ 1] = isr_pvd_vddio2, /* [ 1] PVD & VDDIO2 Interrupts through EXTI Lines 16 and 31 */ - [ 4] = isr_rcc_crs, /* [ 4] RCC & CRS Global Interrupts */ - [ 5] = isr_exti, /* [ 5] EXTI Line 0 and 1 Interrupts */ - [ 6] = isr_exti, /* [ 6] EXTI Line 2 and 3 Interrupts */ - [ 7] = isr_exti, /* [ 7] EXTI Line 4 to 15 Interrupts */ - [ 8] = isr_tsc, /* [ 8] Touch Sensing Controller Interrupts */ - [ 9] = isr_dma1_channel1, /* [ 9] DMA1 Channel 1 Interrupt */ - [10] = isr_dma1_channel2_3, /* [10] DMA1 Channel 2 and Channel 3 Interrupts */ - [11] = isr_dma1_channel4_5, /* [11] DMA1 Channel 4 and Channel 5 Interrupts */ - [12] = isr_adc1, /* [12] ADC1 Interrupt */ - [13] = isr_tim1_brk_up_trg_com, /* [13] TIM1 Break, Update, Trigger and Commutation Interrupts */ - [15] = isr_tim2, /* [15] TIM2 global Interrupt */ - [23] = isr_i2c1, /* [23] I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ - [26] = isr_spi2, /* [26] SPI2 global Interrupt */ - [27] = isr_usart1, /* [27] USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ - [28] = isr_usart2, /* [28] USART2 global Interrupt */ - [30] = isr_cec_can, /* [30] CEC and CAN global Interrupts & EXTI Line27 Interrupt */ - [31] = isr_usb, /* [31] USB global Interrupts & EXTI Line18 Interrupt */ -#elif defined(CPU_LINE_STM32F051x8) - [ 1] = isr_pvd, /* [ 1] PVD Interrupt through EXTI Lines 16 */ - [ 4] = isr_rcc, /* [ 4] RCC global Interrupt */ - [ 5] = isr_exti, /* [ 5] EXTI Line 0 and 1 Interrupts */ - [ 6] = isr_exti, /* [ 6] EXTI Line 2 and 3 Interrupts */ - [ 7] = isr_exti, /* [ 7] EXTI Line 4 to 15 Interrupts */ - [ 8] = isr_tsc, /* [ 8] Touch Sensing Controller Interrupts */ - [ 9] = isr_dma1_channel1, /* [ 9] DMA1 Channel 1 Interrupt */ - [10] = isr_dma1_channel2_3, /* [10] DMA1 Channel 2 and Channel 3 Interrupts */ - [11] = isr_dma1_channel4_5, /* [11] DMA1 Channel 4 and Channel 5 Interrupts */ - [12] = isr_adc1_comp, /* [12] ADC1 and COMP interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */ - [13] = isr_tim1_brk_up_trg_com, /* [13] TIM1 Break, Update, Trigger and Commutation Interrupts */ - [15] = isr_tim2, /* [15] TIM2 global Interrupt */ - [17] = isr_tim6_dac, /* [17] TIM6 global and DAC channel underrun error Interrupts */ - [20] = isr_tim15, /* [20] TIM15 global Interrupt */ - [23] = isr_i2c1, /* [23] I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ - [24] = isr_i2c2, /* [24] I2C2 Event Interrupt */ - [26] = isr_spi2, /* [26] SPI2 global Interrupt */ - [27] = isr_usart1, /* [27] USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ - [28] = isr_usart2, /* [28] USART2 global Interrupt */ - [30] = isr_cec_can, /* [30] CEC and CAN global Interrupts & EXTI Line27 Interrupt */ -#elif defined(CPU_LINE_STM32F070xB) - [ 4] = isr_rcc, /* [ 4] RCC global Interrupt */ - [ 5] = isr_exti, /* [ 5] EXTI Line 0 and 1 Interrupt */ - [ 6] = isr_exti, /* [ 6] EXTI Line 2 and 3 Interrupt */ - [ 7] = isr_exti, /* [ 7] EXTI Line 4 to 15 Interrupt */ - [ 9] = isr_dma1_channel1, /* [ 9] DMA1 Channel 1 Interrupt */ - [10] = isr_dma1_channel2_3, /* [10] DMA1 Channel 2 and Channel 3 Interrupt */ - [11] = isr_dma1_channel4_5, /* [11] DMA1 Channel 4 and Channel 5 Interrupt */ - [12] = isr_adc1, /* [12] ADC1 Interrupt */ - [13] = isr_tim1_brk_up_trg_com, /* [13] TIM1 Break, Update, Trigger and Commutation Interrupt */ - [17] = isr_tim6, /* [17] TIM6 global Interrupt */ - [18] = isr_tim7, /* [18] TIM7 global Interrupt */ - [20] = isr_tim15, /* [20] TIM15 global Interrupt */ - [23] = isr_i2c1, /* [23] I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ - [24] = isr_i2c2, /* [24] I2C2 Event Interrupt */ - [26] = isr_spi2, /* [26] SPI2 global Interrupt */ - [27] = isr_usart1, /* [27] USART1 global Interrupt */ - [28] = isr_usart2, /* [28] USART2 global Interrupt */ - [29] = isr_usart3_4, /* [29] USART3 and USART4 global Interrupt */ - [31] = isr_usb, /* [31] USB global Interrupt & EXTI Line18 Interrupt */ -#elif defined(CPU_LINE_STM32F072xB) - [ 1] = isr_pvd_vddio2, /* [ 1] PVD & VDDIO2 Interrupt through EXTI Lines 16 and 31 */ - [ 4] = isr_rcc_crs, /* [ 4] RCC & CRS global Interrupt */ - [ 5] = isr_exti, /* [ 5] EXTI Line 0 and 1 Interrupt */ - [ 6] = isr_exti, /* [ 6] EXTI Line 2 and 3 Interrupt */ - [ 7] = isr_exti, /* [ 7] EXTI Line 4 to 15 Interrupt */ - [ 8] = isr_tsc, /* [ 8] Touch Sensing Controller Interrupts */ - [ 9] = isr_dma1_channel1, /* [ 9] DMA1 Channel 1 Interrupt */ - [10] = isr_dma1_channel2_3, /* [10] DMA1 Channel 2 and Channel 3 Interrupt */ - [11] = isr_dma1_channel4_5_6_7, /* [11] DMA1 Channel 4 to Channel 7 Interrupt */ - [12] = isr_adc1_comp, /* [12] ADC1 and COMP interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */ - [13] = isr_tim1_brk_up_trg_com, /* [13] TIM1 Break, Update, Trigger and Commutation Interrupt */ - [15] = isr_tim2, /* [15] TIM2 global Interrupt */ - [17] = isr_tim6_dac, /* [17] TIM6 global and DAC channel underrun error Interrupt */ - [18] = isr_tim7, /* [18] TIM7 global Interrupt */ - [20] = isr_tim15, /* [20] TIM15 global Interrupt */ - [23] = isr_i2c1, /* [23] I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ - [24] = isr_i2c2, /* [24] I2C2 Event Interrupt */ - [26] = isr_spi2, /* [26] SPI2 global Interrupt */ - [27] = isr_usart1, /* [27] USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ - [28] = isr_usart2, /* [28] USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ - [29] = isr_usart3_4, /* [29] USART3 and USART4 global Interrupt */ - [30] = isr_cec_can, /* [30] CEC and CAN global Interrupts & EXTI Line27 Interrupt */ - [31] = isr_usb, /* [31] USB global Interrupt & EXTI Line18 Interrupt */ -#elif defined(CPU_LINE_STM32F091xC) - [ 1] = isr_pvd_vddio2, /* [ 1] PVD & VDDIO2 Interrupts through EXTI Lines 16 and 31 */ - [ 4] = isr_rcc_crs, /* [ 4] RCC & CRS global Interrupts */ - [ 5] = isr_exti, /* [ 5] EXTI Line 0 and 1 Interrupts */ - [ 6] = isr_exti, /* [ 6] EXTI Line 2 and 3 Interrupts */ - [ 7] = isr_exti, /* [ 7] EXTI Line 4 to 15 Interrupts */ - [ 8] = isr_tsc, /* [ 8] Touch Sensing Controller Interrupts */ - [ 9] = isr_dma1_ch1, /* [ 9] DMA1 Channel 1 Interrupt */ - [10] = isr_dma1_ch2_3_dma2_ch1_2,/* [10] DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2 Interrupts */ - [11] = isr_dma1_ch4_7_dma2_ch3_5,/* [11] DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5 Interrupts */ - [12] = isr_adc1_comp, /* [12] ADC, COMP1 and COMP2 Interrupts (EXTI Lines 21 and 22) */ - [13] = isr_tim1_brk_up_trg_com, /* [13] TIM1 Break, Update, Trigger and Commutation Interrupts */ - [15] = isr_tim2, /* [15] TIM2 global Interrupt */ - [17] = isr_tim6_dac, /* [17] TIM6 global and DAC channel underrun error Interrupts */ - [18] = isr_tim7, /* [18] TIM7 global Interrupt */ - [20] = isr_tim15, /* [20] TIM15 global Interrupt */ - [23] = isr_i2c1, /* [23] I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ - [24] = isr_i2c2, /* [24] I2C2 Event Interrupt */ - [26] = isr_spi2, /* [26] SPI2 global Interrupt */ - [27] = isr_usart1, /* [27] USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ - [28] = isr_usart2, /* [28] USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ - [29] = isr_usart3_8, /* [29] USART3 to USART8 global Interrupts */ - [30] = isr_cec_can, /* [30] CEC and CAN global Interrupts & EXTI Line27 Interrupt */ -#elif defined(CPU_LINE_STM32F030xC) - [ 4] = isr_rcc, /* [ 4] RCC global Interrupt */ - [ 5] = isr_exti, /* [ 5] EXTI Line 0 and 1 Interrupt */ - [ 6] = isr_exti, /* [ 6] EXTI Line 2 and 3 Interrupt */ - [ 7] = isr_exti, /* [ 7] EXTI Line 4 to 15 Interrupt */ - [ 9] = isr_dma1_channel1, /* [ 9] DMA1 Channel 1 Interrupt */ - [10] = isr_dma1_channel2_3, /* [10] DMA1 Channel 2 and Channel 3 Interrupt */ - [11] = isr_dma1_channel4_5, /* [11] DMA1 Channel 4 and Channel 5 Interrupt */ - [12] = isr_adc1, /* [12] ADC1 Interrupt */ - [13] = isr_tim1_brk_up_trg_com, /* [13] TIM1 Break, Update, Trigger and Commutation Interrupt */ - [17] = isr_tim6, /* [17] TIM6 global Interrupt */ - [18] = isr_tim7, /* [18] TIM7 global Interrupt */ - [20] = isr_tim15, /* [20] TIM15 global Interrupt */ - [23] = isr_i2c1, /* [23] I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ - [24] = isr_i2c2, /* [24] I2C2 Event Interrupt */ - [26] = isr_spi2, /* [26] SPI2 global Interrupt */ - [27] = isr_usart1, /* [27] USART1 global Interrupt */ - [28] = isr_usart2, /* [28] USART2 global Interrupt */ - [29] = isr_usart3_6, /* [29] USART3..6 global Interrupt */ -#endif -}; diff --git a/cpu/stm32/vectors/vectors_f1.c b/cpu/stm32/vectors/vectors_f1.c deleted file mode 100644 index 0b0758160a..0000000000 --- a/cpu/stm32/vectors/vectors_f1.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (C) 2014-2017 Freie Universität Berlin - * - * This file is subject to the terms and conditions of the GNU Lesser General - * Public License v2.1. See the file LICENSE in the top level directory for more - * details. - */ - -/** - * @ingroup cpu_stm32 - * @{ - * - * @file - * @brief Interrupt vector definitions for STM32F1 - * - * @author Hauke Petersen - * @author Thomas Eichinger - * - * @} - */ - -#include "vectors_cortexm.h" - -/* define a local dummy handler as it needs to be in the same compilation unit - * as the alias definition */ -void dummy_handler(void) { - dummy_handler_default(); -} - -/* STM32F1 specific interrupt vectors */ -WEAK_DEFAULT void isr_adc1_2(void); -WEAK_DEFAULT void isr_adc3(void); -WEAK_DEFAULT void isr_can1_rx1(void); -WEAK_DEFAULT void isr_can1_sce(void); -WEAK_DEFAULT void isr_dma1_channel1(void); -WEAK_DEFAULT void isr_dma1_channel2(void); -WEAK_DEFAULT void isr_dma1_channel3(void); -WEAK_DEFAULT void isr_dma1_channel4(void); -WEAK_DEFAULT void isr_dma1_channel5(void); -WEAK_DEFAULT void isr_dma1_channel6(void); -WEAK_DEFAULT void isr_dma1_channel7(void); -WEAK_DEFAULT void isr_dma2_channel1(void); -WEAK_DEFAULT void isr_dma2_channel2(void); -WEAK_DEFAULT void isr_dma2_channel3(void); -WEAK_DEFAULT void isr_dma2_channel4_5(void); -WEAK_DEFAULT void isr_exti(void); -WEAK_DEFAULT void isr_flash(void); -WEAK_DEFAULT void isr_fsmc(void); -WEAK_DEFAULT void isr_i2c1_er(void); -WEAK_DEFAULT void isr_i2c1_ev(void); -WEAK_DEFAULT void isr_i2c2_er(void); -WEAK_DEFAULT void isr_i2c2_ev(void); -WEAK_DEFAULT void isr_pvd(void); -WEAK_DEFAULT void isr_rcc(void); -WEAK_DEFAULT void isr_rtc(void); -WEAK_DEFAULT void isr_rtc_alarm(void); -WEAK_DEFAULT void isr_sdio(void); -WEAK_DEFAULT void isr_spi1(void); -WEAK_DEFAULT void isr_spi2(void); -WEAK_DEFAULT void isr_spi3(void); -WEAK_DEFAULT void isr_tamper(void); -WEAK_DEFAULT void isr_tim1_brk(void); -WEAK_DEFAULT void isr_tim1_cc(void); -WEAK_DEFAULT void isr_tim1_trg_com(void); -WEAK_DEFAULT void isr_tim1_up(void); -WEAK_DEFAULT void isr_tim2(void); -WEAK_DEFAULT void isr_tim3(void); -WEAK_DEFAULT void isr_tim4(void); -WEAK_DEFAULT void isr_tim5(void); -WEAK_DEFAULT void isr_tim6(void); -WEAK_DEFAULT void isr_tim7(void); -WEAK_DEFAULT void isr_tim8_brk(void); -WEAK_DEFAULT void isr_tim8_cc(void); -WEAK_DEFAULT void isr_tim8_trg_com(void); -WEAK_DEFAULT void isr_tim8_up(void); -WEAK_DEFAULT void isr_uart4(void); -WEAK_DEFAULT void isr_uart5(void); -WEAK_DEFAULT void isr_usart1(void); -WEAK_DEFAULT void isr_usart2(void); -WEAK_DEFAULT void isr_usart3(void); -WEAK_DEFAULT void isr_usb_hp_can1_tx(void); -WEAK_DEFAULT void isr_usb_lp_can1_rx0(void); -WEAK_DEFAULT void isr_usbwakeup(void); -WEAK_DEFAULT void isr_wwdg(void); - -/* CPU specific interrupt vector table */ -ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = { - /* shared vectors for all family members */ - [ 0] = isr_wwdg, /* [ 0] Window WatchDog Interrupt */ - [ 1] = isr_pvd, /* [ 1] PVD through EXTI Line detection Interrupt */ - [ 2] = isr_tamper, /* [ 2] Tamper Interrupt */ - [ 3] = isr_rtc, /* [ 3] RTC global Interrupt */ - [ 4] = isr_flash, /* [ 4] FLASH global Interrupt */ - [ 5] = isr_rcc, /* [ 5] RCC global Interrupt */ - [ 6] = isr_exti, /* [ 6] EXTI Line0 Interrupt */ - [ 7] = isr_exti, /* [ 7] EXTI Line1 Interrupt */ - [ 8] = isr_exti, /* [ 8] EXTI Line2 Interrupt */ - [ 9] = isr_exti, /* [ 9] EXTI Line3 Interrupt */ - [10] = isr_exti, /* [10] EXTI Line4 Interrupt */ - [11] = isr_dma1_channel1, /* [11] DMA1 Channel 1 global Interrupt */ - [12] = isr_dma1_channel2, /* [12] DMA1 Channel 2 global Interrupt */ - [13] = isr_dma1_channel3, /* [13] DMA1 Channel 3 global Interrupt */ - [14] = isr_dma1_channel4, /* [14] DMA1 Channel 4 global Interrupt */ - [15] = isr_dma1_channel5, /* [15] DMA1 Channel 5 global Interrupt */ - [16] = isr_dma1_channel6, /* [16] DMA1 Channel 6 global Interrupt */ - [17] = isr_dma1_channel7, /* [17] DMA1 Channel 7 global Interrupt */ - [18] = isr_adc1_2, /* [18] ADC1 and ADC2 global Interrupt */ - [19] = isr_usb_hp_can1_tx, /* [19] USB Device High Priority or CAN1 TX Interrupts */ - [20] = isr_usb_lp_can1_rx0, /* [20] USB Device Low Priority or CAN1 RX0 Interrupts */ - [21] = isr_can1_rx1, /* [21] CAN1 RX1 Interrupt */ - [22] = isr_can1_sce, /* [22] CAN1 SCE Interrupt */ - [23] = isr_exti, /* [23] External Line[9:5] Interrupts */ - [24] = isr_tim1_brk, /* [24] TIM1 Break Interrupt */ - [25] = isr_tim1_up, /* [25] TIM1 Update Interrupt */ - [26] = isr_tim1_trg_com, /* [26] TIM1 Trigger and Commutation Interrupt */ - [27] = isr_tim1_cc, /* [27] TIM1 Capture Compare Interrupt */ - [28] = isr_tim2, /* [28] TIM2 global Interrupt */ - [29] = isr_tim3, /* [29] TIM3 global Interrupt */ - [30] = isr_tim4, /* [30] TIM4 global Interrupt */ - [31] = isr_i2c1_ev, /* [31] I2C1 Event Interrupt */ - [32] = isr_i2c1_er, /* [32] I2C1 Error Interrupt */ - [33] = isr_i2c2_ev, /* [33] I2C2 Event Interrupt */ - [34] = isr_i2c2_er, /* [34] I2C2 Error Interrupt */ - [35] = isr_spi1, /* [35] SPI1 global Interrupt */ - [36] = isr_spi2, /* [36] SPI2 global Interrupt */ - [37] = isr_usart1, /* [37] USART1 global Interrupt */ - [38] = isr_usart2, /* [38] USART2 global Interrupt */ - [39] = isr_usart3, /* [39] USART3 global Interrupt */ - [40] = isr_exti, /* [40] External Line[15:10] Interrupts */ - [41] = isr_rtc_alarm, /* [41] RTC Alarm through EXTI Line Interrupt */ - [42] = isr_usbwakeup, /* [42] USB Device WakeUp from suspend through EXTI Line Interrupt */ - -#if defined(CPU_LINE_STM32F103xE) - [43] = isr_tim8_brk, /* [43] TIM8 Break Interrupt */ - [44] = isr_tim8_up, /* [44] TIM8 Update Interrupt */ - [45] = isr_tim8_trg_com, /* [45] TIM8 Trigger and Commutation Interrupt */ - [46] = isr_tim8_cc, /* [46] TIM8 Capture Compare Interrupt */ - [47] = isr_adc3, /* [47] ADC3 global Interrupt */ - [48] = isr_fsmc, /* [48] FSMC global Interrupt */ - [49] = isr_sdio, /* [49] SDIO global Interrupt */ - [50] = isr_tim5, /* [50] TIM5 global Interrupt */ - [51] = isr_spi3, /* [51] SPI3 global Interrupt */ - [52] = isr_uart4, /* [52] UART4 global Interrupt */ - [53] = isr_uart5, /* [53] UART5 global Interrupt */ - [54] = isr_tim6, /* [54] TIM6 global Interrupt */ - [55] = isr_tim7, /* [55] TIM7 global Interrupt */ - [56] = isr_dma2_channel1, /* [56] DMA2 Channel 1 global Interrupt */ - [57] = isr_dma2_channel2, /* [57] DMA2 Channel 2 global Interrupt */ - [58] = isr_dma2_channel3, /* [58] DMA2 Channel 3 global Interrupt */ - [59] = isr_dma2_channel4_5, /* [59] DMA2 Channel 4 and Channel 5 global Interrupt */ -#endif -}; diff --git a/cpu/stm32/vectors/vectors_f2.c b/cpu/stm32/vectors/vectors_f2.c deleted file mode 100644 index 3781462d75..0000000000 --- a/cpu/stm32/vectors/vectors_f2.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - * Copyright (C) 2015 Engineering-Spirit - * 2017 Freie Universität Berlin - * - * This file is subject to the terms and conditions of the GNU Lesser General - * Public License v2.1. See the file LICENSE in the top level directory for more - * details. - */ - -/** - * @ingroup cpu_stm32 - * @{ - * - * @file - * @brief Interrupt vector definitions for STM32F2 - * - * @author Hauke Petersen - * @author Nick v. IJzendoorn - * - * @} - */ - -#include "vectors_cortexm.h" - -/* define a local dummy handler as it needs to be in the same compilation unit - * as the alias definition */ -void dummy_handler(void) { - dummy_handler_default(); -} - -/* STM32F2 specific interrupt vectors */ -WEAK_DEFAULT void isr_adc(void); -WEAK_DEFAULT void isr_can1_rx0(void); -WEAK_DEFAULT void isr_can1_rx1(void); -WEAK_DEFAULT void isr_can1_sce(void); -WEAK_DEFAULT void isr_can1_tx(void); -WEAK_DEFAULT void isr_can2_rx0(void); -WEAK_DEFAULT void isr_can2_rx1(void); -WEAK_DEFAULT void isr_can2_sce(void); -WEAK_DEFAULT void isr_can2_tx(void); -WEAK_DEFAULT void isr_cryp(void); -WEAK_DEFAULT void isr_dcmi(void); -WEAK_DEFAULT void isr_dma1_stream0(void); -WEAK_DEFAULT void isr_dma1_stream1(void); -WEAK_DEFAULT void isr_dma1_stream2(void); -WEAK_DEFAULT void isr_dma1_stream3(void); -WEAK_DEFAULT void isr_dma1_stream4(void); -WEAK_DEFAULT void isr_dma1_stream5(void); -WEAK_DEFAULT void isr_dma1_stream6(void); -WEAK_DEFAULT void isr_dma1_stream7(void); -WEAK_DEFAULT void isr_dma2_stream0(void); -WEAK_DEFAULT void isr_dma2_stream1(void); -WEAK_DEFAULT void isr_dma2_stream2(void); -WEAK_DEFAULT void isr_dma2_stream3(void); -WEAK_DEFAULT void isr_dma2_stream4(void); -WEAK_DEFAULT void isr_dma2_stream5(void); -WEAK_DEFAULT void isr_dma2_stream6(void); -WEAK_DEFAULT void isr_dma2_stream7(void); -WEAK_DEFAULT void isr_eth(void); -WEAK_DEFAULT void isr_eth_wkup(void); -WEAK_DEFAULT void isr_exti(void); -WEAK_DEFAULT void isr_flash(void); -WEAK_DEFAULT void isr_fsmc(void); -WEAK_DEFAULT void isr_hash_rng(void); -WEAK_DEFAULT void isr_i2c1_er(void); -WEAK_DEFAULT void isr_i2c1_ev(void); -WEAK_DEFAULT void isr_i2c2_er(void); -WEAK_DEFAULT void isr_i2c2_ev(void); -WEAK_DEFAULT void isr_i2c3_er(void); -WEAK_DEFAULT void isr_i2c3_ev(void); -WEAK_DEFAULT void isr_otg_fs(void); -WEAK_DEFAULT void isr_otg_fs_wkup(void); -WEAK_DEFAULT void isr_otg_hs(void); -WEAK_DEFAULT void isr_otg_hs_ep1_in(void); -WEAK_DEFAULT void isr_otg_hs_ep1_out(void); -WEAK_DEFAULT void isr_otg_hs_wkup(void); -WEAK_DEFAULT void isr_pvd(void); -WEAK_DEFAULT void isr_rcc(void); -WEAK_DEFAULT void isr_rtc_alarm(void); -WEAK_DEFAULT void isr_rtc_wkup(void); -WEAK_DEFAULT void isr_sdio(void); -WEAK_DEFAULT void isr_spi1(void); -WEAK_DEFAULT void isr_spi2(void); -WEAK_DEFAULT void isr_spi3(void); -WEAK_DEFAULT void isr_tamp_stamp(void); -WEAK_DEFAULT void isr_tim1_brk_tim9(void); -WEAK_DEFAULT void isr_tim1_cc(void); -WEAK_DEFAULT void isr_tim1_trg_com_tim11(void); -WEAK_DEFAULT void isr_tim1_up_tim10(void); -WEAK_DEFAULT void isr_tim2(void); -WEAK_DEFAULT void isr_tim3(void); -WEAK_DEFAULT void isr_tim4(void); -WEAK_DEFAULT void isr_tim5(void); -WEAK_DEFAULT void isr_tim6_dac(void); -WEAK_DEFAULT void isr_tim7(void); -WEAK_DEFAULT void isr_tim8_brk_tim12(void); -WEAK_DEFAULT void isr_tim8_cc(void); -WEAK_DEFAULT void isr_tim8_trg_com_tim14(void); -WEAK_DEFAULT void isr_tim8_up_tim13(void); -WEAK_DEFAULT void isr_uart4(void); -WEAK_DEFAULT void isr_uart5(void); -WEAK_DEFAULT void isr_usart1(void); -WEAK_DEFAULT void isr_usart2(void); -WEAK_DEFAULT void isr_usart3(void); -WEAK_DEFAULT void isr_usart6(void); -WEAK_DEFAULT void isr_wwdg(void); - -/* CPU specific interrupt vector table */ -ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = { - /* shared vectors for all family members */ - [ 0] = isr_wwdg, /* [ 0] Window WatchDog Interrupt */ - [ 1] = isr_pvd, /* [ 1] PVD through EXTI Line detection Interrupt */ - [ 2] = isr_tamp_stamp, /* [ 2] Tamper and TimeStamp interrupts through the EXTI line */ - [ 3] = isr_rtc_wkup, /* [ 3] RTC Wakeup interrupt through the EXTI line */ - [ 4] = isr_flash, /* [ 4] FLASH global Interrupt */ - [ 5] = isr_rcc, /* [ 5] RCC global Interrupt */ - [ 6] = isr_exti, /* [ 6] EXTI Line0 Interrupt */ - [ 7] = isr_exti, /* [ 7] EXTI Line1 Interrupt */ - [ 8] = isr_exti, /* [ 8] EXTI Line2 Interrupt */ - [ 9] = isr_exti, /* [ 9] EXTI Line3 Interrupt */ - [10] = isr_exti, /* [10] EXTI Line4 Interrupt */ - [11] = isr_dma1_stream0, /* [11] DMA1 Stream 0 global Interrupt */ - [12] = isr_dma1_stream1, /* [12] DMA1 Stream 1 global Interrupt */ - [13] = isr_dma1_stream2, /* [13] DMA1 Stream 2 global Interrupt */ - [14] = isr_dma1_stream3, /* [14] DMA1 Stream 3 global Interrupt */ - [15] = isr_dma1_stream4, /* [15] DMA1 Stream 4 global Interrupt */ - [16] = isr_dma1_stream5, /* [16] DMA1 Stream 5 global Interrupt */ - [17] = isr_dma1_stream6, /* [17] DMA1 Stream 6 global Interrupt */ - [18] = isr_adc, /* [18] ADC1, ADC2 and ADC3 global Interrupts */ - [19] = isr_can1_tx, /* [19] CAN1 TX Interrupt */ - [20] = isr_can1_rx0, /* [20] CAN1 RX0 Interrupt */ - [21] = isr_can1_rx1, /* [21] CAN1 RX1 Interrupt */ - [22] = isr_can1_sce, /* [22] CAN1 SCE Interrupt */ - [23] = isr_exti, /* [23] External Line[9:5] Interrupts */ - [24] = isr_tim1_brk_tim9, /* [24] TIM1 Break interrupt and TIM9 global interrupt */ - [25] = isr_tim1_up_tim10, /* [25] TIM1 Update Interrupt and TIM10 global interrupt */ - [26] = isr_tim1_trg_com_tim11, /* [26] TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - [27] = isr_tim1_cc, /* [27] TIM1 Capture Compare Interrupt */ - [28] = isr_tim2, /* [28] TIM2 global Interrupt */ - [29] = isr_tim3, /* [29] TIM3 global Interrupt */ - [30] = isr_tim4, /* [30] TIM4 global Interrupt */ - [31] = isr_i2c1_ev, /* [31] I2C1 Event Interrupt */ - [32] = isr_i2c1_er, /* [32] I2C1 Error Interrupt */ - [33] = isr_i2c2_ev, /* [33] I2C2 Event Interrupt */ - [34] = isr_i2c2_er, /* [34] I2C2 Error Interrupt */ - [35] = isr_spi1, /* [35] SPI1 global Interrupt */ - [36] = isr_spi2, /* [36] SPI2 global Interrupt */ - [37] = isr_usart1, /* [37] USART1 global Interrupt */ - [38] = isr_usart2, /* [38] USART2 global Interrupt */ - [39] = isr_usart3, /* [39] USART3 global Interrupt */ - [40] = isr_exti, /* [40] External Line[15:10] Interrupts */ - [41] = isr_rtc_alarm, /* [41] RTC Alarm (A and B) through EXTI Line Interrupt */ - [42] = isr_otg_fs_wkup, /* [42] USB OTG FS Wakeup through EXTI line interrupt */ - [43] = isr_tim8_brk_tim12, /* [43] TIM8 Break Interrupt and TIM12 global interrupt */ - [44] = isr_tim8_up_tim13, /* [44] TIM8 Update Interrupt and TIM13 global interrupt */ - [45] = isr_tim8_trg_com_tim14, /* [45] TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - [46] = isr_tim8_cc, /* [46] TIM8 Capture Compare Interrupt */ - [47] = isr_dma1_stream7, /* [47] DMA1 Stream7 Interrupt */ - [48] = isr_fsmc, /* [48] FSMC global Interrupt */ - [49] = isr_sdio, /* [49] SDIO global Interrupt */ - [50] = isr_tim5, /* [50] TIM5 global Interrupt */ - [51] = isr_spi3, /* [51] SPI3 global Interrupt */ - [52] = isr_uart4, /* [52] UART4 global Interrupt */ - [53] = isr_uart5, /* [53] UART5 global Interrupt */ - [54] = isr_tim6_dac, /* [54] TIM6 global and DAC1&2 underrun error interrupts */ - [55] = isr_tim7, /* [55] TIM7 global interrupt */ - [56] = isr_dma2_stream0, /* [56] DMA2 Stream 0 global Interrupt */ - [57] = isr_dma2_stream1, /* [57] DMA2 Stream 1 global Interrupt */ - [58] = isr_dma2_stream2, /* [58] DMA2 Stream 2 global Interrupt */ - [59] = isr_dma2_stream3, /* [59] DMA2 Stream 3 global Interrupt */ - [60] = isr_dma2_stream4, /* [60] DMA2 Stream 4 global Interrupt */ - [63] = isr_can2_tx, /* [63] CAN2 TX Interrupt */ - [64] = isr_can2_rx0, /* [64] CAN2 RX0 Interrupt */ - [65] = isr_can2_rx1, /* [65] CAN2 RX1 Interrupt */ - [66] = isr_can2_sce, /* [66] CAN2 SCE Interrupt */ - [67] = isr_otg_fs, /* [67] USB OTG FS global Interrupt */ - [68] = isr_dma2_stream5, /* [68] DMA2 Stream 5 global interrupt */ - [69] = isr_dma2_stream6, /* [69] DMA2 Stream 6 global interrupt */ - [70] = isr_dma2_stream7, /* [70] DMA2 Stream 7 global interrupt */ - [71] = isr_usart6, /* [71] USART6 global interrupt */ - [72] = isr_i2c3_ev, /* [72] I2C3 event interrupt */ - [73] = isr_i2c3_er, /* [73] I2C3 error interrupt */ - [74] = isr_otg_hs_ep1_out, /* [74] USB OTG HS End Point 1 Out global interrupt */ - [75] = isr_otg_hs_ep1_in, /* [75] USB OTG HS End Point 1 In global interrupt */ - [76] = isr_otg_hs_wkup, /* [76] USB OTG HS Wakeup through EXTI interrupt */ - [77] = isr_otg_hs, /* [77] USB OTG HS global interrupt */ - -#if defined(CPU_LINE_STM32F207xx) - [61] = isr_eth, /* [61] Ethernet global Interrupt */ - [62] = isr_eth_wkup, /* [62] Ethernet Wakeup through EXTI line Interrupt */ - [78] = isr_dcmi, /* [78] DCMI global interrupt */ - [80] = isr_hash_rng, /* [80] Hash and RNG global interrupt */ -#elif defined(CPU_LINE_STM32F215xx) - [79] = isr_cryp, /* [79] CRYP crypto global interrupt */ - [80] = isr_hash_rng, /* [80] Hash and RNG global interrupt */ -#elif defined(CPU_LINE_STM32F217xx) - [61] = isr_eth, /* [61] Ethernet global Interrupt */ - [62] = isr_eth_wkup, /* [62] Ethernet Wakeup through EXTI line Interrupt */ - [78] = isr_dcmi, /* [78] DCMI global interrupt */ - [79] = isr_cryp, /* [79] CRYP crypto global interrupt */ - [80] = isr_hash_rng, /* [80] Hash and Rng global interrupt */ -#endif -}; diff --git a/cpu/stm32/vectors/vectors_f3.c b/cpu/stm32/vectors/vectors_f3.c deleted file mode 100644 index f203514a9b..0000000000 --- a/cpu/stm32/vectors/vectors_f3.c +++ /dev/null @@ -1,376 +0,0 @@ -/* - * Copyright (C) 2014-2015 Freie Universität Berlin - * - * This file is subject to the terms and conditions of the GNU Lesser General - * Public License v2.1. See the file LICENSE in the top level directory for more - * details. - */ - -/** - * @ingroup cpu_stm32 - * @{ - * - * @file - * @brief Interrupt vector definitions for STM32F3 - * - * @author Hauke Petersen - * - * @} - */ - -#include -#include "vectors_cortexm.h" - -/* define a local dummy handler as it needs to be in the same compilation unit - * as the alias definition */ -void dummy_handler(void) { - dummy_handler_default(); -} - -/* STM32F3 specific interrupt vectors */ -WEAK_DEFAULT void isr_wwdg(void); -WEAK_DEFAULT void isr_pvd(void); -WEAK_DEFAULT void isr_tamp_stamp(void); -WEAK_DEFAULT void isr_rtc_wkup(void); -WEAK_DEFAULT void isr_flash(void); -WEAK_DEFAULT void isr_rcc(void); -WEAK_DEFAULT void isr_exti(void); -WEAK_DEFAULT void isr_dma1_channel1(void); -WEAK_DEFAULT void isr_dma1_channel2(void); -WEAK_DEFAULT void isr_dma1_channel3(void); -WEAK_DEFAULT void isr_dma1_channel4(void); -WEAK_DEFAULT void isr_dma1_channel5(void); -WEAK_DEFAULT void isr_dma1_channel6(void); -WEAK_DEFAULT void isr_dma1_channel7(void); -WEAK_DEFAULT void isr_adc1_2(void); -WEAK_DEFAULT void isr_usb_hp_can_tx(void); -WEAK_DEFAULT void isr_usb_lp_can_rx0(void); -WEAK_DEFAULT void isr_can_rx1(void); -WEAK_DEFAULT void isr_can_sce(void); -WEAK_DEFAULT void isr_tim1_brk_tim15(void); -WEAK_DEFAULT void isr_tim1_up_tim16(void); -WEAK_DEFAULT void isr_tim1_trg_com_tim17(void); -WEAK_DEFAULT void isr_tim1_cc(void); -WEAK_DEFAULT void isr_tim2(void); -WEAK_DEFAULT void isr_tim3(void); -WEAK_DEFAULT void isr_tim4(void); -WEAK_DEFAULT void isr_i2c1_ev(void); -WEAK_DEFAULT void isr_i2c1_er(void); -WEAK_DEFAULT void isr_i2c2_ev(void); -WEAK_DEFAULT void isr_i2c2_er(void); -WEAK_DEFAULT void isr_i2c3_ev(void); -WEAK_DEFAULT void isr_i2c3_er(void); -WEAK_DEFAULT void isr_spi1(void); -WEAK_DEFAULT void isr_spi2(void); -WEAK_DEFAULT void isr_usart1(void); -WEAK_DEFAULT void isr_usart2(void); -WEAK_DEFAULT void isr_usart3(void); -WEAK_DEFAULT void isr_rtc_alarm(void); -WEAK_DEFAULT void isr_usbwakeup(void); -WEAK_DEFAULT void isr_tim8_brk(void); -WEAK_DEFAULT void isr_tim8_up(void); -WEAK_DEFAULT void isr_tim8_trg_com(void); -WEAK_DEFAULT void isr_tim8_cc(void); -WEAK_DEFAULT void isr_adc3(void); -WEAK_DEFAULT void isr_fmc(void); -WEAK_DEFAULT void isr_spi3(void); -WEAK_DEFAULT void isr_uart4(void); -WEAK_DEFAULT void isr_uart5(void); -WEAK_DEFAULT void isr_tim6_dac(void); -WEAK_DEFAULT void isr_tim7(void); -WEAK_DEFAULT void isr_tim7_dac(void); -WEAK_DEFAULT void isr_dma2_channel1(void); -WEAK_DEFAULT void isr_dma2_channel2(void); -WEAK_DEFAULT void isr_dma2_channel3(void); -WEAK_DEFAULT void isr_dma2_channel4(void); -WEAK_DEFAULT void isr_dma2_channel5(void); -WEAK_DEFAULT void isr_adc4(void); -WEAK_DEFAULT void isr_comp1_2_3(void); -WEAK_DEFAULT void isr_comp4_5_6(void); -WEAK_DEFAULT void isr_comp7(void); -WEAK_DEFAULT void isr_hrtim(void); -WEAK_DEFAULT void isr_hrtim_tim_a(void); -WEAK_DEFAULT void isr_hrtim_tim_b(void); -WEAK_DEFAULT void isr_hrtim_tim_c(void); -WEAK_DEFAULT void isr_hrtim_tim_d(void); -WEAK_DEFAULT void isr_hrtim_tim_e(void); -WEAK_DEFAULT void isr_hrtim_flt(void); -WEAK_DEFAULT void isr_usb_hp(void); -WEAK_DEFAULT void isr_usb_lp(void); -WEAK_DEFAULT void isr_usbwakeup_rmp(void); -WEAK_DEFAULT void isr_tim20_brk(void); -WEAK_DEFAULT void isr_tim20_up(void); -WEAK_DEFAULT void isr_tim20_trg_com(void); -WEAK_DEFAULT void isr_tim20_cc(void); -WEAK_DEFAULT void isr_fpu(void); -WEAK_DEFAULT void isr_spi4(void); - -/* CPU specific interrupt vector table */ -ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = { - isr_wwdg, /* [0] Window WatchDog Interrupt */ - isr_pvd, /* [1] PVD through EXTI Line detection Interrupt */ - isr_tamp_stamp, /* [2] Tamper and TimeStamp interrupts through the EXTI line 19 */ - isr_rtc_wkup, /* [3] RTC Wakeup interrupt through the EXTI line 20 */ - isr_flash, /* [4] FLASH global Interrupt */ - isr_rcc, /* [5] RCC global Interrupt */ - isr_exti, /* [6] EXTI Line0 Interrupt */ - isr_exti, /* [7] EXTI Line1 Interrupt */ - isr_exti, /* [8] EXTI Line2 Interrupt and Touch Sense Controller Interrupt */ - isr_exti, /* [9] EXTI Line3 Interrupt */ - isr_exti, /* [10] EXTI Line4 Interrupt */ - isr_dma1_channel1, /* [11] DMA1 Channel 1 Interrupt */ - isr_dma1_channel2, /* [12] DMA1 Channel 2 Interrupt */ - isr_dma1_channel3, /* [13] DMA1 Channel 3 Interrupt */ - isr_dma1_channel4, /* [14] DMA1 Channel 4 Interrupt */ - isr_dma1_channel5, /* [15] DMA1 Channel 5 Interrupt */ - isr_dma1_channel6, /* [16] DMA1 Channel 6 Interrupt */ - isr_dma1_channel7, /* [17] DMA1 Channel 7 Interrupt */ - isr_adc1_2, /* [18] ADC1 & ADC2 Interrupts */ - isr_usb_hp_can_tx, /* [19] USB Device High Priority or CAN TX Interrupts */ - isr_usb_lp_can_rx0, /* [20] USB Device Low Priority or CAN RX0 Interrupts */ - isr_can_rx1, /* [21] CAN RX1 Interrupt */ - isr_can_sce, /* [22] CAN SCE Interrupt */ - isr_exti, /* [23] External Line[9:5] Interrupts */ - isr_tim1_brk_tim15, /* [24] TIM1 Break and TIM15 Interrupts */ - isr_tim1_up_tim16, /* [25] TIM1 Update and TIM16 Interrupts */ - isr_tim1_trg_com_tim17, /* [26] TIM1 Trigger and Commutation and TIM17 Interrupt */ - isr_tim1_cc, /* [27] TIM1 Capture Compare Interrupt */ - isr_tim2, /* [28] TIM2 global Interrupt */ -#if defined(CPU_LINE_STM32F302x8) - (0UL), /* [29] Reserved */ - (0UL), /* [30] Reserved */ - isr_i2c1_ev, /* [31] I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ - isr_i2c1_er, /* [32] I2C1 Error Interrupt */ - isr_i2c2_ev, /* [33] I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */ - isr_i2c2_er, /* [34] I2C2 Error Interrupt */ - (0UL), /* [35] Reserved */ - isr_spi2, /* [36] SPI2 global Interrupt */ - isr_usart1, /* [37] USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ - isr_usart2, /* [38] USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ - isr_usart3, /* [39] USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */ - isr_exti, /* [40] External Line[15:10] Interrupts */ - isr_rtc_alarm, /* [41] RTC Alarm (A and B) through EXTI Line 17 Interrupt */ - isr_usbwakeup, /* [42] USB Wakeup Interrupt */ - (0UL), /* [43] Reserved */ - (0UL), /* [44] Reserved */ - (0UL), /* [45] Reserved */ - (0UL), /* [46] Reserved */ - (0UL), /* [47] Reserved */ - (0UL), /* [48] Reserved */ - (0UL), /* [49] Reserved */ - (0UL), /* [50] Reserved */ - isr_spi3, /* [51] SPI3 global Interrupt */ - (0UL), /* [52] Reserved */ - (0UL), /* [53] Reserved */ - isr_tim6_dac, /* [54] TIM6 global and DAC channel 1&2 underrun error interrupts */ - (0UL), /* [55] Reserved */ - (0UL), /* [56] Reserved */ - (0UL), /* [57] Reserved */ - (0UL), /* [58] Reserved */ - (0UL), /* [59] Reserved */ - (0UL), /* [60] Reserved */ - (0UL), /* [61] Reserved */ - (0UL), /* [62] Reserved */ - (0UL), /* [63] Reserved */ - isr_comp1_2_3, /* [64] COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29 */ - isr_comp4_5_6, /* [65] COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32 */ - (0UL), /* [66] Reserved */ - (0UL), /* [67] Reserved */ - (0UL), /* [68] Reserved */ - (0UL), /* [69] Reserved */ - (0UL), /* [70] Reserved */ - (0UL), /* [71] Reserved */ - isr_i2c3_ev, /* [72] I2C3 event interrupt */ - isr_i2c3_er, /* [73] I2C3 error interrupt */ - isr_usb_hp, /* [74] USB High Priority global Interrupt remap */ - isr_usb_lp, /* [75] USB Low Priority global Interrupt remap */ - isr_usbwakeup_rmp, /* [76] USB Wakeup Interrupt remap */ - (0UL), /* [77] Reserved */ - (0UL), /* [78] Reserved */ - (0UL), /* [79] Reserved */ - (0UL), /* [80] Reserved */ - isr_fpu /* [81] Floating point Interrupt */ -#elif defined(CPU_LINE_STM32F303x8) - isr_tim3, /* [29] TIM3 global Interrupt */ - (0UL), /* [30] Reserved */ - isr_i2c1_ev, /* [31] I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ - isr_i2c1_er, /* [32] I2C1 Error Interrupt */ - (0UL), /* [33] Reserved */ - (0UL), /* [34] Reserved */ - isr_spi1, /* [35] SPI1 global Interrupt */ - (0UL), /* [36] Reserved */ - isr_usart1, /* [37] USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ - isr_usart2, /* [38] USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ - isr_usart3, /* [39] USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */ - isr_exti, /* [40] External Line[15:10] Interrupts */ - isr_rtc_alarm, /* [41] RTC Alarm (A and B) through EXTI Line 17 Interrupt */ - (0UL), /* [42] Reserved */ - (0UL), /* [43] Reserved */ - (0UL), /* [44] Reserved */ - (0UL), /* [45] Reserved */ - (0UL), /* [46] Reserved */ - (0UL), /* [47] Reserved */ - (0UL), /* [48] Reserved */ - (0UL), /* [49] Reserved */ - (0UL), /* [50] Reserved */ - (0UL), /* [51] Reserved */ - (0UL), /* [52] Reserved */ - (0UL), /* [53] Reserved */ - isr_tim6_dac, /* [54] TIM6 global and DAC channel 1&2 underrun error interrupts */ - isr_tim7_dac, /* [55] TIM7 global and DAC2 channel1 underrun error Interrupt */ - (0UL), /* [56] Reserved */ - (0UL), /* [57] Reserved */ - (0UL), /* [58] Reserved */ - (0UL), /* [59] Reserved */ - (0UL), /* [60] Reserved */ - (0UL), /* [61] Reserved */ - (0UL), /* [62] Reserved */ - (0UL), /* [63] Reserved */ - isr_comp1_2_3, /* [64] COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29 */ - isr_comp4_5_6, /* [65] COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32 */ - (0UL), /* [66] Reserved */ - (0UL), /* [67] Reserved */ - (0UL), /* [68] Reserved */ - (0UL), /* [69] Reserved */ - (0UL), /* [70] Reserved */ - (0UL), /* [71] Reserved */ - (0UL), /* [72] Reserved */ - (0UL), /* [73] Reserved */ - (0UL), /* [74] Reserved */ - (0UL), /* [75] Reserved */ - (0UL), /* [76] Reserved */ - (0UL), /* [77] Reserved */ - (0UL), /* [78] Reserved */ - (0UL), /* [79] Reserved */ - (0UL), /* [80] Reserved */ - isr_fpu /* [81] Floating point Interrupt */ -#elif defined(CPU_LINE_STM32F334x8) - isr_tim3, /* [29] TIM3 global Interrupt */ - (0UL), /* [30] Reserved */ - isr_i2c1_ev, /* [31] I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ - isr_i2c1_er, /* [32] I2C1 Error Interrupt */ - (0UL), /* [33] Reserved */ - (0UL), /* [34] Reserved */ - isr_spi1, /* [35] SPI1 global Interrupt */ - (0UL), /* [36] Reserved */ - isr_usart1, /* [37] USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ - isr_usart2, /* [38] USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ - isr_usart3, /* [39] USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */ - isr_exti, /* [40] External Line[15:10] Interrupts */ - isr_rtc_alarm, /* [41] RTC Alarm (A and B) through EXTI Line 17 Interrupt */ - (0UL), /* [42] Reserved */ - (0UL), /* [43] Reserved */ - (0UL), /* [44] Reserved */ - (0UL), /* [45] Reserved */ - (0UL), /* [46] Reserved */ - (0UL), /* [47] Reserved */ - (0UL), /* [48] Reserved */ - (0UL), /* [49] Reserved */ - (0UL), /* [50] Reserved */ - (0UL), /* [51] Reserved */ - (0UL), /* [52] Reserved */ - (0UL), /* [53] Reserved */ - isr_tim6_dac, /* [54] TIM6 global and DAC channel 1&2 underrun error interrupts */ - isr_tim7_dac, /* [55] TIM7 global and DAC2 channel1 underrun error Interrupt */ - (0UL), /* [56] Reserved */ - (0UL), /* [57] Reserved */ - (0UL), /* [58] Reserved */ - (0UL), /* [59] Reserved */ - (0UL), /* [60] Reserved */ - (0UL), /* [61] Reserved */ - (0UL), /* [62] Reserved */ - (0UL), /* [63] Reserved */ - isr_comp1_2_3, /* [64] COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29 */ - isr_comp4_5_6, /* [65] COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32 */ - (0UL), /* [66] Reserved */ - isr_hrtim, /* [67] HRTIM Master Timer global Interrupts */ - isr_hrtim_tim_a, /* [68] HRTIM Timer A global Interrupt */ - isr_hrtim_tim_b, /* [69] HRTIM Timer B global Interrupt */ - isr_hrtim_tim_c, /* [70] HRTIM Timer C global Interrupt */ - isr_hrtim_tim_d, /* [71] HRTIM Timer D global Interrupt */ - isr_hrtim_tim_e, /* [72] HRTIM Timer E global Interrupt */ - isr_hrtim_flt, /* [73] HRTIM Fault global Interrupt */ - (0UL), /* [74] Reserved */ - (0UL), /* [75] Reserved */ - (0UL), /* [76] Reserved */ - (0UL), /* [77] Reserved */ - (0UL), /* [78] Reserved */ - (0UL), /* [79] Reserved */ - (0UL), /* [80] Reserved */ - isr_fpu /* [81] Floating point Interrupt */ -#else /* CPU_LINE_STM32F303xC, CPU_LINE_STM32F303xE */ - isr_tim3, /* [29] TIM3 global Interrupt */ - isr_tim4, /* [30] TIM4 global Interrupt */ - isr_i2c1_ev, /* [31] I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ - isr_i2c1_er, /* [32] I2C1 Error Interrupt */ - isr_i2c2_ev, /* [33] I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */ - isr_i2c2_er, /* [34] I2C2 Error Interrupt */ - isr_spi1, /* [35] SPI1 global Interrupt */ - isr_spi2, /* [36] SPI2 global Interrupt */ - isr_usart1, /* [37] USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ - isr_usart2, /* [38] USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ - isr_usart3, /* [39] USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */ - isr_exti, /* [40] External Line[15:10] Interrupts */ - isr_rtc_alarm, /* [41] RTC Alarm (A and B) through EXTI Line 17 Interrupt */ - isr_usbwakeup, /* [42] USB Wakeup Interrupt */ - isr_tim8_brk, /* [43] TIM8 Break Interrupt */ - isr_tim8_up, /* [44] TIM8 Update Interrupt */ - isr_tim8_trg_com, /* [45] TIM8 Trigger and Commutation Interrupt */ - isr_tim8_cc, /* [46] TIM8 Capture Compare Interrupt */ - isr_adc3, /* [47] ADC3 global Interrupt */ -#if defined(CPU_LINE_STM32F303xC) - (0UL), /* [48] Reserved */ -#else - isr_fmc, /* [48] FMC global Interrupt */ -#endif - (0UL), /* [49] Reserved */ - (0UL), /* [50] Reserved */ - isr_spi3, /* [51] SPI3 global Interrupt */ - isr_uart4, /* [52] UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */ - isr_uart5, /* [53] UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */ - isr_tim6_dac, /* [54] TIM6 global and DAC channel 1&2 underrun error interrupts */ - isr_tim7, /* [55] TIM7 global Interrupt */ - isr_dma2_channel1, /* [56] DMA2 Channel 1 global Interrupt */ - isr_dma2_channel2, /* [57] DMA2 Channel 2 global Interrupt */ - isr_dma2_channel3, /* [58] DMA2 Channel 3 global Interrupt */ - isr_dma2_channel4, /* [59] DMA2 Channel 4 global Interrupt */ - isr_dma2_channel5, /* [60] DMA2 Channel 5 global Interrupt */ - isr_adc4, /* [61] ADC4 global Interrupt */ - (0UL), /* [62] Reserved */ - (0UL), /* [63] Reserved */ - isr_comp1_2_3, /* [64] COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29 */ - isr_comp4_5_6, /* [65] COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32 */ - isr_comp7, /* [66] COMP7 global Interrupt via EXTI Line33 */ - (0UL), /* [67] Reserved */ - (0UL), /* [68] Reserved */ - (0UL), /* [69] Reserved */ - (0UL), /* [70] Reserved */ - (0UL), /* [71] Reserved */ -#if defined(CPU_LINE_STM32F303xC) - (0UL), /* [72] Reserved */ - (0UL), /* [73] Reserved */ - isr_usb_hp, /* [74] USB High Priority global Interrupt remap */ - isr_usb_lp, /* [75] USB Low Priority global Interrupt remap */ - isr_usbwakeup_rmp, /* [76] USB Wakeup Interrupt remap */ - (0UL), /* [77] Reserved */ - (0UL), /* [78] Reserved */ - (0UL), /* [79] Reserved */ - (0UL), /* [80] Reserved */ - isr_fpu /* [81] Floating point Interrupt */ -#else /* CPU_LINE_STM32F303xE */ - isr_i2c3_ev, /* [72] I2C3 event interrupt */ - isr_i2c3_er, /* [73] I2C3 error interrupt */ - isr_usb_hp, /* [74] USB High Priority global Interrupt remap */ - isr_usb_lp, /* [75] USB Low Priority global Interrupt remap */ - isr_usbwakeup_rmp, /* [76] USB Wakeup Interrupt remap */ - isr_tim20_brk, /* [77] TIM20 Break Interrupt */ - isr_tim20_up, /* [78] TIM20 Update Interrupt */ - isr_tim20_trg_com, /* [79] TIM20 Trigger and Commutation Interrupt */ - isr_tim8_cc, /* [80] TIM20 Capture Compare Interrupt */ - isr_fpu, /* [81] Floating point Interrupt */ - (0UL), /* [82] Reserved */ - (0UL), /* [83] Reserved */ - isr_spi4, /* [84] SPI4 global Interrupt */ -#endif -#endif -}; diff --git a/cpu/stm32/vectors/vectors_f4.c b/cpu/stm32/vectors/vectors_f4.c deleted file mode 100644 index 3fd7287a1e..0000000000 --- a/cpu/stm32/vectors/vectors_f4.c +++ /dev/null @@ -1,608 +0,0 @@ -/* - * Copyright (C) 2014-2017 Freie Universität Berlin - * 2017-2018 OTA keys S.A. - * - * This file is subject to the terms and conditions of the GNU Lesser General - * Public License v2.1. See the file LICENSE in the top level directory for more - * details. - */ - -/** - * @ingroup cpu_stm32 - * @{ - * - * @file - * @brief Interrupt vector definitions for STM32F4 - * - * @author Hauke Petersen - * @author Vincent Dupont - * - * @} - */ - -#include "vectors_cortexm.h" - -/* define a local dummy handler as it needs to be in the same compilation unit - * as the alias definition */ -void dummy_handler(void) { - dummy_handler_default(); -} - -WEAK_DEFAULT void isr_adc(void); -WEAK_DEFAULT void isr_aes(void); -WEAK_DEFAULT void isr_can1_rx0(void); -WEAK_DEFAULT void isr_can1_rx1(void); -WEAK_DEFAULT void isr_can1_sce(void); -WEAK_DEFAULT void isr_can1_tx(void); -WEAK_DEFAULT void isr_can2_rx0(void); -WEAK_DEFAULT void isr_can2_rx1(void); -WEAK_DEFAULT void isr_can2_sce(void); -WEAK_DEFAULT void isr_can2_tx(void); -WEAK_DEFAULT void isr_can3_rx0(void); -WEAK_DEFAULT void isr_can3_rx1(void); -WEAK_DEFAULT void isr_can3_sce(void); -WEAK_DEFAULT void isr_can3_tx(void); -WEAK_DEFAULT void isr_cec(void); -WEAK_DEFAULT void isr_cryp(void); -WEAK_DEFAULT void isr_dcmi(void); -WEAK_DEFAULT void isr_dfsdm1_flt0(void); -WEAK_DEFAULT void isr_dfsdm1_flt1(void); -WEAK_DEFAULT void isr_dfsdm2_flt0(void); -WEAK_DEFAULT void isr_dfsdm2_flt1(void); -WEAK_DEFAULT void isr_dfsdm2_flt2(void); -WEAK_DEFAULT void isr_dfsdm2_flt3(void); -WEAK_DEFAULT void isr_dma1_stream0(void); -WEAK_DEFAULT void isr_dma1_stream1(void); -WEAK_DEFAULT void isr_dma1_stream2(void); -WEAK_DEFAULT void isr_dma1_stream3(void); -WEAK_DEFAULT void isr_dma1_stream4(void); -WEAK_DEFAULT void isr_dma1_stream5(void); -WEAK_DEFAULT void isr_dma1_stream6(void); -WEAK_DEFAULT void isr_dma1_stream7(void); -WEAK_DEFAULT void isr_dma2_stream0(void); -WEAK_DEFAULT void isr_dma2_stream1(void); -WEAK_DEFAULT void isr_dma2_stream2(void); -WEAK_DEFAULT void isr_dma2_stream3(void); -WEAK_DEFAULT void isr_dma2_stream4(void); -WEAK_DEFAULT void isr_dma2_stream5(void); -WEAK_DEFAULT void isr_dma2_stream6(void); -WEAK_DEFAULT void isr_dma2_stream7(void); -WEAK_DEFAULT void isr_dma2d(void); -WEAK_DEFAULT void isr_eth(void); -WEAK_DEFAULT void isr_eth_wkup(void); -WEAK_DEFAULT void isr_exti(void); -WEAK_DEFAULT void isr_flash(void); -WEAK_DEFAULT void isr_fmc(void); -WEAK_DEFAULT void isr_fmpi2c1_er(void); -WEAK_DEFAULT void isr_fmpi2c1_ev(void); -WEAK_DEFAULT void isr_fpu(void); -WEAK_DEFAULT void isr_fsmc(void); -WEAK_DEFAULT void isr_hash_rng(void); -WEAK_DEFAULT void isr_i2c1_er(void); -WEAK_DEFAULT void isr_i2c1_ev(void); -WEAK_DEFAULT void isr_i2c2_er(void); -WEAK_DEFAULT void isr_i2c2_ev(void); -WEAK_DEFAULT void isr_i2c3_er(void); -WEAK_DEFAULT void isr_i2c3_ev(void); -WEAK_DEFAULT void isr_lptim1(void); -WEAK_DEFAULT void isr_ltdc(void); -WEAK_DEFAULT void isr_ltdc_er(void); -WEAK_DEFAULT void isr_otg_fs(void); -WEAK_DEFAULT void isr_otg_fs_wkup(void); -WEAK_DEFAULT void isr_otg_hs(void); -WEAK_DEFAULT void isr_otg_hs_ep1_in(void); -WEAK_DEFAULT void isr_otg_hs_ep1_out(void); -WEAK_DEFAULT void isr_otg_hs_wkup(void); -WEAK_DEFAULT void isr_pvd(void); -WEAK_DEFAULT void isr_quadspi(void); -WEAK_DEFAULT void isr_rcc(void); -WEAK_DEFAULT void isr_rng(void); -WEAK_DEFAULT void isr_rtc_alarm(void); -WEAK_DEFAULT void isr_rtc_wkup(void); -WEAK_DEFAULT void isr_sai1(void); -WEAK_DEFAULT void isr_sai2(void); -WEAK_DEFAULT void isr_sdio(void); -WEAK_DEFAULT void isr_spdif_rx(void); -WEAK_DEFAULT void isr_spi1(void); -WEAK_DEFAULT void isr_spi2(void); -WEAK_DEFAULT void isr_spi3(void); -WEAK_DEFAULT void isr_spi4(void); -WEAK_DEFAULT void isr_spi5(void); -WEAK_DEFAULT void isr_spi6(void); -WEAK_DEFAULT void isr_tamp_stamp(void); -WEAK_DEFAULT void isr_tim1_brk_tim9(void); -WEAK_DEFAULT void isr_tim1_cc(void); -WEAK_DEFAULT void isr_tim1_trg_com_tim11(void); -WEAK_DEFAULT void isr_tim1_up(void); -WEAK_DEFAULT void isr_tim1_up_tim10(void); -WEAK_DEFAULT void isr_tim2(void); -WEAK_DEFAULT void isr_tim3(void); -WEAK_DEFAULT void isr_tim4(void); -WEAK_DEFAULT void isr_tim5(void); -WEAK_DEFAULT void isr_tim6(void); -WEAK_DEFAULT void isr_tim6_dac(void); -WEAK_DEFAULT void isr_tim7(void); -WEAK_DEFAULT void isr_tim8_brk_tim12(void); -WEAK_DEFAULT void isr_tim8_cc(void); -WEAK_DEFAULT void isr_tim8_trg_com_tim14(void); -WEAK_DEFAULT void isr_tim8_up_tim13(void); -WEAK_DEFAULT void isr_uart10(void); -WEAK_DEFAULT void isr_uart4(void); -WEAK_DEFAULT void isr_uart5(void); -WEAK_DEFAULT void isr_uart7(void); -WEAK_DEFAULT void isr_uart8(void); -WEAK_DEFAULT void isr_uart9(void); -WEAK_DEFAULT void isr_usart1(void); -WEAK_DEFAULT void isr_usart2(void); -WEAK_DEFAULT void isr_usart3(void); -WEAK_DEFAULT void isr_usart6(void); -WEAK_DEFAULT void isr_wwdg(void); - -/* CPU specific interrupt vector table */ -ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = { - /* shared vectors for all family members */ - [ 0] = isr_wwdg, /* [ 0] Window WatchDog Interrupt */ - [ 1] = isr_pvd, /* [ 1] PVD through EXTI Line detection Interrupt */ - [ 2] = isr_tamp_stamp, /* [ 2] Tamper and TimeStamp interrupts through the EXTI line */ - [ 3] = isr_rtc_wkup, /* [ 3] RTC Wakeup interrupt through the EXTI line */ - [ 4] = isr_flash, /* [ 4] FLASH global Interrupt */ - [ 5] = isr_rcc, /* [ 5] RCC global Interrupt */ - [ 6] = isr_exti, /* [ 6] EXTI Line0 Interrupt */ - [ 7] = isr_exti, /* [ 7] EXTI Line1 Interrupt */ - [ 8] = isr_exti, /* [ 8] EXTI Line2 Interrupt */ - [ 9] = isr_exti, /* [ 9] EXTI Line3 Interrupt */ - [10] = isr_exti, /* [10] EXTI Line4 Interrupt */ - [11] = isr_dma1_stream0, /* [11] DMA1 Stream 0 global Interrupt */ - [12] = isr_dma1_stream1, /* [12] DMA1 Stream 1 global Interrupt */ - [13] = isr_dma1_stream2, /* [13] DMA1 Stream 2 global Interrupt */ - [14] = isr_dma1_stream3, /* [14] DMA1 Stream 3 global Interrupt */ - [15] = isr_dma1_stream4, /* [15] DMA1 Stream 4 global Interrupt */ - [16] = isr_dma1_stream5, /* [16] DMA1 Stream 5 global Interrupt */ - [17] = isr_dma1_stream6, /* [17] DMA1 Stream 6 global Interrupt */ - [23] = isr_exti, /* [23] External Line[9:5] Interrupts */ - [24] = isr_tim1_brk_tim9, /* [24] TIM1 Break interrupt and TIM9 global interrupt */ - [26] = isr_tim1_trg_com_tim11, /* [26] TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - [27] = isr_tim1_cc, /* [27] TIM1 Capture Compare Interrupt */ - [31] = isr_i2c1_ev, /* [31] I2C1 Event Interrupt */ - [32] = isr_i2c1_er, /* [32] I2C1 Error Interrupt */ - [33] = isr_i2c2_ev, /* [33] I2C2 Event Interrupt */ - [34] = isr_i2c2_er, /* [34] I2C2 Error Interrupt */ - [35] = isr_spi1, /* [35] SPI1 global Interrupt */ - [36] = isr_spi2, /* [36] SPI2 global Interrupt */ - [37] = isr_usart1, /* [37] USART1 global Interrupt */ - [38] = isr_usart2, /* [38] USART2 global Interrupt */ - [40] = isr_exti, /* [40] External Line[15:10] Interrupts */ - [41] = isr_rtc_alarm, /* [41] RTC Alarm (A and B) through EXTI Line Interrupt */ - [47] = isr_dma1_stream7, /* [47] DMA1 Stream7 Interrupt */ - [50] = isr_tim5, /* [50] TIM5 global Interrupt */ - [56] = isr_dma2_stream0, /* [56] DMA2 Stream 0 global Interrupt */ - [57] = isr_dma2_stream1, /* [57] DMA2 Stream 1 global Interrupt */ - [58] = isr_dma2_stream2, /* [58] DMA2 Stream 2 global Interrupt */ - [59] = isr_dma2_stream3, /* [59] DMA2 Stream 3 global Interrupt */ - [60] = isr_dma2_stream4, /* [60] DMA2 Stream 4 global Interrupt */ - [68] = isr_dma2_stream5, /* [68] DMA2 Stream 5 global interrupt */ - [69] = isr_dma2_stream6, /* [69] DMA2 Stream 6 global interrupt */ - [70] = isr_dma2_stream7, /* [70] DMA2 Stream 7 global interrupt */ - [71] = isr_usart6, /* [71] USART6 global interrupt */ - [81] = isr_fpu, /* [81] FPU global interrupt */ - -#if defined(CPU_LINE_STM32F401xE) - [18] = isr_adc, /* [18] ADC1, ADC2 and ADC3 global Interrupts */ - [25] = isr_tim1_up_tim10, /* [25] TIM1 Update Interrupt and TIM10 global interrupt */ - [28] = isr_tim2, /* [28] TIM2 global Interrupt */ - [29] = isr_tim3, /* [29] TIM3 global Interrupt */ - [30] = isr_tim4, /* [30] TIM4 global Interrupt */ - [42] = isr_otg_fs_wkup, /* [42] USB OTG FS Wakeup through EXTI line interrupt */ - [49] = isr_sdio, /* [49] SDIO global Interrupt */ - [51] = isr_spi3, /* [51] SPI3 global Interrupt */ - [67] = isr_otg_fs, /* [67] USB OTG FS global Interrupt */ - [72] = isr_i2c3_ev, /* [72] I2C3 event interrupt */ - [73] = isr_i2c3_er, /* [73] I2C3 error interrupt */ - [84] = isr_spi4, /* [84] SPI4 global Interrupt */ -#elif defined(CPU_LINE_STM32F405xx) - [18] = isr_adc, /* [18] ADC1, ADC2 and ADC3 global Interrupts */ - [19] = isr_can1_tx, /* [19] CAN1 TX Interrupt */ - [20] = isr_can1_rx0, /* [20] CAN1 RX0 Interrupt */ - [21] = isr_can1_rx1, /* [21] CAN1 RX1 Interrupt */ - [22] = isr_can1_sce, /* [22] CAN1 SCE Interrupt */ - [25] = isr_tim1_up_tim10, /* [25] TIM1 Update Interrupt and TIM10 global interrupt */ - [28] = isr_tim2, /* [28] TIM2 global Interrupt */ - [29] = isr_tim3, /* [29] TIM3 global Interrupt */ - [30] = isr_tim4, /* [30] TIM4 global Interrupt */ - [39] = isr_usart3, /* [39] USART3 global Interrupt */ - [42] = isr_otg_fs_wkup, /* [42] USB OTG FS Wakeup through EXTI line interrupt */ - [43] = isr_tim8_brk_tim12, /* [43] TIM8 Break Interrupt and TIM12 global interrupt */ - [44] = isr_tim8_up_tim13, /* [44] TIM8 Update Interrupt and TIM13 global interrupt */ - [45] = isr_tim8_trg_com_tim14, /* [45] TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - [46] = isr_tim8_cc, /* [46] TIM8 Capture Compare global interrupt */ - [48] = isr_fsmc, /* [48] FSMC global Interrupt */ - [49] = isr_sdio, /* [49] SDIO global Interrupt */ - [51] = isr_spi3, /* [51] SPI3 global Interrupt */ - [52] = isr_uart4, /* [52] UART4 global Interrupt */ - [53] = isr_uart5, /* [53] UART5 global Interrupt */ - [54] = isr_tim6_dac, /* [54] TIM6 global and DAC1&2 underrun error interrupts */ - [55] = isr_tim7, /* [55] TIM7 global interrupt */ - [63] = isr_can2_tx, /* [63] CAN2 TX Interrupt */ - [64] = isr_can2_rx0, /* [64] CAN2 RX0 Interrupt */ - [65] = isr_can2_rx1, /* [65] CAN2 RX1 Interrupt */ - [66] = isr_can2_sce, /* [66] CAN2 SCE Interrupt */ - [67] = isr_otg_fs, /* [67] USB OTG FS global Interrupt */ - [72] = isr_i2c3_ev, /* [72] I2C3 event interrupt */ - [73] = isr_i2c3_er, /* [73] I2C3 error interrupt */ - [74] = isr_otg_hs_ep1_out, /* [74] USB OTG HS End Point 1 Out global interrupt */ - [75] = isr_otg_hs_ep1_in, /* [75] USB OTG HS End Point 1 In global interrupt */ - [76] = isr_otg_hs_wkup, /* [76] USB OTG HS Wakeup through EXTI interrupt */ - [77] = isr_otg_hs, /* [77] USB OTG HS global interrupt */ - [78] = isr_dcmi, /* [78] DCMI global interrupt */ - [80] = isr_rng, /* [80] RNG global Interrupt */ -#elif defined(CPU_LINE_STM32F407xx) - [18] = isr_adc, /* [18] ADC1, ADC2 and ADC3 global Interrupts */ - [19] = isr_can1_tx, /* [19] CAN1 TX Interrupt */ - [20] = isr_can1_rx0, /* [20] CAN1 RX0 Interrupt */ - [21] = isr_can1_rx1, /* [21] CAN1 RX1 Interrupt */ - [22] = isr_can1_sce, /* [22] CAN1 SCE Interrupt */ - [25] = isr_tim1_up_tim10, /* [25] TIM1 Update Interrupt and TIM10 global interrupt */ - [28] = isr_tim2, /* [28] TIM2 global Interrupt */ - [29] = isr_tim3, /* [29] TIM3 global Interrupt */ - [30] = isr_tim4, /* [30] TIM4 global Interrupt */ - [39] = isr_usart3, /* [39] USART3 global Interrupt */ - [42] = isr_otg_fs_wkup, /* [42] USB OTG FS Wakeup through EXTI line interrupt */ - [43] = isr_tim8_brk_tim12, /* [43] TIM8 Break Interrupt and TIM12 global interrupt */ - [44] = isr_tim8_up_tim13, /* [44] TIM8 Update Interrupt and TIM13 global interrupt */ - [45] = isr_tim8_trg_com_tim14, /* [45] TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - [46] = isr_tim8_cc, /* [46] TIM8 Capture Compare global interrupt */ - [48] = isr_fsmc, /* [48] FSMC global Interrupt */ - [49] = isr_sdio, /* [49] SDIO global Interrupt */ - [51] = isr_spi3, /* [51] SPI3 global Interrupt */ - [52] = isr_uart4, /* [52] UART4 global Interrupt */ - [53] = isr_uart5, /* [53] UART5 global Interrupt */ - [54] = isr_tim6_dac, /* [54] TIM6 global and DAC1&2 underrun error interrupts */ - [55] = isr_tim7, /* [55] TIM7 global interrupt */ - [61] = isr_eth, /* [61] Ethernet global Interrupt */ - [62] = isr_eth_wkup, /* [62] Ethernet Wakeup through EXTI line Interrupt */ - [63] = isr_can2_tx, /* [63] CAN2 TX Interrupt */ - [64] = isr_can2_rx0, /* [64] CAN2 RX0 Interrupt */ - [65] = isr_can2_rx1, /* [65] CAN2 RX1 Interrupt */ - [66] = isr_can2_sce, /* [66] CAN2 SCE Interrupt */ - [67] = isr_otg_fs, /* [67] USB OTG FS global Interrupt */ - [72] = isr_i2c3_ev, /* [72] I2C3 event interrupt */ - [73] = isr_i2c3_er, /* [73] I2C3 error interrupt */ - [74] = isr_otg_hs_ep1_out, /* [74] USB OTG HS End Point 1 Out global interrupt */ - [75] = isr_otg_hs_ep1_in, /* [75] USB OTG HS End Point 1 In global interrupt */ - [76] = isr_otg_hs_wkup, /* [76] USB OTG HS Wakeup through EXTI interrupt */ - [77] = isr_otg_hs, /* [77] USB OTG HS global interrupt */ - [78] = isr_dcmi, /* [78] DCMI global interrupt */ -#elif defined(CPU_LINE_STM32F410Rx) - [18] = isr_adc, /* [18] ADC1 global Interrupts */ - [25] = isr_tim1_up, /* [25] TIM1 Update Interrupt */ - [54] = isr_tim6_dac, /* [54] TIM6 global Interrupt and DAC Global Interrupt */ - [80] = isr_rng, /* [80] RNG global Interrupt */ - [85] = isr_spi5, /* [85] SPI5 global Interrupt */ - [95] = isr_fmpi2c1_ev, /* [95] FMPI2C1 Event Interrupt */ - [96] = isr_fmpi2c1_er, /* [96] FMPI2C1 Error Interrupt */ - [97] = isr_lptim1, /* [97] LPTIM1 interrupt */ -#elif defined(CPU_LINE_STM32F411xE) - [18] = isr_adc, /* [18] ADC1, ADC2 and ADC3 global Interrupts */ - [25] = isr_tim1_up_tim10, /* [25] TIM1 Update Interrupt and TIM10 global interrupt */ - [28] = isr_tim2, /* [28] TIM2 global Interrupt */ - [29] = isr_tim3, /* [29] TIM3 global Interrupt */ - [30] = isr_tim4, /* [30] TIM4 global Interrupt */ - [42] = isr_otg_fs_wkup, /* [42] USB OTG FS Wakeup through EXTI line interrupt */ - [49] = isr_sdio, /* [49] SDIO global Interrupt */ - [51] = isr_spi3, /* [51] SPI3 global Interrupt */ - [67] = isr_otg_fs, /* [67] USB OTG FS global Interrupt */ - [72] = isr_i2c3_ev, /* [72] I2C3 event interrupt */ - [73] = isr_i2c3_er, /* [73] I2C3 error interrupt */ - [84] = isr_spi4, /* [84] SPI4 global Interrupt */ - [85] = isr_spi5, /* [85] SPI5 global Interrupt */ -#elif defined(CPU_LINE_STM32F412Zx) - [18] = isr_adc, /* [18] ADC1, ADC2 and ADC3 global Interrupts */ - [19] = isr_can1_tx, /* [19] CAN1 TX Interrupt */ - [20] = isr_can1_rx0, /* [20] CAN1 RX0 Interrupt */ - [21] = isr_can1_rx1, /* [21] CAN1 RX1 Interrupt */ - [22] = isr_can1_sce, /* [22] CAN1 SCE Interrupt */ - [25] = isr_tim1_up_tim10, /* [25] TIM1 Update Interrupt and TIM10 global interrupt */ - [28] = isr_tim2, /* [28] TIM2 global Interrupt */ - [29] = isr_tim3, /* [29] TIM3 global Interrupt */ - [30] = isr_tim4, /* [30] TIM4 global Interrupt */ - [39] = isr_usart3, /* [39] USART3 global Interrupt */ - [42] = isr_otg_fs_wkup, /* [42] USB OTG FS Wakeup through EXTI line interrupt */ - [43] = isr_tim8_brk_tim12, /* [43] TIM8 Break Interrupt and TIM12 global interrupt */ - [44] = isr_tim8_up_tim13, /* [44] TIM8 Update Interrupt and TIM13 global interrupt */ - [45] = isr_tim8_trg_com_tim14, /* [45] TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - [46] = isr_tim8_cc, /* [46] TIM8 Capture Compare global interrupt */ - [49] = isr_sdio, /* [49] SDIO global Interrupt */ - [51] = isr_spi3, /* [51] SPI3 global Interrupt */ - [54] = isr_tim6, /* [54] TIM6 global interrupt */ - [55] = isr_tim7, /* [55] TIM7 global interrupt */ - [61] = isr_dfsdm1_flt0, /* [61] DFSDM1 Filter 0 global Interrupt */ - [62] = isr_dfsdm1_flt1, /* [62] DFSDM1 Filter 1 global Interrupt */ - [63] = isr_can2_tx, /* [63] CAN2 TX Interrupt */ - [64] = isr_can2_rx0, /* [64] CAN2 RX0 Interrupt */ - [65] = isr_can2_rx1, /* [65] CAN2 RX1 Interrupt */ - [66] = isr_can2_sce, /* [66] CAN2 SCE Interrupt */ - [67] = isr_otg_fs, /* [67] USB OTG FS global Interrupt */ - [72] = isr_i2c3_ev, /* [72] I2C3 event interrupt */ - [73] = isr_i2c3_er, /* [73] I2C3 error interrupt */ - [80] = isr_rng, /* [80] RNG global Interrupt */ - [84] = isr_spi4, /* [84] SPI4 global Interrupt */ - [85] = isr_spi5, /* [85] SPI5 global Interrupt */ - [92] = isr_quadspi, /* [92] QuadSPI global Interrupt */ - [95] = isr_fmpi2c1_ev, /* [95] FMPI2C1 Event Interrupt */ - [96] = isr_fmpi2c1_er, /* [96] FMPI2C1 Error Interrupt */ -#elif defined(CPU_LINE_STM32F413xx) - [18] = isr_adc, /* [18] ADC1, ADC2 and ADC3 global Interrupts */ - [19] = isr_can1_tx, /* [19] CAN1 TX Interrupt */ - [20] = isr_can1_rx0, /* [20] CAN1 RX0 Interrupt */ - [21] = isr_can1_rx1, /* [21] CAN1 RX1 Interrupt */ - [22] = isr_can1_sce, /* [22] CAN1 SCE Interrupt */ - [25] = isr_tim1_up_tim10, /* [25] TIM1 Update Interrupt and TIM10 global interrupt */ - [28] = isr_tim2, /* [28] TIM2 global Interrupt */ - [29] = isr_tim3, /* [29] TIM3 global Interrupt */ - [30] = isr_tim4, /* [30] TIM4 global Interrupt */ - [39] = isr_usart3, /* [39] USART3 global Interrupt */ - [42] = isr_otg_fs_wkup, /* [42] USB OTG FS Wakeup through EXTI line interrupt */ - [43] = isr_tim8_brk_tim12, /* [43] TIM8 Break Interrupt and TIM12 global interrupt */ - [44] = isr_tim8_up_tim13, /* [44] TIM8 Update Interrupt and TIM13 global interrupt */ - [45] = isr_tim8_trg_com_tim14, /* [45] TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - [46] = isr_tim8_cc, /* [46] TIM8 Capture Compare global interrupt */ - [49] = isr_sdio, /* [49] SDIO global Interrupt */ - [51] = isr_spi3, /* [51] SPI3 global Interrupt */ - [52] = isr_uart4, /* [52] UART4 global Interrupt */ - [53] = isr_uart5, /* [53] UART5 global Interrupt */ - [54] = isr_tim6_dac, /* [54] TIM6 global and DAC1&2 underrun error interrupts */ - [55] = isr_tim7, /* [55] TIM7 global interrupt */ - [61] = isr_dfsdm1_flt0, /* [61] DFSDM1 Filter 0 global Interrupt */ - [62] = isr_dfsdm1_flt1, /* [62] DFSDM1 Filter 1 global Interrupt */ - [63] = isr_can2_tx, /* [63] CAN2 TX Interrupt */ - [64] = isr_can2_rx0, /* [64] CAN2 RX0 Interrupt */ - [65] = isr_can2_rx1, /* [65] CAN2 RX1 Interrupt */ - [66] = isr_can2_sce, /* [66] CAN2 SCE Interrupt */ - [67] = isr_otg_fs, /* [67] USB OTG FS global Interrupt */ - [72] = isr_i2c3_ev, /* [72] I2C3 event interrupt */ - [73] = isr_i2c3_er, /* [73] I2C3 error interrupt */ - [74] = isr_can3_tx, /* [74] CAN3 TX Interrupt */ - [75] = isr_can3_rx0, /* [75] CAN3 RX0 Interrupt */ - [76] = isr_can3_rx1, /* [76] CAN3 RX1 Interrupt */ - [77] = isr_can3_sce, /* [77] CAN3 SCE Interrupt */ - [80] = isr_rng, /* [80] RNG global Interrupt */ - [82] = isr_uart7, /* [82] UART7 global interrupt */ - [83] = isr_uart8, /* [83] UART8 global interrupt */ - [84] = isr_spi4, /* [84] SPI4 global Interrupt */ - [85] = isr_spi5, /* [85] SPI5 global Interrupt */ - [87] = isr_sai1, /* [87] SAI1 global Interrupt */ - [88] = isr_uart9, /* [88] UART9 global Interrupt */ - [89] = isr_uart10, /* [89] UART10 global Interrupt */ - [92] = isr_quadspi, /* [92] QuadSPI global Interrupt */ - [95] = isr_fmpi2c1_ev, /* [95] FMPI2C1 Event Interrupt */ - [96] = isr_fmpi2c1_er, /* [96] FMPI2C1 Error Interrupt */ - [97] = isr_lptim1, /* [97] LP TIM1 interrupt */ - [98] = isr_dfsdm2_flt0, /* [98] DFSDM2 Filter 0 global Interrupt */ - [99] = isr_dfsdm2_flt1, /* [99] DFSDM2 Filter 1 global Interrupt */ - [100] = isr_dfsdm2_flt2, /* [100] DFSDM2 Filter 2 global Interrupt */ - [101] = isr_dfsdm2_flt3, /* [101] DFSDM2 Filter 3 global Interrupt */ -#elif defined(CPU_LINE_STM32F415xx) - [18] = isr_adc, /* [18] ADC1, ADC2 and ADC3 global Interrupts */ - [19] = isr_can1_tx, /* [19] CAN1 TX Interrupt */ - [20] = isr_can1_rx0, /* [20] CAN1 RX0 Interrupt */ - [21] = isr_can1_rx1, /* [21] CAN1 RX1 Interrupt */ - [22] = isr_can1_sce, /* [22] CAN1 SCE Interrupt */ - [25] = isr_tim1_up_tim10, /* [25] TIM1 Update Interrupt and TIM10 global interrupt */ - [28] = isr_tim2, /* [28] TIM2 global Interrupt */ - [29] = isr_tim3, /* [29] TIM3 global Interrupt */ - [30] = isr_tim4, /* [30] TIM4 global Interrupt */ - [39] = isr_usart3, /* [39] USART3 global Interrupt */ - [42] = isr_otg_fs_wkup, /* [42] USB OTG FS Wakeup through EXTI line interrupt */ - [43] = isr_tim8_brk_tim12, /* [43] TIM8 Break Interrupt and TIM12 global interrupt */ - [44] = isr_tim8_up_tim13, /* [44] TIM8 Update Interrupt and TIM13 global interrupt */ - [45] = isr_tim8_trg_com_tim14, /* [45] TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - [46] = isr_tim8_cc, /* [46] TIM8 Capture Compare global interrupt */ - [48] = isr_fsmc, /* [48] FSMC global Interrupt */ - [49] = isr_sdio, /* [49] SDIO global Interrupt */ - [51] = isr_spi3, /* [51] SPI3 global Interrupt */ - [52] = isr_uart4, /* [52] UART4 global Interrupt */ - [53] = isr_uart5, /* [53] UART5 global Interrupt */ - [54] = isr_tim6_dac, /* [54] TIM6 global and DAC1&2 underrun error interrupts */ - [55] = isr_tim7, /* [55] TIM7 global interrupt */ - [63] = isr_can2_tx, /* [63] CAN2 TX Interrupt */ - [64] = isr_can2_rx0, /* [64] CAN2 RX0 Interrupt */ - [65] = isr_can2_rx1, /* [65] CAN2 RX1 Interrupt */ - [66] = isr_can2_sce, /* [66] CAN2 SCE Interrupt */ - [67] = isr_otg_fs, /* [67] USB OTG FS global Interrupt */ - [72] = isr_i2c3_ev, /* [72] I2C3 event interrupt */ - [73] = isr_i2c3_er, /* [73] I2C3 error interrupt */ - [74] = isr_otg_hs_ep1_out, /* [74] USB OTG HS End Point 1 Out global interrupt */ - [75] = isr_otg_hs_ep1_in, /* [75] USB OTG HS End Point 1 In global interrupt */ - [76] = isr_otg_hs_wkup, /* [76] USB OTG HS Wakeup through EXTI interrupt */ - [77] = isr_otg_hs, /* [77] USB OTG HS global interrupt */ - [79] = isr_cryp, /* [79] CRYP crypto global interrupt */ - [80] = isr_hash_rng, /* [80] Hash and Rng global interrupt */ -#elif defined(CPU_LINE_STM32F423xx) - [18] = isr_adc, /* [18] ADC1, ADC2 and ADC3 global Interrupts */ - [19] = isr_can1_tx, /* [19] CAN1 TX Interrupt */ - [20] = isr_can1_rx0, /* [20] CAN1 RX0 Interrupt */ - [21] = isr_can1_rx1, /* [21] CAN1 RX1 Interrupt */ - [22] = isr_can1_sce, /* [22] CAN1 SCE Interrupt */ - [25] = isr_tim1_up_tim10, /* [25] TIM1 Update Interrupt and TIM10 global interrupt */ - [28] = isr_tim2, /* [28] TIM2 global Interrupt */ - [29] = isr_tim3, /* [29] TIM3 global Interrupt */ - [30] = isr_tim4, /* [30] TIM4 global Interrupt */ - [39] = isr_usart3, /* [39] USART3 global Interrupt */ - [42] = isr_otg_fs_wkup, /* [42] USB OTG FS Wakeup through EXTI line interrupt */ - [43] = isr_tim8_brk_tim12, /* [43] TIM8 Break Interrupt and TIM12 global interrupt */ - [44] = isr_tim8_up_tim13, /* [44] TIM8 Update Interrupt and TIM13 global interrupt */ - [45] = isr_tim8_trg_com_tim14, /* [45] TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - [46] = isr_tim8_cc, /* [46] TIM8 Capture Compare global interrupt */ - [49] = isr_sdio, /* [49] SDIO global Interrupt */ - [51] = isr_spi3, /* [51] SPI3 global Interrupt */ - [52] = isr_uart4, /* [52] UART4 global Interrupt */ - [53] = isr_uart5, /* [53] UART5 global Interrupt */ - [54] = isr_tim6_dac, /* [54] TIM6 global and DAC1&2 underrun error interrupts */ - [55] = isr_tim7, /* [55] TIM7 global interrupt */ - [61] = isr_dfsdm1_flt0, /* [61] DFSDM1 Filter 0 global Interrupt */ - [62] = isr_dfsdm1_flt1, /* [62] DFSDM1 Filter 1 global Interrupt */ - [63] = isr_can2_tx, /* [63] CAN2 TX Interrupt */ - [64] = isr_can2_rx0, /* [64] CAN2 RX0 Interrupt */ - [65] = isr_can2_rx1, /* [65] CAN2 RX1 Interrupt */ - [66] = isr_can2_sce, /* [66] CAN2 SCE Interrupt */ - [67] = isr_otg_fs, /* [67] USB OTG FS global Interrupt */ - [72] = isr_i2c3_ev, /* [72] I2C3 event interrupt */ - [73] = isr_i2c3_er, /* [73] I2C3 error interrupt */ - [74] = isr_can3_tx, /* [74] CAN3 TX Interrupt */ - [75] = isr_can3_rx0, /* [75] CAN3 RX0 Interrupt */ - [76] = isr_can3_rx1, /* [76] CAN3 RX1 Interrupt */ - [77] = isr_can3_sce, /* [77] CAN3 SCE Interrupt */ - [79] = isr_aes, /* [79] AES global Interrupt */ - [80] = isr_rng, /* [80] RNG global Interrupt */ - [82] = isr_uart7, /* [82] UART7 global interrupt */ - [83] = isr_uart8, /* [83] UART8 global interrupt */ - [84] = isr_spi4, /* [84] SPI4 global Interrupt */ - [85] = isr_spi5, /* [85] SPI5 global Interrupt */ - [87] = isr_sai1, /* [87] SAI1 global Interrupt */ - [88] = isr_uart9, /* [88] UART9 global Interrupt */ - [89] = isr_uart10, /* [89] UART10 global Interrupt */ - [92] = isr_quadspi, /* [92] QuadSPI global Interrupt */ - [95] = isr_fmpi2c1_ev, /* [95] FMPI2C1 Event Interrupt */ - [96] = isr_fmpi2c1_er, /* [96] FMPI2C1 Error Interrupt */ - [97] = isr_lptim1, /* [97] LP TIM1 interrupt */ - [98] = isr_dfsdm2_flt0, /* [98] DFSDM2 Filter 0 global Interrupt */ - [99] = isr_dfsdm2_flt1, /* [99] DFSDM2 Filter 1 global Interrupt */ - [100] = isr_dfsdm2_flt2, /* [100] DFSDM2 Filter 2 global Interrupt */ - [101] = isr_dfsdm2_flt3, /* [101] DFSDM2 Filter 3 global Interrupt */ -#elif defined(CPU_LINE_STM32F429xx) - [18] = isr_adc, /* [18] ADC1, ADC2 and ADC3 global Interrupts */ - [19] = isr_can1_tx, /* [19] CAN1 TX Interrupt */ - [20] = isr_can1_rx0, /* [20] CAN1 RX0 Interrupt */ - [21] = isr_can1_rx1, /* [21] CAN1 RX1 Interrupt */ - [22] = isr_can1_sce, /* [22] CAN1 SCE Interrupt */ - [25] = isr_tim1_up_tim10, /* [25] TIM1 Update Interrupt and TIM10 global interrupt */ - [28] = isr_tim2, /* [28] TIM2 global Interrupt */ - [29] = isr_tim3, /* [29] TIM3 global Interrupt */ - [30] = isr_tim4, /* [30] TIM4 global Interrupt */ - [39] = isr_usart3, /* [39] USART3 global Interrupt */ - [42] = isr_otg_fs_wkup, /* [42] USB OTG FS Wakeup through EXTI line interrupt */ - [43] = isr_tim8_brk_tim12, /* [43] TIM8 Break Interrupt and TIM12 global interrupt */ - [44] = isr_tim8_up_tim13, /* [44] TIM8 Update Interrupt and TIM13 global interrupt */ - [45] = isr_tim8_trg_com_tim14, /* [45] TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - [46] = isr_tim8_cc, /* [46] TIM8 Capture Compare global interrupt */ - [48] = isr_fmc, /* [48] FMC global Interrupt */ - [49] = isr_sdio, /* [49] SDIO global Interrupt */ - [51] = isr_spi3, /* [51] SPI3 global Interrupt */ - [52] = isr_uart4, /* [52] UART4 global Interrupt */ - [53] = isr_uart5, /* [53] UART5 global Interrupt */ - [54] = isr_tim6_dac, /* [54] TIM6 global and DAC1&2 underrun error interrupts */ - [55] = isr_tim7, /* [55] TIM7 global interrupt */ - [61] = isr_eth, /* [61] Ethernet global Interrupt */ - [62] = isr_eth_wkup, /* [62] Ethernet Wakeup through EXTI line Interrupt */ - [63] = isr_can2_tx, /* [63] CAN2 TX Interrupt */ - [64] = isr_can2_rx0, /* [64] CAN2 RX0 Interrupt */ - [65] = isr_can2_rx1, /* [65] CAN2 RX1 Interrupt */ - [66] = isr_can2_sce, /* [66] CAN2 SCE Interrupt */ - [67] = isr_otg_fs, /* [67] USB OTG FS global Interrupt */ - [72] = isr_i2c3_ev, /* [72] I2C3 event interrupt */ - [73] = isr_i2c3_er, /* [73] I2C3 error interrupt */ - [74] = isr_otg_hs_ep1_out, /* [74] USB OTG HS End Point 1 Out global interrupt */ - [75] = isr_otg_hs_ep1_in, /* [75] USB OTG HS End Point 1 In global interrupt */ - [76] = isr_otg_hs_wkup, /* [76] USB OTG HS Wakeup through EXTI interrupt */ - [77] = isr_otg_hs, /* [77] USB OTG HS global interrupt */ - [78] = isr_dcmi, /* [78] DCMI global interrupt */ - [82] = isr_uart7, /* [82] UART7 global interrupt */ - [83] = isr_uart8, /* [83] UART8 global interrupt */ - [84] = isr_spi4, /* [84] SPI4 global Interrupt */ - [85] = isr_spi5, /* [85] SPI5 global Interrupt */ - [86] = isr_spi6, /* [86] SPI6 global Interrupt */ - [87] = isr_sai1, /* [87] SAI1 global Interrupt */ - [88] = isr_ltdc, /* [88] LTDC global Interrupt */ - [89] = isr_ltdc_er, /* [89] LTDC Error global Interrupt */ - [90] = isr_dma2d, /* [90] DMA2D global Interrupt */ -#elif defined(CPU_LINE_STM32F437xx) - [18] = isr_adc, /* [18] ADC1, ADC2 and ADC3 global Interrupts */ - [19] = isr_can1_tx, /* [19] CAN1 TX Interrupt */ - [20] = isr_can1_rx0, /* [20] CAN1 RX0 Interrupt */ - [21] = isr_can1_rx1, /* [21] CAN1 RX1 Interrupt */ - [22] = isr_can1_sce, /* [22] CAN1 SCE Interrupt */ - [25] = isr_tim1_up_tim10, /* [25] TIM1 Update Interrupt and TIM10 global interrupt */ - [28] = isr_tim2, /* [28] TIM2 global Interrupt */ - [29] = isr_tim3, /* [29] TIM3 global Interrupt */ - [30] = isr_tim4, /* [30] TIM4 global Interrupt */ - [39] = isr_usart3, /* [39] USART3 global Interrupt */ - [42] = isr_otg_fs_wkup, /* [42] USB OTG FS Wakeup through EXTI line interrupt */ - [43] = isr_tim8_brk_tim12, /* [43] TIM8 Break Interrupt and TIM12 global interrupt */ - [44] = isr_tim8_up_tim13, /* [44] TIM8 Update Interrupt and TIM13 global interrupt */ - [45] = isr_tim8_trg_com_tim14, /* [45] TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - [46] = isr_tim8_cc, /* [46] TIM8 Capture Compare global interrupt */ - [48] = isr_fmc, /* [48] FMC global Interrupt */ - [49] = isr_sdio, /* [49] SDIO global Interrupt */ - [51] = isr_spi3, /* [51] SPI3 global Interrupt */ - [52] = isr_uart4, /* [52] UART4 global Interrupt */ - [53] = isr_uart5, /* [53] UART5 global Interrupt */ - [54] = isr_tim6_dac, /* [54] TIM6 global and DAC1&2 underrun error interrupts */ - [55] = isr_tim7, /* [55] TIM7 global interrupt */ - [61] = isr_eth, /* [61] Ethernet global Interrupt */ - [62] = isr_eth_wkup, /* [62] Ethernet Wakeup through EXTI line Interrupt */ - [63] = isr_can2_tx, /* [63] CAN2 TX Interrupt */ - [64] = isr_can2_rx0, /* [64] CAN2 RX0 Interrupt */ - [65] = isr_can2_rx1, /* [65] CAN2 RX1 Interrupt */ - [66] = isr_can2_sce, /* [66] CAN2 SCE Interrupt */ - [67] = isr_otg_fs, /* [67] USB OTG FS global Interrupt */ - [72] = isr_i2c3_ev, /* [72] I2C3 event interrupt */ - [73] = isr_i2c3_er, /* [73] I2C3 error interrupt */ - [74] = isr_otg_hs_ep1_out, /* [74] USB OTG HS End Point 1 Out global interrupt */ - [75] = isr_otg_hs_ep1_in, /* [75] USB OTG HS End Point 1 In global interrupt */ - [76] = isr_otg_hs_wkup, /* [76] USB OTG HS Wakeup through EXTI interrupt */ - [77] = isr_otg_hs, /* [77] USB OTG HS global interrupt */ - [78] = isr_dcmi, /* [78] DCMI global interrupt */ - [79] = isr_cryp, /* [79] CRYP crypto global interrupt */ - [80] = isr_hash_rng, /* [80] Hash and Rng global interrupt */ - [82] = isr_uart7, /* [82] UART7 global interrupt */ - [83] = isr_uart8, /* [83] UART8 global interrupt */ - [84] = isr_spi4, /* [84] SPI4 global Interrupt */ - [85] = isr_spi5, /* [85] SPI5 global Interrupt */ - [86] = isr_spi6, /* [86] SPI6 global Interrupt */ - [87] = isr_sai1, /* [87] SAI1 global Interrupt */ - [90] = isr_dma2d, /* [90] DMA2D global Interrupt */ -#elif defined(CPU_LINE_STM32F446xx) - [18] = isr_adc, /* [18] ADC1, ADC2 and ADC3 global Interrupts */ - [19] = isr_can1_tx, /* [19] CAN1 TX Interrupt */ - [20] = isr_can1_rx0, /* [20] CAN1 RX0 Interrupt */ - [21] = isr_can1_rx1, /* [21] CAN1 RX1 Interrupt */ - [22] = isr_can1_sce, /* [22] CAN1 SCE Interrupt */ - [25] = isr_tim1_up_tim10, /* [25] TIM1 Update Interrupt and TIM10 global interrupt */ - [28] = isr_tim2, /* [28] TIM2 global Interrupt */ - [29] = isr_tim3, /* [29] TIM3 global Interrupt */ - [30] = isr_tim4, /* [30] TIM4 global Interrupt */ - [39] = isr_usart3, /* [39] USART3 global Interrupt */ - [42] = isr_otg_fs_wkup, /* [42] USB OTG FS Wakeup through EXTI line interrupt */ - [43] = isr_tim8_brk_tim12, /* [43] TIM8 Break Interrupt and TIM12 global interrupt */ - [44] = isr_tim8_up_tim13, /* [44] TIM8 Update Interrupt and TIM13 global interrupt */ - [45] = isr_tim8_trg_com_tim14, /* [45] TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - [46] = isr_tim8_cc, /* [46] TIM8 Capture Compare global interrupt */ - [48] = isr_fmc, /* [48] FMC global Interrupt */ - [49] = isr_sdio, /* [49] SDIO global Interrupt */ - [51] = isr_spi3, /* [51] SPI3 global Interrupt */ - [52] = isr_uart4, /* [52] UART4 global Interrupt */ - [53] = isr_uart5, /* [53] UART5 global Interrupt */ - [54] = isr_tim6_dac, /* [54] TIM6 global and DAC1&2 underrun error interrupts */ - [55] = isr_tim7, /* [55] TIM7 global interrupt */ - [63] = isr_can2_tx, /* [63] CAN2 TX Interrupt */ - [64] = isr_can2_rx0, /* [64] CAN2 RX0 Interrupt */ - [65] = isr_can2_rx1, /* [65] CAN2 RX1 Interrupt */ - [66] = isr_can2_sce, /* [66] CAN2 SCE Interrupt */ - [67] = isr_otg_fs, /* [67] USB OTG FS global Interrupt */ - [72] = isr_i2c3_ev, /* [72] I2C3 event interrupt */ - [73] = isr_i2c3_er, /* [73] I2C3 error interrupt */ - [74] = isr_otg_hs_ep1_out, /* [74] USB OTG HS End Point 1 Out global interrupt */ - [75] = isr_otg_hs_ep1_in, /* [75] USB OTG HS End Point 1 In global interrupt */ - [76] = isr_otg_hs_wkup, /* [76] USB OTG HS Wakeup through EXTI interrupt */ - [77] = isr_otg_hs, /* [77] USB OTG HS global interrupt */ - [78] = isr_dcmi, /* [78] DCMI global interrupt */ - [84] = isr_spi4, /* [84] SPI4 global Interrupt */ - [87] = isr_sai1, /* [87] SAI1 global Interrupt */ - [91] = isr_sai2, /* [91] SAI2 global Interrupt */ - [92] = isr_quadspi, /* [92] QuadSPI global Interrupt */ - [93] = isr_cec, /* [93] CEC global Interrupt */ - [94] = isr_spdif_rx, /* [94] SPDIF-RX global Interrupt */ - [95] = isr_fmpi2c1_ev, /* [95] FMPI2C1 Event Interrupt */ - [96] = isr_fmpi2c1_er, /* [96] FMPI2C1 Error Interrupt */ -#endif -}; diff --git a/cpu/stm32/vectors/vectors_f7.c b/cpu/stm32/vectors/vectors_f7.c deleted file mode 100644 index 448dbc2575..0000000000 --- a/cpu/stm32/vectors/vectors_f7.c +++ /dev/null @@ -1,278 +0,0 @@ -/* - * Copyright (C) 2017 Freie Universität Berlin - * - * This file is subject to the terms and conditions of the GNU Lesser - * General Public License v2.1. See the file LICENSE in the top level - * directory for more details. - */ - -/** - * @ingroup cpu_stm32 - * @{ - * - * @file - * @brief Interrupt vector definitions for STM32F7 - * - * @author Hauke Petersen - * - * @} - */ - -#include "vectors_cortexm.h" - -/* define a local dummy handler as it needs to be in the same compilation unit - * as the alias definition */ -void dummy_handler(void) { - dummy_handler_default(); -} - -/* STM32F7 specific interrupt vectors */ -WEAK_DEFAULT void isr_adc(void); -WEAK_DEFAULT void isr_can1_rx0(void); -WEAK_DEFAULT void isr_can1_rx1(void); -WEAK_DEFAULT void isr_can1_sce(void); -WEAK_DEFAULT void isr_can1_tx(void); -WEAK_DEFAULT void isr_can2_rx0(void); -WEAK_DEFAULT void isr_can2_rx1(void); -WEAK_DEFAULT void isr_can2_sce(void); -WEAK_DEFAULT void isr_can2_tx(void); -WEAK_DEFAULT void isr_can3_rx0(void); -WEAK_DEFAULT void isr_can3_rx1(void); -WEAK_DEFAULT void isr_can3_sce(void); -WEAK_DEFAULT void isr_can3_tx(void); -WEAK_DEFAULT void isr_cec(void); -WEAK_DEFAULT void isr_dcmi(void); -WEAK_DEFAULT void isr_dma1_stream0(void); -WEAK_DEFAULT void isr_dma1_stream1(void); -WEAK_DEFAULT void isr_dma1_stream2(void); -WEAK_DEFAULT void isr_dma1_stream3(void); -WEAK_DEFAULT void isr_dma1_stream4(void); -WEAK_DEFAULT void isr_dma1_stream5(void); -WEAK_DEFAULT void isr_dma1_stream6(void); -WEAK_DEFAULT void isr_dma1_stream7(void); -WEAK_DEFAULT void isr_dma2_stream0(void); -WEAK_DEFAULT void isr_dma2_stream1(void); -WEAK_DEFAULT void isr_dma2_stream2(void); -WEAK_DEFAULT void isr_dma2_stream3(void); -WEAK_DEFAULT void isr_dma2_stream4(void); -WEAK_DEFAULT void isr_dma2_stream5(void); -WEAK_DEFAULT void isr_dma2_stream6(void); -WEAK_DEFAULT void isr_dma2_stream7(void); -WEAK_DEFAULT void isr_dma2d(void); -WEAK_DEFAULT void isr_dsi(void); -WEAK_DEFAULT void isr_eth(void); -WEAK_DEFAULT void isr_eth_wkup(void); -WEAK_DEFAULT void isr_exti(void); -WEAK_DEFAULT void isr_flash(void); -WEAK_DEFAULT void isr_fmc(void); -WEAK_DEFAULT void isr_fpu(void); -WEAK_DEFAULT void isr_i2c1_er(void); -WEAK_DEFAULT void isr_i2c1_ev(void); -WEAK_DEFAULT void isr_i2c2_er(void); -WEAK_DEFAULT void isr_i2c2_ev(void); -WEAK_DEFAULT void isr_i2c3_er(void); -WEAK_DEFAULT void isr_i2c3_ev(void); -WEAK_DEFAULT void isr_i2c4_er(void); -WEAK_DEFAULT void isr_i2c4_ev(void); -WEAK_DEFAULT void isr_jpeg(void); -WEAK_DEFAULT void isr_lptim1(void); -WEAK_DEFAULT void isr_ltdc(void); -WEAK_DEFAULT void isr_ltdc_er(void); -WEAK_DEFAULT void isr_mdios(void); -WEAK_DEFAULT void isr_otg_fs(void); -WEAK_DEFAULT void isr_otg_fs_wkup(void); -WEAK_DEFAULT void isr_otg_hs(void); -WEAK_DEFAULT void isr_otg_hs_ep1_in(void); -WEAK_DEFAULT void isr_otg_hs_ep1_out(void); -WEAK_DEFAULT void isr_otg_hs_wkup(void); -WEAK_DEFAULT void isr_pvd(void); -WEAK_DEFAULT void isr_quadspi(void); -WEAK_DEFAULT void isr_rcc(void); -WEAK_DEFAULT void isr_rng(void); -WEAK_DEFAULT void isr_rtc_alarm(void); -WEAK_DEFAULT void isr_rtc_wkup(void); -WEAK_DEFAULT void isr_sai1(void); -WEAK_DEFAULT void isr_sai2(void); -WEAK_DEFAULT void isr_sdmmc1(void); -WEAK_DEFAULT void isr_sdmmc2(void); -WEAK_DEFAULT void isr_spdif_rx(void); -WEAK_DEFAULT void isr_spi1(void); -WEAK_DEFAULT void isr_spi2(void); -WEAK_DEFAULT void isr_spi3(void); -WEAK_DEFAULT void isr_spi4(void); -WEAK_DEFAULT void isr_spi5(void); -WEAK_DEFAULT void isr_spi6(void); -WEAK_DEFAULT void isr_tamp_stamp(void); -WEAK_DEFAULT void isr_tim1_brk_tim9(void); -WEAK_DEFAULT void isr_tim1_cc(void); -WEAK_DEFAULT void isr_tim1_trg_com_tim11(void); -WEAK_DEFAULT void isr_tim1_up_tim10(void); -WEAK_DEFAULT void isr_tim2(void); -WEAK_DEFAULT void isr_tim3(void); -WEAK_DEFAULT void isr_tim4(void); -WEAK_DEFAULT void isr_tim5(void); -WEAK_DEFAULT void isr_tim6_dac(void); -WEAK_DEFAULT void isr_tim7(void); -WEAK_DEFAULT void isr_tim8_brk_tim12(void); -WEAK_DEFAULT void isr_tim8_cc(void); -WEAK_DEFAULT void isr_tim8_trg_com_tim14(void); -WEAK_DEFAULT void isr_tim8_up_tim13(void); -WEAK_DEFAULT void isr_uart4(void); -WEAK_DEFAULT void isr_uart5(void); -WEAK_DEFAULT void isr_uart7(void); -WEAK_DEFAULT void isr_uart8(void); -WEAK_DEFAULT void isr_usart1(void); -WEAK_DEFAULT void isr_usart2(void); -WEAK_DEFAULT void isr_usart3(void); -WEAK_DEFAULT void isr_usart6(void); -WEAK_DEFAULT void isr_wwdg(void); - -/* CPU specific interrupt vector table */ -ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = { - /* shared vectors for all family members */ - [ 0] = isr_wwdg, /* [ 0] Window WatchDog Interrupt */ - [ 1] = isr_pvd, /* [ 1] PVD through EXTI Line detection Interrupt */ - [ 2] = isr_tamp_stamp, /* [ 2] Tamper and TimeStamp interrupts through the EXTI line */ - [ 3] = isr_rtc_wkup, /* [ 3] RTC Wakeup interrupt through the EXTI line */ - [ 4] = isr_flash, /* [ 4] FLASH global Interrupt */ - [ 5] = isr_rcc, /* [ 5] RCC global Interrupt */ - [ 6] = isr_exti, /* [ 6] EXTI Line0 Interrupt */ - [ 7] = isr_exti, /* [ 7] EXTI Line1 Interrupt */ - [ 8] = isr_exti, /* [ 8] EXTI Line2 Interrupt */ - [ 9] = isr_exti, /* [ 9] EXTI Line3 Interrupt */ - [10] = isr_exti, /* [10] EXTI Line4 Interrupt */ - [11] = isr_dma1_stream0, /* [11] DMA1 Stream 0 global Interrupt */ - [12] = isr_dma1_stream1, /* [12] DMA1 Stream 1 global Interrupt */ - [13] = isr_dma1_stream2, /* [13] DMA1 Stream 2 global Interrupt */ - [14] = isr_dma1_stream3, /* [14] DMA1 Stream 3 global Interrupt */ - [15] = isr_dma1_stream4, /* [15] DMA1 Stream 4 global Interrupt */ - [16] = isr_dma1_stream5, /* [16] DMA1 Stream 5 global Interrupt */ - [17] = isr_dma1_stream6, /* [17] DMA1 Stream 6 global Interrupt */ - [18] = isr_adc, /* [18] ADC1, ADC2 and ADC3 global Interrupts */ - [19] = isr_can1_tx, /* [19] CAN1 TX Interrupt */ - [20] = isr_can1_rx0, /* [20] CAN1 RX0 Interrupt */ - [21] = isr_can1_rx1, /* [21] CAN1 RX1 Interrupt */ - [22] = isr_can1_sce, /* [22] CAN1 SCE Interrupt */ - [23] = isr_exti, /* [23] External Line[9:5] Interrupts */ - [24] = isr_tim1_brk_tim9, /* [24] TIM1 Break interrupt and TIM9 global interrupt */ - [25] = isr_tim1_up_tim10, /* [25] TIM1 Update Interrupt and TIM10 global interrupt */ - [26] = isr_tim1_trg_com_tim11, /* [26] TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - [27] = isr_tim1_cc, /* [27] TIM1 Capture Compare Interrupt */ - [28] = isr_tim2, /* [28] TIM2 global Interrupt */ - [29] = isr_tim3, /* [29] TIM3 global Interrupt */ - [30] = isr_tim4, /* [30] TIM4 global Interrupt */ - [31] = isr_i2c1_ev, /* [31] I2C1 Event Interrupt */ - [32] = isr_i2c1_er, /* [32] I2C1 Error Interrupt */ - [33] = isr_i2c2_ev, /* [33] I2C2 Event Interrupt */ - [34] = isr_i2c2_er, /* [34] I2C2 Error Interrupt */ - [35] = isr_spi1, /* [35] SPI1 global Interrupt */ - [36] = isr_spi2, /* [36] SPI2 global Interrupt */ - [37] = isr_usart1, /* [37] USART1 global Interrupt */ - [38] = isr_usart2, /* [38] USART2 global Interrupt */ - [39] = isr_usart3, /* [39] USART3 global Interrupt */ - [40] = isr_exti, /* [40] External Line[15:10] Interrupts */ - [41] = isr_rtc_alarm, /* [41] RTC Alarm (A and B) through EXTI Line Interrupt */ - [42] = isr_otg_fs_wkup, /* [42] USB OTG FS Wakeup through EXTI line interrupt */ - [43] = isr_tim8_brk_tim12, /* [43] TIM8 Break Interrupt and TIM12 global interrupt */ - [44] = isr_tim8_up_tim13, /* [44] TIM8 Update Interrupt and TIM13 global interrupt */ - [45] = isr_tim8_trg_com_tim14, /* [45] TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - [46] = isr_tim8_cc, /* [46] TIM8 Capture Compare Interrupt */ - [47] = isr_dma1_stream7, /* [47] DMA1 Stream7 Interrupt */ - [48] = isr_fmc, /* [48] FMC global Interrupt */ - [49] = isr_sdmmc1, /* [49] SDMMC1 global Interrupt */ - [50] = isr_tim5, /* [50] TIM5 global Interrupt */ - [51] = isr_spi3, /* [51] SPI3 global Interrupt */ - [52] = isr_uart4, /* [52] UART4 global Interrupt */ - [53] = isr_uart5, /* [53] UART5 global Interrupt */ - [54] = isr_tim6_dac, /* [54] TIM6 global and DAC1&2 underrun error interrupts */ - [55] = isr_tim7, /* [55] TIM7 global interrupt */ - [56] = isr_dma2_stream0, /* [56] DMA2 Stream 0 global Interrupt */ - [57] = isr_dma2_stream1, /* [57] DMA2 Stream 1 global Interrupt */ - [58] = isr_dma2_stream2, /* [58] DMA2 Stream 2 global Interrupt */ - [59] = isr_dma2_stream3, /* [59] DMA2 Stream 3 global Interrupt */ - [60] = isr_dma2_stream4, /* [60] DMA2 Stream 4 global Interrupt */ - [61] = isr_eth, /* [61] Ethernet global Interrupt */ - [62] = isr_eth_wkup, /* [62] Ethernet Wakeup through EXTI line Interrupt */ - [67] = isr_otg_fs, /* [67] USB OTG FS global Interrupt */ - [68] = isr_dma2_stream5, /* [68] DMA2 Stream 5 global interrupt */ - [69] = isr_dma2_stream6, /* [69] DMA2 Stream 6 global interrupt */ - [70] = isr_dma2_stream7, /* [70] DMA2 Stream 7 global interrupt */ - [71] = isr_usart6, /* [71] USART6 global interrupt */ - [72] = isr_i2c3_ev, /* [72] I2C3 event interrupt */ - [73] = isr_i2c3_er, /* [73] I2C3 error interrupt */ - [74] = isr_otg_hs_ep1_out, /* [74] USB OTG HS End Point 1 Out global interrupt */ - [75] = isr_otg_hs_ep1_in, /* [75] USB OTG HS End Point 1 In global interrupt */ - [76] = isr_otg_hs_wkup, /* [76] USB OTG HS Wakeup through EXTI interrupt */ - [77] = isr_otg_hs, /* [77] USB OTG HS global interrupt */ - [80] = isr_rng, /* [80] RNG global interrupt */ - [81] = isr_fpu, /* [81] FPU global interrupt */ - [82] = isr_uart7, /* [82] UART7 global interrupt */ - [83] = isr_uart8, /* [83] UART8 global interrupt */ - [84] = isr_spi4, /* [84] SPI4 global Interrupt */ - [85] = isr_spi5, /* [85] SPI5 global Interrupt */ - [87] = isr_sai1, /* [87] SAI1 global Interrupt */ - [91] = isr_sai2, /* [91] SAI2 global Interrupt */ - [92] = isr_quadspi, /* [92] Quad SPI global interrupt */ - [93] = isr_lptim1, /* [93] LP TIM1 interrupt */ - -#if defined(CPU_LINE_STM32F746xx) - [63] = isr_can2_tx, /* [63] CAN2 TX Interrupt */ - [64] = isr_can2_rx0, /* [64] CAN2 RX0 Interrupt */ - [65] = isr_can2_rx1, /* [65] CAN2 RX1 Interrupt */ - [66] = isr_can2_sce, /* [66] CAN2 SCE Interrupt */ - [78] = isr_dcmi, /* [78] DCMI global interrupt */ - [86] = isr_spi6, /* [86] SPI6 global Interrupt */ - [88] = isr_ltdc, /* [88] LTDC global Interrupt */ - [89] = isr_ltdc_er, /* [89] LTDC Error global Interrupt */ - [90] = isr_dma2d, /* [90] DMA2D global Interrupt */ - [94] = isr_cec, /* [94] HDMI-CEC global Interrupt */ - [95] = isr_i2c4_ev, /* [95] I2C4 Event Interrupt */ - [96] = isr_i2c4_er, /* [96] I2C4 Error Interrupt */ - [97] = isr_spdif_rx, /* [97] SPDIF-RX global Interrupt */ -#elif defined(CPU_LINE_STM32F767xx) - [63] = isr_can2_tx, /* [63] CAN2 TX Interrupt */ - [64] = isr_can2_rx0, /* [64] CAN2 RX0 Interrupt */ - [65] = isr_can2_rx1, /* [65] CAN2 RX1 Interrupt */ - [66] = isr_can2_sce, /* [66] CAN2 SCE Interrupt */ - [78] = isr_dcmi, /* [78] DCMI global interrupt */ - [86] = isr_spi6, /* [86] SPI6 global Interrupt */ - [88] = isr_ltdc, /* [88] LTDC global Interrupt */ - [89] = isr_ltdc_er, /* [89] LTDC Error global Interrupt */ - [90] = isr_dma2d, /* [90] DMA2D global Interrupt */ - [94] = isr_cec, /* [94] HDMI-CEC global Interrupt */ - [95] = isr_i2c4_ev, /* [95] I2C4 Event Interrupt */ - [96] = isr_i2c4_er, /* [96] I2C4 Error Interrupt */ - [97] = isr_spdif_rx, /* [97] SPDIF-RX global Interrupt */ - [103] = isr_sdmmc2, /* [103] SDMMC2 global Interrupt */ - [104] = isr_can3_tx, /* [104] CAN3 TX Interrupt */ - [105] = isr_can3_rx0, /* [105] CAN3 RX0 Interrupt */ - [106] = isr_can3_rx1, /* [106] CAN3 RX1 Interrupt */ - [107] = isr_can3_sce, /* [107] CAN3 SCE Interrupt */ - [108] = isr_jpeg, /* [108] JPEG global Interrupt */ - [109] = isr_mdios, /* [109] MDIO Slave global Interrupt */ -#elif defined(CPU_LINE_STM32F769xx) - [63] = isr_can2_tx, /* [63] CAN2 TX Interrupt */ - [64] = isr_can2_rx0, /* [64] CAN2 RX0 Interrupt */ - [65] = isr_can2_rx1, /* [65] CAN2 RX1 Interrupt */ - [66] = isr_can2_sce, /* [66] CAN2 SCE Interrupt */ - [78] = isr_dcmi, /* [78] DCMI global interrupt */ - [86] = isr_spi6, /* [86] SPI6 global Interrupt */ - [88] = isr_ltdc, /* [88] LTDC global Interrupt */ - [89] = isr_ltdc_er, /* [89] LTDC Error global Interrupt */ - [90] = isr_dma2d, /* [90] DMA2D global Interrupt */ - [94] = isr_cec, /* [94] HDMI-CEC global Interrupt */ - [95] = isr_i2c4_ev, /* [95] I2C4 Event Interrupt */ - [96] = isr_i2c4_er, /* [96] I2C4 Error Interrupt */ - [97] = isr_spdif_rx, /* [97] SPDIF-RX global Interrupt */ - [98] = isr_dsi, /* [98] DSI global Interrupt */ - [103] = isr_sdmmc2, /* [103] SDMMC2 global Interrupt */ - [104] = isr_can3_tx, /* [104] CAN3 TX Interrupt */ - [105] = isr_can3_rx0, /* [105] CAN3 RX0 Interrupt */ - [106] = isr_can3_rx1, /* [106] CAN3 RX1 Interrupt */ - [107] = isr_can3_sce, /* [107] CAN3 SCE Interrupt */ - [108] = isr_jpeg, /* [108] JPEG global Interrupt */ - [109] = isr_mdios, /* [109] MDIO Slave global Interrupt */ -#elif defined(CPU_LINE_STM32F723xx) - [103] = isr_sdmmc2, /* [103] SDMMC2 global Interrupt */ -#endif -}; diff --git a/cpu/stm32/vectors/vectors_g0.c b/cpu/stm32/vectors/vectors_g0.c deleted file mode 100644 index 6560898fd8..0000000000 --- a/cpu/stm32/vectors/vectors_g0.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (C) 2020 Inria - * - * This file is subject to the terms and conditions of the GNU Lesser General - * Public License v2.1. See the file LICENSE in the top level directory for more - * details. - */ - -/** - * @ingroup cpu_stm32 - * @{ - * - * @file - * @brief Interrupt vector definitions for STM32G0 - * - * @author Alexandre Abadie - * - * @} - */ - -#include "vectors_cortexm.h" - -/* define a local dummy handler as it needs to be in the same compilation unit - * as the alias definition */ -void dummy_handler(void) { - dummy_handler_default(); -} - -/* STM32G0 specific interrupt vectors */ -WEAK_DEFAULT void isr_adc1(void); -WEAK_DEFAULT void isr_dma1_channel1(void); -WEAK_DEFAULT void isr_dma1_channel2_3(void); -WEAK_DEFAULT void isr_dma1_ch4_7_dmamux1_ovr(void); -WEAK_DEFAULT void isr_exti(void); -WEAK_DEFAULT void isr_flash(void); -WEAK_DEFAULT void isr_i2c1(void); -WEAK_DEFAULT void isr_i2c2(void); -WEAK_DEFAULT void isr_rcc(void); -WEAK_DEFAULT void isr_rtc_tamp(void); -WEAK_DEFAULT void isr_spi1(void); -WEAK_DEFAULT void isr_spi2(void); -WEAK_DEFAULT void isr_tim1_brk_up_trg_com(void); -WEAK_DEFAULT void isr_tim1_cc(void); -WEAK_DEFAULT void isr_tim3(void); -WEAK_DEFAULT void isr_tim6(void); -WEAK_DEFAULT void isr_tim7(void); -WEAK_DEFAULT void isr_tim14(void); -WEAK_DEFAULT void isr_tim15(void); -WEAK_DEFAULT void isr_tim16(void); -WEAK_DEFAULT void isr_tim17(void); -WEAK_DEFAULT void isr_usart1(void); -WEAK_DEFAULT void isr_usart2(void); -WEAK_DEFAULT void isr_usart3_4(void); -WEAK_DEFAULT void isr_wwdg(void); - -/* CPU specific interrupt vector table */ -ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = { - /* shared vectors for all family members */ - [WWDG_IRQn ] = isr_wwdg, /* [ 0] Window WatchDog Interrupt */ - [RTC_TAMP_IRQn ] = isr_rtc_tamp, /* [ 2] RTC interrupt through the EXTI line 19 & 21 */ - [FLASH_IRQn ] = isr_flash, /* [ 3] FLASH global Interrupt */ - [RCC_IRQn ] = isr_rcc, /* [ 4] RCC global Interrupt */ - [EXTI0_1_IRQn ] = isr_exti, /* [ 5] EXTI 0 and 1 Interrupts */ - [EXTI2_3_IRQn ] = isr_exti, /* [ 6] EXTI 2 and 3 Interrupts */ - [EXTI4_15_IRQn ] = isr_exti, /* [ 7] EXTI 4 to 15 Interrupts */ - [DMA1_Channel1_IRQn ] = isr_dma1_channel1, /* [ 9] DMA1 Channel 1 Interrupt */ - [DMA1_Channel2_3_IRQn ] = isr_dma1_channel2_3, /* [10] DMA1 Channel 2 and Channel 3 Interrupts */ - [DMA1_Ch4_7_DMAMUX1_OVR_IRQn ] = isr_dma1_ch4_7_dmamux1_ovr, /* [11] DMA1 Channel 4 to Channel 7 and DMAMUX1 Overrun Interrupts */ - [ADC1_IRQn ] = isr_adc1, /* [12] ADC1 Interrupts */ - [TIM1_BRK_UP_TRG_COM_IRQn ] = isr_tim1_brk_up_trg_com, /* [13] TIM1 Break, Update, Trigger and Commutation Interrupts */ - [TIM1_CC_IRQn ] = isr_tim1_cc, /* [14] TIM1 Capture Compare Interrupt */ - [TIM3_IRQn ] = isr_tim3, /* [16] TIM3 global Interrupt */ - [TIM6_IRQn ] = isr_tim6, /* [17] TIM6 global Interrupts */ - [TIM7_IRQn ] = isr_tim7, /* [18] TIM7 global Interrupt */ - [TIM14_IRQn ] = isr_tim14, /* [19] TIM14 global Interrupt */ - [TIM15_IRQn ] = isr_tim15, /* [20] TIM15 global Interrupt */ - [TIM16_IRQn ] = isr_tim16, /* [21] TIM16 global Interrupt */ - [TIM17_IRQn ] = isr_tim17, /* [22] TIM17 global Interrupt */ - [I2C1_IRQn ] = isr_i2c1, /* [23] I2C1 Interrupt (combined with EXTI 23) */ - [I2C2_IRQn ] = isr_i2c2, /* [24] I2C2 Interrupt */ - [SPI1_IRQn ] = isr_spi1, /* [25] SPI1/I2S1 Interrupt */ - [SPI2_IRQn ] = isr_spi2, /* [26] SPI2 Interrupt */ - [USART1_IRQn ] = isr_usart1, /* [27] USART1 Interrupt */ - [USART2_IRQn ] = isr_usart2, /* [28] USART2 Interrupt */ - [USART3_4_IRQn ] = isr_usart3_4, /* [29] USART3, USART4 globlal Interrupts */ -}; diff --git a/cpu/stm32/vectors/vectors_g4.c b/cpu/stm32/vectors/vectors_g4.c deleted file mode 100644 index 5f0a31b6ef..0000000000 --- a/cpu/stm32/vectors/vectors_g4.c +++ /dev/null @@ -1,257 +0,0 @@ -/* - * Copyright (C) 2020 - * - * This file is subject to the terms and conditions of the GNU Lesser - * General Public License v2.1. See the file LICENSE in the top level - * directory for more details. - */ - -/** - * @ingroup cpu_stm32 - * @{ - * - * @file - * @brief Interrupt vector definitions for STM32G4 - * - * @author Alexandre Abadie - * - * @} - */ - -#include "vectors_cortexm.h" - -/* define a local dummy handler as it needs to be in the same compilation unit - * as the alias definition */ -void dummy_handler(void) { - dummy_handler_default(); -} - -/* STM32L4 specific interrupt vectors */ -WEAK_DEFAULT void isr_adc1(void); -WEAK_DEFAULT void isr_adc1_2(void); -WEAK_DEFAULT void isr_adc3(void); -WEAK_DEFAULT void isr_adc4(void); -WEAK_DEFAULT void isr_adc5(void); -WEAK_DEFAULT void isr_can1_rx0(void); -WEAK_DEFAULT void isr_can1_rx1(void); -WEAK_DEFAULT void isr_can1_sce(void); -WEAK_DEFAULT void isr_can1_tx(void); -WEAK_DEFAULT void isr_can2_rx0(void); -WEAK_DEFAULT void isr_can2_rx1(void); -WEAK_DEFAULT void isr_can2_sce(void); -WEAK_DEFAULT void isr_can2_tx(void); -WEAK_DEFAULT void isr_comp1_2_3(void); -WEAK_DEFAULT void isr_comp4_5_6(void); -WEAK_DEFAULT void isr_comp7(void); -WEAK_DEFAULT void isr_cordic(void); -WEAK_DEFAULT void isr_crs(void); -WEAK_DEFAULT void isr_dcmi(void); -WEAK_DEFAULT void isr_dfsdm1_flt0(void); -WEAK_DEFAULT void isr_dfsdm1_flt1(void); -WEAK_DEFAULT void isr_dfsdm1_flt2(void); -WEAK_DEFAULT void isr_dfsdm1_flt3(void); -WEAK_DEFAULT void isr_dmamux(void); -WEAK_DEFAULT void isr_dma1_channel1(void); -WEAK_DEFAULT void isr_dma1_channel2(void); -WEAK_DEFAULT void isr_dma1_channel3(void); -WEAK_DEFAULT void isr_dma1_channel4(void); -WEAK_DEFAULT void isr_dma1_channel5(void); -WEAK_DEFAULT void isr_dma1_channel6(void); -WEAK_DEFAULT void isr_dma1_channel7(void); -WEAK_DEFAULT void isr_dma1_channel8(void); -WEAK_DEFAULT void isr_dma2_channel1(void); -WEAK_DEFAULT void isr_dma2_channel2(void); -WEAK_DEFAULT void isr_dma2_channel3(void); -WEAK_DEFAULT void isr_dma2_channel4(void); -WEAK_DEFAULT void isr_dma2_channel5(void); -WEAK_DEFAULT void isr_dma2_channel6(void); -WEAK_DEFAULT void isr_dma2_channel7(void); -WEAK_DEFAULT void isr_dma2_channel8(void); -WEAK_DEFAULT void isr_dma2d(void); -WEAK_DEFAULT void isr_dmamux1_ovr(void); -WEAK_DEFAULT void isr_exti(void); -WEAK_DEFAULT void isr_fdcan1_it0(void); -WEAK_DEFAULT void isr_fdcan1_it1(void); -WEAK_DEFAULT void isr_fdcan2_it0(void); -WEAK_DEFAULT void isr_fdcan2_it1(void); -WEAK_DEFAULT void isr_fdcan3_it0(void); -WEAK_DEFAULT void isr_fdcan3_it1(void); -WEAK_DEFAULT void isr_flash(void); -WEAK_DEFAULT void isr_fmc(void); -WEAK_DEFAULT void isr_fmac(void); -WEAK_DEFAULT void isr_fpu(void); -WEAK_DEFAULT void isr_hrtim1_flt(void); -WEAK_DEFAULT void isr_hrtim1_master(void); -WEAK_DEFAULT void isr_hrtim1_tima(void); -WEAK_DEFAULT void isr_hrtim1_timb(void); -WEAK_DEFAULT void isr_hrtim1_timc(void); -WEAK_DEFAULT void isr_hrtim1_timd(void); -WEAK_DEFAULT void isr_hrtim1_time(void); -WEAK_DEFAULT void isr_hrtim1_timf(void); -WEAK_DEFAULT void isr_i2c1_er(void); -WEAK_DEFAULT void isr_i2c1_ev(void); -WEAK_DEFAULT void isr_i2c2_er(void); -WEAK_DEFAULT void isr_i2c2_ev(void); -WEAK_DEFAULT void isr_i2c3_er(void); -WEAK_DEFAULT void isr_i2c3_ev(void); -WEAK_DEFAULT void isr_i2c4_ev(void); -WEAK_DEFAULT void isr_i2c4_er(void); -WEAK_DEFAULT void isr_lcd(void); -WEAK_DEFAULT void isr_lptim1(void); -WEAK_DEFAULT void isr_lptim2(void); -WEAK_DEFAULT void isr_lpuart1(void); -WEAK_DEFAULT void isr_octospi1(void); -WEAK_DEFAULT void isr_octospi2(void); -WEAK_DEFAULT void isr_otg_fs(void); -WEAK_DEFAULT void isr_pvd_pvm(void); -WEAK_DEFAULT void isr_quadspi(void); -WEAK_DEFAULT void isr_rcc(void); -WEAK_DEFAULT void isr_rng(void); -WEAK_DEFAULT void isr_rtc_alarm(void); -WEAK_DEFAULT void isr_rtc_tamp_lsecss(void); -WEAK_DEFAULT void isr_rtc_wkup(void); -WEAK_DEFAULT void isr_sai1(void); -WEAK_DEFAULT void isr_sai2(void); -WEAK_DEFAULT void isr_sdmmc1(void); -WEAK_DEFAULT void isr_spi1(void); -WEAK_DEFAULT void isr_spi2(void); -WEAK_DEFAULT void isr_spi3(void); -WEAK_DEFAULT void isr_spi4(void); -WEAK_DEFAULT void isr_swpmi1(void); -WEAK_DEFAULT void isr_tim1_brk_tim15(void); -WEAK_DEFAULT void isr_tim1_cc(void); -WEAK_DEFAULT void isr_tim1_trg_com(void); -WEAK_DEFAULT void isr_tim1_trg_com_tim17(void); -WEAK_DEFAULT void isr_tim1_up_tim16(void); -WEAK_DEFAULT void isr_tim2(void); -WEAK_DEFAULT void isr_tim3(void); -WEAK_DEFAULT void isr_tim4(void); -WEAK_DEFAULT void isr_tim5(void); -WEAK_DEFAULT void isr_tim6_dac(void); -WEAK_DEFAULT void isr_tim7_dac(void); -WEAK_DEFAULT void isr_tim8_brk(void); -WEAK_DEFAULT void isr_tim8_cc(void); -WEAK_DEFAULT void isr_tim8_trg_com(void); -WEAK_DEFAULT void isr_tim8_up(void); -WEAK_DEFAULT void isr_tim20_brk(void); -WEAK_DEFAULT void isr_tim20_up(void); -WEAK_DEFAULT void isr_tim20_trg_com(void); -WEAK_DEFAULT void isr_tim20_cc(void); -WEAK_DEFAULT void isr_tsc(void); -WEAK_DEFAULT void isr_uart4(void); -WEAK_DEFAULT void isr_uart5(void); -WEAK_DEFAULT void isr_ucpd1(void); -WEAK_DEFAULT void isr_usart1(void); -WEAK_DEFAULT void isr_usart2(void); -WEAK_DEFAULT void isr_usart3(void); -WEAK_DEFAULT void isr_usb(void); -WEAK_DEFAULT void isr_usb_hp(void); -WEAK_DEFAULT void isr_usb_lp(void); -WEAK_DEFAULT void isr_usbwakeup(void); -WEAK_DEFAULT void isr_wwdg(void); - -/* CPU specific interrupt vector table */ -ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = { - /* shared vectors for all family members */ - [WWDG_IRQn ] = isr_wwdg, /* [ 0] Window WatchDog Interrupt */ - [PVD_PVM_IRQn ] = isr_pvd_pvm, /* [ 1] PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ - [RTC_TAMP_LSECSS_IRQn ] = isr_rtc_tamp_lsecss, /* [ 2] RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */ - [RTC_WKUP_IRQn ] = isr_rtc_wkup, /* [ 3] RTC Wakeup interrupt through the EXTI line */ - [FLASH_IRQn ] = isr_flash, /* [ 4] FLASH global Interrupt */ - [RCC_IRQn ] = isr_rcc, /* [ 5] RCC global Interrupt */ - [EXTI0_IRQn ] = isr_exti, /* [ 6] EXTI Line0 Interrupt */ - [EXTI1_IRQn ] = isr_exti, /* [ 7] EXTI Line1 Interrupt */ - [EXTI2_IRQn ] = isr_exti, /* [ 8] EXTI Line2 Interrupt */ - [EXTI3_IRQn ] = isr_exti, /* [ 9] EXTI Line3 Interrupt */ - [EXTI4_IRQn ] = isr_exti, /* [10] EXTI Line4 Interrupt */ - [DMA1_Channel1_IRQn ] = isr_dma1_channel1, /* [11] DMA1 Channel 1 global Interrupt */ - [DMA1_Channel2_IRQn ] = isr_dma1_channel2, /* [12] DMA1 Channel 2 global Interrupt */ - [DMA1_Channel3_IRQn ] = isr_dma1_channel3, /* [13] DMA1 Channel 3 global Interrupt */ - [DMA1_Channel4_IRQn ] = isr_dma1_channel4, /* [14] DMA1 Channel 4 global Interrupt */ - [DMA1_Channel5_IRQn ] = isr_dma1_channel5, /* [15] DMA1 Channel 5 global Interrupt */ - [DMA1_Channel6_IRQn ] = isr_dma1_channel6, /* [16] DMA1 Channel 6 global Interrupt */ - [DMA1_Channel7_IRQn ] = isr_dma1_channel7, /* [17] DMA1 Channel 7 global Interrupt */ - [ADC1_2_IRQn ] = isr_adc1_2, /* [18] ADC1, ADC2 SAR global Interrupts */ - [USB_HP_IRQn ] = isr_usb_hp, /* [19] USB HP Interrupt */ - [USB_LP_IRQn ] = isr_usb_lp, /* [20] USB LP Interrupt */ - [FDCAN1_IT0_IRQn ] = isr_fdcan1_it0, /* [21] FDCAN1 IT0 Interrupt */ - [FDCAN1_IT1_IRQn ] = isr_fdcan1_it1, /* [22] FDCAN1 IT1 Interrupt */ - [EXTI9_5_IRQn ] = isr_exti, /* [23] External Line[9:5] Interrupts */ - [TIM1_BRK_TIM15_IRQn ] = isr_tim1_brk_tim15, /* [24] TIM1 Break interrupt and TIM15 global interrupt */ - [TIM1_UP_TIM16_IRQn ] = isr_tim1_up_tim16, /* [25] TIM1 Update Interrupt and TIM16 global interrupt */ - [TIM1_TRG_COM_TIM17_IRQn ] = isr_tim1_trg_com_tim17, /* [26] TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */ - [TIM1_CC_IRQn ] = isr_tim1_cc, /* [27] TIM1 Capture Compare Interrupt */ - [TIM2_IRQn ] = isr_tim2, /* [28] TIM2 global Interrupt */ - [TIM3_IRQn ] = isr_tim3, /* [29] TIM3 global Interrupt */ - [TIM4_IRQn ] = isr_tim4, /* [30] TIM4 global Interrupt */ - [I2C1_EV_IRQn ] = isr_i2c1_ev, /* [31] I2C1 Event Interrupt */ - [I2C1_ER_IRQn ] = isr_i2c1_er, /* [32] I2C1 Error Interrupt */ - [I2C2_EV_IRQn ] = isr_i2c2_ev, /* [33] I2C2 Event Interrupt */ - [I2C2_ER_IRQn ] = isr_i2c2_er, /* [34] I2C2 Error Interrupt */ - [SPI1_IRQn ] = isr_spi1, /* [35] SPI1 global Interrupt */ - [SPI2_IRQn ] = isr_spi2, /* [36] SPI2 global Interrupt */ - [USART1_IRQn ] = isr_usart1, /* [37] USART1 global Interrupt */ - [USART2_IRQn ] = isr_usart2, /* [38] USART2 global Interrupt */ - [USART3_IRQn ] = isr_usart3, /* [39] USART3 global Interrupt */ - [EXTI15_10_IRQn ] = isr_exti, /* [40] External Line[15:10] Interrupts */ - [RTC_Alarm_IRQn ] = isr_rtc_alarm, /* [41] RTC Alarm (A and B) through EXTI Line Interrupt */ - [USBWakeUp_IRQn ] = isr_usbwakeup, /* [42] USB Wakeup through EXTI line Interrupt */ - [TIM8_BRK_IRQn ] = isr_tim8_brk, /* [43] TIM8 Break Interrupt */ - [TIM8_UP_IRQn ] = isr_tim8_up, /* [44] TIM8 Update Interrupt */ - [TIM8_TRG_COM_IRQn ] = isr_tim8_trg_com, /* [45] TIM8 Trigger and Commutation Interrupt */ - [TIM8_CC_IRQn ] = isr_tim8_cc, /* [46] TIM8 Capture Compare Interrupt */ - [ADC3_IRQn ] = isr_adc3, /* [47] ADC3 global Interrupt */ - [FMC_IRQn ] = isr_fmc, /* [48] FMC global Interrupt */ - [LPTIM1_IRQn ] = isr_lptim1, /* [49] LP TIM1 Interrupt */ - [TIM5_IRQn ] = isr_tim5, /* [50] TIM5 global Interrupt */ - [SPI3_IRQn ] = isr_spi3, /* [51] SPI3 global Interrupt */ - [UART4_IRQn ] = isr_uart4, /* [52] UART4 global Interrupt */ - [UART5_IRQn ] = isr_uart5, /* [53] UART5 global Interrupt */ - [TIM6_DAC_IRQn ] = isr_tim6_dac, /* [54] TIM6 global and DAC1&3 underrun error interrupts */ - [TIM7_DAC_IRQn ] = isr_tim7_dac, /* [55] TIM7 global and DAC2&4 underrun error interrupts */ - [DMA2_Channel1_IRQn ] = isr_dma2_channel1, /* [56] DMA2 Channel 1 global Interrupt */ - [DMA2_Channel2_IRQn ] = isr_dma2_channel2, /* [57] DMA2 Channel 2 global Interrupt */ - [DMA2_Channel3_IRQn ] = isr_dma2_channel3, /* [58] DMA2 Channel 3 global Interrupt */ - [DMA2_Channel4_IRQn ] = isr_dma2_channel4, /* [59] DMA2 Channel 4 global Interrupt */ - [DMA2_Channel5_IRQn ] = isr_dma2_channel5, /* [60] DMA2 Channel 5 global Interrupt */ - [ADC4_IRQn ] = isr_adc4, /* [61] ADC4 global Interrupt */ - [ADC5_IRQn ] = isr_adc5, /* [62] ADC5 global Interrupt */ - [UCPD1_IRQn ] = isr_ucpd1, /* [63] UCPD global Interrupt */ - [COMP1_2_3_IRQn ] = isr_comp1_2_3, /* [64] COMP1, COMP2 and COMP3 Interrupt */ - [COMP4_5_6_IRQn ] = isr_comp4_5_6, /* [65] COMP4, COMP5 and Interrupt */ - [COMP7_IRQn ] = isr_comp7, /* [66] COMP7 Interrupt */ - [HRTIM1_Master_IRQn ] = isr_hrtim1_master, /* [67] HRTIM Master Timer global Interrupt */ - [HRTIM1_TIMA_IRQn ] = isr_hrtim1_tima, /* [68] HRTIM Timer A global Interrupt */ - [HRTIM1_TIMB_IRQn ] = isr_hrtim1_timb, /* [69] HRTIM Timer B global Interrupt */ - [HRTIM1_TIMC_IRQn ] = isr_hrtim1_timc, /* [70] HRTIM Timer C global Interrupt */ - [HRTIM1_TIMD_IRQn ] = isr_hrtim1_timd, /* [71] HRTIM Timer D global Interrupt */ - [HRTIM1_TIME_IRQn ] = isr_hrtim1_time, /* [72] HRTIM Timer E global Interrupt */ - [HRTIM1_FLT_IRQn ] = isr_hrtim1_flt, /* [73] HRTIM Fault global Interrupt */ - [HRTIM1_TIMF_IRQn ] = isr_hrtim1_timf, /* [74] HRTIM Timer F global Interrupt */ - [CRS_IRQn ] = isr_crs, /* [75] CRS global Interrupt */ - [SAI1_IRQn ] = isr_sai1, /* [76] Serial Audio Interface global Interrupt */ - [TIM20_BRK_IRQn ] = isr_tim20_brk, /* [77] TIM20 Break, Transition error and Index error Interrupt */ - [TIM20_UP_IRQn ] = isr_tim20_up, /* [78] TIM20 Update Interrupt */ - [TIM20_TRG_COM_IRQn ] = isr_tim20_trg_com, /* [79] TIM20 Trigger, Commutation, Direction change and Index Interrupt */ - [TIM20_CC_IRQn ] = isr_tim20_cc, /* [80] TIM20 Capture Compare Interrupt */ - [FPU_IRQn ] = isr_fpu, /* [81] FPU global Interrupt */ - [I2C4_EV_IRQn ] = isr_i2c4_ev, /* [82] I2C4 Event Interrupt */ - [I2C4_ER_IRQn ] = isr_i2c4_er, /* [83] I2C4 Error Interrupt */ - [SPI4_IRQn ] = isr_spi4, /* [84] SPI4 Event Interrupt */ - [FDCAN2_IT0_IRQn ] = isr_fdcan2_it0, /* [86] FDCAN2 interrupt line 0 Interrupt */ - [FDCAN2_IT1_IRQn ] = isr_fdcan2_it1, /* [87] FDCAN2 interrupt line 1 Interrupt */ - [FDCAN3_IT0_IRQn ] = isr_fdcan3_it0, /* [88] FDCAN3 interrupt line 0 Interrupt */ - [FDCAN3_IT1_IRQn ] = isr_fdcan3_it1, /* [89] FDCAN3 interrupt line 1 Interrupt */ - [RNG_IRQn ] = isr_rng, /* [90] RNG global Interrupt */ - [LPUART1_IRQn ] = isr_lpuart1, /* [91] LP UART 1 Interrupt */ - [I2C3_EV_IRQn ] = isr_i2c3_ev, /* [92] I2C3 Event Interrupt */ - [I2C3_ER_IRQn ] = isr_i2c3_er, /* [93] I2C3 Error Interrupt */ - [DMAMUX_OVR_IRQn ] = isr_dmamux, /* [94] DMAMUX overrun global Interrupt */ - [QUADSPI_IRQn ] = isr_quadspi, /* [95] QUADSPI Interrupt */ - [DMA1_Channel8_IRQn ] = isr_dma1_channel8, /* [96] DMA1 Channel 8 Interrupt */ - [DMA2_Channel6_IRQn ] = isr_dma2_channel6, /* [97] DMA2 Channel 6 Interrupt */ - [DMA2_Channel7_IRQn ] = isr_dma2_channel7, /* [98] DMA2 Channel 7 Interrupt */ - [DMA2_Channel8_IRQn ] = isr_dma2_channel8, /* [99] DMA2 Channel 8 Interrupt */ - [CORDIC_IRQn ] = isr_cordic, /* [100] CORDIC global Interrupt */ - [FMAC_IRQn ] = isr_fmac, /* [101] FMAC global Interrupt */ -}; diff --git a/cpu/stm32/vectors/vectors_l0.c b/cpu/stm32/vectors/vectors_l0.c deleted file mode 100644 index 8e37484db0..0000000000 --- a/cpu/stm32/vectors/vectors_l0.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (C) 2014-2017 Freie Universität Berlin - * 2017 Inria - * - * This file is subject to the terms and conditions of the GNU Lesser General - * Public License v2.1. See the file LICENSE in the top level directory for more - * details. - */ - -/** - * @ingroup cpu_stm32 - * @{ - * - * @file - * @brief Interrupt vector definitions for STM32L0 - * - * @author Hauke Petersen - * @author Alexandre Abadie - * - * @} - */ - -#include "vectors_cortexm.h" - -/* define a local dummy handler as it needs to be in the same compilation unit - * as the alias definition */ -void dummy_handler(void) { - dummy_handler_default(); -} - -/* STM32L0 specific interrupt vectors */ -WEAK_DEFAULT void isr_adc1_comp(void); -WEAK_DEFAULT void isr_dma1_channel1(void); -WEAK_DEFAULT void isr_dma1_channel2_3(void); -WEAK_DEFAULT void isr_dma1_channel4_5_6_7(void); -WEAK_DEFAULT void isr_exti(void); -WEAK_DEFAULT void isr_flash(void); -WEAK_DEFAULT void isr_i2c1(void); -WEAK_DEFAULT void isr_i2c2(void); -WEAK_DEFAULT void isr_i2c3(void); -WEAK_DEFAULT void isr_lcd(void); -WEAK_DEFAULT void isr_lptim1(void); -WEAK_DEFAULT void isr_lpuart1(void); -WEAK_DEFAULT void isr_pvd(void); -WEAK_DEFAULT void isr_rcc(void); -WEAK_DEFAULT void isr_rcc_crs(void); -WEAK_DEFAULT void isr_rng_lpuart1(void); -WEAK_DEFAULT void isr_rtc(void); -WEAK_DEFAULT void isr_spi1(void); -WEAK_DEFAULT void isr_spi2(void); -WEAK_DEFAULT void isr_tim2(void); -WEAK_DEFAULT void isr_tim21(void); -WEAK_DEFAULT void isr_tim22(void); -WEAK_DEFAULT void isr_tim3(void); -WEAK_DEFAULT void isr_tim6_dac(void); -WEAK_DEFAULT void isr_tim7(void); -WEAK_DEFAULT void isr_tsc(void); -WEAK_DEFAULT void isr_usart1(void); -WEAK_DEFAULT void isr_usart2(void); -WEAK_DEFAULT void isr_usart4_5(void); -WEAK_DEFAULT void isr_usb(void); -WEAK_DEFAULT void isr_wwdg(void); - -/* CPU specific interrupt vector table */ -ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = { - /* shared vectors for all family members */ - [ 0] = isr_wwdg, /* [ 0] Window WatchDog Interrupt */ - [ 1] = isr_pvd, /* [ 1] PVD through EXTI Line detect Interrupt */ - [ 2] = isr_rtc, /* [ 2] RTC through EXTI Line Interrupt */ - [ 3] = isr_flash, /* [ 3] FLASH Interrupt */ - [ 5] = isr_exti, /* [ 5] EXTI Line 0 and 1 Interrupts */ - [ 6] = isr_exti, /* [ 6] EXTI Line 2 and 3 Interrupts */ - [ 7] = isr_exti, /* [ 7] EXTI Line 4 to 15 Interrupts */ - [ 9] = isr_dma1_channel1, /* [ 9] DMA1 Channel 1 Interrupt */ - [10] = isr_dma1_channel2_3, /* [10] DMA1 Channel 2 and Channel 3 Interrupts */ - [11] = isr_dma1_channel4_5_6_7, /* [11] DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ - [12] = isr_adc1_comp, /* [12] ADC1, COMP1 and COMP2 Interrupts */ - [13] = isr_lptim1, /* [13] LPTIM1 Interrupt */ - [15] = isr_tim2, /* [15] TIM2 Interrupt */ - [20] = isr_tim21, /* [20] TIM21 Interrupt */ - [22] = isr_tim22, /* [22] TIM22 Interrupt */ - [23] = isr_i2c1, /* [23] I2C1 Interrupt */ - [25] = isr_spi1, /* [25] SPI1 Interrupt */ - [28] = isr_usart2, /* [28] USART2 Interrupt */ - -#if defined(CPU_LINE_STM32L031xx) - [ 4] = isr_rcc, /* [ 4] RCC Interrupt */ - [29] = isr_lpuart1, /* [29] LPUART1 Interrupt */ -#elif defined(CPU_LINE_STM32L052xx) - [ 4] = isr_rcc_crs, /* [ 4] RCC and CRS Interrupts */ - [ 8] = isr_tsc, /* [ 8] TSC Interrupt */ - [17] = isr_tim6_dac, /* [17] TIM6 and DAC Interrupts */ - [24] = isr_i2c2, /* [24] I2C2 Interrupt */ - [26] = isr_spi2, /* [26] SPI2 Interrupt */ - [27] = isr_usart1, /* [27] USART1 Interrupt */ - [29] = isr_rng_lpuart1, /* [29] RNG and LPUART1 Interrupts */ - [31] = isr_usb, /* [31] USB global Interrupt */ -#elif defined(CPU_LINE_STM32L053xx) - [ 4] = isr_rcc_crs, /* [ 4] RCC and CRS Interrupts */ - [ 8] = isr_tsc, /* [ 8] TSC Interrupt */ - [17] = isr_tim6_dac, /* [17] TIM6 and DAC Interrupts */ - [24] = isr_i2c2, /* [24] I2C2 Interrupt */ - [26] = isr_spi2, /* [26] SPI2 Interrupt */ - [27] = isr_usart1, /* [27] USART1 Interrupt */ - [29] = isr_rng_lpuart1, /* [29] RNG and LPUART1 Interrupts */ - [30] = isr_lcd, /* [30] LCD Interrupt */ - [31] = isr_usb, /* [31] USB global Interrupt */ -#elif defined(CPU_LINE_STM32L072xx) - [ 4] = isr_rcc_crs, /* [ 4] RCC and CRS Interrupts */ - [ 8] = isr_tsc, /* [ 8] TSC Interrupt */ - [14] = isr_usart4_5, /* [14] USART4 and USART5 Interrupt */ - [16] = isr_tim3, /* [16] TIM3 Interrupt */ - [17] = isr_tim6_dac, /* [17] TIM6 and DAC Interrupts */ - [18] = isr_tim7, /* [18] TIM7 Interrupt */ - [21] = isr_i2c3, /* [21] I2C3 Interrupt */ - [24] = isr_i2c2, /* [24] I2C2 Interrupt */ - [26] = isr_spi2, /* [26] SPI2 Interrupt */ - [27] = isr_usart1, /* [27] USART1 Interrupt */ - [29] = isr_rng_lpuart1, /* [29] RNG and LPUART1 Interrupts */ - [31] = isr_usb, /* [31] USB global Interrupt */ -#elif defined(CPU_LINE_STM32L073xx) - [ 4] = isr_rcc_crs, /* [ 4] RCC and CRS Interrupts */ - [ 8] = isr_tsc, /* [ 8] TSC Interrupt */ - [14] = isr_usart4_5, /* [14] USART4 and USART5 Interrupt */ - [16] = isr_tim3, /* [16] TIM3 Interrupt */ - [17] = isr_tim6_dac, /* [17] TIM6 and DAC Interrupts */ - [18] = isr_tim7, /* [18] TIM7 Interrupt */ - [21] = isr_i2c3, /* [21] I2C3 Interrupt */ - [24] = isr_i2c2, /* [24] I2C2 Interrupt */ - [26] = isr_spi2, /* [26] SPI2 Interrupt */ - [27] = isr_usart1, /* [27] USART1 Interrupt */ - [29] = isr_rng_lpuart1, /* [29] RNG and LPUART1 Interrupts */ - [30] = isr_lcd, /* [30] LCD Interrupt */ - [31] = isr_usb, /* [31] USB global Interrupt */ -#endif -}; diff --git a/cpu/stm32/vectors/vectors_l1.c b/cpu/stm32/vectors/vectors_l1.c deleted file mode 100644 index 69c39beb32..0000000000 --- a/cpu/stm32/vectors/vectors_l1.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Copyright (C) 2014-2015 Freie Universität Berlin - * - * This file is subject to the terms and conditions of the GNU Lesser General - * Public License v2.1. See the file LICENSE in the top level directory for more - * details. - */ - -/** - * @ingroup cpu_stm32 - * @{ - * - * @file - * @brief Interrupt vector definitions for STM32L1 - * - * @author Hauke Petersen - * @author Thomas Eichinger - * - * @} - */ - -#include -#include "vectors_cortexm.h" - -/* define a local dummy handler as it needs to be in the same compilation unit - * as the alias definition */ -void dummy_handler(void) { - dummy_handler_default(); -} - -/* STM32L1 specific interrupt vectors */ -WEAK_DEFAULT void isr_wwdg(void); -WEAK_DEFAULT void isr_pvd(void); -WEAK_DEFAULT void isr_tamper_stamp(void); -WEAK_DEFAULT void isr_rtc_wkup(void); -WEAK_DEFAULT void isr_flash(void); -WEAK_DEFAULT void isr_rcc(void); -WEAK_DEFAULT void isr_exti(void); -WEAK_DEFAULT void isr_dma1_ch1(void); -WEAK_DEFAULT void isr_dma1_ch2(void); -WEAK_DEFAULT void isr_dma1_ch3(void); -WEAK_DEFAULT void isr_dma1_ch4(void); -WEAK_DEFAULT void isr_dma1_ch5(void); -WEAK_DEFAULT void isr_dma1_ch6(void); -WEAK_DEFAULT void isr_dma1_ch7(void); -WEAK_DEFAULT void isr_adc1(void); -WEAK_DEFAULT void isr_usb_hp(void); -WEAK_DEFAULT void isr_usb_lp(void); -WEAK_DEFAULT void isr_dac(void); -WEAK_DEFAULT void isr_comp(void); -WEAK_DEFAULT void isr_lcd(void); -WEAK_DEFAULT void isr_tim9(void); -WEAK_DEFAULT void isr_tim10(void); -WEAK_DEFAULT void isr_tim11(void); -WEAK_DEFAULT void isr_tim2(void); -WEAK_DEFAULT void isr_tim3(void); -WEAK_DEFAULT void isr_tim4(void); -WEAK_DEFAULT void isr_i2c1_ev(void); -WEAK_DEFAULT void isr_i2c1_er(void); -WEAK_DEFAULT void isr_i2c2_ev(void); -WEAK_DEFAULT void isr_i2c2_er(void); -WEAK_DEFAULT void isr_spi1(void); -WEAK_DEFAULT void isr_spi2(void); -WEAK_DEFAULT void isr_usart1(void); -WEAK_DEFAULT void isr_usart2(void); -WEAK_DEFAULT void isr_usart3(void); -WEAK_DEFAULT void isr_rtc_alarm(void); -WEAK_DEFAULT void isr_usb_fs_wkup(void); -WEAK_DEFAULT void isr_tim6(void); -WEAK_DEFAULT void isr_tim7(void); -WEAK_DEFAULT void isr_sdio(void); -WEAK_DEFAULT void isr_tim5(void); -WEAK_DEFAULT void isr_spi3(void); -WEAK_DEFAULT void isr_uart4(void); -WEAK_DEFAULT void isr_uart5(void); -WEAK_DEFAULT void isr_dma2_ch1(void); -WEAK_DEFAULT void isr_dma2_ch2(void); -WEAK_DEFAULT void isr_dma2_ch3(void); -WEAK_DEFAULT void isr_dma2_ch4(void); -WEAK_DEFAULT void isr_dma2_ch5(void); -WEAK_DEFAULT void isr_aes(void); -WEAK_DEFAULT void isr_comp_acq(void); - -/* CPU specific interrupt vector table */ -ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = { - isr_wwdg, /* [0] Window WatchDog Interrupt */ - isr_pvd, /* [1] PVD through EXTI Line detection Interrupt */ - isr_tamper_stamp, /* [2] Tamper and Time Stamp through EXTI Line Interrupts */ - isr_rtc_wkup, /* [3] RTC Wakeup Timer through EXTI Line Interrupt */ - isr_flash, /* [4] FLASH global Interrupt */ - isr_rcc, /* [5] RCC global Interrupt */ - isr_exti, /* [6] EXTI Line0 Interrupt */ - isr_exti, /* [7] EXTI Line1 Interrupt */ - isr_exti, /* [8] EXTI Line2 Interrupt */ - isr_exti, /* [9] EXTI Line3 Interrupt */ - isr_exti, /* [10] EXTI Line4 Interrupt */ - isr_dma1_ch1, /* [11] DMA1 Channel 1 global Interrupt */ - isr_dma1_ch2, /* [12] DMA1 Channel 2 global Interrupt */ - isr_dma1_ch3, /* [13] DMA1 Channel 3 global Interrupt */ - isr_dma1_ch4, /* [14] DMA1 Channel 4 global Interrupt */ - isr_dma1_ch5, /* [15] DMA1 Channel 5 global Interrupt */ - isr_dma1_ch6, /* [16] DMA1 Channel 6 global Interrupt */ - isr_dma1_ch7, /* [17] DMA1 Channel 7 global Interrupt */ - isr_adc1, /* [18] ADC1 global Interrupt */ - isr_usb_hp, /* [19] USB High Priority Interrupt */ - isr_usb_lp, /* [20] USB Low Priority Interrupt */ - isr_dac, /* [21] DAC Interrupt */ - isr_comp, /* [22] Comparator through EXTI Line Interrupt */ - isr_exti, /* [23] External Line[9:5] Interrupts */ - isr_lcd, /* [24] LCD Interrupt */ - isr_tim9, /* [25] TIM9 global Interrupt */ - isr_tim10, /* [26] TIM10 global Interrupt */ - isr_tim11, /* [27] TIM11 global Interrupt */ - isr_tim2, /* [28] TIM2 global Interrupt */ - isr_tim3, /* [29] TIM3 global Interrupt */ - isr_tim4, /* [30] TIM4 global Interrupt */ - isr_i2c1_ev, /* [31] I2C1 Event Interrupt */ - isr_i2c1_er, /* [32] I2C1 Error Interrupt */ - isr_i2c2_ev, /* [33] I2C2 Event Interrupt */ - isr_i2c2_er, /* [34] I2C2 Error Interrupt */ - isr_spi1, /* [35] SPI1 global Interrupt */ - isr_spi2, /* [36] SPI2 global Interrupt */ - isr_usart1, /* [37] USART1 global Interrupt */ - isr_usart2, /* [38] USART2 global Interrupt */ - isr_usart3, /* [39] USART3 global Interrupt */ - isr_exti, /* [40] External Line[15:10] Interrupts */ - isr_rtc_alarm, /* [41] RTC Alarm through EXTI Line Interrupt */ - isr_usb_fs_wkup, /* [42] USB FS WakeUp from suspend through EXTI Line Interrupt */ - isr_tim6, /* [43] TIM6 global Interrupt */ - isr_tim7, /* [44] TIM7 global Interrupt */ -#if defined(CPU_MODEL_STM32L151RC) - (0UL), /* [45] Reserved */ - isr_tim5, /* [46] TIM5 global Interrupt */ - isr_spi3, /* [47] SPI3 global Interrupt */ - (0UL), /* [48] Reserved */ - (0UL), /* [49] Reserved */ - isr_dma2_ch1, /* [50] DMA2 Channel 1 global Interrupt */ - isr_dma2_ch2, /* [51] DMA2 Channel 2 global Interrupt */ - isr_dma2_ch3, /* [52] DMA2 Channel 3 global Interrupt */ - isr_dma2_ch4, /* [53] DMA2 Channel 4 global Interrupt */ - isr_dma2_ch5, /* [54] DMA2 Channel 5 global Interrupt */ - isr_aes, /* [55] AES global Interrupt */ - isr_comp_acq /* [56] Comparator Channel Acquisition global Interrupt */ -#elif defined(CPU_MODEL_STM32L152RE) - (0UL), /* [45] Reserved */ - isr_tim5, /* [46] TIM5 global Interrupt */ - isr_spi3, /* [47] SPI3 global Interrupt */ - isr_uart4, /* [48] UART4 global Interrupt */ - isr_uart5, /* [49] UART5 global Interrupt */ - isr_dma2_ch1, /* [50] DMA2 Channel 1 global Interrupt */ - isr_dma2_ch2, /* [51] DMA2 Channel 2 global Interrupt */ - isr_dma2_ch3, /* [52] DMA2 Channel 3 global Interrupt */ - isr_dma2_ch4, /* [53] DMA2 Channel 4 global Interrupt */ - isr_dma2_ch5, /* [54] DMA2 Channel 5 global Interrupt */ - isr_aes, /* [55] AES global Interrupt */ - isr_comp_acq /* [56] Comparator Channel Acquisition global Interrupt */ -#endif -}; diff --git a/cpu/stm32/vectors/vectors_l4.c b/cpu/stm32/vectors/vectors_l4.c deleted file mode 100644 index 0d4139a598..0000000000 --- a/cpu/stm32/vectors/vectors_l4.c +++ /dev/null @@ -1,292 +0,0 @@ -/* - * Copyright (C) 2017 Freie Universität Berlin - * - * This file is subject to the terms and conditions of the GNU Lesser - * General Public License v2.1. See the file LICENSE in the top level - * directory for more details. - */ - -/** - * @ingroup cpu_stm32 - * @{ - * - * @file - * @brief Interrupt vector definitions for STM32L4 - * - * @author Hauke Petersen - * - * @} - */ - -#include "vectors_cortexm.h" - -/* define a local dummy handler as it needs to be in the same compilation unit - * as the alias definition */ -void dummy_handler(void) { - dummy_handler_default(); -} - -/* STM32L4 specific interrupt vectors */ -WEAK_DEFAULT void isr_adc1(void); -WEAK_DEFAULT void isr_adc1_2(void); -WEAK_DEFAULT void isr_adc3(void); -WEAK_DEFAULT void isr_can1_rx0(void); -WEAK_DEFAULT void isr_can1_rx1(void); -WEAK_DEFAULT void isr_can1_sce(void); -WEAK_DEFAULT void isr_can1_tx(void); -WEAK_DEFAULT void isr_can2_rx0(void); -WEAK_DEFAULT void isr_can2_rx1(void); -WEAK_DEFAULT void isr_can2_sce(void); -WEAK_DEFAULT void isr_can2_tx(void); -WEAK_DEFAULT void isr_comp(void); -WEAK_DEFAULT void isr_crs(void); -WEAK_DEFAULT void isr_dcmi(void); -WEAK_DEFAULT void isr_dfsdm1_flt0(void); -WEAK_DEFAULT void isr_dfsdm1_flt1(void); -WEAK_DEFAULT void isr_dfsdm1_flt2(void); -WEAK_DEFAULT void isr_dfsdm1_flt3(void); -WEAK_DEFAULT void isr_dma1_channel1(void); -WEAK_DEFAULT void isr_dma1_channel2(void); -WEAK_DEFAULT void isr_dma1_channel3(void); -WEAK_DEFAULT void isr_dma1_channel4(void); -WEAK_DEFAULT void isr_dma1_channel5(void); -WEAK_DEFAULT void isr_dma1_channel6(void); -WEAK_DEFAULT void isr_dma1_channel7(void); -WEAK_DEFAULT void isr_dma2_channel1(void); -WEAK_DEFAULT void isr_dma2_channel2(void); -WEAK_DEFAULT void isr_dma2_channel3(void); -WEAK_DEFAULT void isr_dma2_channel4(void); -WEAK_DEFAULT void isr_dma2_channel5(void); -WEAK_DEFAULT void isr_dma2_channel6(void); -WEAK_DEFAULT void isr_dma2_channel7(void); -WEAK_DEFAULT void isr_dma2d(void); -WEAK_DEFAULT void isr_dmamux1_ovr(void); -WEAK_DEFAULT void isr_exti(void); -WEAK_DEFAULT void isr_flash(void); -WEAK_DEFAULT void isr_fmc(void); -WEAK_DEFAULT void isr_fpu(void); -WEAK_DEFAULT void isr_i2c1_er(void); -WEAK_DEFAULT void isr_i2c1_ev(void); -WEAK_DEFAULT void isr_i2c2_er(void); -WEAK_DEFAULT void isr_i2c2_ev(void); -WEAK_DEFAULT void isr_i2c3_er(void); -WEAK_DEFAULT void isr_i2c3_ev(void); -WEAK_DEFAULT void isr_i2c4_ev(void); -WEAK_DEFAULT void isr_i2c4_er(void); -WEAK_DEFAULT void isr_lcd(void); -WEAK_DEFAULT void isr_lptim1(void); -WEAK_DEFAULT void isr_lptim2(void); -WEAK_DEFAULT void isr_lpuart1(void); -WEAK_DEFAULT void isr_octospi1(void); -WEAK_DEFAULT void isr_octospi2(void); -WEAK_DEFAULT void isr_otg_fs(void); -WEAK_DEFAULT void isr_pvd_pvm(void); -WEAK_DEFAULT void isr_quadspi(void); -WEAK_DEFAULT void isr_rcc(void); -WEAK_DEFAULT void isr_rng(void); -WEAK_DEFAULT void isr_rtc_alarm(void); -WEAK_DEFAULT void isr_rtc_wkup(void); -WEAK_DEFAULT void isr_sai1(void); -WEAK_DEFAULT void isr_sai2(void); -WEAK_DEFAULT void isr_sdmmc1(void); -WEAK_DEFAULT void isr_spi1(void); -WEAK_DEFAULT void isr_spi2(void); -WEAK_DEFAULT void isr_spi3(void); -WEAK_DEFAULT void isr_swpmi1(void); -WEAK_DEFAULT void isr_tamp_stamp(void); -WEAK_DEFAULT void isr_tim1_brk_tim15(void); -WEAK_DEFAULT void isr_tim1_cc(void); -WEAK_DEFAULT void isr_tim1_trg_com(void); -WEAK_DEFAULT void isr_tim1_trg_com_tim17(void); -WEAK_DEFAULT void isr_tim1_up_tim16(void); -WEAK_DEFAULT void isr_tim2(void); -WEAK_DEFAULT void isr_tim3(void); -WEAK_DEFAULT void isr_tim4(void); -WEAK_DEFAULT void isr_tim5(void); -WEAK_DEFAULT void isr_tim6_dac(void); -WEAK_DEFAULT void isr_tim7(void); -WEAK_DEFAULT void isr_tim8_brk(void); -WEAK_DEFAULT void isr_tim8_cc(void); -WEAK_DEFAULT void isr_tim8_trg_com(void); -WEAK_DEFAULT void isr_tim8_up(void); -WEAK_DEFAULT void isr_tsc(void); -WEAK_DEFAULT void isr_uart4(void); -WEAK_DEFAULT void isr_uart5(void); -WEAK_DEFAULT void isr_usart1(void); -WEAK_DEFAULT void isr_usart2(void); -WEAK_DEFAULT void isr_usart3(void); -WEAK_DEFAULT void isr_usb(void); -WEAK_DEFAULT void isr_wwdg(void); - -/* CPU specific interrupt vector table */ -ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = { - /* shared vectors for all family members */ - [WWDG_IRQn ] = isr_wwdg, /* [ 0] Window WatchDog Interrupt */ - [PVD_PVM_IRQn ] = isr_pvd_pvm, /* [ 1] PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ - [TAMP_STAMP_IRQn ] = isr_tamp_stamp, /* [ 2] Tamper and TimeStamp interrupts through the EXTI line */ - [RTC_WKUP_IRQn ] = isr_rtc_wkup, /* [ 3] RTC Wakeup interrupt through the EXTI line */ - [FLASH_IRQn ] = isr_flash, /* [ 4] FLASH global Interrupt */ - [RCC_IRQn ] = isr_rcc, /* [ 5] RCC global Interrupt */ - [EXTI0_IRQn ] = isr_exti, /* [ 6] EXTI Line0 Interrupt */ - [EXTI1_IRQn ] = isr_exti, /* [ 7] EXTI Line1 Interrupt */ - [EXTI2_IRQn ] = isr_exti, /* [ 8] EXTI Line2 Interrupt */ - [EXTI3_IRQn ] = isr_exti, /* [ 9] EXTI Line3 Interrupt */ - [EXTI4_IRQn ] = isr_exti, /* [10] EXTI Line4 Interrupt */ - [DMA1_Channel1_IRQn ] = isr_dma1_channel1, /* [11] DMA1 Channel 1 global Interrupt */ - [DMA1_Channel2_IRQn ] = isr_dma1_channel2, /* [12] DMA1 Channel 2 global Interrupt */ - [DMA1_Channel3_IRQn ] = isr_dma1_channel3, /* [13] DMA1 Channel 3 global Interrupt */ - [DMA1_Channel4_IRQn ] = isr_dma1_channel4, /* [14] DMA1 Channel 4 global Interrupt */ - [DMA1_Channel5_IRQn ] = isr_dma1_channel5, /* [15] DMA1 Channel 5 global Interrupt */ - [DMA1_Channel6_IRQn ] = isr_dma1_channel6, /* [16] DMA1 Channel 6 global Interrupt */ - [DMA1_Channel7_IRQn ] = isr_dma1_channel7, /* [17] DMA1 Channel 7 global Interrupt */ -#if defined(CPU_MODEL_STM32L412KB) -#else - [CAN1_TX_IRQn ] = isr_can1_tx, /* [19] CAN1 TX Interrupt */ - [CAN1_RX0_IRQn ] = isr_can1_rx0, /* [20] CAN1 RX0 Interrupt */ - [CAN1_RX1_IRQn ] = isr_can1_rx1, /* [21] CAN1 RX1 Interrupt */ - [CAN1_SCE_IRQn ] = isr_can1_sce, /* [22] CAN1 SCE Interrupt */ -#endif - [EXTI9_5_IRQn ] = isr_exti, /* [23] External Line[9:5] Interrupts */ - [TIM1_BRK_TIM15_IRQn ] = isr_tim1_brk_tim15, /* [24] TIM1 Break interrupt and TIM15 global interrupt */ - [TIM1_UP_TIM16_IRQn ] = isr_tim1_up_tim16, /* [25] TIM1 Update Interrupt and TIM16 global interrupt */ - [TIM1_CC_IRQn ] = isr_tim1_cc, /* [27] TIM1 Capture Compare Interrupt */ - [TIM2_IRQn ] = isr_tim2, /* [28] TIM2 global Interrupt */ - [I2C1_EV_IRQn ] = isr_i2c1_ev, /* [31] I2C1 Event Interrupt */ - [I2C1_ER_IRQn ] = isr_i2c1_er, /* [32] I2C1 Error Interrupt */ - [SPI1_IRQn ] = isr_spi1, /* [35] SPI1 global Interrupt */ - [USART1_IRQn ] = isr_usart1, /* [37] USART1 global Interrupt */ - [USART2_IRQn ] = isr_usart2, /* [38] USART2 global Interrupt */ - [EXTI15_10_IRQn ] = isr_exti, /* [40] External Line[15:10] Interrupts */ - [RTC_Alarm_IRQn ] = isr_rtc_alarm, /* [41] RTC Alarm (A and B) through EXTI Line Interrupt */ -#if defined(CPU_MODEL_STM32L412KB) -#else - [SPI3_IRQn ] = isr_spi3, /* [51] SPI3 global Interrupt */ -#endif - [TIM6_DAC_IRQn ] = isr_tim6_dac, /* [54] TIM6 global and DAC1&2 underrun error interrupts */ - [DMA2_Channel1_IRQn ] = isr_dma2_channel1, /* [56] DMA2 Channel 1 global Interrupt */ - [DMA2_Channel2_IRQn ] = isr_dma2_channel2, /* [57] DMA2 Channel 2 global Interrupt */ - [DMA2_Channel3_IRQn ] = isr_dma2_channel3, /* [58] DMA2 Channel 3 global Interrupt */ - [DMA2_Channel4_IRQn ] = isr_dma2_channel4, /* [59] DMA2 Channel 4 global Interrupt */ - [DMA2_Channel5_IRQn ] = isr_dma2_channel5, /* [60] DMA2 Channel 5 global Interrupt */ - [COMP_IRQn ] = isr_comp, /* [64] COMP1 and COMP2 Interrupts */ - [LPTIM1_IRQn ] = isr_lptim1, /* [65] LP TIM1 interrupt */ - [LPTIM2_IRQn ] = isr_lptim2, /* [66] LP TIM2 interrupt */ - [DMA2_Channel6_IRQn ] = isr_dma2_channel6, /* [68] DMA2 Channel 6 global interrupt */ - [DMA2_Channel7_IRQn ] = isr_dma2_channel7, /* [69] DMA2 Channel 7 global interrupt */ - [LPUART1_IRQn ] = isr_lpuart1, /* [70] LP UART1 interrupt */ - [I2C3_EV_IRQn ] = isr_i2c3_ev, /* [72] I2C3 event interrupt */ - [I2C3_ER_IRQn ] = isr_i2c3_er, /* [73] I2C3 error interrupt */ -#if defined(CPU_MODEL_STM32L412KB) -#else - [SAI1_IRQn ] = isr_sai1, /* [74] Serial Audio Interface 1 global interrupt */ -#endif - [TSC_IRQn ] = isr_tsc, /* [77] Touch Sense Controller global interrupt */ - [RNG_IRQn ] = isr_rng, /* [80] RNG global interrupt */ - [FPU_IRQn ] = isr_fpu, /* [81] FPU global interrupt */ - -#if defined(CPU_MODEL_STM32L432KC) || defined(CPU_MODEL_STM32L433RC) || \ - defined(CPU_MODEL_STM32L412KB) - [ADC1_IRQn ] = isr_adc1, /* [18] ADC1 global Interrupt */ - [TIM1_TRG_COM_IRQn ] = isr_tim1_trg_com, /* [26] TIM1 Trigger and Commutation Interrupt */ - [USB_IRQn ] = isr_usb, /* [67] USB event Interrupt */ -#endif -#if defined(CPU_MODEL_STM32L432KC) || defined(CPU_MODEL_STM32L433RC) - [CRS_IRQn ] = isr_crs, /* [82] CRS global interrupt */ -#endif -#if defined(CPU_MODEL_STM32L476RG) || defined(CPU_MODEL_STM32L476VG) || \ - defined(CPU_MODEL_STM32L475VG) || defined(CPU_MODEL_STM32L452RE) || \ - defined(CPU_MODEL_STM32L496ZG) - [ADC1_2_IRQn ] = isr_adc1_2, /* [18] ADC1, ADC2 SAR global Interrupts */ - [TIM1_TRG_COM_TIM17_IRQn ] = isr_tim1_trg_com_tim17, /* [26] TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */ - [TIM3_IRQn ] = isr_tim3, /* [29] TIM3 global Interrupt */ - [I2C2_EV_IRQn ] = isr_i2c2_ev, /* [33] I2C2 Event Interrupt */ - [I2C2_ER_IRQn ] = isr_i2c2_er, /* [34] I2C2 Error Interrupt */ - [SPI2_IRQn ] = isr_spi2, /* [36] SPI2 global Interrupt */ - [USART3_IRQn ] = isr_usart3, /* [39] USART3 global Interrupt */ - [SDMMC1_IRQn ] = isr_sdmmc1, /* [49] SDMMC1 global Interrupt */ - [UART4_IRQn ] = isr_uart4, /* [52] UART4 global Interrupt */ - [DFSDM1_FLT0_IRQn ] = isr_dfsdm1_flt0, /* [61] DFSDM1 Filter 0 global Interrupt */ - [DFSDM1_FLT1_IRQn ] = isr_dfsdm1_flt1, /* [62] DFSDM1 Filter 1 global Interrupt */ -#endif -#if defined(CPU_MODEL_STM32L476RG) || defined(CPU_MODEL_STM32L476VG) || \ - defined(CPU_MODEL_STM32L475VG) - [TIM4_IRQn ] = isr_tim4, /* [30] TIM4 global Interrupt */ - [DFSDM1_FLT3_IRQn ] = isr_dfsdm1_flt3, /* [42] DFSDM1 Filter 3 global Interrupt */ - [TIM8_BRK_IRQn ] = isr_tim8_brk, /* [43] TIM8 Break Interrupt */ - [TIM8_UP_IRQn ] = isr_tim8_up, /* [44] TIM8 Update Interrupt */ - [TIM8_TRG_COM_IRQn ] = isr_tim8_trg_com, /* [45] TIM8 Trigger and Commutation Interrupt */ - [TIM8_CC_IRQn ] = isr_tim8_cc, /* [46] TIM8 Capture Compare Interrupt */ - [ADC3_IRQn ] = isr_adc3, /* [47] ADC3 global Interrupt */ - [FMC_IRQn ] = isr_fmc, /* [48] FMC global Interrupt */ - [TIM5_IRQn ] = isr_tim5, /* [50] TIM5 global Interrupt */ - [UART5_IRQn ] = isr_uart5, /* [53] UART5 global Interrupt */ - [DFSDM1_FLT2_IRQn ] = isr_dfsdm1_flt2, /* [63] DFSDM1 Filter 2 global Interrupt */ - [OTG_FS_IRQn ] = isr_otg_fs, /* [67] USB OTG FS global Interrupt */ - [SAI2_IRQn ] = isr_sai2, /* [75] Serial Audio Interface 2 global interrupt */ -#endif -#if defined(CPU_MODEL_STM32L432KC) || defined(CPU_MODEL_STM32L433RC) || \ - defined(CPU_MODEL_STM32L476RG) || defined(CPU_MODEL_STM32L476VG) || \ - defined(CPU_MODEL_STM32L475VG) || defined(CPU_MODEL_STM32L496ZG) - [TIM7_IRQn ] = isr_tim7, /* [55] TIM7 global interrupt */ - [QUADSPI_IRQn ] = isr_quadspi, /* [71] Quad SPI global interrupt */ - [SWPMI1_IRQn ] = isr_swpmi1, /* [76] Serial Wire Interface 1 global interrupt */ -#endif -#if defined(CPU_MODEL_STM32L452RE) || defined(CPU_MODEL_STM32L412KB) - [QUADSPI_IRQn ] = isr_quadspi, /* [71] Quad SPI global interrupt */ -#endif -#if defined(CPU_MODEL_STM32L476RG) || defined(CPU_MODEL_STM32L476VG) - [LCD_IRQn ] = isr_lcd, /* [78] LCD global interrupt */ -#endif -#if defined(CPU_MODEL_STM32L496ZG) - [TIM4_IRQn ] = isr_tim4, /* [30] TIM4 global Interrupt */ - [TIM5_IRQn ] = isr_tim5, /* [50] TIM5 global Interrupt */ - [UART5_IRQn ] = isr_uart5, /* [53] UART5 global Interrupt */ - [DFSDM1_FLT2_IRQn ] = isr_dfsdm1_flt2, /* [63] DFSDM1 Filter 2 global Interrupt */ - [OTG_FS_IRQn ] = isr_otg_fs, /* [67] USB OTG FS global Interrupt */ - [SAI2_IRQn ] = isr_sai2, /* [75] Serial Audio Interface 2 global interrupt */ - [LCD_IRQn ] = isr_lcd, /* [78] LCD global interrupt */ - [CRS_IRQn ] = isr_crs, /* [82] CRS global interrupt */ - [I2C4_EV_IRQn ] = isr_i2c4_ev, /* [83] I2C4 Event interrupt */ - [I2C4_ER_IRQn ] = isr_i2c4_er, /* [84] I2C4 Error interrupt */ - [DCMI_IRQn ] = isr_dcmi, /* [85] DCMI global interrupt */ - [CAN2_TX_IRQn ] = isr_can2_tx, /* [86] CAN2 TX interrupt */ - [CAN2_RX0_IRQn ] = isr_can2_rx0, /* [87] CAN2 RX0 interrupt */ - [CAN2_RX1_IRQn ] = isr_can2_rx1, /* [88] CAN2 RX1 interrupt */ - [CAN2_SCE_IRQn ] = isr_can2_sce, /* [89] CAN2 SCE interrupt */ - [DMA2D_IRQn ] = isr_dma2d, /* [90] DMA2D global interrupt */ -#endif -#if defined(CPU_MODEL_STM32L4R5ZI) - [ADC1_IRQn ] = isr_adc1, /* [18] ADC1 global Interrupts */ - [TIM1_TRG_COM_TIM17_IRQn ] = isr_tim1_trg_com_tim17, /* [26] TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */ - [TIM3_IRQn ] = isr_tim3, /* [29] TIM3 global Interrupt */ - [TIM4_IRQn ] = isr_tim4, /* [30] TIM4 global Interrupt */ - [I2C2_EV_IRQn ] = isr_i2c2_ev, /* [33] I2C2 Event Interrupt */ - [I2C2_ER_IRQn ] = isr_i2c2_er, /* [34] I2C2 Error Interrupt */ - [SPI2_IRQn ] = isr_spi2, /* [36] SPI2 global Interrupt */ - [USART3_IRQn ] = isr_usart3, /* [39] USART3 global Interrupt */ - [DFSDM1_FLT3_IRQn ] = isr_dfsdm1_flt3, /* [42] DFSDM1 Filter 3 global Interrupt */ - [TIM8_BRK_IRQn ] = isr_tim8_brk, /* [43] TIM8 Break Interrupt */ - [TIM8_UP_IRQn ] = isr_tim8_up, /* [44] TIM8 Update Interrupt */ - [TIM8_TRG_COM_IRQn ] = isr_tim8_trg_com, /* [45] TIM8 Trigger and Commutation Interrupt */ - [TIM8_CC_IRQn ] = isr_tim8_cc, /* [46] TIM8 Capture Compare Interrupt */ - [FMC_IRQn ] = isr_fmc, /* [48] FMC global Interrupt */ - [SDMMC1_IRQn ] = isr_sdmmc1, /* [49] SDMMC1 global Interrupt */ - [TIM5_IRQn ] = isr_tim5, /* [50] TIM5 global Interrupt */ - [UART4_IRQn ] = isr_uart4, /* [52] UART4 global Interrupt */ - [UART5_IRQn ] = isr_uart5, /* [53] UART5 global Interrupt */ - [TIM7_IRQn ] = isr_tim7, /* [55] TIM7 global interrupt */ - [DFSDM1_FLT0_IRQn ] = isr_dfsdm1_flt0, /* [61] DFSDM1 Filter 0 global Interrupt */ - [DFSDM1_FLT1_IRQn ] = isr_dfsdm1_flt1, /* [62] DFSDM1 Filter 1 global Interrupt */ - [DFSDM1_FLT2_IRQn ] = isr_dfsdm1_flt2, /* [63] DFSDM1 Filter 2 global Interrupt */ - [OTG_FS_IRQn ] = isr_otg_fs, /* [67] USB OTG FS global Interrupt */ - [OCTOSPI1_IRQn ] = isr_octospi1, /* [71] OctoSPI1 global interrupt */ - [SAI2_IRQn ] = isr_sai2, /* [75] Serial Audio Interface 2 global interrupt */ - [OCTOSPI2_IRQn ] = isr_octospi2, /* [76] OctoSPI2 global interrupt */ - [CRS_IRQn ] = isr_crs, /* [82] CRS global interrupt */ - [I2C4_EV_IRQn ] = isr_i2c4_ev, /* [83] I2C4 Event interrupt */ - [I2C4_ER_IRQn ] = isr_i2c4_er, /* [84] I2C4 Error interrupt */ - [DCMI_IRQn ] = isr_dcmi, /* [85] DCMI global interrupt */ - [DMA2D_IRQn ] = isr_dma2d, /* [90] DMA2D global interrupt */ - [DMAMUX1_OVR_IRQn ] = isr_dmamux1_ovr, /* [94] DMAMUX1 overrun global interrupt */ -#endif -}; diff --git a/cpu/stm32/vectors/vectors_wb.c b/cpu/stm32/vectors/vectors_wb.c deleted file mode 100644 index e03d3c03fc..0000000000 --- a/cpu/stm32/vectors/vectors_wb.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Copyright (C) 2017 Freie Universität Berlin - * - * This file is subject to the terms and conditions of the GNU Lesser - * General Public License v2.1. See the file LICENSE in the top level - * directory for more details. - */ - -/** - * @ingroup cpu_stm32 - * @{ - * - * @file - * @brief Interrupt vector definitions for STM32WB - * - * @author Hauke Petersen - * - * @} - */ - -#include "vectors_cortexm.h" - -/* define a local dummy handler as it needs to be in the same compilation unit - * as the alias definition */ -void dummy_handler(void) { - dummy_handler_default(); -} - -/* STM32L4 specific interrupt vectors */ -WEAK_DEFAULT void isr_adc1(void); -WEAK_DEFAULT void isr_aes1(void); -WEAK_DEFAULT void isr_aes2(void); -WEAK_DEFAULT void isr_c2sev_pwr_c2h(void); -WEAK_DEFAULT void isr_comp(void); -WEAK_DEFAULT void isr_crs(void); -WEAK_DEFAULT void isr_dma1_channel1(void); -WEAK_DEFAULT void isr_dma1_channel2(void); -WEAK_DEFAULT void isr_dma1_channel3(void); -WEAK_DEFAULT void isr_dma1_channel4(void); -WEAK_DEFAULT void isr_dma1_channel5(void); -WEAK_DEFAULT void isr_dma1_channel6(void); -WEAK_DEFAULT void isr_dma1_channel7(void); -WEAK_DEFAULT void isr_dma2_channel1(void); -WEAK_DEFAULT void isr_dma2_channel2(void); -WEAK_DEFAULT void isr_dma2_channel3(void); -WEAK_DEFAULT void isr_dma2_channel4(void); -WEAK_DEFAULT void isr_dma2_channel5(void); -WEAK_DEFAULT void isr_dma2_channel6(void); -WEAK_DEFAULT void isr_dma2_channel7(void); -WEAK_DEFAULT void isr_dmamux1_ovr(void); -WEAK_DEFAULT void isr_exti(void); -WEAK_DEFAULT void isr_flash(void); -WEAK_DEFAULT void isr_fpu(void); -WEAK_DEFAULT void isr_hsem(void); -WEAK_DEFAULT void isr_ipcc_c1_rx(void); -WEAK_DEFAULT void isr_ipcc_c1_tx(void); -WEAK_DEFAULT void isr_i2c1_er(void); -WEAK_DEFAULT void isr_i2c1_ev(void); -WEAK_DEFAULT void isr_i2c3_er(void); -WEAK_DEFAULT void isr_i2c3_ev(void); -WEAK_DEFAULT void isr_lcd(void); -WEAK_DEFAULT void isr_lptim1(void); -WEAK_DEFAULT void isr_lptim2(void); -WEAK_DEFAULT void isr_lpuart1(void); -WEAK_DEFAULT void isr_pka(void); -WEAK_DEFAULT void isr_pvd_pvm(void); -WEAK_DEFAULT void isr_quadspi(void); -WEAK_DEFAULT void isr_rcc(void); -WEAK_DEFAULT void isr_rng(void); -WEAK_DEFAULT void isr_rtc_alarm(void); -WEAK_DEFAULT void isr_rtc_wkup(void); -WEAK_DEFAULT void isr_sai1(void); -WEAK_DEFAULT void isr_sotf_pwr_ble_802_rfphase(void); -WEAK_DEFAULT void isr_spi1(void); -WEAK_DEFAULT void isr_spi2(void); -WEAK_DEFAULT void isr_tamp_stamp(void); -WEAK_DEFAULT void isr_tim1_brk(void); -WEAK_DEFAULT void isr_tim1_cc(void); -WEAK_DEFAULT void isr_tim1_up_tim16(void); -WEAK_DEFAULT void isr_tim2(void); -WEAK_DEFAULT void isr_tsc(void); -WEAK_DEFAULT void isr_usart1(void); -WEAK_DEFAULT void isr_usb_hp(void); -WEAK_DEFAULT void isr_usb_lp(void); -WEAK_DEFAULT void isr_wwdg(void); - -/* CPU specific interrupt vector table */ -ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = { - [WWDG_IRQn ] = isr_wwdg, /* [ 0] Window WatchDog Interrupt */ - [PVD_PVM_IRQn ] = isr_pvd_pvm, /* [ 1] PVD and PVM detector */ - [TAMP_STAMP_LSECSS_IRQn ] = isr_tamp_stamp, /* [ 2] RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts */ - [RTC_WKUP_IRQn ] = isr_rtc_wkup, /* [ 3] RTC Wakeup Interrupt */ - [FLASH_IRQn ] = isr_flash, /* [ 4] FLASH global Interrupt */ - [RCC_IRQn ] = isr_rcc, /* [ 5] RCC global Interrupt */ - [EXTI0_IRQn ] = isr_exti, /* [ 6] EXTI Line0 Interrupt */ - [EXTI1_IRQn ] = isr_exti, /* [ 7] EXTI Line1 Interrupt */ - [EXTI2_IRQn ] = isr_exti, /* [ 8] EXTI Line2 Interrupt */ - [EXTI3_IRQn ] = isr_exti, /* [ 9] EXTI Line3 Interrupt */ - [EXTI4_IRQn ] = isr_exti, /* [10] EXTI Line4 Interrupt */ - [DMA1_Channel1_IRQn ] = isr_dma1_channel1, /* [11] DMA1 Channel 1 global Interrupt */ - [DMA1_Channel2_IRQn ] = isr_dma1_channel2, /* [12] DMA1 Channel 2 global Interrupt */ - [DMA1_Channel3_IRQn ] = isr_dma1_channel3, /* [13] DMA1 Channel 3 global Interrupt */ - [DMA1_Channel4_IRQn ] = isr_dma1_channel4, /* [14] DMA1 Channel 4 global Interrupt */ - [DMA1_Channel5_IRQn ] = isr_dma1_channel5, /* [15] DMA1 Channel 5 global Interrupt */ - [DMA1_Channel6_IRQn ] = isr_dma1_channel6, /* [16] DMA1 Channel 6 global Interrupt */ - [DMA1_Channel7_IRQn ] = isr_dma1_channel7, /* [17] DMA1 Channel 7 global Interrupt */ - [ADC1_IRQn ] = isr_adc1, /* [18] ADC1 Interrup */ - [USB_HP_IRQn ] = isr_usb_hp, /* [19] USB High Priority Interrupt */ - [USB_LP_IRQn ] = isr_usb_lp, /* [20] USB Low Priority Interrupt (including USB wakeup) */ - [C2SEV_PWR_C2H_IRQn ] = isr_c2sev_pwr_c2h, /* [21] CPU2 SEV Interrupt */ - [COMP_IRQn ] = isr_comp, /* [62] COMP1 and COMP2 Interrupts */ - [EXTI9_5_IRQn ] = isr_exti, /* [23] External Line[9:5] Interrupts */ - [TIM1_BRK_IRQn ] = isr_tim1_brk, /* [24] TIM1 Break interrupt */ - [TIM1_UP_TIM16_IRQn ] = isr_tim1_up_tim16, /* [25] TIM1 Update Interrupt and TIM16 global interrupt */ - [TIM1_CC_IRQn ] = isr_tim1_cc, /* [27] TIM1 Capture Compare Interrupt */ - [TIM2_IRQn ] = isr_tim2, /* [28] TIM2 global Interrupt */ - [PKA_IRQn ] = isr_pka, /* [29] PKA Interrup */ - [I2C1_EV_IRQn ] = isr_i2c1_ev, /* [30] I2C1 Event Interrupt */ - [I2C1_ER_IRQn ] = isr_i2c1_er, /* [31] I2C1 Error Interrupt */ - [I2C3_EV_IRQn ] = isr_i2c3_ev, /* [32] I2C3 Event Interrupt */ - [I2C3_ER_IRQn ] = isr_i2c3_er, /* [33] I2C3 Error Interrupt */ - [SPI1_IRQn ] = isr_spi1, /* [34] SPI1 global Interrupt */ - [SPI2_IRQn ] = isr_spi2, /* [35] SPI2 global Interrupt */ - [USART1_IRQn ] = isr_usart1, /* [36] USART1 global Interrupt */ - [LPUART1_IRQn ] = isr_lpuart1, /* [37] LP UART1 interrupt */ - [SAI1_IRQn ] = isr_sai1, /* [38] Serial Audio Interface 1 global interrupt */ - [TSC_IRQn ] = isr_tsc, /* [39] Touch Sense Controller global interrupt */ - [EXTI15_10_IRQn ] = isr_exti, /* [40] External Line[15:10] Interrupts */ - [RTC_Alarm_IRQn ] = isr_rtc_alarm, /* [41] RTC Alarm (A and B) through EXTI Line Interrupt */ - [CRS_IRQn ] = isr_crs, /* [42] CRS global interrupt */ - [PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQn] = isr_sotf_pwr_ble_802_rfphase, /* [43] PWR switching on the fly interrupt - PWR end of BLE activity interrupt - PWR end of 802.15.4 (Zigbee) activity interrupt - PWR end of critical radio phase interrupt */ - [IPCC_C1_RX_IRQn ] = isr_ipcc_c1_rx, /* [44] IPCC RX Occupied Interrupt */ - [IPCC_C1_TX_IRQn ] = isr_ipcc_c1_tx, /* [45] HIPCC TX Free Interrupt */ - [HSEM_IRQn ] = isr_hsem, /* [46] HSEM Interrupt */ - [LPTIM1_IRQn ] = isr_lptim1, /* [47] LP TIM1 interrupt */ - [LPTIM2_IRQn ] = isr_lptim2, /* [48] LP TIM2 interrupt */ - [LCD_IRQn ] = isr_lcd, /* [49] LCD global interrupt */ - [QUADSPI_IRQn ] = isr_quadspi, /* [50] Quad SPI global interrupt */ - [AES1_IRQn ] = isr_aes1, /* [51] AES1 Interrup */ - [AES2_IRQn ] = isr_aes2, /* [52] AES2 Interrupt */ - [RNG_IRQn ] = isr_rng, /* [53] RNG global interrupt */ - [FPU_IRQn ] = isr_fpu, /* [54] FPU global interrupt */ - [DMA2_Channel1_IRQn ] = isr_dma2_channel1, /* [55] DMA2 Channel 1 global Interrupt */ - [DMA2_Channel2_IRQn ] = isr_dma2_channel2, /* [56] DMA2 Channel 2 global Interrupt */ - [DMA2_Channel3_IRQn ] = isr_dma2_channel3, /* [57] DMA2 Channel 3 global Interrupt */ - [DMA2_Channel4_IRQn ] = isr_dma2_channel4, /* [58] DMA2 Channel 4 global Interrupt */ - [DMA2_Channel5_IRQn ] = isr_dma2_channel5, /* [69] DMA2 Channel 5 global Interrupt */ - [DMA2_Channel6_IRQn ] = isr_dma2_channel6, /* [60] DMA2 Channel 6 global interrupt */ - [DMA2_Channel7_IRQn ] = isr_dma2_channel7, /* [61] DMA2 Channel 7 global interrupt */ - [DMAMUX1_OVR_IRQn ] = isr_dmamux1_ovr, /* [62] DMAMUX1 overrun global interrupt */ -};