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https://github.com/RIOT-OS/RIOT.git
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Merge pull request #20714 from dylad/pr/cpu/samd5x/avoid_bitfields_reg
cpu/samd5x: avoid the use of bitfields
This commit is contained in:
Dylan Laduranty
GitHub
commit
6b7dd90e86
@ -109,7 +109,7 @@ static void xosc32k_init(void)
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| OSC32KCTRL_XOSC32K_XTALEN
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| OSC32KCTRL_XOSC32K_STARTUP(7);
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while (!OSC32KCTRL->STATUS.bit.XOSC32KRDY) {}
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while (!(OSC32KCTRL->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KRDY)) {}
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}
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static void xosc_init(uint8_t idx)
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@ -175,12 +175,12 @@ static void dfll_init(void)
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/* workaround for Errata 2.8.3 DFLLVAL.FINE Value When DFLL48M Re-enabled */
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OSCCTRL->DFLLMUL.reg = 0; /* Write new DFLLMULL configuration */
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OSCCTRL->DFLLCTRLB.reg = 0; /* Select Open loop configuration */
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OSCCTRL->DFLLCTRLA.bit.ENABLE = 1; /* Enable DFLL */
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OSCCTRL->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ENABLE; /* Enable DFLL */
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OSCCTRL->DFLLVAL.reg = OSCCTRL->DFLLVAL.reg; /* Reload DFLLVAL register */
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OSCCTRL->DFLLCTRLB.reg = reg; /* Write final DFLL configuration */
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OSCCTRL->DFLLCTRLA.reg = OSCCTRL_DFLLCTRLA_ENABLE;
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while (!OSCCTRL->STATUS.bit.DFLLRDY) {}
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while (!(OSCCTRL->STATUS.reg & OSCCTRL_STATUS_DFLLRDY)) {}
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}
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static void fdpll_init_nolock(uint8_t idx, uint32_t f_cpu, uint8_t flags)
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@ -197,7 +197,7 @@ static void fdpll_init_nolock(uint8_t idx, uint32_t f_cpu, uint8_t flags)
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const uint32_t LDR = (f_cpu >> 10);
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/* disable the DPLL before changing the configuration */
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OSCCTRL->Dpll[idx].DPLLCTRLA.bit.ENABLE = 0;
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OSCCTRL->Dpll[idx].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE;
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while (OSCCTRL->Dpll[idx].DPLLSYNCBUSY.reg) {}
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/* set DPLL clock source */
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@ -218,8 +218,8 @@ static void fdpll_init_nolock(uint8_t idx, uint32_t f_cpu, uint8_t flags)
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}
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static void fdpll_lock(uint8_t idx) {
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while (!(OSCCTRL->Dpll[idx].DPLLSTATUS.bit.CLKRDY &&
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OSCCTRL->Dpll[idx].DPLLSTATUS.bit.LOCK)) {}
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const uint32_t flags = (OSCCTRL_DPLLSTATUS_CLKRDY | OSCCTRL_DPLLSTATUS_LOCK);
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while (!((OSCCTRL->Dpll[idx].DPLLSTATUS.reg & flags) == flags)) {}
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}
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static void gclk_connect(uint8_t id, uint8_t src, uint32_t flags) {
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@ -346,7 +346,7 @@ void cpu_init(void)
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MCLK->APBDMASK.reg = 0;
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/* enable the Cortex M Cache Controller */
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CMCC->CTRL.bit.CEN = 1;
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CMCC->CTRL.reg |= CMCC_CTRL_CEN;
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/* make sure main clock is not sourced from DPLL */
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dfll_init();
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@ -437,22 +437,27 @@ static int _send(candev_t *candev, const struct can_frame *frame)
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DEBUG("Tx FIFO get index = %u\n", fifo_queue_get_idx);
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can_mm.put = fifo_queue_put_idx;
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can_mm.get = fifo_queue_get_idx;
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uint32_t txbe0 = 0;
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uint32_t txbe1 = 0;
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if (frame->can_id & CAN_EFF_FLAG) {
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DEBUG_PUTS("Extended ID");
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dev->msg_ram_conf.tx_fifo_queue[can_mm.put].TXBE_0.bit.ID = frame->can_id & CAN_EFF_MASK;
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dev->msg_ram_conf.tx_fifo_queue[can_mm.put].TXBE_0.bit.XTD = 1;
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txbe0 = CAN_TXBE_0_ID(frame->can_id & CAN_EFF_MASK) | CAN_TXBE_0_XTD;
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}
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else {
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DEBUG_PUTS("Standard identifier");
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dev->msg_ram_conf.tx_fifo_queue[can_mm.put].TXBE_0.bit.ID = (frame->can_id & CAN_SFF_MASK) << 18;
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dev->msg_ram_conf.tx_fifo_queue[can_mm.put].TXBE_0.bit.XTD = 0;
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txbe0 = CAN_TXBE_0_ID((frame->can_id & CAN_SFF_MASK) << 18);
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}
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dev->msg_ram_conf.tx_fifo_queue[can_mm.put].TXBE_0.bit.RTR = (frame->can_id & CAN_RTR_FLAG) >> 30;
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dev->msg_ram_conf.tx_fifo_queue[can_mm.put].TXBE_0.bit.ESI = 1;
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dev->msg_ram_conf.tx_fifo_queue[can_mm.put].TXBE_1.bit.DLC = frame->can_dlc;
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dev->msg_ram_conf.tx_fifo_queue[can_mm.put].TXBE_1.bit.EFC = 1;
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dev->msg_ram_conf.tx_fifo_queue[can_mm.put].TXBE_1.bit.MM = _form_message_marker(&can_mm);
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txbe0 |= (((frame->can_id & CAN_RTR_FLAG) >> 30) << CAN_TXBE_0_RTR_Pos);
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txbe0 |= CAN_TXBE_0_ESI;
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/* Write the prepared word */
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dev->msg_ram_conf.tx_fifo_queue[can_mm.put].TXBE_0.reg = txbe0;
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/* Prepare second word */
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txbe1 = CAN_TXBE_1_DLC(frame->can_dlc) | CAN_TXBE_1_EFC |
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CAN_TXBE_1_MM(_form_message_marker(&can_mm));
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/* Write the second word */
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dev->msg_ram_conf.tx_fifo_queue[can_mm.put].TXBE_1.reg = txbe1;
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memcpy((void *)dev->msg_ram_conf.tx_fifo_queue[can_mm.put].TXBE_DATA, frame->data, frame->can_dlc);
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/* Request transmission */
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@ -464,12 +469,14 @@ static int _send(candev_t *candev, const struct can_frame *frame)
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static int16_t _find_filter(can_t *can, const struct can_filter *filter, bool is_std_filter)
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{
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int16_t idx = -1;
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uint32_t msg_id;
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/* Standard filter */
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if (is_std_filter) {
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/* Search for the standard filter in the CAN controller message RAM */
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for (uint8_t i = 0; i < ARRAY_SIZE(can->msg_ram_conf.std_filter); i++) {
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if (((filter->can_id & CAN_SFF_MASK) == can->msg_ram_conf.std_filter[i].SIDFE_0.bit.SFID1)) {
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msg_id = ((can->msg_ram_conf.std_filter[i].SIDFE_0.reg &
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CAN_SIDFE_0_SFID1_Msk) >> CAN_SIDFE_0_SFID1_Pos);
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if ((filter->can_id & CAN_SFF_MASK) == msg_id ) {
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idx = i;
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break;
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}
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@ -479,7 +486,9 @@ static int16_t _find_filter(can_t *can, const struct can_filter *filter, bool is
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else {
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/* Search for the extended filter in the CAN controller message RAM */
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for (uint8_t i = 0; i < ARRAY_SIZE(can->msg_ram_conf.ext_filter); i++) {
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if (((filter->can_id & CAN_EFF_MASK) == can->msg_ram_conf.ext_filter[i].XIDFE_0.bit.EFID1)) {
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msg_id = ((can->msg_ram_conf.ext_filter[i].XIDFE_0.reg &
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CAN_XIDFE_0_EFID1_Msk) >> CAN_XIDFE_0_EFID1_Pos);
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if ((filter->can_id & CAN_EFF_MASK) == msg_id) {
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idx = i;
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break;
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}
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@ -494,6 +503,7 @@ static int _set_filter(candev_t *candev, const struct can_filter *filter)
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can_t *dev = container_of(candev, can_t, candev);
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int16_t idx = 0;
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uint32_t tmp = 0;
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uint8_t filter_conf = 0;
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switch (filter->target_mailbox) {
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case 0:
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@ -516,7 +526,10 @@ static int _set_filter(candev_t *candev, const struct can_filter *filter)
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else {
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/* Find a free slot where to save the filter */
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for (idx = 0; (uint16_t)idx < ARRAY_SIZE(dev->msg_ram_conf.ext_filter); idx++) {
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if (dev->msg_ram_conf.ext_filter[idx].XIDFE_0.bit.EFEC == CANDEV_SAMD5X_FILTER_DISABLE) {
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tmp = dev->msg_ram_conf.ext_filter[idx].XIDFE_0.reg;
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if (((tmp & CAN_XIDFE_0_EFEC_Msk) >> CAN_XIDFE_0_EFEC_Pos) ==
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CANDEV_SAMD5X_FILTER_DISABLE)
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{
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DEBUG_PUTS("empty slot");
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break;
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}
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@ -529,11 +542,11 @@ static int _set_filter(candev_t *candev, const struct can_filter *filter)
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}
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DEBUG("Extended Filter to add at idx = %d\n", idx);
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dev->msg_ram_conf.ext_filter[idx].XIDFE_0.bit.EFEC = filter_conf;
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dev->msg_ram_conf.ext_filter[idx].XIDFE_0.reg |= CAN_XIDFE_0_EFEC(filter_conf);
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/* For now, only CLASSIC filters are supported */
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dev->msg_ram_conf.ext_filter[idx].XIDFE_1.bit.EFT = CANDEV_SAMD5X_CLASSIC_FILTER;
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dev->msg_ram_conf.ext_filter[idx].XIDFE_0.bit.EFID1 = filter->can_id;
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dev->msg_ram_conf.ext_filter[idx].XIDFE_1.bit.EFID2 = filter->can_mask & CAN_EFF_MASK;
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dev->msg_ram_conf.ext_filter[idx].XIDFE_1.reg |= CAN_XIDFE_1_EFT(CANDEV_SAMD5X_CLASSIC_FILTER);
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dev->msg_ram_conf.ext_filter[idx].XIDFE_0.reg |= CAN_XIDFE_0_EFID1(filter->can_id);
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dev->msg_ram_conf.ext_filter[idx].XIDFE_1.reg |= CAN_XIDFE_1_EFID2(filter->can_mask & CAN_EFF_MASK);
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DEBUG("Extended filter element N°%d: F0 = 0x%08lx, F1 = 0x%08lx\n", idx,
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(uint32_t)(dev->msg_ram_conf.ext_filter[idx].XIDFE_0.reg),
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(uint32_t)(dev->msg_ram_conf.ext_filter[idx].XIDFE_1.reg));
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@ -552,7 +565,10 @@ static int _set_filter(candev_t *candev, const struct can_filter *filter)
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else {
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/* Find a free slot where to save the filter */
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for (idx = 0; (uint16_t)idx < ARRAY_SIZE(dev->msg_ram_conf.std_filter); idx++) {
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if (dev->msg_ram_conf.std_filter[idx].SIDFE_0.bit.SFEC == CANDEV_SAMD5X_FILTER_DISABLE) {
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tmp = dev->msg_ram_conf.std_filter[idx].SIDFE_0.reg;
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if (((tmp & CAN_SIDFE_0_SFEC_Msk) >> CAN_SIDFE_0_SFEC_Pos) ==
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CANDEV_SAMD5X_FILTER_DISABLE)
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{
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DEBUG_PUTS("empty slot");
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break;
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}
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@ -565,11 +581,12 @@ static int _set_filter(candev_t *candev, const struct can_filter *filter)
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}
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DEBUG("Standard Filter to add at idx = %d\n", idx);
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dev->msg_ram_conf.std_filter[idx].SIDFE_0.bit.SFEC = filter_conf;
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/* For now, only CLASSIC filters are supported */
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dev->msg_ram_conf.std_filter[idx].SIDFE_0.bit.SFT = CANDEV_SAMD5X_CLASSIC_FILTER;
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dev->msg_ram_conf.std_filter[idx].SIDFE_0.bit.SFID1 = filter->can_id & CAN_SFF_MASK;
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dev->msg_ram_conf.std_filter[idx].SIDFE_0.bit.SFID2 = filter->can_mask & CAN_SFF_MASK;
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dev->msg_ram_conf.std_filter[idx].SIDFE_0.reg = CAN_SIDFE_0_SFEC(filter_conf)
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| CAN_SIDFE_0_SFT(CANDEV_SAMD5X_CLASSIC_FILTER)
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| CAN_SIDFE_0_SFID1(filter->can_id & CAN_SFF_MASK)
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| CAN_SIDFE_0_SFID2(filter->can_mask & CAN_SFF_MASK);
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DEBUG("Standard filter element N°%d: S0 = 0x%08lx\n", idx,
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(uint32_t)(dev->msg_ram_conf.std_filter[idx].SIDFE_0.reg));
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_set_mode(dev->conf->can, MODE_INIT);
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@ -590,7 +607,7 @@ static int _remove_filter(candev_t *candev, const struct can_filter *filter)
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idx = _find_filter(dev, filter, false);
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if (idx != -1) {
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DEBUG("Extended filter to disable at idx = %d\n", idx);
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dev->msg_ram_conf.ext_filter[idx].XIDFE_0.bit.EFEC = CANDEV_SAMD5X_FILTER_DISABLE;
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dev->msg_ram_conf.ext_filter[idx].XIDFE_0.reg &= ~CAN_XIDFE_0_EFEC_Msk;
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}
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else {
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DEBUG_PUTS("Filter not found");
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@ -601,7 +618,7 @@ static int _remove_filter(candev_t *candev, const struct can_filter *filter)
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idx = _find_filter(dev, filter, true);
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if (idx != -1) {
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DEBUG("Standard filter to disable at idx = %d\n", idx);
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dev->msg_ram_conf.std_filter[idx].SIDFE_0.bit.SFEC = CANDEV_SAMD5X_FILTER_DISABLE;
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dev->msg_ram_conf.std_filter[idx].SIDFE_0.reg &= ~CAN_SIDFE_0_SFEC_Msk;
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}
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else {
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DEBUG_PUTS("Filter not found");
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@ -708,26 +725,30 @@ static void _isr(candev_t *candev)
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uint16_t rx_get_idx = 0;
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uint16_t rx_put_idx = 0;
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rx_get_idx = (dev->conf->can->RXF0S.reg >> CAN_RXF0S_F0GI_Pos) & 0x3F;
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uint32_t reg = dev->conf->can->RXF0S.reg;
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rx_get_idx = (reg >> CAN_RXF0S_F0GI_Pos) & 0x3F;
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DEBUG("rx get index = %u\n", rx_get_idx);
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rx_put_idx = (dev->conf->can->RXF0S.reg >> CAN_RXF0S_F0PI_Pos) & 0x3F;
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rx_put_idx = (reg >> CAN_RXF0S_F0PI_Pos) & 0x3F;
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DEBUG("rx put index = %u\n", rx_put_idx);
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struct can_frame frame_received = {0};
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if (!dev->msg_ram_conf.rx_fifo_0[rx_get_idx].RXF0E_0.bit.XTD) {
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/* Reuse variable to avoid multiple read of the same register */
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reg = dev->msg_ram_conf.rx_fifo_0[rx_get_idx].RXF0E_0.reg;
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if (!(reg & CAN_RXF0E_0_XTD)) {
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DEBUG_PUTS("Received standard CAN frame");
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frame_received.can_id = dev->msg_ram_conf.rx_fifo_0[rx_get_idx].RXF0E_0.bit.ID >> 18;
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frame_received.can_id = (reg & CAN_RXF0E_0_ID_Msk) >> 18;
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}
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else {
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DEBUG_PUTS("Received extended CAN frame");
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frame_received.can_id = dev->msg_ram_conf.rx_fifo_0[rx_get_idx].RXF0E_0.bit.ID;
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frame_received.can_id |= CAN_EFF_FLAG;
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frame_received.can_id = (reg & CAN_RXF0E_0_ID_Msk) | CAN_EFF_FLAG;
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}
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if (dev->msg_ram_conf.rx_fifo_0[rx_get_idx].RXF0E_0.bit.RTR) {
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if (reg & CAN_RXF0E_0_RTR) {
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frame_received.can_id |= CAN_RTR_FLAG;
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}
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frame_received.can_dlc = dev->msg_ram_conf.rx_fifo_0[rx_get_idx].RXF0E_1.bit.DLC;
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frame_received.can_dlc =
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(dev->msg_ram_conf.rx_fifo_0[rx_get_idx].RXF0E_1.reg & CAN_RXF0E_1_DLC_Msk) >>
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CAN_RXF0E_1_DLC_Pos;
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memcpy(frame_received.data, (uint32_t *)dev->msg_ram_conf.rx_fifo_0[rx_get_idx].RXF0E_DATA, frame_received.can_dlc);
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dev->conf->can->RXF0A.reg = CAN_RXF0A_F0AI(rx_get_idx);
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@ -744,26 +765,30 @@ static void _isr(candev_t *candev)
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uint16_t rx_get_idx = 0;
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uint16_t rx_put_idx = 0;
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rx_get_idx = (dev->conf->can->RXF1S.reg >> CAN_RXF1S_F1GI_Pos) & 0x3F;
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uint32_t reg = dev->conf->can->RXF1S.reg;
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rx_get_idx = (reg >> CAN_RXF1S_F1GI_Pos) & 0x3F;
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DEBUG("rx get index = %u\n", rx_get_idx);
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rx_put_idx = (dev->conf->can->RXF1S.reg >> CAN_RXF1S_F1PI_Pos) & 0x3F;
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rx_put_idx = (reg >> CAN_RXF1S_F1PI_Pos) & 0x3F;
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DEBUG("rx put index = %u\n", rx_put_idx);
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struct can_frame frame_received = {0};
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if (!dev->msg_ram_conf.rx_fifo_1[rx_get_idx].RXF1E_0.bit.XTD) {
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/* Reuse variable to avoid multiple read of the same register */
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reg = dev->msg_ram_conf.rx_fifo_1[rx_get_idx].RXF1E_0.reg;
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if (!(reg & CAN_RXF1E_0_XTD)) {
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DEBUG_PUTS("Received standard CAN frame");
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frame_received.can_id = dev->msg_ram_conf.rx_fifo_1[rx_get_idx].RXF1E_0.bit.ID >> 18;
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frame_received.can_id = (reg & CAN_RXF1E_0_ID_Msk) >> 18;
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}
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else {
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DEBUG_PUTS("Received extended CAN frame");
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frame_received.can_id = dev->msg_ram_conf.rx_fifo_1[rx_get_idx].RXF1E_0.bit.ID;
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frame_received.can_id |= CAN_EFF_FLAG;
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frame_received.can_id = ((reg & CAN_RXF1E_0_ID_Msk) | CAN_EFF_FLAG);
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}
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if (dev->msg_ram_conf.rx_fifo_1[rx_get_idx].RXF1E_0.bit.RTR) {
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if (reg & CAN_RXF1E_0_RTR) {
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frame_received.can_id |= CAN_RTR_FLAG;
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}
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frame_received.can_dlc = dev->msg_ram_conf.rx_fifo_1[rx_get_idx].RXF1E_1.bit.DLC;
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frame_received.can_dlc =
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(dev->msg_ram_conf.rx_fifo_1[rx_get_idx].RXF1E_1.reg & CAN_RXF1E_1_DLC_Msk) >>
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CAN_RXF1E_1_DLC_Pos;
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memcpy(frame_received.data, (uint32_t *)dev->msg_ram_conf.rx_fifo_1[rx_get_idx].RXF1E_DATA, frame_received.can_dlc);
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dev->conf->can->RXF1A.reg = CAN_RXF1A_F1AI(rx_get_idx);
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@ -787,12 +812,13 @@ static void _isr(candev_t *candev)
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DEBUG_PUTS("protocol error in data phase");
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dev->conf->can->IR.reg |= CAN_IR_PED;
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/* Extract the Tx and Rx error counters */
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uint8_t tx_err_cnt = (uint8_t)dev->conf->can->ECR.bit.TEC;
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uint32_t reg = dev->conf->can->ECR.reg;
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uint8_t tx_err_cnt = (uint8_t) (reg & CAN_ECR_TEC_Msk);
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DEBUG("tx error counter = %u\n", tx_err_cnt);
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uint8_t rx_err_cnt = (uint8_t)dev->conf->can->ECR.bit.REC;
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uint8_t rx_err_cnt = (uint8_t)((reg & CAN_ECR_REC_Msk) >> CAN_ECR_REC_Pos);
|
||||
DEBUG("rx error counter = %u\n", rx_err_cnt);
|
||||
/* Check the CAN error type */
|
||||
uint8_t error_code = (uint8_t)dev->conf->can->PSR.bit.LEC;
|
||||
uint8_t error_code = (uint8_t)(dev->conf->can->PSR.reg & CAN_PSR_LEC_Msk);
|
||||
DEBUG("error code = %u\n", error_code);
|
||||
if (error_code == CANDEV_SAMD5X_NO_CHANGE_ERROR) {
|
||||
error_code = last_error_code;
|
||||
@ -847,12 +873,13 @@ static void _isr(candev_t *candev)
|
||||
DEBUG_PUTS("protocol error in arbitration phase");
|
||||
dev->conf->can->IR.reg |= CAN_IR_PEA;
|
||||
/* Extract the Tx and Rx error counters */
|
||||
uint8_t tx_err_cnt = (uint8_t)dev->conf->can->ECR.bit.TEC;
|
||||
uint32_t reg = dev->conf->can->ECR.reg;
|
||||
uint8_t tx_err_cnt = (uint8_t) (reg & CAN_ECR_TEC_Msk);
|
||||
DEBUG("tx error counter = %u\n", tx_err_cnt);
|
||||
uint8_t rx_err_cnt = (uint8_t)dev->conf->can->ECR.bit.REC;
|
||||
uint8_t rx_err_cnt = (uint8_t)((reg & CAN_ECR_REC_Msk) >> CAN_ECR_REC_Pos);
|
||||
DEBUG("rx error counter = %u\n", rx_err_cnt);
|
||||
/* Check the CAN error type */
|
||||
uint8_t error_code = (uint8_t)dev->conf->can->PSR.bit.LEC;
|
||||
uint8_t error_code = (uint8_t)(dev->conf->can->PSR.reg & CAN_PSR_LEC_Msk);
|
||||
DEBUG("error code = %u\n", error_code);
|
||||
if (error_code == CANDEV_SAMD5X_NO_CHANGE_ERROR) {
|
||||
error_code = last_error_code;
|
||||
|
||||
@ -55,9 +55,9 @@ void pm_set(unsigned mode)
|
||||
}
|
||||
|
||||
/* write sleep configuration */
|
||||
PM->SLEEPCFG.bit.SLEEPMODE = _mode;
|
||||
PM->SLEEPCFG.reg = _mode;
|
||||
/* make sure value has been set */
|
||||
while (PM->SLEEPCFG.bit.SLEEPMODE != _mode) {}
|
||||
while ((PM->SLEEPCFG.reg & PM_SLEEPCFG_SLEEPMODE_Msk) != _mode) {}
|
||||
|
||||
sam0_cortexm_sleep(deep);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user