RIOT-OS/RIOT
RIOT-OS/RIOT
1
0
Fork 0
mirror of https://github.com/RIOT-OS/RIOT.git synced 2025-01-18 12:52:44 +01:00
Code Releases Activity

cpu/stm32-common: add RTC support to stm32l0

Browse Source 
Signed-off-by: joris <laborde.joris@gmail.com>
This commit is contained in:
joris 2017-06-02 20:03:09 +02:00
parent 3cdb92aaf4
commit 6a5da1c1f7
1 changed files with 15 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
cpu/stm32_common/periph/rtc.c
View File

@ -27,7 +27,8 @@
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F2) || \ #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F2) || \
defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32F4) || \ defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32F4) || \
defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L1) defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L0) || \
defined(CPU_FAM_STM32L1)
/* guard file in case no RTC device was specified */ /* guard file in case no RTC device was specified */
#if RTC_NUMOF #if RTC_NUMOF
@ -65,7 +66,7 @@ void rtc_init(void)
PWR->CR |= PWR_CR_DBP; PWR->CR |= PWR_CR_DBP;
#endif #endif
#if defined(CPU_FAM_STM32L1) #if defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32L0)
if (!(RCC->CSR & RCC_CSR_RTCEN)) { if (!(RCC->CSR & RCC_CSR_RTCEN)) {
#else #else
if (!(RCC->BDCR & RCC_BDCR_RTCEN)) { if (!(RCC->BDCR & RCC_BDCR_RTCEN)) {
@ -192,9 +193,15 @@ int rtc_set_alarm(struct tm *time, rtc_alarm_cb_t cb, void *arg)
/* Enable RTC write protection */ /* Enable RTC write protection */
RTC->WPR = 0xFF; RTC->WPR = 0xFF;
#if defined(CPU_FAM_STM32L0)
EXTI->IMR |= EXTI_IMR_IM17;
#else
EXTI->IMR |= EXTI_IMR_MR17; EXTI->IMR |= EXTI_IMR_MR17;
#endif
EXTI->RTSR |= EXTI_RTSR_TR17; EXTI->RTSR |= EXTI_RTSR_TR17;
#if defined(CPU_FAM_STM32F0)
#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0)
NVIC_SetPriority(RTC_IRQn, 10); NVIC_SetPriority(RTC_IRQn, 10);
NVIC_EnableIRQ(RTC_IRQn); NVIC_EnableIRQ(RTC_IRQn);
#else #else
@ -235,7 +242,7 @@ void rtc_clear_alarm(void)
void rtc_poweron(void) void rtc_poweron(void)
{ {
#if defined(CPU_FAM_STM32L1) #if defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32L0)
/* Reset RTC domain */ /* Reset RTC domain */
RCC->CSR |= RCC_CSR_RTCRST; RCC->CSR |= RCC_CSR_RTCRST;
RCC->CSR &= ~(RCC_CSR_RTCRST); RCC->CSR &= ~(RCC_CSR_RTCRST);
@ -274,7 +281,7 @@ void rtc_poweron(void)
void rtc_poweroff(void) void rtc_poweroff(void)
{ {
#if defined(CPU_FAM_STM32L1) #if defined(CPU_FAM_STM32L1) || defined(CPU_FAM_STM32L0)
/* Reset RTC domain */ /* Reset RTC domain */
RCC->CSR |= RCC_CSR_RTCRST; RCC->CSR |= RCC_CSR_RTCRST;
RCC->CSR &= ~(RCC_CSR_RTCRST); RCC->CSR &= ~(RCC_CSR_RTCRST);
@ -293,7 +300,7 @@ void rtc_poweroff(void)
#endif #endif
} }
#if defined(CPU_FAM_STM32F0) #if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0)
void isr_rtc(void) void isr_rtc(void)
#else #else
void isr_rtc_alarm(void) void isr_rtc_alarm(void)
@ -331,4 +338,5 @@ static uint8_t byte2bcd(uint8_t value)
#endif /* defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F2) || \ #endif /* defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F2) || \
defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32F4) || \ defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32F4) || \
defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L1) */ defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L0) || \
defined(CPU_FAM_STM32L1) */