mirror of
https://github.com/RIOT-OS/RIOT.git
synced 2024-12-29 04:50:03 +01:00
cpu/nrfxx: move I2C/SPI/UART structs to nrf5x_common
This will reduces code duplication across nRF52,nRF53 and nRF9160 families Signed-off-by: Dylan Laduranty <dylan.laduranty@mesotic.com>
This commit is contained in:
Dylan Laduranty
dylad
parent
9a46bcdbe7
commit
63310189a5
@ -27,14 +27,6 @@
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extern "C" {
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#endif
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/**
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* @brief Enable the workaround for the SPI single byte transmit errata (No.
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* 58 on the nrf52832)
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*/
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#ifdef CPU_MODEL_NRF52832XXAA
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#define ERRATA_SPI_SINGLE_BYTE_WORKAROUND (1)
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#endif
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/**
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* @brief System core clock speed, fixed to 64MHz for all NRF52x CPUs
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*/
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@ -45,18 +37,6 @@ extern "C" {
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*/
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#define PERIPH_CLOCK (16000000U)
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/**
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* @brief Redefine some peripheral names to unify them between nRF51 and 52
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* @{
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*/
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#define SPI_SCKSEL (dev(bus)->PSEL.SCK)
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#define SPI_MOSISEL (dev(bus)->PSEL.MOSI)
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#define SPI_MISOSEL (dev(bus)->PSEL.MISO)
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#ifdef CPU_MODEL_NRF52832XXAA
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#define UART_IRQN (UARTE0_UART0_IRQn)
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#endif
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/** @} */
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/**
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* @brief The nRF52 family of CPUs provides a fixed number of 9 ADC lines
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*/
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@ -66,14 +46,6 @@ extern "C" {
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#define ADC_NUMOF (9U)
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#endif
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/**
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* @brief SPI temporary buffer size for storing const data in RAM before
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* initiating DMA transfer
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*/
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#ifndef CONFIG_SPI_MBUF_SIZE
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#define CONFIG_SPI_MBUF_SIZE 64
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#endif
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/**
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* @brief nRF52 specific naming of ADC lines (for convenience)
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*/
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@ -109,50 +81,6 @@ typedef enum {
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/** @} */
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#endif /* ndef DOXYGEN */
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#ifndef DOXYGEN
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/**
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* @brief Override I2C speed settings
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* @{
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*/
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#define HAVE_I2C_SPEED_T
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typedef enum {
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I2C_SPEED_LOW = 0xff, /**< not supported */
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I2C_SPEED_NORMAL = TWIM_FREQUENCY_FREQUENCY_K100, /**< 100kbit/s */
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I2C_SPEED_FAST = TWIM_FREQUENCY_FREQUENCY_K400, /**< 400kbit/s */
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I2C_SPEED_FAST_PLUS = 0xfe, /**< not supported */
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I2C_SPEED_HIGH = 0xfd, /**< not supported */
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} i2c_speed_t;
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/** @} */
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#endif /* ndef DOXYGEN */
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/**
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* @brief I2C (TWI) configuration options
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* @{
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*/
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typedef struct {
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NRF_TWIM_Type *dev; /**< TWIM hardware device */
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gpio_t scl; /**< SCL pin */
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gpio_t sda; /**< SDA pin */
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i2c_speed_t speed; /**< Bus speed */
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} i2c_conf_t;
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/** @} */
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/**
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* @name Use shared I2C functions
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* @{
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*/
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#define PERIPH_I2C_NEED_READ_REG
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#define PERIPH_I2C_NEED_WRITE_REG
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/** @} */
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/**
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* @name Define macros for sda and scl pin to be able to reinitialize them
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* @{
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*/
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#define i2c_pin_sda(dev) i2c_config[dev].sda
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#define i2c_pin_scl(dev) i2c_config[dev].scl
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/** @} */
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/**
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* @brief Size of the UART TX buffer for non-blocking mode.
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*/
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@ -160,19 +88,6 @@ typedef struct {
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#define UART_TXBUF_SIZE (64)
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#endif
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/**
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* @brief SPI configuration values
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*/
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typedef struct {
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NRF_SPIM_Type *dev; /**< SPI device used */
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gpio_t sclk; /**< CLK pin */
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gpio_t mosi; /**< MOSI pin */
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gpio_t miso; /**< MISO pin */
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#if ERRATA_SPI_SINGLE_BYTE_WORKAROUND
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uint8_t ppi; /**< PPI channel */
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#endif
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} spi_conf_t;
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/**
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* @brief Common SPI/I2C interrupt callback
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*
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@ -31,6 +31,15 @@ extern "C" {
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#ifdef NRF_FICR_S
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#define NRF_FICR NRF_FICR_S
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#endif
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/**
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* @brief Enable the workaround for the SPI single byte transmit errata (No.
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* 58 on the nrf52832)
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*/
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#ifdef CPU_MODEL_NRF52832XXAA
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#define ERRATA_SPI_SINGLE_BYTE_WORKAROUND (1)
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#endif
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/**
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* @name Power management configuration
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* @{
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@ -136,6 +145,38 @@ typedef enum {
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} gpio_pull_t;
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#endif /* END: GPIO LL overwrites */
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#if !defined(DOXYGEN) && (defined(CPU_NRF53) || defined(CPU_NRF9160))
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/**
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* @brief Wrapper to fix differences between nRF families vendor files
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*/
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#define UART_BAUDRATE_BAUDRATE_Baud1200 UARTE_BAUDRATE_BAUDRATE_Baud1200
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#define UART_BAUDRATE_BAUDRATE_Baud2400 UARTE_BAUDRATE_BAUDRATE_Baud2400
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#define UART_BAUDRATE_BAUDRATE_Baud4800 UARTE_BAUDRATE_BAUDRATE_Baud4800
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#define UART_BAUDRATE_BAUDRATE_Baud9600 UARTE_BAUDRATE_BAUDRATE_Baud9600
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#define UART_BAUDRATE_BAUDRATE_Baud14400 UARTE_BAUDRATE_BAUDRATE_Baud14400
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#define UART_BAUDRATE_BAUDRATE_Baud19200 UARTE_BAUDRATE_BAUDRATE_Baud19200
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#define UART_BAUDRATE_BAUDRATE_Baud28800 UARTE_BAUDRATE_BAUDRATE_Baud28800
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#define UART_BAUDRATE_BAUDRATE_Baud31250 UARTE_BAUDRATE_BAUDRATE_Baud31250
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#define UART_BAUDRATE_BAUDRATE_Baud38400 UARTE_BAUDRATE_BAUDRATE_Baud38400
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#define UART_BAUDRATE_BAUDRATE_Baud56000 UARTE_BAUDRATE_BAUDRATE_Baud56000
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#define UART_BAUDRATE_BAUDRATE_Baud57600 UARTE_BAUDRATE_BAUDRATE_Baud57600
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#define UART_BAUDRATE_BAUDRATE_Baud76800 UARTE_BAUDRATE_BAUDRATE_Baud76800
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#define UART_BAUDRATE_BAUDRATE_Baud115200 UARTE_BAUDRATE_BAUDRATE_Baud115200
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#define UART_BAUDRATE_BAUDRATE_Baud230400 UARTE_BAUDRATE_BAUDRATE_Baud230400
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#define UART_BAUDRATE_BAUDRATE_Baud250000 UARTE_BAUDRATE_BAUDRATE_Baud250000
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#define UART_BAUDRATE_BAUDRATE_Baud460800 UARTE_BAUDRATE_BAUDRATE_Baud460800
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#define UART_BAUDRATE_BAUDRATE_Baud921600 UARTE_BAUDRATE_BAUDRATE_Baud921600
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#define UART_BAUDRATE_BAUDRATE_Baud1M UARTE_BAUDRATE_BAUDRATE_Baud1M
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#define SPI_FREQUENCY_FREQUENCY_K125 SPIM_FREQUENCY_FREQUENCY_K125
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#define SPI_FREQUENCY_FREQUENCY_K500 SPIM_FREQUENCY_FREQUENCY_K500
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#define SPI_FREQUENCY_FREQUENCY_M1 SPIM_FREQUENCY_FREQUENCY_M1
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#define SPI_FREQUENCY_FREQUENCY_M4 SPIM_FREQUENCY_FREQUENCY_M4
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#define SPI_FREQUENCY_FREQUENCY_M8 SPIM_FREQUENCY_FREQUENCY_M8
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#define SPI_CONFIG_CPHA_Msk SPIM_CONFIG_CPHA_Msk
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#define SPI_CONFIG_CPOL_Msk SPIM_CONFIG_CPOL_Msk
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#endif
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/**
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* @brief No support for HW chip select...
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*/
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@ -221,7 +262,6 @@ typedef struct {
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* @brief Override SPI mode values
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* @{
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*/
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#if !defined(CPU_FAM_NRF9160) && !defined(CPU_FAM_NRF53)
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#define HAVE_SPI_MODE_T
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typedef enum {
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SPI_MODE_0 = 0, /**< CPOL=0, CPHA=0 */
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@ -244,7 +284,6 @@ typedef enum {
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SPI_CLK_10MHZ = SPI_FREQUENCY_FREQUENCY_M8 /**< 10MHz */
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} spi_clk_t;
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/** @} */
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#endif /* ndef CPU_FAM_NRF9160 */
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#endif /* ndef DOXYGEN */
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/**
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@ -360,6 +399,159 @@ typedef struct {
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} pwm_conf_t;
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#endif
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#endif /* ndef CPU_FAM_NRF51 */
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#ifndef CPU_NRF51
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/**
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* @brief Redefine some peripheral names to unify them across nRF families
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*/
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#define SPI_SCKSEL (dev(bus)->PSEL.SCK) /**< Macro for SPI clk */
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#define SPI_MOSISEL (dev(bus)->PSEL.MOSI) /**< Macro for SPI mosi */
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#define SPI_MISOSEL (dev(bus)->PSEL.MISO) /**< Macro for SPI miso */
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#ifdef CPU_MODEL_NRF52832XXAA
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#define UART_IRQN (UARTE0_UART0_IRQn)
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#endif
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/**
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* @brief SPI configuration values
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*/
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typedef struct {
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NRF_SPIM_Type *dev; /**< SPI device used */
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gpio_t sclk; /**< CLK pin */
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gpio_t mosi; /**< MOSI pin */
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gpio_t miso; /**< MISO pin */
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#if ERRATA_SPI_SINGLE_BYTE_WORKAROUND
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uint8_t ppi; /**< PPI channel */
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#endif
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} spi_conf_t;
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/**
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* @brief Common UART/SPI/I2C interrupt callback
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*
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* @param arg Opaque context pointer
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*/
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typedef void (*shared_irq_cb_t)(void *arg);
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/**
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* @brief Register a SPI IRQ handler for a shared UART/I2C/SPI irq vector
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*
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* @param bus bus to register the IRQ handler on
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* @param cb callback to call on IRQ
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* @param arg Argument to pass to the handler
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*/
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void shared_irq_register_spi(NRF_SPIM_Type *bus,
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shared_irq_cb_t cb, void *arg);
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/**
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* @brief Register an I2C IRQ handler for a shared UART/I2C/SPI irq vector
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*
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* @param bus bus to register the IRQ handler on
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* @param cb callback to call on IRQ
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* @param arg Argument to pass to the handler
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*/
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void shared_irq_register_i2c(NRF_TWIM_Type *bus,
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shared_irq_cb_t cb, void *arg);
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/**
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* @brief Register an UART IRQ handler for a shared UART/I2C/SPI irq vector
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*
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* @param bus bus to register the IRQ handler on
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* @param cb callback to call on IRQ
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* @param arg Argument to pass to the handler
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*/
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void shared_irq_register_uart(NRF_UARTE_Type *bus,
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shared_irq_cb_t cb, void *arg);
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/**
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* @brief Acquire the shared I2C/SPI peripheral in I2C mode
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*
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* @param bus bus to acquire exclusive access on
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* @param cb ISR handler to call on IRQ
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* @param arg ISR handler argument
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*/
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void nrf5x_i2c_acquire(NRF_TWIM_Type *bus, shared_irq_cb_t cb, void *arg);
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/**
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* @brief Release the shared I2C/SPI peripheral in I2C mode
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*
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* @param bus bus to release exclusive access on
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*/
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void nrf5x_i2c_release(NRF_TWIM_Type *bus);
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/**
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* @brief Acquire the shared I2C/SPI peripheral in SPI mode
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*
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* @param bus bus to release exclusive access on
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* @param cb ISR handler to call on IRQ
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* @param arg ISR handler argument
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*/
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void nrf5x_spi_acquire(NRF_SPIM_Type *bus, shared_irq_cb_t cb, void *arg);
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/**
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* @brief Acquire the shared I2C/SPI peripheral in SPI mode
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*
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* @param bus bus to release exclusive access on
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*/
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void nrf5x_spi_release(NRF_SPIM_Type *bus);
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/**
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* @brief Size of the UART TX buffer for non-blocking mode.
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*/
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#ifndef UART_TXBUF_SIZE
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#define UART_TXBUF_SIZE (64)
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#endif
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/**
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* @brief SPI temporary buffer size for storing const data in RAM before
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* initiating DMA transfer
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*/
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#ifndef CONFIG_SPI_MBUF_SIZE
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#define CONFIG_SPI_MBUF_SIZE 64
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#endif
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#ifndef DOXYGEN
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/**
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* @brief Override I2C speed settings
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* @{
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*/
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#define HAVE_I2C_SPEED_T
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typedef enum {
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I2C_SPEED_LOW = 0xff, /**< not supported */
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I2C_SPEED_NORMAL = TWIM_FREQUENCY_FREQUENCY_K100, /**< 100kbit/s */
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I2C_SPEED_FAST = TWIM_FREQUENCY_FREQUENCY_K400, /**< 400kbit/s */
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I2C_SPEED_FAST_PLUS = 0xfe, /**< not supported */
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I2C_SPEED_HIGH = 0xfd, /**< not supported */
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} i2c_speed_t;
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/** @} */
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#endif /* ndef DOXYGEN */
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/**
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* @brief I2C (TWI) configuration options
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* @{
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*/
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typedef struct {
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NRF_TWIM_Type *dev; /**< TWIM hardware device */
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gpio_t scl; /**< SCL pin */
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gpio_t sda; /**< SDA pin */
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i2c_speed_t speed; /**< Bus speed */
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} i2c_conf_t;
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/** @} */
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/**
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* @name Use shared I2C functions
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* @{
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*/
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#define PERIPH_I2C_NEED_READ_REG
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#define PERIPH_I2C_NEED_WRITE_REG
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/** @} */
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/**
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* @name Define macros for sda and scl pin to be able to reinitialize them
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* @{
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*/
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#define i2c_pin_sda(dev) i2c_config[dev].sda /**< Macro for getting SDA pin */
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#define i2c_pin_scl(dev) i2c_config[dev].scl /**< Macro for getting SCL pin */
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/** @} */
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#endif /* ndef CPU_NRF51 */
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#ifdef __cplusplus
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}
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@ -36,189 +36,6 @@ extern "C" {
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*/
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#define PERIPH_CLOCK MHZ(16)
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#ifndef DOXYGEN
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/**
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* @brief Wrapper to fix differences between nRF9160 and
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* nRF52 vendor files
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*/
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#define UART_BAUDRATE_BAUDRATE_Baud1200 UARTE_BAUDRATE_BAUDRATE_Baud1200
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#define UART_BAUDRATE_BAUDRATE_Baud2400 UARTE_BAUDRATE_BAUDRATE_Baud2400
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#define UART_BAUDRATE_BAUDRATE_Baud4800 UARTE_BAUDRATE_BAUDRATE_Baud4800
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#define UART_BAUDRATE_BAUDRATE_Baud9600 UARTE_BAUDRATE_BAUDRATE_Baud9600
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#define UART_BAUDRATE_BAUDRATE_Baud14400 UARTE_BAUDRATE_BAUDRATE_Baud14400
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#define UART_BAUDRATE_BAUDRATE_Baud19200 UARTE_BAUDRATE_BAUDRATE_Baud19200
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#define UART_BAUDRATE_BAUDRATE_Baud28800 UARTE_BAUDRATE_BAUDRATE_Baud28800
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#define UART_BAUDRATE_BAUDRATE_Baud31250 UARTE_BAUDRATE_BAUDRATE_Baud31250
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#define UART_BAUDRATE_BAUDRATE_Baud38400 UARTE_BAUDRATE_BAUDRATE_Baud38400
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#define UART_BAUDRATE_BAUDRATE_Baud56000 UARTE_BAUDRATE_BAUDRATE_Baud56000
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#define UART_BAUDRATE_BAUDRATE_Baud57600 UARTE_BAUDRATE_BAUDRATE_Baud57600
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#define UART_BAUDRATE_BAUDRATE_Baud76800 UARTE_BAUDRATE_BAUDRATE_Baud76800
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#define UART_BAUDRATE_BAUDRATE_Baud115200 UARTE_BAUDRATE_BAUDRATE_Baud115200
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#define UART_BAUDRATE_BAUDRATE_Baud230400 UARTE_BAUDRATE_BAUDRATE_Baud230400
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#define UART_BAUDRATE_BAUDRATE_Baud250000 UARTE_BAUDRATE_BAUDRATE_Baud250000
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#define UART_BAUDRATE_BAUDRATE_Baud460800 UARTE_BAUDRATE_BAUDRATE_Baud460800
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#define UART_BAUDRATE_BAUDRATE_Baud921600 UARTE_BAUDRATE_BAUDRATE_Baud921600
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#define UART_BAUDRATE_BAUDRATE_Baud1M UARTE_BAUDRATE_BAUDRATE_Baud1M
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/**
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* @brief Override I2C speed settings
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* @{
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*/
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#define HAVE_I2C_SPEED_T
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typedef enum {
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I2C_SPEED_LOW = 0xff, /**< not supported */
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I2C_SPEED_NORMAL = TWIM_FREQUENCY_FREQUENCY_K100, /**< 100kbit/s */
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I2C_SPEED_FAST = TWIM_FREQUENCY_FREQUENCY_K400, /**< 400kbit/s */
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I2C_SPEED_FAST_PLUS = 0xfe, /**< not supported */
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I2C_SPEED_HIGH = 0xfd, /**< not supported */
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} i2c_speed_t;
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/** @} */
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#endif /* ndef DOXYGEN */
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/**
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* @brief I2C (TWI) configuration options
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* @{
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*/
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typedef struct {
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NRF_TWIM_Type *dev; /**< TWIM hardware device */
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gpio_t scl; /**< SCL pin */
|
||||
gpio_t sda; /**< SDA pin */
|
||||
i2c_speed_t speed; /**< Bus speed */
|
||||
} i2c_conf_t;
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Use shared I2C functions
|
||||
* @{
|
||||
*/
|
||||
#define PERIPH_I2C_NEED_READ_REG
|
||||
#define PERIPH_I2C_NEED_WRITE_REG
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Define macros for sda and scl pin to be able to reinitialize them
|
||||
* @{
|
||||
*/
|
||||
#define i2c_pin_sda(dev) i2c_config[dev].sda
|
||||
#define i2c_pin_scl(dev) i2c_config[dev].scl
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief Defines macros for SPI pins initialization
|
||||
* @{
|
||||
*/
|
||||
#define SPI_SCKSEL (dev(bus)->PSEL.SCK)
|
||||
#define SPI_MOSISEL (dev(bus)->PSEL.MOSI)
|
||||
#define SPI_MISOSEL (dev(bus)->PSEL.MISO)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief SPI temporary buffer size for storing const data in RAM before
|
||||
* initiating DMA transfer
|
||||
*/
|
||||
#ifndef CONFIG_SPI_MBUF_SIZE
|
||||
#define CONFIG_SPI_MBUF_SIZE 64
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief SPI configuration values
|
||||
*/
|
||||
typedef struct {
|
||||
NRF_SPIM_Type *dev; /**< SPI device used */
|
||||
gpio_t sclk; /**< CLK pin */
|
||||
gpio_t mosi; /**< MOSI pin */
|
||||
gpio_t miso; /**< MISO pin */
|
||||
} spi_conf_t;
|
||||
|
||||
#ifndef DOXYGEN
|
||||
/**
|
||||
* @brief Override SPI mode values
|
||||
* @{
|
||||
*/
|
||||
#define HAVE_SPI_MODE_T
|
||||
typedef enum {
|
||||
SPI_MODE_0 = 0, /**< CPOL=0, CPHA=0 */
|
||||
SPI_MODE_1 = SPIM_CONFIG_CPHA_Msk, /**< CPOL=0, CPHA=1 */
|
||||
SPI_MODE_2 = SPIM_CONFIG_CPOL_Msk, /**< CPOL=1, CPHA=0 */
|
||||
SPI_MODE_3 = (SPIM_CONFIG_CPOL_Msk | SPIM_CONFIG_CPHA_Msk) /**< CPOL=1, CPHA=1 */
|
||||
} spi_mode_t;
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief Override SPI clock values
|
||||
* @{
|
||||
*/
|
||||
#define HAVE_SPI_CLK_T
|
||||
typedef enum {
|
||||
SPI_CLK_100KHZ = SPIM_FREQUENCY_FREQUENCY_K125, /**< 100KHz */
|
||||
SPI_CLK_400KHZ = SPIM_FREQUENCY_FREQUENCY_K500, /**< 400KHz */
|
||||
SPI_CLK_1MHZ = SPIM_FREQUENCY_FREQUENCY_M1, /**< 1MHz */
|
||||
SPI_CLK_5MHZ = SPIM_FREQUENCY_FREQUENCY_M4, /**< 5MHz */
|
||||
SPI_CLK_10MHZ = SPIM_FREQUENCY_FREQUENCY_M8 /**< 10MHz */
|
||||
} spi_clk_t;
|
||||
/** @} */
|
||||
#endif /* ndef DOXYGEN */
|
||||
|
||||
/**
|
||||
* @brief Common SPI/I2C interrupt callback
|
||||
*
|
||||
* @param arg Opaque context pointer
|
||||
*/
|
||||
typedef void (*spi_twi_irq_cb_t)(void *arg);
|
||||
|
||||
/**
|
||||
* @brief Register a SPI IRQ handler for a shared I2C/SPI irq vector
|
||||
*
|
||||
* @param bus bus to register the IRQ handler on
|
||||
* @param cb callback to call on IRQ
|
||||
* @param arg Argument to pass to the handler
|
||||
*/
|
||||
void spi_twi_irq_register_spi(NRF_SPIM_Type *bus,
|
||||
spi_twi_irq_cb_t cb, void *arg);
|
||||
|
||||
/**
|
||||
* @brief Register a I2C IRQ handler for a shared I2C/SPI irq vector
|
||||
*
|
||||
* @param bus bus to register the IRQ handler on
|
||||
* @param cb callback to call on IRQ
|
||||
* @param arg Argument to pass to the handler
|
||||
*/
|
||||
void spi_twi_irq_register_i2c(NRF_TWIM_Type *bus,
|
||||
spi_twi_irq_cb_t cb, void *arg);
|
||||
|
||||
/**
|
||||
* @brief Acquire the shared I2C/SPI peripheral in I2C mode
|
||||
*
|
||||
* @param bus bus to acquire exclusive access on
|
||||
* @param cb ISR handler to call on IRQ
|
||||
* @param arg ISR handler argument
|
||||
*/
|
||||
void nrf5x_i2c_acquire(NRF_TWIM_Type *bus, spi_twi_irq_cb_t cb, void *arg);
|
||||
|
||||
/**
|
||||
* @brief Release the shared I2C/SPI peripheral in I2C mode
|
||||
*
|
||||
* @param bus bus to release exclusive access on
|
||||
*/
|
||||
void nrf5x_i2c_release(NRF_TWIM_Type *bus);
|
||||
|
||||
/**
|
||||
* @brief Acquire the shared I2C/SPI peripheral in SPI mode
|
||||
*
|
||||
* @param bus bus to release exclusive access on
|
||||
* @param cb ISR handler to call on IRQ
|
||||
* @param arg ISR handler argument
|
||||
*/
|
||||
void nrf5x_spi_acquire(NRF_SPIM_Type *bus, spi_twi_irq_cb_t cb, void *arg);
|
||||
|
||||
/**
|
||||
* @brief Acquire the shared I2C/SPI peripheral in SPI mode
|
||||
*
|
||||
* @param bus bus to release exclusive access on
|
||||
*/
|
||||
void nrf5x_spi_release(NRF_SPIM_Type *bus);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user