From 619dd9ee3b49692b8a6773a0d1b5313e602b62dd Mon Sep 17 00:00:00 2001 From: kenrabold Date: Mon, 16 Apr 2018 10:07:04 -0700 Subject: [PATCH] board/hifive1: add RISC-V board HiFive1 Add new RISC-V board HiFive1 from SiFive based on FE310 CPU --- boards/hifive1/Makefile | 3 + boards/hifive1/Makefile.dep | 1 + boards/hifive1/Makefile.features | 15 ++ boards/hifive1/Makefile.include | 12 ++ boards/hifive1/board.c | 138 ++++++++++++++++ boards/hifive1/dist/flasher.sh | 132 +++++++++++++++ boards/hifive1/dist/openocd.cfg | 44 +++++ boards/hifive1/include/board.h | 67 ++++++++ boards/hifive1/include/periph_conf.h | 102 ++++++++++++ boards/hifive1/include/vendor/LICENSE | 206 ++++++++++++++++++++++++ boards/hifive1/include/vendor/hifive1.h | 78 +++++++++ 11 files changed, 798 insertions(+) create mode 100644 boards/hifive1/Makefile create mode 100644 boards/hifive1/Makefile.dep create mode 100644 boards/hifive1/Makefile.features create mode 100644 boards/hifive1/Makefile.include create mode 100644 boards/hifive1/board.c create mode 100644 boards/hifive1/dist/flasher.sh create mode 100644 boards/hifive1/dist/openocd.cfg create mode 100644 boards/hifive1/include/board.h create mode 100644 boards/hifive1/include/periph_conf.h create mode 100644 boards/hifive1/include/vendor/LICENSE create mode 100644 boards/hifive1/include/vendor/hifive1.h diff --git a/boards/hifive1/Makefile b/boards/hifive1/Makefile new file mode 100644 index 0000000000..f8fcbb53a0 --- /dev/null +++ b/boards/hifive1/Makefile @@ -0,0 +1,3 @@ +MODULE = board + +include $(RIOTBASE)/Makefile.base diff --git a/boards/hifive1/Makefile.dep b/boards/hifive1/Makefile.dep new file mode 100644 index 0000000000..2b839df74c --- /dev/null +++ b/boards/hifive1/Makefile.dep @@ -0,0 +1 @@ +include $(RIOTCPU)/fe310/Makefile.dep diff --git a/boards/hifive1/Makefile.features b/boards/hifive1/Makefile.features new file mode 100644 index 0000000000..b6af178082 --- /dev/null +++ b/boards/hifive1/Makefile.features @@ -0,0 +1,15 @@ +# Put defined MCU peripherals here (in alphabetical order) +FEATURES_PROVIDED += periph_gpio +FEATURES_PROVIDED += periph_pwm +FEATURES_PROVIDED += periph_rtc +FEATURES_PROVIDED += periph_rtt +#FEATURES_PROVIDED += periph_spi +FEATURES_PROVIDED += periph_timer +FEATURES_PROVIDED += periph_uart + +ifneq (,$(filter periph_rtc,$(FEATURES_REQUIRED))) + FEATURES_REQUIRED += periph_rtt +endif + +# The board MPU family (used for grouping by the CI system) +FEATURES_MCU_GROUP = risc_v diff --git a/boards/hifive1/Makefile.include b/boards/hifive1/Makefile.include new file mode 100644 index 0000000000..962c9399c7 --- /dev/null +++ b/boards/hifive1/Makefile.include @@ -0,0 +1,12 @@ +# define the cpu used by the HiFive1 board +export CPU = fe310 +export CPU_MODEL = fe310 + +# Uses UART0 for stdio input/output (comment out to disable) +USEMODULE += uart_stdio + +# this board uses openocd +include $(RIOTMAKE)/tools/openocd.inc.mk + +# use our own openocd script to flash since HiFive1 has reset problems. +export FLASHER = $(RIOTBASE)/boards/hifive1/dist/flasher.sh diff --git a/boards/hifive1/board.c b/boards/hifive1/board.c new file mode 100644 index 0000000000..98b0e91460 --- /dev/null +++ b/boards/hifive1/board.c @@ -0,0 +1,138 @@ +/* + * Copyright (C) 2017 Ken Rabold, JP Bonn + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup boards_hifive HiFive1 + * @{ + * + * @file + * @brief Support for the HiFive1 RISC-V board + * + * @author Ken Rabold, JP Bonn + * + * @} + */ + +#include +#include + +#include "cpu.h" +#include "board.h" +#include "periph/gpio.h" +#include "vendor/encoding.h" +#include "vendor/platform.h" +#include "vendor/prci_driver.h" + +/* + * Configure the memory mapped flash for faster throughput + * to minimize interrupt latency on an I-Cache miss and refill + * from flash. Alternatively (and faster) the interrupt + * routine could be put in SRAM. The linker script supports + * code in SRAM using the ".hotcode" section. + + * The flash chip on the HiFive1 is the ISSI 25LP128 + * http://www.issi.com/WW/pdf/25LP128.pdf + * The maximum frequency it can run at is 133MHz in + * "Fast Read Dual I/O" mode. + * Note the updated data sheet: + * https://static.dev.sifive.com/SiFive-FE310-G000-datasheet-v1.0.4.pdf + * states "Address and write data using DQ[3] for transmission will not + * function properly." This rules out QPI for the XIP memory mapped flash. + * #define MAX_FLASH_FREQ 133000000 + * On forum SiFive says "safe" operation would be 40MHz. 50MHz seems to work + * fine. + */ +#define MAX_FLASH_FREQ 50000000 + +/* + * CPU max is 320MHz+ according to datasheet but + * the relationship between cpu clock and spi clock is determined + * by SCKDIV. Given we're trying to achieve maximum I-cache refill + * for the flash we let MAX_FLASH_FREQ dictate the CPU clock. + */ +#define CPU_DESIRED_FREQ 200000000 + +/* + * The relationship between the input clock and SCK is given + * by the following formula (Fin is processor/tile-link clock): + * Fsck = Fin/(2(div + 1)) + * FYI - For 320MHZ it seems to be tolerating a faster SPI clock (56MHz) + */ +#define SCKDIV ((CPU_DESIRED_FREQ - 1) / (MAX_FLASH_FREQ * 2)) + +/* This should work for any reasonable cpu clock value. */ +#define SCKDIV_SAFE 3 + +/* + * By default the SPI initialized as: + * https://github.com/sifive/sifive-blocks/blob/master/src/main/scala/devices/spi/SPIFlash.scala + * insn.cmd.en := Bool(true) + * insn.cmd.code := Bits(0x03) + * insn.cmd.proto := SPIProtocol.Single + * insn.addr.len := UInt(3) + * insn.addr.proto := SPIProtocol.Single + * insn.pad.cnt := UInt(0) + * insn.pad.code := Bits(0) + * insn.data.proto := SPIProtocol.Single + * + * 25LP128 appears to left in post-reset default state. Boot code + * does not modify it. We change the SPI configuration here. + */ + +void board_init_clock(void) +{ + /* In case we are executing from QSPI, (which is quite likely) we need to + * set the QSPI clock divider appropriately before boosting the clock + * frequency. PRCI_set_hfrosctrim_for_f_cpu() tries multiple clocks + * so choose a safe value that should work for all frequencies. + */ + SPI0_REG(SPI_REG_SCKDIV) = SCKDIV_SAFE; + + /* Note: The range is limited to ~100MHz and depends on PLL settings */ + PRCI_set_hfrosctrim_for_f_cpu(CPU_DESIRED_FREQ, PRCI_FREQ_UNDERSHOOT); + + /* disable uncrustify *INDENT-OFF* */ + SPI0_REG(SPI_REG_FFMT) = /* setup "Fast Read Dual I/O" 1-1-2 */ + SPI_INSN_CMD_EN | /* Enable memory-mapped flash */ + SPI_INSN_ADDR_LEN(3) | /* 25LP128 read commands have 3 address bytes */ + SPI_INSN_PAD_CNT(4) | /* 25LP128 Table 6.9 Read Dummy Cycles P4,P3=0,0 */ + SPI_INSN_CMD_PROTO(SPI_PROTO_S) | /* 25LP128 Table 8.1 "Instruction */ + SPI_INSN_ADDR_PROTO(SPI_PROTO_D) | /* Set" shows mode for cmd, addr, and */ + SPI_INSN_DATA_PROTO(SPI_PROTO_D) | /* data protocol for given instruction */ + SPI_INSN_CMD_CODE(0xbb) | /* Set the instruction to "Fast Read Dual I/O" */ + SPI_INSN_PAD_CODE(0x00); /* Dummy cycle sends 0 value bits */ + /* *INDENT-ON* */ + + SPI0_REG(SPI_REG_SCKDIV) = SCKDIV; +} + +void board_init(void) +{ + /* Initialize CPU and clocks */ + cpu_init(); + board_init_clock(); + + /* Configure pin muxing for UART0 */ + GPIO_REG(GPIO_OUTPUT_VAL) |= IOF0_UART0_MASK; + GPIO_REG(GPIO_OUTPUT_EN) |= IOF0_UART0_MASK; + GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK; + GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK; + + /* Configure GPIOs for LEDs */ + gpio_init(LED0_PIN, GPIO_OUT); + gpio_init(LED1_PIN, GPIO_OUT); + gpio_init(LED2_PIN, GPIO_OUT); + + /* Turn all the LEDs off */ + LED0_OFF; + LED1_OFF; + LED2_OFF; + + /* Initialize newlib-nano library stubs */ + nanostubs_init(); +} diff --git a/boards/hifive1/dist/flasher.sh b/boards/hifive1/dist/flasher.sh new file mode 100644 index 0000000000..df2b36eee5 --- /dev/null +++ b/boards/hifive1/dist/flasher.sh @@ -0,0 +1,132 @@ +#!/bin/sh +# +# Former Unified OpenOCD script for RIOT.. +# This has been modified to not do "reset" or "reset run" commands while +# flashing since the HiFive1 does not support them. +# +# This script is supposed to be called from RIOTs make system, +# as it depends on certain environment variables. An OpenOCD +# configuration file must be present in a the boards dist folder. +# +# Any extra command line arguments after the command name are passed on the +# openocd command line after the configuration file name but before any other +# initialization commands. +# +# Global environment variables used: +# OPENOCD: OpenOCD command name, default: "openocd" +# OPENOCD_CONFIG: OpenOCD configuration file name, +# default: "${RIOTBOARD}/${BOARD}/dist/openocd.cfg" +# +# The script supports the following actions: +# +# flash: flash a given ELF file to the target. +# +# options: +# IMAGE_FILE: Filename of the file that will be flashed +# PRE_FLASH_CHECK_SCRIPT: a command to run before flashing to +# verify the integrity of the image to be flashed. ELFFILE is +# passed as a command line argument to this command. +# Even though the file name variable is named ELFFILE, flashing +# works with any file format recognized by OpenOCD (elf, ihex, s19, bin). +# +# @author Hauke Peteresen +# @author Joakim Nohlgård + +# Default path to OpenOCD configuration file +: ${OPENOCD_CONFIG:=${RIOTBOARD}/${BOARD}/dist/openocd.cfg} +# Default OpenOCD command +: ${OPENOCD:=openocd} +# This is an optional offset to the base address that can be used to flash an +# image in a different location than it is linked at. This feature can be useful +# when flashing images for firmware swapping/remapping boot loaders. +# Default offset is 0, meaning the image will be flashed at the address that it +# was linked at. +: ${IMAGE_OFFSET:=0} +# Image file used for flashing. Must be in a format that OpenOCD can handle (ELF, +# Intel hex, S19, or raw binary) +# Default is to use $ELFFILE +: ${IMAGE_FILE:=${ELFFILE}} +# Type of image, leave empty to let OpenOCD automatically detect the type from +# the file (default). +# Valid values: elf, hex, s19, bin (see OpenOCD manual for more information) +: ${IMAGE_TYPE:=} + +# +# a couple of tests for certain configuration options +# +test_config() { + if [ ! -f "${OPENOCD_CONFIG}" ]; then + echo "Error: Unable to locate OpenOCD configuration file" + echo " (${OPENOCD_CONFIG})" + exit 1 + fi + echo "Using OpenOCD configuration file" + echo " (${OPENOCD_CONFIG})" +} + +test_elffile() { + if [ ! -f "${ELFFILE}" ]; then + echo "Error: Unable to locate ELFFILE" + echo " (${ELFFILE})" + exit 1 + fi +} + +test_imagefile() { + if [ ! -f "${IMAGE_FILE}" ]; then + echo "Error: Unable to locate IMAGE_FILE" + echo " (${IMAGE_FILE})" + exit 1 + fi +} + +# +# now comes the actual actions +# +do_flash() { + test_config + test_imagefile + if [ -n "${PRE_FLASH_CHECK_SCRIPT}" ]; then + sh -c "${PRE_FLASH_CHECK_SCRIPT} '${IMAGE_FILE}'" + RETVAL=$? + if [ $RETVAL -ne 0 ]; then + echo "pre-flash checks failed, status=$RETVAL" + exit $RETVAL + fi + fi + # flash device + echo 'Doing flashing' + + # For some reason 'halt' seems to be more reliable then 'reset halt' at + # getting the HiFive's attention. + sh -c "${OPENOCD} -f '${OPENOCD_CONFIG}' \ + -c 'tcl_port disabled' \ + -c 'telnet_port disabled' \ + -c 'gdb_port disabled' \ + -c 'init' \ + -c 'halt' \ + -c 'flash protect 0 64 last off' \ + -c 'flash write_image erase \"${IMAGE_FILE}\" ${IMAGE_OFFSET} ${IMAGE_TYPE}' \ + -c 'verify_image \"${IMAGE_FILE}\"' \ + -c 'reset halt' \ + -c 'reg pc 0x20000000' \ + -c 'resume' \ + -c 'exit'" && + echo 'Done flashing' +} + +# +# parameter dispatching +# +ACTION="$1" + +case "${ACTION}" in + flash) + echo "### Flashing Target ###" + do_flash + ;; + *) + echo "Usage: $0 flash" + exit 2 + ;; +esac diff --git a/boards/hifive1/dist/openocd.cfg b/boards/hifive1/dist/openocd.cfg new file mode 100644 index 0000000000..76e9213761 --- /dev/null +++ b/boards/hifive1/dist/openocd.cfg @@ -0,0 +1,44 @@ +# +# Originally from: +# https://github.com/sifive/freedom-e-sdk/blob/master/bsp/env/freedom-e300-hifive1/openocd.cfg +# Note this is called by riot/dist/tools/openocd/openocd.sh which +# issues a series of openocd commands. +# +# HiFive1 does not support openocd "reset run" aka "reset" +# +adapter_khz 10000 + + +interface ftdi +ftdi_device_desc "Dual RS232-HS" +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x001b +ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 + +#Reset Stretcher logic on FE310 is ~1 second long +#This doesn't apply if you use +# ftdi_set_signal, but still good to document +#adapter_nsrst_delay 1500 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME +#init +#reset -- This type of reset is not implemented yet +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z + #Wait for the reset stretcher + #It will work without this, but + #will incur lots of delays for later commands. + sleep 1500 +} +#halt +#flash protect 0 64 last off +# diff --git a/boards/hifive1/include/board.h b/boards/hifive1/include/board.h new file mode 100644 index 0000000000..76134a9b01 --- /dev/null +++ b/boards/hifive1/include/board.h @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2017 Ken Rabold + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @defgroup boards_hifive + * @ingroup boards + * @brief Support for the HiFive1 RISC-V board + * @{ + * + * @file + * @brief Board specific definitions for the HiFive1 RISC-V board + * + * @author Ken Rabold + */ + +#ifndef BOARD_H +#define BOARD_H + +#include "periph/gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Macros for controlling the on-board LEDs + * @{ + */ +#define LED0_PIN GPIO_PIN(0, 22) /* Red */ +#define LED1_PIN GPIO_PIN(0, 19) /* Green */ +#define LED2_PIN GPIO_PIN(0, 21) /* Blue */ + +#define LED0_ON gpio_clear(LED0_PIN) +#define LED0_OFF gpio_set(LED0_PIN) +#define LED0_TOGGLE gpio_toggle(LED0_PIN) + +#define LED1_ON gpio_clear(LED1_PIN) +#define LED1_OFF gpio_set(LED1_PIN) +#define LED1_TOGGLE gpio_toggle(LED1_PIN) + +#define LED2_ON gpio_clear(LED2_PIN) +#define LED2_OFF gpio_set(LED2_PIN) +#define LED2_TOGGLE gpio_toggle(LED2_PIN) + +/** + * @brief Initialize board specific hardware, including clock, LEDs and std-IO + */ +void board_init(void); + +/** + * @brief Initialize the board clock to use PLL and faster SPI access. + * @detail This must be done before UART initialization. RIOT assumes + * newlib initializes the UART in the _init() routine. + */ +void board_init_clock(void); + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_H */ +/** @} */ diff --git a/boards/hifive1/include/periph_conf.h b/boards/hifive1/include/periph_conf.h new file mode 100644 index 0000000000..6c595300ac --- /dev/null +++ b/boards/hifive1/include/periph_conf.h @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2017 Ken Rabold + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @defgroup boards_hifive HiFive1 + * @ingroup boards + * @brief Support for the HiFive1 RISC-V board + * @{ + * + * @file + * @brief Peripheral specific definitions for the HiFive1 RISC-V board + * + * @author Ken Rabold + */ + +#ifndef PERIPH_CONF_H +#define PERIPH_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Core Clock configuration + * @{ + */ +#define CLOCK_CORECLOCK (1600000ul) +/* + * #define CLOCK_CORECLOCK (20000000ul) + * #define CLOCK_CORECLOCK (27000000ul) + * #define CLOCK_CORECLOCK (38400000ul) + */ +/** @} */ + +/** + * @name Xtimer configuration + * @{ + */ +#define XTIMER_DEV (0) +#define XTIMER_CHAN (0) +#define XTIMER_WIDTH (32) +#define XTIMER_HZ (32768ul) +/** @} */ + +/** + * @name Timer configuration + * + * @{ + */ +#define TIMER_NUMOF (1) +/** @} */ + +/** + * @name RTT/RTC configuration + * + * @{ + */ +#define RTT_NUMOF (1) +#define RTT_FREQUENCY (1) /* in Hz */ +#define RTT_MAX_VALUE (0xFFFFFFFF) +#define RTT_INTR_PRIORITY (2) + +#define RTC_NUMOF (1) +/** @} */ + +/** + * @name GPIO configuration + * + * @{ + */ +#define GPIO_INTR_PRIORITY (3) +/** @} */ + +/** + * @name PWM configuration + * + * @{ + */ +#define PWM_NUMOF (3) +/** @} */ + +/** + * @name UART configuration + * + * @{ + */ +#define UART_NUMOF (2) +#define UART0_RX_INTR_PRIORITY (2) +#define UART1_RX_INTR_PRIORITY (2) +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* PERIPH_CONF_H */ +/** @} */ diff --git a/boards/hifive1/include/vendor/LICENSE b/boards/hifive1/include/vendor/LICENSE new file mode 100644 index 0000000000..78c6ebc176 --- /dev/null +++ b/boards/hifive1/include/vendor/LICENSE @@ -0,0 +1,206 @@ + +This software, except as otherwise noted in subrepositories, +is licensed under the Apache 2 license, quoted below. + + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright 2016 SiFive, Inc. + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/boards/hifive1/include/vendor/hifive1.h b/boards/hifive1/include/vendor/hifive1.h new file mode 100644 index 0000000000..713674e63e --- /dev/null +++ b/boards/hifive1/include/vendor/hifive1.h @@ -0,0 +1,78 @@ +// See LICENSE for license details. + +#ifndef _SIFIVE_HIFIVE1_H +#define _SIFIVE_HIFIVE1_H + +#include + +/**************************************************************************** + * GPIO Connections + *****************************************************************************/ + +// These are the GPIO bit offsets for the RGB LED on HiFive1 Board. +// These are also mapped to RGB LEDs on the Freedom E300 Arty +// FPGA +// Dev Kit. + +#define RED_LED_OFFSET 22 +#define GREEN_LED_OFFSET 19 +#define BLUE_LED_OFFSET 21 + +// These are the GPIO bit offsets for the differen digital pins +// on the headers for both the HiFive1 Board and the Freedom E300 Arty FPGA Dev Kit. +#define PIN_0_OFFSET 16 +#define PIN_1_OFFSET 17 +#define PIN_2_OFFSET 18 +#define PIN_3_OFFSET 19 +#define PIN_4_OFFSET 20 +#define PIN_5_OFFSET 21 +#define PIN_6_OFFSET 22 +#define PIN_7_OFFSET 23 +#define PIN_8_OFFSET 0 +#define PIN_9_OFFSET 1 +#define PIN_10_OFFSET 2 +#define PIN_11_OFFSET 3 +#define PIN_12_OFFSET 4 +#define PIN_13_OFFSET 5 +//#define PIN_14_OFFSET 8 //This pin is not connected on either board. +#define PIN_15_OFFSET 9 +#define PIN_16_OFFSET 10 +#define PIN_17_OFFSET 11 +#define PIN_18_OFFSET 12 +#define PIN_19_OFFSET 13 + +// These are *PIN* numbers, not +// GPIO Offset Numbers. +#define PIN_SPI1_SCK (13u) +#define PIN_SPI1_MISO (12u) +#define PIN_SPI1_MOSI (11u) +#define PIN_SPI1_SS0 (10u) +#define PIN_SPI1_SS1 (14u) +#define PIN_SPI1_SS2 (15u) +#define PIN_SPI1_SS3 (16u) + +#define SS_PIN_TO_CS_ID(x) \ + ((x==PIN_SPI1_SS0 ? 0 : \ + (x==PIN_SPI1_SS1 ? 1 : \ + (x==PIN_SPI1_SS2 ? 2 : \ + (x==PIN_SPI1_SS3 ? 3 : \ + -1))))) + + +// These buttons are present only on the Freedom E300 Arty Dev Kit. +#ifdef HAS_BOARD_BUTTONS +#define BUTTON_0_OFFSET 15 +#define BUTTON_1_OFFSET 30 +#define BUTTON_2_OFFSET 31 + +#define INT_DEVICE_BUTTON_0 (INT_GPIO_BASE + BUTTON_0_OFFSET) +#define INT_DEVICE_BUTTON_1 (INT_GPIO_BASE + BUTTON_1_OFFSET) +#define INT_DEVICE_BUTTON_2 (INT_GPIO_BASE + BUTTON_2_OFFSET) + +#endif + +#define HAS_HFXOSC 1 +#define HAS_LFROSC_BYPASS 1 + + +#endif /* _SIFIVE_HIFIVE1_H */