cpu/kw2x: adapted to centralized cpu conf

cpu/kw2x/Makefile.include

@@ -1,3 +1,5 @@
+export CPU_ARCH = cortex-m4
+
 # this CPU implementation is using the explicit core/CPU interface
 export CFLAGS += -DCOREIF_NG=1
 
@@ -26,6 +28,8 @@ export LINKERSCRIPT = $(RIOTCPU)/$(CPU)/$(CPU_MODEL)_linkerscript.ld
 #export the CPU model
 MODEL = $(shell echo $(CPU_MODEL)|tr 'a-z' 'A-Z')
 export CFLAGS += -DCPU_MODEL_$(MODEL)
+ARCH = $(shell echo $(CPU_ARCH) | tr 'a-z-' 'A-Z_')
+export CFLAGS += -DCPU_ARCH_$(ARCH)
 
 # include CPU specific includes
 export INCLUDES += -I$(RIOTCPU)/$(CPU)/include

cpu/kw2x/cpu.c

@@ -31,14 +31,10 @@ static void cpu_clock_init(void);
  */
 void cpu_init(void)
 {
-    /* configure the vector table location to internal flash */
-    SCB->VTOR = FLASH_BASE;
-
+    /* initialize the Cortex-M core */
+    cortexm_init();
     /* initialize the clock system */
     cpu_clock_init();
-
-    /* set pendSV interrupt to lowest possible priority */
-    NVIC_SetPriority(PendSV_IRQn, 0xff);
 }
 
 static inline void modem_clock_init(void)

cpu/kw2x/include/cpu_conf.h

@@ -43,17 +43,12 @@ extern "C"
 #endif
 
 /**
- * @name Kernel configuration
- *
+ * @brief   ARM Cortex-M specific CPU configuration
  * @{
  */
-#define THREAD_EXTRA_STACKSIZE_PRINTF     (1024)
-
-#ifndef THREAD_STACKSIZE_DEFAULT
-#define THREAD_STACKSIZE_DEFAULT    (1024)
-#endif
-
-#define THREAD_STACKSIZE_IDLE       (256)
+#define CPU_DEFAULT_IRQ_PRIO            (1U)
+#define CPU_IRQ_NUMOF                   (65U)
+#define CPU_FLASH_BASE                  (0x00000000)
 /** @} */
 
 /**
@@ -66,17 +61,6 @@ extern "C"
  */
 #define CPUID_ID_PTR                     ((void *)(&(SIM_UIDH)))
 
-/**
- * @name UART0 buffer size definition for compatibility reasons.
- *
- * TODO: remove once the remodeling of the uart0 driver is done.
- * @{
- */
-#ifndef UART0_BUFSIZE
-#define UART0_BUFSIZE                    (128)
-#endif
-/** @} */
-
 #define TRANSCEIVER_BUFFER_SIZE          (3) /**< Buffer Size for Transceiver Module */
 
 /**