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rakendrathapa
Rakendra Thapa
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@ -1,192 +1,192 @@
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//*****************************************************************************
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//
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// hw_gpio.h - Defines and Macros for GPIO hardware.
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//
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// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Firmware Development Package.
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||||
//
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||||
//*****************************************************************************
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#ifndef __HW_GPIO_H__
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#define __HW_GPIO_H__
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//*****************************************************************************
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//
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// The following are defines for the GPIO register offsets.
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//
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//*****************************************************************************
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#define GPIO_O_DATA 0x00000000 // GPIO Data
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#define GPIO_O_DIR 0x00000400 // GPIO Direction
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#define GPIO_O_IS 0x00000404 // GPIO Interrupt Sense
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#define GPIO_O_IBE 0x00000408 // GPIO Interrupt Both Edges
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#define GPIO_O_IEV 0x0000040C // GPIO Interrupt Event
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#define GPIO_O_IM 0x00000410 // GPIO Interrupt Mask
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#define GPIO_O_RIS 0x00000414 // GPIO Raw Interrupt Status
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#define GPIO_O_MIS 0x00000418 // GPIO Masked Interrupt Status
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#define GPIO_O_ICR 0x0000041C // GPIO Interrupt Clear
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#define GPIO_O_AFSEL 0x00000420 // GPIO Alternate Function Select
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#define GPIO_O_DR2R 0x00000500 // GPIO 2-mA Drive Select
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#define GPIO_O_DR4R 0x00000504 // GPIO 4-mA Drive Select
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#define GPIO_O_DR8R 0x00000508 // GPIO 8-mA Drive Select
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#define GPIO_O_ODR 0x0000050C // GPIO Open Drain Select
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#define GPIO_O_PUR 0x00000510 // GPIO Pull-Up Select
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#define GPIO_O_PDR 0x00000514 // GPIO Pull-Down Select
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#define GPIO_O_SLR 0x00000518 // GPIO Slew Rate Control Select
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#define GPIO_O_DEN 0x0000051C // GPIO Digital Enable
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#define GPIO_O_LOCK 0x00000520 // GPIO Lock
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#define GPIO_O_CR 0x00000524 // GPIO Commit
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#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select
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#define GPIO_O_PCTL 0x0000052C // GPIO Port Control
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#define GPIO_O_ADCCTL 0x00000530 // GPIO ADC Control
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#define GPIO_O_DMACTL 0x00000534 // GPIO DMA Control
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#define GPIO_O_SI 0x00000538 // GPIO Select Interrupt
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_IM register.
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//
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//*****************************************************************************
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#define GPIO_IM_GPIO_M 0x000000FF // GPIO Interrupt Mask Enable
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#define GPIO_IM_GPIO_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_RIS register.
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//
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//*****************************************************************************
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#define GPIO_RIS_GPIO_M 0x000000FF // GPIO Interrupt Raw Status
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#define GPIO_RIS_GPIO_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_MIS register.
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//
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//*****************************************************************************
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#define GPIO_MIS_GPIO_M 0x000000FF // GPIO Masked Interrupt Status
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#define GPIO_MIS_GPIO_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_ICR register.
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//
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//*****************************************************************************
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#define GPIO_ICR_GPIO_M 0x000000FF // GPIO Interrupt Clear
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#define GPIO_ICR_GPIO_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_LOCK register.
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//
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//*****************************************************************************
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#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock
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#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked
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// and may be modified
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#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked
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// and may not be modified
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#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register
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#define GPIO_LOCK_KEY_DD 0x4C4F434B // Unlocks the GPIO_CR register on
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// DustDevil-class devices and
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// later
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_SI register.
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//
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//*****************************************************************************
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#define GPIO_SI_SUM 0x00000001 // Summary Interrupt
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//*****************************************************************************
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//
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// The following definitions are deprecated.
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//
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//*****************************************************************************
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#ifndef DEPRECATED
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//*****************************************************************************
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//
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// The following are deprecated defines for the GPIO register offsets.
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//
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//*****************************************************************************
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#define GPIO_O_PeriphID4 0x00000FD0
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#define GPIO_O_PeriphID5 0x00000FD4
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#define GPIO_O_PeriphID6 0x00000FD8
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#define GPIO_O_PeriphID7 0x00000FDC
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#define GPIO_O_PeriphID0 0x00000FE0
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#define GPIO_O_PeriphID1 0x00000FE4
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#define GPIO_O_PeriphID2 0x00000FE8
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#define GPIO_O_PeriphID3 0x00000FEC
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#define GPIO_O_PCellID0 0x00000FF0
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#define GPIO_O_PCellID1 0x00000FF4
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#define GPIO_O_PCellID2 0x00000FF8
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#define GPIO_O_PCellID3 0x00000FFC
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//*****************************************************************************
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//
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// The following are deprecated defines for the GPIO Register reset values.
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//
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//*****************************************************************************
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#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV
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#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV
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#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV
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#define GPIO_RV_PCellID1 0x000000F0
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#define GPIO_RV_PCellID3 0x000000B1
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#define GPIO_RV_PeriphID0 0x00000061
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#define GPIO_RV_PeriphID1 0x00000010
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#define GPIO_RV_PCellID0 0x0000000D
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#define GPIO_RV_PCellID2 0x00000005
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#define GPIO_RV_PeriphID2 0x00000004
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#define GPIO_RV_LOCK 0x00000001 // Lock register RV
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#define GPIO_RV_PeriphID7 0x00000000
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#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV
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#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV
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#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV
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#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV
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#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV
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#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV
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#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV
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#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV
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#define GPIO_RV_PeriphID4 0x00000000
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#define GPIO_RV_PeriphID5 0x00000000
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#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV
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#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV
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#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV
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#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV
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#define GPIO_RV_DIR 0x00000000 // Data direction reg RV
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#define GPIO_RV_PeriphID6 0x00000000
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#define GPIO_RV_PeriphID3 0x00000000
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#define GPIO_RV_DATA 0x00000000 // Data register reset value
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#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV
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#endif
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#endif // __HW_GPIO_H__
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//*****************************************************************************
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//
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// hw_gpio.h - Defines and Macros for GPIO hardware.
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//
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// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Firmware Development Package.
|
||||
//
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||||
//*****************************************************************************
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#ifndef __HW_GPIO_H__
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#define __HW_GPIO_H__
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//*****************************************************************************
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//
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// The following are defines for the GPIO register offsets.
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//
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//*****************************************************************************
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#define GPIO_O_DATA 0x00000000 // GPIO Data
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#define GPIO_O_DIR 0x00000400 // GPIO Direction
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#define GPIO_O_IS 0x00000404 // GPIO Interrupt Sense
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#define GPIO_O_IBE 0x00000408 // GPIO Interrupt Both Edges
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#define GPIO_O_IEV 0x0000040C // GPIO Interrupt Event
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#define GPIO_O_IM 0x00000410 // GPIO Interrupt Mask
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#define GPIO_O_RIS 0x00000414 // GPIO Raw Interrupt Status
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#define GPIO_O_MIS 0x00000418 // GPIO Masked Interrupt Status
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#define GPIO_O_ICR 0x0000041C // GPIO Interrupt Clear
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#define GPIO_O_AFSEL 0x00000420 // GPIO Alternate Function Select
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#define GPIO_O_DR2R 0x00000500 // GPIO 2-mA Drive Select
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#define GPIO_O_DR4R 0x00000504 // GPIO 4-mA Drive Select
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#define GPIO_O_DR8R 0x00000508 // GPIO 8-mA Drive Select
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#define GPIO_O_ODR 0x0000050C // GPIO Open Drain Select
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#define GPIO_O_PUR 0x00000510 // GPIO Pull-Up Select
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#define GPIO_O_PDR 0x00000514 // GPIO Pull-Down Select
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#define GPIO_O_SLR 0x00000518 // GPIO Slew Rate Control Select
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#define GPIO_O_DEN 0x0000051C // GPIO Digital Enable
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#define GPIO_O_LOCK 0x00000520 // GPIO Lock
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#define GPIO_O_CR 0x00000524 // GPIO Commit
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#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select
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#define GPIO_O_PCTL 0x0000052C // GPIO Port Control
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#define GPIO_O_ADCCTL 0x00000530 // GPIO ADC Control
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#define GPIO_O_DMACTL 0x00000534 // GPIO DMA Control
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#define GPIO_O_SI 0x00000538 // GPIO Select Interrupt
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_IM register.
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//
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//*****************************************************************************
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#define GPIO_IM_GPIO_M 0x000000FF // GPIO Interrupt Mask Enable
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#define GPIO_IM_GPIO_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_RIS register.
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//
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//*****************************************************************************
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#define GPIO_RIS_GPIO_M 0x000000FF // GPIO Interrupt Raw Status
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#define GPIO_RIS_GPIO_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_MIS register.
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//
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//*****************************************************************************
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#define GPIO_MIS_GPIO_M 0x000000FF // GPIO Masked Interrupt Status
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#define GPIO_MIS_GPIO_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_ICR register.
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//
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//*****************************************************************************
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#define GPIO_ICR_GPIO_M 0x000000FF // GPIO Interrupt Clear
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#define GPIO_ICR_GPIO_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the GPIO_O_LOCK register.
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//
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//*****************************************************************************
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#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock
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#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked
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// and may be modified
|
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#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked
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// and may not be modified
|
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#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register
|
||||
#define GPIO_LOCK_KEY_DD 0x4C4F434B // Unlocks the GPIO_CR register on
|
||||
// DustDevil-class devices and
|
||||
// later
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the GPIO_O_SI register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_SI_SUM 0x00000001 // Summary Interrupt
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||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following definitions are deprecated.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the GPIO register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_O_PeriphID4 0x00000FD0
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||||
#define GPIO_O_PeriphID5 0x00000FD4
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#define GPIO_O_PeriphID6 0x00000FD8
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#define GPIO_O_PeriphID7 0x00000FDC
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#define GPIO_O_PeriphID0 0x00000FE0
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#define GPIO_O_PeriphID1 0x00000FE4
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#define GPIO_O_PeriphID2 0x00000FE8
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#define GPIO_O_PeriphID3 0x00000FEC
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||||
#define GPIO_O_PCellID0 0x00000FF0
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||||
#define GPIO_O_PCellID1 0x00000FF4
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#define GPIO_O_PCellID2 0x00000FF8
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||||
#define GPIO_O_PCellID3 0x00000FFC
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||||
|
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//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the GPIO Register reset values.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV
|
||||
#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV
|
||||
#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV
|
||||
#define GPIO_RV_PCellID1 0x000000F0
|
||||
#define GPIO_RV_PCellID3 0x000000B1
|
||||
#define GPIO_RV_PeriphID0 0x00000061
|
||||
#define GPIO_RV_PeriphID1 0x00000010
|
||||
#define GPIO_RV_PCellID0 0x0000000D
|
||||
#define GPIO_RV_PCellID2 0x00000005
|
||||
#define GPIO_RV_PeriphID2 0x00000004
|
||||
#define GPIO_RV_LOCK 0x00000001 // Lock register RV
|
||||
#define GPIO_RV_PeriphID7 0x00000000
|
||||
#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV
|
||||
#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV
|
||||
#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV
|
||||
#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV
|
||||
#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV
|
||||
#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV
|
||||
#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV
|
||||
#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV
|
||||
#define GPIO_RV_PeriphID4 0x00000000
|
||||
#define GPIO_RV_PeriphID5 0x00000000
|
||||
#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV
|
||||
#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV
|
||||
#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV
|
||||
#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV
|
||||
#define GPIO_RV_DIR 0x00000000 // Data direction reg RV
|
||||
#define GPIO_RV_PeriphID6 0x00000000
|
||||
#define GPIO_RV_PeriphID3 0x00000000
|
||||
#define GPIO_RV_DATA 0x00000000 // Data register reset value
|
||||
#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV
|
||||
|
||||
#endif
|
||||
|
||||
#endif // __HW_GPIO_H__
|
||||
|
||||
@ -1,286 +1,286 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_hibernate.h - Defines and Macros for the Hibernation module.
|
||||
//
|
||||
// Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_HIBERNATE_H__
|
||||
#define __HW_HIBERNATE_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the Hibernation module register addresses.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCC 0x400FC000 // Hibernation RTC Counter
|
||||
#define HIB_RTCM0 0x400FC004 // Hibernation RTC Match 0
|
||||
#define HIB_RTCM1 0x400FC008 // Hibernation RTC Match 1
|
||||
#define HIB_RTCLD 0x400FC00C // Hibernation RTC Load
|
||||
#define HIB_CTL 0x400FC010 // Hibernation Control
|
||||
#define HIB_IM 0x400FC014 // Hibernation Interrupt Mask
|
||||
#define HIB_RIS 0x400FC018 // Hibernation Raw Interrupt Status
|
||||
#define HIB_MIS 0x400FC01C // Hibernation Masked Interrupt
|
||||
// Status
|
||||
#define HIB_IC 0x400FC020 // Hibernation Interrupt Clear
|
||||
#define HIB_RTCT 0x400FC024 // Hibernation RTC Trim
|
||||
#define HIB_RTCSS 0x400FC028 // Hibernation RTC Sub Seconds
|
||||
#define HIB_DATA 0x400FC030 // Hibernation Data
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_RTCC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter
|
||||
#define HIB_RTCC_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_RTCM0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0
|
||||
#define HIB_RTCM0_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_RTCM1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCM1_M 0xFFFFFFFF // RTC Match 1
|
||||
#define HIB_RTCM1_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_RTCLD register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load
|
||||
#define HIB_RTCLD_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_CTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable
|
||||
#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability
|
||||
#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass
|
||||
#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery
|
||||
// Comparator
|
||||
#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts
|
||||
#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default)
|
||||
#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts
|
||||
#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts
|
||||
#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status
|
||||
#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery
|
||||
#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered
|
||||
#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable
|
||||
#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable
|
||||
#define HIB_CTL_LOWBATEN 0x00000020 // Low Battery Monitoring Enable
|
||||
#define HIB_CTL_PINWEN 0x00000010 // External WAKE Pin Enable
|
||||
#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable
|
||||
#define HIB_CTL_CLKSEL 0x00000004 // Hibernation Module Clock Select
|
||||
#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request
|
||||
#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_IM register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_IM_WC 0x00000010 // External Write Complete/Capable
|
||||
// Interrupt Mask
|
||||
#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask
|
||||
#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
|
||||
// Mask
|
||||
#define HIB_IM_RTCALT1 0x00000002 // RTC Alert 1 Interrupt Mask
|
||||
#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_RIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw
|
||||
// Interrupt Status
|
||||
#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt
|
||||
// Status
|
||||
#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw
|
||||
// Interrupt Status
|
||||
#define HIB_RIS_RTCALT1 0x00000002 // RTC Alert 1 Raw Interrupt Status
|
||||
#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_MIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked
|
||||
// Interrupt Status
|
||||
#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked
|
||||
// Interrupt Status
|
||||
#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked
|
||||
// Interrupt Status
|
||||
#define HIB_MIS_RTCALT1 0x00000002 // RTC Alert 1 Masked Interrupt
|
||||
// Status
|
||||
#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt
|
||||
// Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_IC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_IC_WC 0x00000010 // Write Complete/Capable Masked
|
||||
// Interrupt Clear
|
||||
#define HIB_IC_EXTW 0x00000008 // External Wake-Up Masked
|
||||
// Interrupt Clear
|
||||
#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Masked
|
||||
// Interrupt Clear
|
||||
#define HIB_IC_RTCALT1 0x00000002 // RTC Alert1 Masked Interrupt
|
||||
// Clear
|
||||
#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
|
||||
// Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_RTCT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value
|
||||
#define HIB_RTCT_TRIM_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_RTCSS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match
|
||||
#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count
|
||||
#define HIB_RTCSS_RTCSSM_S 16
|
||||
#define HIB_RTCSS_RTCSSC_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_DATA register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data
|
||||
#define HIB_DATA_RTD_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following definitions are deprecated.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the Hibernation module register
|
||||
// addresses.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_DATA_END 0x400FC130 // end of data area, exclusive
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the HIB_RTCC
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCC_MASK 0xFFFFFFFF // RTC counter mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the HIB_RTCM0
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCM0_MASK 0xFFFFFFFF // RTC match 0 mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the HIB_RTCM1
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCM1_MASK 0xFFFFFFFF // RTC match 1 mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the HIB_RTCLD
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCLD_MASK 0xFFFFFFFF // RTC load mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the HIB_RIS
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the HIB_MIS
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the HIB_RTCT
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCT_MASK 0x0000FFFF // RTC trim mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the HIB_DATA
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_DATA_MASK 0xFFFFFFFF // NV memory data mask
|
||||
|
||||
#endif
|
||||
|
||||
#endif // __HW_HIBERNATE_H__
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_hibernate.h - Defines and Macros for the Hibernation module.
|
||||
//
|
||||
// Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_HIBERNATE_H__
|
||||
#define __HW_HIBERNATE_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the Hibernation module register addresses.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCC 0x400FC000 // Hibernation RTC Counter
|
||||
#define HIB_RTCM0 0x400FC004 // Hibernation RTC Match 0
|
||||
#define HIB_RTCM1 0x400FC008 // Hibernation RTC Match 1
|
||||
#define HIB_RTCLD 0x400FC00C // Hibernation RTC Load
|
||||
#define HIB_CTL 0x400FC010 // Hibernation Control
|
||||
#define HIB_IM 0x400FC014 // Hibernation Interrupt Mask
|
||||
#define HIB_RIS 0x400FC018 // Hibernation Raw Interrupt Status
|
||||
#define HIB_MIS 0x400FC01C // Hibernation Masked Interrupt
|
||||
// Status
|
||||
#define HIB_IC 0x400FC020 // Hibernation Interrupt Clear
|
||||
#define HIB_RTCT 0x400FC024 // Hibernation RTC Trim
|
||||
#define HIB_RTCSS 0x400FC028 // Hibernation RTC Sub Seconds
|
||||
#define HIB_DATA 0x400FC030 // Hibernation Data
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_RTCC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter
|
||||
#define HIB_RTCC_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_RTCM0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0
|
||||
#define HIB_RTCM0_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_RTCM1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCM1_M 0xFFFFFFFF // RTC Match 1
|
||||
#define HIB_RTCM1_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_RTCLD register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load
|
||||
#define HIB_RTCLD_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_CTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable
|
||||
#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability
|
||||
#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass
|
||||
#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery
|
||||
// Comparator
|
||||
#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts
|
||||
#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default)
|
||||
#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts
|
||||
#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts
|
||||
#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status
|
||||
#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery
|
||||
#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered
|
||||
#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable
|
||||
#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable
|
||||
#define HIB_CTL_LOWBATEN 0x00000020 // Low Battery Monitoring Enable
|
||||
#define HIB_CTL_PINWEN 0x00000010 // External WAKE Pin Enable
|
||||
#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable
|
||||
#define HIB_CTL_CLKSEL 0x00000004 // Hibernation Module Clock Select
|
||||
#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request
|
||||
#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_IM register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_IM_WC 0x00000010 // External Write Complete/Capable
|
||||
// Interrupt Mask
|
||||
#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask
|
||||
#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
|
||||
// Mask
|
||||
#define HIB_IM_RTCALT1 0x00000002 // RTC Alert 1 Interrupt Mask
|
||||
#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_RIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw
|
||||
// Interrupt Status
|
||||
#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt
|
||||
// Status
|
||||
#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw
|
||||
// Interrupt Status
|
||||
#define HIB_RIS_RTCALT1 0x00000002 // RTC Alert 1 Raw Interrupt Status
|
||||
#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_MIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked
|
||||
// Interrupt Status
|
||||
#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked
|
||||
// Interrupt Status
|
||||
#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked
|
||||
// Interrupt Status
|
||||
#define HIB_MIS_RTCALT1 0x00000002 // RTC Alert 1 Masked Interrupt
|
||||
// Status
|
||||
#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt
|
||||
// Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_IC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_IC_WC 0x00000010 // Write Complete/Capable Masked
|
||||
// Interrupt Clear
|
||||
#define HIB_IC_EXTW 0x00000008 // External Wake-Up Masked
|
||||
// Interrupt Clear
|
||||
#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Masked
|
||||
// Interrupt Clear
|
||||
#define HIB_IC_RTCALT1 0x00000002 // RTC Alert1 Masked Interrupt
|
||||
// Clear
|
||||
#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
|
||||
// Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_RTCT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value
|
||||
#define HIB_RTCT_TRIM_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_RTCSS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match
|
||||
#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count
|
||||
#define HIB_RTCSS_RTCSSM_S 16
|
||||
#define HIB_RTCSS_RTCSSC_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the HIB_DATA register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data
|
||||
#define HIB_DATA_RTD_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following definitions are deprecated.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the Hibernation module register
|
||||
// addresses.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_DATA_END 0x400FC130 // end of data area, exclusive
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the HIB_RTCC
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCC_MASK 0xFFFFFFFF // RTC counter mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the HIB_RTCM0
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCM0_MASK 0xFFFFFFFF // RTC match 0 mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the HIB_RTCM1
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCM1_MASK 0xFFFFFFFF // RTC match 1 mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the HIB_RTCLD
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCLD_MASK 0xFFFFFFFF // RTC load mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the HIB_RIS
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the HIB_MIS
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the HIB_RTCT
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_RTCT_MASK 0x0000FFFF // RTC trim mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the HIB_DATA
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIB_DATA_MASK 0xFFFFFFFF // NV memory data mask
|
||||
|
||||
#endif
|
||||
|
||||
#endif // __HW_HIBERNATE_H__
|
||||
|
||||
@ -1,489 +1,489 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_I2C_H__
|
||||
#define __HW_I2C_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the I2C register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_O_MSA 0x00000000 // I2C Master Slave Address
|
||||
#define I2C_O_SOAR 0x00000000 // I2C Slave Own Address
|
||||
#define I2C_O_SCSR 0x00000004 // I2C Slave Control/Status
|
||||
#define I2C_O_MCS 0x00000004 // I2C Master Control/Status
|
||||
#define I2C_O_SDR 0x00000008 // I2C Slave Data
|
||||
#define I2C_O_MDR 0x00000008 // I2C Master Data
|
||||
#define I2C_O_MTPR 0x0000000C // I2C Master Timer Period
|
||||
#define I2C_O_SIMR 0x0000000C // I2C Slave Interrupt Mask
|
||||
#define I2C_O_SRIS 0x00000010 // I2C Slave Raw Interrupt Status
|
||||
#define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask
|
||||
#define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status
|
||||
#define I2C_O_SMIS 0x00000014 // I2C Slave Masked Interrupt
|
||||
// Status
|
||||
#define I2C_O_SICR 0x00000018 // I2C Slave Interrupt Clear
|
||||
#define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt
|
||||
// Status
|
||||
#define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear
|
||||
#define I2C_O_SOAR2 0x0000001C // I2C Slave Own Address 2
|
||||
#define I2C_O_MCR 0x00000020 // I2C Master Configuration
|
||||
#define I2C_O_SACKCTL 0x00000020 // I2C Slave ACK Control
|
||||
#define I2C_O_MCLKOCNT 0x00000024 // I2C Master Clock Low Timeout
|
||||
// Count
|
||||
#define I2C_O_MBMON 0x0000002C // I2C Master Bus Monitor
|
||||
#define I2C_O_PP 0x00000FC0 // I2C Peripheral Properties
|
||||
#define I2C_O_PC 0x00000FC4 // I2C Peripheral Configuration
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MSA register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address
|
||||
#define I2C_MSA_RS 0x00000001 // Receive not send
|
||||
#define I2C_MSA_SA_S 1
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SOAR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address
|
||||
#define I2C_SOAR_OAR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SCSR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write
|
||||
#define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status
|
||||
#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched
|
||||
#define I2C_SCSR_FBR 0x00000004 // First Byte Received
|
||||
#define I2C_SCSR_TREQ 0x00000002 // Transmit Request
|
||||
#define I2C_SCSR_DA 0x00000001 // Device Active
|
||||
#define I2C_SCSR_RREQ 0x00000001 // Receive Request
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MCS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error
|
||||
#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy
|
||||
#define I2C_MCS_IDLE 0x00000020 // I2C Idle
|
||||
#define I2C_MCS_QCMD 0x00000020 // Quick Command
|
||||
#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost
|
||||
#define I2C_MCS_HS 0x00000010 // High-Speed Enable
|
||||
#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable
|
||||
#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data
|
||||
#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address
|
||||
#define I2C_MCS_STOP 0x00000004 // Generate STOP
|
||||
#define I2C_MCS_ERROR 0x00000002 // Error
|
||||
#define I2C_MCS_START 0x00000002 // Generate START
|
||||
#define I2C_MCS_RUN 0x00000001 // I2C Master Enable
|
||||
#define I2C_MCS_BUSY 0x00000001 // I2C Busy
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SDR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer
|
||||
#define I2C_SDR_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MDR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MDR_DATA_M 0x000000FF // Data Transferred
|
||||
#define I2C_MDR_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MTPR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MTPR_HS 0x00000080 // High-Speed Enable
|
||||
#define I2C_MTPR_TPR_M 0x0000007F // SCL Clock Period
|
||||
#define I2C_MTPR_TPR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SIMR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask
|
||||
#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask
|
||||
#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SRIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt
|
||||
// Status
|
||||
#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt
|
||||
// Status
|
||||
#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MIMR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask
|
||||
#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MRIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt
|
||||
// Status
|
||||
#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SMIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt
|
||||
// Status
|
||||
#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt
|
||||
// Status
|
||||
#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SICR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear
|
||||
#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear
|
||||
#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MMIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt
|
||||
// Status
|
||||
#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MICR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear
|
||||
#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SOAR2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable
|
||||
#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2
|
||||
#define I2C_SOAR2_OAR2_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MCR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable
|
||||
#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable
|
||||
#define I2C_MCR_LPBK 0x00000001 // I2C Loopback
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SACKCTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value
|
||||
#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MCLKOCNT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count
|
||||
#define I2C_MCLKOCNT_CNTL_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MBMON register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status
|
||||
#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_PP register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_PP_HS 0x00000001 // High-Speed Capable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_PC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_PC_HS 0x00000001 // High-Speed Capable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following definitions are deprecated.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the I2C register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_O_SLAVE 0x00000800 // Offset from master to slave
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C_O_SIMR
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SIMR_IM 0x00000001 // Interrupt Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C_O_SRIS
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SRIS_RIS 0x00000001 // Raw Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C_O_SMIS
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SMIS_MIS 0x00000001 // Masked Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C_O_SICR
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SICR_IC 0x00000001 // Clear Interrupt
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the I2C master register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_O_SA 0x00000000 // Slave address register
|
||||
#define I2C_MASTER_O_CS 0x00000004 // Control and Status register
|
||||
#define I2C_MASTER_O_DR 0x00000008 // Data register
|
||||
#define I2C_MASTER_O_TPR 0x0000000C // Timer period register
|
||||
#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register
|
||||
#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register
|
||||
#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg
|
||||
#define I2C_MASTER_O_MICR 0x0000001C // Interrupt clear register
|
||||
#define I2C_MASTER_O_CR 0x00000020 // Configuration register
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the I2C slave register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register
|
||||
#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg
|
||||
#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register
|
||||
#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register
|
||||
#define I2C_SLAVE_O_DR 0x00000008 // Data register
|
||||
#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register
|
||||
#define I2C_SLAVE_O_OAR 0x00000000 // Own address register
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C master
|
||||
// slave address register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address
|
||||
#define I2C_MASTER_SA_RS 0x00000001 // Receive/send
|
||||
#define I2C_MASTER_SA_SA_SHIFT 1
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C Master
|
||||
// Control and Status register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy
|
||||
#define I2C_MASTER_CS_IDLE 0x00000020 // Idle
|
||||
#define I2C_MASTER_CS_ERR_MASK 0x0000001C
|
||||
#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data
|
||||
#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred
|
||||
#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged
|
||||
#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged
|
||||
#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration
|
||||
#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde
|
||||
#define I2C_MASTER_CS_STOP 0x00000004 // Stop
|
||||
#define I2C_MASTER_CS_START 0x00000002 // Start
|
||||
#define I2C_MASTER_CS_RUN 0x00000001 // Run
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the values used in determining the
|
||||
// contents of the I2C Master Timer Period register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SCL_FAST 400000 // SCL fast frequency
|
||||
#define I2C_SCL_STANDARD 100000 // SCL standard frequency
|
||||
#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period
|
||||
#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period
|
||||
#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C Master
|
||||
// Interrupt Mask register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C Master
|
||||
// Raw Interrupt Status register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C Master
|
||||
// Masked Interrupt Status register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C Master
|
||||
// Interrupt Clear register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C Master
|
||||
// Configuration register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable
|
||||
#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable
|
||||
#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C Slave Own
|
||||
// Address register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C Slave
|
||||
// Control/Status register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SLAVE_CSR_FBR 0x00000004 // First byte received from master
|
||||
#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received
|
||||
#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device
|
||||
#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C Slave
|
||||
// Interrupt Mask register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C Slave Raw
|
||||
// Interrupt Status register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C Slave
|
||||
// Masked Interrupt Status register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C Slave
|
||||
// Interrupt Clear register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear
|
||||
|
||||
#endif
|
||||
|
||||
#endif // __HW_I2C_H__
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_I2C_H__
|
||||
#define __HW_I2C_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the I2C register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_O_MSA 0x00000000 // I2C Master Slave Address
|
||||
#define I2C_O_SOAR 0x00000000 // I2C Slave Own Address
|
||||
#define I2C_O_SCSR 0x00000004 // I2C Slave Control/Status
|
||||
#define I2C_O_MCS 0x00000004 // I2C Master Control/Status
|
||||
#define I2C_O_SDR 0x00000008 // I2C Slave Data
|
||||
#define I2C_O_MDR 0x00000008 // I2C Master Data
|
||||
#define I2C_O_MTPR 0x0000000C // I2C Master Timer Period
|
||||
#define I2C_O_SIMR 0x0000000C // I2C Slave Interrupt Mask
|
||||
#define I2C_O_SRIS 0x00000010 // I2C Slave Raw Interrupt Status
|
||||
#define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask
|
||||
#define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status
|
||||
#define I2C_O_SMIS 0x00000014 // I2C Slave Masked Interrupt
|
||||
// Status
|
||||
#define I2C_O_SICR 0x00000018 // I2C Slave Interrupt Clear
|
||||
#define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt
|
||||
// Status
|
||||
#define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear
|
||||
#define I2C_O_SOAR2 0x0000001C // I2C Slave Own Address 2
|
||||
#define I2C_O_MCR 0x00000020 // I2C Master Configuration
|
||||
#define I2C_O_SACKCTL 0x00000020 // I2C Slave ACK Control
|
||||
#define I2C_O_MCLKOCNT 0x00000024 // I2C Master Clock Low Timeout
|
||||
// Count
|
||||
#define I2C_O_MBMON 0x0000002C // I2C Master Bus Monitor
|
||||
#define I2C_O_PP 0x00000FC0 // I2C Peripheral Properties
|
||||
#define I2C_O_PC 0x00000FC4 // I2C Peripheral Configuration
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MSA register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address
|
||||
#define I2C_MSA_RS 0x00000001 // Receive not send
|
||||
#define I2C_MSA_SA_S 1
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SOAR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address
|
||||
#define I2C_SOAR_OAR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SCSR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write
|
||||
#define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status
|
||||
#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched
|
||||
#define I2C_SCSR_FBR 0x00000004 // First Byte Received
|
||||
#define I2C_SCSR_TREQ 0x00000002 // Transmit Request
|
||||
#define I2C_SCSR_DA 0x00000001 // Device Active
|
||||
#define I2C_SCSR_RREQ 0x00000001 // Receive Request
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MCS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error
|
||||
#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy
|
||||
#define I2C_MCS_IDLE 0x00000020 // I2C Idle
|
||||
#define I2C_MCS_QCMD 0x00000020 // Quick Command
|
||||
#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost
|
||||
#define I2C_MCS_HS 0x00000010 // High-Speed Enable
|
||||
#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable
|
||||
#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data
|
||||
#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address
|
||||
#define I2C_MCS_STOP 0x00000004 // Generate STOP
|
||||
#define I2C_MCS_ERROR 0x00000002 // Error
|
||||
#define I2C_MCS_START 0x00000002 // Generate START
|
||||
#define I2C_MCS_RUN 0x00000001 // I2C Master Enable
|
||||
#define I2C_MCS_BUSY 0x00000001 // I2C Busy
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SDR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer
|
||||
#define I2C_SDR_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MDR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MDR_DATA_M 0x000000FF // Data Transferred
|
||||
#define I2C_MDR_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MTPR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MTPR_HS 0x00000080 // High-Speed Enable
|
||||
#define I2C_MTPR_TPR_M 0x0000007F // SCL Clock Period
|
||||
#define I2C_MTPR_TPR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SIMR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask
|
||||
#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask
|
||||
#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SRIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt
|
||||
// Status
|
||||
#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt
|
||||
// Status
|
||||
#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MIMR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask
|
||||
#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MRIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt
|
||||
// Status
|
||||
#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SMIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt
|
||||
// Status
|
||||
#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt
|
||||
// Status
|
||||
#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SICR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear
|
||||
#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear
|
||||
#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MMIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt
|
||||
// Status
|
||||
#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MICR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear
|
||||
#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SOAR2 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable
|
||||
#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2
|
||||
#define I2C_SOAR2_OAR2_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MCR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable
|
||||
#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable
|
||||
#define I2C_MCR_LPBK 0x00000001 // I2C Loopback
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_SACKCTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value
|
||||
#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MCLKOCNT register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count
|
||||
#define I2C_MCLKOCNT_CNTL_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_MBMON register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status
|
||||
#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_PP register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_PP_HS 0x00000001 // High-Speed Capable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the I2C_O_PC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_PC_HS 0x00000001 // High-Speed Capable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following definitions are deprecated.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the I2C register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_O_SLAVE 0x00000800 // Offset from master to slave
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C_O_SIMR
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SIMR_IM 0x00000001 // Interrupt Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C_O_SRIS
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SRIS_RIS 0x00000001 // Raw Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C_O_SMIS
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SMIS_MIS 0x00000001 // Masked Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C_O_SICR
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SICR_IC 0x00000001 // Clear Interrupt
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the I2C master register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_O_SA 0x00000000 // Slave address register
|
||||
#define I2C_MASTER_O_CS 0x00000004 // Control and Status register
|
||||
#define I2C_MASTER_O_DR 0x00000008 // Data register
|
||||
#define I2C_MASTER_O_TPR 0x0000000C // Timer period register
|
||||
#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register
|
||||
#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register
|
||||
#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg
|
||||
#define I2C_MASTER_O_MICR 0x0000001C // Interrupt clear register
|
||||
#define I2C_MASTER_O_CR 0x00000020 // Configuration register
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the I2C slave register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register
|
||||
#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg
|
||||
#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register
|
||||
#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register
|
||||
#define I2C_SLAVE_O_DR 0x00000008 // Data register
|
||||
#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register
|
||||
#define I2C_SLAVE_O_OAR 0x00000000 // Own address register
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C master
|
||||
// slave address register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address
|
||||
#define I2C_MASTER_SA_RS 0x00000001 // Receive/send
|
||||
#define I2C_MASTER_SA_SA_SHIFT 1
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C Master
|
||||
// Control and Status register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy
|
||||
#define I2C_MASTER_CS_IDLE 0x00000020 // Idle
|
||||
#define I2C_MASTER_CS_ERR_MASK 0x0000001C
|
||||
#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data
|
||||
#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred
|
||||
#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged
|
||||
#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged
|
||||
#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration
|
||||
#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde
|
||||
#define I2C_MASTER_CS_STOP 0x00000004 // Stop
|
||||
#define I2C_MASTER_CS_START 0x00000002 // Start
|
||||
#define I2C_MASTER_CS_RUN 0x00000001 // Run
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the values used in determining the
|
||||
// contents of the I2C Master Timer Period register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SCL_FAST 400000 // SCL fast frequency
|
||||
#define I2C_SCL_STANDARD 100000 // SCL standard frequency
|
||||
#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period
|
||||
#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period
|
||||
#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C Master
|
||||
// Interrupt Mask register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C Master
|
||||
// Raw Interrupt Status register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C Master
|
||||
// Masked Interrupt Status register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C Master
|
||||
// Interrupt Clear register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C Master
|
||||
// Configuration register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable
|
||||
#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable
|
||||
#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C Slave Own
|
||||
// Address register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C Slave
|
||||
// Control/Status register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SLAVE_CSR_FBR 0x00000004 // First byte received from master
|
||||
#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received
|
||||
#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device
|
||||
#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C Slave
|
||||
// Interrupt Mask register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C Slave Raw
|
||||
// Interrupt Status register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C Slave
|
||||
// Masked Interrupt Status register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the I2C Slave
|
||||
// Interrupt Clear register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear
|
||||
|
||||
#endif
|
||||
|
||||
#endif // __HW_I2C_H__
|
||||
|
||||
@ -1,217 +1,217 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_ints.h - Macros that define the interrupt assignment on Stellaris.
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_INTS_H__
|
||||
#define __HW_INTS_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the fault assignments.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FAULT_NMI 2 // NMI fault
|
||||
#define FAULT_HARD 3 // Hard fault
|
||||
#define FAULT_MPU 4 // MPU fault
|
||||
#define FAULT_BUS 5 // Bus fault
|
||||
#define FAULT_USAGE 6 // Usage fault
|
||||
#define FAULT_SVCALL 11 // SVCall
|
||||
#define FAULT_DEBUG 12 // Debug monitor
|
||||
#define FAULT_PENDSV 14 // PendSV
|
||||
#define FAULT_SYSTICK 15 // System Tick
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the interrupt assignments.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define INT_GPIOA 16 // GPIO Port A
|
||||
#define INT_GPIOB 17 // GPIO Port B
|
||||
#define INT_GPIOC 18 // GPIO Port C
|
||||
#define INT_GPIOD 19 // GPIO Port D
|
||||
#define INT_GPIOE 20 // GPIO Port E
|
||||
#define INT_UART0 21 // UART0 Rx and Tx
|
||||
#define INT_UART1 22 // UART1 Rx and Tx
|
||||
#define INT_SSI0 23 // SSI0 Rx and Tx
|
||||
#define INT_I2C0 24 // I2C0 Master and Slave
|
||||
#define INT_PWM0_FAULT 25 // PWM0 Fault
|
||||
#define INT_PWM0_0 26 // PWM0 Generator 0
|
||||
#define INT_PWM0_1 27 // PWM0 Generator 1
|
||||
#define INT_PWM0_2 28 // PWM0 Generator 2
|
||||
#define INT_QEI0 29 // Quadrature Encoder 0
|
||||
#define INT_ADC0SS0 30 // ADC0 Sequence 0
|
||||
#define INT_ADC0SS1 31 // ADC0 Sequence 1
|
||||
#define INT_ADC0SS2 32 // ADC0 Sequence 2
|
||||
#define INT_ADC0SS3 33 // ADC0 Sequence 3
|
||||
#define INT_WATCHDOG 34 // Watchdog timer
|
||||
#define INT_TIMER0A 35 // Timer 0 subtimer A
|
||||
#define INT_TIMER0B 36 // Timer 0 subtimer B
|
||||
#define INT_TIMER1A 37 // Timer 1 subtimer A
|
||||
#define INT_TIMER1B 38 // Timer 1 subtimer B
|
||||
#define INT_TIMER2A 39 // Timer 2 subtimer A
|
||||
#define INT_TIMER2B 40 // Timer 2 subtimer B
|
||||
#define INT_COMP0 41 // Analog Comparator 0
|
||||
#define INT_COMP1 42 // Analog Comparator 1
|
||||
#define INT_COMP2 43 // Analog Comparator 2
|
||||
#define INT_SYSCTL 44 // System Control (PLL, OSC, BO)
|
||||
#define INT_FLASH 45 // FLASH Control
|
||||
#define INT_GPIOF 46 // GPIO Port F
|
||||
#define INT_GPIOG 47 // GPIO Port G
|
||||
#define INT_GPIOH 48 // GPIO Port H
|
||||
#define INT_UART2 49 // UART2 Rx and Tx
|
||||
#define INT_SSI1 50 // SSI1 Rx and Tx
|
||||
#define INT_TIMER3A 51 // Timer 3 subtimer A
|
||||
#define INT_TIMER3B 52 // Timer 3 subtimer B
|
||||
#define INT_I2C1 53 // I2C1 Master and Slave
|
||||
#define INT_QEI1 54 // Quadrature Encoder 1
|
||||
#define INT_CAN0 55 // CAN0
|
||||
#define INT_CAN1 56 // CAN1
|
||||
#define INT_CAN2 57 // CAN2
|
||||
#define INT_ETH 58 // Ethernet
|
||||
#define INT_HIBERNATE 59 // Hibernation module
|
||||
#define INT_USB0 60 // USB 0 Controller
|
||||
#define INT_PWM0_3 61 // PWM0 Generator 3
|
||||
#define INT_UDMA 62 // uDMA controller
|
||||
#define INT_UDMAERR 63 // uDMA Error
|
||||
#define INT_ADC1SS0 64 // ADC1 Sequence 0
|
||||
#define INT_ADC1SS1 65 // ADC1 Sequence 1
|
||||
#define INT_ADC1SS2 66 // ADC1 Sequence 2
|
||||
#define INT_ADC1SS3 67 // ADC1 Sequence 3
|
||||
#define INT_I2S0 68 // I2S0
|
||||
#define INT_EPI0 69 // EPI0
|
||||
#define INT_GPIOJ 70 // GPIO Port J
|
||||
#define INT_GPIOK 71 // GPIO Port K
|
||||
#define INT_GPIOL 72 // GPIO Port L
|
||||
#define INT_SSI2 73 // SSI2
|
||||
#define INT_SSI3 74 // SSI3
|
||||
#define INT_UART3 75 // UART3
|
||||
#define INT_UART4 76 // UART4
|
||||
#define INT_UART5 77 // UART5
|
||||
#define INT_UART6 78 // UART6
|
||||
#define INT_UART7 79 // UART7
|
||||
#define INT_I2C2 84 // I2C2
|
||||
#define INT_I2C3 85 // I2C3
|
||||
#define INT_TIMER4A 86 // Timer 4A
|
||||
#define INT_TIMER4B 87 // Timer 4B
|
||||
#define INT_TIMER5A 108 // Timer 5A
|
||||
#define INT_TIMER5B 109 // Timer 5B
|
||||
#define INT_WTIMER0A 110 // Wide Timer 0A
|
||||
#define INT_WTIMER0B 111 // Wide Timer 0B
|
||||
#define INT_WTIMER1A 112 // Wide Timer 1A
|
||||
#define INT_WTIMER1B 113 // Wide Timer 1B
|
||||
#define INT_WTIMER2A 114 // Wide Timer 2A
|
||||
#define INT_WTIMER2B 115 // Wide Timer 2B
|
||||
#define INT_WTIMER3A 116 // Wide Timer 3A
|
||||
#define INT_WTIMER3B 117 // Wide Timer 3B
|
||||
#define INT_WTIMER4A 118 // Wide Timer 4A
|
||||
#define INT_WTIMER4B 119 // Wide Timer 4B
|
||||
#define INT_WTIMER5A 120 // Wide Timer 5A
|
||||
#define INT_WTIMER5B 121 // Wide Timer 5B
|
||||
#define INT_SYSEXC 122 // System Exception (imprecise)
|
||||
#define INT_PECI0 123 // PECI 0
|
||||
#define INT_LPC0 124 // LPC 0
|
||||
#define INT_I2C4 125 // I2C4
|
||||
#define INT_I2C5 126 // I2C5
|
||||
#define INT_GPIOM 127 // GPIO Port M
|
||||
#define INT_GPION 128 // GPIO Port N
|
||||
#define INT_FAN0 130 // FAN 0
|
||||
#define INT_GPIOP0 132 // GPIO Port P (Summary or P0)
|
||||
#define INT_GPIOP1 133 // GPIO Port P1
|
||||
#define INT_GPIOP2 134 // GPIO Port P2
|
||||
#define INT_GPIOP3 135 // GPIO Port P3
|
||||
#define INT_GPIOP4 136 // GPIO Port P4
|
||||
#define INT_GPIOP5 137 // GPIO Port P5
|
||||
#define INT_GPIOP6 138 // GPIO Port P6
|
||||
#define INT_GPIOP7 139 // GPIO Port P7
|
||||
#define INT_GPIOQ0 140 // GPIO Port Q (Summary or Q0)
|
||||
#define INT_GPIOQ1 141 // GPIO Port Q1
|
||||
#define INT_GPIOQ2 142 // GPIO Port Q2
|
||||
#define INT_GPIOQ3 143 // GPIO Port Q3
|
||||
#define INT_GPIOQ4 144 // GPIO Port Q4
|
||||
#define INT_GPIOQ5 145 // GPIO Port Q5
|
||||
#define INT_GPIOQ6 146 // GPIO Port Q6
|
||||
#define INT_GPIOQ7 147 // GPIO Port Q7
|
||||
#define INT_PWM1_0 150 // PWM1 Generator 0
|
||||
#define INT_PWM1_1 151 // PWM1 Generator 1
|
||||
#define INT_PWM1_2 152 // PWM1 Generator 2
|
||||
#define INT_PWM1_3 153 // PWM1 Generator 3
|
||||
#define INT_PWM1_FAULT 154 // PWM1 Fault
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the total number of interrupts.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NUM_INTERRUPTS 155
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the total number of priority levels.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NUM_PRIORITY 8
|
||||
#define NUM_PRIORITY_BITS 3
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following definitions are deprecated.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the interrupt assignments.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define INT_SSI 23 // SSI Rx and Tx
|
||||
#define INT_I2C 24 // I2C Master and Slave
|
||||
#define INT_PWM_FAULT 25 // PWM Fault
|
||||
#define INT_PWM0 26 // PWM Generator 0
|
||||
#define INT_PWM1 27 // PWM Generator 1
|
||||
#define INT_PWM2 28 // PWM Generator 2
|
||||
#define INT_QEI 29 // Quadrature Encoder
|
||||
#define INT_ADC0 30 // ADC Sequence 0
|
||||
#define INT_ADC1 31 // ADC Sequence 1
|
||||
#define INT_ADC2 32 // ADC Sequence 2
|
||||
#define INT_ADC3 33 // ADC Sequence 3
|
||||
#define INT_PWM3 61 // PWM Generator 3
|
||||
|
||||
#endif
|
||||
|
||||
#endif // __HW_INTS_H__
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_ints.h - Macros that define the interrupt assignment on Stellaris.
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_INTS_H__
|
||||
#define __HW_INTS_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the fault assignments.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FAULT_NMI 2 // NMI fault
|
||||
#define FAULT_HARD 3 // Hard fault
|
||||
#define FAULT_MPU 4 // MPU fault
|
||||
#define FAULT_BUS 5 // Bus fault
|
||||
#define FAULT_USAGE 6 // Usage fault
|
||||
#define FAULT_SVCALL 11 // SVCall
|
||||
#define FAULT_DEBUG 12 // Debug monitor
|
||||
#define FAULT_PENDSV 14 // PendSV
|
||||
#define FAULT_SYSTICK 15 // System Tick
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the interrupt assignments.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define INT_GPIOA 16 // GPIO Port A
|
||||
#define INT_GPIOB 17 // GPIO Port B
|
||||
#define INT_GPIOC 18 // GPIO Port C
|
||||
#define INT_GPIOD 19 // GPIO Port D
|
||||
#define INT_GPIOE 20 // GPIO Port E
|
||||
#define INT_UART0 21 // UART0 Rx and Tx
|
||||
#define INT_UART1 22 // UART1 Rx and Tx
|
||||
#define INT_SSI0 23 // SSI0 Rx and Tx
|
||||
#define INT_I2C0 24 // I2C0 Master and Slave
|
||||
#define INT_PWM0_FAULT 25 // PWM0 Fault
|
||||
#define INT_PWM0_0 26 // PWM0 Generator 0
|
||||
#define INT_PWM0_1 27 // PWM0 Generator 1
|
||||
#define INT_PWM0_2 28 // PWM0 Generator 2
|
||||
#define INT_QEI0 29 // Quadrature Encoder 0
|
||||
#define INT_ADC0SS0 30 // ADC0 Sequence 0
|
||||
#define INT_ADC0SS1 31 // ADC0 Sequence 1
|
||||
#define INT_ADC0SS2 32 // ADC0 Sequence 2
|
||||
#define INT_ADC0SS3 33 // ADC0 Sequence 3
|
||||
#define INT_WATCHDOG 34 // Watchdog timer
|
||||
#define INT_TIMER0A 35 // Timer 0 subtimer A
|
||||
#define INT_TIMER0B 36 // Timer 0 subtimer B
|
||||
#define INT_TIMER1A 37 // Timer 1 subtimer A
|
||||
#define INT_TIMER1B 38 // Timer 1 subtimer B
|
||||
#define INT_TIMER2A 39 // Timer 2 subtimer A
|
||||
#define INT_TIMER2B 40 // Timer 2 subtimer B
|
||||
#define INT_COMP0 41 // Analog Comparator 0
|
||||
#define INT_COMP1 42 // Analog Comparator 1
|
||||
#define INT_COMP2 43 // Analog Comparator 2
|
||||
#define INT_SYSCTL 44 // System Control (PLL, OSC, BO)
|
||||
#define INT_FLASH 45 // FLASH Control
|
||||
#define INT_GPIOF 46 // GPIO Port F
|
||||
#define INT_GPIOG 47 // GPIO Port G
|
||||
#define INT_GPIOH 48 // GPIO Port H
|
||||
#define INT_UART2 49 // UART2 Rx and Tx
|
||||
#define INT_SSI1 50 // SSI1 Rx and Tx
|
||||
#define INT_TIMER3A 51 // Timer 3 subtimer A
|
||||
#define INT_TIMER3B 52 // Timer 3 subtimer B
|
||||
#define INT_I2C1 53 // I2C1 Master and Slave
|
||||
#define INT_QEI1 54 // Quadrature Encoder 1
|
||||
#define INT_CAN0 55 // CAN0
|
||||
#define INT_CAN1 56 // CAN1
|
||||
#define INT_CAN2 57 // CAN2
|
||||
#define INT_ETH 58 // Ethernet
|
||||
#define INT_HIBERNATE 59 // Hibernation module
|
||||
#define INT_USB0 60 // USB 0 Controller
|
||||
#define INT_PWM0_3 61 // PWM0 Generator 3
|
||||
#define INT_UDMA 62 // uDMA controller
|
||||
#define INT_UDMAERR 63 // uDMA Error
|
||||
#define INT_ADC1SS0 64 // ADC1 Sequence 0
|
||||
#define INT_ADC1SS1 65 // ADC1 Sequence 1
|
||||
#define INT_ADC1SS2 66 // ADC1 Sequence 2
|
||||
#define INT_ADC1SS3 67 // ADC1 Sequence 3
|
||||
#define INT_I2S0 68 // I2S0
|
||||
#define INT_EPI0 69 // EPI0
|
||||
#define INT_GPIOJ 70 // GPIO Port J
|
||||
#define INT_GPIOK 71 // GPIO Port K
|
||||
#define INT_GPIOL 72 // GPIO Port L
|
||||
#define INT_SSI2 73 // SSI2
|
||||
#define INT_SSI3 74 // SSI3
|
||||
#define INT_UART3 75 // UART3
|
||||
#define INT_UART4 76 // UART4
|
||||
#define INT_UART5 77 // UART5
|
||||
#define INT_UART6 78 // UART6
|
||||
#define INT_UART7 79 // UART7
|
||||
#define INT_I2C2 84 // I2C2
|
||||
#define INT_I2C3 85 // I2C3
|
||||
#define INT_TIMER4A 86 // Timer 4A
|
||||
#define INT_TIMER4B 87 // Timer 4B
|
||||
#define INT_TIMER5A 108 // Timer 5A
|
||||
#define INT_TIMER5B 109 // Timer 5B
|
||||
#define INT_WTIMER0A 110 // Wide Timer 0A
|
||||
#define INT_WTIMER0B 111 // Wide Timer 0B
|
||||
#define INT_WTIMER1A 112 // Wide Timer 1A
|
||||
#define INT_WTIMER1B 113 // Wide Timer 1B
|
||||
#define INT_WTIMER2A 114 // Wide Timer 2A
|
||||
#define INT_WTIMER2B 115 // Wide Timer 2B
|
||||
#define INT_WTIMER3A 116 // Wide Timer 3A
|
||||
#define INT_WTIMER3B 117 // Wide Timer 3B
|
||||
#define INT_WTIMER4A 118 // Wide Timer 4A
|
||||
#define INT_WTIMER4B 119 // Wide Timer 4B
|
||||
#define INT_WTIMER5A 120 // Wide Timer 5A
|
||||
#define INT_WTIMER5B 121 // Wide Timer 5B
|
||||
#define INT_SYSEXC 122 // System Exception (imprecise)
|
||||
#define INT_PECI0 123 // PECI 0
|
||||
#define INT_LPC0 124 // LPC 0
|
||||
#define INT_I2C4 125 // I2C4
|
||||
#define INT_I2C5 126 // I2C5
|
||||
#define INT_GPIOM 127 // GPIO Port M
|
||||
#define INT_GPION 128 // GPIO Port N
|
||||
#define INT_FAN0 130 // FAN 0
|
||||
#define INT_GPIOP0 132 // GPIO Port P (Summary or P0)
|
||||
#define INT_GPIOP1 133 // GPIO Port P1
|
||||
#define INT_GPIOP2 134 // GPIO Port P2
|
||||
#define INT_GPIOP3 135 // GPIO Port P3
|
||||
#define INT_GPIOP4 136 // GPIO Port P4
|
||||
#define INT_GPIOP5 137 // GPIO Port P5
|
||||
#define INT_GPIOP6 138 // GPIO Port P6
|
||||
#define INT_GPIOP7 139 // GPIO Port P7
|
||||
#define INT_GPIOQ0 140 // GPIO Port Q (Summary or Q0)
|
||||
#define INT_GPIOQ1 141 // GPIO Port Q1
|
||||
#define INT_GPIOQ2 142 // GPIO Port Q2
|
||||
#define INT_GPIOQ3 143 // GPIO Port Q3
|
||||
#define INT_GPIOQ4 144 // GPIO Port Q4
|
||||
#define INT_GPIOQ5 145 // GPIO Port Q5
|
||||
#define INT_GPIOQ6 146 // GPIO Port Q6
|
||||
#define INT_GPIOQ7 147 // GPIO Port Q7
|
||||
#define INT_PWM1_0 150 // PWM1 Generator 0
|
||||
#define INT_PWM1_1 151 // PWM1 Generator 1
|
||||
#define INT_PWM1_2 152 // PWM1 Generator 2
|
||||
#define INT_PWM1_3 153 // PWM1 Generator 3
|
||||
#define INT_PWM1_FAULT 154 // PWM1 Fault
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the total number of interrupts.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NUM_INTERRUPTS 155
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the total number of priority levels.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define NUM_PRIORITY 8
|
||||
#define NUM_PRIORITY_BITS 3
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following definitions are deprecated.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the interrupt assignments.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define INT_SSI 23 // SSI Rx and Tx
|
||||
#define INT_I2C 24 // I2C Master and Slave
|
||||
#define INT_PWM_FAULT 25 // PWM Fault
|
||||
#define INT_PWM0 26 // PWM Generator 0
|
||||
#define INT_PWM1 27 // PWM Generator 1
|
||||
#define INT_PWM2 28 // PWM Generator 2
|
||||
#define INT_QEI 29 // Quadrature Encoder
|
||||
#define INT_ADC0 30 // ADC Sequence 0
|
||||
#define INT_ADC1 31 // ADC Sequence 1
|
||||
#define INT_ADC2 32 // ADC Sequence 2
|
||||
#define INT_ADC3 33 // ADC Sequence 3
|
||||
#define INT_PWM3 61 // PWM Generator 3
|
||||
|
||||
#endif
|
||||
|
||||
#endif // __HW_INTS_H__
|
||||
|
||||
@ -1,164 +1,164 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_memmap.h - Macros defining the memory map of Stellaris.
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_MEMMAP_H__
|
||||
#define __HW_MEMMAP_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the base address of the memories and
|
||||
// peripherals.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_BASE 0x00000000 // FLASH memory
|
||||
#define SRAM_BASE 0x20000000 // SRAM memory
|
||||
#define WATCHDOG0_BASE 0x40000000 // Watchdog0
|
||||
#define WATCHDOG1_BASE 0x40001000 // Watchdog1
|
||||
#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A
|
||||
#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B
|
||||
#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C
|
||||
#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D
|
||||
#define SSI0_BASE 0x40008000 // SSI0
|
||||
#define SSI1_BASE 0x40009000 // SSI1
|
||||
#define SSI2_BASE 0x4000A000 // SSI2
|
||||
#define SSI3_BASE 0x4000B000 // SSI3
|
||||
#define UART0_BASE 0x4000C000 // UART0
|
||||
#define UART1_BASE 0x4000D000 // UART1
|
||||
#define UART2_BASE 0x4000E000 // UART2
|
||||
#define UART3_BASE 0x4000F000 // UART3
|
||||
#define UART4_BASE 0x40010000 // UART4
|
||||
#define UART5_BASE 0x40011000 // UART5
|
||||
#define UART6_BASE 0x40012000 // UART6
|
||||
#define UART7_BASE 0x40013000 // UART7
|
||||
#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master
|
||||
#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave
|
||||
#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master
|
||||
#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave
|
||||
#define I2C2_MASTER_BASE 0x40022000 // I2C2 Master
|
||||
#define I2C2_SLAVE_BASE 0x40022800 // I2C2 Slave
|
||||
#define I2C3_MASTER_BASE 0x40023000 // I2C3 Master
|
||||
#define I2C3_SLAVE_BASE 0x40023800 // I2C3 Slave
|
||||
#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E
|
||||
#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F
|
||||
#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G
|
||||
#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H
|
||||
#define PWM0_BASE 0x40028000 // Pulse Width Modulator (PWM)
|
||||
#define PWM1_BASE 0x40029000 // Pulse Width Modulator (PWM)
|
||||
#define QEI0_BASE 0x4002C000 // QEI0
|
||||
#define QEI1_BASE 0x4002D000 // QEI1
|
||||
#define TIMER0_BASE 0x40030000 // Timer0
|
||||
#define TIMER1_BASE 0x40031000 // Timer1
|
||||
#define TIMER2_BASE 0x40032000 // Timer2
|
||||
#define TIMER3_BASE 0x40033000 // Timer3
|
||||
#define TIMER4_BASE 0x40034000 // Timer4
|
||||
#define TIMER5_BASE 0x40035000 // Timer5
|
||||
#define WTIMER0_BASE 0x40036000 // Wide Timer0
|
||||
#define WTIMER1_BASE 0x40037000 // Wide Timer1
|
||||
#define ADC0_BASE 0x40038000 // ADC0
|
||||
#define ADC1_BASE 0x40039000 // ADC1
|
||||
#define COMP_BASE 0x4003C000 // Analog comparators
|
||||
#define GPIO_PORTJ_BASE 0x4003D000 // GPIO Port J
|
||||
#define CAN0_BASE 0x40040000 // CAN0
|
||||
#define CAN1_BASE 0x40041000 // CAN1
|
||||
#define CAN2_BASE 0x40042000 // CAN2
|
||||
#define ETH_BASE 0x40048000 // Ethernet
|
||||
#define MAC_BASE 0x40048000 // Ethernet
|
||||
#define WTIMER2_BASE 0x4004C000 // Wide Timer2
|
||||
#define WTIMER3_BASE 0x4004D000 // Wide Timer3
|
||||
#define WTIMER4_BASE 0x4004E000 // Wide Timer4
|
||||
#define WTIMER5_BASE 0x4004F000 // Wide Timer5
|
||||
#define USB0_BASE 0x40050000 // USB 0 Controller
|
||||
#define I2S0_BASE 0x40054000 // I2S0
|
||||
#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed)
|
||||
#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed)
|
||||
#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed)
|
||||
#define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed)
|
||||
#define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed)
|
||||
#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed)
|
||||
#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed)
|
||||
#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed)
|
||||
#define GPIO_PORTJ_AHB_BASE 0x40060000 // GPIO Port J (high speed)
|
||||
#define GPIO_PORTK_BASE 0x40061000 // GPIO Port K
|
||||
#define GPIO_PORTL_BASE 0x40062000 // GPIO Port L
|
||||
#define GPIO_PORTM_BASE 0x40063000 // GPIO Port M
|
||||
#define GPIO_PORTN_BASE 0x40064000 // GPIO Port N
|
||||
#define GPIO_PORTP_BASE 0x40065000 // GPIO Port P
|
||||
#define GPIO_PORTQ_BASE 0x40066000 // GPIO Port Q
|
||||
#define LPC0_BASE 0x40080000 // Low Pin Count Interface (LPC)
|
||||
#define FAN0_BASE 0x40084000 // Fan Control (FAN)
|
||||
#define EEPROM_BASE 0x400AF000 // EEPROM memory
|
||||
#define PECI0_BASE 0x400B0000 // Platform Environment Control
|
||||
// Interface (PECI)
|
||||
#define I2C4_MASTER_BASE 0x400C0000 // I2C4 Master
|
||||
#define I2C4_SLAVE_BASE 0x400C0800 // I2C4 Slave
|
||||
#define I2C5_MASTER_BASE 0x400C1000 // I2C5 Master
|
||||
#define I2C5_SLAVE_BASE 0x400C1800 // I2C5 Slave
|
||||
#define EPI0_BASE 0x400D0000 // EPI0
|
||||
#define SYSEXC_BASE 0x400F9000 // System Exception Module
|
||||
#define HIB_BASE 0x400FC000 // Hibernation Module
|
||||
#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller
|
||||
#define SYSCTL_BASE 0x400FE000 // System Control
|
||||
#define UDMA_BASE 0x400FF000 // uDMA Controller
|
||||
#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint
|
||||
#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following definitions are deprecated.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the base address of the memories
|
||||
// and peripherals.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WATCHDOG_BASE 0x40000000 // Watchdog
|
||||
#define SSI_BASE 0x40008000 // SSI
|
||||
#define I2C_MASTER_BASE 0x40020000 // I2C Master
|
||||
#define I2C_SLAVE_BASE 0x40020800 // I2C Slave
|
||||
#define PWM_BASE 0x40028000 // PWM
|
||||
#define QEI_BASE 0x4002C000 // QEI
|
||||
#define ADC_BASE 0x40038000 // ADC
|
||||
|
||||
#endif
|
||||
|
||||
#endif // __HW_MEMMAP_H__
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_memmap.h - Macros defining the memory map of Stellaris.
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_MEMMAP_H__
|
||||
#define __HW_MEMMAP_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the base address of the memories and
|
||||
// peripherals.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FLASH_BASE 0x00000000 // FLASH memory
|
||||
#define SRAM_BASE 0x20000000 // SRAM memory
|
||||
#define WATCHDOG0_BASE 0x40000000 // Watchdog0
|
||||
#define WATCHDOG1_BASE 0x40001000 // Watchdog1
|
||||
#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A
|
||||
#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B
|
||||
#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C
|
||||
#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D
|
||||
#define SSI0_BASE 0x40008000 // SSI0
|
||||
#define SSI1_BASE 0x40009000 // SSI1
|
||||
#define SSI2_BASE 0x4000A000 // SSI2
|
||||
#define SSI3_BASE 0x4000B000 // SSI3
|
||||
#define UART0_BASE 0x4000C000 // UART0
|
||||
#define UART1_BASE 0x4000D000 // UART1
|
||||
#define UART2_BASE 0x4000E000 // UART2
|
||||
#define UART3_BASE 0x4000F000 // UART3
|
||||
#define UART4_BASE 0x40010000 // UART4
|
||||
#define UART5_BASE 0x40011000 // UART5
|
||||
#define UART6_BASE 0x40012000 // UART6
|
||||
#define UART7_BASE 0x40013000 // UART7
|
||||
#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master
|
||||
#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave
|
||||
#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master
|
||||
#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave
|
||||
#define I2C2_MASTER_BASE 0x40022000 // I2C2 Master
|
||||
#define I2C2_SLAVE_BASE 0x40022800 // I2C2 Slave
|
||||
#define I2C3_MASTER_BASE 0x40023000 // I2C3 Master
|
||||
#define I2C3_SLAVE_BASE 0x40023800 // I2C3 Slave
|
||||
#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E
|
||||
#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F
|
||||
#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G
|
||||
#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H
|
||||
#define PWM0_BASE 0x40028000 // Pulse Width Modulator (PWM)
|
||||
#define PWM1_BASE 0x40029000 // Pulse Width Modulator (PWM)
|
||||
#define QEI0_BASE 0x4002C000 // QEI0
|
||||
#define QEI1_BASE 0x4002D000 // QEI1
|
||||
#define TIMER0_BASE 0x40030000 // Timer0
|
||||
#define TIMER1_BASE 0x40031000 // Timer1
|
||||
#define TIMER2_BASE 0x40032000 // Timer2
|
||||
#define TIMER3_BASE 0x40033000 // Timer3
|
||||
#define TIMER4_BASE 0x40034000 // Timer4
|
||||
#define TIMER5_BASE 0x40035000 // Timer5
|
||||
#define WTIMER0_BASE 0x40036000 // Wide Timer0
|
||||
#define WTIMER1_BASE 0x40037000 // Wide Timer1
|
||||
#define ADC0_BASE 0x40038000 // ADC0
|
||||
#define ADC1_BASE 0x40039000 // ADC1
|
||||
#define COMP_BASE 0x4003C000 // Analog comparators
|
||||
#define GPIO_PORTJ_BASE 0x4003D000 // GPIO Port J
|
||||
#define CAN0_BASE 0x40040000 // CAN0
|
||||
#define CAN1_BASE 0x40041000 // CAN1
|
||||
#define CAN2_BASE 0x40042000 // CAN2
|
||||
#define ETH_BASE 0x40048000 // Ethernet
|
||||
#define MAC_BASE 0x40048000 // Ethernet
|
||||
#define WTIMER2_BASE 0x4004C000 // Wide Timer2
|
||||
#define WTIMER3_BASE 0x4004D000 // Wide Timer3
|
||||
#define WTIMER4_BASE 0x4004E000 // Wide Timer4
|
||||
#define WTIMER5_BASE 0x4004F000 // Wide Timer5
|
||||
#define USB0_BASE 0x40050000 // USB 0 Controller
|
||||
#define I2S0_BASE 0x40054000 // I2S0
|
||||
#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed)
|
||||
#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed)
|
||||
#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed)
|
||||
#define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed)
|
||||
#define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed)
|
||||
#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed)
|
||||
#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed)
|
||||
#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed)
|
||||
#define GPIO_PORTJ_AHB_BASE 0x40060000 // GPIO Port J (high speed)
|
||||
#define GPIO_PORTK_BASE 0x40061000 // GPIO Port K
|
||||
#define GPIO_PORTL_BASE 0x40062000 // GPIO Port L
|
||||
#define GPIO_PORTM_BASE 0x40063000 // GPIO Port M
|
||||
#define GPIO_PORTN_BASE 0x40064000 // GPIO Port N
|
||||
#define GPIO_PORTP_BASE 0x40065000 // GPIO Port P
|
||||
#define GPIO_PORTQ_BASE 0x40066000 // GPIO Port Q
|
||||
#define LPC0_BASE 0x40080000 // Low Pin Count Interface (LPC)
|
||||
#define FAN0_BASE 0x40084000 // Fan Control (FAN)
|
||||
#define EEPROM_BASE 0x400AF000 // EEPROM memory
|
||||
#define PECI0_BASE 0x400B0000 // Platform Environment Control
|
||||
// Interface (PECI)
|
||||
#define I2C4_MASTER_BASE 0x400C0000 // I2C4 Master
|
||||
#define I2C4_SLAVE_BASE 0x400C0800 // I2C4 Slave
|
||||
#define I2C5_MASTER_BASE 0x400C1000 // I2C5 Master
|
||||
#define I2C5_SLAVE_BASE 0x400C1800 // I2C5 Slave
|
||||
#define EPI0_BASE 0x400D0000 // EPI0
|
||||
#define SYSEXC_BASE 0x400F9000 // System Exception Module
|
||||
#define HIB_BASE 0x400FC000 // Hibernation Module
|
||||
#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller
|
||||
#define SYSCTL_BASE 0x400FE000 // System Control
|
||||
#define UDMA_BASE 0x400FF000 // uDMA Controller
|
||||
#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint
|
||||
#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following definitions are deprecated.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the base address of the memories
|
||||
// and peripherals.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WATCHDOG_BASE 0x40000000 // Watchdog
|
||||
#define SSI_BASE 0x40008000 // SSI
|
||||
#define I2C_MASTER_BASE 0x40020000 // I2C Master
|
||||
#define I2C_SLAVE_BASE 0x40020800 // I2C Slave
|
||||
#define PWM_BASE 0x40028000 // PWM
|
||||
#define QEI_BASE 0x4002C000 // QEI
|
||||
#define ADC_BASE 0x40038000 // ADC
|
||||
|
||||
#endif
|
||||
|
||||
#endif // __HW_MEMMAP_H__
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,244 +1,244 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_ssi.h - Macros used when accessing the SSI hardware.
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_SSI_H__
|
||||
#define __HW_SSI_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the SSI register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_O_CR0 0x00000000 // SSI Control 0
|
||||
#define SSI_O_CR1 0x00000004 // SSI Control 1
|
||||
#define SSI_O_DR 0x00000008 // SSI Data
|
||||
#define SSI_O_SR 0x0000000C // SSI Status
|
||||
#define SSI_O_CPSR 0x00000010 // SSI Clock Prescale
|
||||
#define SSI_O_IM 0x00000014 // SSI Interrupt Mask
|
||||
#define SSI_O_RIS 0x00000018 // SSI Raw Interrupt Status
|
||||
#define SSI_O_MIS 0x0000001C // SSI Masked Interrupt Status
|
||||
#define SSI_O_ICR 0x00000020 // SSI Interrupt Clear
|
||||
#define SSI_O_DMACTL 0x00000024 // SSI DMA Control
|
||||
#define SSI_O_CC 0x00000FC8 // SSI Clock Configuration
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_CR0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate
|
||||
#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase
|
||||
#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity
|
||||
#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select
|
||||
#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format
|
||||
#define SSI_CR0_FRF_TI 0x00000010 // Texas Instruments Synchronous
|
||||
// Serial Frame Format
|
||||
#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format
|
||||
#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select
|
||||
#define SSI_CR0_DSS_4 0x00000003 // 4-bit data
|
||||
#define SSI_CR0_DSS_5 0x00000004 // 5-bit data
|
||||
#define SSI_CR0_DSS_6 0x00000005 // 6-bit data
|
||||
#define SSI_CR0_DSS_7 0x00000006 // 7-bit data
|
||||
#define SSI_CR0_DSS_8 0x00000007 // 8-bit data
|
||||
#define SSI_CR0_DSS_9 0x00000008 // 9-bit data
|
||||
#define SSI_CR0_DSS_10 0x00000009 // 10-bit data
|
||||
#define SSI_CR0_DSS_11 0x0000000A // 11-bit data
|
||||
#define SSI_CR0_DSS_12 0x0000000B // 12-bit data
|
||||
#define SSI_CR0_DSS_13 0x0000000C // 13-bit data
|
||||
#define SSI_CR0_DSS_14 0x0000000D // 14-bit data
|
||||
#define SSI_CR0_DSS_15 0x0000000E // 15-bit data
|
||||
#define SSI_CR0_DSS_16 0x0000000F // 16-bit data
|
||||
#define SSI_CR0_SCR_S 8
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_CR1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_CR1_EOT 0x00000010 // End of Transmission
|
||||
#define SSI_CR1_SOD 0x00000008 // SSI Slave Mode Output Disable
|
||||
#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select
|
||||
#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port
|
||||
// Enable
|
||||
#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_DR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data
|
||||
#define SSI_DR_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_SR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_SR_BSY 0x00000010 // SSI Busy Bit
|
||||
#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full
|
||||
#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty
|
||||
#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full
|
||||
#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_CPSR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor
|
||||
#define SSI_CPSR_CPSDVSR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_IM register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask
|
||||
#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask
|
||||
#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt
|
||||
// Mask
|
||||
#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt
|
||||
// Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_RIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt
|
||||
// Status
|
||||
#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt
|
||||
// Status
|
||||
#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw
|
||||
// Interrupt Status
|
||||
#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw
|
||||
// Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_MIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked
|
||||
// Interrupt Status
|
||||
#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked
|
||||
// Interrupt Status
|
||||
#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked
|
||||
// Interrupt Status
|
||||
#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked
|
||||
// Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_ICR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt
|
||||
// Clear
|
||||
#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt
|
||||
// Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_DMACTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
|
||||
#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_CC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source
|
||||
#define SSI_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the
|
||||
// PLL bypass is in effect) or the
|
||||
// PLL output (default)
|
||||
#define SSI_CC_CS_PIOSC 0x00000005 // PIOSC
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following definitions are deprecated.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the SSI_O_CR0
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate
|
||||
#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask
|
||||
#define SSI_CR0_DSS 0x0000000F // Data size select
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the SSI_O_CPSR
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the SSI controller's FIFO size.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO
|
||||
#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the interrupt
|
||||
// mask set and clear, raw interrupt, masked interrupt, and interrupt clear
|
||||
// registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt
|
||||
#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt
|
||||
#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt
|
||||
#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt
|
||||
|
||||
#endif
|
||||
|
||||
#endif // __HW_SSI_H__
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_ssi.h - Macros used when accessing the SSI hardware.
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_SSI_H__
|
||||
#define __HW_SSI_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the SSI register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_O_CR0 0x00000000 // SSI Control 0
|
||||
#define SSI_O_CR1 0x00000004 // SSI Control 1
|
||||
#define SSI_O_DR 0x00000008 // SSI Data
|
||||
#define SSI_O_SR 0x0000000C // SSI Status
|
||||
#define SSI_O_CPSR 0x00000010 // SSI Clock Prescale
|
||||
#define SSI_O_IM 0x00000014 // SSI Interrupt Mask
|
||||
#define SSI_O_RIS 0x00000018 // SSI Raw Interrupt Status
|
||||
#define SSI_O_MIS 0x0000001C // SSI Masked Interrupt Status
|
||||
#define SSI_O_ICR 0x00000020 // SSI Interrupt Clear
|
||||
#define SSI_O_DMACTL 0x00000024 // SSI DMA Control
|
||||
#define SSI_O_CC 0x00000FC8 // SSI Clock Configuration
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_CR0 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate
|
||||
#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase
|
||||
#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity
|
||||
#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select
|
||||
#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format
|
||||
#define SSI_CR0_FRF_TI 0x00000010 // Texas Instruments Synchronous
|
||||
// Serial Frame Format
|
||||
#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format
|
||||
#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select
|
||||
#define SSI_CR0_DSS_4 0x00000003 // 4-bit data
|
||||
#define SSI_CR0_DSS_5 0x00000004 // 5-bit data
|
||||
#define SSI_CR0_DSS_6 0x00000005 // 6-bit data
|
||||
#define SSI_CR0_DSS_7 0x00000006 // 7-bit data
|
||||
#define SSI_CR0_DSS_8 0x00000007 // 8-bit data
|
||||
#define SSI_CR0_DSS_9 0x00000008 // 9-bit data
|
||||
#define SSI_CR0_DSS_10 0x00000009 // 10-bit data
|
||||
#define SSI_CR0_DSS_11 0x0000000A // 11-bit data
|
||||
#define SSI_CR0_DSS_12 0x0000000B // 12-bit data
|
||||
#define SSI_CR0_DSS_13 0x0000000C // 13-bit data
|
||||
#define SSI_CR0_DSS_14 0x0000000D // 14-bit data
|
||||
#define SSI_CR0_DSS_15 0x0000000E // 15-bit data
|
||||
#define SSI_CR0_DSS_16 0x0000000F // 16-bit data
|
||||
#define SSI_CR0_SCR_S 8
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_CR1 register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_CR1_EOT 0x00000010 // End of Transmission
|
||||
#define SSI_CR1_SOD 0x00000008 // SSI Slave Mode Output Disable
|
||||
#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select
|
||||
#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port
|
||||
// Enable
|
||||
#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_DR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data
|
||||
#define SSI_DR_DATA_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_SR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_SR_BSY 0x00000010 // SSI Busy Bit
|
||||
#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full
|
||||
#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty
|
||||
#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full
|
||||
#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_CPSR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor
|
||||
#define SSI_CPSR_CPSDVSR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_IM register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask
|
||||
#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask
|
||||
#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt
|
||||
// Mask
|
||||
#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt
|
||||
// Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_RIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt
|
||||
// Status
|
||||
#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt
|
||||
// Status
|
||||
#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw
|
||||
// Interrupt Status
|
||||
#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw
|
||||
// Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_MIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked
|
||||
// Interrupt Status
|
||||
#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked
|
||||
// Interrupt Status
|
||||
#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked
|
||||
// Interrupt Status
|
||||
#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked
|
||||
// Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_ICR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt
|
||||
// Clear
|
||||
#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt
|
||||
// Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_DMACTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
|
||||
#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SSI_O_CC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source
|
||||
#define SSI_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the
|
||||
// PLL bypass is in effect) or the
|
||||
// PLL output (default)
|
||||
#define SSI_CC_CS_PIOSC 0x00000005 // PIOSC
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following definitions are deprecated.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the SSI_O_CR0
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate
|
||||
#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask
|
||||
#define SSI_CR0_DSS 0x0000000F // Data size select
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the SSI_O_CPSR
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the SSI controller's FIFO size.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO
|
||||
#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the interrupt
|
||||
// mask set and clear, raw interrupt, masked interrupt, and interrupt clear
|
||||
// registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt
|
||||
#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt
|
||||
#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt
|
||||
#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt
|
||||
|
||||
#endif
|
||||
|
||||
#endif // __HW_SSI_H__
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,132 +1,132 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_sysexc.h - Macros used when accessing the system exception module.
|
||||
//
|
||||
// Copyright (c) 2011-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_SYSEXC_H__
|
||||
#define __HW_SYSEXC_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the System Exception Module register
|
||||
// addresses.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSEXC_RIS 0x400F9000 // System Exception Raw Interrupt
|
||||
// Status
|
||||
#define SYSEXC_IM 0x400F9004 // System Exception Interrupt Mask
|
||||
#define SYSEXC_MIS 0x400F9008 // System Exception Masked
|
||||
// Interrupt Status
|
||||
#define SYSEXC_IC 0x400F900C // System Exception Interrupt Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SYSEXC_RIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSEXC_RIS_FPIXCRIS 0x00000020 // Floating-Point Inexact Exception
|
||||
// Raw Interrupt Status
|
||||
#define SYSEXC_RIS_FPOFCRIS 0x00000010 // Floating-Point Overflow
|
||||
// Exception Raw Interrupt Status
|
||||
#define SYSEXC_RIS_FPUFCRIS 0x00000008 // Floating-Point Underflow
|
||||
// Exception Raw Interrupt Status
|
||||
#define SYSEXC_RIS_FPIOCRIS 0x00000004 // Floating-Point Invalid Operation
|
||||
// Raw Interrupt Status
|
||||
#define SYSEXC_RIS_FPDZCRIS 0x00000002 // Floating-Point Divide By 0
|
||||
// Exception Raw Interrupt Status
|
||||
#define SYSEXC_RIS_FPIDCRIS 0x00000001 // Floating-Point Input Denormal
|
||||
// Exception Raw Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SYSEXC_IM register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSEXC_IM_FPIXCIM 0x00000020 // Floating-Point Inexact Exception
|
||||
// Interrupt Mask
|
||||
#define SYSEXC_IM_FPOFCIM 0x00000010 // Floating-Point Overflow
|
||||
// Exception Interrupt Mask
|
||||
#define SYSEXC_IM_FPUFCIM 0x00000008 // Floating-Point Underflow
|
||||
// Exception Interrupt Mask
|
||||
#define SYSEXC_IM_FPIOCIM 0x00000004 // Floating-Point Invalid Operation
|
||||
// Interrupt Mask
|
||||
#define SYSEXC_IM_FPDZCIM 0x00000002 // Floating-Point Divide By 0
|
||||
// Exception Interrupt Mask
|
||||
#define SYSEXC_IM_FPIDCIM 0x00000001 // Floating-Point Input Denormal
|
||||
// Exception Interrupt Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SYSEXC_MIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSEXC_MIS_FPIXCMIS 0x00000020 // Floating-Point Inexact Exception
|
||||
// Masked Interrupt Status
|
||||
#define SYSEXC_MIS_FPOFCMIS 0x00000010 // Floating-Point Overflow
|
||||
// Exception Masked Interrupt
|
||||
// Status
|
||||
#define SYSEXC_MIS_FPUFCMIS 0x00000008 // Floating-Point Underflow
|
||||
// Exception Masked Interrupt
|
||||
// Status
|
||||
#define SYSEXC_MIS_FPIOCMIS 0x00000004 // Floating-Point Invalid Operation
|
||||
// Masked Interrupt Status
|
||||
#define SYSEXC_MIS_FPDZCMIS 0x00000002 // Floating-Point Divide By 0
|
||||
// Exception Masked Interrupt
|
||||
// Status
|
||||
#define SYSEXC_MIS_FPIDCMIS 0x00000001 // Floating-Point Input Denormal
|
||||
// Exception Masked Interrupt
|
||||
// Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SYSEXC_IC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSEXC_IC_FPIXCIC 0x00000020 // Floating-Point Inexact Exception
|
||||
// Interrupt Clear
|
||||
#define SYSEXC_IC_FPOFCIC 0x00000010 // Floating-Point Overflow
|
||||
// Exception Interrupt Clear
|
||||
#define SYSEXC_IC_FPUFCIC 0x00000008 // Floating-Point Underflow
|
||||
// Exception Interrupt Clear
|
||||
#define SYSEXC_IC_FPIOCIC 0x00000004 // Floating-Point Invalid Operation
|
||||
// Interrupt Clear
|
||||
#define SYSEXC_IC_FPDZCIC 0x00000002 // Floating-Point Divide By 0
|
||||
// Exception Interrupt Clear
|
||||
#define SYSEXC_IC_FPIDCIC 0x00000001 // Floating-Point Input Denormal
|
||||
// Exception Interrupt Clear
|
||||
|
||||
#endif // __HW_SYSEXC_H__
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_sysexc.h - Macros used when accessing the system exception module.
|
||||
//
|
||||
// Copyright (c) 2011-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_SYSEXC_H__
|
||||
#define __HW_SYSEXC_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the System Exception Module register
|
||||
// addresses.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSEXC_RIS 0x400F9000 // System Exception Raw Interrupt
|
||||
// Status
|
||||
#define SYSEXC_IM 0x400F9004 // System Exception Interrupt Mask
|
||||
#define SYSEXC_MIS 0x400F9008 // System Exception Masked
|
||||
// Interrupt Status
|
||||
#define SYSEXC_IC 0x400F900C // System Exception Interrupt Clear
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SYSEXC_RIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSEXC_RIS_FPIXCRIS 0x00000020 // Floating-Point Inexact Exception
|
||||
// Raw Interrupt Status
|
||||
#define SYSEXC_RIS_FPOFCRIS 0x00000010 // Floating-Point Overflow
|
||||
// Exception Raw Interrupt Status
|
||||
#define SYSEXC_RIS_FPUFCRIS 0x00000008 // Floating-Point Underflow
|
||||
// Exception Raw Interrupt Status
|
||||
#define SYSEXC_RIS_FPIOCRIS 0x00000004 // Floating-Point Invalid Operation
|
||||
// Raw Interrupt Status
|
||||
#define SYSEXC_RIS_FPDZCRIS 0x00000002 // Floating-Point Divide By 0
|
||||
// Exception Raw Interrupt Status
|
||||
#define SYSEXC_RIS_FPIDCRIS 0x00000001 // Floating-Point Input Denormal
|
||||
// Exception Raw Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SYSEXC_IM register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSEXC_IM_FPIXCIM 0x00000020 // Floating-Point Inexact Exception
|
||||
// Interrupt Mask
|
||||
#define SYSEXC_IM_FPOFCIM 0x00000010 // Floating-Point Overflow
|
||||
// Exception Interrupt Mask
|
||||
#define SYSEXC_IM_FPUFCIM 0x00000008 // Floating-Point Underflow
|
||||
// Exception Interrupt Mask
|
||||
#define SYSEXC_IM_FPIOCIM 0x00000004 // Floating-Point Invalid Operation
|
||||
// Interrupt Mask
|
||||
#define SYSEXC_IM_FPDZCIM 0x00000002 // Floating-Point Divide By 0
|
||||
// Exception Interrupt Mask
|
||||
#define SYSEXC_IM_FPIDCIM 0x00000001 // Floating-Point Input Denormal
|
||||
// Exception Interrupt Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SYSEXC_MIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSEXC_MIS_FPIXCMIS 0x00000020 // Floating-Point Inexact Exception
|
||||
// Masked Interrupt Status
|
||||
#define SYSEXC_MIS_FPOFCMIS 0x00000010 // Floating-Point Overflow
|
||||
// Exception Masked Interrupt
|
||||
// Status
|
||||
#define SYSEXC_MIS_FPUFCMIS 0x00000008 // Floating-Point Underflow
|
||||
// Exception Masked Interrupt
|
||||
// Status
|
||||
#define SYSEXC_MIS_FPIOCMIS 0x00000004 // Floating-Point Invalid Operation
|
||||
// Masked Interrupt Status
|
||||
#define SYSEXC_MIS_FPDZCMIS 0x00000002 // Floating-Point Divide By 0
|
||||
// Exception Masked Interrupt
|
||||
// Status
|
||||
#define SYSEXC_MIS_FPIDCMIS 0x00000001 // Floating-Point Input Denormal
|
||||
// Exception Masked Interrupt
|
||||
// Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the SYSEXC_IC register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSEXC_IC_FPIXCIC 0x00000020 // Floating-Point Inexact Exception
|
||||
// Interrupt Clear
|
||||
#define SYSEXC_IC_FPOFCIC 0x00000010 // Floating-Point Overflow
|
||||
// Exception Interrupt Clear
|
||||
#define SYSEXC_IC_FPUFCIC 0x00000008 // Floating-Point Underflow
|
||||
// Exception Interrupt Clear
|
||||
#define SYSEXC_IC_FPIOCIC 0x00000004 // Floating-Point Invalid Operation
|
||||
// Interrupt Clear
|
||||
#define SYSEXC_IC_FPDZCIC 0x00000002 // Floating-Point Divide By 0
|
||||
// Exception Interrupt Clear
|
||||
#define SYSEXC_IC_FPIDCIC 0x00000001 // Floating-Point Input Denormal
|
||||
// Exception Interrupt Clear
|
||||
|
||||
#endif // __HW_SYSEXC_H__
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,218 +1,218 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_types.h - Common types and macros.
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_TYPES_H__
|
||||
#define __HW_TYPES_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Define a boolean type, and values for true and false.
|
||||
//
|
||||
//*****************************************************************************
|
||||
typedef unsigned char tBoolean;
|
||||
|
||||
#ifndef true
|
||||
#define true 1
|
||||
#endif
|
||||
|
||||
#ifndef false
|
||||
#define false 0
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Macros for hardware access, both direct and via the bit-band region.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HWREG(x) \
|
||||
(*((volatile unsigned long *)(x)))
|
||||
#define HWREGH(x) \
|
||||
(*((volatile unsigned short *)(x)))
|
||||
#define HWREGB(x) \
|
||||
(*((volatile unsigned char *)(x)))
|
||||
#define HWREGBITW(x, b) \
|
||||
HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
|
||||
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
|
||||
#define HWREGBITH(x, b) \
|
||||
HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
|
||||
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
|
||||
#define HWREGBITB(x, b) \
|
||||
HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
|
||||
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Helper Macros for determining silicon revisions, etc.
|
||||
//
|
||||
// These macros will be used by Driverlib at "run-time" to create necessary
|
||||
// conditional code blocks that will allow a single version of the Driverlib
|
||||
// "binary" code to support multiple(all) Stellaris silicon revisions.
|
||||
//
|
||||
// It is expected that these macros will be used inside of a standard 'C'
|
||||
// conditional block of code, e.g.
|
||||
//
|
||||
// if(CLASS_IS_SANDSTORM)
|
||||
// {
|
||||
// do some Sandstorm-class specific code here.
|
||||
// }
|
||||
//
|
||||
// By default, these macros will be defined as run-time checks of the
|
||||
// appropriate register(s) to allow creation of run-time conditional code
|
||||
// blocks for a common DriverLib across the entire Stellaris family.
|
||||
//
|
||||
// However, if code-space optimization is required, these macros can be "hard-
|
||||
// coded" for a specific version of Stellaris silicon. Many compilers will
|
||||
// then detect the "hard-coded" conditionals, and appropriately optimize the
|
||||
// code blocks, eliminating any "unreachable" code. This would result in
|
||||
// a smaller Driverlib, thus producing a smaller final application size, but
|
||||
// at the cost of limiting the Driverlib binary to a specific Stellaris
|
||||
// silicon revision.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef CLASS_IS_SANDSTORM
|
||||
#define CLASS_IS_SANDSTORM \
|
||||
(((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_M) == SYSCTL_DID0_VER_0) || \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
|
||||
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_SANDSTORM)))
|
||||
#endif
|
||||
|
||||
#ifndef CLASS_IS_FURY
|
||||
#define CLASS_IS_FURY \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
|
||||
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FURY))
|
||||
#endif
|
||||
|
||||
#ifndef CLASS_IS_DUSTDEVIL
|
||||
#define CLASS_IS_DUSTDEVIL \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
|
||||
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_DUSTDEVIL))
|
||||
#endif
|
||||
|
||||
#ifndef CLASS_IS_TEMPEST
|
||||
#define CLASS_IS_TEMPEST \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
|
||||
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TEMPEST))
|
||||
#endif
|
||||
|
||||
#ifndef CLASS_IS_FIRESTORM
|
||||
#define CLASS_IS_FIRESTORM \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
|
||||
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FIRESTORM))
|
||||
#endif
|
||||
|
||||
#ifndef CLASS_IS_BLIZZARD
|
||||
#define CLASS_IS_BLIZZARD \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
|
||||
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_BLIZZARD))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_A0
|
||||
#define REVISION_IS_A0 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_A1
|
||||
#define REVISION_IS_A1 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_A2
|
||||
#define REVISION_IS_A2 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_B0
|
||||
#define REVISION_IS_B0 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_0))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_B1
|
||||
#define REVISION_IS_B1 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_1))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_C0
|
||||
#define REVISION_IS_C0 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_0))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_C1
|
||||
#define REVISION_IS_C1 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_1))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_C2
|
||||
#define REVISION_IS_C2 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_2))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_C3
|
||||
#define REVISION_IS_C3 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_3))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_C5
|
||||
#define REVISION_IS_C5 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_5))
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Deprecated silicon class and revision detection macros.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
#define DEVICE_IS_SANDSTORM CLASS_IS_SANDSTORM
|
||||
#define DEVICE_IS_FURY CLASS_IS_FURY
|
||||
#define DEVICE_IS_REVA2 REVISION_IS_A2
|
||||
#define DEVICE_IS_REVC1 REVISION_IS_C1
|
||||
#define DEVICE_IS_REVC2 REVISION_IS_C2
|
||||
#endif
|
||||
|
||||
#endif // __HW_TYPES_H__
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_types.h - Common types and macros.
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_TYPES_H__
|
||||
#define __HW_TYPES_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Define a boolean type, and values for true and false.
|
||||
//
|
||||
//*****************************************************************************
|
||||
typedef unsigned char tBoolean;
|
||||
|
||||
#ifndef true
|
||||
#define true 1
|
||||
#endif
|
||||
|
||||
#ifndef false
|
||||
#define false 0
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Macros for hardware access, both direct and via the bit-band region.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HWREG(x) \
|
||||
(*((volatile unsigned long *)(x)))
|
||||
#define HWREGH(x) \
|
||||
(*((volatile unsigned short *)(x)))
|
||||
#define HWREGB(x) \
|
||||
(*((volatile unsigned char *)(x)))
|
||||
#define HWREGBITW(x, b) \
|
||||
HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
|
||||
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
|
||||
#define HWREGBITH(x, b) \
|
||||
HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
|
||||
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
|
||||
#define HWREGBITB(x, b) \
|
||||
HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
|
||||
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Helper Macros for determining silicon revisions, etc.
|
||||
//
|
||||
// These macros will be used by Driverlib at "run-time" to create necessary
|
||||
// conditional code blocks that will allow a single version of the Driverlib
|
||||
// "binary" code to support multiple(all) Stellaris silicon revisions.
|
||||
//
|
||||
// It is expected that these macros will be used inside of a standard 'C'
|
||||
// conditional block of code, e.g.
|
||||
//
|
||||
// if(CLASS_IS_SANDSTORM)
|
||||
// {
|
||||
// do some Sandstorm-class specific code here.
|
||||
// }
|
||||
//
|
||||
// By default, these macros will be defined as run-time checks of the
|
||||
// appropriate register(s) to allow creation of run-time conditional code
|
||||
// blocks for a common DriverLib across the entire Stellaris family.
|
||||
//
|
||||
// However, if code-space optimization is required, these macros can be "hard-
|
||||
// coded" for a specific version of Stellaris silicon. Many compilers will
|
||||
// then detect the "hard-coded" conditionals, and appropriately optimize the
|
||||
// code blocks, eliminating any "unreachable" code. This would result in
|
||||
// a smaller Driverlib, thus producing a smaller final application size, but
|
||||
// at the cost of limiting the Driverlib binary to a specific Stellaris
|
||||
// silicon revision.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef CLASS_IS_SANDSTORM
|
||||
#define CLASS_IS_SANDSTORM \
|
||||
(((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_M) == SYSCTL_DID0_VER_0) || \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
|
||||
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_SANDSTORM)))
|
||||
#endif
|
||||
|
||||
#ifndef CLASS_IS_FURY
|
||||
#define CLASS_IS_FURY \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
|
||||
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FURY))
|
||||
#endif
|
||||
|
||||
#ifndef CLASS_IS_DUSTDEVIL
|
||||
#define CLASS_IS_DUSTDEVIL \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
|
||||
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_DUSTDEVIL))
|
||||
#endif
|
||||
|
||||
#ifndef CLASS_IS_TEMPEST
|
||||
#define CLASS_IS_TEMPEST \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
|
||||
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TEMPEST))
|
||||
#endif
|
||||
|
||||
#ifndef CLASS_IS_FIRESTORM
|
||||
#define CLASS_IS_FIRESTORM \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
|
||||
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FIRESTORM))
|
||||
#endif
|
||||
|
||||
#ifndef CLASS_IS_BLIZZARD
|
||||
#define CLASS_IS_BLIZZARD \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
|
||||
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_BLIZZARD))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_A0
|
||||
#define REVISION_IS_A0 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_A1
|
||||
#define REVISION_IS_A1 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_A2
|
||||
#define REVISION_IS_A2 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_B0
|
||||
#define REVISION_IS_B0 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_0))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_B1
|
||||
#define REVISION_IS_B1 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_1))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_C0
|
||||
#define REVISION_IS_C0 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_0))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_C1
|
||||
#define REVISION_IS_C1 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_1))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_C2
|
||||
#define REVISION_IS_C2 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_2))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_C3
|
||||
#define REVISION_IS_C3 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_3))
|
||||
#endif
|
||||
|
||||
#ifndef REVISION_IS_C5
|
||||
#define REVISION_IS_C5 \
|
||||
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
|
||||
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_5))
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Deprecated silicon class and revision detection macros.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
#define DEVICE_IS_SANDSTORM CLASS_IS_SANDSTORM
|
||||
#define DEVICE_IS_FURY CLASS_IS_FURY
|
||||
#define DEVICE_IS_REVA2 REVISION_IS_A2
|
||||
#define DEVICE_IS_REVC1 REVISION_IS_C1
|
||||
#define DEVICE_IS_REVC2 REVISION_IS_C2
|
||||
#endif
|
||||
|
||||
#endif // __HW_TYPES_H__
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,191 +1,191 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_WATCHDOG_H__
|
||||
#define __HW_WATCHDOG_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the Watchdog Timer register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_O_LOAD 0x00000000 // Watchdog Load
|
||||
#define WDT_O_VALUE 0x00000004 // Watchdog Value
|
||||
#define WDT_O_CTL 0x00000008 // Watchdog Control
|
||||
#define WDT_O_ICR 0x0000000C // Watchdog Interrupt Clear
|
||||
#define WDT_O_RIS 0x00000010 // Watchdog Raw Interrupt Status
|
||||
#define WDT_O_MIS 0x00000014 // Watchdog Masked Interrupt Status
|
||||
#define WDT_O_TEST 0x00000418 // Watchdog Test
|
||||
#define WDT_O_LOCK 0x00000C00 // Watchdog Lock
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the WDT_O_LOAD register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value
|
||||
#define WDT_LOAD_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the WDT_O_VALUE register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value
|
||||
#define WDT_VALUE_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the WDT_O_CTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_CTL_WRC 0x80000000 // Write Complete
|
||||
#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type
|
||||
#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable
|
||||
#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the WDT_O_ICR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear
|
||||
#define WDT_ICR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the WDT_O_RIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the WDT_O_MIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the WDT_O_TEST register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the WDT_O_LOCK register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock
|
||||
#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked
|
||||
#define WDT_LOCK_LOCKED 0x00000001 // Locked
|
||||
#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and
|
||||
// WDT_MIS registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following definitions are deprecated.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the Watchdog Timer register
|
||||
// offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_O_PeriphID4 0x00000FD0
|
||||
#define WDT_O_PeriphID5 0x00000FD4
|
||||
#define WDT_O_PeriphID6 0x00000FD8
|
||||
#define WDT_O_PeriphID7 0x00000FDC
|
||||
#define WDT_O_PeriphID0 0x00000FE0
|
||||
#define WDT_O_PeriphID1 0x00000FE4
|
||||
#define WDT_O_PeriphID2 0x00000FE8
|
||||
#define WDT_O_PeriphID3 0x00000FEC
|
||||
#define WDT_O_PCellID0 0x00000FF0
|
||||
#define WDT_O_PCellID1 0x00000FF4
|
||||
#define WDT_O_PCellID2 0x00000FF8
|
||||
#define WDT_O_PCellID3 0x00000FFC
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the WDT_O_TEST
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the reset values for the WDT
|
||||
// registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_RV_VALUE 0xFFFFFFFF // Current value register
|
||||
#define WDT_RV_LOAD 0xFFFFFFFF // Load register
|
||||
#define WDT_RV_PCellID1 0x000000F0
|
||||
#define WDT_RV_PCellID3 0x000000B1
|
||||
#define WDT_RV_PeriphID1 0x00000018
|
||||
#define WDT_RV_PeriphID2 0x00000018
|
||||
#define WDT_RV_PCellID0 0x0000000D
|
||||
#define WDT_RV_PCellID2 0x00000005
|
||||
#define WDT_RV_PeriphID0 0x00000005
|
||||
#define WDT_RV_PeriphID3 0x00000001
|
||||
#define WDT_RV_PeriphID5 0x00000000
|
||||
#define WDT_RV_RIS 0x00000000 // Raw interrupt status register
|
||||
#define WDT_RV_CTL 0x00000000 // Control register
|
||||
#define WDT_RV_PeriphID4 0x00000000
|
||||
#define WDT_RV_PeriphID6 0x00000000
|
||||
#define WDT_RV_PeriphID7 0x00000000
|
||||
#define WDT_RV_LOCK 0x00000000 // Lock register
|
||||
#define WDT_RV_MIS 0x00000000 // Masked interrupt status register
|
||||
|
||||
#endif
|
||||
|
||||
#endif // __HW_WATCHDOG_H__
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Firmware Development Package.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HW_WATCHDOG_H__
|
||||
#define __HW_WATCHDOG_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the Watchdog Timer register offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_O_LOAD 0x00000000 // Watchdog Load
|
||||
#define WDT_O_VALUE 0x00000004 // Watchdog Value
|
||||
#define WDT_O_CTL 0x00000008 // Watchdog Control
|
||||
#define WDT_O_ICR 0x0000000C // Watchdog Interrupt Clear
|
||||
#define WDT_O_RIS 0x00000010 // Watchdog Raw Interrupt Status
|
||||
#define WDT_O_MIS 0x00000014 // Watchdog Masked Interrupt Status
|
||||
#define WDT_O_TEST 0x00000418 // Watchdog Test
|
||||
#define WDT_O_LOCK 0x00000C00 // Watchdog Lock
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the WDT_O_LOAD register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value
|
||||
#define WDT_LOAD_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the WDT_O_VALUE register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value
|
||||
#define WDT_VALUE_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the WDT_O_CTL register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_CTL_WRC 0x80000000 // Write Complete
|
||||
#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type
|
||||
#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable
|
||||
#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the WDT_O_ICR register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear
|
||||
#define WDT_ICR_S 0
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the WDT_O_RIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the WDT_O_MIS register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the WDT_O_TEST register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the WDT_O_LOCK register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock
|
||||
#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked
|
||||
#define WDT_LOCK_LOCKED 0x00000001 // Locked
|
||||
#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and
|
||||
// WDT_MIS registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following definitions are deprecated.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the Watchdog Timer register
|
||||
// offsets.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_O_PeriphID4 0x00000FD0
|
||||
#define WDT_O_PeriphID5 0x00000FD4
|
||||
#define WDT_O_PeriphID6 0x00000FD8
|
||||
#define WDT_O_PeriphID7 0x00000FDC
|
||||
#define WDT_O_PeriphID0 0x00000FE0
|
||||
#define WDT_O_PeriphID1 0x00000FE4
|
||||
#define WDT_O_PeriphID2 0x00000FE8
|
||||
#define WDT_O_PeriphID3 0x00000FEC
|
||||
#define WDT_O_PCellID0 0x00000FF0
|
||||
#define WDT_O_PCellID1 0x00000FF4
|
||||
#define WDT_O_PCellID2 0x00000FF8
|
||||
#define WDT_O_PCellID3 0x00000FFC
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the bit fields in the WDT_O_TEST
|
||||
// register.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following are deprecated defines for the reset values for the WDT
|
||||
// registers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WDT_RV_VALUE 0xFFFFFFFF // Current value register
|
||||
#define WDT_RV_LOAD 0xFFFFFFFF // Load register
|
||||
#define WDT_RV_PCellID1 0x000000F0
|
||||
#define WDT_RV_PCellID3 0x000000B1
|
||||
#define WDT_RV_PeriphID1 0x00000018
|
||||
#define WDT_RV_PeriphID2 0x00000018
|
||||
#define WDT_RV_PCellID0 0x0000000D
|
||||
#define WDT_RV_PCellID2 0x00000005
|
||||
#define WDT_RV_PeriphID0 0x00000005
|
||||
#define WDT_RV_PeriphID3 0x00000001
|
||||
#define WDT_RV_PeriphID5 0x00000000
|
||||
#define WDT_RV_RIS 0x00000000 // Raw interrupt status register
|
||||
#define WDT_RV_CTL 0x00000000 // Control register
|
||||
#define WDT_RV_PeriphID4 0x00000000
|
||||
#define WDT_RV_PeriphID6 0x00000000
|
||||
#define WDT_RV_PeriphID7 0x00000000
|
||||
#define WDT_RV_LOCK 0x00000000 // Lock register
|
||||
#define WDT_RV_MIS 0x00000000 // Masked interrupt status register
|
||||
|
||||
#endif
|
||||
|
||||
#endif // __HW_WATCHDOG_H__
|
||||
|
||||
@ -1,311 +1,311 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// adc.h - ADC headers for using the ADC driver functions.
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __ADC_H__
|
||||
#define __ADC_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ADCSequenceConfigure as the ulTrigger
|
||||
// parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event
|
||||
#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event
|
||||
#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event
|
||||
#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event
|
||||
#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event
|
||||
#define ADC_TRIGGER_TIMER 0x00000005 // Timer event
|
||||
#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event
|
||||
#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event
|
||||
#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event
|
||||
#define ADC_TRIGGER_PWM3 0x00000009 // PWM3 event
|
||||
#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ADCSequenceStepConfigure as the ulConfig
|
||||
// parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_CTL_TS 0x00000080 // Temperature sensor select
|
||||
#define ADC_CTL_IE 0x00000040 // Interrupt enable
|
||||
#define ADC_CTL_END 0x00000020 // Sequence end select
|
||||
#define ADC_CTL_D 0x00000010 // Differential select
|
||||
#define ADC_CTL_CH0 0x00000000 // Input channel 0
|
||||
#define ADC_CTL_CH1 0x00000001 // Input channel 1
|
||||
#define ADC_CTL_CH2 0x00000002 // Input channel 2
|
||||
#define ADC_CTL_CH3 0x00000003 // Input channel 3
|
||||
#define ADC_CTL_CH4 0x00000004 // Input channel 4
|
||||
#define ADC_CTL_CH5 0x00000005 // Input channel 5
|
||||
#define ADC_CTL_CH6 0x00000006 // Input channel 6
|
||||
#define ADC_CTL_CH7 0x00000007 // Input channel 7
|
||||
#define ADC_CTL_CH8 0x00000008 // Input channel 8
|
||||
#define ADC_CTL_CH9 0x00000009 // Input channel 9
|
||||
#define ADC_CTL_CH10 0x0000000A // Input channel 10
|
||||
#define ADC_CTL_CH11 0x0000000B // Input channel 11
|
||||
#define ADC_CTL_CH12 0x0000000C // Input channel 12
|
||||
#define ADC_CTL_CH13 0x0000000D // Input channel 13
|
||||
#define ADC_CTL_CH14 0x0000000E // Input channel 14
|
||||
#define ADC_CTL_CH15 0x0000000F // Input channel 15
|
||||
#define ADC_CTL_CH16 0x00000100 // Input channel 16
|
||||
#define ADC_CTL_CH17 0x00000101 // Input channel 17
|
||||
#define ADC_CTL_CH18 0x00000102 // Input channel 18
|
||||
#define ADC_CTL_CH19 0x00000103 // Input channel 19
|
||||
#define ADC_CTL_CH20 0x00000104 // Input channel 20
|
||||
#define ADC_CTL_CH21 0x00000105 // Input channel 21
|
||||
#define ADC_CTL_CH22 0x00000106 // Input channel 22
|
||||
#define ADC_CTL_CH23 0x00000107 // Input channel 23
|
||||
#define ADC_CTL_CMP0 0x00080000 // Select Comparator 0
|
||||
#define ADC_CTL_CMP1 0x00090000 // Select Comparator 1
|
||||
#define ADC_CTL_CMP2 0x000A0000 // Select Comparator 2
|
||||
#define ADC_CTL_CMP3 0x000B0000 // Select Comparator 3
|
||||
#define ADC_CTL_CMP4 0x000C0000 // Select Comparator 4
|
||||
#define ADC_CTL_CMP5 0x000D0000 // Select Comparator 5
|
||||
#define ADC_CTL_CMP6 0x000E0000 // Select Comparator 6
|
||||
#define ADC_CTL_CMP7 0x000F0000 // Select Comparator 7
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ADCComparatorConfigure as part of the
|
||||
// ulConfig parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_COMP_TRIG_NONE 0x00000000 // Trigger Disabled
|
||||
#define ADC_COMP_TRIG_LOW_ALWAYS \
|
||||
0x00001000 // Trigger Low Always
|
||||
#define ADC_COMP_TRIG_LOW_ONCE 0x00001100 // Trigger Low Once
|
||||
#define ADC_COMP_TRIG_LOW_HALWAYS \
|
||||
0x00001200 // Trigger Low Always (Hysteresis)
|
||||
#define ADC_COMP_TRIG_LOW_HONCE 0x00001300 // Trigger Low Once (Hysteresis)
|
||||
#define ADC_COMP_TRIG_MID_ALWAYS \
|
||||
0x00001400 // Trigger Mid Always
|
||||
#define ADC_COMP_TRIG_MID_ONCE 0x00001500 // Trigger Mid Once
|
||||
#define ADC_COMP_TRIG_HIGH_ALWAYS \
|
||||
0x00001C00 // Trigger High Always
|
||||
#define ADC_COMP_TRIG_HIGH_ONCE 0x00001D00 // Trigger High Once
|
||||
#define ADC_COMP_TRIG_HIGH_HALWAYS \
|
||||
0x00001E00 // Trigger High Always (Hysteresis)
|
||||
#define ADC_COMP_TRIG_HIGH_HONCE \
|
||||
0x00001F00 // Trigger High Once (Hysteresis)
|
||||
|
||||
#define ADC_COMP_INT_NONE 0x00000000 // Interrupt Disabled
|
||||
#define ADC_COMP_INT_LOW_ALWAYS \
|
||||
0x00000010 // Interrupt Low Always
|
||||
#define ADC_COMP_INT_LOW_ONCE 0x00000011 // Interrupt Low Once
|
||||
#define ADC_COMP_INT_LOW_HALWAYS \
|
||||
0x00000012 // Interrupt Low Always
|
||||
// (Hysteresis)
|
||||
#define ADC_COMP_INT_LOW_HONCE 0x00000013 // Interrupt Low Once (Hysteresis)
|
||||
#define ADC_COMP_INT_MID_ALWAYS \
|
||||
0x00000014 // Interrupt Mid Always
|
||||
#define ADC_COMP_INT_MID_ONCE 0x00000015 // Interrupt Mid Once
|
||||
#define ADC_COMP_INT_HIGH_ALWAYS \
|
||||
0x0000001C // Interrupt High Always
|
||||
#define ADC_COMP_INT_HIGH_ONCE 0x0000001D // Interrupt High Once
|
||||
#define ADC_COMP_INT_HIGH_HALWAYS \
|
||||
0x0000001E // Interrupt High Always
|
||||
// (Hysteresis)
|
||||
#define ADC_COMP_INT_HIGH_HONCE \
|
||||
0x0000001F // Interrupt High Once (Hysteresis)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be used to modify the sequence number passed to
|
||||
// ADCProcessorTrigger in order to get cross-module synchronous processor
|
||||
// triggers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_TRIGGER_WAIT 0x08000000 // Wait for the synchronous trigger
|
||||
#define ADC_TRIGGER_SIGNAL 0x80000000 // Signal the synchronous trigger
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ADCPhaseDelaySet as the ulPhase parameter and
|
||||
// returned from ADCPhaseDelayGet.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_PHASE_0 0x00000000 // 0 degrees
|
||||
#define ADC_PHASE_22_5 0x00000001 // 22.5 degrees
|
||||
#define ADC_PHASE_45 0x00000002 // 45 degrees
|
||||
#define ADC_PHASE_67_5 0x00000003 // 67.5 degrees
|
||||
#define ADC_PHASE_90 0x00000004 // 90 degrees
|
||||
#define ADC_PHASE_112_5 0x00000005 // 112.5 degrees
|
||||
#define ADC_PHASE_135 0x00000006 // 135 degrees
|
||||
#define ADC_PHASE_157_5 0x00000007 // 157.5 degrees
|
||||
#define ADC_PHASE_180 0x00000008 // 180 degrees
|
||||
#define ADC_PHASE_202_5 0x00000009 // 202.5 degrees
|
||||
#define ADC_PHASE_225 0x0000000A // 225 degrees
|
||||
#define ADC_PHASE_247_5 0x0000000B // 247.5 degrees
|
||||
#define ADC_PHASE_270 0x0000000C // 270 degrees
|
||||
#define ADC_PHASE_292_5 0x0000000D // 292.5 degrees
|
||||
#define ADC_PHASE_315 0x0000000E // 315 degrees
|
||||
#define ADC_PHASE_337_5 0x0000000F // 337.5 degrees
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ADCReferenceSet as the ulRef parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_REF_INT 0x00000000 // Internal reference
|
||||
#define ADC_REF_EXT_3V 0x00000001 // External 3V reference
|
||||
#define ADC_REF_EXT_1V 0x00000003 // External 1V reference
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ADCResolutionSet as the ulResolution parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_RES_10BIT_S 0x00000000 // 10-bit resolution
|
||||
#define ADC_RES_12BIT_S 0x00000010 // 12-bit resolution
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ADCIntDisableEx(), ADCIntEnableEx(),
|
||||
// ADCIntClearEx() and ADCIntStatusEx().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_INT_SS0 0x00000001
|
||||
#define ADC_INT_SS1 0x00000002
|
||||
#define ADC_INT_SS2 0x00000004
|
||||
#define ADC_INT_SS3 0x00000008
|
||||
#define ADC_INT_DMA_SS0 0x00000100
|
||||
#define ADC_INT_DMA_SS1 0x00000200
|
||||
#define ADC_INT_DMA_SS2 0x00000400
|
||||
#define ADC_INT_DMA_SS3 0x00000800
|
||||
#define ADC_INT_DCON_SS0 0x00010000
|
||||
#define ADC_INT_DCON_SS1 0x00020000
|
||||
#define ADC_INT_DCON_SS2 0x00040000
|
||||
#define ADC_INT_DCON_SS3 0x00080000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
|
||||
void (*pfnHandler)(void));
|
||||
extern void ADCIntUnregister(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum);
|
||||
extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum);
|
||||
extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum);
|
||||
extern unsigned long ADCIntStatus(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum,
|
||||
tBoolean bMasked);
|
||||
extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum);
|
||||
extern void ADCSequenceEnable(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum);
|
||||
extern void ADCSequenceDisable(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum);
|
||||
extern void ADCSequenceConfigure(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum,
|
||||
unsigned long ulTrigger,
|
||||
unsigned long ulPriority);
|
||||
extern void ADCSequenceStepConfigure(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum,
|
||||
unsigned long ulStep,
|
||||
unsigned long ulConfig);
|
||||
extern long ADCSequenceOverflow(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum);
|
||||
extern void ADCSequenceOverflowClear(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum);
|
||||
extern long ADCSequenceUnderflow(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum);
|
||||
extern void ADCSequenceUnderflowClear(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum);
|
||||
extern long ADCSequenceDataGet(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum,
|
||||
unsigned long *pulBuffer);
|
||||
extern void ADCProcessorTrigger(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum);
|
||||
extern void ADCSoftwareOversampleConfigure(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum,
|
||||
unsigned long ulFactor);
|
||||
extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum,
|
||||
unsigned long ulStep,
|
||||
unsigned long ulConfig);
|
||||
extern void ADCSoftwareOversampleDataGet(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum,
|
||||
unsigned long *pulBuffer,
|
||||
unsigned long ulCount);
|
||||
extern void ADCHardwareOversampleConfigure(unsigned long ulBase,
|
||||
unsigned long ulFactor);
|
||||
extern void ADCComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
|
||||
unsigned long ulConfig);
|
||||
extern void ADCComparatorRegionSet(unsigned long ulBase, unsigned long ulComp,
|
||||
unsigned long ulLowRef,
|
||||
unsigned long ulHighRef);
|
||||
extern void ADCComparatorReset(unsigned long ulBase, unsigned long ulComp,
|
||||
tBoolean bTrigger, tBoolean bInterrupt);
|
||||
extern void ADCComparatorIntDisable(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum);
|
||||
extern void ADCComparatorIntEnable(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum);
|
||||
extern unsigned long ADCComparatorIntStatus(unsigned long ulBase);
|
||||
extern void ADCComparatorIntClear(unsigned long ulBase,
|
||||
unsigned long ulStatus);
|
||||
extern void ADCReferenceSet(unsigned long ulBase, unsigned long ulRef);
|
||||
extern unsigned long ADCReferenceGet(unsigned long ulBase);
|
||||
extern void ADCResolutionSet(unsigned long ulBase, unsigned long ulResolution);
|
||||
extern unsigned long ADCResolutionGet(unsigned long ulBase);
|
||||
extern void ADCPhaseDelaySet(unsigned long ulBase, unsigned long ulPhase);
|
||||
extern unsigned long ADCPhaseDelayGet(unsigned long ulBase);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __ADC_H__
|
||||
//*****************************************************************************
|
||||
//
|
||||
// adc.h - ADC headers for using the ADC driver functions.
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __ADC_H__
|
||||
#define __ADC_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ADCSequenceConfigure as the ulTrigger
|
||||
// parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event
|
||||
#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event
|
||||
#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event
|
||||
#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event
|
||||
#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event
|
||||
#define ADC_TRIGGER_TIMER 0x00000005 // Timer event
|
||||
#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event
|
||||
#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event
|
||||
#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event
|
||||
#define ADC_TRIGGER_PWM3 0x00000009 // PWM3 event
|
||||
#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ADCSequenceStepConfigure as the ulConfig
|
||||
// parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_CTL_TS 0x00000080 // Temperature sensor select
|
||||
#define ADC_CTL_IE 0x00000040 // Interrupt enable
|
||||
#define ADC_CTL_END 0x00000020 // Sequence end select
|
||||
#define ADC_CTL_D 0x00000010 // Differential select
|
||||
#define ADC_CTL_CH0 0x00000000 // Input channel 0
|
||||
#define ADC_CTL_CH1 0x00000001 // Input channel 1
|
||||
#define ADC_CTL_CH2 0x00000002 // Input channel 2
|
||||
#define ADC_CTL_CH3 0x00000003 // Input channel 3
|
||||
#define ADC_CTL_CH4 0x00000004 // Input channel 4
|
||||
#define ADC_CTL_CH5 0x00000005 // Input channel 5
|
||||
#define ADC_CTL_CH6 0x00000006 // Input channel 6
|
||||
#define ADC_CTL_CH7 0x00000007 // Input channel 7
|
||||
#define ADC_CTL_CH8 0x00000008 // Input channel 8
|
||||
#define ADC_CTL_CH9 0x00000009 // Input channel 9
|
||||
#define ADC_CTL_CH10 0x0000000A // Input channel 10
|
||||
#define ADC_CTL_CH11 0x0000000B // Input channel 11
|
||||
#define ADC_CTL_CH12 0x0000000C // Input channel 12
|
||||
#define ADC_CTL_CH13 0x0000000D // Input channel 13
|
||||
#define ADC_CTL_CH14 0x0000000E // Input channel 14
|
||||
#define ADC_CTL_CH15 0x0000000F // Input channel 15
|
||||
#define ADC_CTL_CH16 0x00000100 // Input channel 16
|
||||
#define ADC_CTL_CH17 0x00000101 // Input channel 17
|
||||
#define ADC_CTL_CH18 0x00000102 // Input channel 18
|
||||
#define ADC_CTL_CH19 0x00000103 // Input channel 19
|
||||
#define ADC_CTL_CH20 0x00000104 // Input channel 20
|
||||
#define ADC_CTL_CH21 0x00000105 // Input channel 21
|
||||
#define ADC_CTL_CH22 0x00000106 // Input channel 22
|
||||
#define ADC_CTL_CH23 0x00000107 // Input channel 23
|
||||
#define ADC_CTL_CMP0 0x00080000 // Select Comparator 0
|
||||
#define ADC_CTL_CMP1 0x00090000 // Select Comparator 1
|
||||
#define ADC_CTL_CMP2 0x000A0000 // Select Comparator 2
|
||||
#define ADC_CTL_CMP3 0x000B0000 // Select Comparator 3
|
||||
#define ADC_CTL_CMP4 0x000C0000 // Select Comparator 4
|
||||
#define ADC_CTL_CMP5 0x000D0000 // Select Comparator 5
|
||||
#define ADC_CTL_CMP6 0x000E0000 // Select Comparator 6
|
||||
#define ADC_CTL_CMP7 0x000F0000 // Select Comparator 7
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ADCComparatorConfigure as part of the
|
||||
// ulConfig parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_COMP_TRIG_NONE 0x00000000 // Trigger Disabled
|
||||
#define ADC_COMP_TRIG_LOW_ALWAYS \
|
||||
0x00001000 // Trigger Low Always
|
||||
#define ADC_COMP_TRIG_LOW_ONCE 0x00001100 // Trigger Low Once
|
||||
#define ADC_COMP_TRIG_LOW_HALWAYS \
|
||||
0x00001200 // Trigger Low Always (Hysteresis)
|
||||
#define ADC_COMP_TRIG_LOW_HONCE 0x00001300 // Trigger Low Once (Hysteresis)
|
||||
#define ADC_COMP_TRIG_MID_ALWAYS \
|
||||
0x00001400 // Trigger Mid Always
|
||||
#define ADC_COMP_TRIG_MID_ONCE 0x00001500 // Trigger Mid Once
|
||||
#define ADC_COMP_TRIG_HIGH_ALWAYS \
|
||||
0x00001C00 // Trigger High Always
|
||||
#define ADC_COMP_TRIG_HIGH_ONCE 0x00001D00 // Trigger High Once
|
||||
#define ADC_COMP_TRIG_HIGH_HALWAYS \
|
||||
0x00001E00 // Trigger High Always (Hysteresis)
|
||||
#define ADC_COMP_TRIG_HIGH_HONCE \
|
||||
0x00001F00 // Trigger High Once (Hysteresis)
|
||||
|
||||
#define ADC_COMP_INT_NONE 0x00000000 // Interrupt Disabled
|
||||
#define ADC_COMP_INT_LOW_ALWAYS \
|
||||
0x00000010 // Interrupt Low Always
|
||||
#define ADC_COMP_INT_LOW_ONCE 0x00000011 // Interrupt Low Once
|
||||
#define ADC_COMP_INT_LOW_HALWAYS \
|
||||
0x00000012 // Interrupt Low Always
|
||||
// (Hysteresis)
|
||||
#define ADC_COMP_INT_LOW_HONCE 0x00000013 // Interrupt Low Once (Hysteresis)
|
||||
#define ADC_COMP_INT_MID_ALWAYS \
|
||||
0x00000014 // Interrupt Mid Always
|
||||
#define ADC_COMP_INT_MID_ONCE 0x00000015 // Interrupt Mid Once
|
||||
#define ADC_COMP_INT_HIGH_ALWAYS \
|
||||
0x0000001C // Interrupt High Always
|
||||
#define ADC_COMP_INT_HIGH_ONCE 0x0000001D // Interrupt High Once
|
||||
#define ADC_COMP_INT_HIGH_HALWAYS \
|
||||
0x0000001E // Interrupt High Always
|
||||
// (Hysteresis)
|
||||
#define ADC_COMP_INT_HIGH_HONCE \
|
||||
0x0000001F // Interrupt High Once (Hysteresis)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be used to modify the sequence number passed to
|
||||
// ADCProcessorTrigger in order to get cross-module synchronous processor
|
||||
// triggers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_TRIGGER_WAIT 0x08000000 // Wait for the synchronous trigger
|
||||
#define ADC_TRIGGER_SIGNAL 0x80000000 // Signal the synchronous trigger
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ADCPhaseDelaySet as the ulPhase parameter and
|
||||
// returned from ADCPhaseDelayGet.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_PHASE_0 0x00000000 // 0 degrees
|
||||
#define ADC_PHASE_22_5 0x00000001 // 22.5 degrees
|
||||
#define ADC_PHASE_45 0x00000002 // 45 degrees
|
||||
#define ADC_PHASE_67_5 0x00000003 // 67.5 degrees
|
||||
#define ADC_PHASE_90 0x00000004 // 90 degrees
|
||||
#define ADC_PHASE_112_5 0x00000005 // 112.5 degrees
|
||||
#define ADC_PHASE_135 0x00000006 // 135 degrees
|
||||
#define ADC_PHASE_157_5 0x00000007 // 157.5 degrees
|
||||
#define ADC_PHASE_180 0x00000008 // 180 degrees
|
||||
#define ADC_PHASE_202_5 0x00000009 // 202.5 degrees
|
||||
#define ADC_PHASE_225 0x0000000A // 225 degrees
|
||||
#define ADC_PHASE_247_5 0x0000000B // 247.5 degrees
|
||||
#define ADC_PHASE_270 0x0000000C // 270 degrees
|
||||
#define ADC_PHASE_292_5 0x0000000D // 292.5 degrees
|
||||
#define ADC_PHASE_315 0x0000000E // 315 degrees
|
||||
#define ADC_PHASE_337_5 0x0000000F // 337.5 degrees
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ADCReferenceSet as the ulRef parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_REF_INT 0x00000000 // Internal reference
|
||||
#define ADC_REF_EXT_3V 0x00000001 // External 3V reference
|
||||
#define ADC_REF_EXT_1V 0x00000003 // External 1V reference
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ADCResolutionSet as the ulResolution parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_RES_10BIT_S 0x00000000 // 10-bit resolution
|
||||
#define ADC_RES_12BIT_S 0x00000010 // 12-bit resolution
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ADCIntDisableEx(), ADCIntEnableEx(),
|
||||
// ADCIntClearEx() and ADCIntStatusEx().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define ADC_INT_SS0 0x00000001
|
||||
#define ADC_INT_SS1 0x00000002
|
||||
#define ADC_INT_SS2 0x00000004
|
||||
#define ADC_INT_SS3 0x00000008
|
||||
#define ADC_INT_DMA_SS0 0x00000100
|
||||
#define ADC_INT_DMA_SS1 0x00000200
|
||||
#define ADC_INT_DMA_SS2 0x00000400
|
||||
#define ADC_INT_DMA_SS3 0x00000800
|
||||
#define ADC_INT_DCON_SS0 0x00010000
|
||||
#define ADC_INT_DCON_SS1 0x00020000
|
||||
#define ADC_INT_DCON_SS2 0x00040000
|
||||
#define ADC_INT_DCON_SS3 0x00080000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
|
||||
void (*pfnHandler)(void));
|
||||
extern void ADCIntUnregister(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum);
|
||||
extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum);
|
||||
extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum);
|
||||
extern unsigned long ADCIntStatus(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum,
|
||||
tBoolean bMasked);
|
||||
extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum);
|
||||
extern void ADCSequenceEnable(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum);
|
||||
extern void ADCSequenceDisable(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum);
|
||||
extern void ADCSequenceConfigure(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum,
|
||||
unsigned long ulTrigger,
|
||||
unsigned long ulPriority);
|
||||
extern void ADCSequenceStepConfigure(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum,
|
||||
unsigned long ulStep,
|
||||
unsigned long ulConfig);
|
||||
extern long ADCSequenceOverflow(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum);
|
||||
extern void ADCSequenceOverflowClear(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum);
|
||||
extern long ADCSequenceUnderflow(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum);
|
||||
extern void ADCSequenceUnderflowClear(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum);
|
||||
extern long ADCSequenceDataGet(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum,
|
||||
unsigned long *pulBuffer);
|
||||
extern void ADCProcessorTrigger(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum);
|
||||
extern void ADCSoftwareOversampleConfigure(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum,
|
||||
unsigned long ulFactor);
|
||||
extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum,
|
||||
unsigned long ulStep,
|
||||
unsigned long ulConfig);
|
||||
extern void ADCSoftwareOversampleDataGet(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum,
|
||||
unsigned long *pulBuffer,
|
||||
unsigned long ulCount);
|
||||
extern void ADCHardwareOversampleConfigure(unsigned long ulBase,
|
||||
unsigned long ulFactor);
|
||||
extern void ADCComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
|
||||
unsigned long ulConfig);
|
||||
extern void ADCComparatorRegionSet(unsigned long ulBase, unsigned long ulComp,
|
||||
unsigned long ulLowRef,
|
||||
unsigned long ulHighRef);
|
||||
extern void ADCComparatorReset(unsigned long ulBase, unsigned long ulComp,
|
||||
tBoolean bTrigger, tBoolean bInterrupt);
|
||||
extern void ADCComparatorIntDisable(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum);
|
||||
extern void ADCComparatorIntEnable(unsigned long ulBase,
|
||||
unsigned long ulSequenceNum);
|
||||
extern unsigned long ADCComparatorIntStatus(unsigned long ulBase);
|
||||
extern void ADCComparatorIntClear(unsigned long ulBase,
|
||||
unsigned long ulStatus);
|
||||
extern void ADCReferenceSet(unsigned long ulBase, unsigned long ulRef);
|
||||
extern unsigned long ADCReferenceGet(unsigned long ulBase);
|
||||
extern void ADCResolutionSet(unsigned long ulBase, unsigned long ulResolution);
|
||||
extern unsigned long ADCResolutionGet(unsigned long ulBase);
|
||||
extern void ADCPhaseDelaySet(unsigned long ulBase, unsigned long ulPhase);
|
||||
extern unsigned long ADCPhaseDelayGet(unsigned long ulBase);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __ADC_H__
|
||||
|
||||
@ -1,145 +1,145 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// comp.h - Prototypes for the analog comparator driver.
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __COMP_H__
|
||||
#define __COMP_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ComparatorConfigure() as the ulConfig
|
||||
// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of
|
||||
// the values may be selected and combined together with values from the other
|
||||
// groups via a logical OR.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_TRIG_NONE 0x00000000 // No ADC trigger
|
||||
#define COMP_TRIG_HIGH 0x00000880 // Trigger when high
|
||||
#define COMP_TRIG_LOW 0x00000800 // Trigger when low
|
||||
#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge
|
||||
#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge
|
||||
#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges
|
||||
#define COMP_INT_HIGH 0x00000010 // Interrupt when high
|
||||
#define COMP_INT_LOW 0x00000000 // Interrupt when low
|
||||
#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge
|
||||
#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge
|
||||
#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges
|
||||
#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
|
||||
#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin
|
||||
#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference
|
||||
#ifndef DEPRECATED
|
||||
#define COMP_OUTPUT_NONE 0x00000000 // No comparator output
|
||||
#endif
|
||||
#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal
|
||||
#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ComparatorSetRef() as the ulRef parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_REF_OFF 0x00000000 // Turn off the internal reference
|
||||
#define COMP_REF_0V 0x00000300 // Internal reference of 0V
|
||||
#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V
|
||||
#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V
|
||||
#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V
|
||||
#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V
|
||||
#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V
|
||||
#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V
|
||||
#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V
|
||||
#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V
|
||||
#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V
|
||||
#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V
|
||||
#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V
|
||||
#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V
|
||||
#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V
|
||||
#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V
|
||||
#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V
|
||||
#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V
|
||||
#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V
|
||||
#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V
|
||||
#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V
|
||||
#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V
|
||||
#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V
|
||||
#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V
|
||||
#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V
|
||||
#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V
|
||||
#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V
|
||||
#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V
|
||||
#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
|
||||
unsigned long ulConfig);
|
||||
extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef);
|
||||
extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp);
|
||||
extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,
|
||||
void (*pfnHandler)(void));
|
||||
extern void ComparatorIntUnregister(unsigned long ulBase,
|
||||
unsigned long ulComp);
|
||||
extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp);
|
||||
extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp);
|
||||
extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,
|
||||
tBoolean bMasked);
|
||||
extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __COMP_H__
|
||||
//*****************************************************************************
|
||||
//
|
||||
// comp.h - Prototypes for the analog comparator driver.
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __COMP_H__
|
||||
#define __COMP_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ComparatorConfigure() as the ulConfig
|
||||
// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of
|
||||
// the values may be selected and combined together with values from the other
|
||||
// groups via a logical OR.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_TRIG_NONE 0x00000000 // No ADC trigger
|
||||
#define COMP_TRIG_HIGH 0x00000880 // Trigger when high
|
||||
#define COMP_TRIG_LOW 0x00000800 // Trigger when low
|
||||
#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge
|
||||
#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge
|
||||
#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges
|
||||
#define COMP_INT_HIGH 0x00000010 // Interrupt when high
|
||||
#define COMP_INT_LOW 0x00000000 // Interrupt when low
|
||||
#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge
|
||||
#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge
|
||||
#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges
|
||||
#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
|
||||
#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin
|
||||
#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference
|
||||
#ifndef DEPRECATED
|
||||
#define COMP_OUTPUT_NONE 0x00000000 // No comparator output
|
||||
#endif
|
||||
#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal
|
||||
#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to ComparatorSetRef() as the ulRef parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define COMP_REF_OFF 0x00000000 // Turn off the internal reference
|
||||
#define COMP_REF_0V 0x00000300 // Internal reference of 0V
|
||||
#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V
|
||||
#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V
|
||||
#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V
|
||||
#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V
|
||||
#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V
|
||||
#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V
|
||||
#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V
|
||||
#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V
|
||||
#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V
|
||||
#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V
|
||||
#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V
|
||||
#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V
|
||||
#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V
|
||||
#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V
|
||||
#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V
|
||||
#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V
|
||||
#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V
|
||||
#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V
|
||||
#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V
|
||||
#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V
|
||||
#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V
|
||||
#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V
|
||||
#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V
|
||||
#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V
|
||||
#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V
|
||||
#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V
|
||||
#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
|
||||
unsigned long ulConfig);
|
||||
extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef);
|
||||
extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp);
|
||||
extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,
|
||||
void (*pfnHandler)(void));
|
||||
extern void ComparatorIntUnregister(unsigned long ulBase,
|
||||
unsigned long ulComp);
|
||||
extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp);
|
||||
extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp);
|
||||
extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,
|
||||
tBoolean bMasked);
|
||||
extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __COMP_H__
|
||||
|
||||
@ -1,75 +1,75 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// cpu.h - Prototypes for the CPU instruction wrapper functions.
|
||||
//
|
||||
// Copyright (c) 2006-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __CPU_H__
|
||||
#define __CPU_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern unsigned long CPUcpsid(void);
|
||||
extern unsigned long CPUcpsie(void);
|
||||
extern unsigned long CPUprimask(void);
|
||||
extern void CPUwfi(void);
|
||||
extern unsigned long CPUbasepriGet(void);
|
||||
extern void CPUbasepriSet(unsigned long ulNewBasepri);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __CPU_H__
|
||||
//*****************************************************************************
|
||||
//
|
||||
// cpu.h - Prototypes for the CPU instruction wrapper functions.
|
||||
//
|
||||
// Copyright (c) 2006-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __CPU_H__
|
||||
#define __CPU_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern unsigned long CPUcpsid(void);
|
||||
extern unsigned long CPUcpsie(void);
|
||||
extern unsigned long CPUprimask(void);
|
||||
extern void CPUwfi(void);
|
||||
extern unsigned long CPUbasepriGet(void);
|
||||
extern void CPUbasepriSet(unsigned long ulNewBasepri);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __CPU_H__
|
||||
|
||||
@ -1,68 +1,68 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// debug.h - Macros for assisting debug of the driver library.
|
||||
//
|
||||
// Copyright (c) 2006-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DEBUG_H__
|
||||
#define __DEBUG_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototype for the function that is called when an invalid argument is passed
|
||||
// to an API. This is only used when doing a DEBUG build.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void __error__(char *pcFilename, unsigned long ulLine);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The ASSERT macro, which does the actual assertion checking. Typically, this
|
||||
// will be for procedure arguments.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef DEBUG
|
||||
#define ASSERT(expr) { \
|
||||
if(!(expr)) \
|
||||
{ \
|
||||
__error__(__FILE__, __LINE__); \
|
||||
} \
|
||||
}
|
||||
#else
|
||||
#define ASSERT(expr)
|
||||
#endif
|
||||
|
||||
#endif // __DEBUG_H__
|
||||
//*****************************************************************************
|
||||
//
|
||||
// debug.h - Macros for assisting debug of the driver library.
|
||||
//
|
||||
// Copyright (c) 2006-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __DEBUG_H__
|
||||
#define __DEBUG_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototype for the function that is called when an invalid argument is passed
|
||||
// to an API. This is only used when doing a DEBUG build.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void __error__(char *pcFilename, unsigned long ulLine);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The ASSERT macro, which does the actual assertion checking. Typically, this
|
||||
// will be for procedure arguments.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef DEBUG
|
||||
#define ASSERT(expr) { \
|
||||
if(!(expr)) \
|
||||
{ \
|
||||
__error__(__FILE__, __LINE__); \
|
||||
} \
|
||||
}
|
||||
#else
|
||||
#define ASSERT(expr)
|
||||
#endif
|
||||
|
||||
#endif // __DEBUG_H__
|
||||
|
||||
@ -1,112 +1,112 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// fpu.h - Prototypes for the floatint point manipulation routines.
|
||||
//
|
||||
// Copyright (c) 2011-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __FPU_H__
|
||||
#define __FPU_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to FPUHalfPrecisionSet as the ulMode parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FPU_HALF_IEEE 0x00000000
|
||||
#define FPU_HALF_ALTERNATE 0x04000000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to FPUNaNModeSet as the ulMode parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FPU_NAN_PROPAGATE 0x00000000
|
||||
#define FPU_NAN_DEFAULT 0x02000000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to FPUFlushToZeroModeSet as the ulMode parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FPU_FLUSH_TO_ZERO_DIS 0x00000000
|
||||
#define FPU_FLUSH_TO_ZERO_EN 0x01000000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to FPURoundingModeSet as the ulMode parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FPU_ROUND_NEAREST 0x00000000
|
||||
#define FPU_ROUND_POS_INF 0x00400000
|
||||
#define FPU_ROUND_NEG_INF 0x00800000
|
||||
#define FPU_ROUND_ZERO 0x00c00000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void FPUEnable(void);
|
||||
extern void FPUDisable(void);
|
||||
extern void FPUStackingEnable(void);
|
||||
extern void FPULazyStackingEnable(void);
|
||||
extern void FPUStackingDisable(void);
|
||||
extern void FPUHalfPrecisionModeSet(unsigned long ulMode);
|
||||
extern void FPUNaNModeSet(unsigned long ulMode);
|
||||
extern void FPUFlushToZeroModeSet(unsigned long ulMode);
|
||||
extern void FPURoundingModeSet(unsigned long ulMode);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __FPU_H__
|
||||
//*****************************************************************************
|
||||
//
|
||||
// fpu.h - Prototypes for the floatint point manipulation routines.
|
||||
//
|
||||
// Copyright (c) 2011-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __FPU_H__
|
||||
#define __FPU_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to FPUHalfPrecisionSet as the ulMode parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FPU_HALF_IEEE 0x00000000
|
||||
#define FPU_HALF_ALTERNATE 0x04000000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to FPUNaNModeSet as the ulMode parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FPU_NAN_PROPAGATE 0x00000000
|
||||
#define FPU_NAN_DEFAULT 0x02000000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to FPUFlushToZeroModeSet as the ulMode parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FPU_FLUSH_TO_ZERO_DIS 0x00000000
|
||||
#define FPU_FLUSH_TO_ZERO_EN 0x01000000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to FPURoundingModeSet as the ulMode parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define FPU_ROUND_NEAREST 0x00000000
|
||||
#define FPU_ROUND_POS_INF 0x00400000
|
||||
#define FPU_ROUND_NEG_INF 0x00800000
|
||||
#define FPU_ROUND_ZERO 0x00c00000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void FPUEnable(void);
|
||||
extern void FPUDisable(void);
|
||||
extern void FPUStackingEnable(void);
|
||||
extern void FPULazyStackingEnable(void);
|
||||
extern void FPUStackingDisable(void);
|
||||
extern void FPUHalfPrecisionModeSet(unsigned long ulMode);
|
||||
extern void FPUNaNModeSet(unsigned long ulMode);
|
||||
extern void FPUFlushToZeroModeSet(unsigned long ulMode);
|
||||
extern void FPURoundingModeSet(unsigned long ulMode);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __FPU_H__
|
||||
|
||||
@ -1,199 +1,199 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// gpio.h - Defines and Macros for GPIO API.
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __GPIO_H__
|
||||
#define __GPIO_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following values define the bit field for the ucPins argument to several
|
||||
// of the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_PIN_0 0x00000001 // GPIO pin 0
|
||||
#define GPIO_PIN_1 0x00000002 // GPIO pin 1
|
||||
#define GPIO_PIN_2 0x00000004 // GPIO pin 2
|
||||
#define GPIO_PIN_3 0x00000008 // GPIO pin 3
|
||||
#define GPIO_PIN_4 0x00000010 // GPIO pin 4
|
||||
#define GPIO_PIN_5 0x00000020 // GPIO pin 5
|
||||
#define GPIO_PIN_6 0x00000040 // GPIO pin 6
|
||||
#define GPIO_PIN_7 0x00000080 // GPIO pin 7
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and
|
||||
// returned from GPIODirModeGet.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input
|
||||
#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output
|
||||
#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and
|
||||
// returned from GPIOIntTypeGet.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge
|
||||
#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge
|
||||
#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges
|
||||
#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level
|
||||
#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level
|
||||
#define GPIO_DISCRETE_INT 0x00010000 // Interrupt for individual pins
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,
|
||||
// and returned by GPIOPadConfigGet in the *pulStrength parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength
|
||||
#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength
|
||||
#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength
|
||||
#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control
|
||||
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,
|
||||
// and returned by GPIOPadConfigGet in the *pulPadType parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull
|
||||
#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up
|
||||
#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down
|
||||
#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain
|
||||
#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up
|
||||
#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down
|
||||
#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
|
||||
unsigned long ulPinIO);
|
||||
extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);
|
||||
extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
|
||||
unsigned long ulIntType);
|
||||
extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);
|
||||
extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,
|
||||
unsigned long ulStrength,
|
||||
unsigned long ulPadType);
|
||||
extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,
|
||||
unsigned long *pulStrength,
|
||||
unsigned long *pulPadType);
|
||||
extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);
|
||||
extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);
|
||||
extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPortIntRegister(unsigned long ulPort,
|
||||
void (*pfnIntHandler)(void));
|
||||
extern void GPIOPortIntUnregister(unsigned long ulPort);
|
||||
extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,
|
||||
unsigned char ucVal);
|
||||
extern void GPIOPinConfigure(unsigned long ulPinConfig);
|
||||
extern void GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeEPI(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeEthernetLED(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeEthernetMII(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeFan(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeGPIOOutputOD(unsigned long ulPort,
|
||||
unsigned char ucPins);
|
||||
extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeI2CSCL(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeLPC(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypePECIRx(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypePECITx(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeUSBAnalog(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIODMATriggerEnable(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIODMATriggerDisable(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOADCTriggerEnable(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOADCTriggerDisable(unsigned long ulPort, unsigned char ucPins);
|
||||
|
||||
//****************************************************************************
|
||||
//
|
||||
// The definitions for GPIOPinConfigure previously resided in this file but
|
||||
// have been moved to pin_map.h and made part-specific (in other words, only
|
||||
// those definitions that are valid based on the selected part, as defined by
|
||||
// PART_<partnum>, will be made available). For backwards compatibility,
|
||||
// pin_map.h is included here so that the expected definitions will still be
|
||||
// available (though part-specific now, so some that were previously available
|
||||
// but inappropriate for the given part will not be available).
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
#include "pin_map.h"
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __GPIO_H__
|
||||
//*****************************************************************************
|
||||
//
|
||||
// gpio.h - Defines and Macros for GPIO API.
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __GPIO_H__
|
||||
#define __GPIO_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following values define the bit field for the ucPins argument to several
|
||||
// of the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_PIN_0 0x00000001 // GPIO pin 0
|
||||
#define GPIO_PIN_1 0x00000002 // GPIO pin 1
|
||||
#define GPIO_PIN_2 0x00000004 // GPIO pin 2
|
||||
#define GPIO_PIN_3 0x00000008 // GPIO pin 3
|
||||
#define GPIO_PIN_4 0x00000010 // GPIO pin 4
|
||||
#define GPIO_PIN_5 0x00000020 // GPIO pin 5
|
||||
#define GPIO_PIN_6 0x00000040 // GPIO pin 6
|
||||
#define GPIO_PIN_7 0x00000080 // GPIO pin 7
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and
|
||||
// returned from GPIODirModeGet.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input
|
||||
#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output
|
||||
#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and
|
||||
// returned from GPIOIntTypeGet.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge
|
||||
#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge
|
||||
#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges
|
||||
#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level
|
||||
#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level
|
||||
#define GPIO_DISCRETE_INT 0x00010000 // Interrupt for individual pins
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter,
|
||||
// and returned by GPIOPadConfigGet in the *pulStrength parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength
|
||||
#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength
|
||||
#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength
|
||||
#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control
|
||||
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter,
|
||||
// and returned by GPIOPadConfigGet in the *pulPadType parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull
|
||||
#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up
|
||||
#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down
|
||||
#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain
|
||||
#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up
|
||||
#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down
|
||||
#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
|
||||
unsigned long ulPinIO);
|
||||
extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);
|
||||
extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
|
||||
unsigned long ulIntType);
|
||||
extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);
|
||||
extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins,
|
||||
unsigned long ulStrength,
|
||||
unsigned long ulPadType);
|
||||
extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin,
|
||||
unsigned long *pulStrength,
|
||||
unsigned long *pulPadType);
|
||||
extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins);
|
||||
extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked);
|
||||
extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPortIntRegister(unsigned long ulPort,
|
||||
void (*pfnIntHandler)(void));
|
||||
extern void GPIOPortIntUnregister(unsigned long ulPort);
|
||||
extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,
|
||||
unsigned char ucVal);
|
||||
extern void GPIOPinConfigure(unsigned long ulPinConfig);
|
||||
extern void GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeEPI(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeEthernetLED(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeEthernetMII(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeFan(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeGPIOOutputOD(unsigned long ulPort,
|
||||
unsigned char ucPins);
|
||||
extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeI2CSCL(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeI2S(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeLPC(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypePECIRx(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypePECITx(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeUSBAnalog(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIODMATriggerEnable(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIODMATriggerDisable(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOADCTriggerEnable(unsigned long ulPort, unsigned char ucPins);
|
||||
extern void GPIOADCTriggerDisable(unsigned long ulPort, unsigned char ucPins);
|
||||
|
||||
//****************************************************************************
|
||||
//
|
||||
// The definitions for GPIOPinConfigure previously resided in this file but
|
||||
// have been moved to pin_map.h and made part-specific (in other words, only
|
||||
// those definitions that are valid based on the selected part, as defined by
|
||||
// PART_<partnum>, will be made available). For backwards compatibility,
|
||||
// pin_map.h is included here so that the expected definitions will still be
|
||||
// available (though part-specific now, so some that were previously available
|
||||
// but inappropriate for the given part will not be available).
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
#include "pin_map.h"
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __GPIO_H__
|
||||
|
||||
@ -1,167 +1,167 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hibernate.h - API definition for the Hibernation module.
|
||||
//
|
||||
// Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HIBERNATE_H__
|
||||
#define __HIBERNATE_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Macros needed for selecting the clock source for HibernateClockSelect()
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIBERNATE_CLOCK_SEL_RAW 0x00000004
|
||||
#define HIBERNATE_CLOCK_SEL_DIV128 0x00000000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Macros need to configure wake events for HibernateWakeSet()
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIBERNATE_WAKE_PIN 0x00000010
|
||||
#define HIBERNATE_WAKE_RTC 0x00000008
|
||||
#define HIBERNATE_WAKE_LOW_BAT 0x00000200
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Macros needed to configure low battery detect for HibernateLowBatSet()
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIBERNATE_LOW_BAT_DETECT 0x00000020
|
||||
#define HIBERNATE_LOW_BAT_ABORT 0x000000A0
|
||||
#define HIBERNATE_LOW_BAT_1_9V 0x00000000
|
||||
#define HIBERNATE_LOW_BAT_2_1V 0x00002000
|
||||
#define HIBERNATE_LOW_BAT_2_3V 0x00004000
|
||||
#define HIBERNATE_LOW_BAT_2_5V 0x00006000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Macros defining interrupt source bits for the interrupt functions.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIBERNATE_INT_WR_COMPLETE 0x00000010
|
||||
#define HIBERNATE_INT_PIN_WAKE 0x00000008
|
||||
#define HIBERNATE_INT_LOW_BAT 0x00000004
|
||||
#define HIBERNATE_INT_RTC_MATCH_0 0x00000001
|
||||
#define HIBERNATE_INT_RTC_MATCH_1 0x00000002
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Macros defining oscillator configuration options for the
|
||||
// HibernateClockConfig() function.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIBERNATE_OSC_LOWDRIVE 0x00040000
|
||||
#define HIBERNATE_OSC_HIGHDRIVE 0x00060000
|
||||
#define HIBERNATE_OSC_DISABLE 0x00010000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// API Function prototypes
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void HibernateGPIORetentionEnable(void);
|
||||
extern void HibernateGPIORetentionDisable(void);
|
||||
extern tBoolean HibernateGPIORetentionGet(void);
|
||||
extern void HibernateEnableExpClk(unsigned long ulHibClk);
|
||||
extern void HibernateDisable(void);
|
||||
extern void HibernateClockSelect(unsigned long ulClockInput);
|
||||
extern void HibernateRTCEnable(void);
|
||||
extern void HibernateRTCDisable(void);
|
||||
extern void HibernateWakeSet(unsigned long ulWakeFlags);
|
||||
extern unsigned long HibernateWakeGet(void);
|
||||
extern void HibernateLowBatSet(unsigned long ulLowBatFlags);
|
||||
extern unsigned long HibernateLowBatGet(void);
|
||||
extern void HibernateRTCSet(unsigned long ulRTCValue);
|
||||
extern unsigned long HibernateRTCGet(void);
|
||||
extern void HibernateRTCMatch0Set(unsigned long ulMatch);
|
||||
extern unsigned long HibernateRTCMatch0Get(void);
|
||||
extern void HibernateRTCMatch1Set(unsigned long ulMatch);
|
||||
extern unsigned long HibernateRTCMatch1Get(void);
|
||||
extern void HibernateRTCTrimSet(unsigned long ulTrim);
|
||||
extern unsigned long HibernateRTCTrimGet(void);
|
||||
extern void HibernateDataSet(unsigned long *pulData, unsigned long ulCount);
|
||||
extern void HibernateDataGet(unsigned long *pulData, unsigned long ulCount);
|
||||
extern void HibernateRequest(void);
|
||||
extern void HibernateIntEnable(unsigned long ulIntFlags);
|
||||
extern void HibernateIntDisable(unsigned long ulIntFlags);
|
||||
extern void HibernateIntRegister(void (*pfnHandler)(void));
|
||||
extern void HibernateIntUnregister(void);
|
||||
extern unsigned long HibernateIntStatus(tBoolean bMasked);
|
||||
extern void HibernateIntClear(unsigned long ulIntFlags);
|
||||
extern unsigned long HibernateIsActive(void);
|
||||
extern void HibernateRTCSSMatch0Set(unsigned long ulMatch);
|
||||
extern unsigned long HibernateRTCSSMatch0Get(void);
|
||||
extern unsigned long HibernateRTCSSGet(void);
|
||||
extern void HibernateClockConfig(unsigned long ulConfig);
|
||||
extern void HibernateBatCheckStart(void);
|
||||
extern unsigned long HibernateBatCheckDone(void);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Several Hibernate module APIs have been renamed, with the original function
|
||||
// name being deprecated. These defines provide backward compatibility.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
#include "sysctl.h"
|
||||
#define HibernateEnable(a) \
|
||||
HibernateEnableExpClk(a, SysCtlClockGet())
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __HIBERNATE_H__
|
||||
//*****************************************************************************
|
||||
//
|
||||
// hibernate.h - API definition for the Hibernation module.
|
||||
//
|
||||
// Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __HIBERNATE_H__
|
||||
#define __HIBERNATE_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Macros needed for selecting the clock source for HibernateClockSelect()
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIBERNATE_CLOCK_SEL_RAW 0x00000004
|
||||
#define HIBERNATE_CLOCK_SEL_DIV128 0x00000000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Macros need to configure wake events for HibernateWakeSet()
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIBERNATE_WAKE_PIN 0x00000010
|
||||
#define HIBERNATE_WAKE_RTC 0x00000008
|
||||
#define HIBERNATE_WAKE_LOW_BAT 0x00000200
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Macros needed to configure low battery detect for HibernateLowBatSet()
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIBERNATE_LOW_BAT_DETECT 0x00000020
|
||||
#define HIBERNATE_LOW_BAT_ABORT 0x000000A0
|
||||
#define HIBERNATE_LOW_BAT_1_9V 0x00000000
|
||||
#define HIBERNATE_LOW_BAT_2_1V 0x00002000
|
||||
#define HIBERNATE_LOW_BAT_2_3V 0x00004000
|
||||
#define HIBERNATE_LOW_BAT_2_5V 0x00006000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Macros defining interrupt source bits for the interrupt functions.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIBERNATE_INT_WR_COMPLETE 0x00000010
|
||||
#define HIBERNATE_INT_PIN_WAKE 0x00000008
|
||||
#define HIBERNATE_INT_LOW_BAT 0x00000004
|
||||
#define HIBERNATE_INT_RTC_MATCH_0 0x00000001
|
||||
#define HIBERNATE_INT_RTC_MATCH_1 0x00000002
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Macros defining oscillator configuration options for the
|
||||
// HibernateClockConfig() function.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define HIBERNATE_OSC_LOWDRIVE 0x00040000
|
||||
#define HIBERNATE_OSC_HIGHDRIVE 0x00060000
|
||||
#define HIBERNATE_OSC_DISABLE 0x00010000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// API Function prototypes
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void HibernateGPIORetentionEnable(void);
|
||||
extern void HibernateGPIORetentionDisable(void);
|
||||
extern tBoolean HibernateGPIORetentionGet(void);
|
||||
extern void HibernateEnableExpClk(unsigned long ulHibClk);
|
||||
extern void HibernateDisable(void);
|
||||
extern void HibernateClockSelect(unsigned long ulClockInput);
|
||||
extern void HibernateRTCEnable(void);
|
||||
extern void HibernateRTCDisable(void);
|
||||
extern void HibernateWakeSet(unsigned long ulWakeFlags);
|
||||
extern unsigned long HibernateWakeGet(void);
|
||||
extern void HibernateLowBatSet(unsigned long ulLowBatFlags);
|
||||
extern unsigned long HibernateLowBatGet(void);
|
||||
extern void HibernateRTCSet(unsigned long ulRTCValue);
|
||||
extern unsigned long HibernateRTCGet(void);
|
||||
extern void HibernateRTCMatch0Set(unsigned long ulMatch);
|
||||
extern unsigned long HibernateRTCMatch0Get(void);
|
||||
extern void HibernateRTCMatch1Set(unsigned long ulMatch);
|
||||
extern unsigned long HibernateRTCMatch1Get(void);
|
||||
extern void HibernateRTCTrimSet(unsigned long ulTrim);
|
||||
extern unsigned long HibernateRTCTrimGet(void);
|
||||
extern void HibernateDataSet(unsigned long *pulData, unsigned long ulCount);
|
||||
extern void HibernateDataGet(unsigned long *pulData, unsigned long ulCount);
|
||||
extern void HibernateRequest(void);
|
||||
extern void HibernateIntEnable(unsigned long ulIntFlags);
|
||||
extern void HibernateIntDisable(unsigned long ulIntFlags);
|
||||
extern void HibernateIntRegister(void (*pfnHandler)(void));
|
||||
extern void HibernateIntUnregister(void);
|
||||
extern unsigned long HibernateIntStatus(tBoolean bMasked);
|
||||
extern void HibernateIntClear(unsigned long ulIntFlags);
|
||||
extern unsigned long HibernateIsActive(void);
|
||||
extern void HibernateRTCSSMatch0Set(unsigned long ulMatch);
|
||||
extern unsigned long HibernateRTCSSMatch0Get(void);
|
||||
extern unsigned long HibernateRTCSSGet(void);
|
||||
extern void HibernateClockConfig(unsigned long ulConfig);
|
||||
extern void HibernateBatCheckStart(void);
|
||||
extern unsigned long HibernateBatCheckDone(void);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Several Hibernate module APIs have been renamed, with the original function
|
||||
// name being deprecated. These defines provide backward compatibility.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
#include "sysctl.h"
|
||||
#define HibernateEnable(a) \
|
||||
HibernateEnableExpClk(a, SysCtlClockGet())
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __HIBERNATE_H__
|
||||
|
||||
@ -1,224 +1,224 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// i2c.h - Prototypes for the I2C Driver.
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __I2C_H__
|
||||
#define __I2C_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines for the API.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Interrupt defines.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_INT_MASTER 0x00000001
|
||||
#define I2C_INT_SLAVE 0x00000002
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// I2C Master commands.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_CMD_SINGLE_SEND \
|
||||
0x00000007
|
||||
#define I2C_MASTER_CMD_SINGLE_RECEIVE \
|
||||
0x00000007
|
||||
#define I2C_MASTER_CMD_BURST_SEND_START \
|
||||
0x00000003
|
||||
#define I2C_MASTER_CMD_BURST_SEND_CONT \
|
||||
0x00000001
|
||||
#define I2C_MASTER_CMD_BURST_SEND_FINISH \
|
||||
0x00000005
|
||||
#define I2C_MASTER_CMD_BURST_SEND_STOP \
|
||||
0x00000004
|
||||
#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \
|
||||
0x00000004
|
||||
#define I2C_MASTER_CMD_BURST_RECEIVE_START \
|
||||
0x0000000b
|
||||
#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \
|
||||
0x00000009
|
||||
#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \
|
||||
0x00000005
|
||||
#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \
|
||||
0x00000004
|
||||
#define I2C_MASTER_CMD_QUICK_COMMAND \
|
||||
0x00000027
|
||||
#define I2C_MASTER_CMD_HS_MASTER_CODE_SEND \
|
||||
0x00000011
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// I2C Master error status.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_ERR_NONE 0
|
||||
#define I2C_MASTER_ERR_ADDR_ACK 0x00000004
|
||||
#define I2C_MASTER_ERR_DATA_ACK 0x00000008
|
||||
#define I2C_MASTER_ERR_ARB_LOST 0x00000010
|
||||
#define I2C_MASTER_ERR_CLK_TOUT 0x00000080
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// I2C Slave action requests
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SLAVE_ACT_NONE 0
|
||||
#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data
|
||||
#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data
|
||||
#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte
|
||||
#define I2C_SLAVE_ACT_OWN2SEL 0x00000008 // Master requested secondary slave
|
||||
#define I2C_SLAVE_ACT_QCMD 0x00000010 // Master has sent a Quick Command
|
||||
#define I2C_SLAVE_ACT_QCMD_DATA 0x00000020 // Master Quick Command value
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Miscellaneous I2C driver definitions.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// I2C Master interrupts.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_INT_TIMEOUT 0x00000002 // Clock Timeout Interrupt.
|
||||
#define I2C_MASTER_INT_DATA 0x00000001 // Data Interrupt.
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// I2C Slave interrupts.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt.
|
||||
#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt.
|
||||
#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt.
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void));
|
||||
extern void I2CIntUnregister(unsigned long ulBase);
|
||||
extern tBoolean I2CMasterBusBusy(unsigned long ulBase);
|
||||
extern tBoolean I2CMasterBusy(unsigned long ulBase);
|
||||
extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd);
|
||||
extern unsigned long I2CMasterDataGet(unsigned long ulBase);
|
||||
extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData);
|
||||
extern void I2CMasterDisable(unsigned long ulBase);
|
||||
extern void I2CMasterEnable(unsigned long ulBase);
|
||||
extern unsigned long I2CMasterErr(unsigned long ulBase);
|
||||
extern void I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk,
|
||||
tBoolean bFast);
|
||||
extern void I2CMasterIntClear(unsigned long ulBase);
|
||||
extern void I2CMasterIntDisable(unsigned long ulBase);
|
||||
extern void I2CMasterIntEnable(unsigned long ulBase);
|
||||
extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked);
|
||||
extern void I2CMasterIntEnableEx(unsigned long ulBase,
|
||||
unsigned long ulIntFlags);
|
||||
extern void I2CMasterIntDisableEx(unsigned long ulBase,
|
||||
unsigned long ulIntFlags);
|
||||
extern unsigned long I2CMasterIntStatusEx(unsigned long ulBase,
|
||||
tBoolean bMasked);
|
||||
extern void I2CMasterIntClearEx(unsigned long ulBase,
|
||||
unsigned long ulIntFlags);
|
||||
extern void I2CMasterTimeoutSet(unsigned long ulBase, unsigned long ulValue);
|
||||
extern void I2CSlaveACKOverride(unsigned long ulBase, tBoolean bEnable);
|
||||
extern void I2CSlaveACKValueSet(unsigned long ulBase, tBoolean bACK);
|
||||
extern unsigned long I2CMasterLineStateGet(unsigned long ulBase);
|
||||
extern void I2CMasterSlaveAddrSet(unsigned long ulBase,
|
||||
unsigned char ucSlaveAddr,
|
||||
tBoolean bReceive);
|
||||
extern unsigned long I2CSlaveDataGet(unsigned long ulBase);
|
||||
extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData);
|
||||
extern void I2CSlaveDisable(unsigned long ulBase);
|
||||
extern void I2CSlaveEnable(unsigned long ulBase);
|
||||
extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr);
|
||||
extern void I2CSlaveAddressSet(unsigned long ulBase, unsigned char ucAddrNum,
|
||||
unsigned char ucSlaveAddr);
|
||||
extern void I2CSlaveIntClear(unsigned long ulBase);
|
||||
extern void I2CSlaveIntDisable(unsigned long ulBase);
|
||||
extern void I2CSlaveIntEnable(unsigned long ulBase);
|
||||
extern void I2CSlaveIntClearEx(unsigned long ulBase, unsigned long ulIntFlags);
|
||||
extern void I2CSlaveIntDisableEx(unsigned long ulBase,
|
||||
unsigned long ulIntFlags);
|
||||
extern void I2CSlaveIntEnableEx(unsigned long ulBase, unsigned long ulIntFlags);
|
||||
extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked);
|
||||
extern unsigned long I2CSlaveIntStatusEx(unsigned long ulBase,
|
||||
tBoolean bMasked);
|
||||
extern unsigned long I2CSlaveStatus(unsigned long ulBase);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Several I2C APIs have been renamed, with the original function name being
|
||||
// deprecated. These defines provide backward compatibility.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
#include "driverlib/sysctl.h"
|
||||
#define I2CMasterInit(a, b) \
|
||||
I2CMasterInitExpClk(a, SysCtlClockGet(), b)
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __I2C_H__
|
||||
//*****************************************************************************
|
||||
//
|
||||
// i2c.h - Prototypes for the I2C Driver.
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __I2C_H__
|
||||
#define __I2C_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines for the API.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Interrupt defines.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_INT_MASTER 0x00000001
|
||||
#define I2C_INT_SLAVE 0x00000002
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// I2C Master commands.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_CMD_SINGLE_SEND \
|
||||
0x00000007
|
||||
#define I2C_MASTER_CMD_SINGLE_RECEIVE \
|
||||
0x00000007
|
||||
#define I2C_MASTER_CMD_BURST_SEND_START \
|
||||
0x00000003
|
||||
#define I2C_MASTER_CMD_BURST_SEND_CONT \
|
||||
0x00000001
|
||||
#define I2C_MASTER_CMD_BURST_SEND_FINISH \
|
||||
0x00000005
|
||||
#define I2C_MASTER_CMD_BURST_SEND_STOP \
|
||||
0x00000004
|
||||
#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \
|
||||
0x00000004
|
||||
#define I2C_MASTER_CMD_BURST_RECEIVE_START \
|
||||
0x0000000b
|
||||
#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \
|
||||
0x00000009
|
||||
#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \
|
||||
0x00000005
|
||||
#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \
|
||||
0x00000004
|
||||
#define I2C_MASTER_CMD_QUICK_COMMAND \
|
||||
0x00000027
|
||||
#define I2C_MASTER_CMD_HS_MASTER_CODE_SEND \
|
||||
0x00000011
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// I2C Master error status.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_ERR_NONE 0
|
||||
#define I2C_MASTER_ERR_ADDR_ACK 0x00000004
|
||||
#define I2C_MASTER_ERR_DATA_ACK 0x00000008
|
||||
#define I2C_MASTER_ERR_ARB_LOST 0x00000010
|
||||
#define I2C_MASTER_ERR_CLK_TOUT 0x00000080
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// I2C Slave action requests
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SLAVE_ACT_NONE 0
|
||||
#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data
|
||||
#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data
|
||||
#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte
|
||||
#define I2C_SLAVE_ACT_OWN2SEL 0x00000008 // Master requested secondary slave
|
||||
#define I2C_SLAVE_ACT_QCMD 0x00000010 // Master has sent a Quick Command
|
||||
#define I2C_SLAVE_ACT_QCMD_DATA 0x00000020 // Master Quick Command value
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Miscellaneous I2C driver definitions.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// I2C Master interrupts.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_MASTER_INT_TIMEOUT 0x00000002 // Clock Timeout Interrupt.
|
||||
#define I2C_MASTER_INT_DATA 0x00000001 // Data Interrupt.
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// I2C Slave interrupts.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt.
|
||||
#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt.
|
||||
#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt.
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void));
|
||||
extern void I2CIntUnregister(unsigned long ulBase);
|
||||
extern tBoolean I2CMasterBusBusy(unsigned long ulBase);
|
||||
extern tBoolean I2CMasterBusy(unsigned long ulBase);
|
||||
extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd);
|
||||
extern unsigned long I2CMasterDataGet(unsigned long ulBase);
|
||||
extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData);
|
||||
extern void I2CMasterDisable(unsigned long ulBase);
|
||||
extern void I2CMasterEnable(unsigned long ulBase);
|
||||
extern unsigned long I2CMasterErr(unsigned long ulBase);
|
||||
extern void I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk,
|
||||
tBoolean bFast);
|
||||
extern void I2CMasterIntClear(unsigned long ulBase);
|
||||
extern void I2CMasterIntDisable(unsigned long ulBase);
|
||||
extern void I2CMasterIntEnable(unsigned long ulBase);
|
||||
extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked);
|
||||
extern void I2CMasterIntEnableEx(unsigned long ulBase,
|
||||
unsigned long ulIntFlags);
|
||||
extern void I2CMasterIntDisableEx(unsigned long ulBase,
|
||||
unsigned long ulIntFlags);
|
||||
extern unsigned long I2CMasterIntStatusEx(unsigned long ulBase,
|
||||
tBoolean bMasked);
|
||||
extern void I2CMasterIntClearEx(unsigned long ulBase,
|
||||
unsigned long ulIntFlags);
|
||||
extern void I2CMasterTimeoutSet(unsigned long ulBase, unsigned long ulValue);
|
||||
extern void I2CSlaveACKOverride(unsigned long ulBase, tBoolean bEnable);
|
||||
extern void I2CSlaveACKValueSet(unsigned long ulBase, tBoolean bACK);
|
||||
extern unsigned long I2CMasterLineStateGet(unsigned long ulBase);
|
||||
extern void I2CMasterSlaveAddrSet(unsigned long ulBase,
|
||||
unsigned char ucSlaveAddr,
|
||||
tBoolean bReceive);
|
||||
extern unsigned long I2CSlaveDataGet(unsigned long ulBase);
|
||||
extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData);
|
||||
extern void I2CSlaveDisable(unsigned long ulBase);
|
||||
extern void I2CSlaveEnable(unsigned long ulBase);
|
||||
extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr);
|
||||
extern void I2CSlaveAddressSet(unsigned long ulBase, unsigned char ucAddrNum,
|
||||
unsigned char ucSlaveAddr);
|
||||
extern void I2CSlaveIntClear(unsigned long ulBase);
|
||||
extern void I2CSlaveIntDisable(unsigned long ulBase);
|
||||
extern void I2CSlaveIntEnable(unsigned long ulBase);
|
||||
extern void I2CSlaveIntClearEx(unsigned long ulBase, unsigned long ulIntFlags);
|
||||
extern void I2CSlaveIntDisableEx(unsigned long ulBase,
|
||||
unsigned long ulIntFlags);
|
||||
extern void I2CSlaveIntEnableEx(unsigned long ulBase, unsigned long ulIntFlags);
|
||||
extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked);
|
||||
extern unsigned long I2CSlaveIntStatusEx(unsigned long ulBase,
|
||||
tBoolean bMasked);
|
||||
extern unsigned long I2CSlaveStatus(unsigned long ulBase);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Several I2C APIs have been renamed, with the original function name being
|
||||
// deprecated. These defines provide backward compatibility.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
#include "driverlib/sysctl.h"
|
||||
#define I2CMasterInit(a, b) \
|
||||
I2CMasterInitExpClk(a, SysCtlClockGet(), b)
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __I2C_H__
|
||||
|
||||
@ -1,93 +1,93 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __INTERRUPT_H__
|
||||
#define __INTERRUPT_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Macro to generate an interrupt priority mask based on the number of bits
|
||||
// of priority supported by the hardware.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern tBoolean IntMasterEnable(void);
|
||||
extern tBoolean IntMasterDisable(void);
|
||||
extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));
|
||||
extern void IntUnregister(unsigned long ulInterrupt);
|
||||
extern void IntPriorityGroupingSet(unsigned long ulBits);
|
||||
extern unsigned long IntPriorityGroupingGet(void);
|
||||
extern void IntPrioritySet(unsigned long ulInterrupt,
|
||||
unsigned char ucPriority);
|
||||
extern long IntPriorityGet(unsigned long ulInterrupt);
|
||||
extern void IntEnable(unsigned long ulInterrupt);
|
||||
extern void IntDisable(unsigned long ulInterrupt);
|
||||
extern unsigned long IntIsEnabled(unsigned long ulInterrupt);
|
||||
extern void IntPendSet(unsigned long ulInterrupt);
|
||||
extern void IntPendClear(unsigned long ulInterrupt);
|
||||
extern void IntPriorityMaskSet(unsigned long ulPriorityMask);
|
||||
extern unsigned long IntPriorityMaskGet(void);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __INTERRUPT_H__
|
||||
//*****************************************************************************
|
||||
//
|
||||
// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __INTERRUPT_H__
|
||||
#define __INTERRUPT_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Macro to generate an interrupt priority mask based on the number of bits
|
||||
// of priority supported by the hardware.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern tBoolean IntMasterEnable(void);
|
||||
extern tBoolean IntMasterDisable(void);
|
||||
extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));
|
||||
extern void IntUnregister(unsigned long ulInterrupt);
|
||||
extern void IntPriorityGroupingSet(unsigned long ulBits);
|
||||
extern unsigned long IntPriorityGroupingGet(void);
|
||||
extern void IntPrioritySet(unsigned long ulInterrupt,
|
||||
unsigned char ucPriority);
|
||||
extern long IntPriorityGet(unsigned long ulInterrupt);
|
||||
extern void IntEnable(unsigned long ulInterrupt);
|
||||
extern void IntDisable(unsigned long ulInterrupt);
|
||||
extern unsigned long IntIsEnabled(unsigned long ulInterrupt);
|
||||
extern void IntPendSet(unsigned long ulInterrupt);
|
||||
extern void IntPendClear(unsigned long ulInterrupt);
|
||||
extern void IntPriorityMaskSet(unsigned long ulPriorityMask);
|
||||
extern unsigned long IntPriorityMaskGet(void);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __INTERRUPT_H__
|
||||
|
||||
@ -1,298 +1,298 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __PWM_H__
|
||||
#define __PWM_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following defines are passed to PWMGenConfigure() as the ulConfig
|
||||
// parameter and specify the configuration of the PWM generator.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode
|
||||
#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode
|
||||
#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates
|
||||
#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates
|
||||
#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode
|
||||
#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode
|
||||
#define PWM_GEN_MODE_FAULT_LATCHED \
|
||||
0x00040000 // Fault is latched
|
||||
#define PWM_GEN_MODE_FAULT_UNLATCHED \
|
||||
0x00000000 // Fault is not latched
|
||||
#define PWM_GEN_MODE_FAULT_MINPER \
|
||||
0x00020000 // Enable min fault period
|
||||
#define PWM_GEN_MODE_FAULT_NO_MINPER \
|
||||
0x00000000 // Disable min fault period
|
||||
#define PWM_GEN_MODE_FAULT_EXT 0x00010000 // Enable extended fault support
|
||||
#define PWM_GEN_MODE_FAULT_LEGACY \
|
||||
0x00000000 // Disable extended fault support
|
||||
#define PWM_GEN_MODE_DB_NO_SYNC 0x00000000 // Deadband updates occur
|
||||
// immediately
|
||||
#define PWM_GEN_MODE_DB_SYNC_LOCAL \
|
||||
0x0000A800 // Deadband updates locally
|
||||
// synchronized
|
||||
#define PWM_GEN_MODE_DB_SYNC_GLOBAL \
|
||||
0x0000FC00 // Deadband updates globally
|
||||
// synchronized
|
||||
#define PWM_GEN_MODE_GEN_NO_SYNC \
|
||||
0x00000000 // Generator mode updates occur
|
||||
// immediately
|
||||
#define PWM_GEN_MODE_GEN_SYNC_LOCAL \
|
||||
0x00000280 // Generator mode updates locally
|
||||
// synchronized
|
||||
#define PWM_GEN_MODE_GEN_SYNC_GLOBAL \
|
||||
0x000003C0 // Generator mode updates globally
|
||||
// synchronized
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines for enabling, disabling, and clearing PWM generator interrupts and
|
||||
// triggers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0
|
||||
#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD
|
||||
#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U
|
||||
#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D
|
||||
#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U
|
||||
#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D
|
||||
#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0
|
||||
#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD
|
||||
#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U
|
||||
#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D
|
||||
#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U
|
||||
#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines for enabling, disabling, and clearing PWM interrupts.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt
|
||||
#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt
|
||||
#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt
|
||||
#define PWM_INT_GEN_3 0x00000008 // Generator 3 interrupt
|
||||
#ifndef DEPRECATED
|
||||
#define PWM_INT_FAULT 0x00010000 // Fault interrupt
|
||||
#endif
|
||||
#define PWM_INT_FAULT0 0x00010000 // Fault0 interrupt
|
||||
#define PWM_INT_FAULT1 0x00020000 // Fault1 interrupt
|
||||
#define PWM_INT_FAULT2 0x00040000 // Fault2 interrupt
|
||||
#define PWM_INT_FAULT3 0x00080000 // Fault3 interrupt
|
||||
#define PWM_INT_FAULT_M 0x000F0000 // Fault interrupt source mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines to identify the generators within a module.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_GEN_0 0x00000040 // Offset address of Gen0
|
||||
#define PWM_GEN_1 0x00000080 // Offset address of Gen1
|
||||
#define PWM_GEN_2 0x000000C0 // Offset address of Gen2
|
||||
#define PWM_GEN_3 0x00000100 // Offset address of Gen3
|
||||
|
||||
#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0
|
||||
#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1
|
||||
#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2
|
||||
#define PWM_GEN_3_BIT 0x00000008 // Bit-wise ID for Gen3
|
||||
|
||||
#define PWM_GEN_EXT_0 0x00000800 // Offset of Gen0 ext address range
|
||||
#define PWM_GEN_EXT_1 0x00000880 // Offset of Gen1 ext address range
|
||||
#define PWM_GEN_EXT_2 0x00000900 // Offset of Gen2 ext address range
|
||||
#define PWM_GEN_EXT_3 0x00000980 // Offset of Gen3 ext address range
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines to identify the outputs within a module.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0
|
||||
#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1
|
||||
#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2
|
||||
#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3
|
||||
#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4
|
||||
#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5
|
||||
#define PWM_OUT_6 0x00000106 // Encoded offset address of PWM6
|
||||
#define PWM_OUT_7 0x00000107 // Encoded offset address of PWM7
|
||||
|
||||
#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0
|
||||
#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1
|
||||
#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2
|
||||
#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3
|
||||
#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4
|
||||
#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5
|
||||
#define PWM_OUT_6_BIT 0x00000040 // Bit-wise ID for PWM6
|
||||
#define PWM_OUT_7_BIT 0x00000080 // Bit-wise ID for PWM7
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines to identify each of the possible fault trigger conditions in
|
||||
// PWM_FAULT_GROUP_0.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_FAULT_GROUP_0 0
|
||||
|
||||
#define PWM_FAULT_FAULT0 0x00000001
|
||||
#define PWM_FAULT_FAULT1 0x00000002
|
||||
#define PWM_FAULT_FAULT2 0x00000004
|
||||
#define PWM_FAULT_FAULT3 0x00000008
|
||||
#define PWM_FAULT_ACMP0 0x00010000
|
||||
#define PWM_FAULT_ACMP1 0x00020000
|
||||
#define PWM_FAULT_ACMP2 0x00040000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines to identify each of the possible fault trigger conditions in
|
||||
// PWM_FAULT_GROUP_1.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_FAULT_GROUP_1 1
|
||||
|
||||
#define PWM_FAULT_DCMP0 0x00000001
|
||||
#define PWM_FAULT_DCMP1 0x00000002
|
||||
#define PWM_FAULT_DCMP2 0x00000004
|
||||
#define PWM_FAULT_DCMP3 0x00000008
|
||||
#define PWM_FAULT_DCMP4 0x00000010
|
||||
#define PWM_FAULT_DCMP5 0x00000020
|
||||
#define PWM_FAULT_DCMP6 0x00000040
|
||||
#define PWM_FAULT_DCMP7 0x00000080
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines to identify the sense of each of the external FAULTn signals
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_FAULT0_SENSE_HIGH 0x00000000
|
||||
#define PWM_FAULT0_SENSE_LOW 0x00000001
|
||||
#define PWM_FAULT1_SENSE_HIGH 0x00000000
|
||||
#define PWM_FAULT1_SENSE_LOW 0x00000002
|
||||
#define PWM_FAULT2_SENSE_HIGH 0x00000000
|
||||
#define PWM_FAULT2_SENSE_LOW 0x00000004
|
||||
#define PWM_FAULT3_SENSE_HIGH 0x00000000
|
||||
#define PWM_FAULT3_SENSE_LOW 0x00000008
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// API Function prototypes
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,
|
||||
unsigned long ulConfig);
|
||||
extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,
|
||||
unsigned long ulPeriod);
|
||||
extern unsigned long PWMGenPeriodGet(unsigned long ulBase,
|
||||
unsigned long ulGen);
|
||||
extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen);
|
||||
extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen);
|
||||
extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,
|
||||
unsigned long ulWidth);
|
||||
extern unsigned long PWMPulseWidthGet(unsigned long ulBase,
|
||||
unsigned long ulPWMOut);
|
||||
extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,
|
||||
unsigned short usRise, unsigned short usFall);
|
||||
extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen);
|
||||
extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits);
|
||||
extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits);
|
||||
extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,
|
||||
tBoolean bEnable);
|
||||
extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,
|
||||
tBoolean bInvert);
|
||||
extern void PWMOutputFaultLevel(unsigned long ulBase,
|
||||
unsigned long ulPWMOutBits,
|
||||
tBoolean bDriveHigh);
|
||||
extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,
|
||||
tBoolean bFaultSuppress);
|
||||
extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,
|
||||
void (*pfnIntHandler)(void));
|
||||
extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen);
|
||||
extern void PWMFaultIntRegister(unsigned long ulBase,
|
||||
void (*pfnIntHandler)(void));
|
||||
extern void PWMFaultIntUnregister(unsigned long ulBase);
|
||||
extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,
|
||||
unsigned long ulIntTrig);
|
||||
extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,
|
||||
unsigned long ulIntTrig);
|
||||
extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen,
|
||||
tBoolean bMasked);
|
||||
extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen,
|
||||
unsigned long ulInts);
|
||||
extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault);
|
||||
extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault);
|
||||
extern void PWMFaultIntClear(unsigned long ulBase);
|
||||
extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked);
|
||||
extern void PWMFaultIntClearExt(unsigned long ulBase,
|
||||
unsigned long ulFaultInts);
|
||||
extern void PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen,
|
||||
unsigned long ulMinFaultPeriod,
|
||||
unsigned long ulFaultSenses);
|
||||
extern void PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen,
|
||||
unsigned long ulGroup,
|
||||
unsigned long ulFaultTriggers);
|
||||
extern unsigned long PWMGenFaultTriggerGet(unsigned long ulBase,
|
||||
unsigned long ulGen,
|
||||
unsigned long ulGroup);
|
||||
extern unsigned long PWMGenFaultStatus(unsigned long ulBase,
|
||||
unsigned long ulGen,
|
||||
unsigned long ulGroup);
|
||||
extern void PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen,
|
||||
unsigned long ulGroup,
|
||||
unsigned long ulFaultTriggers);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __PWM_H__
|
||||
//*****************************************************************************
|
||||
//
|
||||
// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __PWM_H__
|
||||
#define __PWM_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The following defines are passed to PWMGenConfigure() as the ulConfig
|
||||
// parameter and specify the configuration of the PWM generator.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode
|
||||
#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode
|
||||
#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates
|
||||
#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates
|
||||
#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode
|
||||
#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode
|
||||
#define PWM_GEN_MODE_FAULT_LATCHED \
|
||||
0x00040000 // Fault is latched
|
||||
#define PWM_GEN_MODE_FAULT_UNLATCHED \
|
||||
0x00000000 // Fault is not latched
|
||||
#define PWM_GEN_MODE_FAULT_MINPER \
|
||||
0x00020000 // Enable min fault period
|
||||
#define PWM_GEN_MODE_FAULT_NO_MINPER \
|
||||
0x00000000 // Disable min fault period
|
||||
#define PWM_GEN_MODE_FAULT_EXT 0x00010000 // Enable extended fault support
|
||||
#define PWM_GEN_MODE_FAULT_LEGACY \
|
||||
0x00000000 // Disable extended fault support
|
||||
#define PWM_GEN_MODE_DB_NO_SYNC 0x00000000 // Deadband updates occur
|
||||
// immediately
|
||||
#define PWM_GEN_MODE_DB_SYNC_LOCAL \
|
||||
0x0000A800 // Deadband updates locally
|
||||
// synchronized
|
||||
#define PWM_GEN_MODE_DB_SYNC_GLOBAL \
|
||||
0x0000FC00 // Deadband updates globally
|
||||
// synchronized
|
||||
#define PWM_GEN_MODE_GEN_NO_SYNC \
|
||||
0x00000000 // Generator mode updates occur
|
||||
// immediately
|
||||
#define PWM_GEN_MODE_GEN_SYNC_LOCAL \
|
||||
0x00000280 // Generator mode updates locally
|
||||
// synchronized
|
||||
#define PWM_GEN_MODE_GEN_SYNC_GLOBAL \
|
||||
0x000003C0 // Generator mode updates globally
|
||||
// synchronized
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines for enabling, disabling, and clearing PWM generator interrupts and
|
||||
// triggers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0
|
||||
#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD
|
||||
#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U
|
||||
#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D
|
||||
#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U
|
||||
#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D
|
||||
#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0
|
||||
#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD
|
||||
#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U
|
||||
#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D
|
||||
#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U
|
||||
#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines for enabling, disabling, and clearing PWM interrupts.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt
|
||||
#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt
|
||||
#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt
|
||||
#define PWM_INT_GEN_3 0x00000008 // Generator 3 interrupt
|
||||
#ifndef DEPRECATED
|
||||
#define PWM_INT_FAULT 0x00010000 // Fault interrupt
|
||||
#endif
|
||||
#define PWM_INT_FAULT0 0x00010000 // Fault0 interrupt
|
||||
#define PWM_INT_FAULT1 0x00020000 // Fault1 interrupt
|
||||
#define PWM_INT_FAULT2 0x00040000 // Fault2 interrupt
|
||||
#define PWM_INT_FAULT3 0x00080000 // Fault3 interrupt
|
||||
#define PWM_INT_FAULT_M 0x000F0000 // Fault interrupt source mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines to identify the generators within a module.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_GEN_0 0x00000040 // Offset address of Gen0
|
||||
#define PWM_GEN_1 0x00000080 // Offset address of Gen1
|
||||
#define PWM_GEN_2 0x000000C0 // Offset address of Gen2
|
||||
#define PWM_GEN_3 0x00000100 // Offset address of Gen3
|
||||
|
||||
#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0
|
||||
#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1
|
||||
#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2
|
||||
#define PWM_GEN_3_BIT 0x00000008 // Bit-wise ID for Gen3
|
||||
|
||||
#define PWM_GEN_EXT_0 0x00000800 // Offset of Gen0 ext address range
|
||||
#define PWM_GEN_EXT_1 0x00000880 // Offset of Gen1 ext address range
|
||||
#define PWM_GEN_EXT_2 0x00000900 // Offset of Gen2 ext address range
|
||||
#define PWM_GEN_EXT_3 0x00000980 // Offset of Gen3 ext address range
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines to identify the outputs within a module.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0
|
||||
#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1
|
||||
#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2
|
||||
#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3
|
||||
#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4
|
||||
#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5
|
||||
#define PWM_OUT_6 0x00000106 // Encoded offset address of PWM6
|
||||
#define PWM_OUT_7 0x00000107 // Encoded offset address of PWM7
|
||||
|
||||
#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0
|
||||
#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1
|
||||
#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2
|
||||
#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3
|
||||
#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4
|
||||
#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5
|
||||
#define PWM_OUT_6_BIT 0x00000040 // Bit-wise ID for PWM6
|
||||
#define PWM_OUT_7_BIT 0x00000080 // Bit-wise ID for PWM7
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines to identify each of the possible fault trigger conditions in
|
||||
// PWM_FAULT_GROUP_0.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_FAULT_GROUP_0 0
|
||||
|
||||
#define PWM_FAULT_FAULT0 0x00000001
|
||||
#define PWM_FAULT_FAULT1 0x00000002
|
||||
#define PWM_FAULT_FAULT2 0x00000004
|
||||
#define PWM_FAULT_FAULT3 0x00000008
|
||||
#define PWM_FAULT_ACMP0 0x00010000
|
||||
#define PWM_FAULT_ACMP1 0x00020000
|
||||
#define PWM_FAULT_ACMP2 0x00040000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines to identify each of the possible fault trigger conditions in
|
||||
// PWM_FAULT_GROUP_1.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_FAULT_GROUP_1 1
|
||||
|
||||
#define PWM_FAULT_DCMP0 0x00000001
|
||||
#define PWM_FAULT_DCMP1 0x00000002
|
||||
#define PWM_FAULT_DCMP2 0x00000004
|
||||
#define PWM_FAULT_DCMP3 0x00000008
|
||||
#define PWM_FAULT_DCMP4 0x00000010
|
||||
#define PWM_FAULT_DCMP5 0x00000020
|
||||
#define PWM_FAULT_DCMP6 0x00000040
|
||||
#define PWM_FAULT_DCMP7 0x00000080
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Defines to identify the sense of each of the external FAULTn signals
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define PWM_FAULT0_SENSE_HIGH 0x00000000
|
||||
#define PWM_FAULT0_SENSE_LOW 0x00000001
|
||||
#define PWM_FAULT1_SENSE_HIGH 0x00000000
|
||||
#define PWM_FAULT1_SENSE_LOW 0x00000002
|
||||
#define PWM_FAULT2_SENSE_HIGH 0x00000000
|
||||
#define PWM_FAULT2_SENSE_LOW 0x00000004
|
||||
#define PWM_FAULT3_SENSE_HIGH 0x00000000
|
||||
#define PWM_FAULT3_SENSE_LOW 0x00000008
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// API Function prototypes
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen,
|
||||
unsigned long ulConfig);
|
||||
extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen,
|
||||
unsigned long ulPeriod);
|
||||
extern unsigned long PWMGenPeriodGet(unsigned long ulBase,
|
||||
unsigned long ulGen);
|
||||
extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen);
|
||||
extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen);
|
||||
extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut,
|
||||
unsigned long ulWidth);
|
||||
extern unsigned long PWMPulseWidthGet(unsigned long ulBase,
|
||||
unsigned long ulPWMOut);
|
||||
extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen,
|
||||
unsigned short usRise, unsigned short usFall);
|
||||
extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen);
|
||||
extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits);
|
||||
extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits);
|
||||
extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits,
|
||||
tBoolean bEnable);
|
||||
extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits,
|
||||
tBoolean bInvert);
|
||||
extern void PWMOutputFaultLevel(unsigned long ulBase,
|
||||
unsigned long ulPWMOutBits,
|
||||
tBoolean bDriveHigh);
|
||||
extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits,
|
||||
tBoolean bFaultSuppress);
|
||||
extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen,
|
||||
void (*pfnIntHandler)(void));
|
||||
extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen);
|
||||
extern void PWMFaultIntRegister(unsigned long ulBase,
|
||||
void (*pfnIntHandler)(void));
|
||||
extern void PWMFaultIntUnregister(unsigned long ulBase);
|
||||
extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen,
|
||||
unsigned long ulIntTrig);
|
||||
extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen,
|
||||
unsigned long ulIntTrig);
|
||||
extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen,
|
||||
tBoolean bMasked);
|
||||
extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen,
|
||||
unsigned long ulInts);
|
||||
extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault);
|
||||
extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault);
|
||||
extern void PWMFaultIntClear(unsigned long ulBase);
|
||||
extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked);
|
||||
extern void PWMFaultIntClearExt(unsigned long ulBase,
|
||||
unsigned long ulFaultInts);
|
||||
extern void PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen,
|
||||
unsigned long ulMinFaultPeriod,
|
||||
unsigned long ulFaultSenses);
|
||||
extern void PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen,
|
||||
unsigned long ulGroup,
|
||||
unsigned long ulFaultTriggers);
|
||||
extern unsigned long PWMGenFaultTriggerGet(unsigned long ulBase,
|
||||
unsigned long ulGen,
|
||||
unsigned long ulGroup);
|
||||
extern unsigned long PWMGenFaultStatus(unsigned long ulBase,
|
||||
unsigned long ulGen,
|
||||
unsigned long ulGroup);
|
||||
extern void PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen,
|
||||
unsigned long ulGroup,
|
||||
unsigned long ulFaultTriggers);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __PWM_H__
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,151 +1,151 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// ssi.h - Prototypes for the Synchronous Serial Interface Driver.
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __SSI_H__
|
||||
#define __SSI_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear
|
||||
// as the ulIntFlags parameter, and returned by SSIIntStatus.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_TXFF 0x00000008 // TX FIFO half full or less
|
||||
#define SSI_RXFF 0x00000004 // RX FIFO half full or more
|
||||
#define SSI_RXTO 0x00000002 // RX timeout
|
||||
#define SSI_RXOR 0x00000001 // RX overrun
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to SSIConfigSetExpClk.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0
|
||||
#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1
|
||||
#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0
|
||||
#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1
|
||||
#define SSI_FRF_TI 0x00000010 // TI frame format
|
||||
#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format
|
||||
|
||||
#define SSI_MODE_MASTER 0x00000000 // SSI master
|
||||
#define SSI_MODE_SLAVE 0x00000001 // SSI slave
|
||||
#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to SSIDMAEnable() and SSIDMADisable().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit
|
||||
#define SSI_DMA_RX 0x00000001 // Enable DMA for receive
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to SSIClockSourceSet() or returned from
|
||||
// SSIClockSourceGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_CLOCK_SYSTEM 0x00000000
|
||||
#define SSI_CLOCK_PIOSC 0x00000005
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk,
|
||||
unsigned long ulProtocol, unsigned long ulMode,
|
||||
unsigned long ulBitRate,
|
||||
unsigned long ulDataWidth);
|
||||
extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData);
|
||||
extern long SSIDataGetNonBlocking(unsigned long ulBase,
|
||||
unsigned long *pulData);
|
||||
extern void SSIDataPut(unsigned long ulBase, unsigned long ulData);
|
||||
extern long SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData);
|
||||
extern void SSIDisable(unsigned long ulBase);
|
||||
extern void SSIEnable(unsigned long ulBase);
|
||||
extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
|
||||
extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
|
||||
extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
|
||||
extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
|
||||
extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);
|
||||
extern void SSIIntUnregister(unsigned long ulBase);
|
||||
extern void SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
|
||||
extern void SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
|
||||
extern tBoolean SSIBusy(unsigned long ulBase);
|
||||
extern void SSIClockSourceSet(unsigned long ulBase, unsigned long ulSource);
|
||||
extern unsigned long SSIClockSourceGet(unsigned long ulBase);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Several SSI APIs have been renamed, with the original function name being
|
||||
// deprecated. These defines provide backward compatibility.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
#include "sysctl.h"
|
||||
#define SSIConfig(a, b, c, d, e) \
|
||||
SSIConfigSetExpClk(a, SysCtlClockGet(), b, c, d, e)
|
||||
#define SSIDataNonBlockingGet(a, b) \
|
||||
SSIDataGetNonBlocking(a, b)
|
||||
#define SSIDataNonBlockingPut(a, b) \
|
||||
SSIDataPutNonBlocking(a, b)
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __SSI_H__
|
||||
//*****************************************************************************
|
||||
//
|
||||
// ssi.h - Prototypes for the Synchronous Serial Interface Driver.
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __SSI_H__
|
||||
#define __SSI_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear
|
||||
// as the ulIntFlags parameter, and returned by SSIIntStatus.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_TXFF 0x00000008 // TX FIFO half full or less
|
||||
#define SSI_RXFF 0x00000004 // RX FIFO half full or more
|
||||
#define SSI_RXTO 0x00000002 // RX timeout
|
||||
#define SSI_RXOR 0x00000001 // RX overrun
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to SSIConfigSetExpClk.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0
|
||||
#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1
|
||||
#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0
|
||||
#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1
|
||||
#define SSI_FRF_TI 0x00000010 // TI frame format
|
||||
#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format
|
||||
|
||||
#define SSI_MODE_MASTER 0x00000000 // SSI master
|
||||
#define SSI_MODE_SLAVE 0x00000001 // SSI slave
|
||||
#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to SSIDMAEnable() and SSIDMADisable().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit
|
||||
#define SSI_DMA_RX 0x00000001 // Enable DMA for receive
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to SSIClockSourceSet() or returned from
|
||||
// SSIClockSourceGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SSI_CLOCK_SYSTEM 0x00000000
|
||||
#define SSI_CLOCK_PIOSC 0x00000005
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk,
|
||||
unsigned long ulProtocol, unsigned long ulMode,
|
||||
unsigned long ulBitRate,
|
||||
unsigned long ulDataWidth);
|
||||
extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData);
|
||||
extern long SSIDataGetNonBlocking(unsigned long ulBase,
|
||||
unsigned long *pulData);
|
||||
extern void SSIDataPut(unsigned long ulBase, unsigned long ulData);
|
||||
extern long SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData);
|
||||
extern void SSIDisable(unsigned long ulBase);
|
||||
extern void SSIEnable(unsigned long ulBase);
|
||||
extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
|
||||
extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
|
||||
extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
|
||||
extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
|
||||
extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked);
|
||||
extern void SSIIntUnregister(unsigned long ulBase);
|
||||
extern void SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
|
||||
extern void SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
|
||||
extern tBoolean SSIBusy(unsigned long ulBase);
|
||||
extern void SSIClockSourceSet(unsigned long ulBase, unsigned long ulSource);
|
||||
extern unsigned long SSIClockSourceGet(unsigned long ulBase);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Several SSI APIs have been renamed, with the original function name being
|
||||
// deprecated. These defines provide backward compatibility.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
#include "sysctl.h"
|
||||
#define SSIConfig(a, b, c, d, e) \
|
||||
SSIConfigSetExpClk(a, SysCtlClockGet(), b, c, d, e)
|
||||
#define SSIDataNonBlockingGet(a, b) \
|
||||
SSIDataGetNonBlocking(a, b)
|
||||
#define SSIDataNonBlockingPut(a, b) \
|
||||
SSIDataPutNonBlocking(a, b)
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __SSI_H__
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,89 +1,89 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// sysexc.h - Prototypes for the System Exception Module routines.
|
||||
//
|
||||
// Copyright (c) 2011-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __SYSEXC_H__
|
||||
#define __SYSEXC_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to SysExcIntEnable, SysExcIntDisable, and
|
||||
// SysExcIntClear as the ulIntFlags parameter, and returned from
|
||||
// SysExcIntStatus.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSEXC_INT_FP_IXC 0x00000020 // FP Inexact exception interrupt
|
||||
#define SYSEXC_INT_FP_OFC 0x00000010 // FP Overflow exception interrupt
|
||||
#define SYSEXC_INT_FP_UFC 0x00000008 // FP Underflow exception interrupt
|
||||
#define SYSEXC_INT_FP_IOC 0x00000004 // FP Invalid operation interrupt
|
||||
#define SYSEXC_INT_FP_DZC 0x00000002 // FP Divide by zero exception int
|
||||
#define SYSEXC_INT_FP_IDC 0x00000001 // FP Input denormal exception int
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void SysExcIntRegister(void (*pfnHandler)(void));
|
||||
extern void SysExcIntUnregister(void);
|
||||
extern void SysExcIntEnable(unsigned long ulIntFlags);
|
||||
extern void SysExcIntDisable(unsigned long ulIntFlags);
|
||||
extern unsigned long SysExcIntStatus(tBoolean bMasked);
|
||||
extern void SysExcIntClear(unsigned long ulIntFlags);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __SYSEXC_H__
|
||||
//*****************************************************************************
|
||||
//
|
||||
// sysexc.h - Prototypes for the System Exception Module routines.
|
||||
//
|
||||
// Copyright (c) 2011-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __SYSEXC_H__
|
||||
#define __SYSEXC_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to SysExcIntEnable, SysExcIntDisable, and
|
||||
// SysExcIntClear as the ulIntFlags parameter, and returned from
|
||||
// SysExcIntStatus.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define SYSEXC_INT_FP_IXC 0x00000020 // FP Inexact exception interrupt
|
||||
#define SYSEXC_INT_FP_OFC 0x00000010 // FP Overflow exception interrupt
|
||||
#define SYSEXC_INT_FP_UFC 0x00000008 // FP Underflow exception interrupt
|
||||
#define SYSEXC_INT_FP_IOC 0x00000004 // FP Invalid operation interrupt
|
||||
#define SYSEXC_INT_FP_DZC 0x00000002 // FP Divide by zero exception int
|
||||
#define SYSEXC_INT_FP_IDC 0x00000001 // FP Input denormal exception int
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void SysExcIntRegister(void (*pfnHandler)(void));
|
||||
extern void SysExcIntUnregister(void);
|
||||
extern void SysExcIntEnable(unsigned long ulIntFlags);
|
||||
extern void SysExcIntDisable(unsigned long ulIntFlags);
|
||||
extern unsigned long SysExcIntStatus(tBoolean bMasked);
|
||||
extern void SysExcIntClear(unsigned long ulIntFlags);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __SYSEXC_H__
|
||||
|
||||
@ -1,78 +1,78 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// systick.h - Prototypes for the SysTick driver.
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __SYSTICK_H__
|
||||
#define __SYSTICK_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void SysTickEnable(void);
|
||||
extern void SysTickDisable(void);
|
||||
extern void SysTickIntRegister(void (*pfnHandler)(void));
|
||||
extern void SysTickIntUnregister(void);
|
||||
extern void SysTickIntEnable(void);
|
||||
extern void SysTickIntDisable(void);
|
||||
extern void SysTickPeriodSet(unsigned long ulPeriod);
|
||||
extern unsigned long SysTickPeriodGet(void);
|
||||
extern unsigned long SysTickValueGet(void);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __SYSTICK_H__
|
||||
//*****************************************************************************
|
||||
//
|
||||
// systick.h - Prototypes for the SysTick driver.
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __SYSTICK_H__
|
||||
#define __SYSTICK_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void SysTickEnable(void);
|
||||
extern void SysTickDisable(void);
|
||||
extern void SysTickIntRegister(void (*pfnHandler)(void));
|
||||
extern void SysTickIntUnregister(void);
|
||||
extern void SysTickIntEnable(void);
|
||||
extern void SysTickIntDisable(void);
|
||||
extern void SysTickPeriodSet(unsigned long ulPeriod);
|
||||
extern unsigned long SysTickPeriodGet(void);
|
||||
extern unsigned long SysTickValueGet(void);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __SYSTICK_H__
|
||||
|
||||
@ -1,236 +1,236 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// timer.h - Prototypes for the timer module
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __TIMER_H__
|
||||
#define __TIMER_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to TimerConfigure as the ulConfig parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer
|
||||
#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count
|
||||
// timer
|
||||
#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer
|
||||
#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count
|
||||
// timer
|
||||
#define TIMER_CFG_RTC 0x01000000 // Full-width RTC timer
|
||||
#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers
|
||||
#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer
|
||||
#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer
|
||||
#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer
|
||||
#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer
|
||||
#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter
|
||||
#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter
|
||||
#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer
|
||||
#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer
|
||||
#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output
|
||||
#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer
|
||||
#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer
|
||||
#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer
|
||||
#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer
|
||||
#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter
|
||||
#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter
|
||||
#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer
|
||||
#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer
|
||||
#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to TimerIntEnable, TimerIntDisable, and
|
||||
// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt
|
||||
#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt
|
||||
#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt
|
||||
#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt
|
||||
#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt
|
||||
#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask
|
||||
#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt
|
||||
#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt
|
||||
#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to TimerControlEvent as the ulEvent parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges
|
||||
#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges
|
||||
#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to most of the timer APIs as the ulTimer
|
||||
// parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_A 0x000000ff // Timer A
|
||||
#define TIMER_B 0x0000ff00 // Timer B
|
||||
#define TIMER_BOTH 0x0000ffff // Timer Both
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to TimerSynchronize as the ulTimers parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A
|
||||
#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B
|
||||
#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A
|
||||
#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B
|
||||
#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A
|
||||
#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B
|
||||
#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A
|
||||
#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B
|
||||
#define TIMER_4A_SYNC 0x00000100 // Synchronize Timer 4A
|
||||
#define TIMER_4B_SYNC 0x00000200 // Synchronize Timer 4B
|
||||
#define TIMER_5A_SYNC 0x00000400 // Synchronize Timer 5A
|
||||
#define TIMER_5B_SYNC 0x00000800 // Synchronize Timer 5B
|
||||
#define WTIMER_0A_SYNC 0x00001000 // Synchronize Wide Timer 0A
|
||||
#define WTIMER_0B_SYNC 0x00002000 // Synchronize Wide Timer 0B
|
||||
#define WTIMER_1A_SYNC 0x00004000 // Synchronize Wide Timer 1A
|
||||
#define WTIMER_1B_SYNC 0x00008000 // Synchronize Wide Timer 1B
|
||||
#define WTIMER_2A_SYNC 0x00010000 // Synchronize Wide Timer 2A
|
||||
#define WTIMER_2B_SYNC 0x00020000 // Synchronize Wide Timer 2B
|
||||
#define WTIMER_3A_SYNC 0x00040000 // Synchronize Wide Timer 3A
|
||||
#define WTIMER_3B_SYNC 0x00080000 // Synchronize Wide Timer 3B
|
||||
#define WTIMER_4A_SYNC 0x00100000 // Synchronize Wide Timer 4A
|
||||
#define WTIMER_4B_SYNC 0x00200000 // Synchronize Wide Timer 4B
|
||||
#define WTIMER_5A_SYNC 0x00400000 // Synchronize Wide Timer 5A
|
||||
#define WTIMER_5B_SYNC 0x00800000 // Synchronize Wide Timer 5B
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);
|
||||
extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);
|
||||
extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);
|
||||
extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
|
||||
tBoolean bInvert);
|
||||
extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,
|
||||
tBoolean bEnable);
|
||||
extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
|
||||
unsigned long ulEvent);
|
||||
extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
|
||||
tBoolean bStall);
|
||||
extern void TimerControlWaitOnTrigger(unsigned long ulBase,
|
||||
unsigned long ulTimer,
|
||||
tBoolean bWait);
|
||||
extern void TimerRTCEnable(unsigned long ulBase);
|
||||
extern void TimerRTCDisable(unsigned long ulBase);
|
||||
extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
|
||||
unsigned long ulValue);
|
||||
extern unsigned long TimerPrescaleGet(unsigned long ulBase,
|
||||
unsigned long ulTimer);
|
||||
extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,
|
||||
unsigned long ulValue);
|
||||
extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,
|
||||
unsigned long ulTimer);
|
||||
extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
|
||||
unsigned long ulValue);
|
||||
extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);
|
||||
extern void TimerLoadSet64(unsigned long ulBase, unsigned long long ullValue);
|
||||
extern unsigned long long TimerLoadGet64(unsigned long ulBase);
|
||||
extern unsigned long TimerValueGet(unsigned long ulBase,
|
||||
unsigned long ulTimer);
|
||||
extern unsigned long long TimerValueGet64(unsigned long ulBase);
|
||||
extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
|
||||
unsigned long ulValue);
|
||||
extern unsigned long TimerMatchGet(unsigned long ulBase,
|
||||
unsigned long ulTimer);
|
||||
extern void TimerMatchSet64(unsigned long ulBase, unsigned long long ullValue);
|
||||
extern unsigned long long TimerMatchGet64(unsigned long ulBase);
|
||||
extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
|
||||
void (*pfnHandler)(void));
|
||||
extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);
|
||||
extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
|
||||
extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
|
||||
extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);
|
||||
extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);
|
||||
extern void TimerSynchronize(unsigned long ulBase, unsigned long ulTimers);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// TimerQuiesce() has been deprecated. SysCtlPeripheralReset() should be used
|
||||
// instead to return the timer to its reset state.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
extern void TimerQuiesce(unsigned long ulBase);
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// These values for TimerConfigure have been deprecated.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
#define TIMER_CFG_32_BIT_OS 0x00000021 // 32-bit one-shot timer
|
||||
#define TIMER_CFG_32_BIT_OS_UP 0x00000031 // 32-bit one-shot up-count timer
|
||||
#define TIMER_CFG_32_BIT_PER 0x00000022 // 32-bit periodic timer
|
||||
#define TIMER_CFG_32_BIT_PER_UP 0x00000032 // 32-bit periodic up-count timer
|
||||
#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer
|
||||
#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __TIMER_H__
|
||||
//*****************************************************************************
|
||||
//
|
||||
// timer.h - Prototypes for the timer module
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __TIMER_H__
|
||||
#define __TIMER_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to TimerConfigure as the ulConfig parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer
|
||||
#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count
|
||||
// timer
|
||||
#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer
|
||||
#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count
|
||||
// timer
|
||||
#define TIMER_CFG_RTC 0x01000000 // Full-width RTC timer
|
||||
#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers
|
||||
#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer
|
||||
#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer
|
||||
#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer
|
||||
#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer
|
||||
#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter
|
||||
#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter
|
||||
#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer
|
||||
#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer
|
||||
#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output
|
||||
#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer
|
||||
#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer
|
||||
#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer
|
||||
#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer
|
||||
#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter
|
||||
#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter
|
||||
#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer
|
||||
#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer
|
||||
#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to TimerIntEnable, TimerIntDisable, and
|
||||
// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt
|
||||
#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt
|
||||
#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt
|
||||
#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt
|
||||
#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt
|
||||
#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask
|
||||
#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt
|
||||
#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt
|
||||
#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to TimerControlEvent as the ulEvent parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges
|
||||
#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges
|
||||
#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to most of the timer APIs as the ulTimer
|
||||
// parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_A 0x000000ff // Timer A
|
||||
#define TIMER_B 0x0000ff00 // Timer B
|
||||
#define TIMER_BOTH 0x0000ffff // Timer Both
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to TimerSynchronize as the ulTimers parameter.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A
|
||||
#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B
|
||||
#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A
|
||||
#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B
|
||||
#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A
|
||||
#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B
|
||||
#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A
|
||||
#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B
|
||||
#define TIMER_4A_SYNC 0x00000100 // Synchronize Timer 4A
|
||||
#define TIMER_4B_SYNC 0x00000200 // Synchronize Timer 4B
|
||||
#define TIMER_5A_SYNC 0x00000400 // Synchronize Timer 5A
|
||||
#define TIMER_5B_SYNC 0x00000800 // Synchronize Timer 5B
|
||||
#define WTIMER_0A_SYNC 0x00001000 // Synchronize Wide Timer 0A
|
||||
#define WTIMER_0B_SYNC 0x00002000 // Synchronize Wide Timer 0B
|
||||
#define WTIMER_1A_SYNC 0x00004000 // Synchronize Wide Timer 1A
|
||||
#define WTIMER_1B_SYNC 0x00008000 // Synchronize Wide Timer 1B
|
||||
#define WTIMER_2A_SYNC 0x00010000 // Synchronize Wide Timer 2A
|
||||
#define WTIMER_2B_SYNC 0x00020000 // Synchronize Wide Timer 2B
|
||||
#define WTIMER_3A_SYNC 0x00040000 // Synchronize Wide Timer 3A
|
||||
#define WTIMER_3B_SYNC 0x00080000 // Synchronize Wide Timer 3B
|
||||
#define WTIMER_4A_SYNC 0x00100000 // Synchronize Wide Timer 4A
|
||||
#define WTIMER_4B_SYNC 0x00200000 // Synchronize Wide Timer 4B
|
||||
#define WTIMER_5A_SYNC 0x00400000 // Synchronize Wide Timer 5A
|
||||
#define WTIMER_5B_SYNC 0x00800000 // Synchronize Wide Timer 5B
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);
|
||||
extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);
|
||||
extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);
|
||||
extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
|
||||
tBoolean bInvert);
|
||||
extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer,
|
||||
tBoolean bEnable);
|
||||
extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
|
||||
unsigned long ulEvent);
|
||||
extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
|
||||
tBoolean bStall);
|
||||
extern void TimerControlWaitOnTrigger(unsigned long ulBase,
|
||||
unsigned long ulTimer,
|
||||
tBoolean bWait);
|
||||
extern void TimerRTCEnable(unsigned long ulBase);
|
||||
extern void TimerRTCDisable(unsigned long ulBase);
|
||||
extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
|
||||
unsigned long ulValue);
|
||||
extern unsigned long TimerPrescaleGet(unsigned long ulBase,
|
||||
unsigned long ulTimer);
|
||||
extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,
|
||||
unsigned long ulValue);
|
||||
extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,
|
||||
unsigned long ulTimer);
|
||||
extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
|
||||
unsigned long ulValue);
|
||||
extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);
|
||||
extern void TimerLoadSet64(unsigned long ulBase, unsigned long long ullValue);
|
||||
extern unsigned long long TimerLoadGet64(unsigned long ulBase);
|
||||
extern unsigned long TimerValueGet(unsigned long ulBase,
|
||||
unsigned long ulTimer);
|
||||
extern unsigned long long TimerValueGet64(unsigned long ulBase);
|
||||
extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
|
||||
unsigned long ulValue);
|
||||
extern unsigned long TimerMatchGet(unsigned long ulBase,
|
||||
unsigned long ulTimer);
|
||||
extern void TimerMatchSet64(unsigned long ulBase, unsigned long long ullValue);
|
||||
extern unsigned long long TimerMatchGet64(unsigned long ulBase);
|
||||
extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
|
||||
void (*pfnHandler)(void));
|
||||
extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);
|
||||
extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
|
||||
extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
|
||||
extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);
|
||||
extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);
|
||||
extern void TimerSynchronize(unsigned long ulBase, unsigned long ulTimers);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// TimerQuiesce() has been deprecated. SysCtlPeripheralReset() should be used
|
||||
// instead to return the timer to its reset state.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
extern void TimerQuiesce(unsigned long ulBase);
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// These values for TimerConfigure have been deprecated.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
#define TIMER_CFG_32_BIT_OS 0x00000021 // 32-bit one-shot timer
|
||||
#define TIMER_CFG_32_BIT_OS_UP 0x00000031 // 32-bit one-shot up-count timer
|
||||
#define TIMER_CFG_32_BIT_PER 0x00000022 // 32-bit periodic timer
|
||||
#define TIMER_CFG_32_BIT_PER_UP 0x00000032 // 32-bit periodic up-count timer
|
||||
#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer
|
||||
#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __TIMER_H__
|
||||
|
||||
@ -1,275 +1,275 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// uart.h - Defines and Macros for the UART.
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __UART_H__
|
||||
#define __UART_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear
|
||||
// as the ulIntFlags parameter, and returned from UARTIntStatus.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_INT_9BIT 0x1000 // 9-bit address match interrupt
|
||||
#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask
|
||||
#define UART_INT_BE 0x200 // Break Error Interrupt Mask
|
||||
#define UART_INT_PE 0x100 // Parity Error Interrupt Mask
|
||||
#define UART_INT_FE 0x080 // Framing Error Interrupt Mask
|
||||
#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask
|
||||
#define UART_INT_TX 0x020 // Transmit Interrupt Mask
|
||||
#define UART_INT_RX 0x010 // Receive Interrupt Mask
|
||||
#define UART_INT_DSR 0x008 // DSR Modem Interrupt Mask
|
||||
#define UART_INT_DCD 0x004 // DCD Modem Interrupt Mask
|
||||
#define UART_INT_CTS 0x002 // CTS Modem Interrupt Mask
|
||||
#define UART_INT_RI 0x001 // RI Modem Interrupt Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter
|
||||
// and returned by UARTConfigGetExpClk in the pulConfig parameter.
|
||||
// Additionally, the UART_CONFIG_PAR_* subset can be passed to
|
||||
// UARTParityModeSet as the ulParity parameter, and are returned by
|
||||
// UARTParityModeGet.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length
|
||||
#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data
|
||||
#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data
|
||||
#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data
|
||||
#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data
|
||||
#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits
|
||||
#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit
|
||||
#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits
|
||||
#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity
|
||||
#define UART_CONFIG_PAR_NONE 0x00000000 // No parity
|
||||
#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity
|
||||
#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity
|
||||
#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one
|
||||
#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and
|
||||
// returned by UARTFIFOLevelGet in the pulTxLevel.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full
|
||||
#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full
|
||||
#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full
|
||||
#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full
|
||||
#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and
|
||||
// returned by UARTFIFOLevelGet in the pulRxLevel.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full
|
||||
#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full
|
||||
#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full
|
||||
#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full
|
||||
#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTDMAEnable() and UARTDMADisable().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error
|
||||
#define UART_DMA_TX 0x00000002 // Enable DMA for transmit
|
||||
#define UART_DMA_RX 0x00000001 // Enable DMA for receive
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values returned from UARTRxErrorGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_RXERROR_OVERRUN 0x00000008
|
||||
#define UART_RXERROR_BREAK 0x00000004
|
||||
#define UART_RXERROR_PARITY 0x00000002
|
||||
#define UART_RXERROR_FRAMING 0x00000001
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTHandshakeOutputsSet() or returned from
|
||||
// UARTHandshakeOutputGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_OUTPUT_RTS 0x00000800
|
||||
#define UART_OUTPUT_DTR 0x00000400
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be returned from UARTHandshakeInputsGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_INPUT_RI 0x00000100
|
||||
#define UART_INPUT_DCD 0x00000004
|
||||
#define UART_INPUT_DSR 0x00000002
|
||||
#define UART_INPUT_CTS 0x00000001
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTFlowControl() or returned from
|
||||
// UARTFlowControlGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_FLOWCONTROL_TX 0x00008000
|
||||
#define UART_FLOWCONTROL_RX 0x00004000
|
||||
#define UART_FLOWCONTROL_NONE 0x00000000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTTxIntModeSet() or returned from
|
||||
// UARTTxIntModeGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_TXINT_MODE_FIFO 0x00000000
|
||||
#define UART_TXINT_MODE_EOT 0x00000010
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTClockSourceSet() or returned from
|
||||
// UARTClockSourceGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_CLOCK_SYSTEM 0x00000000
|
||||
#define UART_CLOCK_PIOSC 0x00000005
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// API Function prototypes
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);
|
||||
extern unsigned long UARTParityModeGet(unsigned long ulBase);
|
||||
extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
|
||||
unsigned long ulRxLevel);
|
||||
extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
|
||||
unsigned long *pulRxLevel);
|
||||
extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
|
||||
unsigned long ulBaud, unsigned long ulConfig);
|
||||
extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
|
||||
unsigned long *pulBaud,
|
||||
unsigned long *pulConfig);
|
||||
extern void UARTEnable(unsigned long ulBase);
|
||||
extern void UARTDisable(unsigned long ulBase);
|
||||
extern void UARTFIFOEnable(unsigned long ulBase);
|
||||
extern void UARTFIFODisable(unsigned long ulBase);
|
||||
extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower);
|
||||
extern void UARTDisableSIR(unsigned long ulBase);
|
||||
extern tBoolean UARTCharsAvail(unsigned long ulBase);
|
||||
extern tBoolean UARTSpaceAvail(unsigned long ulBase);
|
||||
extern long UARTCharGetNonBlocking(unsigned long ulBase);
|
||||
extern long UARTCharGet(unsigned long ulBase);
|
||||
extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase,
|
||||
unsigned char ucData);
|
||||
extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);
|
||||
extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);
|
||||
extern tBoolean UARTBusy(unsigned long ulBase);
|
||||
extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
|
||||
extern void UARTIntUnregister(unsigned long ulBase);
|
||||
extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
|
||||
extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
|
||||
extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);
|
||||
extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);
|
||||
extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
|
||||
extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
|
||||
extern unsigned long UARTRxErrorGet(unsigned long ulBase);
|
||||
extern void UARTRxErrorClear(unsigned long ulBase);
|
||||
extern void UARTSmartCardEnable(unsigned long ulBase);
|
||||
extern void UARTSmartCardDisable(unsigned long ulBase);
|
||||
extern void UARTModemControlSet(unsigned long ulBase,
|
||||
unsigned long ulControl);
|
||||
extern void UARTModemControlClear(unsigned long ulBase,
|
||||
unsigned long ulControl);
|
||||
extern unsigned long UARTModemControlGet(unsigned long ulBase);
|
||||
extern unsigned long UARTModemStatusGet(unsigned long ulBase);
|
||||
extern void UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode);
|
||||
extern unsigned long UARTFlowControlGet(unsigned long ulBase);
|
||||
extern void UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode);
|
||||
extern unsigned long UARTTxIntModeGet(unsigned long ulBase);
|
||||
extern void UARTClockSourceSet(unsigned long ulBase, unsigned long ulSource);
|
||||
extern unsigned long UARTClockSourceGet(unsigned long ulBase);
|
||||
extern void UART9BitEnable(unsigned long ulBase);
|
||||
extern void UART9BitDisable(unsigned long ulBase);
|
||||
extern void UART9BitAddrSet(unsigned long ulBase, unsigned char ucAddr,
|
||||
unsigned char ucMask);
|
||||
extern void UART9BitAddrSend(unsigned long ulBase, unsigned char ucAddr);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Several UART APIs have been renamed, with the original function name being
|
||||
// deprecated. These defines provide backward compatibility.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
#include "sysctl.h"
|
||||
#define UARTConfigSet(a, b, c) \
|
||||
UARTConfigSetExpClk(a, SysCtlClockGet(), b, c)
|
||||
#define UARTConfigGet(a, b, c) \
|
||||
UARTConfigGetExpClk(a, SysCtlClockGet(), b, c)
|
||||
#define UARTCharNonBlockingGet(a) \
|
||||
UARTCharGetNonBlocking(a)
|
||||
#define UARTCharNonBlockingPut(a, b) \
|
||||
UARTCharPutNonBlocking(a, b)
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __UART_H__
|
||||
//*****************************************************************************
|
||||
//
|
||||
// uart.h - Defines and Macros for the UART.
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __UART_H__
|
||||
#define __UART_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear
|
||||
// as the ulIntFlags parameter, and returned from UARTIntStatus.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_INT_9BIT 0x1000 // 9-bit address match interrupt
|
||||
#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask
|
||||
#define UART_INT_BE 0x200 // Break Error Interrupt Mask
|
||||
#define UART_INT_PE 0x100 // Parity Error Interrupt Mask
|
||||
#define UART_INT_FE 0x080 // Framing Error Interrupt Mask
|
||||
#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask
|
||||
#define UART_INT_TX 0x020 // Transmit Interrupt Mask
|
||||
#define UART_INT_RX 0x010 // Receive Interrupt Mask
|
||||
#define UART_INT_DSR 0x008 // DSR Modem Interrupt Mask
|
||||
#define UART_INT_DCD 0x004 // DCD Modem Interrupt Mask
|
||||
#define UART_INT_CTS 0x002 // CTS Modem Interrupt Mask
|
||||
#define UART_INT_RI 0x001 // RI Modem Interrupt Mask
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter
|
||||
// and returned by UARTConfigGetExpClk in the pulConfig parameter.
|
||||
// Additionally, the UART_CONFIG_PAR_* subset can be passed to
|
||||
// UARTParityModeSet as the ulParity parameter, and are returned by
|
||||
// UARTParityModeGet.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length
|
||||
#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data
|
||||
#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data
|
||||
#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data
|
||||
#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data
|
||||
#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits
|
||||
#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit
|
||||
#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits
|
||||
#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity
|
||||
#define UART_CONFIG_PAR_NONE 0x00000000 // No parity
|
||||
#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity
|
||||
#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity
|
||||
#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one
|
||||
#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and
|
||||
// returned by UARTFIFOLevelGet in the pulTxLevel.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full
|
||||
#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full
|
||||
#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full
|
||||
#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full
|
||||
#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and
|
||||
// returned by UARTFIFOLevelGet in the pulRxLevel.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full
|
||||
#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full
|
||||
#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full
|
||||
#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full
|
||||
#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTDMAEnable() and UARTDMADisable().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error
|
||||
#define UART_DMA_TX 0x00000002 // Enable DMA for transmit
|
||||
#define UART_DMA_RX 0x00000001 // Enable DMA for receive
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values returned from UARTRxErrorGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_RXERROR_OVERRUN 0x00000008
|
||||
#define UART_RXERROR_BREAK 0x00000004
|
||||
#define UART_RXERROR_PARITY 0x00000002
|
||||
#define UART_RXERROR_FRAMING 0x00000001
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTHandshakeOutputsSet() or returned from
|
||||
// UARTHandshakeOutputGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_OUTPUT_RTS 0x00000800
|
||||
#define UART_OUTPUT_DTR 0x00000400
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be returned from UARTHandshakeInputsGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_INPUT_RI 0x00000100
|
||||
#define UART_INPUT_DCD 0x00000004
|
||||
#define UART_INPUT_DSR 0x00000002
|
||||
#define UART_INPUT_CTS 0x00000001
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTFlowControl() or returned from
|
||||
// UARTFlowControlGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_FLOWCONTROL_TX 0x00008000
|
||||
#define UART_FLOWCONTROL_RX 0x00004000
|
||||
#define UART_FLOWCONTROL_NONE 0x00000000
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTTxIntModeSet() or returned from
|
||||
// UARTTxIntModeGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_TXINT_MODE_FIFO 0x00000000
|
||||
#define UART_TXINT_MODE_EOT 0x00000010
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Values that can be passed to UARTClockSourceSet() or returned from
|
||||
// UARTClockSourceGet().
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define UART_CLOCK_SYSTEM 0x00000000
|
||||
#define UART_CLOCK_PIOSC 0x00000005
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// API Function prototypes
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);
|
||||
extern unsigned long UARTParityModeGet(unsigned long ulBase);
|
||||
extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
|
||||
unsigned long ulRxLevel);
|
||||
extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
|
||||
unsigned long *pulRxLevel);
|
||||
extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
|
||||
unsigned long ulBaud, unsigned long ulConfig);
|
||||
extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
|
||||
unsigned long *pulBaud,
|
||||
unsigned long *pulConfig);
|
||||
extern void UARTEnable(unsigned long ulBase);
|
||||
extern void UARTDisable(unsigned long ulBase);
|
||||
extern void UARTFIFOEnable(unsigned long ulBase);
|
||||
extern void UARTFIFODisable(unsigned long ulBase);
|
||||
extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower);
|
||||
extern void UARTDisableSIR(unsigned long ulBase);
|
||||
extern tBoolean UARTCharsAvail(unsigned long ulBase);
|
||||
extern tBoolean UARTSpaceAvail(unsigned long ulBase);
|
||||
extern long UARTCharGetNonBlocking(unsigned long ulBase);
|
||||
extern long UARTCharGet(unsigned long ulBase);
|
||||
extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase,
|
||||
unsigned char ucData);
|
||||
extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);
|
||||
extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);
|
||||
extern tBoolean UARTBusy(unsigned long ulBase);
|
||||
extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
|
||||
extern void UARTIntUnregister(unsigned long ulBase);
|
||||
extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
|
||||
extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
|
||||
extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);
|
||||
extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);
|
||||
extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
|
||||
extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
|
||||
extern unsigned long UARTRxErrorGet(unsigned long ulBase);
|
||||
extern void UARTRxErrorClear(unsigned long ulBase);
|
||||
extern void UARTSmartCardEnable(unsigned long ulBase);
|
||||
extern void UARTSmartCardDisable(unsigned long ulBase);
|
||||
extern void UARTModemControlSet(unsigned long ulBase,
|
||||
unsigned long ulControl);
|
||||
extern void UARTModemControlClear(unsigned long ulBase,
|
||||
unsigned long ulControl);
|
||||
extern unsigned long UARTModemControlGet(unsigned long ulBase);
|
||||
extern unsigned long UARTModemStatusGet(unsigned long ulBase);
|
||||
extern void UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode);
|
||||
extern unsigned long UARTFlowControlGet(unsigned long ulBase);
|
||||
extern void UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode);
|
||||
extern unsigned long UARTTxIntModeGet(unsigned long ulBase);
|
||||
extern void UARTClockSourceSet(unsigned long ulBase, unsigned long ulSource);
|
||||
extern unsigned long UARTClockSourceGet(unsigned long ulBase);
|
||||
extern void UART9BitEnable(unsigned long ulBase);
|
||||
extern void UART9BitDisable(unsigned long ulBase);
|
||||
extern void UART9BitAddrSet(unsigned long ulBase, unsigned char ucAddr,
|
||||
unsigned char ucMask);
|
||||
extern void UART9BitAddrSend(unsigned long ulBase, unsigned char ucAddr);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Several UART APIs have been renamed, with the original function name being
|
||||
// deprecated. These defines provide backward compatibility.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifndef DEPRECATED
|
||||
#include "sysctl.h"
|
||||
#define UARTConfigSet(a, b, c) \
|
||||
UARTConfigSetExpClk(a, SysCtlClockGet(), b, c)
|
||||
#define UARTConfigGet(a, b, c) \
|
||||
UARTConfigGetExpClk(a, SysCtlClockGet(), b, c)
|
||||
#define UARTCharNonBlockingGet(a) \
|
||||
UARTCharGetNonBlocking(a)
|
||||
#define UARTCharNonBlockingPut(a, b) \
|
||||
UARTCharPutNonBlocking(a, b)
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __UART_H__
|
||||
|
||||
@ -1,95 +1,95 @@
|
||||
//*****************************************************************************
|
||||
//
|
||||
// watchdog.h - Prototypes for the Watchdog Timer API
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __WATCHDOG_H__
|
||||
#define __WATCHDOG_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The type of interrupt that can be generated by the watchdog.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WATCHDOG_INT_TYPE_INT 0x00000000
|
||||
#define WATCHDOG_INT_TYPE_NMI 0x00000004
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern tBoolean WatchdogRunning(unsigned long ulBase);
|
||||
extern void WatchdogEnable(unsigned long ulBase);
|
||||
extern void WatchdogResetEnable(unsigned long ulBase);
|
||||
extern void WatchdogResetDisable(unsigned long ulBase);
|
||||
extern void WatchdogLock(unsigned long ulBase);
|
||||
extern void WatchdogUnlock(unsigned long ulBase);
|
||||
extern tBoolean WatchdogLockState(unsigned long ulBase);
|
||||
extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal);
|
||||
extern unsigned long WatchdogReloadGet(unsigned long ulBase);
|
||||
extern unsigned long WatchdogValueGet(unsigned long ulBase);
|
||||
extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
|
||||
extern void WatchdogIntUnregister(unsigned long ulBase);
|
||||
extern void WatchdogIntEnable(unsigned long ulBase);
|
||||
extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);
|
||||
extern void WatchdogIntClear(unsigned long ulBase);
|
||||
extern void WatchdogIntTypeSet(unsigned long ulBase, unsigned long ulType);
|
||||
extern void WatchdogStallEnable(unsigned long ulBase);
|
||||
extern void WatchdogStallDisable(unsigned long ulBase);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __WATCHDOG_H__
|
||||
//*****************************************************************************
|
||||
//
|
||||
// watchdog.h - Prototypes for the Watchdog Timer API
|
||||
//
|
||||
// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
|
||||
// Software License Agreement
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions
|
||||
// are met:
|
||||
//
|
||||
// Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
//
|
||||
// Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
//
|
||||
// Neither the name of Texas Instruments Incorporated nor the names of
|
||||
// its contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// This is part of revision 9453 of the Stellaris Peripheral Driver Library.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
#ifndef __WATCHDOG_H__
|
||||
#define __WATCHDOG_H__
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// If building with a C++ compiler, make all of the definitions in this header
|
||||
// have a C binding.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// The type of interrupt that can be generated by the watchdog.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#define WATCHDOG_INT_TYPE_INT 0x00000000
|
||||
#define WATCHDOG_INT_TYPE_NMI 0x00000004
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Prototypes for the APIs.
|
||||
//
|
||||
//*****************************************************************************
|
||||
extern tBoolean WatchdogRunning(unsigned long ulBase);
|
||||
extern void WatchdogEnable(unsigned long ulBase);
|
||||
extern void WatchdogResetEnable(unsigned long ulBase);
|
||||
extern void WatchdogResetDisable(unsigned long ulBase);
|
||||
extern void WatchdogLock(unsigned long ulBase);
|
||||
extern void WatchdogUnlock(unsigned long ulBase);
|
||||
extern tBoolean WatchdogLockState(unsigned long ulBase);
|
||||
extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal);
|
||||
extern unsigned long WatchdogReloadGet(unsigned long ulBase);
|
||||
extern unsigned long WatchdogValueGet(unsigned long ulBase);
|
||||
extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
|
||||
extern void WatchdogIntUnregister(unsigned long ulBase);
|
||||
extern void WatchdogIntEnable(unsigned long ulBase);
|
||||
extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);
|
||||
extern void WatchdogIntClear(unsigned long ulBase);
|
||||
extern void WatchdogIntTypeSet(unsigned long ulBase, unsigned long ulType);
|
||||
extern void WatchdogStallEnable(unsigned long ulBase);
|
||||
extern void WatchdogStallDisable(unsigned long ulBase);
|
||||
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Mark the end of the C bindings section for C++ compilers.
|
||||
//
|
||||
//*****************************************************************************
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __WATCHDOG_H__
|
||||
|
||||
Loading…
Reference in New Issue
Block a user