diff --git a/cpu/sam0_common/periph/pwm.c b/cpu/sam0_common/periph/pwm.c
index eb707776cd..a521bc3b34 100644
--- a/cpu/sam0_common/periph/pwm.c
+++ b/cpu/sam0_common/periph/pwm.c
@@ -205,7 +205,7 @@ static void poweroff(pwm_t dev)
     *cfg->tim.mclk &= ~cfg->tim.mclk_mask;
 #else
     PM->APBCMASK.reg &= ~cfg->tim.pm_mask;
-    GCLK->CLKCTRL.reg = GCLK_CLKCTRL_GEN_GCLK7
+    GCLK->CLKCTRL.reg = GCLK_CLKCTRL_GEN(SAM0_GCLK_DISABLED)
                       | GCLK_CLKCTRL_ID(cfg->tim.gclk_id);
 #endif
 }
diff --git a/cpu/samd21/cpu.c b/cpu/samd21/cpu.c
index 383584f7b6..17151d9780 100644
--- a/cpu/samd21/cpu.c
+++ b/cpu/samd21/cpu.c
@@ -252,8 +252,8 @@ static void clk_init(void)
 #endif
 
     /* redirect all peripherals to a disabled clock generator (7) by default */
-    for (int i = 0x3; i <= 0x22; i++) {
-        GCLK->CLKCTRL.reg = ( GCLK_CLKCTRL_ID(i) | GCLK_CLKCTRL_GEN_GCLK7 );
+    for (unsigned i = 0x3; i <= GCLK_CLKCTRL_ID_Msk; i++) {
+        GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(i) | GCLK_CLKCTRL_GEN(SAM0_GCLK_DISABLED);
         while (GCLK->STATUS.bit.SYNCBUSY) {}
     }
 }
diff --git a/cpu/samd21/include/periph_cpu.h b/cpu/samd21/include/periph_cpu.h
index 08abcbd8e5..cd1c76d1b1 100644
--- a/cpu/samd21/include/periph_cpu.h
+++ b/cpu/samd21/include/periph_cpu.h
@@ -60,6 +60,7 @@ enum {
     SAM0_GCLK_1MHZ,                     /**< 1 MHz clock for xTimer */
     SAM0_GCLK_32KHZ,                    /**< 32 kHz clock           */
     SAM0_GCLK_1KHZ,                     /**< 1 kHz clock            */
+    SAM0_GCLK_DISABLED = 0xF,           /**< disabled GCLK          */
 };
 /** @} */