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boards/common/gd32v: add USB OTG support

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This commit is contained in:
Gunar Schorcht 2023-02-07 00:55:44 +01:00
parent 7e0d1df9c3
commit 5e913a3974
2 changed files with 70 additions and 0 deletions
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63
boards/common/gd32v/include/cfg_usbdev_default.h Normal file
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@ -0,0 +1,63 @@
/*
* Copyright (C) 2023 Gunar Schorcht <gunar@schorcht.net>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_gd32v
* @{
*
* @file
* @brief Default USB OTG configuration for GD32 RISC-V board
*
* @author Gunar Schorcht <gunar@schorcht.net>
*/
#ifndef CFG_USBDEV_DEFAULT_H
#define CFG_USBDEV_DEFAULT_H
#include "vendor/usbdev_gd32v.h"
#include "usbdev_synopsys_dwc2.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name USB OTG configuration
* @{
*/
/**
* @brief Enable the full speed USB OTG peripheral
*/
#define DWC2_USB_OTG_FS_ENABLED
/**
* @brief Common USB OTG FS configuration
*/
static const dwc2_usb_otg_fshs_config_t dwc2_usb_otg_fshs_config[] = {
{
.periph = USB_OTG_FS_PERIPH_BASE,
.type = DWC2_USB_OTG_FS,
.phy = DWC2_USB_OTG_PHY_BUILTIN,
.rcu_mask = RCU_AHBEN_USBFSEN_Msk,
.bus = AHB,
.irqn = USBFS_IRQn,
}
};
/**
* @brief Number of available USB OTG peripherals
*/
#define USBDEV_NUMOF ARRAY_SIZE(dwc2_usb_otg_fshs_config)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* CFG_USBDEV_DEFAULT_H */
/** @} */

7
boards/common/gd32v/include/periph_common_conf.h
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@ -28,7 +28,14 @@
extern "C" {
#endif
#if defined(MODULE_USBDEV_SYNOPSYS_DWC2) || defined(MODULE_TINYUSB_DEVICE)
/* If the USB OTG peripheral is used, the USB clock of 48 MHz is derived by
* dividing the PLL clock by 1, 1.5, 2, or 2.5. That is the maximum core clock
* frequency can be 96 MHz. */
#define CLOCK_CORECLOCK MHZ(96) /**< CPU clock frequency in Hz */
#else
#define CLOCK_CORECLOCK MHZ(108) /**< CPU clock frequency in Hz */
#endif
#define CLOCK_AHB CLOCK_CORECLOCK /**< Equal to the CPU clock */
#define CLOCK_APB1 CLOCK_AHB/2 /**< Half AHB clock */