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boards/stm32l0/l1: merge default clock configuration headers

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This commit is contained in:
Alexandre Abadie 2020-08-28 21:30:38 +02:00
parent 4bdb3db0f9
commit 5e886a76c9
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GPG Key ID: 1C919A403CAE1405
14 changed files with 30 additions and 175 deletions
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2
boards/b-l072z-lrwan1/include/periph_conf.h
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@ -25,7 +25,7 @@
#endif
#include "periph_cpu.h"
#include "l0/cfg_clock_default.h"
#include "l0l1/cfg_clock_default.h"
#include "cfg_rtt_default.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_timer_tim2.h"

27
boards/common/stm32/include/l0/cfg_clock_default.h → boards/common/stm32/include/l0l1/cfg_clock_default.h
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@ -11,13 +11,13 @@
* @{
*
* @file
* @brief Default STM32L0 clock configuration
* @brief Default STM32L0/STM32L1 clock configuration
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef L0_CFG_CLOCK_DEFAULT_H
#define L0_CFG_CLOCK_DEFAULT_H
#ifndef L0L1_CFG_CLOCK_DEFAULT_H
#define L0L1_CFG_CLOCK_DEFAULT_H
#include "periph_cpu.h"
@ -97,6 +97,10 @@ extern "C" {
#define CLOCK_HSI MHZ(16)
#ifndef CONFIG_CLOCK_MSI
#define CONFIG_CLOCK_MSI KHZ(4194)
#endif
#if CONFIG_USE_CLOCK_HSI
#define CLOCK_CORECLOCK (CLOCK_HSI)
@ -107,9 +111,6 @@ extern "C" {
#define CLOCK_CORECLOCK (CLOCK_HSE)
#elif CONFIG_USE_CLOCK_MSI
#ifndef CONFIG_CLOCK_MSI
#define CONFIG_CLOCK_MSI KHZ(4194)
#endif
#define CLOCK_CORECLOCK (CONFIG_CLOCK_MSI)
#elif CONFIG_USE_CLOCK_PLL
@ -127,8 +128,16 @@ extern "C" {
#define CLOCK_PLL_SRC (CLOCK_HSE)
#else /* CLOCK_HSI */
#define CLOCK_PLL_SRC (CLOCK_HSI)
#endif
#endif /* CONFIG_BOARD_HAS_HSE */
/* PLL configuration: make sure your values are legit!
*
* compute by: CORECLOCK = ((PLL_IN / PLL_PREDIV) * PLL_MUL)
* with:
* PLL_IN: input clock is HSE if available or HSI otherwise
* PLL_DIV : divider, allowed values: 2, 3, 4
* PLL_MUL: multiplier, allowed values: 3, 4, 6, 8, 12, 16, 24, 32, 48
* CORECLOCK -> 48MHz MAX!
*/
#define CLOCK_CORECLOCK ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_DIV) * CONFIG_CLOCK_PLL_MUL)
#if CLOCK_CORECLOCK > MHZ(32)
#error "SYSCLK cannot exceed 32MHz"
@ -144,12 +153,12 @@ extern "C" {
#ifndef CONFIG_CLOCK_APB2_DIV
#define CONFIG_CLOCK_APB2_DIV (1)
#endif
#define CLOCK_APB2 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB2_DIV) /* max: 32MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB2_DIV) /* max: 32MHz */
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* L0_CFG_CLOCK_DEFAULT_H */
#endif /* L0L1_CFG_CLOCK_DEFAULT_H */
/** @} */

154
boards/common/stm32/include/l1/cfg_clock_default.h
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@ -1,154 +0,0 @@
/*
* Copyright (C) 2020 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Default clock configuration for the STM32L1
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef L1_CFG_CLOCK_DEFAULT_H
#define L1_CFG_CLOCK_DEFAULT_H
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock system configuration
* @{
*/
/* Select the desired system clock source between PLL, HSE or HSI */
#ifndef CONFIG_USE_CLOCK_PLL
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \
IS_ACTIVE(CONFIG_USE_CLOCK_MSI)
#define CONFIG_USE_CLOCK_PLL (0)
#else
#define CONFIG_USE_CLOCK_PLL (1) /* Use PLL by default */
#endif
#endif /* CONFIG_USE_CLOCK_PLL */
#ifndef CONFIG_USE_CLOCK_MSI
#define CONFIG_USE_CLOCK_MSI (0)
#endif /* CONFIG_USE_CLOCK_MSI */
#ifndef CONFIG_USE_CLOCK_HSE
#define CONFIG_USE_CLOCK_HSE (0)
#endif /* CONFIG_USE_CLOCK_HSE */
#ifndef CONFIG_USE_CLOCK_HSI
#define CONFIG_USE_CLOCK_HSI (0)
#endif /* CONFIG_USE_CLOCK_HSI */
#if CONFIG_USE_CLOCK_PLL && \
(CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSE || CONFIG_USE_CLOCK_HSI)
#error "Cannot use PLL as clock source with other clock configurations"
#endif
#if CONFIG_USE_CLOCK_MSI && \
(CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_HSE || CONFIG_USE_CLOCK_HSI)
#error "Cannot use MSI as clock source with other clock configurations"
#endif
#if CONFIG_USE_CLOCK_HSE && \
(CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSI)
#error "Cannot use HSE as clock source with other clock configurations"
#endif
#if CONFIG_USE_CLOCK_HSI && \
(CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_MSI || CONFIG_USE_CLOCK_HSE)
#error "Cannot use HSI as clock source with other clock configurations"
#endif
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE (0)
#endif
#ifndef CLOCK_HSE
#define CLOCK_HSE MHZ(24)
#endif
#if CONFIG_BOARD_HAS_HSE && (CLOCK_HSE < MHZ(1) || CLOCK_HSE > MHZ(24))
#error "HSE clock frequency must be between 1MHz and 24MHz"
#endif
#ifndef CONFIG_CLOCK_HSI_USE_DIV4
#define CONFIG_CLOCK_HSI_USE_DIV4 (0)
#endif
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE (0)
#endif
#if CONFIG_BOARD_HAS_LSE
#define CLOCK_LSE (1)
#else
#define CLOCK_LSE (0)
#endif
#define CLOCK_HSI MHZ(16)
#if CONFIG_USE_CLOCK_HSI
#define CLOCK_CORECLOCK (CLOCK_HSI)
#elif CONFIG_USE_CLOCK_HSE
#if CONFIG_BOARD_HAS_HSE == 0
#error "The board doesn't provide an HSE oscillator"
#endif
#define CLOCK_CORECLOCK (CLOCK_HSE)
#elif CONFIG_USE_CLOCK_MSI
#ifndef CONFIG_CLOCK_MSI
#define CONFIG_CLOCK_MSI KHZ(4194)
#endif
#define CLOCK_CORECLOCK (CONFIG_CLOCK_MSI)
#elif CONFIG_USE_CLOCK_PLL
/* The following parameters configure a 64MHz system clock with HSI as input clock */
#ifndef CONFIG_CLOCK_PLL_DIV
#define CONFIG_CLOCK_PLL_DIV (2)
#endif
#ifndef CONFIG_CLOCK_PLL_MUL
#define CONFIG_CLOCK_PLL_MUL (4)
#endif
#if CONFIG_BOARD_HAS_HSE
#if CLOCK_HSE < MHZ(2)
#error "HSE must be greater than 2MHz when used as PLL input clock"
#endif
#define CLOCK_PLL_SRC (CLOCK_HSE)
#else /* CLOCK_HSI */
#define CLOCK_PLL_SRC (CLOCK_HSI)
#endif /* CONFIG_BOARD_HAS_HSE */
#define CLOCK_CORECLOCK ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_DIV) * CONFIG_CLOCK_PLL_MUL)
#if CLOCK_CORECLOCK > MHZ(32)
#error "SYSCLK cannot exceed 32MHz"
#endif
#endif /* CONFIG_USE_CLOCK_PLL */
#define CLOCK_AHB CLOCK_CORECLOCK /* max: 32MHz */
#ifndef CONFIG_CLOCK_APB1_DIV
#define CONFIG_CLOCK_APB1_DIV (1)
#endif
#define CLOCK_APB1 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV) /* max: 32MHz */
#ifndef CONFIG_CLOCK_APB2_DIV
#define CONFIG_CLOCK_APB2_DIV (1)
#endif
#define CLOCK_APB2 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB2_DIV) /* max: 32MHz */
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* L1_CFG_CLOCK_DEFAULT_H */
/** @} */

2
boards/i-nucleo-lrwan1/include/periph_conf.h
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@ -25,7 +25,7 @@
#endif
#include "periph_cpu.h"
#include "l0/cfg_clock_default.h"
#include "l0l1/cfg_clock_default.h"
#include "cfg_rtt_default.h"
#include "cfg_timer_tim2.h"

2
boards/im880b/include/periph_conf.h
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@ -27,7 +27,7 @@
#endif
#include "periph_cpu.h"
#include "l1/cfg_clock_default.h"
#include "l0l1/cfg_clock_default.h"
#ifdef __cplusplus
extern "C" {

2
boards/limifrog-v1/include/periph_conf.h
View File

@ -20,7 +20,7 @@
#define PERIPH_CONF_H
#include "periph_cpu.h"
#include "l1/cfg_clock_default.h"
#include "l0l1/cfg_clock_default.h"
#ifdef __cplusplus
extern "C" {

2
boards/lobaro-lorabox/include/periph_conf.h
View File

@ -32,7 +32,7 @@
#endif
#include "periph_cpu.h"
#include "l1/cfg_clock_default.h"
#include "l0l1/cfg_clock_default.h"
#include "cfg_timer_tim2.h"
#ifdef __cplusplus

2
boards/lsn50/include/periph_conf.h
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@ -25,7 +25,7 @@
#endif
#include "periph_cpu.h"
#include "l0/cfg_clock_default.h"
#include "l0l1/cfg_clock_default.h"
#include "cfg_rtt_default.h"
#include "cfg_timer_tim2.h"

2
boards/nucleo-l031k6/include/periph_conf.h
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@ -27,7 +27,7 @@
#endif
#include "periph_cpu.h"
#include "l0/cfg_clock_default.h"
#include "l0l1/cfg_clock_default.h"
#include "cfg_i2c1_pb6_pb7.h"
#include "cfg_rtt_default.h"
#include "cfg_timer_tim2.h"

2
boards/nucleo-l053r8/include/periph_conf.h
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@ -27,7 +27,7 @@
#endif
#include "periph_cpu.h"
#include "l0/cfg_clock_default.h"
#include "l0l1/cfg_clock_default.h"
#include "cfg_rtt_default.h"
#include "cfg_timer_tim2.h"

2
boards/nucleo-l073rz/include/periph_conf.h
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@ -27,7 +27,7 @@
#endif
#include "periph_cpu.h"
#include "l0/cfg_clock_default.h"
#include "l0l1/cfg_clock_default.h"
#include "cfg_rtt_default.h"
#include "cfg_timer_tim2.h"

2
boards/nucleo-l152re/include/periph_conf.h
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@ -21,7 +21,7 @@
#define PERIPH_CONF_H
#include "periph_cpu.h"
#include "l1/cfg_clock_default.h"
#include "l0l1/cfg_clock_default.h"
#include "cfg_timer_tim5.h"
#ifdef __cplusplus

2
boards/nz32-sc151/include/periph_conf.h
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@ -20,7 +20,7 @@
#define PERIPH_CONF_H
#include "periph_cpu.h"
#include "l1/cfg_clock_default.h"
#include "l0l1/cfg_clock_default.h"
#include "cfg_timer_tim5.h"
#ifdef __cplusplus

2
boards/stm32l0538-disco/include/periph_conf.h
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@ -20,7 +20,7 @@
#define PERIPH_CONF_H
#include "periph_cpu.h"
#include "l0/cfg_clock_default.h"
#include "l0l1/cfg_clock_default.h"
#ifdef __cplusplus
extern "C" {