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Merge pull request #17951 from maribu/makefiles/arch/riscv.inc.mk

build system: Fix compilation for RISC-V with newer GCC
This commit is contained in:
fabian18 2022-05-02 19:23:46 +02:00 committed by GitHub
commit 5db3ddd642
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@ -15,11 +15,14 @@
_TRIPLES_TO_TEST := \
riscv-none-embed \
riscv32-none-elf \
riscv-none-elf \
riscv32-unknown-elf \
riscv32-elf \
riscv-none-elf \
riscv-unknown-elf \
riscv-elf \
riscv64-none-elf \
riscv64-unknown-elf
riscv64-unknown-elf \
riscv64-elf
TARGET_ARCH_RISCV ?= \
$(strip \
@ -30,8 +33,28 @@ TARGET_ARCH_RISCV ?= \
TARGET_ARCH ?= $(TARGET_ARCH_RISCV)
# define build specific options
CFLAGS_CPU = -march=rv32imac -mabi=ilp32
ifeq (,$(TARGET_ARCH))
$(error No RISC-V toolchain detected. Make sure a RISC-V toolchain is installed.)
endif
ifeq ($(TOOLCHAIN),gnu)
NEW_RISCV_ISA := $(shell echo "" | $(TARGET_ARCH)-as -march=rv32imac_zicsr -mabi=ilp32 - > /dev/null 2>&1 && echo 1 || echo 0)
endif
NEW_RISCV_ISA ?= 0
# Since RISC-V ISA specifications 20191213 instructions previously included in
# rv32imac have been moved to the ZICSR extension. See
# https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf
#
# Select the march based on the ISA spec implemented by the used compiler:
ifeq (1,$(NEW_RISCV_ISA))
CFLAGS_CPU := -march=rv32imac_zicsr
else
CFLAGS_CPU := -march=rv32imac
endif
CFLAGS_CPU += -mabi=ilp32
ifeq ($(TOOLCHAIN),llvm)
# Always use riscv32-none-elf as target triple for clang, as some
# autodetected gcc target triples are incompatible with clang
@ -53,7 +76,7 @@ LINKFLAGS += -T$(LINKER_SCRIPT)
CFLAGS += $(CFLAGS_CPU) $(CFLAGS_DBG) $(CFLAGS_OPT) $(CFLAGS_LINK)
ASFLAGS += $(CFLAGS_CPU) $(CFLAGS_DBG)
# export linker flags
LINKFLAGS += $(CFLAGS_CPU) $(CFLAGS_LINK) $(CFLAGS_DBG) $(CFLAGS_OPT) -nostartfiles -Wl,--gc-sections -static -lgcc
LINKFLAGS += -march=rv32imac -mabi=ilp32 $(CFLAGS_LINK) $(CFLAGS_DBG) $(CFLAGS_OPT) -nostartfiles -Wl,--gc-sections -static -lgcc
# Platform triple as used by Rust
RUST_TARGET = riscv32imac-unknown-none-elf