cpu/nrf9160: add initial support

cpu/nrf5x_common/Makefile.features

@@ -1,18 +1,21 @@
 # Put defined MCU peripherals here (in alphabetical order)
 FEATURES_PROVIDED += periph_cpuid
-FEATURES_PROVIDED += periph_flashpage
-FEATURES_PROVIDED += periph_flashpage_pagewise
 FEATURES_PROVIDED += periph_gpio periph_gpio_irq
-FEATURES_PROVIDED += periph_hwrng
-FEATURES_PROVIDED += periph_temperature
 FEATURES_PROVIDED += periph_timer_periodic
-FEATURES_PROVIDED += periph_rtt_overflow
 FEATURES_PROVIDED += periph_uart_modecfg
-FEATURES_PROVIDED += periph_wdt periph_wdt_cb
+
+ifneq (nrf9160,$(CPU_MODEL))
+  FEATURES_PROVIDED += periph_flashpage
+  FEATURES_PROVIDED += periph_flashpage_pagewise
+  FEATURES_PROVIDED += periph_hwrng
+  FEATURES_PROVIDED += periph_rtt_overflow
+  FEATURES_PROVIDED += periph_temperature
+  FEATURES_PROVIDED += periph_wdt periph_wdt_cb
 
 # Various other features (if any)
-FEATURES_PROVIDED += ble_nimble
+  FEATURES_PROVIDED += ble_nimble
-FEATURES_PROVIDED += radio_nrfble
+  FEATURES_PROVIDED += radio_nrfble
-FEATURES_PROVIDED += radio_nrfmin
+  FEATURES_PROVIDED += radio_nrfmin
+endif
 
 include $(RIOTCPU)/cortexm_common/Makefile.features

cpu/nrf5x_common/clock.c

@@ -31,6 +31,15 @@
 #error "Clock init: CLOCK_LFCLK is not defined by your board!"
 #endif
 
+/* Add compatibility wrapper defines for nRF9160 */
+#ifdef NRF_CLOCK_S
+#define NRF_CLOCK NRF_CLOCK_S
+#endif
+
+#ifdef CLOCK_LFCLKSRC_SRC_LFRC
+#define CLOCK_LFCLKSRC_SRC_RC CLOCK_LFCLKSRC_SRC_LFRC
+#endif
+
 static unsigned _hfxo_requests = 0;
 
 void clock_init_hf(void)
@@ -89,6 +98,8 @@ void clock_start_lf(void)
     NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_Xtal);
 #elif (CLOCK_LFCLK == 2)
     NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_Synth);
+#elif (CLOCK_LFCLK == 3)
+    NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_LFXO);
 #else
 #error "LFCLK init: CLOCK_LFCLK has invalid value"
 #endif

cpu/nrf5x_common/include/periph_cpu_common.h

@@ -25,6 +25,12 @@
 extern "C" {
 #endif
 
+/**
+ * @brief   Compatibility wrapper for nRF9160
+ */
+#ifdef NRF_FICR_S
+#define NRF_FICR NRF_FICR_S
+#endif
 /**
  * @name    Power management configuration
  * @{
@@ -35,7 +41,11 @@ extern "C" {
 /**
  * @brief   Starting offset of CPU_ID
  */
+#ifdef FICR_INFO_DEVICEID_DEVICEID_Msk
+#define CPUID_ADDR          (&NRF_FICR->INFO.DEVICEID[0])
+#else
 #define CPUID_ADDR          (&NRF_FICR->DEVICEID[0])
+#endif
 /**
  * @brief   Length of the CPU_ID in octets
  */
@@ -143,6 +153,7 @@ typedef struct {
  * @brief   Override SPI mode values
  * @{
  */
+#ifndef CPU_FAM_NRF9160
 #define HAVE_SPI_MODE_T
 typedef enum {
     SPI_MODE_0 = 0,                                             /**< CPOL=0, CPHA=0 */
@@ -165,6 +176,7 @@ typedef enum {
     SPI_CLK_10MHZ  = SPI_FREQUENCY_FREQUENCY_M8     /**< 10MHz */
 } spi_clk_t;
 /** @} */
+#endif /* ndef CPU_FAM_NRF9160 */
 #endif /* ndef DOXYGEN */
 
 /**

cpu/nrf5x_common/periph/gpio.c

@@ -38,6 +38,16 @@
 #define PORT_BIT            (1 << 5)
 #define PIN_MASK            (0x1f)
 
+/* Compatibility wrapper defines for nRF9160 */
+#ifdef NRF_P0_S
+#define NRF_P0 NRF_P0_S
+#endif
+
+#ifdef NRF_GPIOTE0_S
+#define NRF_GPIOTE NRF_GPIOTE0_S
+#define GPIOTE_IRQn GPIOTE0_IRQn
+#endif
+
 #ifdef MODULE_PERIPH_GPIO_IRQ
 
 #if CPU_FAM_NRF51

cpu/nrf5x_common/periph/pm.c

@@ -23,8 +23,14 @@
 
 #include "cpu.h"
 
+#ifdef NRF_POWER_S
+#define NRF_POWER NRF_POWER_S
+#endif
+
+/* TODO: implement proper pm_off for nRF9160 */
 void pm_off(void)
 {
+#ifndef CPU_FAM_NRF9160
 #ifdef CPU_FAM_NRF51
     NRF_POWER->RAMON = 0;
 #else
@@ -34,5 +40,6 @@ void pm_off(void)
     }
 #endif
     NRF_POWER->SYSTEMOFF = 1;
-    while(1) {}
+    while (1) {}
+#endif /* ndef CPU_FAM_NRF9160 */
 }

cpu/nrf9160/Makefile

@@ -0,0 +1,7 @@
+# define the module that is build
+MODULE = cpu
+
+# add a list of subdirectories, that should also be build
+DIRS = periph $(RIOTCPU)/cortexm_common $(RIOTCPU)/nrf5x_common vectors
+
+include $(RIOTBASE)/Makefile.base

cpu/nrf9160/Makefile.dep

@@ -0,0 +1,4 @@
+USEMODULE += nrf9160_vectors
+
+include $(RIOTCPU)/nrf5x_common/Makefile.dep
+include $(RIOTCPU)/cortexm_common/Makefile.dep

cpu/nrf9160/Makefile.features

@@ -0,0 +1,4 @@
+CPU_CORE = cortex-m33
+CPU_FAM  = nrf9160
+
+include $(RIOTCPU)/nrf5x_common/Makefile.features

cpu/nrf9160/Makefile.include

@@ -0,0 +1,17 @@
+
+ROM_LEN ?= 0x100000
+RAM_LEN ?= 0x40000
+
+ROM_START_ADDR ?= 0x00000000
+RAM_START_ADDR ?= 0x20000000
+
+LINKER_SCRIPT ?= cortexm.ld
+
+FLASHFILE = $(BINFILE)
+
+PROGRAMMER ?= jlink
+JLINK_DEVICE = NRF9160_XXAA
+
+
+include $(RIOTCPU)/nrf5x_common/Makefile.include
+include $(RIOTMAKE)/arch/cortexm.inc.mk

cpu/nrf9160/cpu.c

@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2021 Mesotic SAS
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     cpu_nrf9160
+ * @{
+ *
+ * @file
+ * @brief       Implementation of the CPU initialization
+ *
+ * @author      Dylan Laduranty <dylan.laduranty@mesotic.com>
+ *
+ * @}
+ */
+
+#include "cpu.h"
+#include "nrf_clock.h"
+#include "periph_conf.h"
+#include "periph/init.h"
+#include "stdio_base.h"
+
+/**
+ * @brief   Initialize the CPU, set IRQ priorities
+ */
+void cpu_init(void)
+{
+    /* initialize hf clock */
+    clock_init_hf();
+
+#ifdef NVMC_ICACHECNF_CACHEEN_Msk
+    /* enable instruction cache */
+    NRF_NVMC_S->ICACHECNF = (NVMC_ICACHECNF_CACHEEN_Msk);
+#endif
+
+    /* call cortexm default initialization */
+    cortexm_init();
+
+    /* enable wake up on events for __WFE CPU sleep */
+    SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
+
+    /* initialize stdio prior to periph_init() to allow use of DEBUG() there */
+    stdio_init();
+
+    /* trigger static peripheral initialization */
+    periph_init();
+}

cpu/nrf9160/include/cpu_conf.h

@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2021 Mesotic SAS
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @defgroup        cpu_nrf9160 Nordic nRF9160 MCU
+ * @ingroup         cpu
+ * @brief           Nordic nRF9160 family of CPUs
+ * @{
+ *
+ * @file
+ * @brief       nRF9160 specific CPU configuration
+ *
+ * @author      Dylan Laduranty <dylan.laduranty@mesotic.com>
+ *
+ */
+
+#ifndef CPU_CONF_H
+#define CPU_CONF_H
+
+#include "vendor/nrf9160.h"
+#include "vendor/nrf9160_bitfields.h"
+#include "vendor/nrf9160_peripherals.h"
+
+#include "cpu_conf_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name    ARM Cortex-M specific CPU configuration
+ * @{
+ */
+#define CPU_DEFAULT_IRQ_PRIO            (1U)    /**< Default ARM IRQ priority */
+#define CPU_FLASH_BASE                  (0x00000000) /**< ROM Base Address */
+
+#define CPU_IRQ_NUMOF                   (65U)   /**< nRF9160 specific IRQ count */
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CPU_CONF_H */
+/** @} */

cpu/nrf9160/include/periph_cpu.h

@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2021 Mesotic SAS
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup         cpu_nrf9160
+ * @{
+ *
+ * @file
+ * @brief           nRF9160 specific definitions for handling peripherals
+ *
+ * @author          Dylan Laduranty <dylan.laduranty@mesotic.com>
+ */
+
+#ifndef PERIPH_CPU_H
+#define PERIPH_CPU_H
+
+#include "periph_cpu_common.h"
+#include "macros/units.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief   System core clock speed, fixed to 64MHz for all NRF9160 CPUs
+ */
+#define CLOCK_CORECLOCK     MHZ(64)
+
+/**
+ * @brief    Peripheral clock speed (fixed to 16MHz for nRF9160 based CPUs)
+ */
+#define PERIPH_CLOCK        MHZ(16)
+
+/**
+ * @brief   Structure for UART configuration data
+ */
+typedef struct {
+    NRF_UARTE_Type *dev;    /**< UART with EasyDMA device base
+                             * register address */
+    gpio_t rx_pin;          /**< RX pin */
+    gpio_t tx_pin;          /**< TX pin */
+#ifdef MODULE_PERIPH_UART_HW_FC
+    gpio_t rts_pin;         /**< RTS pin */
+    gpio_t cts_pin;         /**< CTS pin */
+#endif
+    uint8_t irqn;           /**< IRQ channel */
+} uart_conf_t;
+
+/**
+ * @brief   Size of the UART TX buffer for non-blocking mode.
+ */
+#ifndef UART_TXBUF_SIZE
+#define UART_TXBUF_SIZE    (64)
+#endif
+
+#ifndef DOXYGEN
+/**
+ * @brief Wrapper to fix differences between nRF9160 and
+  *       nRF52 vendor files
+  */
+#define UART_BAUDRATE_BAUDRATE_Baud1200 UARTE_BAUDRATE_BAUDRATE_Baud1200
+#define UART_BAUDRATE_BAUDRATE_Baud2400 UARTE_BAUDRATE_BAUDRATE_Baud2400
+#define UART_BAUDRATE_BAUDRATE_Baud4800 UARTE_BAUDRATE_BAUDRATE_Baud4800
+#define UART_BAUDRATE_BAUDRATE_Baud9600 UARTE_BAUDRATE_BAUDRATE_Baud9600
+#define UART_BAUDRATE_BAUDRATE_Baud14400 UARTE_BAUDRATE_BAUDRATE_Baud14400
+#define UART_BAUDRATE_BAUDRATE_Baud19200 UARTE_BAUDRATE_BAUDRATE_Baud19200
+#define UART_BAUDRATE_BAUDRATE_Baud28800 UARTE_BAUDRATE_BAUDRATE_Baud28800
+#define UART_BAUDRATE_BAUDRATE_Baud31250 UARTE_BAUDRATE_BAUDRATE_Baud31250
+#define UART_BAUDRATE_BAUDRATE_Baud38400 UARTE_BAUDRATE_BAUDRATE_Baud38400
+#define UART_BAUDRATE_BAUDRATE_Baud56000 UARTE_BAUDRATE_BAUDRATE_Baud56000
+#define UART_BAUDRATE_BAUDRATE_Baud57600 UARTE_BAUDRATE_BAUDRATE_Baud57600
+#define UART_BAUDRATE_BAUDRATE_Baud76800 UARTE_BAUDRATE_BAUDRATE_Baud76800
+#define UART_BAUDRATE_BAUDRATE_Baud115200 UARTE_BAUDRATE_BAUDRATE_Baud115200
+#define UART_BAUDRATE_BAUDRATE_Baud230400 UARTE_BAUDRATE_BAUDRATE_Baud230400
+#define UART_BAUDRATE_BAUDRATE_Baud250000 UARTE_BAUDRATE_BAUDRATE_Baud250000
+#define UART_BAUDRATE_BAUDRATE_Baud460800 UARTE_BAUDRATE_BAUDRATE_Baud460800
+#define UART_BAUDRATE_BAUDRATE_Baud921600 UARTE_BAUDRATE_BAUDRATE_Baud921600
+#define UART_BAUDRATE_BAUDRATE_Baud1M UARTE_BAUDRATE_BAUDRATE_Baud1M
+#endif /* ndef DOXYGEN */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PERIPH_CPU_H */
+/** @} */

cpu/nrf9160/include/vendor/nrf9160_peripherals.h

@@ -0,0 +1,227 @@
+/*
+
+Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
+
+SPDX-License-Identifier: BSD-3-Clause
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+   list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright
+   notice, this list of conditions and the following disclaimer in the
+   documentation and/or other materials provided with the distribution.
+
+3. Neither the name of Nordic Semiconductor ASA nor the names of its
+   contributors may be used to endorse or promote products derived from this
+   software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+#ifndef _NRF9160_PERIPHERALS_H
+#define _NRF9160_PERIPHERALS_H
+
+/* UICR */
+#define UICR_KEYSLOT_COUNT 128
+
+/* Clock Peripheral */
+#define CLOCK_PRESENT
+#define CLOCK_COUNT 1
+
+/* Power Peripheral */
+#define POWER_PRESENT
+#define POWER_COUNT 1
+
+/* Non-Volatile Memory Controller */
+#define NVMC_PRESENT
+#define NVMC_COUNT 1
+
+#define NVMC_FEATURE_CACHE_PRESENT
+
+/* GPIO */
+#define GPIO_PRESENT
+#define GPIO_COUNT 1
+
+#define P0_PIN_NUM 32
+
+#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
+
+/* Distributed  Peripheral to Peripheral Interconnect */
+#define DPPI_PRESENT
+#define DPPI_COUNT 1
+
+#define DPPI_CH_NUM 16
+#define DPPI_GROUP_NUM 6
+
+/* Event Generator Unit */
+#define EGU_PRESENT
+#define EGU_COUNT 6
+
+#define EGU0_CH_NUM 16
+#define EGU1_CH_NUM 16
+#define EGU2_CH_NUM 16
+#define EGU3_CH_NUM 16
+#define EGU4_CH_NUM 16
+#define EGU5_CH_NUM 16
+
+/* Timer/Counter */
+#define TIMER_PRESENT
+#define TIMER_COUNT 3
+
+#define TIMER0_MAX_SIZE 32
+#define TIMER1_MAX_SIZE 32
+#define TIMER2_MAX_SIZE 32
+
+
+#define TIMER0_CC_NUM 6
+#define TIMER1_CC_NUM 6
+#define TIMER2_CC_NUM 6
+
+/* Real Time Counter */
+#define RTC_PRESENT
+#define RTC_COUNT 2
+
+#define RTC0_CC_NUM 4
+#define RTC1_CC_NUM 4
+
+/* Watchdog Timer */
+#define WDT_PRESENT
+#define WDT_COUNT 1
+
+/* Serial Peripheral Interface Master with DMA */
+#define SPIM_PRESENT
+#define SPIM_COUNT 4
+
+#define SPIM0_MAX_DATARATE  8
+#define SPIM1_MAX_DATARATE  8
+#define SPIM2_MAX_DATARATE  8
+#define SPIM3_MAX_DATARATE  8
+
+#define SPIM0_EASYDMA_MAXCNT_SIZE 12
+#define SPIM1_EASYDMA_MAXCNT_SIZE 12
+#define SPIM2_EASYDMA_MAXCNT_SIZE 12
+#define SPIM3_EASYDMA_MAXCNT_SIZE 12
+
+/* Serial Peripheral Interface Slave with DMA*/
+#define SPIS_PRESENT
+#define SPIS_COUNT 4
+
+#define SPIS0_EASYDMA_MAXCNT_SIZE 12
+#define SPIS1_EASYDMA_MAXCNT_SIZE 12
+#define SPIS2_EASYDMA_MAXCNT_SIZE 12
+#define SPIS3_EASYDMA_MAXCNT_SIZE 12
+
+/* Two Wire Interface Master with DMA */
+#define TWIM_PRESENT
+#define TWIM_COUNT 4
+
+#define TWIM0_EASYDMA_MAXCNT_SIZE 12
+#define TWIM1_EASYDMA_MAXCNT_SIZE 12
+#define TWIM2_EASYDMA_MAXCNT_SIZE 12
+#define TWIM3_EASYDMA_MAXCNT_SIZE 12
+
+/* Two Wire Interface Slave with DMA */
+#define TWIS_PRESENT
+#define TWIS_COUNT 4
+
+#define TWIS0_EASYDMA_MAXCNT_SIZE 12
+#define TWIS1_EASYDMA_MAXCNT_SIZE 12
+#define TWIS2_EASYDMA_MAXCNT_SIZE 12
+#define TWIS3_EASYDMA_MAXCNT_SIZE 12
+
+/* Universal Asynchronous Receiver-Transmitter with DMA */
+#define UARTE_PRESENT
+#define UARTE_COUNT 4
+
+#define UARTE0_EASYDMA_MAXCNT_SIZE 12
+#define UARTE1_EASYDMA_MAXCNT_SIZE 12
+#define UARTE2_EASYDMA_MAXCNT_SIZE 12
+#define UARTE3_EASYDMA_MAXCNT_SIZE 12
+
+/* Successive Approximation Analog to Digital Converter */
+#define SAADC_PRESENT
+#define SAADC_COUNT 1
+
+#define SAADC_CH_NUM 8
+#define SAADC_EASYDMA_MAXCNT_SIZE 15
+
+/* GPIO Tasks and Events */
+#define GPIOTE_PRESENT
+#define GPIOTE_COUNT 2
+
+#define GPIOTE_CH_NUM 8
+
+#define GPIOTE_FEATURE_SET_PRESENT
+#define GPIOTE_FEATURE_CLR_PRESENT
+
+/* Pulse Width Modulator */
+#define PWM_PRESENT
+#define PWM_COUNT 4
+
+#define PWM_CH_NUM 4
+
+#define PWM_EASYDMA_MAXCNT_SIZE 15
+
+/* Pulse Density Modulator */
+#define PDM_PRESENT
+#define PDM_COUNT 1
+
+#define PDM_EASYDMA_MAXCNT_SIZE 15
+
+/* Inter-IC Sound Interface */
+#define I2S_PRESENT
+#define I2S_COUNT 1
+
+#define I2S_EASYDMA_MAXCNT_SIZE 14
+
+/* Inter Processor Communication */
+#define IPC_PRESENT
+#define IPC_COUNT 1
+
+#define IPC_CH_NUM 8
+#define IPC_CONF_NUM 8
+#define IPC_GPMEM_NUM 4
+
+/* FPU */
+#define FPU_PRESENT
+#define FPU_COUNT 1
+
+/* SPU */
+#define SPU_PRESENT
+#define SPU_COUNT 1
+
+/* CRYPTOCELL */
+#define CRYPTOCELL_PRESENT
+#define CRYPTOCELL_COUNT 1
+
+/* KMU */
+#define KMU_PRESENT
+#define KMU_COUNT 1
+
+#define KMU_KEYSLOT_PRESENT
+
+/* MAGPIO */
+#define MAGPIO_PRESENT
+#define MAGPIO_COUNT 1
+#define MAGPIO_PIN_NUM 3
+
+/* REGULATORS */
+#define REGULATORS_PRESENT
+#define REGULATORS_COUNT 1
+
+
+#endif  // _NRF9160_PERIPHERALS_H

cpu/nrf9160/periph/Makefile

@@ -0,0 +1 @@
+include $(RIOTMAKE)/periph.mk

cpu/nrf9160/vectors/Makefile

@@ -0,0 +1,11 @@
+MODULE = nrf9160_vectors
+
+NO_AUTO_SRC = 1
+
+SRC_FILE = vectors_$(CPU_MODEL).c
+
+SRCS += $(SRC_FILE)
+# (file triggers compiler bug. see #5775)
+SRC_NOLTO += $(SRC_FILE)
+
+include $(RIOTBASE)/Makefile.base

cpu/nrf9160/vectors/vectors_nrf9160.c

@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2021 Mesotic SAS
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     cpu_nrf9160
+ * @{
+ *
+ * @file
+ * @brief       nRF9160 interrupt vector definitions
+ *
+ * @author      Dylan Laduranty <dylan.laduranty@mesotic.com>
+ *
+ * @}
+ */
+
+#include <stdint.h>
+
+#include "cpu.h"
+#include "vectors_cortexm.h"
+
+/* define a local dummy handler as it needs to be in the same compilation unit
+ * as the alias definition */
+void dummy_handler(void) {
+    dummy_handler_default();
+}
+
+/* nRF9160 specific interrupt vectors */
+WEAK_DEFAULT void isr_spu(void);
+WEAK_DEFAULT void isr_clock_power(void);
+WEAK_DEFAULT void isr_uarte0_spim0_spis0_twim0_twis0(void);
+WEAK_DEFAULT void isr_uarte1_spim1_spis1_twim1_twis1(void);
+WEAK_DEFAULT void isr_uarte2_spim2_spis2_twim2_twis2(void);
+WEAK_DEFAULT void isr_uarte3_spim3_spis3_twim3_twis3(void);
+WEAK_DEFAULT void isr_gpiote(void);
+WEAK_DEFAULT void isr_saadc(void);
+WEAK_DEFAULT void isr_timer0(void);
+WEAK_DEFAULT void isr_timer1(void);
+WEAK_DEFAULT void isr_timer2(void);
+WEAK_DEFAULT void isr_rtc0(void);
+WEAK_DEFAULT void isr_rtc1(void);
+WEAK_DEFAULT void isr_wdt(void);
+WEAK_DEFAULT void isr_egu0(void);
+WEAK_DEFAULT void isr_egu1(void);
+WEAK_DEFAULT void isr_egu2(void);
+WEAK_DEFAULT void isr_egu3(void);
+WEAK_DEFAULT void isr_egu4(void);
+WEAK_DEFAULT void isr_egu5(void);
+WEAK_DEFAULT void isr_pwm0(void);
+WEAK_DEFAULT void isr_pwm1(void);
+WEAK_DEFAULT void isr_pwm2(void);
+WEAK_DEFAULT void isr_pwm3(void);
+WEAK_DEFAULT void isr_pdm(void);
+WEAK_DEFAULT void isr_i2s(void);
+WEAK_DEFAULT void isr_ipc(void);
+WEAK_DEFAULT void isr_fpu(void);
+WEAK_DEFAULT void isr_gpiote1(void);
+WEAK_DEFAULT void isr_kmu(void);
+WEAK_DEFAULT void isr_cryptocell(void);
+
+/* CPU specific interrupt vector table */
+ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
+    [3] = isr_spu,                /* SPU */
+    [5] = isr_clock_power,        /* power_clock */
+    [8] = isr_uarte0_spim0_spis0_twim0_twis0,
+    [9] = isr_uarte1_spim1_spis1_twim1_twis1,
+    [10] = isr_uarte2_spim2_spis2_twim2_twis2,
+    [11] = isr_uarte3_spim3_spis3_twim3_twis3,
+    [13] = isr_gpiote,             /* gpiote0 */
+    [14] = isr_saadc,
+    [15] = isr_timer0,
+    [16] = isr_timer1,
+    [17] = isr_timer2,
+    [20] = isr_rtc0,
+    [21] = isr_rtc1,
+    [24] = isr_wdt,
+    [27] = isr_egu0,
+    [28] = isr_egu1,
+    [29] = isr_egu2,
+    [30] = isr_egu3,
+    [31] = isr_egu4,
+    [32] = isr_egu5,
+    [33] = isr_pwm0,
+    [34] = isr_pwm1,
+    [35] = isr_pwm2,
+    [36] = isr_pwm3,
+    [38] = isr_pdm,
+    [40] = isr_i2s,
+    [42] = isr_ipc,
+    [44] = isr_fpu,
+    [49] = isr_gpiote1,
+    [57] = isr_kmu,
+    [64] = isr_cryptocell
+};