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cpu/stm32f1: adapted UART driver

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This commit is contained in:
Hauke Petersen 2015-10-20 16:27:05 +02:00
parent b71d8ea750
commit 59b935bd1e
1 changed files with 19 additions and 135 deletions
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154
cpu/stm32f1/periph/uart.c
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@ -30,41 +30,19 @@
#include "sched.h"
#include "thread.h"
/* guard file in case no UART device is defined */
#if UART_0_EN || UART_1_EN
/**
* @brief Each UART device has to store two callbacks.
*/
typedef struct {
uart_rx_cb_t rx_cb;
uart_tx_cb_t tx_cb;
void *arg;
} uart_conf_t;
/**
* @brief Unified interrupt handler for all UART devices
*
* @param uartnum the number of the UART that triggered the ISR
* @param uart the UART device that triggered the ISR
*/
static inline void irq_handler(uart_t uartnum, USART_TypeDef *uart);
/**
* @brief Allocate memory to store the callback functions.
*/
static uart_conf_t config[UART_NUMOF];
static uart_isr_ctx_t config[UART_NUMOF];
static int init_base(uart_t uart, uint32_t baudrate);
int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb,
uart_tx_cb_t tx_cb, void *arg)
int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
{
int res;
/* initialize UART in blocking mode first */
res = uart_init_blocking(uart, baudrate);
res = init_base(uart, baudrate);
if (res < 0) {
return res;
}
@ -73,14 +51,12 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb,
switch (uart) {
#if UART_0_EN
case UART_0:
NVIC_SetPriority(UART_0_IRQ, UART_IRQ_PRIO);
NVIC_EnableIRQ(UART_0_IRQ);
UART_0_DEV->CR1 |= USART_CR1_RXNEIE;
break;
#endif
#if UART_1_EN
case UART_1:
NVIC_SetPriority(UART_1_IRQ, UART_IRQ_PRIO);
NVIC_EnableIRQ(UART_1_IRQ);
UART_1_DEV->CR1 |= USART_CR1_RXNEIE;
break;
@ -91,13 +67,12 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb,
/* register callbacks */
config[uart].rx_cb = rx_cb;
config[uart].tx_cb = tx_cb;
config[uart].arg = arg;
return 0;
}
int uart_init_blocking(uart_t uart, uint32_t baudrate)
static int init_base(uart_t uart, uint32_t baudrate)
{
USART_TypeDef *dev;
uint32_t bus_freq;
@ -146,39 +121,7 @@ int uart_init_blocking(uart_t uart, uint32_t baudrate)
return 0;
}
void uart_tx_begin(uart_t uart)
{
switch (uart) {
#if UART_0_EN
case UART_0:
UART_0_DEV->CR1 |= USART_CR1_TXEIE;
break;
#endif
#if UART_1_EN
case UART_1:
UART_1_DEV->CR1 |= USART_CR1_TXEIE;
break;
#endif
}
}
void uart_tx_end(uart_t uart)
{
switch (uart) {
#if UART_0_EN
case UART_0:
UART_0_DEV->CR1 &= ~USART_CR1_TXEIE;
break;
#endif
#if UART_1_EN
case UART_1:
UART_1_DEV->CR1 &= ~USART_CR1_TXEIE;
break;
#endif
}
}
int uart_write(uart_t uart, char data)
void uart_write(uart_t uart, const uint8_t *data, size_t len)
{
USART_TypeDef *dev;
@ -193,65 +136,27 @@ int uart_write(uart_t uart, char data)
dev = UART_1_DEV;
break;
#endif
default:
return -1;
}
if (dev->SR & USART_SR_TXE) {
dev->DR = (uint8_t)data;
for (size_t i = 0; i < len; i++) {
while (!(dev->SR & USART_SR_TXE));
dev->DR = data[i];
}
return 0;
}
int uart_read_blocking(uart_t uart, char *data)
static inline void irq_handler(uart_t uartnum, USART_TypeDef *dev)
{
USART_TypeDef *dev;
switch (uart) {
#if UART_0_EN
case UART_0:
dev = UART_0_DEV;
break;
#endif
#if UART_1_EN
case UART_1:
dev = UART_1_DEV;
break;
#endif
default:
return -1;
if (dev->SR & USART_SR_RXNE) {
char data = (char)dev->DR;
config[uartnum].rx_cb(config[uartnum].arg, data);
}
while (!(dev->SR & USART_SR_RXNE));
*data = (char)dev->DR;
return 1;
}
int uart_write_blocking(uart_t uart, char data)
{
USART_TypeDef *dev;
switch (uart) {
#if UART_0_EN
case UART_0:
dev = UART_0_DEV;
break;
#endif
#if UART_1_EN
case UART_1:
dev = UART_1_DEV;
break;
#endif
default:
return -1;
else if (dev->SR & USART_SR_ORE) {
/* ORE is cleared by reading SR and DR sequentially */
dev->DR;
}
if (sched_context_switch_request) {
thread_yield();
}
while (!(dev->SR & USART_SR_TXE));
dev->DR = (uint8_t)data;
return 1;
}
#if UART_0_EN
@ -267,24 +172,3 @@ void UART_1_ISR(void)
irq_handler(UART_1, UART_1_DEV);
}
#endif
static inline void irq_handler(uart_t uartnum, USART_TypeDef *dev)
{
if (dev->SR & USART_SR_RXNE) {
char data = (char)dev->DR;
config[uartnum].rx_cb(config[uartnum].arg, data);
}
else if (dev->SR & USART_SR_ORE) {
/* ORE is cleared by reading SR and DR sequentially */
dev->DR;
}
else if (dev->SR & USART_SR_TXE) {
if (config[uartnum].tx_cb(config[uartnum].arg) == 0) {
dev->CR1 &= ~(USART_CR1_TXEIE);
}
}
if (sched_context_switch_request) {
thread_yield();
}
}
#endif /* UART_0_EN || UART_1_EN */