mirror of
https://github.com/RIOT-OS/RIOT.git
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Merge pull request #14372 from benpicco/cpu/nrf52-full
cpu/nrf52: add support for the whole family, fix nrf52811
This commit is contained in:
Francisco
GitHub
commit
578b8b8885
19
boards/e104-bt5010a-tb/Kconfig
Normal file
19
boards/e104-bt5010a-tb/Kconfig
Normal file
@ -0,0 +1,19 @@
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# Copyright (c) 2020 Benjamin Valentin
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#
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# This file is subject to the terms and conditions of the GNU Lesser
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||||||
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# General Public License v2.1. See the file LICENSE in the top level
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# directory for more details.
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config BOARD
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default "e104-bt5010a-tb" if BOARD_E104_BT5010A_TB
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config BOARD_E104_BT5010A_TB
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bool
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default y
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select BOARD_COMMON_NRF52
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select CPU_MODEL_NRF52810XXAA
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select HAS_PERIPH_I2C
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select HAS_PERIPH_SPI
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select HAS_PERIPH_UART
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source "$(RIOTBOARD)/common/nrf52/Kconfig"
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2
boards/e104-bt5010a-tb/Makefile
Normal file
2
boards/e104-bt5010a-tb/Makefile
Normal file
@ -0,0 +1,2 @@
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MODULE = board
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include $(RIOTBASE)/Makefile.base
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5
boards/e104-bt5010a-tb/Makefile.dep
Normal file
5
boards/e104-bt5010a-tb/Makefile.dep
Normal file
@ -0,0 +1,5 @@
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ifneq (,$(filter saul_default,$(USEMODULE)))
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USEMODULE += saul_gpio
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endif
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include $(RIOTBOARD)/common/nrf52/Makefile.dep
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9
boards/e104-bt5010a-tb/Makefile.features
Normal file
9
boards/e104-bt5010a-tb/Makefile.features
Normal file
@ -0,0 +1,9 @@
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CPU_MODEL = nrf52810xxaa
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_rtt
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FEATURES_PROVIDED += periph_uart
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include $(RIOTBOARD)/common/nrf52/Makefile.features
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4
boards/e104-bt5010a-tb/Makefile.include
Normal file
4
boards/e104-bt5010a-tb/Makefile.include
Normal file
@ -0,0 +1,4 @@
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# external programmer required
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DEBUG_ADAPTER ?= jlink
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include $(RIOTBOARD)/common/nrf52/Makefile.include
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32
boards/e104-bt5010a-tb/board.c
Normal file
32
boards/e104-bt5010a-tb/board.c
Normal file
@ -0,0 +1,32 @@
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/*
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* Copyright (C) 2020 Benjamin Valentin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_e104-bt5010a-tb
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* @{
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*
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* @file
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* @brief Board initialization for the E104-BT5010A Test Board
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*
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* @author Benjamin Valentin <benpicco@googlemail.com>
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*
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* @}
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*/
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#include "cpu.h"
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#include "board.h"
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void board_init(void)
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{
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/* initialize the boards LEDs */
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LED_PORT->DIRSET = (LED_MASK);
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LED_PORT->OUTSET = (LED_MASK);
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/* initialize the CPU */
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cpu_init();
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}
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31
boards/e104-bt5010a-tb/doc.txt
Normal file
31
boards/e104-bt5010a-tb/doc.txt
Normal file
@ -0,0 +1,31 @@
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/**
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@defgroup boards_e104-bt5010a-tb E104-BT5010A Test Board
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@ingroup boards
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@brief Support for the Ebyte E104-BT5010A Test Board (nRF52810)
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## General information
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The E104-BT5010A Test Board is a cheap break-out board for the E104-BT5010A module.
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It's based on the nRF52810 and by default comes with a Firmware that accepts AT
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|
commands over UART, but it can be flashed with RIOT easily.
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- [Module Datasheet](http://www.ebyte.com/en/downpdf.aspx?id=832)
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- [Module Website](http://www.ebyte.com/en/product-view-news.aspx?id=832)
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## Flashing the board
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To flash the board, you have to connect a SWD programmer to the pins labeled SWDIO and
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SWCLK. Also make sure to connect GND.
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P0.21 is Reset.
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## Accessing STDIO via UART
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The STDIO is directly accessible via the USB port. On a Linux host, it's
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generally mapped to `/dev/ttyUSB0`.
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Use the `term` target to connect to the board serial port<br/>
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```
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make BOARD=e104-bt5010a-tb -C examples/hello-world term
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```
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*/
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64
boards/e104-bt5010a-tb/include/board.h
Normal file
64
boards/e104-bt5010a-tb/include/board.h
Normal file
@ -0,0 +1,64 @@
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|
/*
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* Copyright (C) 2020 Benjamin Valentin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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||||||
|
* General Public License v2.1. See the file LICENSE in the top level
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||||||
|
* directory for more details.
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*/
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/**
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* @ingroup boards_e104-bt5010a-tb
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* @{
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*
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* @file
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* @brief Board specific configuration for the E104-BT5010A Test Board
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*
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* @author Benjamin Valentin <benpicco@googlemail.com>
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*/
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#ifndef BOARD_H
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#define BOARD_H
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#include "board_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name LED pin configuration
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* @{
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*/
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#define LED0_PIN GPIO_PIN(0, 30)
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#define LED1_PIN GPIO_PIN(0, 31)
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#define LED_PORT (NRF_P0)
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#define LED0_MASK (1 << 30)
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#define LED1_MASK (1 << 31)
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#define LED_MASK (LED0_MASK | LED1_MASK)
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#define LED0_ON (LED_PORT->OUTCLR = LED0_MASK)
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#define LED0_OFF (LED_PORT->OUTSET = LED0_MASK)
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#define LED0_TOGGLE (LED_PORT->OUT ^= LED0_MASK)
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#define LED1_ON (LED_PORT->OUTCLR = LED1_MASK)
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#define LED1_OFF (LED_PORT->OUTSET = LED1_MASK)
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#define LED1_TOGGLE (LED_PORT->OUT ^= LED1_MASK)
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/** @} */
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/**
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* @name Button pin configuration
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* @{
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*/
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#define BTN0_PIN GPIO_PIN(0, 21)
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#define BTN0_MODE GPIO_IN_PU
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#define BTN1_PIN GPIO_PIN(0, 29)
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#define BTN1_MODE GPIO_IN_PU
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* BOARD_H */
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/** @} */
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65
boards/e104-bt5010a-tb/include/gpio_params.h
Normal file
65
boards/e104-bt5010a-tb/include/gpio_params.h
Normal file
@ -0,0 +1,65 @@
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/*
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* Copyright (C) 2020 Benjamin Valentin
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|
*
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* This file is subject to the terms and conditions of the GNU Lesser
|
||||||
|
* General Public License v2.1. See the file LICENSE in the top level
|
||||||
|
* directory for more details.
|
||||||
|
*/
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||||||
|
/**
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* @ingroup boards_e104-bt5010a-tb
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* @{
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|
*
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* @file
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* @brief Board specific configuration of direct mapped GPIOs
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*
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* @author Benjamin Valentin <benpicco@googlemail.com>
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*/
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#ifndef GPIO_PARAMS_H
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#define GPIO_PARAMS_H
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#include "board.h"
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#include "saul/periph.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief GPIO pin configuration
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*/
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static const saul_gpio_params_t saul_gpio_params[] =
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{
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{
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.name = "LED (link)",
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.pin = LED0_PIN,
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.mode = GPIO_OUT,
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.flags = SAUL_GPIO_INVERTED,
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},
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{
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.name = "LED (data)",
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.pin = LED1_PIN,
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.mode = GPIO_OUT,
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.flags = SAUL_GPIO_INVERTED,
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},
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{
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.name = "BTN (RTS)",
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|
.pin = BTN0_PIN,
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|
.mode = BTN0_MODE,
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.flags = SAUL_GPIO_INVERTED,
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|
},
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|
{
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|
.name = "BTN (DBG)",
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.pin = BTN1_PIN,
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|
.mode = BTN1_MODE,
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||||||
|
.flags = SAUL_GPIO_INVERTED,
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||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* GPIO_PARAMS_H */
|
||||||
|
/** @} */
|
||||||
97
boards/e104-bt5010a-tb/include/periph_conf.h
Normal file
97
boards/e104-bt5010a-tb/include/periph_conf.h
Normal file
@ -0,0 +1,97 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 2020 Benjamin Valentin
|
||||||
|
*
|
||||||
|
* This file is subject to the terms and conditions of the GNU Lesser
|
||||||
|
* General Public License v2.1. See the file LICENSE in the top level
|
||||||
|
* directory for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @ingroup boards_e104-bt5010a-tb
|
||||||
|
* @{
|
||||||
|
*
|
||||||
|
* @file
|
||||||
|
* @brief Peripheral configuration for the E104-BT5010A Test Board
|
||||||
|
*
|
||||||
|
* @author Benjamin Valentin <benpicco@googlemail.com>
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef PERIPH_CONF_H
|
||||||
|
#define PERIPH_CONF_H
|
||||||
|
|
||||||
|
#include "periph_cpu.h"
|
||||||
|
#include "cfg_rtt_default.h"
|
||||||
|
#include "cfg_timer_default.h"
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name Clock configuration
|
||||||
|
* The E104-BT5010A module does not have any external oscillators
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define CLOCK_HFCLK (0U) /* internal RC oscillator */
|
||||||
|
#define CLOCK_LFCLK (0) /* internal RC oscillator */
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name SPI configuration
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
static const spi_conf_t spi_config[] = {
|
||||||
|
{
|
||||||
|
.dev = NRF_SPIM0,
|
||||||
|
.sclk = GPIO_PIN(0, 26),
|
||||||
|
.mosi = GPIO_PIN(0, 27),
|
||||||
|
.miso = GPIO_PIN(0, 28),
|
||||||
|
},
|
||||||
|
};
|
||||||
|
#define SPI_NUMOF ARRAY_SIZE(spi_config)
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name I2C configuration
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
static const i2c_conf_t i2c_config[] = {
|
||||||
|
{
|
||||||
|
.dev = NRF_TWIM0,
|
||||||
|
.scl = GPIO_PIN(0, 6),
|
||||||
|
.sda = GPIO_PIN(0, 7),
|
||||||
|
.speed = I2C_SPEED_NORMAL
|
||||||
|
}
|
||||||
|
};
|
||||||
|
#define I2C_NUMOF ARRAY_SIZE(i2c_config)
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name UART configuration
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
static const uart_conf_t uart_config[] = {
|
||||||
|
{ /* Mapped to USB virtual COM port */
|
||||||
|
.dev = NRF_UARTE0,
|
||||||
|
.rx_pin = GPIO_PIN(0,14),
|
||||||
|
.tx_pin = GPIO_PIN(0,18),
|
||||||
|
#ifdef MODULE_PERIPH_UART_HW_FC
|
||||||
|
.rts_pin = GPIO_UNDEF,
|
||||||
|
.cts_pin = GPIO_UNDEF,
|
||||||
|
#endif
|
||||||
|
.irqn = UARTE0_UART0_IRQn,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
#define UART_0_ISR (isr_uart0)
|
||||||
|
|
||||||
|
#define UART_NUMOF ARRAY_SIZE(uart_config)
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* PERIPH_CONF_H */
|
||||||
|
/** @} */
|
||||||
@ -6,7 +6,6 @@
|
|||||||
|
|
||||||
config CPU_FAM_NRF52
|
config CPU_FAM_NRF52
|
||||||
bool
|
bool
|
||||||
select CPU_CORE_CORTEX_M4F
|
|
||||||
select CPU_COMMON_NRF5X
|
select CPU_COMMON_NRF5X
|
||||||
# The ADC does not depend on any board configuration, so always available
|
# The ADC does not depend on any board configuration, so always available
|
||||||
select HAS_PERIPH_ADC
|
select HAS_PERIPH_ADC
|
||||||
@ -17,13 +16,40 @@ config CPU_FAM_NRF52
|
|||||||
select HAS_CPU_NRF52
|
select HAS_CPU_NRF52
|
||||||
|
|
||||||
## CPU Models
|
## CPU Models
|
||||||
|
config CPU_MODEL_NRF52805XXAA
|
||||||
|
bool
|
||||||
|
select CPU_CORE_CORTEX_M4
|
||||||
|
select CPU_FAM_NRF52
|
||||||
|
|
||||||
|
config CPU_MODEL_NRF52810XXAA
|
||||||
|
bool
|
||||||
|
select CPU_CORE_CORTEX_M4
|
||||||
|
select CPU_FAM_NRF52
|
||||||
|
|
||||||
|
config CPU_MODEL_NRF52811XXAA
|
||||||
|
bool
|
||||||
|
select CPU_CORE_CORTEX_M4
|
||||||
|
select CPU_FAM_NRF52
|
||||||
|
|
||||||
|
config CPU_MODEL_NRF52820XXAA
|
||||||
|
bool
|
||||||
|
select CPU_CORE_CORTEX_M4
|
||||||
|
select CPU_FAM_NRF52
|
||||||
|
|
||||||
config CPU_MODEL_NRF52832XXAA
|
config CPU_MODEL_NRF52832XXAA
|
||||||
bool
|
bool
|
||||||
select CPU_FAM_NRF52
|
select CPU_FAM_NRF52
|
||||||
|
select CPU_CORE_CORTEX_M4F
|
||||||
select HAS_BLE_NORDIC_SOFTDEVICE
|
select HAS_BLE_NORDIC_SOFTDEVICE
|
||||||
|
|
||||||
|
config CPU_MODEL_NRF52833XXAA
|
||||||
|
bool
|
||||||
|
select CPU_CORE_CORTEX_M4F
|
||||||
|
select CPU_FAM_NRF52
|
||||||
|
|
||||||
config CPU_MODEL_NRF52840XXAA
|
config CPU_MODEL_NRF52840XXAA
|
||||||
bool
|
bool
|
||||||
|
select CPU_CORE_CORTEX_M4F
|
||||||
select CPU_FAM_NRF52
|
select CPU_FAM_NRF52
|
||||||
|
|
||||||
## CPU common symbols
|
## CPU common symbols
|
||||||
@ -31,7 +57,12 @@ config CPU_FAM
|
|||||||
default "nrf52" if CPU_FAM_NRF52
|
default "nrf52" if CPU_FAM_NRF52
|
||||||
|
|
||||||
config CPU_MODEL
|
config CPU_MODEL
|
||||||
|
default "nrf52805xxaa" if CPU_MODEL_NRF52805XXAA
|
||||||
|
default "nrf52810xxaa" if CPU_MODEL_NRF52810XXAA
|
||||||
|
default "nrf52811xxaa" if CPU_MODEL_NRF52811XXAA
|
||||||
|
default "nrf52820xxaa" if CPU_MODEL_NRF52820XXAA
|
||||||
default "nrf52832xxaa" if CPU_MODEL_NRF52832XXAA
|
default "nrf52832xxaa" if CPU_MODEL_NRF52832XXAA
|
||||||
|
default "nrf52833xxaa" if CPU_MODEL_NRF52833XXAA
|
||||||
default "nrf52840xxaa" if CPU_MODEL_NRF52840XXAA
|
default "nrf52840xxaa" if CPU_MODEL_NRF52840XXAA
|
||||||
|
|
||||||
config CPU
|
config CPU
|
||||||
|
|||||||
@ -2,10 +2,7 @@
|
|||||||
MODULE = cpu
|
MODULE = cpu
|
||||||
|
|
||||||
# add a list of subdirectories, that should also be build
|
# add a list of subdirectories, that should also be build
|
||||||
DIRS = periph $(RIOTCPU)/cortexm_common $(RIOTCPU)/nrf5x_common
|
DIRS = periph $(RIOTCPU)/cortexm_common $(RIOTCPU)/nrf5x_common vectors
|
||||||
|
|
||||||
# (file triggers compiler bug. see #5775)
|
|
||||||
SRC_NOLTO += vectors.c
|
|
||||||
|
|
||||||
# build the nrf802154 driver if selected
|
# build the nrf802154 driver if selected
|
||||||
ifneq (,$(filter nrf802154,$(USEMODULE)))
|
ifneq (,$(filter nrf802154,$(USEMODULE)))
|
||||||
|
|||||||
@ -1,3 +1,5 @@
|
|||||||
|
USEMODULE += nrf52_vectors
|
||||||
|
|
||||||
ifneq (,$(filter nrf802154,$(USEMODULE)))
|
ifneq (,$(filter nrf802154,$(USEMODULE)))
|
||||||
FEATURES_REQUIRED += periph_timer
|
FEATURES_REQUIRED += periph_timer
|
||||||
FEATURES_REQUIRED += radio_nrf802154
|
FEATURES_REQUIRED += radio_nrf802154
|
||||||
|
|||||||
@ -1,4 +1,8 @@
|
|||||||
|
ifneq (,$(filter nrf52832xxaa nrf52833xxaa nrf52840xxaa,$(CPU_MODEL)))
|
||||||
CPU_CORE = cortex-m4f
|
CPU_CORE = cortex-m4f
|
||||||
|
else
|
||||||
|
CPU_CORE = cortex-m4
|
||||||
|
endif
|
||||||
CPU_FAM = nrf52
|
CPU_FAM = nrf52
|
||||||
|
|
||||||
# The ADC does not depend on any board configuration, so always available
|
# The ADC does not depend on any board configuration, so always available
|
||||||
|
|||||||
@ -10,14 +10,22 @@ export MCUBOOT_SLOT1_SIZE = 0x3C000
|
|||||||
export MCUBOOT_SLOT2_SIZE = 0x3C000
|
export MCUBOOT_SLOT2_SIZE = 0x3C000
|
||||||
|
|
||||||
# Set ROM and RAM lengths according to CPU model
|
# Set ROM and RAM lengths according to CPU model
|
||||||
ifneq (,$(filter nrf52811xxaa,$(CPU_MODEL)))
|
ifneq (,$(filter nrf52805xxaa nrf52810xxaa nrf52811xxaa,$(CPU_MODEL)))
|
||||||
ROM_LEN ?= 0x30000
|
ROM_LEN ?= 0x30000
|
||||||
RAM_LEN ?= 0x6000
|
RAM_LEN ?= 0x6000
|
||||||
endif
|
endif
|
||||||
|
ifneq (,$(filter nrf52820xxaa,$(CPU_MODEL)))
|
||||||
|
ROM_LEN ?= 0x40000
|
||||||
|
RAM_LEN ?= 0x8000
|
||||||
|
endif
|
||||||
ifneq (,$(filter nrf52832xxaa,$(CPU_MODEL)))
|
ifneq (,$(filter nrf52832xxaa,$(CPU_MODEL)))
|
||||||
ROM_LEN ?= 0x80000
|
ROM_LEN ?= 0x80000
|
||||||
RAM_LEN ?= 0x10000
|
RAM_LEN ?= 0x10000
|
||||||
endif
|
endif
|
||||||
|
ifneq (,$(filter nrf52833xxaa,$(CPU_MODEL)))
|
||||||
|
ROM_LEN ?= 0x80000
|
||||||
|
RAM_LEN ?= 0x20000
|
||||||
|
endif
|
||||||
ifneq (,$(filter nrf52840xxaa,$(CPU_MODEL)))
|
ifneq (,$(filter nrf52840xxaa,$(CPU_MODEL)))
|
||||||
ROM_LEN ?= 0x100000
|
ROM_LEN ?= 0x100000
|
||||||
RAM_LEN ?= 0x40000
|
RAM_LEN ?= 0x40000
|
||||||
@ -28,5 +36,7 @@ RAM_START_ADDR ?= 0x20000000
|
|||||||
|
|
||||||
LINKER_SCRIPT ?= cortexm.ld
|
LINKER_SCRIPT ?= cortexm.ld
|
||||||
|
|
||||||
|
VECTORS_O ?= $(BINDIR)/nrf52_vectors/vectors_$(CPU_MODEL).o
|
||||||
|
|
||||||
include $(RIOTCPU)/nrf5x_common/Makefile.include
|
include $(RIOTCPU)/nrf5x_common/Makefile.include
|
||||||
include $(RIOTMAKE)/arch/cortexm.inc.mk
|
include $(RIOTMAKE)/arch/cortexm.inc.mk
|
||||||
|
|||||||
@ -68,8 +68,10 @@ void cpu_init(void)
|
|||||||
/* initialize hf clock */
|
/* initialize hf clock */
|
||||||
clock_init_hf();
|
clock_init_hf();
|
||||||
|
|
||||||
|
#ifdef NVMC_ICACHECNF_CACHEEN_Msk
|
||||||
/* enable instruction cache */
|
/* enable instruction cache */
|
||||||
NRF_NVMC->ICACHECNF = (NVMC_ICACHECNF_CACHEEN_Msk);
|
NRF_NVMC->ICACHECNF = (NVMC_ICACHECNF_CACHEEN_Msk);
|
||||||
|
#endif
|
||||||
|
|
||||||
/* softdevice needs to be enabled from ISR context */
|
/* softdevice needs to be enabled from ISR context */
|
||||||
#ifdef SOFTDEVICE_PRESENT
|
#ifdef SOFTDEVICE_PRESENT
|
||||||
|
|||||||
@ -30,10 +30,26 @@
|
|||||||
#include "vendor/nrf52.h"
|
#include "vendor/nrf52.h"
|
||||||
#include "vendor/nrf52_bitfields.h"
|
#include "vendor/nrf52_bitfields.h"
|
||||||
#include "vendor/nrf52832_peripherals.h"
|
#include "vendor/nrf52832_peripherals.h"
|
||||||
|
#elif defined(CPU_MODEL_NRF52805XXAA)
|
||||||
|
#include "vendor/nrf52805.h"
|
||||||
|
#include "vendor/nrf52805_bitfields.h"
|
||||||
|
#include "vendor/nrf52805_peripherals.h"
|
||||||
|
#elif defined(CPU_MODEL_NRF52810XXAA)
|
||||||
|
#include "vendor/nrf52810.h"
|
||||||
|
#include "vendor/nrf52810_bitfields.h"
|
||||||
|
#include "vendor/nrf52810_peripherals.h"
|
||||||
#elif defined(CPU_MODEL_NRF52811XXAA)
|
#elif defined(CPU_MODEL_NRF52811XXAA)
|
||||||
#include "vendor/nrf52811.h"
|
#include "vendor/nrf52811.h"
|
||||||
#include "vendor/nrf52811_bitfields.h"
|
#include "vendor/nrf52811_bitfields.h"
|
||||||
#include "vendor/nrf52811_peripherals.h"
|
#include "vendor/nrf52811_peripherals.h"
|
||||||
|
#elif defined(CPU_MODEL_NRF52820XXAA)
|
||||||
|
#include "vendor/nrf52820.h"
|
||||||
|
#include "vendor/nrf52820_bitfields.h"
|
||||||
|
#include "vendor/nrf52820_peripherals.h"
|
||||||
|
#elif defined(CPU_MODEL_NRF52833XXAA)
|
||||||
|
#include "vendor/nrf52833.h"
|
||||||
|
#include "vendor/nrf52833_bitfields.h"
|
||||||
|
#include "vendor/nrf52833_peripherals.h"
|
||||||
#elif defined(CPU_MODEL_NRF52840XXAA)
|
#elif defined(CPU_MODEL_NRF52840XXAA)
|
||||||
#include "vendor/nrf52840.h"
|
#include "vendor/nrf52840.h"
|
||||||
#include "vendor/nrf52840_bitfields.h"
|
#include "vendor/nrf52840_bitfields.h"
|
||||||
@ -53,12 +69,20 @@ extern "C" {
|
|||||||
#define CPU_DEFAULT_IRQ_PRIO (2U)
|
#define CPU_DEFAULT_IRQ_PRIO (2U)
|
||||||
#define CPU_FLASH_BASE (0x00000000)
|
#define CPU_FLASH_BASE (0x00000000)
|
||||||
|
|
||||||
#if defined(CPU_MODEL_NRF52811XXAA)
|
#if defined(CPU_MODEL_NRF52805XXAA)
|
||||||
#define CPU_IRQ_NUMOF (29U)
|
#define CPU_IRQ_NUMOF (26U)
|
||||||
|
#elif defined(CPU_MODEL_NRF52810XXAA)
|
||||||
|
#define CPU_IRQ_NUMOF (30U)
|
||||||
|
#elif defined(CPU_MODEL_NRF52811XXAA)
|
||||||
|
#define CPU_IRQ_NUMOF (30U)
|
||||||
|
#elif defined(CPU_MODEL_NRF52820XXAA)
|
||||||
|
#define CPU_IRQ_NUMOF (40U)
|
||||||
#elif defined(CPU_MODEL_NRF52832XXAA)
|
#elif defined(CPU_MODEL_NRF52832XXAA)
|
||||||
#define CPU_IRQ_NUMOF (38U)
|
#define CPU_IRQ_NUMOF (39U)
|
||||||
|
#elif defined(CPU_MODEL_NRF52833XXAA)
|
||||||
|
#define CPU_IRQ_NUMOF (48U)
|
||||||
#elif defined(CPU_MODEL_NRF52840XXAA)
|
#elif defined(CPU_MODEL_NRF52840XXAA)
|
||||||
#define CPU_IRQ_NUMOF (46U)
|
#define CPU_IRQ_NUMOF (48U)
|
||||||
#endif
|
#endif
|
||||||
/** @} */
|
/** @} */
|
||||||
|
|
||||||
@ -69,6 +93,12 @@ extern "C" {
|
|||||||
#ifdef BPROT_PRESENT
|
#ifdef BPROT_PRESENT
|
||||||
#define FLASHPAGE_SIZE BPROT_REGIONS_SIZE
|
#define FLASHPAGE_SIZE BPROT_REGIONS_SIZE
|
||||||
#define FLASHPAGE_NUMOF BPROT_REGIONS_NUM
|
#define FLASHPAGE_NUMOF BPROT_REGIONS_NUM
|
||||||
|
#elif defined(CPU_MODEL_NRF52820XXAA)
|
||||||
|
#define FLASHPAGE_SIZE (4096U)
|
||||||
|
#define FLASHPAGE_NUMOF (64U)
|
||||||
|
#elif defined(CPU_MODEL_NRF52833XXAA)
|
||||||
|
#define FLASHPAGE_SIZE (4096U)
|
||||||
|
#define FLASHPAGE_NUMOF (128U)
|
||||||
#elif defined(CPU_MODEL_NRF52840XXAA)
|
#elif defined(CPU_MODEL_NRF52840XXAA)
|
||||||
#define FLASHPAGE_SIZE (4096U)
|
#define FLASHPAGE_SIZE (4096U)
|
||||||
#define FLASHPAGE_NUMOF (256U)
|
#define FLASHPAGE_NUMOF (256U)
|
||||||
|
|||||||
@ -174,12 +174,14 @@ typedef enum {
|
|||||||
* always start with channel 0 to x and the undefined ones are from x+1
|
* always start with channel 0 to x and the undefined ones are from x+1
|
||||||
* to PWM_CHANNELS.
|
* to PWM_CHANNELS.
|
||||||
*/
|
*/
|
||||||
|
#if defined(PWM_PRESENT) || DOXYGEN
|
||||||
typedef struct {
|
typedef struct {
|
||||||
NRF_PWM_Type *dev; /**< PWM device descriptor */
|
NRF_PWM_Type *dev; /**< PWM device descriptor */
|
||||||
gpio_t pin[PWM_CHANNELS]; /**< PWM out pins */
|
gpio_t pin[PWM_CHANNELS]; /**< PWM out pins */
|
||||||
} pwm_conf_t;
|
} pwm_conf_t;
|
||||||
|
#endif
|
||||||
|
|
||||||
#if defined(CPU_MODEL_NRF52811XXAA) || defined(CPU_MODEL_NRF52840XXAA)
|
#if !defined(CPU_MODEL_NRF52832XXAA)
|
||||||
/**
|
/**
|
||||||
* @brief Structure for UART configuration data
|
* @brief Structure for UART configuration data
|
||||||
*/
|
*/
|
||||||
|
|||||||
1765
cpu/nrf52/include/vendor/nrf52805.h
vendored
Normal file
1765
cpu/nrf52/include/vendor/nrf52805.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
10267
cpu/nrf52/include/vendor/nrf52805_bitfields.h
vendored
Normal file
10267
cpu/nrf52/include/vendor/nrf52805_bitfields.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
217
cpu/nrf52/include/vendor/nrf52805_peripherals.h
vendored
Normal file
217
cpu/nrf52/include/vendor/nrf52805_peripherals.h
vendored
Normal file
@ -0,0 +1,217 @@
|
|||||||
|
/*
|
||||||
|
|
||||||
|
Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without
|
||||||
|
modification, are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer in the
|
||||||
|
documentation and/or other materials provided with the distribution.
|
||||||
|
|
||||||
|
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||||
|
contributors may be used to endorse or promote products derived from this
|
||||||
|
software without specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||||
|
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _NRF52805_PERIPHERALS_H
|
||||||
|
#define _NRF52805_PERIPHERALS_H
|
||||||
|
|
||||||
|
|
||||||
|
/* Clock Peripheral */
|
||||||
|
#define CLOCK_PRESENT
|
||||||
|
#define CLOCK_COUNT 1
|
||||||
|
|
||||||
|
/* Power Peripheral */
|
||||||
|
#define POWER_PRESENT
|
||||||
|
#define POWER_COUNT 1
|
||||||
|
|
||||||
|
#define POWER_FEATURE_RAM_REGISTERS_PRESENT
|
||||||
|
#define POWER_FEATURE_RAM_REGISTERS_COUNT 3
|
||||||
|
|
||||||
|
/* Non-Volatile Memory Controller */
|
||||||
|
#define NVMC_PRESENT
|
||||||
|
#define NVMC_COUNT 1
|
||||||
|
|
||||||
|
/* Systick timer */
|
||||||
|
#define SYSTICK_PRESENT
|
||||||
|
#define SYSTICK_COUNT 1
|
||||||
|
|
||||||
|
/* Software Interrupts */
|
||||||
|
#define SWI_PRESENT
|
||||||
|
#define SWI_COUNT 6
|
||||||
|
|
||||||
|
/* GPIO */
|
||||||
|
#define GPIO_PRESENT
|
||||||
|
#define GPIO_COUNT 1
|
||||||
|
|
||||||
|
#define P0_PIN_NUM 32
|
||||||
|
|
||||||
|
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
|
||||||
|
|
||||||
|
/* MPU and BPROT */
|
||||||
|
#define BPROT_PRESENT
|
||||||
|
|
||||||
|
#define BPROT_REGIONS_SIZE 4096
|
||||||
|
#define BPROT_REGIONS_NUM 48
|
||||||
|
|
||||||
|
/* Radio */
|
||||||
|
#define RADIO_PRESENT
|
||||||
|
#define RADIO_COUNT 1
|
||||||
|
|
||||||
|
#define RADIO_EASYDMA_MAXCNT_SIZE 8
|
||||||
|
|
||||||
|
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
|
||||||
|
|
||||||
|
/* Accelerated Address Resolver */
|
||||||
|
#define AAR_PRESENT
|
||||||
|
#define AAR_COUNT 1
|
||||||
|
|
||||||
|
#define AAR_MAX_IRK_NUM 16
|
||||||
|
|
||||||
|
/* AES Electronic CodeBook mode encryption */
|
||||||
|
#define ECB_PRESENT
|
||||||
|
#define ECB_COUNT 1
|
||||||
|
|
||||||
|
/* AES CCM mode encryption */
|
||||||
|
#define CCM_PRESENT
|
||||||
|
#define CCM_COUNT 1
|
||||||
|
|
||||||
|
/* Peripheral to Peripheral Interconnect */
|
||||||
|
#define PPI_PRESENT
|
||||||
|
#define PPI_COUNT 1
|
||||||
|
|
||||||
|
#define PPI_CH_NUM 10
|
||||||
|
#define PPI_FIXED_CH_NUM 12
|
||||||
|
#define PPI_GROUP_NUM 6
|
||||||
|
#define PPI_FEATURE_FORKS_PRESENT
|
||||||
|
|
||||||
|
/* Event Generator Unit */
|
||||||
|
#define EGU_PRESENT
|
||||||
|
#define EGU_COUNT 2
|
||||||
|
|
||||||
|
#define EGU0_CH_NUM 16
|
||||||
|
#define EGU1_CH_NUM 16
|
||||||
|
|
||||||
|
/* Timer/Counter */
|
||||||
|
#define TIMER_PRESENT
|
||||||
|
#define TIMER_COUNT 3
|
||||||
|
|
||||||
|
#define TIMER0_MAX_SIZE 32
|
||||||
|
#define TIMER1_MAX_SIZE 32
|
||||||
|
#define TIMER2_MAX_SIZE 32
|
||||||
|
|
||||||
|
#define TIMER0_CC_NUM 4
|
||||||
|
#define TIMER1_CC_NUM 4
|
||||||
|
#define TIMER2_CC_NUM 4
|
||||||
|
|
||||||
|
/* Real Time Counter */
|
||||||
|
#define RTC_PRESENT
|
||||||
|
#define RTC_COUNT 2
|
||||||
|
|
||||||
|
#define RTC0_CC_NUM 3
|
||||||
|
#define RTC1_CC_NUM 4
|
||||||
|
|
||||||
|
/* RNG */
|
||||||
|
#define RNG_PRESENT
|
||||||
|
#define RNG_COUNT 1
|
||||||
|
|
||||||
|
/* Watchdog Timer */
|
||||||
|
#define WDT_PRESENT
|
||||||
|
#define WDT_COUNT 1
|
||||||
|
|
||||||
|
/* Temperature Sensor */
|
||||||
|
#define TEMP_PRESENT
|
||||||
|
#define TEMP_COUNT 1
|
||||||
|
|
||||||
|
/* Serial Peripheral Interface Master */
|
||||||
|
#define SPI_PRESENT
|
||||||
|
#define SPI_COUNT 2
|
||||||
|
|
||||||
|
/* Serial Peripheral Interface Master with DMA */
|
||||||
|
#define SPIM_PRESENT
|
||||||
|
#define SPIM_COUNT 2
|
||||||
|
|
||||||
|
#define SPIM0_MAX_DATARATE 8
|
||||||
|
#define SPIM1_MAX_DATARATE 8
|
||||||
|
|
||||||
|
#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||||
|
#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||||
|
|
||||||
|
#define SPIM0_FEATURE_DCX_PRESENT 0
|
||||||
|
#define SPIM1_FEATURE_DCX_PRESENT 0
|
||||||
|
|
||||||
|
#define SPIM0_FEATURE_RXDELAY_PRESENT 0
|
||||||
|
#define SPIM1_FEATURE_RXDELAY_PRESENT 0
|
||||||
|
|
||||||
|
#define SPIM0_EASYDMA_MAXCNT_SIZE 14
|
||||||
|
#define SPIM1_EASYDMA_MAXCNT_SIZE 14
|
||||||
|
|
||||||
|
/* Serial Peripheral Interface Slave with DMA*/
|
||||||
|
#define SPIS_PRESENT
|
||||||
|
#define SPIS_COUNT 2
|
||||||
|
|
||||||
|
#define SPIS0_EASYDMA_MAXCNT_SIZE 14
|
||||||
|
#define SPIS1_EASYDMA_MAXCNT_SIZE 14
|
||||||
|
|
||||||
|
/* Two Wire Interface Master */
|
||||||
|
#define TWI_PRESENT
|
||||||
|
#define TWI_COUNT 1
|
||||||
|
|
||||||
|
/* Two Wire Interface Master with DMA */
|
||||||
|
#define TWIM_PRESENT
|
||||||
|
#define TWIM_COUNT 1
|
||||||
|
|
||||||
|
#define TWIM0_EASYDMA_MAXCNT_SIZE 14
|
||||||
|
|
||||||
|
/* Two Wire Interface Slave with DMA */
|
||||||
|
#define TWIS_PRESENT
|
||||||
|
#define TWIS_COUNT 1
|
||||||
|
|
||||||
|
#define TWIS0_EASYDMA_MAXCNT_SIZE 14
|
||||||
|
|
||||||
|
/* Universal Asynchronous Receiver-Transmitter */
|
||||||
|
#define UART_PRESENT
|
||||||
|
#define UART_COUNT 1
|
||||||
|
|
||||||
|
/* Universal Asynchronous Receiver-Transmitter with DMA */
|
||||||
|
#define UARTE_PRESENT
|
||||||
|
#define UARTE_COUNT 1
|
||||||
|
|
||||||
|
#define UARTE0_EASYDMA_MAXCNT_SIZE 14
|
||||||
|
|
||||||
|
/* Successive Approximation Analog to Digital Converter */
|
||||||
|
#define SAADC_PRESENT
|
||||||
|
#define SAADC_COUNT 1
|
||||||
|
|
||||||
|
#define SAADC_EASYDMA_MAXCNT_SIZE 15
|
||||||
|
|
||||||
|
#define SAADC_CH_NUM 8
|
||||||
|
|
||||||
|
/* GPIO Tasks and Events */
|
||||||
|
#define GPIOTE_PRESENT
|
||||||
|
#define GPIOTE_COUNT 1
|
||||||
|
|
||||||
|
#define GPIOTE_CH_NUM 8
|
||||||
|
|
||||||
|
#define GPIOTE_FEATURE_SET_PRESENT
|
||||||
|
#define GPIOTE_FEATURE_CLR_PRESENT
|
||||||
|
|
||||||
|
|
||||||
|
#endif // _NRF52805_PERIPHERALS_H
|
||||||
2004
cpu/nrf52/include/vendor/nrf52810.h
vendored
Normal file
2004
cpu/nrf52/include/vendor/nrf52810.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
11344
cpu/nrf52/include/vendor/nrf52810_bitfields.h
vendored
Normal file
11344
cpu/nrf52/include/vendor/nrf52810_bitfields.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
233
cpu/nrf52/include/vendor/nrf52810_peripherals.h
vendored
Normal file
233
cpu/nrf52/include/vendor/nrf52810_peripherals.h
vendored
Normal file
@ -0,0 +1,233 @@
|
|||||||
|
/*
|
||||||
|
|
||||||
|
Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without
|
||||||
|
modification, are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer in the
|
||||||
|
documentation and/or other materials provided with the distribution.
|
||||||
|
|
||||||
|
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||||
|
contributors may be used to endorse or promote products derived from this
|
||||||
|
software without specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||||
|
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _NRF52810_PERIPHERALS_H
|
||||||
|
#define _NRF52810_PERIPHERALS_H
|
||||||
|
|
||||||
|
|
||||||
|
/* Clock Peripheral */
|
||||||
|
#define CLOCK_PRESENT
|
||||||
|
#define CLOCK_COUNT 1
|
||||||
|
|
||||||
|
/* Power Peripheral */
|
||||||
|
#define POWER_PRESENT
|
||||||
|
#define POWER_COUNT 1
|
||||||
|
|
||||||
|
#define POWER_FEATURE_RAM_REGISTERS_PRESENT
|
||||||
|
#define POWER_FEATURE_RAM_REGISTERS_COUNT 3
|
||||||
|
|
||||||
|
/* Non-Volatile Memory Controller */
|
||||||
|
#define NVMC_PRESENT
|
||||||
|
#define NVMC_COUNT 1
|
||||||
|
|
||||||
|
/* Systick timer */
|
||||||
|
#define SYSTICK_PRESENT
|
||||||
|
#define SYSTICK_COUNT 1
|
||||||
|
|
||||||
|
/* Software Interrupts */
|
||||||
|
#define SWI_PRESENT
|
||||||
|
#define SWI_COUNT 6
|
||||||
|
|
||||||
|
/* GPIO */
|
||||||
|
#define GPIO_PRESENT
|
||||||
|
#define GPIO_COUNT 1
|
||||||
|
|
||||||
|
#define P0_PIN_NUM 32
|
||||||
|
|
||||||
|
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
|
||||||
|
|
||||||
|
/* MPU and BPROT */
|
||||||
|
#define BPROT_PRESENT
|
||||||
|
|
||||||
|
#define BPROT_REGIONS_SIZE 4096
|
||||||
|
#define BPROT_REGIONS_NUM 48
|
||||||
|
|
||||||
|
/* Radio */
|
||||||
|
#define RADIO_PRESENT
|
||||||
|
#define RADIO_COUNT 1
|
||||||
|
|
||||||
|
#define RADIO_EASYDMA_MAXCNT_SIZE 8
|
||||||
|
|
||||||
|
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
|
||||||
|
|
||||||
|
/* Accelerated Address Resolver */
|
||||||
|
#define AAR_PRESENT
|
||||||
|
#define AAR_COUNT 1
|
||||||
|
|
||||||
|
#define AAR_MAX_IRK_NUM 16
|
||||||
|
|
||||||
|
/* AES Electronic CodeBook mode encryption */
|
||||||
|
#define ECB_PRESENT
|
||||||
|
#define ECB_COUNT 1
|
||||||
|
|
||||||
|
/* AES CCM mode encryption */
|
||||||
|
#define CCM_PRESENT
|
||||||
|
#define CCM_COUNT 1
|
||||||
|
|
||||||
|
/* Peripheral to Peripheral Interconnect */
|
||||||
|
#define PPI_PRESENT
|
||||||
|
#define PPI_COUNT 1
|
||||||
|
|
||||||
|
#define PPI_CH_NUM 20
|
||||||
|
#define PPI_FIXED_CH_NUM 12
|
||||||
|
#define PPI_GROUP_NUM 6
|
||||||
|
#define PPI_FEATURE_FORKS_PRESENT
|
||||||
|
|
||||||
|
/* Event Generator Unit */
|
||||||
|
#define EGU_PRESENT
|
||||||
|
#define EGU_COUNT 2
|
||||||
|
|
||||||
|
#define EGU0_CH_NUM 16
|
||||||
|
#define EGU1_CH_NUM 16
|
||||||
|
|
||||||
|
/* Timer/Counter */
|
||||||
|
#define TIMER_PRESENT
|
||||||
|
#define TIMER_COUNT 3
|
||||||
|
|
||||||
|
#define TIMER0_MAX_SIZE 32
|
||||||
|
#define TIMER1_MAX_SIZE 32
|
||||||
|
#define TIMER2_MAX_SIZE 32
|
||||||
|
|
||||||
|
#define TIMER0_CC_NUM 4
|
||||||
|
#define TIMER1_CC_NUM 4
|
||||||
|
#define TIMER2_CC_NUM 4
|
||||||
|
|
||||||
|
/* Real Time Counter */
|
||||||
|
#define RTC_PRESENT
|
||||||
|
#define RTC_COUNT 2
|
||||||
|
|
||||||
|
#define RTC0_CC_NUM 3
|
||||||
|
#define RTC1_CC_NUM 4
|
||||||
|
|
||||||
|
/* RNG */
|
||||||
|
#define RNG_PRESENT
|
||||||
|
#define RNG_COUNT 1
|
||||||
|
|
||||||
|
/* Watchdog Timer */
|
||||||
|
#define WDT_PRESENT
|
||||||
|
#define WDT_COUNT 1
|
||||||
|
|
||||||
|
/* Temperature Sensor */
|
||||||
|
#define TEMP_PRESENT
|
||||||
|
#define TEMP_COUNT 1
|
||||||
|
|
||||||
|
/* Serial Peripheral Interface Master */
|
||||||
|
#define SPI_PRESENT
|
||||||
|
#define SPI_COUNT 1
|
||||||
|
|
||||||
|
/* Serial Peripheral Interface Master with DMA */
|
||||||
|
#define SPIM_PRESENT
|
||||||
|
#define SPIM_COUNT 1
|
||||||
|
|
||||||
|
#define SPIM0_MAX_DATARATE 8
|
||||||
|
|
||||||
|
#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||||
|
|
||||||
|
#define SPIM0_FEATURE_DCX_PRESENT 0
|
||||||
|
|
||||||
|
#define SPIM0_FEATURE_RXDELAY_PRESENT 0
|
||||||
|
|
||||||
|
#define SPIM0_EASYDMA_MAXCNT_SIZE 10
|
||||||
|
|
||||||
|
/* Serial Peripheral Interface Slave with DMA*/
|
||||||
|
#define SPIS_PRESENT
|
||||||
|
#define SPIS_COUNT 1
|
||||||
|
|
||||||
|
#define SPIS0_EASYDMA_MAXCNT_SIZE 10
|
||||||
|
|
||||||
|
/* Two Wire Interface Master */
|
||||||
|
#define TWI_PRESENT
|
||||||
|
#define TWI_COUNT 1
|
||||||
|
|
||||||
|
/* Two Wire Interface Master with DMA */
|
||||||
|
#define TWIM_PRESENT
|
||||||
|
#define TWIM_COUNT 1
|
||||||
|
|
||||||
|
#define TWIM0_EASYDMA_MAXCNT_SIZE 10
|
||||||
|
|
||||||
|
/* Two Wire Interface Slave with DMA */
|
||||||
|
#define TWIS_PRESENT
|
||||||
|
#define TWIS_COUNT 1
|
||||||
|
|
||||||
|
#define TWIS0_EASYDMA_MAXCNT_SIZE 10
|
||||||
|
|
||||||
|
/* Universal Asynchronous Receiver-Transmitter */
|
||||||
|
#define UART_PRESENT
|
||||||
|
#define UART_COUNT 1
|
||||||
|
|
||||||
|
/* Universal Asynchronous Receiver-Transmitter with DMA */
|
||||||
|
#define UARTE_PRESENT
|
||||||
|
#define UARTE_COUNT 1
|
||||||
|
|
||||||
|
#define UARTE0_EASYDMA_MAXCNT_SIZE 10
|
||||||
|
|
||||||
|
/* Quadrature Decoder */
|
||||||
|
#define QDEC_PRESENT
|
||||||
|
#define QDEC_COUNT 1
|
||||||
|
|
||||||
|
/* Successive Approximation Analog to Digital Converter */
|
||||||
|
#define SAADC_PRESENT
|
||||||
|
#define SAADC_COUNT 1
|
||||||
|
|
||||||
|
#define SAADC_EASYDMA_MAXCNT_SIZE 15
|
||||||
|
|
||||||
|
#define SAADC_CH_NUM 8
|
||||||
|
|
||||||
|
/* GPIO Tasks and Events */
|
||||||
|
#define GPIOTE_PRESENT
|
||||||
|
#define GPIOTE_COUNT 1
|
||||||
|
|
||||||
|
#define GPIOTE_CH_NUM 8
|
||||||
|
|
||||||
|
#define GPIOTE_FEATURE_SET_PRESENT
|
||||||
|
#define GPIOTE_FEATURE_CLR_PRESENT
|
||||||
|
|
||||||
|
/* Comparator */
|
||||||
|
#define COMP_PRESENT
|
||||||
|
#define COMP_COUNT 1
|
||||||
|
|
||||||
|
/* Pulse Width Modulator */
|
||||||
|
#define PWM_PRESENT
|
||||||
|
#define PWM_COUNT 1
|
||||||
|
|
||||||
|
#define PWM0_CH_NUM 4
|
||||||
|
|
||||||
|
#define PWM0_EASYDMA_MAXCNT_SIZE 15
|
||||||
|
|
||||||
|
/* Pulse Density Modulator */
|
||||||
|
#define PDM_PRESENT
|
||||||
|
#define PDM_COUNT 1
|
||||||
|
|
||||||
|
#define PDM_EASYDMA_MAXCNT_SIZE 15
|
||||||
|
|
||||||
|
|
||||||
|
#endif // _NRF52810_PERIPHERALS_H
|
||||||
@ -78,6 +78,8 @@ POSSIBILITY OF SUCH DAMAGE.
|
|||||||
#define RADIO_EASYDMA_MAXCNT_SIZE 8
|
#define RADIO_EASYDMA_MAXCNT_SIZE 8
|
||||||
#define RADIO_FEATURE_IEEE_802_15_4_PRESENT
|
#define RADIO_FEATURE_IEEE_802_15_4_PRESENT
|
||||||
|
|
||||||
|
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
|
||||||
|
|
||||||
/* Accelerated Address Resolver */
|
/* Accelerated Address Resolver */
|
||||||
#define AAR_PRESENT
|
#define AAR_PRESENT
|
||||||
#define AAR_COUNT 1
|
#define AAR_COUNT 1
|
||||||
|
|||||||
2095
cpu/nrf52/include/vendor/nrf52820.h
vendored
Normal file
2095
cpu/nrf52/include/vendor/nrf52820.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
12087
cpu/nrf52/include/vendor/nrf52820_bitfields.h
vendored
Normal file
12087
cpu/nrf52/include/vendor/nrf52820_bitfields.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
231
cpu/nrf52/include/vendor/nrf52820_peripherals.h
vendored
Normal file
231
cpu/nrf52/include/vendor/nrf52820_peripherals.h
vendored
Normal file
@ -0,0 +1,231 @@
|
|||||||
|
/*
|
||||||
|
|
||||||
|
Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without
|
||||||
|
modification, are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer in the
|
||||||
|
documentation and/or other materials provided with the distribution.
|
||||||
|
|
||||||
|
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||||
|
contributors may be used to endorse or promote products derived from this
|
||||||
|
software without specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||||
|
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _NRF52820_PERIPHERALS_H
|
||||||
|
#define _NRF52820_PERIPHERALS_H
|
||||||
|
|
||||||
|
/* Clock Peripheral */
|
||||||
|
#define CLOCK_PRESENT
|
||||||
|
#define CLOCK_COUNT 1
|
||||||
|
|
||||||
|
/* Power Peripheral */
|
||||||
|
#define POWER_PRESENT
|
||||||
|
#define POWER_COUNT 1
|
||||||
|
|
||||||
|
#define POWER_FEATURE_RAM_REGISTERS_PRESENT
|
||||||
|
#define POWER_FEATURE_RAM_REGISTERS_COUNT 4
|
||||||
|
|
||||||
|
#define POWER_FEATURE_VDDH_PRESENT
|
||||||
|
|
||||||
|
/* Non-Volatile Memory Controller */
|
||||||
|
#define NVMC_PRESENT
|
||||||
|
#define NVMC_COUNT 1
|
||||||
|
|
||||||
|
/* Systick timer */
|
||||||
|
#define SYSTICK_PRESENT
|
||||||
|
#define SYSTICK_COUNT 1
|
||||||
|
|
||||||
|
/* Software Interrupts */
|
||||||
|
#define SWI_PRESENT
|
||||||
|
#define SWI_COUNT 6
|
||||||
|
|
||||||
|
/* GPIO */
|
||||||
|
#define GPIO_PRESENT
|
||||||
|
#define GPIO_COUNT 1
|
||||||
|
|
||||||
|
#define P0_PIN_NUM (18)
|
||||||
|
#define P0_FEATURE_PINS_PRESENT (nrf52_errata_230() ? 0xF0168E3Ful : 0x7017C1FFul)
|
||||||
|
|
||||||
|
/* ACL */
|
||||||
|
#define ACL_PRESENT
|
||||||
|
|
||||||
|
#define ACL_REGIONS_COUNT 8
|
||||||
|
|
||||||
|
/* Radio */
|
||||||
|
#define RADIO_PRESENT
|
||||||
|
#define RADIO_COUNT 1
|
||||||
|
|
||||||
|
#define RADIO_EASYDMA_MAXCNT_SIZE 16
|
||||||
|
#define RADIO_FEATURE_IEEE_802_15_4_PRESENT
|
||||||
|
|
||||||
|
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos8dBm
|
||||||
|
|
||||||
|
/* Accelerated Address Resolver */
|
||||||
|
#define AAR_PRESENT
|
||||||
|
#define AAR_COUNT 1
|
||||||
|
|
||||||
|
#define AAR_MAX_IRK_NUM 16
|
||||||
|
|
||||||
|
/* AES Electronic CodeBook mode encryption */
|
||||||
|
#define ECB_PRESENT
|
||||||
|
#define ECB_COUNT 1
|
||||||
|
|
||||||
|
/* AES CCM mode encryption */
|
||||||
|
#define CCM_PRESENT
|
||||||
|
#define CCM_COUNT 1
|
||||||
|
|
||||||
|
/* Peripheral to Peripheral Interconnect */
|
||||||
|
#define PPI_PRESENT
|
||||||
|
#define PPI_COUNT 1
|
||||||
|
|
||||||
|
#define PPI_CH_NUM 20
|
||||||
|
#define PPI_FIXED_CH_NUM 12
|
||||||
|
#define PPI_GROUP_NUM 6
|
||||||
|
#define PPI_FEATURE_FORKS_PRESENT
|
||||||
|
|
||||||
|
/* Event Generator Unit */
|
||||||
|
#define EGU_PRESENT
|
||||||
|
#define EGU_COUNT 6
|
||||||
|
|
||||||
|
#define EGU0_CH_NUM 16
|
||||||
|
#define EGU1_CH_NUM 16
|
||||||
|
#define EGU2_CH_NUM 16
|
||||||
|
#define EGU3_CH_NUM 16
|
||||||
|
#define EGU4_CH_NUM 16
|
||||||
|
#define EGU5_CH_NUM 16
|
||||||
|
|
||||||
|
/* Timer/Counter */
|
||||||
|
#define TIMER_PRESENT
|
||||||
|
#define TIMER_COUNT 4
|
||||||
|
|
||||||
|
#define TIMER0_MAX_SIZE 32
|
||||||
|
#define TIMER1_MAX_SIZE 32
|
||||||
|
#define TIMER2_MAX_SIZE 32
|
||||||
|
#define TIMER3_MAX_SIZE 32
|
||||||
|
|
||||||
|
#define TIMER0_CC_NUM 4
|
||||||
|
#define TIMER1_CC_NUM 4
|
||||||
|
#define TIMER2_CC_NUM 4
|
||||||
|
#define TIMER3_CC_NUM 6
|
||||||
|
|
||||||
|
/* Real Time Counter */
|
||||||
|
#define RTC_PRESENT
|
||||||
|
#define RTC_COUNT 2
|
||||||
|
|
||||||
|
#define RTC0_CC_NUM 3
|
||||||
|
#define RTC1_CC_NUM 4
|
||||||
|
|
||||||
|
/* RNG */
|
||||||
|
#define RNG_PRESENT
|
||||||
|
#define RNG_COUNT 1
|
||||||
|
|
||||||
|
/* Watchdog Timer */
|
||||||
|
#define WDT_PRESENT
|
||||||
|
#define WDT_COUNT 1
|
||||||
|
|
||||||
|
/* Temperature Sensor */
|
||||||
|
#define TEMP_PRESENT
|
||||||
|
#define TEMP_COUNT 1
|
||||||
|
|
||||||
|
/* Serial Peripheral Interface Master */
|
||||||
|
#define SPI_PRESENT
|
||||||
|
#define SPI_COUNT 2
|
||||||
|
|
||||||
|
/* Serial Peripheral Interface Master with DMA */
|
||||||
|
#define SPIM_PRESENT
|
||||||
|
#define SPIM_COUNT 2
|
||||||
|
|
||||||
|
#define SPIM0_MAX_DATARATE 8
|
||||||
|
#define SPIM1_MAX_DATARATE 8
|
||||||
|
|
||||||
|
#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||||
|
#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||||
|
|
||||||
|
#define SPIM0_FEATURE_DCX_PRESENT 0
|
||||||
|
#define SPIM1_FEATURE_DCX_PRESENT 0
|
||||||
|
|
||||||
|
#define SPIM0_FEATURE_RXDELAY_PRESENT 0
|
||||||
|
#define SPIM1_FEATURE_RXDELAY_PRESENT 0
|
||||||
|
|
||||||
|
#define SPIM0_EASYDMA_MAXCNT_SIZE 16
|
||||||
|
#define SPIM1_EASYDMA_MAXCNT_SIZE 16
|
||||||
|
|
||||||
|
/* Serial Peripheral Interface Slave with DMA*/
|
||||||
|
#define SPIS_PRESENT
|
||||||
|
#define SPIS_COUNT 2
|
||||||
|
|
||||||
|
#define SPIS0_EASYDMA_MAXCNT_SIZE 16
|
||||||
|
#define SPIS1_EASYDMA_MAXCNT_SIZE 16
|
||||||
|
|
||||||
|
/* Two Wire Interface Master */
|
||||||
|
#define TWI_PRESENT
|
||||||
|
#define TWI_COUNT 2
|
||||||
|
|
||||||
|
/* Two Wire Interface Master with DMA */
|
||||||
|
#define TWIM_PRESENT
|
||||||
|
#define TWIM_COUNT 2
|
||||||
|
|
||||||
|
#define TWIM0_EASYDMA_MAXCNT_SIZE 16
|
||||||
|
#define TWIM1_EASYDMA_MAXCNT_SIZE 16
|
||||||
|
|
||||||
|
/* Two Wire Interface Slave with DMA */
|
||||||
|
#define TWIS_PRESENT
|
||||||
|
#define TWIS_COUNT 2
|
||||||
|
|
||||||
|
#define TWIS0_EASYDMA_MAXCNT_SIZE 16
|
||||||
|
#define TWIS1_EASYDMA_MAXCNT_SIZE 16
|
||||||
|
|
||||||
|
/* Universal Asynchronous Receiver-Transmitter */
|
||||||
|
#define UART_PRESENT
|
||||||
|
#define UART_COUNT 1
|
||||||
|
|
||||||
|
/* Universal Asynchronous Receiver-Transmitter with DMA */
|
||||||
|
#define UARTE_PRESENT
|
||||||
|
#define UARTE_COUNT 1
|
||||||
|
|
||||||
|
#define UARTE0_EASYDMA_MAXCNT_SIZE 16
|
||||||
|
|
||||||
|
/* Quadrature Decoder */
|
||||||
|
#define QDEC_PRESENT
|
||||||
|
#define QDEC_COUNT 1
|
||||||
|
|
||||||
|
/* GPIO Tasks and Events */
|
||||||
|
#define GPIOTE_PRESENT
|
||||||
|
#define GPIOTE_COUNT 1
|
||||||
|
|
||||||
|
#define GPIOTE_CH_NUM 8
|
||||||
|
|
||||||
|
#define GPIOTE_FEATURE_SET_PRESENT
|
||||||
|
#define GPIOTE_FEATURE_CLR_PRESENT
|
||||||
|
|
||||||
|
/* Comparator */
|
||||||
|
#define COMP_PRESENT
|
||||||
|
#define COMP_COUNT 1
|
||||||
|
|
||||||
|
|
||||||
|
/* Universal Serial Bus Device */
|
||||||
|
#define USBD_PRESENT
|
||||||
|
#define USBD_COUNT 1
|
||||||
|
|
||||||
|
#define USBD_EASYDMA_MAXCNT_SIZE 7
|
||||||
|
|
||||||
|
#endif // _NRF52820_PERIPHERALS_H
|
||||||
@ -87,6 +87,8 @@ POSSIBILITY OF SUCH DAMAGE.
|
|||||||
|
|
||||||
#define RADIO_EASYDMA_MAXCNT_SIZE 8
|
#define RADIO_EASYDMA_MAXCNT_SIZE 8
|
||||||
|
|
||||||
|
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
|
||||||
|
|
||||||
/* Accelerated Address Resolver */
|
/* Accelerated Address Resolver */
|
||||||
#define AAR_PRESENT
|
#define AAR_PRESENT
|
||||||
#define AAR_COUNT 1
|
#define AAR_COUNT 1
|
||||||
|
|||||||
2795
cpu/nrf52/include/vendor/nrf52833.h
vendored
Normal file
2795
cpu/nrf52/include/vendor/nrf52833.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
17076
cpu/nrf52/include/vendor/nrf52833_bitfields.h
vendored
Normal file
17076
cpu/nrf52/include/vendor/nrf52833_bitfields.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
313
cpu/nrf52/include/vendor/nrf52833_peripherals.h
vendored
Normal file
313
cpu/nrf52/include/vendor/nrf52833_peripherals.h
vendored
Normal file
@ -0,0 +1,313 @@
|
|||||||
|
/*
|
||||||
|
|
||||||
|
Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without
|
||||||
|
modification, are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer in the
|
||||||
|
documentation and/or other materials provided with the distribution.
|
||||||
|
|
||||||
|
3. Neither the name of Nordic Semiconductor ASA nor the names of its
|
||||||
|
contributors may be used to endorse or promote products derived from this
|
||||||
|
software without specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
|
||||||
|
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _NRF52833_PERIPHERALS_H
|
||||||
|
#define _NRF52833_PERIPHERALS_H
|
||||||
|
|
||||||
|
/* Clock Peripheral */
|
||||||
|
#define CLOCK_PRESENT
|
||||||
|
#define CLOCK_COUNT 1
|
||||||
|
|
||||||
|
#define CLOCK_FEATURE_LFXO_EXTENDED_DEBOUNCE_PRESENT
|
||||||
|
|
||||||
|
/* Power Peripheral */
|
||||||
|
#define POWER_PRESENT
|
||||||
|
#define POWER_COUNT 1
|
||||||
|
|
||||||
|
#define POWER_FEATURE_RAM_REGISTERS_PRESENT
|
||||||
|
#define POWER_FEATURE_RAM_REGISTERS_COUNT 9
|
||||||
|
|
||||||
|
#define POWER_FEATURE_VDDH_PRESENT
|
||||||
|
|
||||||
|
/* Non-Volatile Memory Controller */
|
||||||
|
#define NVMC_PRESENT
|
||||||
|
#define NVMC_COUNT 1
|
||||||
|
|
||||||
|
#define NVMC_FEATURE_CACHE_PRESENT
|
||||||
|
|
||||||
|
/* Floating Point Unit */
|
||||||
|
#define FPU_PRESENT
|
||||||
|
#define FPU_COUNT 1
|
||||||
|
|
||||||
|
/* Systick timer */
|
||||||
|
#define SYSTICK_PRESENT
|
||||||
|
#define SYSTICK_COUNT 1
|
||||||
|
|
||||||
|
/* Software Interrupts */
|
||||||
|
#define SWI_PRESENT
|
||||||
|
#define SWI_COUNT 6
|
||||||
|
|
||||||
|
/* Memory Watch Unit */
|
||||||
|
#define MWU_PRESENT
|
||||||
|
#define MWU_COUNT 1
|
||||||
|
|
||||||
|
/* GPIO */
|
||||||
|
#define GPIO_PRESENT
|
||||||
|
#define GPIO_COUNT 2
|
||||||
|
|
||||||
|
#define P0_PIN_NUM 32
|
||||||
|
#define P1_PIN_NUM 10
|
||||||
|
|
||||||
|
#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL
|
||||||
|
#define P1_FEATURE_PINS_PRESENT 0x000003FFUL
|
||||||
|
|
||||||
|
/* ACL */
|
||||||
|
#define ACL_PRESENT
|
||||||
|
|
||||||
|
#define ACL_REGIONS_COUNT 8
|
||||||
|
|
||||||
|
/* Radio */
|
||||||
|
#define RADIO_PRESENT
|
||||||
|
#define RADIO_COUNT 1
|
||||||
|
|
||||||
|
#define RADIO_EASYDMA_MAXCNT_SIZE 8
|
||||||
|
#define RADIO_FEATURE_IEEE_802_15_4_PRESENT
|
||||||
|
|
||||||
|
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos8dBm
|
||||||
|
|
||||||
|
/* Accelerated Address Resolver */
|
||||||
|
#define AAR_PRESENT
|
||||||
|
#define AAR_COUNT 1
|
||||||
|
|
||||||
|
#define AAR_MAX_IRK_NUM 16
|
||||||
|
|
||||||
|
/* AES Electronic CodeBook mode encryption */
|
||||||
|
#define ECB_PRESENT
|
||||||
|
#define ECB_COUNT 1
|
||||||
|
|
||||||
|
/* AES CCM mode encryption */
|
||||||
|
#define CCM_PRESENT
|
||||||
|
#define CCM_COUNT 1
|
||||||
|
|
||||||
|
/* NFC Tag */
|
||||||
|
#define NFCT_PRESENT
|
||||||
|
#define NFCT_COUNT 1
|
||||||
|
|
||||||
|
#define NFCT_EASYDMA_MAXCNT_SIZE 9
|
||||||
|
|
||||||
|
/* Peripheral to Peripheral Interconnect */
|
||||||
|
#define PPI_PRESENT
|
||||||
|
#define PPI_COUNT 1
|
||||||
|
|
||||||
|
#define PPI_CH_NUM 20
|
||||||
|
#define PPI_FIXED_CH_NUM 12
|
||||||
|
#define PPI_GROUP_NUM 6
|
||||||
|
#define PPI_FEATURE_FORKS_PRESENT
|
||||||
|
|
||||||
|
/* Event Generator Unit */
|
||||||
|
#define EGU_PRESENT
|
||||||
|
#define EGU_COUNT 6
|
||||||
|
|
||||||
|
#define EGU0_CH_NUM 16
|
||||||
|
#define EGU1_CH_NUM 16
|
||||||
|
#define EGU2_CH_NUM 16
|
||||||
|
#define EGU3_CH_NUM 16
|
||||||
|
#define EGU4_CH_NUM 16
|
||||||
|
#define EGU5_CH_NUM 16
|
||||||
|
|
||||||
|
/* Timer/Counter */
|
||||||
|
#define TIMER_PRESENT
|
||||||
|
#define TIMER_COUNT 5
|
||||||
|
|
||||||
|
#define TIMER0_MAX_SIZE 32
|
||||||
|
#define TIMER1_MAX_SIZE 32
|
||||||
|
#define TIMER2_MAX_SIZE 32
|
||||||
|
#define TIMER3_MAX_SIZE 32
|
||||||
|
#define TIMER4_MAX_SIZE 32
|
||||||
|
|
||||||
|
#define TIMER0_CC_NUM 4
|
||||||
|
#define TIMER1_CC_NUM 4
|
||||||
|
#define TIMER2_CC_NUM 4
|
||||||
|
#define TIMER3_CC_NUM 6
|
||||||
|
#define TIMER4_CC_NUM 6
|
||||||
|
|
||||||
|
/* Real Time Counter */
|
||||||
|
#define RTC_PRESENT
|
||||||
|
#define RTC_COUNT 3
|
||||||
|
|
||||||
|
#define RTC0_CC_NUM 3
|
||||||
|
#define RTC1_CC_NUM 4
|
||||||
|
#define RTC2_CC_NUM 4
|
||||||
|
|
||||||
|
/* RNG */
|
||||||
|
#define RNG_PRESENT
|
||||||
|
#define RNG_COUNT 1
|
||||||
|
|
||||||
|
/* Watchdog Timer */
|
||||||
|
#define WDT_PRESENT
|
||||||
|
#define WDT_COUNT 1
|
||||||
|
|
||||||
|
/* Temperature Sensor */
|
||||||
|
#define TEMP_PRESENT
|
||||||
|
#define TEMP_COUNT 1
|
||||||
|
|
||||||
|
/* Serial Peripheral Interface Master */
|
||||||
|
#define SPI_PRESENT
|
||||||
|
#define SPI_COUNT 3
|
||||||
|
|
||||||
|
/* Serial Peripheral Interface Master with DMA */
|
||||||
|
#define SPIM_PRESENT
|
||||||
|
#define SPIM_COUNT 4
|
||||||
|
|
||||||
|
#define SPIM0_MAX_DATARATE 8
|
||||||
|
#define SPIM1_MAX_DATARATE 8
|
||||||
|
#define SPIM2_MAX_DATARATE 8
|
||||||
|
#define SPIM3_MAX_DATARATE 32
|
||||||
|
|
||||||
|
#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||||
|
#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||||
|
#define SPIM2_FEATURE_HARDWARE_CSN_PRESENT 0
|
||||||
|
#define SPIM3_FEATURE_HARDWARE_CSN_PRESENT 1
|
||||||
|
|
||||||
|
#define SPIM0_FEATURE_DCX_PRESENT 0
|
||||||
|
#define SPIM1_FEATURE_DCX_PRESENT 0
|
||||||
|
#define SPIM2_FEATURE_DCX_PRESENT 0
|
||||||
|
#define SPIM3_FEATURE_DCX_PRESENT 1
|
||||||
|
|
||||||
|
#define SPIM0_FEATURE_RXDELAY_PRESENT 0
|
||||||
|
#define SPIM1_FEATURE_RXDELAY_PRESENT 0
|
||||||
|
#define SPIM2_FEATURE_RXDELAY_PRESENT 0
|
||||||
|
#define SPIM3_FEATURE_RXDELAY_PRESENT 1
|
||||||
|
|
||||||
|
#define SPIM0_EASYDMA_MAXCNT_SIZE 16
|
||||||
|
#define SPIM1_EASYDMA_MAXCNT_SIZE 16
|
||||||
|
#define SPIM2_EASYDMA_MAXCNT_SIZE 16
|
||||||
|
#define SPIM3_EASYDMA_MAXCNT_SIZE 16
|
||||||
|
|
||||||
|
/* Serial Peripheral Interface Slave with DMA*/
|
||||||
|
#define SPIS_PRESENT
|
||||||
|
#define SPIS_COUNT 3
|
||||||
|
|
||||||
|
#define SPIS0_EASYDMA_MAXCNT_SIZE 16
|
||||||
|
#define SPIS1_EASYDMA_MAXCNT_SIZE 16
|
||||||
|
#define SPIS2_EASYDMA_MAXCNT_SIZE 16
|
||||||
|
|
||||||
|
/* Two Wire Interface Master */
|
||||||
|
#define TWI_PRESENT
|
||||||
|
#define TWI_COUNT 2
|
||||||
|
|
||||||
|
/* Two Wire Interface Master with DMA */
|
||||||
|
#define TWIM_PRESENT
|
||||||
|
#define TWIM_COUNT 2
|
||||||
|
|
||||||
|
#define TWIM0_EASYDMA_MAXCNT_SIZE 16
|
||||||
|
#define TWIM1_EASYDMA_MAXCNT_SIZE 16
|
||||||
|
|
||||||
|
/* Two Wire Interface Slave with DMA */
|
||||||
|
#define TWIS_PRESENT
|
||||||
|
#define TWIS_COUNT 2
|
||||||
|
|
||||||
|
#define TWIS0_EASYDMA_MAXCNT_SIZE 16
|
||||||
|
#define TWIS1_EASYDMA_MAXCNT_SIZE 16
|
||||||
|
|
||||||
|
/* Universal Asynchronous Receiver-Transmitter */
|
||||||
|
#define UART_PRESENT
|
||||||
|
#define UART_COUNT 1
|
||||||
|
|
||||||
|
#define UART0_FEATURE_ODD_PARITY_PRESENT
|
||||||
|
|
||||||
|
/* Universal Asynchronous Receiver-Transmitter with DMA */
|
||||||
|
#define UARTE_PRESENT
|
||||||
|
#define UARTE_COUNT 2
|
||||||
|
|
||||||
|
#define UARTE0_EASYDMA_MAXCNT_SIZE 16
|
||||||
|
#define UARTE1_EASYDMA_MAXCNT_SIZE 16
|
||||||
|
|
||||||
|
#define UARTE0_FEATURE_ODD_PARITY_PRESENT
|
||||||
|
#define UARTE1_FEATURE_ODD_PARITY_PRESENT
|
||||||
|
|
||||||
|
/* Quadrature Decoder */
|
||||||
|
#define QDEC_PRESENT
|
||||||
|
#define QDEC_COUNT 1
|
||||||
|
|
||||||
|
/* Successive Approximation Analog to Digital Converter */
|
||||||
|
#define SAADC_PRESENT
|
||||||
|
#define SAADC_COUNT 1
|
||||||
|
|
||||||
|
#define SAADC_EASYDMA_MAXCNT_SIZE 15
|
||||||
|
|
||||||
|
#define SAADC_CH_NUM 8
|
||||||
|
|
||||||
|
/* GPIO Tasks and Events */
|
||||||
|
#define GPIOTE_PRESENT
|
||||||
|
#define GPIOTE_COUNT 1
|
||||||
|
|
||||||
|
#define GPIOTE_CH_NUM 8
|
||||||
|
|
||||||
|
#define GPIOTE_FEATURE_SET_PRESENT
|
||||||
|
#define GPIOTE_FEATURE_CLR_PRESENT
|
||||||
|
|
||||||
|
/* Low Power Comparator */
|
||||||
|
#define LPCOMP_PRESENT
|
||||||
|
#define LPCOMP_COUNT 1
|
||||||
|
|
||||||
|
#define LPCOMP_REFSEL_RESOLUTION 16
|
||||||
|
|
||||||
|
#define LPCOMP_FEATURE_HYST_PRESENT
|
||||||
|
|
||||||
|
/* Comparator */
|
||||||
|
#define COMP_PRESENT
|
||||||
|
#define COMP_COUNT 1
|
||||||
|
|
||||||
|
/* Pulse Width Modulator */
|
||||||
|
#define PWM_PRESENT
|
||||||
|
#define PWM_COUNT 4
|
||||||
|
|
||||||
|
#define PWM0_CH_NUM 4
|
||||||
|
#define PWM1_CH_NUM 4
|
||||||
|
#define PWM2_CH_NUM 4
|
||||||
|
#define PWM3_CH_NUM 4
|
||||||
|
|
||||||
|
#define PWM0_EASYDMA_MAXCNT_SIZE 15
|
||||||
|
#define PWM1_EASYDMA_MAXCNT_SIZE 15
|
||||||
|
#define PWM2_EASYDMA_MAXCNT_SIZE 15
|
||||||
|
#define PWM3_EASYDMA_MAXCNT_SIZE 15
|
||||||
|
|
||||||
|
/* Pulse Density Modulator */
|
||||||
|
#define PDM_PRESENT
|
||||||
|
#define PDM_COUNT 1
|
||||||
|
|
||||||
|
#define PDM_EASYDMA_MAXCNT_SIZE 15
|
||||||
|
|
||||||
|
/* Inter-IC Sound Interface */
|
||||||
|
#define I2S_PRESENT
|
||||||
|
#define I2S_COUNT 1
|
||||||
|
|
||||||
|
#define I2S_EASYDMA_MAXCNT_SIZE 14
|
||||||
|
|
||||||
|
/* Universal Serial Bus Device */
|
||||||
|
#define USBD_PRESENT
|
||||||
|
#define USBD_COUNT 1
|
||||||
|
|
||||||
|
#define USBD_EASYDMA_MAXCNT_SIZE 7
|
||||||
|
|
||||||
|
#endif // _NRF52833_PERIPHERALS_H
|
||||||
@ -92,6 +92,8 @@ POSSIBILITY OF SUCH DAMAGE.
|
|||||||
#define RADIO_EASYDMA_MAXCNT_SIZE 8
|
#define RADIO_EASYDMA_MAXCNT_SIZE 8
|
||||||
#define RADIO_FEATURE_IEEE_802_15_4_PRESENT
|
#define RADIO_FEATURE_IEEE_802_15_4_PRESENT
|
||||||
|
|
||||||
|
#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos8dBm
|
||||||
|
|
||||||
/* Accelerated Address Resolver */
|
/* Accelerated Address Resolver */
|
||||||
#define AAR_PRESENT
|
#define AAR_PRESENT
|
||||||
#define AAR_COUNT 1
|
#define AAR_COUNT 1
|
||||||
|
|||||||
@ -20,24 +20,37 @@
|
|||||||
*
|
*
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include "cpu.h"
|
#include "cpu.h"
|
||||||
#include "periph_cpu.h"
|
#include "periph_cpu.h"
|
||||||
|
|
||||||
/* nRF52811 ISR names */
|
#if NRF_SPIM0_BASE != NRF_TWIM0_BASE
|
||||||
#if defined(CPU_MODEL_NRF52811XXAA)
|
|
||||||
|
|
||||||
#define ISR_SPIM0 isr_spi0
|
#define ISR_SPIM0 isr_spi0
|
||||||
|
|
||||||
|
#if defined(NRF_SPIM1)
|
||||||
#define ISR_SPIM1 isr_spi1_twi0
|
#define ISR_SPIM1 isr_spi1_twi0
|
||||||
|
#else
|
||||||
|
#define ISR_SPIM1 isr_twi0
|
||||||
|
#endif
|
||||||
|
|
||||||
/* nRF52832 and nRF52840 ISR names */
|
/* nRF52832 and nRF52840 ISR names */
|
||||||
#elif (defined(CPU_MODEL_NRF52840XXAA) || defined(CPU_MODEL_NRF52832XXAA))
|
#else
|
||||||
|
|
||||||
#define ISR_SPIM0 isr_spi0_twi0
|
#define ISR_SPIM0 isr_spi0_twi0
|
||||||
#define ISR_SPIM1 isr_spi1_twi1
|
#define ISR_SPIM1 isr_spi1_twi1
|
||||||
|
|
||||||
#else
|
#endif
|
||||||
#error Unknown nrf52 MCU model
|
|
||||||
|
/**
|
||||||
|
* The vendor file is weird here. nRF52805 is the only other MCU
|
||||||
|
* that has only 1 SPI and separate 1 TWI interface, but define
|
||||||
|
* SPIM_COUNT = 2, which is in line with how it is used here.
|
||||||
|
* nRF52810 has the same set of SPI/TWI peripherals, but defines
|
||||||
|
* SPIM_COUNT = 1 which is more logical.
|
||||||
|
* Just re-define it to work around this inconsistency.
|
||||||
|
*/
|
||||||
|
#ifdef CPU_MODEL_NRF52810XXAA
|
||||||
|
#undef SPIM_COUNT
|
||||||
|
#define SPIM_COUNT 2
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
static spi_twi_irq_cb_t _irq[SPIM_COUNT];
|
static spi_twi_irq_cb_t _irq[SPIM_COUNT];
|
||||||
@ -49,9 +62,11 @@ static size_t _spi_dev2num(void *dev)
|
|||||||
if (dev == NRF_SPIM0) {
|
if (dev == NRF_SPIM0) {
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
#ifdef NRF_SPIM1
|
||||||
else if (dev == NRF_SPIM1) {
|
else if (dev == NRF_SPIM1) {
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
#ifdef NRF_SPIM2
|
#ifdef NRF_SPIM2
|
||||||
else if (dev == NRF_SPIM2) {
|
else if (dev == NRF_SPIM2) {
|
||||||
return 2;
|
return 2;
|
||||||
@ -70,16 +85,28 @@ static size_t _spi_dev2num(void *dev)
|
|||||||
|
|
||||||
static inline size_t _i2c_dev2num(void *dev)
|
static inline size_t _i2c_dev2num(void *dev)
|
||||||
{
|
{
|
||||||
|
if (NRF_SPIM0_BASE == NRF_TWIM0_BASE) {
|
||||||
return _spi_dev2num(dev);
|
return _spi_dev2num(dev);
|
||||||
|
} else {
|
||||||
|
assert(!IS_ACTIVE(NRF_TWIM1_BASE));
|
||||||
|
/* if they are not equal (nrf528105/10/11)
|
||||||
|
TWI0 is mapped to SPI1 */
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static const IRQn_Type _isr[] = {
|
static const IRQn_Type _isr[] = {
|
||||||
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn,
|
|
||||||
|
|
||||||
#ifdef CPU_MODEL_NRF52811XXAA
|
#if NRF_SPIM0_BASE == NRF_TWIM0_BASE
|
||||||
|
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn,
|
||||||
|
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn,
|
||||||
|
#else
|
||||||
|
SPIM0_SPIS0_SPI0_IRQn,
|
||||||
|
#if defined(NRF_SPIM1)
|
||||||
TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQn,
|
TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQn,
|
||||||
#else
|
#else
|
||||||
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn,
|
TWIM0_TWIS0_TWI0_IRQn,
|
||||||
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef NRF_SPIM2
|
#ifdef NRF_SPIM2
|
||||||
|
|||||||
11
cpu/nrf52/vectors/Makefile
Normal file
11
cpu/nrf52/vectors/Makefile
Normal file
@ -0,0 +1,11 @@
|
|||||||
|
MODULE = nrf52_vectors
|
||||||
|
|
||||||
|
NO_AUTO_SRC = 1
|
||||||
|
|
||||||
|
SRC_FILE = vectors_$(CPU_MODEL).c
|
||||||
|
|
||||||
|
SRCS += $(SRC_FILE)
|
||||||
|
# (file triggers compiler bug. see #5775)
|
||||||
|
SRC_NOLTO += $(SRC_FILE)
|
||||||
|
|
||||||
|
include $(RIOTBASE)/Makefile.base
|
||||||
119
cpu/nrf52/vectors/vectors_nrf52805xxaa.c
Normal file
119
cpu/nrf52/vectors/vectors_nrf52805xxaa.c
Normal file
@ -0,0 +1,119 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 2016 Freie Universität Berlin
|
||||||
|
*
|
||||||
|
* This file is subject to the terms and conditions of the GNU Lesser
|
||||||
|
* General Public License v2.1. See the file LICENSE in the top level
|
||||||
|
* directory for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @ingroup cpu_nrf52
|
||||||
|
* @{
|
||||||
|
*
|
||||||
|
* @file
|
||||||
|
* @brief nRF52805 interrupt vector definitions
|
||||||
|
*
|
||||||
|
* @author Benjamin Valentin <benpicco@googlemail.com>
|
||||||
|
*
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#include "cpu.h"
|
||||||
|
#include "vectors_cortexm.h"
|
||||||
|
|
||||||
|
/* define a local dummy handler as it needs to be in the same compilation unit
|
||||||
|
* as the alias definition */
|
||||||
|
void dummy_handler(void) {
|
||||||
|
dummy_handler_default();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* nRF52 specific interrupt vectors */
|
||||||
|
WEAK_DEFAULT void isr_power_clock(void);
|
||||||
|
WEAK_DEFAULT void isr_radio(void);
|
||||||
|
WEAK_DEFAULT void isr_uart0(void);
|
||||||
|
WEAK_DEFAULT void isr_spi0(void);
|
||||||
|
WEAK_DEFAULT void isr_spi0_twi0(void);
|
||||||
|
WEAK_DEFAULT void isr_spi1_twi0(void);
|
||||||
|
WEAK_DEFAULT void isr_spi1_twi1(void);
|
||||||
|
WEAK_DEFAULT void isr_nfct(void);
|
||||||
|
WEAK_DEFAULT void isr_gpiote(void);
|
||||||
|
WEAK_DEFAULT void isr_saadc(void);
|
||||||
|
WEAK_DEFAULT void isr_timer0(void);
|
||||||
|
WEAK_DEFAULT void isr_timer1(void);
|
||||||
|
WEAK_DEFAULT void isr_timer2(void);
|
||||||
|
WEAK_DEFAULT void isr_rtc0(void);
|
||||||
|
WEAK_DEFAULT void isr_temp(void);
|
||||||
|
WEAK_DEFAULT void isr_twi0(void);
|
||||||
|
WEAK_DEFAULT void isr_rng(void);
|
||||||
|
WEAK_DEFAULT void isr_ecb(void);
|
||||||
|
WEAK_DEFAULT void isr_ccm_aar(void);
|
||||||
|
WEAK_DEFAULT void isr_wdt(void);
|
||||||
|
WEAK_DEFAULT void isr_rtc1(void);
|
||||||
|
WEAK_DEFAULT void isr_qdec(void);
|
||||||
|
WEAK_DEFAULT void isr_lpcomp(void);
|
||||||
|
|
||||||
|
#ifndef SOFTDEVICE_PRESENT
|
||||||
|
WEAK_DEFAULT void isr_swi0(void);
|
||||||
|
#else
|
||||||
|
/* For unknown reasons, setting PendSV pending within
|
||||||
|
* the softdevice ISRs leads to a crash. This workaround
|
||||||
|
* uses swi0 as trampoline.
|
||||||
|
*/
|
||||||
|
extern void thread_yield_higher(void);
|
||||||
|
void isr_swi0(void)
|
||||||
|
{
|
||||||
|
thread_yield_higher();
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
WEAK_DEFAULT void isr_swi1(void);
|
||||||
|
WEAK_DEFAULT void isr_swi2(void);
|
||||||
|
WEAK_DEFAULT void isr_swi3(void);
|
||||||
|
WEAK_DEFAULT void isr_swi4(void);
|
||||||
|
WEAK_DEFAULT void isr_swi5(void);
|
||||||
|
WEAK_DEFAULT void isr_timer3(void);
|
||||||
|
WEAK_DEFAULT void isr_timer4(void);
|
||||||
|
WEAK_DEFAULT void isr_pwm0(void);
|
||||||
|
WEAK_DEFAULT void isr_pdm(void);
|
||||||
|
WEAK_DEFAULT void isr_mwu(void);
|
||||||
|
WEAK_DEFAULT void isr_pwm1(void);
|
||||||
|
WEAK_DEFAULT void isr_pwm2(void);
|
||||||
|
WEAK_DEFAULT void isr_spi2(void);
|
||||||
|
WEAK_DEFAULT void isr_rtc2(void);
|
||||||
|
WEAK_DEFAULT void isr_i2s(void);
|
||||||
|
|
||||||
|
#ifdef SOFTDEVICE_PRESENT
|
||||||
|
extern void SWI2_EGU2_IRQHandler(void);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* CPU specific interrupt vector table */
|
||||||
|
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
|
||||||
|
isr_power_clock, /* power_clock */
|
||||||
|
isr_radio, /* radio */
|
||||||
|
isr_uart0, /* uart0 */
|
||||||
|
isr_twi0, /* twi 0 */
|
||||||
|
isr_spi0, /* spi 0 */
|
||||||
|
(0UL), /* reserved */
|
||||||
|
isr_gpiote, /* gpiote */
|
||||||
|
isr_saadc, /* adc */
|
||||||
|
isr_timer0, /* timer0 */
|
||||||
|
isr_timer1, /* timer1 */
|
||||||
|
isr_timer2, /* timer2 */
|
||||||
|
isr_rtc0, /* rtc0 */
|
||||||
|
isr_temp, /* temp */
|
||||||
|
isr_rng, /* rng */
|
||||||
|
isr_ecb, /* ecb */
|
||||||
|
isr_ccm_aar, /* ccm_aar */
|
||||||
|
isr_wdt, /* wdt */
|
||||||
|
isr_rtc1, /* rtc1 */
|
||||||
|
isr_qdec, /* qdec */
|
||||||
|
isr_lpcomp, /* lpcomp */
|
||||||
|
isr_swi0, /* swi0 */
|
||||||
|
isr_swi1, /* swi1 */
|
||||||
|
isr_swi2, /* swi2 */
|
||||||
|
isr_swi3, /* swi3 */
|
||||||
|
isr_swi4, /* swi4 */
|
||||||
|
isr_swi5, /* swi5 */
|
||||||
|
};
|
||||||
124
cpu/nrf52/vectors/vectors_nrf52810xxaa.c
Normal file
124
cpu/nrf52/vectors/vectors_nrf52810xxaa.c
Normal file
@ -0,0 +1,124 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 2016 Freie Universität Berlin
|
||||||
|
* 2020 Philipp-Alexander Blum <philipp-blum@jakiku.de>
|
||||||
|
*
|
||||||
|
* This file is subject to the terms and conditions of the GNU Lesser
|
||||||
|
* General Public License v2.1. See the file LICENSE in the top level
|
||||||
|
* directory for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @ingroup cpu_nrf52
|
||||||
|
* @{
|
||||||
|
*
|
||||||
|
* @file
|
||||||
|
* @brief nRF52810 interrupt vector definitions
|
||||||
|
*
|
||||||
|
* @author Benjamin Valentin <benpicco@googlemail.com>
|
||||||
|
*
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#include "cpu.h"
|
||||||
|
#include "vectors_cortexm.h"
|
||||||
|
|
||||||
|
/* define a local dummy handler as it needs to be in the same compilation unit
|
||||||
|
* as the alias definition */
|
||||||
|
void dummy_handler(void) {
|
||||||
|
dummy_handler_default();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* nRF52 specific interrupt vectors */
|
||||||
|
WEAK_DEFAULT void isr_power_clock(void);
|
||||||
|
WEAK_DEFAULT void isr_radio(void);
|
||||||
|
WEAK_DEFAULT void isr_uart0(void);
|
||||||
|
WEAK_DEFAULT void isr_spi0(void);
|
||||||
|
WEAK_DEFAULT void isr_spi0_twi0(void);
|
||||||
|
WEAK_DEFAULT void isr_spi1_twi0(void);
|
||||||
|
WEAK_DEFAULT void isr_spi1_twi1(void);
|
||||||
|
WEAK_DEFAULT void isr_nfct(void);
|
||||||
|
WEAK_DEFAULT void isr_gpiote(void);
|
||||||
|
WEAK_DEFAULT void isr_saadc(void);
|
||||||
|
WEAK_DEFAULT void isr_timer0(void);
|
||||||
|
WEAK_DEFAULT void isr_timer1(void);
|
||||||
|
WEAK_DEFAULT void isr_timer2(void);
|
||||||
|
WEAK_DEFAULT void isr_rtc0(void);
|
||||||
|
WEAK_DEFAULT void isr_temp(void);
|
||||||
|
WEAK_DEFAULT void isr_twi0(void);
|
||||||
|
WEAK_DEFAULT void isr_rng(void);
|
||||||
|
WEAK_DEFAULT void isr_ecb(void);
|
||||||
|
WEAK_DEFAULT void isr_ccm_aar(void);
|
||||||
|
WEAK_DEFAULT void isr_wdt(void);
|
||||||
|
WEAK_DEFAULT void isr_rtc1(void);
|
||||||
|
WEAK_DEFAULT void isr_qdec(void);
|
||||||
|
WEAK_DEFAULT void isr_lpcomp(void);
|
||||||
|
|
||||||
|
#ifndef SOFTDEVICE_PRESENT
|
||||||
|
WEAK_DEFAULT void isr_swi0(void);
|
||||||
|
#else
|
||||||
|
/* For unknown reasons, setting PendSV pending within
|
||||||
|
* the softdevice ISRs leads to a crash. This workaround
|
||||||
|
* uses swi0 as trampoline.
|
||||||
|
*/
|
||||||
|
extern void thread_yield_higher(void);
|
||||||
|
void isr_swi0(void)
|
||||||
|
{
|
||||||
|
thread_yield_higher();
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
WEAK_DEFAULT void isr_swi1(void);
|
||||||
|
WEAK_DEFAULT void isr_swi2(void);
|
||||||
|
WEAK_DEFAULT void isr_swi3(void);
|
||||||
|
WEAK_DEFAULT void isr_swi4(void);
|
||||||
|
WEAK_DEFAULT void isr_swi5(void);
|
||||||
|
WEAK_DEFAULT void isr_timer3(void);
|
||||||
|
WEAK_DEFAULT void isr_timer4(void);
|
||||||
|
WEAK_DEFAULT void isr_pwm0(void);
|
||||||
|
WEAK_DEFAULT void isr_pdm(void);
|
||||||
|
WEAK_DEFAULT void isr_mwu(void);
|
||||||
|
WEAK_DEFAULT void isr_pwm1(void);
|
||||||
|
WEAK_DEFAULT void isr_pwm2(void);
|
||||||
|
WEAK_DEFAULT void isr_spi2(void);
|
||||||
|
WEAK_DEFAULT void isr_rtc2(void);
|
||||||
|
WEAK_DEFAULT void isr_i2s(void);
|
||||||
|
|
||||||
|
#ifdef SOFTDEVICE_PRESENT
|
||||||
|
extern void SWI2_EGU2_IRQHandler(void);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* CPU specific interrupt vector table */
|
||||||
|
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
|
||||||
|
isr_power_clock, /* power_clock */
|
||||||
|
isr_radio, /* radio */
|
||||||
|
isr_uart0, /* uart0 */
|
||||||
|
isr_twi0, /* twi 0 */
|
||||||
|
isr_spi0, /* spi 0 */
|
||||||
|
(0UL), /* reserved */
|
||||||
|
isr_gpiote, /* gpiote */
|
||||||
|
isr_saadc, /* adc */
|
||||||
|
isr_timer0, /* timer0 */
|
||||||
|
isr_timer1, /* timer1 */
|
||||||
|
isr_timer2, /* timer2 */
|
||||||
|
isr_rtc0, /* rtc0 */
|
||||||
|
isr_temp, /* temp */
|
||||||
|
isr_rng, /* rng */
|
||||||
|
isr_ecb, /* ecb */
|
||||||
|
isr_ccm_aar, /* ccm_aar */
|
||||||
|
isr_wdt, /* wdt */
|
||||||
|
isr_rtc1, /* rtc1 */
|
||||||
|
isr_qdec, /* qdec */
|
||||||
|
isr_lpcomp, /* lpcomp */
|
||||||
|
isr_swi0, /* swi0 */
|
||||||
|
isr_swi1, /* swi1 */
|
||||||
|
isr_swi2, /* swi2 */
|
||||||
|
isr_swi3, /* swi3 */
|
||||||
|
isr_swi4, /* swi4 */
|
||||||
|
isr_swi5, /* swi5 */
|
||||||
|
(0UL), /* reserved */
|
||||||
|
(0UL), /* reserved */
|
||||||
|
isr_pwm0, /* pwm 0 */
|
||||||
|
isr_pdm, /* pdm */
|
||||||
|
};
|
||||||
125
cpu/nrf52/vectors/vectors_nrf52811xxaa.c
Normal file
125
cpu/nrf52/vectors/vectors_nrf52811xxaa.c
Normal file
@ -0,0 +1,125 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 2016 Freie Universität Berlin
|
||||||
|
* 2020 Philipp-Alexander Blum <philipp-blum@jakiku.de>
|
||||||
|
*
|
||||||
|
* This file is subject to the terms and conditions of the GNU Lesser
|
||||||
|
* General Public License v2.1. See the file LICENSE in the top level
|
||||||
|
* directory for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @ingroup cpu_nrf52
|
||||||
|
* @{
|
||||||
|
*
|
||||||
|
* @file
|
||||||
|
* @brief nRF52811 interrupt vector definitions
|
||||||
|
*
|
||||||
|
* @author Philipp-Alexander Blum <philipp-blum@jakiku.de>
|
||||||
|
* @author Benjamin Valentin <benpicco@googlemail.com>
|
||||||
|
*
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#include "cpu.h"
|
||||||
|
#include "vectors_cortexm.h"
|
||||||
|
|
||||||
|
/* define a local dummy handler as it needs to be in the same compilation unit
|
||||||
|
* as the alias definition */
|
||||||
|
void dummy_handler(void) {
|
||||||
|
dummy_handler_default();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* nRF52 specific interrupt vectors */
|
||||||
|
WEAK_DEFAULT void isr_power_clock(void);
|
||||||
|
WEAK_DEFAULT void isr_radio(void);
|
||||||
|
WEAK_DEFAULT void isr_uart0(void);
|
||||||
|
WEAK_DEFAULT void isr_spi0(void);
|
||||||
|
WEAK_DEFAULT void isr_spi0_twi0(void);
|
||||||
|
WEAK_DEFAULT void isr_spi1_twi0(void);
|
||||||
|
WEAK_DEFAULT void isr_spi1_twi1(void);
|
||||||
|
WEAK_DEFAULT void isr_nfct(void);
|
||||||
|
WEAK_DEFAULT void isr_gpiote(void);
|
||||||
|
WEAK_DEFAULT void isr_saadc(void);
|
||||||
|
WEAK_DEFAULT void isr_timer0(void);
|
||||||
|
WEAK_DEFAULT void isr_timer1(void);
|
||||||
|
WEAK_DEFAULT void isr_timer2(void);
|
||||||
|
WEAK_DEFAULT void isr_rtc0(void);
|
||||||
|
WEAK_DEFAULT void isr_temp(void);
|
||||||
|
WEAK_DEFAULT void isr_twi0(void);
|
||||||
|
WEAK_DEFAULT void isr_rng(void);
|
||||||
|
WEAK_DEFAULT void isr_ecb(void);
|
||||||
|
WEAK_DEFAULT void isr_ccm_aar(void);
|
||||||
|
WEAK_DEFAULT void isr_wdt(void);
|
||||||
|
WEAK_DEFAULT void isr_rtc1(void);
|
||||||
|
WEAK_DEFAULT void isr_qdec(void);
|
||||||
|
WEAK_DEFAULT void isr_lpcomp(void);
|
||||||
|
|
||||||
|
#ifndef SOFTDEVICE_PRESENT
|
||||||
|
WEAK_DEFAULT void isr_swi0(void);
|
||||||
|
#else
|
||||||
|
/* For unknown reasons, setting PendSV pending within
|
||||||
|
* the softdevice ISRs leads to a crash. This workaround
|
||||||
|
* uses swi0 as trampoline.
|
||||||
|
*/
|
||||||
|
extern void thread_yield_higher(void);
|
||||||
|
void isr_swi0(void)
|
||||||
|
{
|
||||||
|
thread_yield_higher();
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
WEAK_DEFAULT void isr_swi1(void);
|
||||||
|
WEAK_DEFAULT void isr_swi2(void);
|
||||||
|
WEAK_DEFAULT void isr_swi3(void);
|
||||||
|
WEAK_DEFAULT void isr_swi4(void);
|
||||||
|
WEAK_DEFAULT void isr_swi5(void);
|
||||||
|
WEAK_DEFAULT void isr_timer3(void);
|
||||||
|
WEAK_DEFAULT void isr_timer4(void);
|
||||||
|
WEAK_DEFAULT void isr_pwm0(void);
|
||||||
|
WEAK_DEFAULT void isr_pdm(void);
|
||||||
|
WEAK_DEFAULT void isr_mwu(void);
|
||||||
|
WEAK_DEFAULT void isr_pwm1(void);
|
||||||
|
WEAK_DEFAULT void isr_pwm2(void);
|
||||||
|
WEAK_DEFAULT void isr_spi2(void);
|
||||||
|
WEAK_DEFAULT void isr_rtc2(void);
|
||||||
|
WEAK_DEFAULT void isr_i2s(void);
|
||||||
|
|
||||||
|
#ifdef SOFTDEVICE_PRESENT
|
||||||
|
extern void SWI2_EGU2_IRQHandler(void);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* CPU specific interrupt vector table */
|
||||||
|
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
|
||||||
|
isr_power_clock, /* power_clock */
|
||||||
|
isr_radio, /* radio */
|
||||||
|
isr_uart0, /* uart0 */
|
||||||
|
isr_spi1_twi0, /* spi1_twi0 */
|
||||||
|
isr_spi0, /* spi 0 */
|
||||||
|
(0UL), /* reserved */
|
||||||
|
isr_gpiote, /* gpiote */
|
||||||
|
isr_saadc, /* adc */
|
||||||
|
isr_timer0, /* timer0 */
|
||||||
|
isr_timer1, /* timer1 */
|
||||||
|
isr_timer2, /* timer2 */
|
||||||
|
isr_rtc0, /* rtc0 */
|
||||||
|
isr_temp, /* temp */
|
||||||
|
isr_rng, /* rng */
|
||||||
|
isr_ecb, /* ecb */
|
||||||
|
isr_ccm_aar, /* ccm_aar */
|
||||||
|
isr_wdt, /* wdt */
|
||||||
|
isr_rtc1, /* rtc1 */
|
||||||
|
isr_qdec, /* qdec */
|
||||||
|
isr_lpcomp, /* lpcomp */
|
||||||
|
isr_swi0, /* swi0 */
|
||||||
|
isr_swi1, /* swi1 */
|
||||||
|
isr_swi2, /* swi2 */
|
||||||
|
isr_swi3, /* swi3 */
|
||||||
|
isr_swi4, /* swi4 */
|
||||||
|
isr_swi5, /* swi5 */
|
||||||
|
(0UL), /* reserved */
|
||||||
|
(0UL), /* reserved */
|
||||||
|
isr_pwm0, /* pwm 0 */
|
||||||
|
isr_pdm, /* pdm */
|
||||||
|
};
|
||||||
146
cpu/nrf52/vectors/vectors_nrf52820xxaa.c
Normal file
146
cpu/nrf52/vectors/vectors_nrf52820xxaa.c
Normal file
@ -0,0 +1,146 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 2016 Freie Universität Berlin
|
||||||
|
*
|
||||||
|
* This file is subject to the terms and conditions of the GNU Lesser
|
||||||
|
* General Public License v2.1. See the file LICENSE in the top level
|
||||||
|
* directory for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @ingroup cpu_nrf52
|
||||||
|
* @{
|
||||||
|
*
|
||||||
|
* @file
|
||||||
|
* @brief nRF52820 interrupt vector definitions
|
||||||
|
*
|
||||||
|
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||||
|
* @author Benjamin Valentin <benpicco@googlemail.com>
|
||||||
|
*
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#include "cpu.h"
|
||||||
|
#include "vectors_cortexm.h"
|
||||||
|
|
||||||
|
/* define a local dummy handler as it needs to be in the same compilation unit
|
||||||
|
* as the alias definition */
|
||||||
|
void dummy_handler(void) {
|
||||||
|
dummy_handler_default();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* nRF52 specific interrupt vectors */
|
||||||
|
WEAK_DEFAULT void isr_power_clock(void);
|
||||||
|
WEAK_DEFAULT void isr_radio(void);
|
||||||
|
WEAK_DEFAULT void isr_uart0(void);
|
||||||
|
WEAK_DEFAULT void isr_spi0(void);
|
||||||
|
WEAK_DEFAULT void isr_spi0_twi0(void);
|
||||||
|
WEAK_DEFAULT void isr_spi1_twi0(void);
|
||||||
|
WEAK_DEFAULT void isr_spi1_twi1(void);
|
||||||
|
WEAK_DEFAULT void isr_nfct(void);
|
||||||
|
WEAK_DEFAULT void isr_gpiote(void);
|
||||||
|
WEAK_DEFAULT void isr_saadc(void);
|
||||||
|
WEAK_DEFAULT void isr_timer0(void);
|
||||||
|
WEAK_DEFAULT void isr_timer1(void);
|
||||||
|
WEAK_DEFAULT void isr_timer2(void);
|
||||||
|
WEAK_DEFAULT void isr_rtc0(void);
|
||||||
|
WEAK_DEFAULT void isr_temp(void);
|
||||||
|
WEAK_DEFAULT void isr_twi0(void);
|
||||||
|
WEAK_DEFAULT void isr_rng(void);
|
||||||
|
WEAK_DEFAULT void isr_ecb(void);
|
||||||
|
WEAK_DEFAULT void isr_ccm_aar(void);
|
||||||
|
WEAK_DEFAULT void isr_wdt(void);
|
||||||
|
WEAK_DEFAULT void isr_rtc1(void);
|
||||||
|
WEAK_DEFAULT void isr_qdec(void);
|
||||||
|
WEAK_DEFAULT void isr_lpcomp(void);
|
||||||
|
|
||||||
|
#ifndef SOFTDEVICE_PRESENT
|
||||||
|
WEAK_DEFAULT void isr_swi0(void);
|
||||||
|
#else
|
||||||
|
/* For unknown reasons, setting PendSV pending within
|
||||||
|
* the softdevice ISRs leads to a crash. This workaround
|
||||||
|
* uses swi0 as trampoline.
|
||||||
|
*/
|
||||||
|
extern void thread_yield_higher(void);
|
||||||
|
void isr_swi0(void)
|
||||||
|
{
|
||||||
|
thread_yield_higher();
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
WEAK_DEFAULT void isr_swi1(void);
|
||||||
|
WEAK_DEFAULT void isr_swi2(void);
|
||||||
|
WEAK_DEFAULT void isr_swi3(void);
|
||||||
|
WEAK_DEFAULT void isr_swi4(void);
|
||||||
|
WEAK_DEFAULT void isr_swi5(void);
|
||||||
|
WEAK_DEFAULT void isr_timer3(void);
|
||||||
|
WEAK_DEFAULT void isr_timer4(void);
|
||||||
|
WEAK_DEFAULT void isr_pwm0(void);
|
||||||
|
WEAK_DEFAULT void isr_pdm(void);
|
||||||
|
WEAK_DEFAULT void isr_mwu(void);
|
||||||
|
WEAK_DEFAULT void isr_pwm1(void);
|
||||||
|
WEAK_DEFAULT void isr_pwm2(void);
|
||||||
|
WEAK_DEFAULT void isr_spi2(void);
|
||||||
|
WEAK_DEFAULT void isr_rtc2(void);
|
||||||
|
WEAK_DEFAULT void isr_i2s(void);
|
||||||
|
WEAK_DEFAULT void isr_fpu(void);
|
||||||
|
WEAK_DEFAULT void isr_usbd(void);
|
||||||
|
WEAK_DEFAULT void isr_uarte1(void);
|
||||||
|
WEAK_DEFAULT void isr_qspi(void);
|
||||||
|
WEAK_DEFAULT void isr_cryptocell(void);
|
||||||
|
WEAK_DEFAULT void isr_spi3(void);
|
||||||
|
WEAK_DEFAULT void isr_pwm3(void);
|
||||||
|
|
||||||
|
#ifdef SOFTDEVICE_PRESENT
|
||||||
|
extern void SWI2_EGU2_IRQHandler(void);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* CPU specific interrupt vector table */
|
||||||
|
ISR_VECTOR(1)
|
||||||
|
const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
|
||||||
|
isr_power_clock, /* power_clock */
|
||||||
|
isr_radio, /* radio */
|
||||||
|
isr_uart0, /* uart0 */
|
||||||
|
isr_spi0_twi0, /* spi0_twi0 */
|
||||||
|
isr_spi1_twi1, /* spi1_twi1 */
|
||||||
|
(0UL), /* reserved */
|
||||||
|
isr_gpiote, /* gpiote */
|
||||||
|
(0UL), /* reserved */
|
||||||
|
isr_timer0, /* timer0 */
|
||||||
|
isr_timer1, /* timer1 */
|
||||||
|
isr_timer2, /* timer2 */
|
||||||
|
isr_rtc0, /* rtc0 */
|
||||||
|
isr_temp, /* temp */
|
||||||
|
isr_rng, /* rng */
|
||||||
|
isr_ecb, /* ecb */
|
||||||
|
isr_ccm_aar, /* ccm_aar */
|
||||||
|
isr_wdt, /* wdt */
|
||||||
|
isr_rtc1, /* rtc1 */
|
||||||
|
isr_qdec, /* qdec */
|
||||||
|
isr_lpcomp, /* lpcomp */
|
||||||
|
isr_swi0, /* swi0 */
|
||||||
|
isr_swi1, /* swi1 */
|
||||||
|
#ifdef SOFTDEVICE_PRESENT
|
||||||
|
SWI2_EGU2_IRQHandler, /* softdevice swi handler */
|
||||||
|
#else
|
||||||
|
isr_swi2, /* swi2 */
|
||||||
|
#endif
|
||||||
|
isr_swi3, /* swi3 */
|
||||||
|
isr_swi4, /* swi4 */
|
||||||
|
isr_swi5, /* swi5 */
|
||||||
|
isr_timer3, /* timer 3 */
|
||||||
|
(0UL), /* reserved */
|
||||||
|
(0UL), /* reserved */
|
||||||
|
(0UL), /* reserved */
|
||||||
|
(0UL), /* reserved */
|
||||||
|
(0UL), /* reserved */
|
||||||
|
(0UL), /* reserved */
|
||||||
|
(0UL), /* reserved */
|
||||||
|
(0UL), /* reserved */
|
||||||
|
(0UL), /* reserved */
|
||||||
|
(0UL), /* reserved */
|
||||||
|
(0UL), /* reserved */
|
||||||
|
(0UL), /* reserved */
|
||||||
|
isr_usbd, /* usbc */
|
||||||
|
};
|
||||||
138
cpu/nrf52/vectors/vectors_nrf52832xxaa.c
Normal file
138
cpu/nrf52/vectors/vectors_nrf52832xxaa.c
Normal file
@ -0,0 +1,138 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 2016 Freie Universität Berlin
|
||||||
|
*
|
||||||
|
* This file is subject to the terms and conditions of the GNU Lesser
|
||||||
|
* General Public License v2.1. See the file LICENSE in the top level
|
||||||
|
* directory for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @ingroup cpu_nrf52
|
||||||
|
* @{
|
||||||
|
*
|
||||||
|
* @file
|
||||||
|
* @brief nRF52832 interrupt vector definitions
|
||||||
|
*
|
||||||
|
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||||
|
*
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#include "cpu.h"
|
||||||
|
#include "vectors_cortexm.h"
|
||||||
|
|
||||||
|
/* define a local dummy handler as it needs to be in the same compilation unit
|
||||||
|
* as the alias definition */
|
||||||
|
void dummy_handler(void) {
|
||||||
|
dummy_handler_default();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* nRF52 specific interrupt vectors */
|
||||||
|
WEAK_DEFAULT void isr_power_clock(void);
|
||||||
|
WEAK_DEFAULT void isr_radio(void);
|
||||||
|
WEAK_DEFAULT void isr_uart0(void);
|
||||||
|
WEAK_DEFAULT void isr_spi0(void);
|
||||||
|
WEAK_DEFAULT void isr_spi0_twi0(void);
|
||||||
|
WEAK_DEFAULT void isr_spi1_twi0(void);
|
||||||
|
WEAK_DEFAULT void isr_spi1_twi1(void);
|
||||||
|
WEAK_DEFAULT void isr_nfct(void);
|
||||||
|
WEAK_DEFAULT void isr_gpiote(void);
|
||||||
|
WEAK_DEFAULT void isr_saadc(void);
|
||||||
|
WEAK_DEFAULT void isr_timer0(void);
|
||||||
|
WEAK_DEFAULT void isr_timer1(void);
|
||||||
|
WEAK_DEFAULT void isr_timer2(void);
|
||||||
|
WEAK_DEFAULT void isr_rtc0(void);
|
||||||
|
WEAK_DEFAULT void isr_temp(void);
|
||||||
|
WEAK_DEFAULT void isr_twi0(void);
|
||||||
|
WEAK_DEFAULT void isr_rng(void);
|
||||||
|
WEAK_DEFAULT void isr_ecb(void);
|
||||||
|
WEAK_DEFAULT void isr_ccm_aar(void);
|
||||||
|
WEAK_DEFAULT void isr_wdt(void);
|
||||||
|
WEAK_DEFAULT void isr_rtc1(void);
|
||||||
|
WEAK_DEFAULT void isr_qdec(void);
|
||||||
|
WEAK_DEFAULT void isr_lpcomp(void);
|
||||||
|
|
||||||
|
#ifndef SOFTDEVICE_PRESENT
|
||||||
|
WEAK_DEFAULT void isr_swi0(void);
|
||||||
|
#else
|
||||||
|
/* For unknown reasons, setting PendSV pending within
|
||||||
|
* the softdevice ISRs leads to a crash. This workaround
|
||||||
|
* uses swi0 as trampoline.
|
||||||
|
*/
|
||||||
|
extern void thread_yield_higher(void);
|
||||||
|
void isr_swi0(void)
|
||||||
|
{
|
||||||
|
thread_yield_higher();
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
WEAK_DEFAULT void isr_swi1(void);
|
||||||
|
WEAK_DEFAULT void isr_swi2(void);
|
||||||
|
WEAK_DEFAULT void isr_swi3(void);
|
||||||
|
WEAK_DEFAULT void isr_swi4(void);
|
||||||
|
WEAK_DEFAULT void isr_swi5(void);
|
||||||
|
WEAK_DEFAULT void isr_timer3(void);
|
||||||
|
WEAK_DEFAULT void isr_timer4(void);
|
||||||
|
WEAK_DEFAULT void isr_pwm0(void);
|
||||||
|
WEAK_DEFAULT void isr_pdm(void);
|
||||||
|
WEAK_DEFAULT void isr_mwu(void);
|
||||||
|
WEAK_DEFAULT void isr_pwm1(void);
|
||||||
|
WEAK_DEFAULT void isr_pwm2(void);
|
||||||
|
WEAK_DEFAULT void isr_spi2(void);
|
||||||
|
WEAK_DEFAULT void isr_rtc2(void);
|
||||||
|
WEAK_DEFAULT void isr_i2s(void);
|
||||||
|
WEAK_DEFAULT void isr_fpu(void);
|
||||||
|
|
||||||
|
#ifdef SOFTDEVICE_PRESENT
|
||||||
|
extern void SWI2_EGU2_IRQHandler(void);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* CPU specific interrupt vector table */
|
||||||
|
ISR_VECTOR(1)
|
||||||
|
const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
|
||||||
|
isr_power_clock, /* power_clock */
|
||||||
|
isr_radio, /* radio */
|
||||||
|
isr_uart0, /* uart0 */
|
||||||
|
isr_spi0_twi0, /* spi0_twi0 */
|
||||||
|
isr_spi1_twi1, /* spi1_twi1 */
|
||||||
|
isr_nfct, /* nfct */
|
||||||
|
isr_gpiote, /* gpiote */
|
||||||
|
isr_saadc, /* adc */
|
||||||
|
isr_timer0, /* timer0 */
|
||||||
|
isr_timer1, /* timer1 */
|
||||||
|
isr_timer2, /* timer2 */
|
||||||
|
isr_rtc0, /* rtc0 */
|
||||||
|
isr_temp, /* temp */
|
||||||
|
isr_rng, /* rng */
|
||||||
|
isr_ecb, /* ecb */
|
||||||
|
isr_ccm_aar, /* ccm_aar */
|
||||||
|
isr_wdt, /* wdt */
|
||||||
|
isr_rtc1, /* rtc1 */
|
||||||
|
isr_qdec, /* qdec */
|
||||||
|
isr_lpcomp, /* lpcomp */
|
||||||
|
isr_swi0, /* swi0 */
|
||||||
|
isr_swi1, /* swi1 */
|
||||||
|
#ifdef SOFTDEVICE_PRESENT
|
||||||
|
SWI2_EGU2_IRQHandler, /* softdevice swi handler */
|
||||||
|
#else
|
||||||
|
isr_swi2, /* swi2 */
|
||||||
|
#endif
|
||||||
|
isr_swi3, /* swi3 */
|
||||||
|
isr_swi4, /* swi4 */
|
||||||
|
isr_swi5, /* swi5 */
|
||||||
|
isr_timer3, /* timer 3 */
|
||||||
|
isr_timer4, /* timer 4 */
|
||||||
|
isr_pwm0, /* pwm 0 */
|
||||||
|
isr_pdm, /* pdm */
|
||||||
|
(0UL), /* reserved */
|
||||||
|
(0UL), /* reserved */
|
||||||
|
isr_mwu, /* mwu */
|
||||||
|
isr_pwm1, /* pwm 1 */
|
||||||
|
isr_pwm2, /* pwm 2 */
|
||||||
|
isr_spi2, /* spi 2 */
|
||||||
|
isr_rtc2, /* rtc 2 */
|
||||||
|
isr_i2s, /* i2s */
|
||||||
|
isr_fpu, /* fpu */
|
||||||
|
};
|
||||||
@ -1,6 +1,5 @@
|
|||||||
/*
|
/*
|
||||||
* Copyright (C) 2016 Freie Universität Berlin
|
* Copyright (C) 2016 Freie Universität Berlin
|
||||||
* 2020 Philipp-Alexander Blum <philipp-blum@jakiku.de>
|
|
||||||
*
|
*
|
||||||
* This file is subject to the terms and conditions of the GNU Lesser
|
* This file is subject to the terms and conditions of the GNU Lesser
|
||||||
* General Public License v2.1. See the file LICENSE in the top level
|
* General Public License v2.1. See the file LICENSE in the top level
|
||||||
@ -12,10 +11,9 @@
|
|||||||
* @{
|
* @{
|
||||||
*
|
*
|
||||||
* @file
|
* @file
|
||||||
* @brief nRF52 interrupt vector definitions
|
* @brief nRF52833 interrupt vector definitions
|
||||||
*
|
*
|
||||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||||
* @author Philipp-Alexander Blum <philipp-blum@jakiku.de>
|
|
||||||
*
|
*
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
@ -47,6 +45,7 @@ WEAK_DEFAULT void isr_timer1(void);
|
|||||||
WEAK_DEFAULT void isr_timer2(void);
|
WEAK_DEFAULT void isr_timer2(void);
|
||||||
WEAK_DEFAULT void isr_rtc0(void);
|
WEAK_DEFAULT void isr_rtc0(void);
|
||||||
WEAK_DEFAULT void isr_temp(void);
|
WEAK_DEFAULT void isr_temp(void);
|
||||||
|
WEAK_DEFAULT void isr_twi0(void);
|
||||||
WEAK_DEFAULT void isr_rng(void);
|
WEAK_DEFAULT void isr_rng(void);
|
||||||
WEAK_DEFAULT void isr_ecb(void);
|
WEAK_DEFAULT void isr_ecb(void);
|
||||||
WEAK_DEFAULT void isr_ccm_aar(void);
|
WEAK_DEFAULT void isr_ccm_aar(void);
|
||||||
@ -84,8 +83,6 @@ WEAK_DEFAULT void isr_pwm2(void);
|
|||||||
WEAK_DEFAULT void isr_spi2(void);
|
WEAK_DEFAULT void isr_spi2(void);
|
||||||
WEAK_DEFAULT void isr_rtc2(void);
|
WEAK_DEFAULT void isr_rtc2(void);
|
||||||
WEAK_DEFAULT void isr_i2s(void);
|
WEAK_DEFAULT void isr_i2s(void);
|
||||||
|
|
||||||
#ifdef CPU_MODEL_NRF52840XXAA
|
|
||||||
WEAK_DEFAULT void isr_fpu(void);
|
WEAK_DEFAULT void isr_fpu(void);
|
||||||
WEAK_DEFAULT void isr_usbd(void);
|
WEAK_DEFAULT void isr_usbd(void);
|
||||||
WEAK_DEFAULT void isr_uarte1(void);
|
WEAK_DEFAULT void isr_uarte1(void);
|
||||||
@ -93,46 +90,11 @@ WEAK_DEFAULT void isr_qspi(void);
|
|||||||
WEAK_DEFAULT void isr_cryptocell(void);
|
WEAK_DEFAULT void isr_cryptocell(void);
|
||||||
WEAK_DEFAULT void isr_spi3(void);
|
WEAK_DEFAULT void isr_spi3(void);
|
||||||
WEAK_DEFAULT void isr_pwm3(void);
|
WEAK_DEFAULT void isr_pwm3(void);
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef SOFTDEVICE_PRESENT
|
#ifdef SOFTDEVICE_PRESENT
|
||||||
extern void SWI2_EGU2_IRQHandler(void);
|
extern void SWI2_EGU2_IRQHandler(void);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(CPU_MODEL_NRF52811XXAA)
|
|
||||||
/* CPU specific interrupt vector table */
|
|
||||||
ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
|
|
||||||
isr_power_clock, /* power_clock */
|
|
||||||
isr_radio, /* radio */
|
|
||||||
isr_uart0, /* uart0 */
|
|
||||||
isr_spi1_twi0, /* spi1_twi0 */
|
|
||||||
isr_spi0, /* spi 0 */
|
|
||||||
(0UL), /* reserved */
|
|
||||||
isr_gpiote, /* gpiote */
|
|
||||||
isr_saadc, /* adc */
|
|
||||||
isr_timer0, /* timer0 */
|
|
||||||
isr_timer1, /* timer1 */
|
|
||||||
isr_timer2, /* timer2 */
|
|
||||||
isr_rtc0, /* rtc0 */
|
|
||||||
isr_temp, /* temp */
|
|
||||||
isr_rng, /* rng */
|
|
||||||
isr_ecb, /* ecb */
|
|
||||||
isr_ccm_aar, /* ccm_aar */
|
|
||||||
isr_wdt, /* wdt */
|
|
||||||
isr_rtc1, /* rtc1 */
|
|
||||||
isr_qdec, /* qdec */
|
|
||||||
isr_lpcomp, /* lpcomp */
|
|
||||||
isr_swi0, /* swi0 */
|
|
||||||
isr_swi1, /* swi1 */
|
|
||||||
isr_swi3, /* swi3 */
|
|
||||||
isr_swi4, /* swi4 */
|
|
||||||
isr_swi5, /* swi5 */
|
|
||||||
(0UL), /* reserved */
|
|
||||||
(0UL), /* reserved */
|
|
||||||
isr_pwm0, /* pwm 0 */
|
|
||||||
isr_pdm, /* pdm */
|
|
||||||
};
|
|
||||||
#else
|
|
||||||
/* CPU specific interrupt vector table */
|
/* CPU specific interrupt vector table */
|
||||||
ISR_VECTOR(1)
|
ISR_VECTOR(1)
|
||||||
const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
|
const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
|
||||||
@ -178,15 +140,14 @@ const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
|
|||||||
isr_spi2, /* spi 2 */
|
isr_spi2, /* spi 2 */
|
||||||
isr_rtc2, /* rtc 2 */
|
isr_rtc2, /* rtc 2 */
|
||||||
isr_i2s, /* i2s */
|
isr_i2s, /* i2s */
|
||||||
#ifdef CPU_MODEL_NRF52840XXAA
|
|
||||||
isr_fpu, /* fpu */
|
isr_fpu, /* fpu */
|
||||||
isr_usbd, /* usbc */
|
isr_usbd, /* usbc */
|
||||||
isr_uarte1, /* uarte1 */
|
isr_uarte1, /* uarte1 */
|
||||||
isr_qspi, /* qspi */
|
isr_qspi, /* qspi */
|
||||||
isr_cryptocell, /* cryptocell */
|
isr_cryptocell, /* cryptocell */
|
||||||
isr_spi3, /* spi3 */
|
(0UL), /* reserved */
|
||||||
(0UL), /* reserved */
|
(0UL), /* reserved */
|
||||||
isr_pwm3, /* pwm3 */
|
isr_pwm3, /* pwm3 */
|
||||||
#endif
|
(0UL), /* reserved */
|
||||||
|
isr_spi3, /* spi3 */
|
||||||
};
|
};
|
||||||
#endif
|
|
||||||
153
cpu/nrf52/vectors/vectors_nrf52840xxaa.c
Normal file
153
cpu/nrf52/vectors/vectors_nrf52840xxaa.c
Normal file
@ -0,0 +1,153 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 2016 Freie Universität Berlin
|
||||||
|
*
|
||||||
|
* This file is subject to the terms and conditions of the GNU Lesser
|
||||||
|
* General Public License v2.1. See the file LICENSE in the top level
|
||||||
|
* directory for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @ingroup cpu_nrf52
|
||||||
|
* @{
|
||||||
|
*
|
||||||
|
* @file
|
||||||
|
* @brief nRF52840 interrupt vector definitions
|
||||||
|
*
|
||||||
|
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||||
|
*
|
||||||
|
* @}
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#include "cpu.h"
|
||||||
|
#include "vectors_cortexm.h"
|
||||||
|
|
||||||
|
/* define a local dummy handler as it needs to be in the same compilation unit
|
||||||
|
* as the alias definition */
|
||||||
|
void dummy_handler(void) {
|
||||||
|
dummy_handler_default();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* nRF52 specific interrupt vectors */
|
||||||
|
WEAK_DEFAULT void isr_power_clock(void);
|
||||||
|
WEAK_DEFAULT void isr_radio(void);
|
||||||
|
WEAK_DEFAULT void isr_uart0(void);
|
||||||
|
WEAK_DEFAULT void isr_spi0(void);
|
||||||
|
WEAK_DEFAULT void isr_spi0_twi0(void);
|
||||||
|
WEAK_DEFAULT void isr_spi1_twi0(void);
|
||||||
|
WEAK_DEFAULT void isr_spi1_twi1(void);
|
||||||
|
WEAK_DEFAULT void isr_nfct(void);
|
||||||
|
WEAK_DEFAULT void isr_gpiote(void);
|
||||||
|
WEAK_DEFAULT void isr_saadc(void);
|
||||||
|
WEAK_DEFAULT void isr_timer0(void);
|
||||||
|
WEAK_DEFAULT void isr_timer1(void);
|
||||||
|
WEAK_DEFAULT void isr_timer2(void);
|
||||||
|
WEAK_DEFAULT void isr_rtc0(void);
|
||||||
|
WEAK_DEFAULT void isr_temp(void);
|
||||||
|
WEAK_DEFAULT void isr_twi0(void);
|
||||||
|
WEAK_DEFAULT void isr_rng(void);
|
||||||
|
WEAK_DEFAULT void isr_ecb(void);
|
||||||
|
WEAK_DEFAULT void isr_ccm_aar(void);
|
||||||
|
WEAK_DEFAULT void isr_wdt(void);
|
||||||
|
WEAK_DEFAULT void isr_rtc1(void);
|
||||||
|
WEAK_DEFAULT void isr_qdec(void);
|
||||||
|
WEAK_DEFAULT void isr_lpcomp(void);
|
||||||
|
|
||||||
|
#ifndef SOFTDEVICE_PRESENT
|
||||||
|
WEAK_DEFAULT void isr_swi0(void);
|
||||||
|
#else
|
||||||
|
/* For unknown reasons, setting PendSV pending within
|
||||||
|
* the softdevice ISRs leads to a crash. This workaround
|
||||||
|
* uses swi0 as trampoline.
|
||||||
|
*/
|
||||||
|
extern void thread_yield_higher(void);
|
||||||
|
void isr_swi0(void)
|
||||||
|
{
|
||||||
|
thread_yield_higher();
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
WEAK_DEFAULT void isr_swi1(void);
|
||||||
|
WEAK_DEFAULT void isr_swi2(void);
|
||||||
|
WEAK_DEFAULT void isr_swi3(void);
|
||||||
|
WEAK_DEFAULT void isr_swi4(void);
|
||||||
|
WEAK_DEFAULT void isr_swi5(void);
|
||||||
|
WEAK_DEFAULT void isr_timer3(void);
|
||||||
|
WEAK_DEFAULT void isr_timer4(void);
|
||||||
|
WEAK_DEFAULT void isr_pwm0(void);
|
||||||
|
WEAK_DEFAULT void isr_pdm(void);
|
||||||
|
WEAK_DEFAULT void isr_mwu(void);
|
||||||
|
WEAK_DEFAULT void isr_pwm1(void);
|
||||||
|
WEAK_DEFAULT void isr_pwm2(void);
|
||||||
|
WEAK_DEFAULT void isr_spi2(void);
|
||||||
|
WEAK_DEFAULT void isr_rtc2(void);
|
||||||
|
WEAK_DEFAULT void isr_i2s(void);
|
||||||
|
WEAK_DEFAULT void isr_fpu(void);
|
||||||
|
WEAK_DEFAULT void isr_usbd(void);
|
||||||
|
WEAK_DEFAULT void isr_uarte1(void);
|
||||||
|
WEAK_DEFAULT void isr_qspi(void);
|
||||||
|
WEAK_DEFAULT void isr_cryptocell(void);
|
||||||
|
WEAK_DEFAULT void isr_spi3(void);
|
||||||
|
WEAK_DEFAULT void isr_pwm3(void);
|
||||||
|
|
||||||
|
#ifdef SOFTDEVICE_PRESENT
|
||||||
|
extern void SWI2_EGU2_IRQHandler(void);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* CPU specific interrupt vector table */
|
||||||
|
ISR_VECTOR(1)
|
||||||
|
const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
|
||||||
|
isr_power_clock, /* power_clock */
|
||||||
|
isr_radio, /* radio */
|
||||||
|
isr_uart0, /* uart0 */
|
||||||
|
isr_spi0_twi0, /* spi0_twi0 */
|
||||||
|
isr_spi1_twi1, /* spi1_twi1 */
|
||||||
|
isr_nfct, /* nfct */
|
||||||
|
isr_gpiote, /* gpiote */
|
||||||
|
isr_saadc, /* adc */
|
||||||
|
isr_timer0, /* timer0 */
|
||||||
|
isr_timer1, /* timer1 */
|
||||||
|
isr_timer2, /* timer2 */
|
||||||
|
isr_rtc0, /* rtc0 */
|
||||||
|
isr_temp, /* temp */
|
||||||
|
isr_rng, /* rng */
|
||||||
|
isr_ecb, /* ecb */
|
||||||
|
isr_ccm_aar, /* ccm_aar */
|
||||||
|
isr_wdt, /* wdt */
|
||||||
|
isr_rtc1, /* rtc1 */
|
||||||
|
isr_qdec, /* qdec */
|
||||||
|
isr_lpcomp, /* lpcomp */
|
||||||
|
isr_swi0, /* swi0 */
|
||||||
|
isr_swi1, /* swi1 */
|
||||||
|
#ifdef SOFTDEVICE_PRESENT
|
||||||
|
SWI2_EGU2_IRQHandler, /* softdevice swi handler */
|
||||||
|
#else
|
||||||
|
isr_swi2, /* swi2 */
|
||||||
|
#endif
|
||||||
|
isr_swi3, /* swi3 */
|
||||||
|
isr_swi4, /* swi4 */
|
||||||
|
isr_swi5, /* swi5 */
|
||||||
|
isr_timer3, /* timer 3 */
|
||||||
|
isr_timer4, /* timer 4 */
|
||||||
|
isr_pwm0, /* pwm 0 */
|
||||||
|
isr_pdm, /* pdm */
|
||||||
|
(0UL), /* reserved */
|
||||||
|
(0UL), /* reserved */
|
||||||
|
isr_mwu, /* mwu */
|
||||||
|
isr_pwm1, /* pwm 1 */
|
||||||
|
isr_pwm2, /* pwm 2 */
|
||||||
|
isr_spi2, /* spi 2 */
|
||||||
|
isr_rtc2, /* rtc 2 */
|
||||||
|
isr_i2s, /* i2s */
|
||||||
|
isr_fpu, /* fpu */
|
||||||
|
isr_usbd, /* usbc */
|
||||||
|
isr_uarte1, /* uarte1 */
|
||||||
|
isr_qspi, /* qspi */
|
||||||
|
isr_cryptocell, /* cryptocell */
|
||||||
|
(0UL), /* reserved */
|
||||||
|
(0UL), /* reserved */
|
||||||
|
isr_pwm3, /* pwm3 */
|
||||||
|
(0UL), /* reserved */
|
||||||
|
isr_spi3, /* spi3 */
|
||||||
|
};
|
||||||
@ -71,11 +71,11 @@ static inline NRF_GPIO_Type *port(gpio_t pin)
|
|||||||
#if (CPU_FAM_NRF51)
|
#if (CPU_FAM_NRF51)
|
||||||
(void) pin;
|
(void) pin;
|
||||||
return NRF_GPIO;
|
return NRF_GPIO;
|
||||||
#elif defined(CPU_MODEL_NRF52832XXAA)
|
#elif defined(NRF_P1)
|
||||||
|
return (pin & PORT_BIT) ? NRF_P1 : NRF_P0;
|
||||||
|
#else
|
||||||
(void) pin;
|
(void) pin;
|
||||||
return NRF_P0;
|
return NRF_P0;
|
||||||
#else
|
|
||||||
return (pin & PORT_BIT) ? NRF_P1 : NRF_P0;
|
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
@ -35,7 +35,7 @@
|
|||||||
#include "periph/uart.h"
|
#include "periph/uart.h"
|
||||||
#include "periph/gpio.h"
|
#include "periph/gpio.h"
|
||||||
|
|
||||||
#if defined(CPU_MODEL_NRF52811XXAA) || defined(CPU_MODEL_NRF52840XXAA)
|
#if !defined(CPU_MODEL_NRF52832XXAA) && !defined(CPU_FAM_NRF51)
|
||||||
#define UART_INVALID (uart >= UART_NUMOF)
|
#define UART_INVALID (uart >= UART_NUMOF)
|
||||||
#define REG_BAUDRATE dev(uart)->BAUDRATE
|
#define REG_BAUDRATE dev(uart)->BAUDRATE
|
||||||
#define REG_CONFIG dev(uart)->CONFIG
|
#define REG_CONFIG dev(uart)->CONFIG
|
||||||
@ -114,7 +114,7 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
|
|||||||
gpio_init(UART_PIN_TX, GPIO_OUT);
|
gpio_init(UART_PIN_TX, GPIO_OUT);
|
||||||
PSEL_TXD = UART_PIN_TX;
|
PSEL_TXD = UART_PIN_TX;
|
||||||
|
|
||||||
#if defined(CPU_MODEL_NRF52811XXAA) || defined(CPU_MODEL_NRF52840XXAA)
|
#if !defined(CPU_MODEL_NRF52832XXAA) && !defined(CPU_FAM_NRF51)
|
||||||
/* enable HW-flow control if defined */
|
/* enable HW-flow control if defined */
|
||||||
#ifdef MODULE_PERIPH_UART_HW_FC
|
#ifdef MODULE_PERIPH_UART_HW_FC
|
||||||
/* set pin mode for RTS and CTS pins */
|
/* set pin mode for RTS and CTS pins */
|
||||||
@ -199,7 +199,7 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
|
|||||||
}
|
}
|
||||||
|
|
||||||
/* enable the UART device */
|
/* enable the UART device */
|
||||||
#if defined(CPU_MODEL_NRF52811XXAA) || defined(CPU_MODEL_NRF52840XXAA)
|
#if !defined(CPU_MODEL_NRF52832XXAA) && !defined(CPU_FAM_NRF51)
|
||||||
dev(uart)->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
|
dev(uart)->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
|
||||||
#else
|
#else
|
||||||
NRF_UART0->ENABLE = UART_ENABLE_ENABLE_Enabled;
|
NRF_UART0->ENABLE = UART_ENABLE_ENABLE_Enabled;
|
||||||
@ -207,7 +207,7 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
if (rx_cb) {
|
if (rx_cb) {
|
||||||
#if defined(CPU_MODEL_NRF52811XXAA) || defined(CPU_MODEL_NRF52840XXAA)
|
#if !defined(CPU_MODEL_NRF52832XXAA) && !defined(CPU_FAM_NRF51)
|
||||||
dev(uart)->RXD.MAXCNT = 1;
|
dev(uart)->RXD.MAXCNT = 1;
|
||||||
dev(uart)->RXD.PTR = (uint32_t)&rx_buf[uart];
|
dev(uart)->RXD.PTR = (uint32_t)&rx_buf[uart];
|
||||||
dev(uart)->INTENSET = UARTE_INTENSET_ENDRX_Msk;
|
dev(uart)->INTENSET = UARTE_INTENSET_ENDRX_Msk;
|
||||||
@ -226,7 +226,7 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
|
|||||||
}
|
}
|
||||||
|
|
||||||
/* nrf52840 || nrf52811 (using EasyDMA) */
|
/* nrf52840 || nrf52811 (using EasyDMA) */
|
||||||
#if defined(CPU_MODEL_NRF52811XXAA) || defined(CPU_MODEL_NRF52840XXAA)
|
#if !defined(CPU_MODEL_NRF52832XXAA) && !defined(CPU_FAM_NRF51)
|
||||||
static void _write_buf(uart_t uart, const uint8_t *data, size_t len)
|
static void _write_buf(uart_t uart, const uint8_t *data, size_t len)
|
||||||
{
|
{
|
||||||
/* reset endtx flag */
|
/* reset endtx flag */
|
||||||
|
|||||||
@ -8,6 +8,7 @@ BOARD_INSUFFICIENT_MEMORY := \
|
|||||||
calliope-mini \
|
calliope-mini \
|
||||||
cc2650-launchpad \
|
cc2650-launchpad \
|
||||||
cc2650stk \
|
cc2650stk \
|
||||||
|
e104-bt5010a-tb \
|
||||||
hifive1 \
|
hifive1 \
|
||||||
hifive1b \
|
hifive1b \
|
||||||
i-nucleo-lrwan1 \
|
i-nucleo-lrwan1 \
|
||||||
|
|||||||
@ -14,6 +14,7 @@ BOARD_INSUFFICIENT_MEMORY := \
|
|||||||
cc2538dk \
|
cc2538dk \
|
||||||
cc2650-launchpad \
|
cc2650-launchpad \
|
||||||
cc2650stk \
|
cc2650stk \
|
||||||
|
e104-bt5010a-tb \
|
||||||
ek-lm4f120xl \
|
ek-lm4f120xl \
|
||||||
esp8266-esp-12x \
|
esp8266-esp-12x \
|
||||||
esp8266-olimex-mod \
|
esp8266-olimex-mod \
|
||||||
|
|||||||
@ -5,6 +5,7 @@ BOARD_INSUFFICIENT_MEMORY := \
|
|||||||
arduino-uno \
|
arduino-uno \
|
||||||
atmega328p \
|
atmega328p \
|
||||||
b-l072z-lrwan1 \
|
b-l072z-lrwan1 \
|
||||||
|
e104-bt5010a-tb \
|
||||||
lsn50 \
|
lsn50 \
|
||||||
msb-430 \
|
msb-430 \
|
||||||
msb-430h \
|
msb-430h \
|
||||||
|
|||||||
@ -22,6 +22,7 @@ LOW_MEMORY_BOARDS += \
|
|||||||
cc1352-launchpad \
|
cc1352-launchpad \
|
||||||
cc2650-launchpad \
|
cc2650-launchpad \
|
||||||
cc2650stk \
|
cc2650stk \
|
||||||
|
e104-bt5010a-tb \
|
||||||
derfmega128 \
|
derfmega128 \
|
||||||
feather-m0 \
|
feather-m0 \
|
||||||
feather-m0-wifi \
|
feather-m0-wifi \
|
||||||
|
|||||||
3
tests/nimble_autoconn_ccnl/Makefile.ci
Normal file
3
tests/nimble_autoconn_ccnl/Makefile.ci
Normal file
@ -0,0 +1,3 @@
|
|||||||
|
BOARD_INSUFFICIENT_MEMORY := \
|
||||||
|
e104-bt5010a-tb \
|
||||||
|
#
|
||||||
3
tests/nimble_autoconn_gnrc/Makefile.ci
Normal file
3
tests/nimble_autoconn_gnrc/Makefile.ci
Normal file
@ -0,0 +1,3 @@
|
|||||||
|
BOARD_INSUFFICIENT_MEMORY := \
|
||||||
|
e104-bt5010a-tb \
|
||||||
|
#
|
||||||
3
tests/nimble_l2cap/Makefile.ci
Normal file
3
tests/nimble_l2cap/Makefile.ci
Normal file
@ -0,0 +1,3 @@
|
|||||||
|
BOARD_INSUFFICIENT_MEMORY := \
|
||||||
|
e104-bt5010a-tb \
|
||||||
|
#
|
||||||
3
tests/nimble_l2cap_server/Makefile.ci
Normal file
3
tests/nimble_l2cap_server/Makefile.ci
Normal file
@ -0,0 +1,3 @@
|
|||||||
|
BOARD_INSUFFICIENT_MEMORY := \
|
||||||
|
e104-bt5010a-tb \
|
||||||
|
#
|
||||||
3
tests/nimble_statconn_gnrc/Makefile.ci
Normal file
3
tests/nimble_statconn_gnrc/Makefile.ci
Normal file
@ -0,0 +1,3 @@
|
|||||||
|
BOARD_INSUFFICIENT_MEMORY := \
|
||||||
|
e104-bt5010a-tb \
|
||||||
|
#
|
||||||
@ -22,6 +22,7 @@ BOARD_INSUFFICIENT_MEMORY := \
|
|||||||
cc2650stk \
|
cc2650stk \
|
||||||
derfmega128 \
|
derfmega128 \
|
||||||
derfmega256 \
|
derfmega256 \
|
||||||
|
e104-bt5010a-tb \
|
||||||
ek-lm4f120xl \
|
ek-lm4f120xl \
|
||||||
esp8266-esp-12x \
|
esp8266-esp-12x \
|
||||||
esp8266-olimex-mod \
|
esp8266-olimex-mod \
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user