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cpu/lpc2387: use hwtimer_compat module
This commit is contained in:
Hauke Petersen
parent
9550ae87fb
commit
56ffc5672c
@ -2,4 +2,4 @@ INCLUDES += -I$(RIOTCPU)/lpc2387/include
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include $(RIOTCPU)/arm7_common/Makefile.include
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USEMODULE += arm7_common periph periph_common bitfield newlib
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USEMODULE += arm7_common periph periph_common bitfield newlib hwtimer_compat
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@ -1,206 +0,0 @@
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/*
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* Copyright (C) 2014 INRIA
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu
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* @file
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* @internal
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* @brief ARM kernel timer CPU dependent functions implementation
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*
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* @author Thomas Hillebrandt <hillebra@inf.fu-berlin.de>
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* @author Heiko Will <hwill@inf.fu-berlin.de>
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* @author Oliver Hahm <oliver.hahm@inria.fr>
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*
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*/
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#include "cpu.h"
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#include "bitarithm.h"
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#include "hwtimer_cpu.h"
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#include "arch/hwtimer_arch.h"
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#include "irq.h"
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#define VULP(x) ((volatile unsigned long*) (x))
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/* High level interrupt handler */
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static void (*int_handler)(int);
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/* Timer 0-3 interrupt handler */
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static void timer_irq(void) __attribute__((interrupt("IRQ")));
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inline static unsigned long get_base_address(short timer)
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{
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return (volatile unsigned long)(TMR0_BASE_ADDR + (timer / 8) * 0x6C000 + (timer / 4 - (timer / 8) * 2) * 0x4000);
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}
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static void timer_irq(void)
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{
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short timer = 0;
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if (T0IR) {
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timer = 0;
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}
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else if (T1IR) {
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timer = 4;
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}
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else if (T2IR) {
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timer = 8;
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}
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volatile unsigned long base = get_base_address(timer);
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if (*VULP(base + TXIR) & BIT0) {
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*VULP(base + TXMCR) &= ~BIT0;
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*VULP(base + TXIR) = BIT0;
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int_handler(timer);
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}
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if (*VULP(base + TXIR) & BIT1) {
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*VULP(base + TXMCR) &= ~BIT3;
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*VULP(base + TXIR) = BIT1;
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int_handler(timer + 1);
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}
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if (*VULP(base + TXIR) & BIT2) {
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*VULP(base + TXMCR) &= ~BIT6;
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*VULP(base + TXIR) = BIT2;
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int_handler(timer + 2);
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}
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if (*VULP(base + TXIR) & BIT3) {
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*VULP(base + TXMCR) &= ~BIT9;
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*VULP(base + TXIR) = BIT3;
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int_handler(timer + 3);
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}
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VICVectAddr = 0; /* acknowledge interrupt (if using VIC IRQ) */
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}
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static void timer0_init(uint32_t cpsr)
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{
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PCONP |= PCTIM0; /* power up timer */
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T0TCR = 2; /* disable and reset timer */
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T0MCR = 0; /* disable compare */
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T0CCR = 0; /* capture is disabled */
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T0EMR = 0; /* no external match output */
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T0PR = cpsr; /* set prescaler */
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install_irq(TIMER0_INT, &timer_irq, 1);
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T0TCR = 1; /* reset counter */
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}
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static void timer1_init(uint32_t cpsr)
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{
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PCONP |= PCTIM1; /* power up timer */
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T1TCR = 2; /* disable and reset timer */
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T1MCR = 0; /* disable compare */
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T1CCR = 0; /* capture is disabled */
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T1EMR = 0; /* no external match output */
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T1PR = cpsr; /* set prescaler */
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install_irq(TIMER1_INT, &timer_irq, 1);
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T1TCR = 1; /* reset counter */
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}
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static void timer2_init(uint32_t cpsr)
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{
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PCONP |= PCTIM2; /* power up timer */
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T2TCR = 2; /* disable and reset timer */
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T2MCR = 0; /* disable compare */
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T2CCR = 0; /* capture is disabled */
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T2EMR = 0; /* no external match output */
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T2PR = cpsr; /* set prescaler */
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install_irq(TIMER2_INT, &timer_irq, 1);
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T2TCR = 1; /* reset counter */
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}
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void hwtimer_arch_init(void (*handler)(int), uint32_t fcpu)
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{
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uint32_t cpsr;
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int_handler = handler;
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cpu_clock_scale(fcpu, HWTIMER_SPEED, &cpsr);
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timer0_init(cpsr);
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timer1_init(cpsr);
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timer2_init(cpsr);
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}
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/*---------------------------------------------------------------------------*/
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void hwtimer_arch_enable_interrupt(void)
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{
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VICIntEnable = 1 << TIMER0_INT; /* Enable Interrupt */
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VICIntEnable = 1 << TIMER1_INT; /* Enable Interrupt */
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VICIntEnable = 1 << TIMER2_INT; /* Enable Interrupt */
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}
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/*---------------------------------------------------------------------------*/
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void hwtimer_arch_disable_interrupt(void)
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{
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VICIntEnClr = 1 << TIMER0_INT; /* Disable Interrupt */
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VICIntEnClr = 1 << TIMER1_INT; /* Disable Interrupt */
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VICIntEnClr = 1 << TIMER2_INT; /* Disable Interrupt */
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}
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/*---------------------------------------------------------------------------*/
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void hwtimer_arch_set(unsigned long offset, short timer)
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{
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/* Calculate base address of timer register */
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/* Timer 0-3 are matched to TIMER0 */
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/* Timer 4-7 are matched to TIMER1 */
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/* Timer 8-11 are matched to TIMER2 */
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volatile unsigned long base = get_base_address(timer);
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/* Calculate match register address of corresponding timer */
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timer %= 4;
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unsigned long cpsr = disableIRQ();
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volatile unsigned long *addr = VULP(base + TXMR0 + 4 * timer);
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/* Calculate match register value */
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unsigned long value = *VULP(base + TXTC) + offset;
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*addr = value; /* set match register */
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*VULP(base + TXIR) = 0x01 << timer; /* reset interrupt register value for corresponding match register */
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*VULP(base + TXMCR) &= ~(7 << (3 * timer)); /* Clear all bits */
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*VULP(base + TXMCR) |= (MR0I << (3 * timer)); /* enable interrupt for match register */
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restoreIRQ(cpsr);
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}
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void hwtimer_arch_set_absolute(unsigned long value, short timer)
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{
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/* Calculate base address of timer register */
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/* Timer 0-3 are matched to TIMER0 */
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/* Timer 4-7 are matched to TIMER1 */
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/* Timer 8-11 are matched to TIMER2 */
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volatile unsigned long base = get_base_address(timer);
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/* Calculate match register address of corresponding timer */
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timer %= 4;
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volatile unsigned long *addr = VULP(base + TXMR0 + 4 * timer);
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/* Calculate match register value */
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*addr = value; /* set match register */
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*VULP(base + TXIR) = 0x01 << timer; /* reset interrupt register value for corresponding match register */
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*VULP(base + TXMCR) &= ~(7 << (3 * timer)); /* Clear all bits */
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*VULP(base + TXMCR) |= (MR0I << (3 * timer)); /* enable interrupt for match register */
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}
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/*---------------------------------------------------------------------------*/
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void hwtimer_arch_unset(short timer)
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{
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volatile unsigned long base = get_base_address(timer);
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timer %= 4;
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*VULP(base + TXMCR) &= ~(MR0I << (3 * timer)); /* disable interrupt for match register */
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*VULP(base + TXIR) = 0x01 << timer; /* reset interrupt register value for corresponding match register */
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}
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/*---------------------------------------------------------------------------*/
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unsigned long hwtimer_arch_now(void)
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{
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return T0TC;
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}
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void hwtimer_arch_setcounter(unsigned int val)
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{
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T0TC = val;
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}
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