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https://github.com/RIOT-OS/RIOT.git
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cpu/cortexm_common: Improve hardfault debug information
Print more relevant information and attempt to reconstruct the state for GDB before halting.
This commit is contained in:
Joakim Gebart
Joakim Nohlgård
parent
830bf36061
commit
56c6d629f7
@ -16,6 +16,7 @@
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Daniel Krebs <github@daniel-krebs.net>
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* @author Joakim Gebart <joakim.gebart@eistec.se>
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*
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* @}
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*/
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@ -23,6 +24,7 @@
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#include <stdint.h>
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#include <stdio.h>
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#include "cpu.h"
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#include "board.h"
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#include "panic.h"
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#include "kernel_internal.h"
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@ -45,7 +47,8 @@ extern uint32_t _sram;
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extern uint32_t _eram;
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/** @} */
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/** @brief Interrupt stack canary value
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/**
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* @brief Interrupt stack canary value
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*
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* @note 0xe7fe is the ARM Thumb machine code equivalent of asm("bl #-2\n") or
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* 'while (1);', i.e. an infinite loop.
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@ -113,90 +116,177 @@ void nmi_default(void)
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#ifdef DEVELHELP
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/* Trampoline function to save stackpointer before calling hardfault handler */
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/* The hard fault handler requires some stack space as a working area for local
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* variables and printf function calls etc. If the stack pointer is located
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* closer than HARDFAULT_HANDLER_REQUIRED_STACK_SPACE from the lowest address of
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* RAM we will reset the stack pointer to the top of available RAM. */
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#define HARDFAULT_HANDLER_REQUIRED_STACK_SPACE (THREAD_EXTRA_STACKSIZE_PRINTF)
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/* Trampoline function to save stack pointer before calling hard fault handler */
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void hard_fault_default(void)
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{
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/* Get stackpointer where exception stackframe lies */
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/* Get stack pointer where exception stack frame lies */
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__ASM volatile
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(
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/* Check that msp is valid first because we want to stack all the
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* r4-r11 registers so that we can use r0, r1, r2, r3 for other things. */
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"mov r0, sp \n" /* r0 = msp */
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"cmp r0, %[eram] \n" /* if(msp > &_eram) { */
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"bhi fix_msp \n" /* goto fix_msp } */
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"cmp r0, %[sram] \n" /* if(msp <= &_sram) { */
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"bls fix_msp \n" /* goto fix_msp } */
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"mov r1, #0 \n" /* else { corrupted = false */
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"b test_sp \n" /* goto test_sp } */
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" fix_msp: \n" /* */
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"mov r1, %[estack] \n" /* r1 = _estack */
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"mov sp, r1 \n" /* sp = r1 */
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"mov r1, #1 \n" /* corrupted = true */
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" test_sp: \n" /* */
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"movs r0, #4 \n" /* r0 = 0x4 */
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"mov r1, lr \n" /* r1 = lr */
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"tst r1, r0 \n" /* if(lr & 0x4) */
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"mov r2, lr \n" /* r2 = lr */
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"tst r2, r0 \n" /* if(lr & 0x4) */
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"bne use_psp \n" /* { */
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"mrs r0, msp \n" /* r0 = msp */
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"b out \n" /* } */
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" use_psp: \n" /* else { */
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"mrs r0, psp \n" /* r0 = psp */
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" out: \n" /* } */
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"mov r1, #0 \n" /* corrupted = false */
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"mov r2, sp \n" /* Cmp with SP is deprecated */
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"cmp r0, r2 \n" /* If msp is active stack- */
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"bne hardfault \n" /* pointer, check if valid so */
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"cmp r0, %[eram] \n" /* so calling c-func works . */
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"bge fix_msp \n" /* if(r0 == msp) { */
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"cmn r0, %[sram] \n" /* if( (r0 >= estack) || */
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"bl hardfault \n" /* (r0 < sstack) ) { */
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" fix_msp: \n" /* corrupted = true */
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"mov r0, %[estack] \n" /* r0 = _estack */
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"mov sp, r0 \n" /* sp = _estack */
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"mov r1, #1 \n" /* } */
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" hardfault: \n" /* } */
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#if (__CORTEX_M == 0)
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"push {r4-r7} \n" /* save r4..r7 to the stack */
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"mov r4, r8 \n" /* */
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"mov r5, r9 \n" /* */
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"mov r6, r10 \n" /* */
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"mov r7, r11 \n" /* */
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"push {r4-r7} \n" /* save r8..r11 to the stack */
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#else
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"push {r4-r11} \n" /* save r4..r11 to the stack */
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#endif
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"mov r3, sp \n" /* r4_to_r11_stack parameter */
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"b hard_fault_handler \n" /* hard_fault_handler(r0) */
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:
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: [sram] "r" (&_sram),
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: [sram] "r" (&_sram + HARDFAULT_HANDLER_REQUIRED_STACK_SPACE),
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[eram] "r" (&_eram),
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[estack] "r" (&_estack)
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: "r0","r1","r2"
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: "r4","r5","r6","r7","r8","r9","r10","r11","lr"
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);
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}
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void hard_fault_handler(uint32_t* sp, uint32_t corrupted)
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{
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/* Make them volatile so that they won't get optimized out */
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volatile unsigned int r0;
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volatile unsigned int r1;
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volatile unsigned int r2;
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volatile unsigned int r3;
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volatile unsigned int r12;
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volatile unsigned int lr; /* Link register. */
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volatile unsigned int pc; /* Program counter. */
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volatile unsigned int psr;/* Program status register. */
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#if (__CORTEX_M == 0)
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/* Cortex-M0 and Cortex-M0+ lack the extended fault status registers found in
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* Cortex-M3 and above. */
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#define CPU_HAS_EXTENDED_FAULT_REGISTERS 0
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#else
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#define CPU_HAS_EXTENDED_FAULT_REGISTERS 1
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#endif
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/* Sanity check stackpointer and give additional feedback about hardfault */
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void hard_fault_handler(uint32_t* sp, uint32_t corrupted, uint32_t exc_return, uint32_t* r4_to_r11_stack)
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{
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/* Sanity check stack pointer and give additional feedback about hard fault */
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if( corrupted ) {
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puts("Stackpointer corrupted, reset to top of stack");
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puts("Stack pointer corrupted, reset to top of stack");
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} else {
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r0 = sp[0];
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r1 = sp[1];
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r2 = sp[2];
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r3 = sp[3];
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r12 = sp[4];
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lr = sp[5];
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pc = sp[6];
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psr = sp[7];
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#if CPU_HAS_EXTENDED_FAULT_REGISTERS
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/* Copy status register contents to local stack storage, this must be
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* done before any calls to other functions to avoid corrupting the
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* register contents. */
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uint32_t bfar = SCB->BFAR;
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uint32_t mmfar = SCB->MMFAR;
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uint32_t cfsr = SCB->CFSR;
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uint32_t hfsr = SCB->HFSR;
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uint32_t dfsr = SCB->DFSR;
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uint32_t afsr = SCB->AFSR;
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#endif
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uint32_t r0 = sp[0];
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uint32_t r1 = sp[1];
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uint32_t r2 = sp[2];
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uint32_t r3 = sp[3];
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uint32_t r12 = sp[4];
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uint32_t lr = sp[5]; /* Link register. */
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uint32_t pc = sp[6]; /* Program counter. */
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uint32_t psr = sp[7]; /* Program status register. */
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/* Reconstruct original stack pointer before fault occurred */
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uint32_t* orig_sp = sp + 8;
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if (psr & SCB_CCR_STKALIGN_Msk) {
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/* Stack was not 8-byte aligned */
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orig_sp += 1;
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}
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puts("\nContext before hardfault:");
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/* TODO: printf in ISR context might be a bad idea */
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printf("r0: 0x%x\n"
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"r1: 0x%x\n"
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"r2: 0x%x\n"
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"r3: 0x%x\n",
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printf(" r0: 0x%08lx\n"
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" r1: 0x%08lx\n"
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" r2: 0x%08lx\n"
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" r3: 0x%08lx\n",
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r0, r1, r2, r3);
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printf("r12: 0x%x\n"
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"lr : 0x%x\n"
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"pc : 0x%x\n"
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"psr: 0x%x\n\n",
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printf(" r12: 0x%08lx\n"
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" lr: 0x%08lx\n"
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" pc: 0x%08lx\n"
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" psr: 0x%08lx\n\n",
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r12, lr, pc, psr);
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#if CPU_HAS_EXTENDED_FAULT_REGISTERS
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puts("FSR/FAR:");
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printf(" CFSR: 0x%08" PRIx32 "\n", cfsr);
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printf(" HFSR: 0x%08" PRIx32 "\n", hfsr);
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printf(" DFSR: 0x%08" PRIx32 "\n", dfsr);
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printf(" AFSR: 0x%08" PRIx32 "\n", afsr);
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if (((cfsr & SCB_CFSR_BUSFAULTSR_Msk) >> SCB_CFSR_BUSFAULTSR_Pos) & 0x80) {
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/* BFAR valid flag set */
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printf(" BFAR: 0x%08" PRIx32 "\n", bfar);
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}
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if (((cfsr & SCB_CFSR_MEMFAULTSR_Msk) >> SCB_CFSR_MEMFAULTSR_Pos) & 0x80) {
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/* MMFAR valid flag set */
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printf("MMFAR: 0x%08" PRIx32 "\n", mmfar);
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}
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#endif
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puts("Misc");
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printf("EXC_RET: 0x%08" PRIx32 "\n", exc_return);
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puts("Attempting to reconstruct state for debugging...");
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printf("In GDB:\n set $pc=0x%lx\n frame 0\n bt\n", pc);
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__ASM volatile (
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"mov r0, %[sp]\n"
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"ldr r2, [r0, #8]\n"
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"ldr r3, [r0, #12]\n"
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"ldr r1, [r0, #16]\n"
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"mov r12, r1\n"
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"ldr r1, [r0, #20]\n"
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"mov lr, r1\n"
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"mov sp, %[orig_sp]\n"
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"mov r1, %[extra_stack]\n"
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#if (__CORTEX_M == 0)
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"ldm r1!, {r4-r7}\n"
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"mov r8, r4\n"
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"mov r9, r5\n"
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"mov r10, r6\n"
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"mov r11, r7\n"
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"ldm r1!, {r4-r7}\n"
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#else
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"ldm r1, {r4-r11}\n"
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#endif
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"ldr r1, [r0, #4]\n"
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"ldr r0, [r0, #0]\n"
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:
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: [sp] "r" (sp),
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[orig_sp] "r" (orig_sp),
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[extra_stack] "r" (r4_to_r11_stack)
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: "r0","r1","r2","r3","r12"
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);
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__BKPT(1);
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}
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core_panic(PANIC_HARD_FAULT, "HARD FAULT HANDLER");
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}
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#else
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void hard_fault_default(void)
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{
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core_panic(PANIC_HARD_FAULT, "HARD FAULT HANDLER");
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}
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#endif /* DEVELHELP */
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#if defined(CPU_ARCH_CORTEX_M3) || defined(CPU_ARCH_CORTEX_M4) || \
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