From 54b889beb7bb707332e85047f5047a7e44574c79 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Fri, 8 Sep 2017 12:54:40 +0200 Subject: [PATCH] boards: add initial support for ST bl-475e-iot01a --- boards/b-l475e-iot01a/Makefile | 3 + boards/b-l475e-iot01a/Makefile.dep | 3 + boards/b-l475e-iot01a/Makefile.features | 11 + boards/b-l475e-iot01a/Makefile.include | 16 ++ boards/b-l475e-iot01a/board.c | 34 +++ boards/b-l475e-iot01a/dist/openocd.cfg | 3 + boards/b-l475e-iot01a/include/board.h | 66 ++++++ boards/b-l475e-iot01a/include/gpio_params.h | 61 ++++++ boards/b-l475e-iot01a/include/periph_conf.h | 216 ++++++++++++++++++++ 9 files changed, 413 insertions(+) create mode 100644 boards/b-l475e-iot01a/Makefile create mode 100644 boards/b-l475e-iot01a/Makefile.dep create mode 100644 boards/b-l475e-iot01a/Makefile.features create mode 100644 boards/b-l475e-iot01a/Makefile.include create mode 100644 boards/b-l475e-iot01a/board.c create mode 100644 boards/b-l475e-iot01a/dist/openocd.cfg create mode 100644 boards/b-l475e-iot01a/include/board.h create mode 100644 boards/b-l475e-iot01a/include/gpio_params.h create mode 100644 boards/b-l475e-iot01a/include/periph_conf.h diff --git a/boards/b-l475e-iot01a/Makefile b/boards/b-l475e-iot01a/Makefile new file mode 100644 index 0000000000..f8fcbb53a0 --- /dev/null +++ b/boards/b-l475e-iot01a/Makefile @@ -0,0 +1,3 @@ +MODULE = board + +include $(RIOTBASE)/Makefile.base diff --git a/boards/b-l475e-iot01a/Makefile.dep b/boards/b-l475e-iot01a/Makefile.dep new file mode 100644 index 0000000000..5472bf8b8d --- /dev/null +++ b/boards/b-l475e-iot01a/Makefile.dep @@ -0,0 +1,3 @@ +ifneq (,$(filter saul_default,$(USEMODULE))) + USEMODULE += saul_gpio +endif diff --git a/boards/b-l475e-iot01a/Makefile.features b/boards/b-l475e-iot01a/Makefile.features new file mode 100644 index 0000000000..7b056e0967 --- /dev/null +++ b/boards/b-l475e-iot01a/Makefile.features @@ -0,0 +1,11 @@ +# Put defined MCU peripherals here (in alphabetical order) +FEATURES_PROVIDED += periph_gpio +FEATURES_PROVIDED += periph_pwm +FEATURES_PROVIDED += periph_spi +FEATURES_PROVIDED += periph_timer +FEATURES_PROVIDED += periph_uart + +# The board MPU family (used for grouping by the CI system) +FEATURES_MCU_GROUP = cortex_m4_2 + +-include $(RIOTCPU)/stm32l4/Makefile.features diff --git a/boards/b-l475e-iot01a/Makefile.include b/boards/b-l475e-iot01a/Makefile.include new file mode 100644 index 0000000000..3f29deeff1 --- /dev/null +++ b/boards/b-l475e-iot01a/Makefile.include @@ -0,0 +1,16 @@ +# the cpu to build for +export CPU = stm32l4 +export CPU_MODEL = stm32l475vg + +# define the default port depending on the host OS +PORT_LINUX ?= /dev/ttyACM0 +PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*))) + +# setup serial terminal +include $(RIOTMAKE)/tools/serial.inc.mk + +export DEBUG_ADAPTER ?= stlink +export STLINK_VERSION ?= 2-1 + +# this board uses openocd +include $(RIOTMAKE)/tools/openocd.inc.mk diff --git a/boards/b-l475e-iot01a/board.c b/boards/b-l475e-iot01a/board.c new file mode 100644 index 0000000000..710d3d95f2 --- /dev/null +++ b/boards/b-l475e-iot01a/board.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2017 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_b-l475e-iot01a + * @{ + * + * @file + * @brief Board specific implementations for the b-l475e-iot01a board + * + * @author Alexandre Abadie + * + * @} + */ + +#include "board.h" +#include "periph/gpio.h" + +void board_init(void) +{ + /* initialize the CPU */ + cpu_init(); + +#ifdef AUTO_INIT_LED0 + /* The LED pin is also used for SPI, so we enable it + only if explicitly wanted by the user */ + gpio_init(LED0_PIN, GPIO_OUT); +#endif +} diff --git a/boards/b-l475e-iot01a/dist/openocd.cfg b/boards/b-l475e-iot01a/dist/openocd.cfg new file mode 100644 index 0000000000..52f860617d --- /dev/null +++ b/boards/b-l475e-iot01a/dist/openocd.cfg @@ -0,0 +1,3 @@ +source [find target/stm32l4x.cfg] + +reset_config srst_only diff --git a/boards/b-l475e-iot01a/include/board.h b/boards/b-l475e-iot01a/include/board.h new file mode 100644 index 0000000000..59cfbf0aeb --- /dev/null +++ b/boards/b-l475e-iot01a/include/board.h @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2017 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @defgroup boards_b-l475e-iot01a ST B-L475E-IOT01A + * @ingroup boards + * @brief Board specific files for the ST b-l475e-iot01a board + * @{ + * + * @file + * @brief Board specific definitions for the ST b-l475e-iot01a board + * + * @author Alexandre Abadie + */ + +#ifndef BOARD_H +#define BOARD_H + +#include + +#include "cpu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name LED pin definitions and handlers + * @{ + */ +#define LED0_PIN GPIO_PIN(PORT_A, 5) +#define LED0_MASK (1 << 5) + +#define LED0_ON (GPIOA->BSRR = LED0_MASK) +#define LED0_OFF (GPIOA->BSRR = (LED0_MASK << 16)) +#define LED0_TOGGLE (GPIOA->ODR ^= LED0_MASK) + +#define LED1_PIN GPIO_PIN(PORT_B, 14) +#define LED1_MASK (1 << 14) + +#define LED1_ON (GPIOB->BSRR = LED1_MASK) +#define LED1_OFF (GPIOB->BSRR = (LED1_MASK << 16)) +#define LED1_TOGGLE (GPIOB->ODR ^= LED1_MASK) +/** @} */ + +/** + * @brief User button + */ +#define BTN_B1_PIN GPIO_PIN(PORT_C, 13) + +/** + * @brief Initialize board specific hardware, including clock, LEDs and std-IO + */ +void board_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_H */ +/** @} */ diff --git a/boards/b-l475e-iot01a/include/gpio_params.h b/boards/b-l475e-iot01a/include/gpio_params.h new file mode 100644 index 0000000000..313ac9cf23 --- /dev/null +++ b/boards/b-l475e-iot01a/include/gpio_params.h @@ -0,0 +1,61 @@ +/* + * Copyright (C) Inria 2017 + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_b-l475e-iot01a-common + * @{ + * + * @file + * @brief Board specific configuration of direct mapped GPIOs + * + * @author Alexandre Abadie + */ + +#ifndef GPIO_PARAMS_H +#define GPIO_PARAMS_H + +#include "board.h" +#include "saul/periph.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief GPIO pin configuration + */ +static const saul_gpio_params_t saul_gpio_params[] = +{ +#ifdef AUTO_INIT_LED0 + /* The LED pin is also used for SPI, so we enable it + only if explicitly wanted by the user */ + { + .name = "LD1", + .pin = LED0_PIN, + .mode = GPIO_OUT + }, +#endif + { + .name = "LD2", + .pin = LED1_PIN, + .mode = GPIO_OUT + }, + { + .name = "Button(B1 User)", + .pin = BTN_B1_PIN, + .mode = GPIO_IN_PU, + .flags = SAUL_GPIO_INVERTED + } +}; + +#ifdef __cplusplus +} +#endif + +#endif /* GPIO_PARAMS_H */ +/** @} */ diff --git a/boards/b-l475e-iot01a/include/periph_conf.h b/boards/b-l475e-iot01a/include/periph_conf.h new file mode 100644 index 0000000000..2045267b41 --- /dev/null +++ b/boards/b-l475e-iot01a/include/periph_conf.h @@ -0,0 +1,216 @@ +/* + * Copyright (C) 2017 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_b-l475e-iot01a + * @{ + * + * @file + * @brief Peripheral MCU configuration for the b-l475e-iot01a board + * + * @author Alexandre Abadie + */ + +#ifndef PERIPH_CONF_H +#define PERIPH_CONF_H + +#include "periph_cpu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Clock system configuration + * @{ + */ +/* 0: no external high speed crystal available + * else: actual crystal frequency [in Hz] */ +#define CLOCK_HSE (0) +/* 0: no external low speed crystal available, + * 1: external crystal available (always 32.768kHz) */ +#define CLOCK_LSE (1) +/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */ +#define CLOCK_CORECLOCK (80000000U) +/* PLL configuration: make sure your values are legit! + * + * compute by: CORECLOCK = (((PLL_IN / M) * N) / R) + * with: + * PLL_IN: input clock, HSE or MSI @ 48MHz + * M: pre-divider, allowed range: [1:8] + * N: multiplier, allowed range: [8:86] + * R: post-divider, allowed range: [2,4,6,8] + * + * Also the following constraints need to be met: + * (PLL_IN / M) -> [4MHz:16MHz] + * (PLL_IN / M) * N -> [64MHz:344MHz] + * CORECLOCK -> 80MHz MAX! + */ +#define CLOCK_PLL_M (6) +#define CLOCK_PLL_N (20) +#define CLOCK_PLL_R (2) +/* peripheral clock setup */ +#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 +#define CLOCK_AHB (CLOCK_CORECLOCK / 1) +#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 +#define CLOCK_APB1 (CLOCK_CORECLOCK / 4) +#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 +#define CLOCK_APB2 (CLOCK_CORECLOCK / 2) +/** @} */ + +/** + * @name Timer configuration + * @{ + */ +static const timer_conf_t timer_config[] = { + { + .dev = TIM5, + .max = 0xffffffff, + .rcc_mask = RCC_APB1ENR1_TIM5EN, + .bus = APB1, + .irqn = TIM5_IRQn + } +}; + +#define TIMER_0_ISR isr_tim5 + +#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0])) +/** @} */ + +/** + * @name UART configuration + * @{ + */ +static const uart_conf_t uart_config[] = { + { + .dev = USART1, + .rcc_mask = RCC_APB2ENR_USART1EN, + .rx_pin = GPIO_PIN(PORT_B, 7), + .tx_pin = GPIO_PIN(PORT_B, 6), + .rx_af = GPIO_AF7, + .tx_af = GPIO_AF7, + .bus = APB2, + .irqn = USART1_IRQn, +#ifdef UART_USE_DMA + .dma_stream = 6, + .dma_chan = 4 +#endif + }, + { + .dev = UART4, + .rcc_mask = RCC_APB1ENR1_UART4EN, + .rx_pin = GPIO_PIN(PORT_A, 1), + .tx_pin = GPIO_PIN(PORT_A, 0), + .rx_af = GPIO_AF8, + .tx_af = GPIO_AF8, + .bus = APB1, + .irqn = UART4_IRQn, +#ifdef UART_USE_DMA + .dma_stream = 5, + .dma_chan = 4 +#endif + } +}; + +#define UART_0_ISR (isr_usart1) +#define UART_1_ISR (isr_uart4) + +#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0])) +/** @} */ + +/** + * @name PWM configuration + * @{ + */ +static const pwm_conf_t pwm_config[] = { + { + .dev = TIM2, + .rcc_mask = RCC_APB1ENR1_TIM2EN, + .chan = { { .pin = GPIO_PIN(PORT_A, 15), .cc_chan = 0}, /* D9 */ + { .pin = GPIO_UNDEF, .cc_chan = 0}, + { .pin = GPIO_UNDEF, .cc_chan = 0}, + { .pin = GPIO_UNDEF, .cc_chan = 0} }, + .af = GPIO_AF1, + .bus = APB1 + } +}; + +#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0])) +/** @} */ + +/** + * @name SPI configuration + * + * @note The spi_divtable is auto-generated from + * `cpu/stm32_common/dist/spi_divtable/spi_divtable.c` + * @{ + */ +static const uint8_t spi_divtable[2][5] = { + { /* for APB1 @ 20000000Hz */ + 7, /* -> 78125Hz */ + 5, /* -> 312500Hz */ + 3, /* -> 1250000Hz */ + 1, /* -> 5000000Hz */ + 0 /* -> 10000000Hz */ + }, + { /* for APB2 @ 40000000Hz */ + 7, /* -> 156250Hz */ + 6, /* -> 312500Hz */ + 4, /* -> 1250000Hz */ + 2, /* -> 5000000Hz */ + 1 /* -> 10000000Hz */ + } +}; + +static const spi_conf_t spi_config[] = { + { + .dev = SPI1, + .mosi_pin = GPIO_PIN(PORT_A, 7), + .miso_pin = GPIO_PIN(PORT_A, 6), + .sclk_pin = GPIO_PIN(PORT_A, 5), + .cs_pin = GPIO_UNDEF, + .af = GPIO_AF5, + .rccmask = RCC_APB2ENR_SPI1EN, + .apbbus = APB2 + } +}; + +#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0])) +/** @} */ + +/** + * @name ADC configuration + * @{ + */ +#define ADC_NUMOF (0) +/** @} */ + +/** + * @name RTT configuration + * + * On the STM32Lx platforms, we always utilize the LPTIM1. + * @{ + */ +#define RTT_NUMOF (1) +#define RTT_FREQUENCY (1024U) /* 32768 / 2^n */ +#define RTT_MAX_VALUE (0x0000ffff) /* 16-bit timer */ +/** @} */ + +/** + * @name RTC configuration + * @{ + */ +#define RTC_NUMOF (1) +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* PERIPH_CONF_H */ +/** @} */