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boards/nucleo-u575zi-q: Add support
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Ollrogge
parent
f048714418
commit
53d53d8cc8
@ -26,8 +26,8 @@
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#ifndef BOARD_H
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#define BOARD_H
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#include "board_nucleo.h"
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#include "arduino_pinmap.h"
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#include "board_nucleo.h"
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#ifdef __cplusplus
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extern "C" {
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@ -38,7 +38,7 @@ extern "C" {
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* @{
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*/
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#if defined(CPU_MODEL_STM32L496ZG) || defined(CPU_MODEL_STM32L4R5ZI) || \
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defined(CPU_MODEL_STM32L552ZE)
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defined(CPU_MODEL_STM32L552ZE) || defined(CPU_MODEL_STM32U575ZI)
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#define LED0_PIN_NUM 7
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#define LED0_PORT_NUM PORT_C
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#else
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@ -52,6 +52,9 @@ extern "C" {
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#if defined(CPU_MODEL_STM32L552ZE)
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#define LED2_PIN_NUM 9
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#define LED2_PORT_NUM PORT_A
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#elif defined(CPU_MODEL_STM32U575ZI)
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#define LED2_PIN_NUM 2
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#define LED2_PORT_NUM PORT_G
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#else
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#define LED2_PIN_NUM 14
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#define LED2_PORT_NUM PORT_B
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4
boards/nucleo-u575zi-q/Makefile
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4
boards/nucleo-u575zi-q/Makefile
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@ -0,0 +1,4 @@
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MODULE = board
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DIRS = $(RIOTBOARD)/common/nucleo
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include $(RIOTBASE)/Makefile.base
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1
boards/nucleo-u575zi-q/Makefile.dep
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1
boards/nucleo-u575zi-q/Makefile.dep
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@ -0,0 +1 @@
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include $(RIOTBOARD)/common/nucleo/Makefile.dep
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12
boards/nucleo-u575zi-q/Makefile.features
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12
boards/nucleo-u575zi-q/Makefile.features
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@ -0,0 +1,12 @@
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CPU = stm32
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CPU_MODEL = stm32u575zi
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_pwm
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart periph_lpuart
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FEATURES_PROVIDED += periph_usbdev
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# load the common Makefile.features for Nucleo boards
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include $(RIOTBOARD)/common/nucleo144/Makefile.features
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2
boards/nucleo-u575zi-q/Makefile.include
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2
boards/nucleo-u575zi-q/Makefile.include
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@ -0,0 +1,2 @@
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# load the common Makefile.include for Nucleo boards
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include $(RIOTBOARD)/common/nucleo144/Makefile.include
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63
boards/nucleo-u575zi-q/doc.txt
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63
boards/nucleo-u575zi-q/doc.txt
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@ -0,0 +1,63 @@
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/**
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@defgroup boards_nucleo-u575zi-q STM32 Nucleo-U575ZI-Q
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@ingroup boards_common_nucleo144
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@brief Support for the STM32 Nucleo-U575ZI-Q
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## Overview
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The Nucleo-L552ZE-Q is a board from ST's Nucleo family supporting the ARM Cortex-M33
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STM32U575ZIT6Q ultra-low-power microcontroller with TrustZone, 768KiB of RAM and 2MiB
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of Flash.
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## Hardware
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### MCU
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| MCU | STM32U575ZIT6Q |
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|:-------------|:-----------------------------|
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| Family | ARM Cortex-M33 |
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| Vendor | ST Microelectronics |
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| RAM | 786KiB |
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| Flash | 2MiB |
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| Frequency | up tp 160MHz |
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| FPU | yes |
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| TrustZone | yes |
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| Timers | 17 |
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| UARTs | 6 (3xUSART, 2xUART, 1xLPUART)|
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| I2cs | 4 |
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| SPIs | 3 |
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| CAN | 1 |
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| Datasheet | [Datasheet](https://www.st.com/resource/en/datasheet/stm32u575zi.pdf)|
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| Programming Manual | [Programming Manual](https://www.st.com/resource/en/programming_manual/pm0264-stm32-cortexm33-mcus-programming-manual-stmicroelectronics.pdf)|
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| Board Manual | [Board Manual](https://www.st.com/resource/en/user_manual/um2861-stm32u5-nucleo144-board-mb1549-stmicroelectronics.pdf)|
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## Flashing the device
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### Flashing the Board Using OpenOCD
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The ST Nucleo-L552ZE-Q board includes an on-board ST-LINK programmer and can be
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flashed using OpenOCD.
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Once OpenOCD is installed, you can flash the board simply by typing
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```
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make BOARD=nucleo-u575zi-q flash
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```
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and debug via GDB by simply typing
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```
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make BOARD=nucleo-u575zi-q debug
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```
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## Accessing RIOT shell
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Default RIOT shell access utilize VCP (Virtual COM Port) via USB interface,
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provided by integrated ST-LINK programmer. ST-LINK is connected to the
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microcontroller USART1.
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The default baud rate is 115 200.
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If a physical connection to USART1 is needed, connect UART interface to pins PA9 (USART1 TX) and PA10 (USART1 RX).
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*/
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183
boards/nucleo-u575zi-q/include/periph_conf.h
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183
boards/nucleo-u575zi-q/include/periph_conf.h
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@ -0,0 +1,183 @@
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/*
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* Copyright (C) 2024 TU Dresden
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_nucleo-u575zi-q
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the nucleo-u575zi-q board
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*
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* @author Nils Ollrogge <nils.ollrogge@mailbox.tu-dresden.de>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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/* Add specific clock configuration (HSE, LSE) for this board here */
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#ifndef CONFIG_BOARD_HAS_LSE
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#define CONFIG_BOARD_HAS_LSE 1
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#endif
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#include "cfg_timer_tim5.h"
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#include "cfg_usb_otg_fs_u5.h"
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#include "clk_conf.h"
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART1,
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.rcc_mask = RCC_APB2ENR_USART1EN,
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.rx_pin = GPIO_PIN(PORT_A, 10),
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.tx_pin = GPIO_PIN(PORT_A, 9),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB2,
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.irqn = USART1_IRQn,
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.type = STM32_USART,
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.clk_src = 0, /* Use APB clock */
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},
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{
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.dev = LPUART1,
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.rcc_mask = RCC_APB3ENR_LPUART1EN,
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.rx_pin = GPIO_PIN(PORT_G, 8),
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.tx_pin = GPIO_PIN(PORT_G, 7),
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.rx_af = GPIO_AF8,
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.tx_af = GPIO_AF8,
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.bus = APB3,
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.irqn = LPUART1_IRQn,
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.type = STM32_LPUART,
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.clk_src = 0, /* Use APB clock */
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},
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};
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#define UART_0_ISR (isr_usart1)
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#define UART_1_ISR (isr_lpuart1)
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#define UART_NUMOF ARRAY_SIZE(uart_config)
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/** @} */
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/**
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* @name SPI configuration
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* @{
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*/
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI1,
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.mosi_pin = GPIO_PIN(PORT_A, 7), /* Arduino D11 */
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.miso_pin = GPIO_PIN(PORT_A, 6), /* Arduino D12 */
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.sclk_pin = GPIO_PIN(PORT_A, 5), /* Arduino D13 */
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.cs_pin = GPIO_UNDEF,
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.mosi_af = GPIO_AF5,
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.miso_af = GPIO_AF5,
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.sclk_af = GPIO_AF5,
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.cs_af = GPIO_AF5,
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.rccmask = RCC_APB2ENR_SPI1EN,
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.apbbus = APB2,
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},
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};
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#define SPI_NUMOF ARRAY_SIZE(spi_config)
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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static const i2c_conf_t i2c_config[] = {
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{
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.dev = I2C1,
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.speed = I2C_SPEED_NORMAL,
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.scl_pin = GPIO_PIN(PORT_B, 8),
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.sda_pin = GPIO_PIN(PORT_B, 9),
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.scl_af = GPIO_AF4,
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.sda_af = GPIO_AF4,
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.bus = APB1,
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.rcc_mask = RCC_APB1ENR1_I2C1EN,
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.rcc_sw_mask = RCC_CCIPR1_I2C1SEL_1,
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.irqn = I2C1_ER_IRQn,
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},
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{
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.dev = I2C2,
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.speed = I2C_SPEED_NORMAL,
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.scl_pin = GPIO_PIN(PORT_F, 1),
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.sda_pin = GPIO_PIN(PORT_F, 0),
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.scl_af = GPIO_AF4,
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.sda_af = GPIO_AF4,
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.bus = APB1,
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.rcc_mask = RCC_APB1ENR1_I2C2EN,
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.rcc_sw_mask = RCC_CCIPR1_I2C2SEL_1,
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.irqn = I2C2_ER_IRQn,
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},
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};
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#define I2C_0_ISR isr_i2c1_er
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#define I2C_1_ISR isr_i2c2_er
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#define I2C_NUMOF ARRAY_SIZE(i2c_config)
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/** @} */
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/**
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* @name PWM configuration
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*
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* To find appriopate device and channel find in the MCU datasheet table
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* concerning "Alternate function AF0 to AF7" a text similar to TIM[X]_CH[Y],
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* where:
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* TIM[X] - is device,
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* [Y] - describes used channel (indexed from 0), for example TIM2_CH1 is
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* channel 0 in configuration structure (cc_chan - field),
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* Port column in the table describes connected port.
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*
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* For Nucleo-U575ZI-Q this information is in the datasheet, Table 27, page 127.
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*
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* @{
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*/
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static const pwm_conf_t pwm_config[] = {
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{ .dev = TIM2,
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.rcc_mask = RCC_APB1ENR1_TIM2EN,
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.chan = { { .pin = GPIO_PIN(PORT_A, 0) /* CN10 D32 */, .cc_chan = 0 },
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{ .pin = GPIO_PIN(PORT_A, 1) /* CN10 A8 */, .cc_chan = 1 },
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{ .pin = GPIO_PIN(PORT_A, 2) /* CN9 A1 */, .cc_chan = 2 },
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{ .pin = GPIO_PIN(PORT_A, 3) /* CN9 A0 */, .cc_chan = 3 } },
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.af = GPIO_AF1,
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.bus = APB1 },
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{ .dev = TIM3,
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.rcc_mask = RCC_APB1ENR1_TIM3EN,
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.chan = { { .pin = GPIO_PIN(PORT_B, 4) /* CN7 D25 */, .cc_chan = 0 },
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{ .pin = GPIO_PIN(PORT_B, 5) /* CN7 D22 */, .cc_chan = 1 },
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{ .pin = GPIO_PIN(PORT_B, 0) /* CN9 A3 */, .cc_chan = 2 },
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{ .pin = GPIO_PIN(PORT_B, 1) /* CN10 A6 */, .cc_chan = 3 } },
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.af = GPIO_AF2,
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.bus = APB1 },
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{ .dev = TIM4,
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.rcc_mask = RCC_APB1ENR1_TIM4EN,
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.chan = { { .pin = GPIO_PIN(PORT_D, 12) /* CN7 D19 */, .cc_chan = 0 },
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{ .pin = GPIO_PIN(PORT_B, 7) /* Blue LD2 */, .cc_chan = 1 },
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{ .pin = GPIO_PIN(PORT_D, 14) /* CN7 D10 */, .cc_chan = 2 },
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{ .pin = GPIO_PIN(PORT_D, 15) /* CN7 D9 */, .cc_chan = 3 } },
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.af = GPIO_AF2,
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.bus = APB1 },
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};
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#define PWM_NUMOF ARRAY_SIZE(pwm_config)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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@ -332,6 +332,10 @@ static inline void uart_init_usart(uart_t uart, uint32_t baudrate)
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#define RCC_CCIPR_LPUART1SEL_0 RCC_CCIPR1_LPUART1SEL_0
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#define RCC_CCIPR_LPUART1SEL_1 RCC_CCIPR1_LPUART1SEL_1
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#define CCIPR CCIPR1
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#elif CPU_FAM_STM32U5
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#define RCC_CCIPR_LPUART1SEL_0 RCC_CCIPR3_LPUART1SEL_0
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#define RCC_CCIPR_LPUART1SEL_1 RCC_CCIPR3_LPUART1SEL_1
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#define CCIPR CCIPR3
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#endif
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#ifdef MODULE_PERIPH_LPUART
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static inline void uart_init_lpuart(uart_t uart, uint32_t baudrate)
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