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boards/sodaq-*: use common code

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This commit is contained in:
Alexandre Abadie 2019-10-13 17:40:46 +02:00
parent f9631953cb
commit 536809cdca
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GPG Key ID: 1C919A403CAE1405
24 changed files with 47 additions and 779 deletions
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2
boards/sodaq-autonomo/Makefile
View File

@ -1,3 +1,5 @@
MODULE = board
DIRS += $(RIOTBOARD)/common/sodaq
include $(RIOTBASE)/Makefile.base

6
boards/sodaq-autonomo/Makefile.dep
View File

@ -1,3 +1,3 @@
ifneq (,$(filter saul_default,$(USEMODULE)))
USEMODULE += saul_gpio
endif
USEMODULE += boards_common_sodaq
include $(RIOTBOARD)/common/sodaq/Makefile.dep

13
boards/sodaq-autonomo/Makefile.features
View File

@ -1,16 +1,5 @@
CPU = samd21
CPU_MODEL = samd21j18a
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_adc
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_usbdev
# Various other features (if any)
FEATURES_PROVIDED += arduino
include $(RIOTBOARD)/common/sodaq/Makefile.features

15
boards/sodaq-autonomo/Makefile.include
View File

@ -1,14 +1 @@
PORT_LINUX ?= /dev/ttyACM0
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
# setup serial terminal
include $(RIOTMAKE)/tools/serial.inc.mk
# setup the flash tool used
# we use BOSSA to flash this board since there's an Arduino bootloader
# preflashed on it. ROM_OFFSET skips the space taken by such bootloader.
ROM_OFFSET ?= 0x2000
include $(RIOTMAKE)/tools/bossa.inc.mk
# setup the boards dependencies
include $(RIOTBOARD)/$(BOARD)/Makefile.dep
include $(RIOTBOARD)/common/sodaq/Makefile.include

32
boards/sodaq-autonomo/board.c
View File

@ -1,32 +0,0 @@
/*
* Copyright (C) 2016 Kees Bakker, SODAQ
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_sodaq-autonomo
* @{
*
* @file
* @brief Board specific implementations for the SODAQ Autonomo
* Pro board
*
* @author Kees Bakker <kees@sodaq.com>
*
* @}
*/
#include "board.h"
#include "periph/gpio.h"
void board_init(void)
{
/* initialize the on-board LED */
gpio_init(LED0_PIN, GPIO_OUT);
/* initialize the CPU */
cpu_init();
}

8
boards/sodaq-autonomo/include/board.h
View File

@ -20,8 +20,7 @@
#define BOARD_H
#include "cpu.h"
#include "periph_conf.h"
#include "periph_cpu.h"
#include "board_common.h"
#ifdef __cplusplus
extern "C" {
@ -49,11 +48,6 @@ extern "C" {
#define LED0_TOGGLE (LED_PORT.OUTTGL.reg = LED0_MASK)
/** @} */
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/
void board_init(void);
#ifdef __cplusplus
}
#endif

154
boards/sodaq-autonomo/include/periph_conf.h
View File

@ -23,102 +23,17 @@
#include "cpu.h"
#include "periph_cpu.h"
#include "cfg_clock_default.h"
#include "cfg_rtc_default.h"
#include "cfg_rtt_default.h"
#include "cfg_spi_default.h"
#include "cfg_timer_default.h"
#include "cfg_usbdev_default.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name External oscillator and clock configuration
*
* For selection of the used CORECLOCK, we have implemented two choices:
*
* - usage of the PLL fed by the internal 8MHz oscillator divided by 8
* - usage of the internal 8MHz oscillator directly, divided by N if needed
*
*
* The PLL option allows for the usage of a wider frequency range and a more
* stable clock with less jitter. This is why we use this option as default.
*
* The target frequency is computed from the PLL multiplier and the PLL divisor.
* Use the following formula to compute your values:
*
* CORECLOCK = ((PLL_MUL + 1) * 1MHz) / PLL_DIV
*
* NOTE: The PLL circuit does not run with less than 32MHz while the maximum PLL
* frequency is 96MHz. So PLL_MULL must be between 31 and 95!
*
*
* The internal Oscillator used directly can lead to a slightly better power
* efficiency to the cost of a less stable clock. Use this option when you know
* what you are doing! The actual core frequency is adjusted as follows:
*
* CORECLOCK = 8MHz / DIV
*
* NOTE: A core clock frequency below 1MHz is not recommended
*
* @{
*/
#define CLOCK_USE_PLL (1)
#if CLOCK_USE_PLL
/* edit these values to adjust the PLL output frequency */
#define CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */
#define CLOCK_PLL_DIV (1U) /* adjust to your needs */
/* generate the actual used core clock frequency */
#define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
#else
/* edit this value to your needs */
#define CLOCK_DIV (1U)
/* generate the actual core clock frequency */
#define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)
#endif
/** @} */
/**
* @name Timer peripheral configuration
* @{
*/
static const tc32_conf_t timer_config[] = {
{ /* Timer 0 - System Clock */
.dev = TC3,
.irq = TC3_IRQn,
.pm_mask = PM_APBCMASK_TC3,
.gclk_ctrl = GCLK_CLKCTRL_ID_TCC2_TC3,
#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
.gclk_src = GCLK_CLKCTRL_GEN(1),
.prescaler = TC_CTRLA_PRESCALER_DIV1,
#else
.gclk_src = GCLK_CLKCTRL_GEN(0),
.prescaler = TC_CTRLA_PRESCALER_DIV8,
#endif
.flags = TC_CTRLA_MODE_COUNT16,
},
{ /* Timer 1 */
.dev = TC4,
.irq = TC4_IRQn,
.pm_mask = PM_APBCMASK_TC4 | PM_APBCMASK_TC5,
.gclk_ctrl = GCLK_CLKCTRL_ID_TC4_TC5,
#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
.gclk_src = GCLK_CLKCTRL_GEN(1),
.prescaler = TC_CTRLA_PRESCALER_DIV1,
#else
.gclk_src = GCLK_CLKCTRL_GEN(0),
.prescaler = TC_CTRLA_PRESCALER_DIV8,
#endif
.flags = TC_CTRLA_MODE_COUNT32,
}
};
#define TIMER_0_MAX_VALUE 0xffff
/* interrupt function name mapping */
#define TIMER_0_ISR isr_tc3
#define TIMER_1_ISR isr_tc4
#define TIMER_NUMOF ARRAY_SIZE(timer_config)
/** @} */
/**
* @name UART configuration
* @{
@ -247,27 +162,6 @@ static const pwm_conf_t pwm_config[] = {
#define PWM_NUMOF (2U)
/** @} */
/**
* @name SPI configuration
* @{
*/
static const spi_conf_t spi_config[] = {
{
.dev = &SERCOM3->SPI,
.miso_pin = GPIO_PIN(PA, 22),
.mosi_pin = GPIO_PIN(PA, 20),
.clk_pin = GPIO_PIN(PA, 21),
.miso_mux = GPIO_MUX_C,
.mosi_mux = GPIO_MUX_D,
.clk_mux = GPIO_MUX_D,
.miso_pad = SPI_PAD_MISO_0,
.mosi_pad = SPI_PAD_MOSI_2_SCK_3,
},
};
#define SPI_NUMOF ARRAY_SIZE(spi_config)
/** @} */
/**
* @name I2C configuration
* @{
@ -286,42 +180,6 @@ static const i2c_conf_t i2c_config[] = {
#define I2C_NUMOF ARRAY_SIZE(i2c_config)
/** @} */
/**
* @name RTC configuration
* @{
*/
#define RTC_NUMOF (1U)
#define RTC_DEV RTC->MODE2
/** @} */
/**
* @name RTT configuration
* @{
*/
#define RTT_NUMOF (1U)
#define RTT_DEV RTC->MODE0
#define RTT_IRQ RTC_IRQn
#define RTT_IRQ_PRIO 10
#define RTT_ISR isr_rtc
#define RTT_MAX_VALUE (0xffffffff)
#define RTT_FREQUENCY (32768U) /* in Hz. For changes see `rtt.c` */
#define RTT_RUNSTDBY (1) /* Keep RTT running in sleep states */
/** @} */
/**
* @name USB peripheral configuration
* @{
*/
static const sam0_common_usb_config_t sam_usbdev_config[] = {
{
.dm = GPIO_PIN(PA, 24),
.dp = GPIO_PIN(PA, 25),
.d_mux = GPIO_MUX_G,
.device = &USB->DEVICE,
}
};
/** @} */
#ifdef __cplusplus
}
#endif

2
boards/sodaq-explorer/Makefile
View File

@ -1,3 +1,5 @@
MODULE = board
DIRS += $(RIOTBOARD)/common/sodaq
include $(RIOTBASE)/Makefile.base

6
boards/sodaq-explorer/Makefile.dep
View File

@ -1,3 +1,3 @@
ifneq (,$(filter saul_default,$(USEMODULE)))
USEMODULE += saul_gpio
endif
USEMODULE += boards_common_sodaq
include $(RIOTBOARD)/common/sodaq/Makefile.dep

14
boards/sodaq-explorer/Makefile.features
View File

@ -1,15 +1,3 @@
CPU = samd21
CPU_MODEL = samd21j18a
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_adc
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_usbdev
# Various other features (if any)
FEATURES_PROVIDED += arduino
include $(RIOTBOARD)/common/sodaq/Makefile.features

15
boards/sodaq-explorer/Makefile.include
View File

@ -1,14 +1 @@
PORT_LINUX ?= /dev/ttyACM0
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
# setup serial terminal
include $(RIOTMAKE)/tools/serial.inc.mk
# setup the flash tool used
# we use BOSSA to flash this board since there's an Arduino bootloader
# preflashed on it
export LINKER_SCRIPT ?= $(RIOTCPU)/sam0_common/ldscripts/$(CPU_MODEL)_arduino_bootloader.ld
include $(RIOTMAKE)/tools/bossa.inc.mk
# setup the boards dependencies
include $(RIOTBOARD)/$(BOARD)/Makefile.dep
include $(RIOTBOARD)/common/sodaq/Makefile.include

29
boards/sodaq-explorer/board.c
View File

@ -1,29 +0,0 @@
/*
* Copyright (C) 2017 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_sodaq-explorer
*
* @file
* @brief Board common implementations for the SODAQ ExpLoRer board
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
* @}
*/
#include "cpu.h"
#include "board.h"
#include "periph/gpio.h"
void board_init(void)
{
/* initialize the CPU */
cpu_init();
/* initialize the on-board LED */
gpio_init(LED0_PIN, GPIO_OUT);
}

7
boards/sodaq-explorer/include/board.h
View File

@ -20,7 +20,7 @@
#define BOARD_H
#include "cpu.h"
#include "periph_conf.h"
#include "board_common.h"
#ifdef __cplusplus
extern "C" {
@ -55,11 +55,6 @@ extern "C" {
#define RN2XX3_PARAM_PIN_RESET GPIO_PIN(PA, 7)
/** @} */
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/
void board_init(void);
#ifdef __cplusplus
}
#endif

155
boards/sodaq-explorer/include/periph_conf.h
View File

@ -20,102 +20,17 @@
#define PERIPH_CONF_H
#include "periph_cpu.h"
#include "cfg_clock_default.h"
#include "cfg_rtc_default.h"
#include "cfg_rtt_default.h"
#include "cfg_spi_default.h"
#include "cfg_timer_default.h"
#include "cfg_usbdev_default.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name External oscillator and clock configuration
*
* For selection of the used CORECLOCK, we have implemented two choices:
*
* - usage of the PLL fed by the internal 8MHz oscillator divided by 8
* - usage of the internal 8MHz oscillator directly, divided by N if needed
*
*
* The PLL option allows for the usage of a wider frequency range and a more
* stable clock with less jitter. This is why we use this option as default.
*
* The target frequency is computed from the PLL multiplier and the PLL divisor.
* Use the following formula to compute your values:
*
* CORECLOCK = ((PLL_MUL + 1) * 1MHz) / PLL_DIV
*
* NOTE: The PLL circuit does not run with less than 32MHz while the maximum PLL
* frequency is 96MHz. So PLL_MULL must be between 31 and 95!
*
*
* The internal Oscillator used directly can lead to a slightly better power
* efficiency to the cost of a less stable clock. Use this option when you know
* what you are doing! The actual core frequency is adjusted as follows:
*
* CORECLOCK = 8MHz / DIV
*
* NOTE: A core clock frequency below 1MHz is not recommended
*
* @{
*/
#define CLOCK_USE_PLL (1)
#if CLOCK_USE_PLL
/* edit these values to adjust the PLL output frequency */
#define CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */
#define CLOCK_PLL_DIV (1U) /* adjust to your needs */
/* generate the actual used core clock frequency */
#define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
#else
/* edit this value to your needs */
#define CLOCK_DIV (1U)
/* generate the actual core clock frequency */
#define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)
#endif
/** @} */
/**
* @name Timer peripheral configuration
* @{
*/
static const tc32_conf_t timer_config[] = {
{ /* Timer 0 - System Clock */
.dev = TC3,
.irq = TC3_IRQn,
.pm_mask = PM_APBCMASK_TC3,
.gclk_ctrl = GCLK_CLKCTRL_ID_TCC2_TC3,
#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
.gclk_src = GCLK_CLKCTRL_GEN(1),
.prescaler = TC_CTRLA_PRESCALER_DIV1,
#else
.gclk_src = GCLK_CLKCTRL_GEN(0),
.prescaler = TC_CTRLA_PRESCALER_DIV8,
#endif
.flags = TC_CTRLA_MODE_COUNT16,
},
{ /* Timer 1 */
.dev = TC4,
.irq = TC4_IRQn,
.pm_mask = PM_APBCMASK_TC4 | PM_APBCMASK_TC5,
.gclk_ctrl = GCLK_CLKCTRL_ID_TC4_TC5,
#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
.gclk_src = GCLK_CLKCTRL_GEN(1),
.prescaler = TC_CTRLA_PRESCALER_DIV1,
#else
.gclk_src = GCLK_CLKCTRL_GEN(0),
.prescaler = TC_CTRLA_PRESCALER_DIV8,
#endif
.flags = TC_CTRLA_MODE_COUNT32,
}
};
#define TIMER_0_MAX_VALUE 0xffff
/* interrupt function name mapping */
#define TIMER_0_ISR isr_tc3
#define TIMER_1_ISR isr_tc4
#define TIMER_NUMOF ARRAY_SIZE(timer_config)
/** @} */
/**
* @name UART configuration
* @{
@ -190,27 +105,6 @@ static const adc_conf_chan_t adc_channels[] = {
#define ADC_NUMOF ARRAY_SIZE(adc_channels)
/** @} */
/**
* @name SPI configuration
* @{
*/
static const spi_conf_t spi_config[] = {
{
.dev = &SERCOM3->SPI,
.miso_pin = GPIO_PIN(PA, 22),
.mosi_pin = GPIO_PIN(PA, 20),
.clk_pin = GPIO_PIN(PA, 21),
.miso_mux = GPIO_MUX_C,
.mosi_mux = GPIO_MUX_C,
.clk_mux = GPIO_MUX_C,
.miso_pad = SPI_PAD_MISO_0,
.mosi_pad = SPI_PAD_MOSI_2_SCK_3
}
};
#define SPI_NUMOF ARRAY_SIZE(spi_config)
/** @} */
/**
* @name I2C configuration
* @{
@ -236,43 +130,6 @@ static const i2c_conf_t i2c_config[] = {
}
};
#define I2C_NUMOF ARRAY_SIZE(i2c_config)
/** @} */
/**
* @name RTC configuration
* @{
*/
#define RTC_NUMOF (1U)
#define RTC_DEV RTC->MODE2
/** @} */
/**
* @name RTT configuration
* @{
*/
#define RTT_NUMOF (1U)
#define RTT_DEV RTC->MODE0
#define RTT_IRQ RTC_IRQn
#define RTT_IRQ_PRIO 10
#define RTT_ISR isr_rtc
#define RTT_MAX_VALUE (0xffffffff)
#define RTT_FREQUENCY (32768U) /* in Hz. For changes see `rtt.c` */
#define RTT_RUNSTDBY (1) /* Keep RTT running in sleep states */
/** @} */
/**
* @name USB peripheral configuration
* @{
*/
static const sam0_common_usb_config_t sam_usbdev_config[] = {
{
.dm = GPIO_PIN(PA, 24),
.dp = GPIO_PIN(PA, 25),
.d_mux = GPIO_MUX_G,
.device = &USB->DEVICE,
}
};
/** @} */
#ifdef __cplusplus

4
boards/sodaq-one/Makefile.dep
View File

@ -1,3 +1 @@
ifneq (,$(filter saul_default,$(USEMODULE)))
USEMODULE += saul_gpio
endif
include $(RIOTBOARD)/common/sodaq/Makefile.dep

14
boards/sodaq-one/Makefile.features
View File

@ -1,15 +1,3 @@
CPU = samd21
CPU_MODEL = samd21g18a
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_adc
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_usbdev
# Various other features (if any)
FEATURES_PROVIDED += arduino
include $(RIOTBOARD)/common/sodaq/Makefile.features

15
boards/sodaq-one/Makefile.include
View File

@ -1,14 +1 @@
PORT_LINUX ?= /dev/ttyACM0
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
# setup serial terminal
include $(RIOTMAKE)/tools/serial.inc.mk
# setup the flash tool used
# we use BOSSA to flash this board since there's an Arduino bootloader
# preflashed on it. ROM_OFFSET skips the space taken by such bootloader.
ROM_OFFSET ?= 0x2000
include $(RIOTMAKE)/tools/bossa.inc.mk
# setup the boards dependencies
include $(RIOTBOARD)/$(BOARD)/Makefile.dep
include $(RIOTBOARD)/common/sodaq/Makefile.include

7
boards/sodaq-one/include/board.h
View File

@ -20,7 +20,7 @@
#define BOARD_H
#include "cpu.h"
#include "periph_conf.h"
#include "board_common.h"
#ifdef __cplusplus
extern "C" {
@ -106,11 +106,6 @@ extern "C" {
#define LORA_RESET_TOGGLE (LORA_RESET_PORT.OUTTGL.reg = LORA_RESET_MASK)
/** @} */
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/
void board_init(void);
#ifdef __cplusplus
}
#endif

133
boards/sodaq-one/include/periph_conf.h
View File

@ -23,102 +23,16 @@
#include "cpu.h"
#include "periph_cpu.h"
#include "cfg_clock_default.h"
#include "cfg_rtc_default.h"
#include "cfg_rtt_default.h"
#include "cfg_timer_default.h"
#include "cfg_usbdev_default.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name External oscillator and clock configuration
*
* For selection of the used CORECLOCK, we have implemented two choices:
*
* - usage of the PLL fed by the internal 8MHz oscillator divided by 8
* - usage of the internal 8MHz oscillator directly, divided by N if needed
*
*
* The PLL option allows for the usage of a wider frequency range and a more
* stable clock with less jitter. This is why we use this option as default.
*
* The target frequency is computed from the PLL multiplier and the PLL divisor.
* Use the following formula to compute your values:
*
* CORECLOCK = ((PLL_MUL + 1) * 1MHz) / PLL_DIV
*
* NOTE: The PLL circuit does not run with less than 32MHz while the maximum PLL
* frequency is 96MHz. So PLL_MULL must be between 31 and 95!
*
*
* The internal Oscillator used directly can lead to a slightly better power
* efficiency to the cost of a less stable clock. Use this option when you know
* what you are doing! The actual core frequency is adjusted as follows:
*
* CORECLOCK = 8MHz / DIV
*
* NOTE: A core clock frequency below 1MHz is not recommended
*
* @{
*/
#define CLOCK_USE_PLL (1)
#if CLOCK_USE_PLL
/* edit these values to adjust the PLL output frequency */
#define CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */
#define CLOCK_PLL_DIV (1U) /* adjust to your needs */
/* generate the actual used core clock frequency */
#define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
#else
/* edit this value to your needs */
#define CLOCK_DIV (1U)
/* generate the actual core clock frequency */
#define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)
#endif
/** @} */
/**
* @name Timer peripheral configuration
* @{
*/
static const tc32_conf_t timer_config[] = {
{ /* Timer 0 - System Clock */
.dev = TC3,
.irq = TC3_IRQn,
.pm_mask = PM_APBCMASK_TC3,
.gclk_ctrl = GCLK_CLKCTRL_ID_TCC2_TC3,
#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
.gclk_src = GCLK_CLKCTRL_GEN(1),
.prescaler = TC_CTRLA_PRESCALER_DIV1,
#else
.gclk_src = GCLK_CLKCTRL_GEN(0),
.prescaler = TC_CTRLA_PRESCALER_DIV8,
#endif
.flags = TC_CTRLA_MODE_COUNT16,
},
{ /* Timer 1 */
.dev = TC4,
.irq = TC4_IRQn,
.pm_mask = PM_APBCMASK_TC4 | PM_APBCMASK_TC5,
.gclk_ctrl = GCLK_CLKCTRL_ID_TC4_TC5,
#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
.gclk_src = GCLK_CLKCTRL_GEN(1),
.prescaler = TC_CTRLA_PRESCALER_DIV1,
#else
.gclk_src = GCLK_CLKCTRL_GEN(0),
.prescaler = TC_CTRLA_PRESCALER_DIV8,
#endif
.flags = TC_CTRLA_MODE_COUNT32,
}
};
#define TIMER_0_MAX_VALUE 0xffff
/* interrupt function name mapping */
#define TIMER_0_ISR isr_tc3
#define TIMER_1_ISR isr_tc4
#define TIMER_NUMOF ARRAY_SIZE(timer_config)
/** @} */
/**
* @name UART configuration
* @{
@ -227,43 +141,6 @@ static const i2c_conf_t i2c_config[] = {
}
};
#define I2C_NUMOF ARRAY_SIZE(i2c_config)
/** @} */
/**
* @name RTC configuration
* @{
*/
#define RTC_NUMOF (1U)
#define RTC_DEV RTC->MODE2
/** @} */
/**
* @name RTT configuration
* @{
*/
#define RTT_NUMOF (1U)
#define RTT_DEV RTC->MODE0
#define RTT_IRQ RTC_IRQn
#define RTT_IRQ_PRIO 10
#define RTT_ISR isr_rtc
#define RTT_MAX_VALUE (0xffffffff)
#define RTT_FREQUENCY (32768U) /* in Hz. For changes see `rtt.c` */
#define RTT_RUNSTDBY (1) /* Keep RTT running in sleep states */
/** @} */
/**
* @name USB peripheral configuration
* @{
*/
static const sam0_common_usb_config_t sam_usbdev_config[] = {
{
.dm = GPIO_PIN(PA, 24),
.dp = GPIO_PIN(PA, 25),
.d_mux = GPIO_MUX_G,
.device = &USB->DEVICE,
}
};
/** @} */
#ifdef __cplusplus

4
boards/sodaq-sara-aff/Makefile.dep
View File

@ -1,3 +1 @@
ifneq (,$(filter saul_default,$(USEMODULE)))
USEMODULE += saul_gpio
endif
include $(RIOTBOARD)/common/sodaq/Makefile.dep

14
boards/sodaq-sara-aff/Makefile.features
View File

@ -1,15 +1,3 @@
CPU = samd21
CPU_MODEL = samd21j18a
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_adc
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_usbdev
# Various other features (if any)
FEATURES_PROVIDED += arduino
include $(RIOTBOARD)/common/sodaq/Makefile.features

15
boards/sodaq-sara-aff/Makefile.include
View File

@ -1,14 +1 @@
PORT_LINUX ?= /dev/ttyACM0
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
# setup serial terminal
include $(RIOTMAKE)/tools/serial.inc.mk
# setup the flash tool used
# we use BOSSA to flash this board since there's an Arduino bootloader
# preflashed on it. ROM_OFFSET skips the space taken by such bootloader.
ROM_OFFSET ?= 0x2000
include $(RIOTMAKE)/tools/bossa.inc.mk
# setup the boards dependencies
include $(RIOTBOARD)/$(BOARD)/Makefile.dep
include $(RIOTBOARD)/common/sodaq/Makefile.include

7
boards/sodaq-sara-aff/include/board.h
View File

@ -20,7 +20,7 @@
#define BOARD_H
#include "cpu.h"
#include "periph_conf.h"
#include "board_common.h"
#ifdef __cplusplus
extern "C" {
@ -155,11 +155,6 @@ extern "C" {
#define NB_IOT_TOGGLE_OFF (NB_IOT_TOGGLE_PORT.OUTCLR.reg = NB_IOT_TOGGLE_MASK)
/** @} */
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/
void board_init(void);
#ifdef __cplusplus
}
#endif

155
boards/sodaq-sara-aff/include/periph_conf.h
View File

@ -25,102 +25,17 @@
#include "cpu.h"
#include "periph_cpu.h"
#include "cfg_clock_default.h"
#include "cfg_rtc_default.h"
#include "cfg_rtt_default.h"
#include "cfg_spi_default.h"
#include "cfg_timer_default.h"
#include "cfg_usbdev_default.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name External oscillator and clock configuration
*
* For selection of the used CORECLOCK, we have implemented two choices:
*
* - usage of the PLL fed by the internal 8MHz oscillator divided by 8
* - usage of the internal 8MHz oscillator directly, divided by N if needed
*
*
* The PLL option allows for the usage of a wider frequency range and a more
* stable clock with less jitter. This is why we use this option as default.
*
* The target frequency is computed from the PLL multiplier and the PLL divisor.
* Use the following formula to compute your values:
*
* CORECLOCK = ((PLL_MUL + 1) * 1MHz) / PLL_DIV
*
* NOTE: The PLL circuit does not run with less than 32MHz while the maximum PLL
* frequency is 96MHz. So PLL_MULL must be between 31 and 95!
*
*
* The internal Oscillator used directly can lead to a slightly better power
* efficiency to the cost of a less stable clock. Use this option when you know
* what you are doing! The actual core frequency is adjusted as follows:
*
* CORECLOCK = 8MHz / DIV
*
* NOTE: A core clock frequency below 1MHz is not recommended
*
* @{
*/
#define CLOCK_USE_PLL (1)
#if CLOCK_USE_PLL
/* edit these values to adjust the PLL output frequency */
#define CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */
#define CLOCK_PLL_DIV (1U) /* adjust to your needs */
/* generate the actual used core clock frequency */
#define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
#else
/* edit this value to your needs */
#define CLOCK_DIV (1U)
/* generate the actual core clock frequency */
#define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)
#endif
/** @} */
/**
* @name Timer peripheral configuration
* @{
*/
static const tc32_conf_t timer_config[] = {
{ /* Timer 0 - System Clock */
.dev = TC3,
.irq = TC3_IRQn,
.pm_mask = PM_APBCMASK_TC3,
.gclk_ctrl = GCLK_CLKCTRL_ID_TCC2_TC3,
#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
.gclk_src = GCLK_CLKCTRL_GEN(1),
.prescaler = TC_CTRLA_PRESCALER_DIV1,
#else
.gclk_src = GCLK_CLKCTRL_GEN(0),
.prescaler = TC_CTRLA_PRESCALER_DIV8,
#endif
.flags = TC_CTRLA_MODE_COUNT16,
},
{ /* Timer 1 */
.dev = TC4,
.irq = TC4_IRQn,
.pm_mask = PM_APBCMASK_TC4 | PM_APBCMASK_TC5,
.gclk_ctrl = GCLK_CLKCTRL_ID_TC4_TC5,
#if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
.gclk_src = GCLK_CLKCTRL_GEN(1),
.prescaler = TC_CTRLA_PRESCALER_DIV1,
#else
.gclk_src = GCLK_CLKCTRL_GEN(0),
.prescaler = TC_CTRLA_PRESCALER_DIV8,
#endif
.flags = TC_CTRLA_MODE_COUNT32,
}
};
#define TIMER_0_MAX_VALUE 0xffff
/* interrupt function name mapping */
#define TIMER_0_ISR isr_tc3
#define TIMER_1_ISR isr_tc4
#define TIMER_NUMOF ARRAY_SIZE(timer_config)
/** @} */
/**
* @name UART configuration
* @{
@ -186,27 +101,6 @@ static const adc_conf_chan_t adc_channels[] = {
#define ADC_NUMOF ARRAY_SIZE(adc_channels)
/** @} */
/**
* @name SPI configuration
* @{
*/
static const spi_conf_t spi_config[] = {
{
.dev = &SERCOM3->SPI,
.miso_pin = GPIO_PIN(PA, 22),
.mosi_pin = GPIO_PIN(PA, 20),
.clk_pin = GPIO_PIN(PA, 21),
.miso_mux = GPIO_MUX_C,
.mosi_mux = GPIO_MUX_D,
.clk_mux = GPIO_MUX_D,
.miso_pad = SPI_PAD_MISO_0,
.mosi_pad = SPI_PAD_MOSI_2_SCK_3
}
};
#define SPI_NUMOF ARRAY_SIZE(spi_config)
/** @} */
/**
* @name I2C configuration
* @{
@ -223,43 +117,6 @@ static const i2c_conf_t i2c_config[] = {
}
};
#define I2C_NUMOF ARRAY_SIZE(i2c_config)
/** @} */
/**
* @name RTC configuration
* @{
*/
#define RTC_NUMOF (1U)
#define RTC_DEV RTC->MODE2
/** @} */
/**
* @name RTT configuration
* @{
*/
#define RTT_NUMOF (1U)
#define RTT_DEV RTC->MODE0
#define RTT_IRQ RTC_IRQn
#define RTT_IRQ_PRIO 10
#define RTT_ISR isr_rtc
#define RTT_MAX_VALUE (0xffffffff)
#define RTT_FREQUENCY (32768U) /* in Hz. For changes see `rtt.c` */
#define RTT_RUNSTDBY (1) /* Keep RTT running in sleep states */
/** @} */
/**
* @name USB peripheral configuration
* @{
*/
static const sam0_common_usb_config_t sam_usbdev_config[] = {
{
.dm = GPIO_PIN(PA, 24),
.dp = GPIO_PIN(PA, 25),
.d_mux = GPIO_MUX_G,
.device = &USB->DEVICE,
}
};
/** @} */
#ifdef __cplusplus