From fc7b4ed06b594559dc48e0844654b36a00e6eae9 Mon Sep 17 00:00:00 2001 From: Gunar Schorcht Date: Wed, 15 Mar 2023 18:37:25 +0100 Subject: [PATCH 01/10] cpu/stm32: use USB EP number when defined in CMSIS --- cpu/stm32/include/periph_cpu.h | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/cpu/stm32/include/periph_cpu.h b/cpu/stm32/include/periph_cpu.h index 2fa42b2c81..45b58bc590 100644 --- a/cpu/stm32/include/periph_cpu.h +++ b/cpu/stm32/include/periph_cpu.h @@ -131,20 +131,24 @@ typedef struct { * @brief Number of endpoints available with the OTG FS peripheral * including the control endpoint */ -#ifdef STM32_USB_OTG_CID_1x -#define STM32_USB_OTG_FS_NUM_EP (4) /**< OTG FS with 4 endpoints */ +#if defined(USB_OTG_FS_MAX_IN_ENDPOINTS) +#define STM32_USB_OTG_FS_NUM_EP (USB_OTG_FS_MAX_IN_ENDPOINTS) +#elif defined(STM32_USB_OTG_CID_1x) +#define STM32_USB_OTG_FS_NUM_EP (4) /**< OTG FS with 4 endpoints */ #elif defined(STM32_USB_OTG_CID_2x) -#define STM32_USB_OTG_FS_NUM_EP (6) /**< OTG FS with 6 endpoints */ +#define STM32_USB_OTG_FS_NUM_EP (6) /**< OTG FS with 6 endpoints */ #endif /** * @brief Number of endpoints available with the OTG HS peripheral * including the control endpoint */ -#ifdef STM32_USB_OTG_CID_1x -#define STM32_USB_OTG_HS_NUM_EP (6) /**< OTG HS with 6 endpoints */ +#if defined(USB_OTG_HS_MAX_IN_ENDPOINTS) +#define STM32_USB_OTG_HS_NUM_EP (USB_OTG_HS_MAX_IN_ENDPOINTS) +#elif defined(STM32_USB_OTG_CID_1x) +#define STM32_USB_OTG_HS_NUM_EP (6) /**< OTG HS with 6 endpoints */ #elif defined(STM32_USB_OTG_CID_2x) -#define STM32_USB_OTG_HS_NUM_EP (9) /**< OTG HS with 9 endpoints */ +#define STM32_USB_OTG_HS_NUM_EP (9) /**< OTG HS with 9 endpoints */ #endif /** From 9c306815c2330caa60e942ba12f04d19a15ce736 Mon Sep 17 00:00:00 2001 From: Gunar Schorcht Date: Thu, 16 Mar 2023 07:10:39 +0100 Subject: [PATCH 02/10] drivers/periph_common: add periph_usbdev_hs feature in Kconfig --- drivers/periph_common/Kconfig.usbdev | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/periph_common/Kconfig.usbdev b/drivers/periph_common/Kconfig.usbdev index a84dc44d30..32a364b558 100644 --- a/drivers/periph_common/Kconfig.usbdev +++ b/drivers/periph_common/Kconfig.usbdev @@ -22,6 +22,16 @@ config MODULE_PERIPH_INIT_USBDEV bool "Auto initialize USBDEV peripheral" default y if MODULE_PERIPH_INIT +config MODULE_PERIPH_USBDEV_HS + bool "Use USB HS peripheral" + depends on HAS_PERIPH_USBDEV_HS + default y if MODULE_PERIPH_INIT_USBDEV_HS_ULPI || MODULE_PERIPH_USBDEV_HS_UTMI + +config MODULE_PERIPH_INIT_USBDEV_HS + bool + depends on MODULE_PERIPH_USBDEV_HS + default y if MODULE_PERIPH_INIT + config MODULE_PERIPH_USBDEV_HS_ULPI bool "Use USB HS peripheral with ULPI HS PHY" depends on HAS_PERIPH_USBDEV_HS_ULPI From fd8182c09d89ebdccf4e57f64e8892868c257c77 Mon Sep 17 00:00:00 2001 From: Gunar Schorcht Date: Thu, 16 Mar 2023 07:17:34 +0100 Subject: [PATCH 03/10] boards/stm32f429i-disc1: add periph_usbdev_hs feature --- boards/stm32f429i-disc1/Kconfig | 3 +++ boards/stm32f429i-disc1/Makefile.dep | 4 ++++ boards/stm32f429i-disc1/Makefile.features | 1 + 3 files changed, 8 insertions(+) diff --git a/boards/stm32f429i-disc1/Kconfig b/boards/stm32f429i-disc1/Kconfig index ff05e0293c..33303137a9 100644 --- a/boards/stm32f429i-disc1/Kconfig +++ b/boards/stm32f429i-disc1/Kconfig @@ -20,6 +20,7 @@ config BOARD_STM32F429I_DISC1 select HAS_PERIPH_TIMER select HAS_PERIPH_UART select HAS_PERIPH_USBDEV + select HAS_PERIPH_USBDEV_HS # Put other features for this board (in alphabetical order) select HAS_RIOTBOOT @@ -38,4 +39,6 @@ config BOARD_STM32F429I_DISC1 select HAVE_I3G4250D select HAVE_L3GD20 + select MODULE_PERIPH_USBDEV_HS if MODULE_PERIPH_USBDEV + source "$(RIOTBOARD)/common/stm32/Kconfig" diff --git a/boards/stm32f429i-disc1/Makefile.dep b/boards/stm32f429i-disc1/Makefile.dep index 1b5ae322af..18b88c7611 100644 --- a/boards/stm32f429i-disc1/Makefile.dep +++ b/boards/stm32f429i-disc1/Makefile.dep @@ -1,3 +1,7 @@ +ifneq (,$(filter periph_usbdev,$(USEMODULE))) + USEMODULE += periph_usbdev_hs +endif + ifneq (,$(filter saul_default,$(USEMODULE))) USEMODULE += saul_gpio USEMODULE += l3gxxxx diff --git a/boards/stm32f429i-disc1/Makefile.features b/boards/stm32f429i-disc1/Makefile.features index 8ce979e427..3ddc733cbf 100644 --- a/boards/stm32f429i-disc1/Makefile.features +++ b/boards/stm32f429i-disc1/Makefile.features @@ -8,6 +8,7 @@ FEATURES_PROVIDED += periph_spi FEATURES_PROVIDED += periph_timer FEATURES_PROVIDED += periph_uart FEATURES_PROVIDED += periph_usbdev +FEATURES_PROVIDED += periph_usbdev_hs # Put other features for this board (in alphabetical order) FEATURES_PROVIDED += riotboot From c3fb8ae97ad6504510484d33017722a98f20720a Mon Sep 17 00:00:00 2001 From: Gunar Schorcht Date: Thu, 16 Mar 2023 07:21:17 +0100 Subject: [PATCH 04/10] cpu/stm32: use largest number of available EPs Use the largest instead of the smallest number of available EPs for this definition. This became necessary to be able to use all EPs of a USB OTG HS peripheral if enabled. --- cpu/stm32/include/periph_cpu.h | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/cpu/stm32/include/periph_cpu.h b/cpu/stm32/include/periph_cpu.h index 45b58bc590..c8b27306ff 100644 --- a/cpu/stm32/include/periph_cpu.h +++ b/cpu/stm32/include/periph_cpu.h @@ -154,14 +154,17 @@ typedef struct { /** * @brief Number of IN/OUT endpoints including EP0 as used by USBUS * - * @note Since only a single number of EPs can be defined for USBUS that is - * valid for all devices, the smallest number of EPs must be used for - * multiple USB devices. + * @note USBUS allows only one definition of the number of available EPs, which + * is then used for all devices. To be able to use all EPs for devices + * with more EPs, the largest possible number of available EPs for + * several USB devices is defined here. The driver has to ensure that the + * number of allocated EPs does not exceed the number of available EPs if + * a device has less EPs. */ -#if defined(STM32_USB_OTG_FS_NUM_EP) -#define USBDEV_NUM_ENDPOINTS STM32_USB_OTG_FS_NUM_EP -#elif defined(STM32_USB_OTG_HS_NUM_EP) +#if defined(MODULE_PERIPH_USBDEV_HS) && defined(STM32_USB_OTG_HS_NUM_EP) #define USBDEV_NUM_ENDPOINTS STM32_USB_OTG_HS_NUM_EP +#elif defined(STM32_USB_OTG_FS_NUM_EP) +#define USBDEV_NUM_ENDPOINTS STM32_USB_OTG_FS_NUM_EP #else #define USBDEV_NUM_ENDPOINTS 8 #endif From 735cb2474e11471ae9359956165ed78e969398ca Mon Sep 17 00:00:00 2001 From: Gunar Schorcht Date: Thu, 16 Mar 2023 07:25:02 +0100 Subject: [PATCH 05/10] tests/usbus_cdc_ecm: remove stm32f429i-disco from blacklist Since the stm32f429i-disco uses the USB OTG HS instead of USB OTG FS peripheral, the number of available EPs is sufficient for this application. With the change of defining the largest number of available EPs for USBUS instead of the smallest number, the board can use all EPs of the USB OTG HS peripheral. --- tests/usbus_cdc_ecm/Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/tests/usbus_cdc_ecm/Makefile b/tests/usbus_cdc_ecm/Makefile index b25c9e7699..fc1a96e1e4 100644 --- a/tests/usbus_cdc_ecm/Makefile +++ b/tests/usbus_cdc_ecm/Makefile @@ -12,7 +12,6 @@ USEMODULE += ps # Boards that don't have enough endpoints to use CDC ACM together with CDC ECM ifeq (,$(filter stdio_%,$(filter-out stdio_cdc_acm,$(USEMODULE)))) BOARD_BLACKLIST += \ - stm32f429i-disco \ stm32f4discovery \ weact-f401cc \ weact-f401ce \ From 97e1cdc15ea62127ee90440daa818a4db4a220d9 Mon Sep 17 00:00:00 2001 From: Gunar Schorcht Date: Thu, 16 Mar 2023 08:44:17 +0100 Subject: [PATCH 06/10] drivers/usbdev_synopsys_dwc2: fix DMA mode --- .../usbdev_synopsys_dwc2.c | 44 ++++++++++++++++--- 1 file changed, 37 insertions(+), 7 deletions(-) diff --git a/drivers/usbdev_synopsys_dwc2/usbdev_synopsys_dwc2.c b/drivers/usbdev_synopsys_dwc2/usbdev_synopsys_dwc2.c index 3977d5d5ac..94e088961e 100644 --- a/drivers/usbdev_synopsys_dwc2/usbdev_synopsys_dwc2.c +++ b/drivers/usbdev_synopsys_dwc2/usbdev_synopsys_dwc2.c @@ -130,6 +130,9 @@ typedef struct { usbdev_ep_t *in; /**< In endpoints */ dwc2_usb_otg_fshs_out_ep_t *out; /**< Out endpoints */ bool suspend; /**< Suspend status */ +#ifdef DWC2_USB_OTG_HS_ENABLED + uint8_t *ep0_out_buf; /**< Points to the buffer of EP0 OUT handler */ +#endif } dwc2_usb_otg_fshs_t; /* List of instantiated USB peripherals */ @@ -219,7 +222,7 @@ static bool _uses_dma(const dwc2_usb_otg_fshs_config_t *config) * request. In this case the enumeration of further interfaces, for example * CDC ECM is stopped. * - The Enumeration fails for CDC ECM interface which uses URB support. */ -#if 0 /* defined(DWC2_USB_OTG_HS_ENABLED) && STM32_USB_OTG_HS_USE_DMA */ +#ifdef DWC2_USB_OTG_HS_ENABLED return config->type == DWC2_USB_OTG_HS; #else (void)config; @@ -975,7 +978,7 @@ static void _usbdev_init(usbdev_t *dev) /* Unmask the transfer complete interrupts * Only needed when using DMA, otherwise the RX FIFO not empty * interrupt is used */ - _device_regs(conf)->DOEPMSK |= USB_OTG_DOEPMSK_XFRCM; + _device_regs(conf)->DOEPMSK |= USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_STUPM; _device_regs(conf)->DIEPMSK |= USB_OTG_DIEPMSK_XFRCM; } @@ -1165,6 +1168,22 @@ static void _usbdev_ep0_stall(usbdev_t *usbdev) /* Stall both directions, cleared automatically on SETUP received */ _in_regs(conf, 0)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; _out_regs(conf, 0)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; + +#ifdef DWC2_USB_OTG_HS_ENABLED + if (_uses_dma(conf) && st_usbdev->ep0_out_buf) { + /* The STALL condition is automatically cleared by the hardware as + * specified in the API documentation. However, in DMA mode the + * reception of the next SETUP must be prepared by setting the SETUP + * packet counter (STUPCNT) and enabling the OUT endpoint. Otherwise + * the USB OTG HS core will not generate an interrupt and the USB stack + * cannot respond correctly to the next SETUP received. In addition, + * the DMA address must be reset to the buffer address of the EP0 + * OUT handler. */ + _out_regs(conf, 0)->DOEPDMA = (uint32_t)(intptr_t)(st_usbdev->ep0_out_buf); + _out_regs(conf, 0)->DOEPTSIZ |= 1 << USB_OTG_DOEPTSIZ_STUPCNT_Pos; + _out_regs(conf, 0)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA; + } +#endif } static void _ep_set_stall(usbdev_ep_t *ep, bool enable) @@ -1306,6 +1325,13 @@ static int _usbdev_ep_xmit(usbdev_ep_t *ep, uint8_t *buf, size_t len) if (_uses_dma(conf)) { _out_regs(conf, ep->num)->DOEPDMA = (uint32_t)(intptr_t)buf; + /* store the buffer address of the EP0 OUT handler to use it in + * _usbdev_ep0_stall */ +#ifdef DWC2_USB_OTG_HS_ENABLED + if (ep->num == 0) { + usbdev->ep0_out_buf = buf; + } +#endif } else { container_of(ep, dwc2_usb_otg_fshs_out_ep_t, ep)->out_buf = buf; @@ -1354,11 +1380,6 @@ static void _read_packet(dwc2_usb_otg_fshs_out_ep_t *st_ep) * complete status */ if (pkt_status == DWC2_PKTSTS_DATA_UPDT || pkt_status == DWC2_PKTSTS_SETUP_UPDT) { -#if defined(MCU_EFM32) - /* TODO For some reason a short delay is required here on EFM32. It has - * to be investigated further. A delay of 1 msec is inserted for now. */ - ztimer_sleep(ZTIMER_MSEC, 1); -#endif _copy_rxfifo(usbdev, st_ep->out_buf, len); #if !defined(STM32_USB_OTG_CID_1x) /* CID 2x doesn't signal SETUP_COMP on non-zero length packets, signal @@ -1409,6 +1430,15 @@ static void _usbdev_ep_esr(usbdev_ep_t *ep) !_uses_dma(conf)) { _read_packet(container_of(ep, dwc2_usb_otg_fshs_out_ep_t, ep)); } +#ifdef DWC2_USB_OTG_HS_ENABLED + else if (_out_regs(conf, ep->num)->DOEPINT & USB_OTG_DOEPINT_STUP) { + _out_regs(conf, ep->num)->DOEPINT = USB_OTG_DOEPINT_STUP; + _out_regs(conf, ep->num)->DOEPINT = USB_OTG_DOEPINT_XFRC; + if (_uses_dma(conf)) { + usbdev->usbdev.epcb(ep, USBDEV_EVENT_TR_COMPLETE); + } + } +#endif /* Transfer complete seems only reliable when used with DMA */ else if (_out_regs(conf, ep->num)->DOEPINT & USB_OTG_DOEPINT_XFRC) { _out_regs(conf, ep->num)->DOEPINT = USB_OTG_DOEPINT_XFRC; From 1cd128b9db6fd302d2e87ad536ac1e6b61dfa539 Mon Sep 17 00:00:00 2001 From: Gunar Schorcht Date: Thu, 16 Mar 2023 07:32:33 +0100 Subject: [PATCH 07/10] cpu/stm32: reenable DMA for periph_usbdev --- cpu/stm32/include/usbdev_stm32.h | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/cpu/stm32/include/usbdev_stm32.h b/cpu/stm32/include/usbdev_stm32.h index 1d0c397f1a..e59aa99bc0 100644 --- a/cpu/stm32/include/usbdev_stm32.h +++ b/cpu/stm32/include/usbdev_stm32.h @@ -111,19 +111,6 @@ extern "C" { */ #define DWC2_USB_OTG_HS_TOTAL_FIFO_SIZE USB_OTG_HS_TOTAL_FIFO_SIZE -/** - * @brief Use the built-in DMA controller of the HS peripheral when possible - */ -#ifndef STM32_USB_OTG_HS_USE_DMA -#ifdef STM32_USB_OTG_CID_1x -/* FIXME: It should be possible to use DMA with the 1.x version of the * - * peripheral, but somehow it doesn't work. */ -#define STM32_USB_OTG_HS_USE_DMA (0) -#else -#define STM32_USB_OTG_HS_USE_DMA (1) -#endif -#endif - /* periph/usbdev.h is included after the definitions above by intention */ #include "periph/usbdev.h" From bf96c28889bd9d7eb9256a425d2a7dcacc1ece56 Mon Sep 17 00:00:00 2001 From: Marian Buschsieweke Date: Wed, 22 Mar 2023 15:08:57 +0100 Subject: [PATCH 08/10] cpu/rpx0xx: Update vendor header files Generated new vendor header files from upstream SVD files using: ./SVDConv "$PICO_SDK_DIR"/src/rp2040/hardware_regs/rp2040.svd \ --generate=header --fields=macro --fields=enum Note: The missing `--fields=struct` flag resulted in the header no longer containing bit-fields to represent different fields within registers. While this would generally ease writing code, the RP2040 has the unpleasant feature of corrupting the remaining bits of the register when a write access that is not word-sized occurs in the memory mapped I/O area. This could happen e.g. when a bit field is byte-sized and byte-aligned. --- boards/rpi-pico/include/board.h | 6 +- cpu/rpx0xx/clock.c | 62 +- cpu/rpx0xx/include/io_reg.h | 2 +- cpu/rpx0xx/include/periph_cpu.h | 6 +- cpu/rpx0xx/include/vendor/RP2040.h | 16466 ++++++--------------------- cpu/rpx0xx/periph/gpio.c | 34 +- cpu/rpx0xx/periph/timer.c | 15 +- cpu/rpx0xx/periph/uart.c | 54 +- cpu/rpx0xx/pll.c | 14 +- cpu/rpx0xx/rosc.c | 16 +- cpu/rpx0xx/xosc.c | 8 +- 11 files changed, 3460 insertions(+), 13223 deletions(-) diff --git a/boards/rpi-pico/include/board.h b/boards/rpi-pico/include/board.h index ecf74bbfdf..e3cc8a45ff 100644 --- a/boards/rpi-pico/include/board.h +++ b/boards/rpi-pico/include/board.h @@ -34,9 +34,9 @@ extern "C" { * @{ */ #define LED0_PIN GPIO_PIN(0, 25) -#define LED0_ON do {SIO->GPIO_OUT_SET.reg = 1UL << 25;} while (0) -#define LED0_OFF do {SIO->GPIO_OUT_CLR.reg = 1UL << 25;} while (0) -#define LED0_TOGGLE do {SIO->GPIO_OUT_XOR.reg = 1UL << 25;} while (0) +#define LED0_ON do {SIO->GPIO_OUT_SET = 1UL << 25;} while (0) +#define LED0_OFF do {SIO->GPIO_OUT_CLR = 1UL << 25;} while (0) +#define LED0_TOGGLE do {SIO->GPIO_OUT_XOR = 1UL << 25;} while (0) #define LED0_NAME "LED(Green)" /** @} */ diff --git a/cpu/rpx0xx/clock.c b/cpu/rpx0xx/clock.c index 3602493623..424632b263 100644 --- a/cpu/rpx0xx/clock.c +++ b/cpu/rpx0xx/clock.c @@ -29,25 +29,25 @@ static void _clk_sys_set_source(CLOCKS_CLK_SYS_CTRL_SRC_Enum source) { - io_reg_write_dont_corrupt(&CLOCKS->CLK_SYS_CTRL.reg, source << CLOCKS_CLK_SYS_CTRL_SRC_Pos, + io_reg_write_dont_corrupt(&CLOCKS->CLK_SYS_CTRL, source << CLOCKS_CLK_SYS_CTRL_SRC_Pos, CLOCKS_CLK_SYS_CTRL_SRC_Msk); } static void _clk_sys_set_aux_source(CLOCKS_CLK_SYS_CTRL_AUXSRC_Enum source) { - io_reg_write_dont_corrupt(&CLOCKS->CLK_SYS_CTRL.reg, source << CLOCKS_CLK_SYS_CTRL_AUXSRC_Pos, + io_reg_write_dont_corrupt(&CLOCKS->CLK_SYS_CTRL, source << CLOCKS_CLK_SYS_CTRL_AUXSRC_Pos, CLOCKS_CLK_SYS_CTRL_AUXSRC_Msk); } static void _clk_ref_set_source(CLOCKS_CLK_REF_CTRL_SRC_Enum source) { - io_reg_write_dont_corrupt(&CLOCKS->CLK_REF_CTRL.reg, source << CLOCKS_CLK_REF_CTRL_SRC_Pos, + io_reg_write_dont_corrupt(&CLOCKS->CLK_REF_CTRL, source << CLOCKS_CLK_REF_CTRL_SRC_Pos, CLOCKS_CLK_REF_CTRL_SRC_Msk); } static void _clk_ref_set_aux_source(CLOCKS_CLK_REF_CTRL_AUXSRC_Enum source) { - io_reg_write_dont_corrupt(&CLOCKS->CLK_REF_CTRL.reg, source << CLOCKS_CLK_REF_CTRL_AUXSRC_Pos, + io_reg_write_dont_corrupt(&CLOCKS->CLK_REF_CTRL, source << CLOCKS_CLK_REF_CTRL_AUXSRC_Pos, CLOCKS_CLK_REF_CTRL_AUXSRC_Msk); } @@ -66,7 +66,7 @@ void clock_sys_configure_source(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_SYS_CT /* switch the glitchless mux to clk_ref */ _clk_sys_set_source(source); /* apply divider */ - CLOCKS->CLK_SYS_DIV.reg = div; + CLOCKS->CLK_SYS_DIV = div; /* poll SELECTED until the switch is completed */ while (!(CLOCKS->CLK_SYS_SELECTED & (1U << source))) { } } @@ -83,7 +83,7 @@ void clock_sys_configure_aux_source(uint32_t f_in, uint32_t f_out, /* change the auxiliary mux */ _clk_sys_set_aux_source(aux); /* apply divider */ - CLOCKS->CLK_SYS_DIV.reg = div; + CLOCKS->CLK_SYS_DIV = div; /* switch the glitchless mux to clk_sys_aux */ _clk_sys_set_source(CLOCKS_CLK_SYS_CTRL_SRC_clksrc_clk_sys_aux); /* poll SELECTED until the switch is completed */ @@ -98,7 +98,7 @@ void clock_ref_configure_source(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_REF_CT /* switch the glitchless mux to clock source */ _clk_ref_set_source(source); /* apply divider */ - CLOCKS->CLK_REF_DIV.reg = div & CLOCKS_CLK_REF_DIV_INT_Msk; + CLOCKS->CLK_REF_DIV = div & CLOCKS_CLK_REF_DIV_INT_Msk; /* poll SELECTED until the switch is completed */ while (!(CLOCKS->CLK_REF_SELECTED & (1U << source))) { } } @@ -115,7 +115,7 @@ void clock_ref_configure_aux_source(uint32_t f_in, uint32_t f_out, /* change the auxiliary mux */ _clk_ref_set_aux_source(aux); /* apply divider */ - CLOCKS->CLK_REF_DIV.reg = div & CLOCKS_CLK_REF_DIV_INT_Msk; + CLOCKS->CLK_REF_DIV = div & CLOCKS_CLK_REF_DIV_INT_Msk; /* switch the glitchless mux to clk_ref_aux */ _clk_ref_set_source(CLOCKS_CLK_REF_CTRL_SRC_clksrc_clk_ref_aux); /* poll SELECTED until the switch is completed */ @@ -124,21 +124,21 @@ void clock_ref_configure_aux_source(uint32_t f_in, uint32_t f_out, void clock_periph_configure(CLOCKS_CLK_PERI_CTRL_AUXSRC_Enum aux) { - io_reg_atomic_clear(&CLOCKS->CLK_PERI_CTRL.reg, (1u << CLOCKS_CLK_PERI_CTRL_ENABLE_Pos)); - io_reg_write_dont_corrupt(&CLOCKS->CLK_PERI_CTRL.reg, aux << CLOCKS_CLK_PERI_CTRL_AUXSRC_Pos, + io_reg_atomic_clear(&CLOCKS->CLK_PERI_CTRL, (1u << CLOCKS_CLK_PERI_CTRL_ENABLE_Pos)); + io_reg_write_dont_corrupt(&CLOCKS->CLK_PERI_CTRL, aux << CLOCKS_CLK_PERI_CTRL_AUXSRC_Pos, CLOCKS_CLK_PERI_CTRL_AUXSRC_Msk); - io_reg_atomic_set(&CLOCKS->CLK_PERI_CTRL.reg, (1u << CLOCKS_CLK_PERI_CTRL_ENABLE_Pos)); + io_reg_atomic_set(&CLOCKS->CLK_PERI_CTRL, (1u << CLOCKS_CLK_PERI_CTRL_ENABLE_Pos)); } void clock_gpout0_configure(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_Enum aux) { assert(f_out <= f_in); uint32_t div = (((uint64_t)f_in) << CLOCKS_CLK_REF_DIV_INT_Pos) / f_out; - io_reg_atomic_clear(&CLOCKS->CLK_GPOUT0_CTRL.reg, 1U << CLOCKS_CLK_GPOUT0_CTRL_ENABLE_Pos); - _gpout_set_aux_source(&CLOCKS->CLK_GPOUT0_CTRL.reg, aux); - CLOCKS->CLK_GPOUT0_DIV.reg = div; - io_reg_atomic_set(&CLOCKS->CLK_GPOUT0_CTRL.reg, 1U << CLOCKS_CLK_GPOUT0_CTRL_ENABLE_Pos); - io_reg_atomic_set(&PADS_BANK0->GPIO21.reg, 1U << PADS_BANK0_GPIO21_IE_Pos); + io_reg_atomic_clear(&CLOCKS->CLK_GPOUT0_CTRL, 1U << CLOCKS_CLK_GPOUT0_CTRL_ENABLE_Pos); + _gpout_set_aux_source(&CLOCKS->CLK_GPOUT0_CTRL, aux); + CLOCKS->CLK_GPOUT0_DIV = div; + io_reg_atomic_set(&CLOCKS->CLK_GPOUT0_CTRL, 1U << CLOCKS_CLK_GPOUT0_CTRL_ENABLE_Pos); + io_reg_atomic_set(&PADS_BANK0->GPIO21, 1U << PADS_BANK0_GPIO21_IE_Pos); gpio_set_function_select(21, FUNCTION_SELECT_CLOCK); } @@ -146,11 +146,11 @@ void clock_gpout1_configure(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT1_CTR { assert(f_out <= f_in); uint32_t div = (((uint64_t)f_in) << CLOCKS_CLK_REF_DIV_INT_Pos) / f_out; - io_reg_atomic_clear(&CLOCKS->CLK_GPOUT1_CTRL.reg, 1U << CLOCKS_CLK_GPOUT1_CTRL_ENABLE_Pos); - _gpout_set_aux_source(&CLOCKS->CLK_GPOUT1_CTRL.reg, aux); - CLOCKS->CLK_GPOUT1_DIV.reg = div; - io_reg_atomic_set(&CLOCKS->CLK_GPOUT1_CTRL.reg, 1U << CLOCKS_CLK_GPOUT1_CTRL_ENABLE_Pos); - io_reg_atomic_set(&PADS_BANK0->GPIO23.reg, 1U << PADS_BANK0_GPIO23_IE_Pos); + io_reg_atomic_clear(&CLOCKS->CLK_GPOUT1_CTRL, 1U << CLOCKS_CLK_GPOUT1_CTRL_ENABLE_Pos); + _gpout_set_aux_source(&CLOCKS->CLK_GPOUT1_CTRL, aux); + CLOCKS->CLK_GPOUT1_DIV = div; + io_reg_atomic_set(&CLOCKS->CLK_GPOUT1_CTRL, 1U << CLOCKS_CLK_GPOUT1_CTRL_ENABLE_Pos); + io_reg_atomic_set(&PADS_BANK0->GPIO23, 1U << PADS_BANK0_GPIO23_IE_Pos); gpio_set_function_select(23, FUNCTION_SELECT_CLOCK); } @@ -158,11 +158,11 @@ void clock_gpout2_configure(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT2_CTR { assert(f_out <= f_in); uint32_t div = (((uint64_t)f_in) << CLOCKS_CLK_REF_DIV_INT_Pos) / f_out; - io_reg_atomic_clear(&CLOCKS->CLK_GPOUT2_CTRL.reg, 1U << CLOCKS_CLK_GPOUT2_CTRL_ENABLE_Pos); - _gpout_set_aux_source(&CLOCKS->CLK_GPOUT2_CTRL.reg, aux); - CLOCKS->CLK_GPOUT2_DIV.reg = div; - io_reg_atomic_set(&CLOCKS->CLK_GPOUT2_CTRL.reg, 1U << CLOCKS_CLK_GPOUT2_CTRL_ENABLE_Pos); - io_reg_atomic_set(&PADS_BANK0->GPIO24.reg, 1U << PADS_BANK0_GPIO24_IE_Pos); + io_reg_atomic_clear(&CLOCKS->CLK_GPOUT2_CTRL, 1U << CLOCKS_CLK_GPOUT2_CTRL_ENABLE_Pos); + _gpout_set_aux_source(&CLOCKS->CLK_GPOUT2_CTRL, aux); + CLOCKS->CLK_GPOUT2_DIV = div; + io_reg_atomic_set(&CLOCKS->CLK_GPOUT2_CTRL, 1U << CLOCKS_CLK_GPOUT2_CTRL_ENABLE_Pos); + io_reg_atomic_set(&PADS_BANK0->GPIO24, 1U << PADS_BANK0_GPIO24_IE_Pos); gpio_set_function_select(24, FUNCTION_SELECT_CLOCK); } @@ -170,10 +170,10 @@ void clock_gpout3_configure(uint32_t f_in, uint32_t f_out, CLOCKS_CLK_GPOUT3_CTR { assert(f_out <= f_in); uint32_t div = (((uint64_t)f_in) << CLOCKS_CLK_REF_DIV_INT_Pos) / f_out; - io_reg_atomic_clear(&CLOCKS->CLK_GPOUT3_CTRL.reg, 1U << CLOCKS_CLK_GPOUT3_CTRL_ENABLE_Pos); - _gpout_set_aux_source(&CLOCKS->CLK_GPOUT3_CTRL.reg, aux); - CLOCKS->CLK_GPOUT3_DIV.reg = div; - io_reg_atomic_set(&CLOCKS->CLK_GPOUT3_CTRL.reg, 1U << CLOCKS_CLK_GPOUT3_CTRL_ENABLE_Pos); - io_reg_atomic_set(&PADS_BANK0->GPIO25.reg, 1U << PADS_BANK0_GPIO25_IE_Pos); + io_reg_atomic_clear(&CLOCKS->CLK_GPOUT3_CTRL, 1U << CLOCKS_CLK_GPOUT3_CTRL_ENABLE_Pos); + _gpout_set_aux_source(&CLOCKS->CLK_GPOUT3_CTRL, aux); + CLOCKS->CLK_GPOUT3_DIV = div; + io_reg_atomic_set(&CLOCKS->CLK_GPOUT3_CTRL, 1U << CLOCKS_CLK_GPOUT3_CTRL_ENABLE_Pos); + io_reg_atomic_set(&PADS_BANK0->GPIO25, 1U << PADS_BANK0_GPIO25_IE_Pos); gpio_set_function_select(25, FUNCTION_SELECT_CLOCK); } diff --git a/cpu/rpx0xx/include/io_reg.h b/cpu/rpx0xx/include/io_reg.h index 70fa076631..ff0ee5a3af 100644 --- a/cpu/rpx0xx/include/io_reg.h +++ b/cpu/rpx0xx/include/io_reg.h @@ -121,7 +121,7 @@ static inline void io_reg_atomic_clear(volatile uint32_t *reg, uint32_t mask) * * Example use: * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.c} - * io_reg_write_dont_corrupt(&CLOCKS->CLK_SYS_CTRL.reg, source << CLOCKS_CLK_SYS_CTRL_SRC_Pos, + * io_reg_write_dont_corrupt(&CLOCKS->CLK_SYS_CTRL, source << CLOCKS_CLK_SYS_CTRL_SRC_Pos, * CLOCKS_CLK_SYS_CTRL_SRC_Msk); * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ diff --git a/cpu/rpx0xx/include/periph_cpu.h b/cpu/rpx0xx/include/periph_cpu.h index dc12c214bf..bd6d40ff18 100644 --- a/cpu/rpx0xx/include/periph_cpu.h +++ b/cpu/rpx0xx/include/periph_cpu.h @@ -487,7 +487,7 @@ static inline void gpio_reset_all_config(uint8_t pin) */ static inline void periph_reset(uint32_t components) { - io_reg_atomic_set(&RESETS->RESET.reg, components); + io_reg_atomic_set(&RESETS->RESET, components); } /** @@ -498,8 +498,8 @@ static inline void periph_reset(uint32_t components) */ static inline void periph_reset_done(uint32_t components) { - io_reg_atomic_clear(&RESETS->RESET.reg, components); - while ((~RESETS->RESET_DONE.reg) & components) { } + io_reg_atomic_clear(&RESETS->RESET, components); + while ((~RESETS->RESET_DONE) & components) { } } /** diff --git a/cpu/rpx0xx/include/vendor/RP2040.h b/cpu/rpx0xx/include/vendor/RP2040.h index 3b31151573..c97836dd4c 100644 --- a/cpu/rpx0xx/include/vendor/RP2040.h +++ b/cpu/rpx0xx/include/vendor/RP2040.h @@ -3,12 +3,12 @@ * * SPDX-License-Identifier: BSD-3-Clause * - * @file /home/fabian/rp2040//RP2040.h + * @file /home/maribu/Downloads/tmp/CMSIS/Utilities/Linux64//RP2040.h * @brief CMSIS HeaderFile * @version 0.1 - * @date 01. June 2021 - * @note Generated by SVDConv V3.3.35 on Tuesday, 01.06.2021 16:07:25 - * from File '/usr/lib/python3.9/site-packages/cmsis_svd/data/RaspberryPi/rp2040.svd', + * @date 22. March 2023 + * @note Generated by SVDConv V3.3.42 on Wednesday, 22.03.2023 20:19:18 + * from File '/home/maribu/Repos/software/pico-sdk/src/rp2040/hardware_regs/rp2040.svd', */ @@ -130,77 +130,9 @@ typedef enum { */ typedef struct { /*!< (@ 0x14000000) XIP_CTRL Structure */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Cache control */ - - struct { - __IOM uint32_t EN : 1; /*!< [0..0] When 1, enable the cache. When the cache is disabled, - all XIP accesses - will go straight to the flash, without querying the cache. - When enabled, - cacheable XIP accesses will query the cache, and the flash - will - not be accessed if the tag matches and the valid bit is - set. - - If the cache is enabled, cache-as-SRAM accesses have no - effect on the - cache data RAM, and will produce a bus error response. */ - __IOM uint32_t ERR_BADWRITE : 1; /*!< [1..1] When 1, writes to any alias other than 0x0 (caching, - allocating) - will produce a bus fault. When 0, these writes are silently - ignored. - In either case, writes to the 0x0 alias will deallocate - on tag match, - as usual. */ - uint32_t : 1; - __IOM uint32_t POWER_DOWN : 1; /*!< [3..3] When 1, the cache memories are powered down. They retain - state, - but can not be accessed. This reduces static power dissipation. - Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache - cannot - be enabled when powered down. - Cache-as-SRAM accesses will produce a bus error response - when - the cache is powered down. */ - uint32_t : 28; - } bit; - } CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Cache Flush control */ - - struct { - __IOM uint32_t FLUSH : 1; /*!< [0..0] Write 1 to flush the cache. This clears the tag memory, - but - the data memory retains its contents. (This means cache-as-SRAM - contents is not affected by flush or reset.) - Reading will hold the bus (stall the processor) until the - flush - completes. Alternatively STAT can be polled until completion. */ - uint32_t : 31; - } bit; - } FLUSH; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000008) Cache Status */ - - struct { - __IM uint32_t FLUSH_READY : 1; /*!< [0..0] Reads as 0 while a cache flush is in progress, and 1 - otherwise. - The cache is flushed whenever the XIP block is reset, and - also - when requested via the FLUSH register. */ - __IM uint32_t FIFO_EMPTY : 1; /*!< [1..1] When 1, indicates the XIP streaming FIFO is completely - empty. */ - __IM uint32_t FIFO_FULL : 1; /*!< [2..2] When 1, indicates the XIP streaming FIFO is completely - full. - The streaming FIFO is 2 entries deep, so the full and empty - flag allow its level to be ascertained. */ - uint32_t : 29; - } bit; - } STAT; + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Cache control */ + __IOM uint32_t FLUSH; /*!< (@ 0x00000004) Cache Flush control */ + __IOM uint32_t STAT; /*!< (@ 0x00000008) Cache Status */ __IOM uint32_t CTR_HIT; /*!< (@ 0x0000000C) Cache Hit counter A 32 bit saturating counter that increments upon each cache hit, @@ -213,37 +145,8 @@ typedef struct { /*!< (@ 0x14000000) XIP_CTRL Str whether the cache is hit or not. This includes noncacheable accesses. Write any value to clear. */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000014) FIFO stream address */ - - struct { - uint32_t : 2; - __IOM uint32_t STREAM_ADDR : 30; /*!< [31..2] The address of the next word to be streamed from flash - to the streaming FIFO. - Increments automatically after each flash access. - Write the initial access address here before starting a - streaming read. */ - } bit; - } STREAM_ADDR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000018) FIFO stream control */ - - struct { - __IOM uint32_t STREAM_CTR : 22; /*!< [21..0] Write a nonzero value to start a streaming read. This - will then - progress in the background, using flash idle cycles to - transfer - a linear data block from flash to the streaming FIFO. - Decrements automatically (1 at a time) as the stream - progresses, and halts on reaching 0. - Write 0 to halt an in-progress stream, and discard any - in-flight - read, so that a new stream can immediately be started (aft */ - uint32_t : 10; - } bit; - } STREAM_CTR; + __IOM uint32_t STREAM_ADDR; /*!< (@ 0x00000014) FIFO stream address */ + __IOM uint32_t STREAM_CTR; /*!< (@ 0x00000018) FIFO stream control */ __IM uint32_t STREAM_FIFO; /*!< (@ 0x0000001C) FIFO stream data Streamed data is buffered here, for retrieval by the system DMA. @@ -290,306 +193,35 @@ typedef struct { /*!< (@ 0x14000000) XIP_CTRL Str */ typedef struct { /*!< (@ 0x18000000) XIP_SSI Structure */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Control register 0 */ - - struct { - __IOM uint32_t DFS : 4; /*!< [3..0] Data frame size */ - __IOM uint32_t FRF : 2; /*!< [5..4] Frame format */ - __IOM uint32_t SCPH : 1; /*!< [6..6] Serial clock phase */ - __IOM uint32_t SCPOL : 1; /*!< [7..7] Serial clock polarity */ - __IOM uint32_t TMOD : 2; /*!< [9..8] Transfer mode */ - __IOM uint32_t SLV_OE : 1; /*!< [10..10] Slave output enable */ - __IOM uint32_t SRL : 1; /*!< [11..11] Shift register loop (test mode) */ - __IOM uint32_t CFS : 4; /*!< [15..12] Control frame size - Value of n -> n+1 clocks per frame. */ - __IOM uint32_t DFS_32 : 5; /*!< [20..16] Data frame size in 32b transfer mode - Value of n -> n+1 clocks per frame. */ - __IOM uint32_t SPI_FRF : 2; /*!< [22..21] SPI frame format */ - uint32_t : 1; - __IOM uint32_t SSTE : 1; /*!< [24..24] Slave select toggle enable */ - uint32_t : 7; - } bit; - } CTRLR0; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Master Control register 1 */ - - struct { - __IOM uint32_t NDF : 16; /*!< [15..0] Number of data frames */ - uint32_t : 16; - } bit; - } CTRLR1; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000008) SSI Enable */ - - struct { - __IOM uint32_t SSI_EN : 1; /*!< [0..0] SSI enable */ - uint32_t : 31; - } bit; - } SSIENR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) Microwire Control */ - - struct { - __IOM uint32_t MWMOD : 1; /*!< [0..0] Microwire transfer mode */ - __IOM uint32_t MDD : 1; /*!< [1..1] Microwire control */ - __IOM uint32_t MHS : 1; /*!< [2..2] Microwire handshaking */ - uint32_t : 29; - } bit; - } MWCR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000010) Slave enable */ - - struct { - __IOM uint32_t SER : 1; /*!< [0..0] For each bit: - 0 -> slave not selected - 1 -> slave selected */ - uint32_t : 31; - } bit; - } SER; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000014) Baud rate */ - - struct { - __IOM uint32_t SCKDV : 16; /*!< [15..0] SSI clock divider */ - uint32_t : 16; - } bit; - } BAUDR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000018) TX FIFO threshold level */ - - struct { - __IOM uint32_t TFT : 8; /*!< [7..0] Transmit FIFO threshold */ - uint32_t : 24; - } bit; - } TXFTLR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) RX FIFO threshold level */ - - struct { - __IOM uint32_t RFT : 8; /*!< [7..0] Receive FIFO threshold */ - uint32_t : 24; - } bit; - } RXFTLR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000020) TX FIFO level */ - - struct { - __IM uint32_t TFTFL : 8; /*!< [7..0] Transmit FIFO level */ - uint32_t : 24; - } bit; - } TXFLR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000024) RX FIFO level */ - - struct { - __IM uint32_t RXTFL : 8; /*!< [7..0] Receive FIFO level */ - uint32_t : 24; - } bit; - } RXFLR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000028) Status register */ - - struct { - __IM uint32_t BUSY : 1; /*!< [0..0] SSI busy flag */ - __IM uint32_t TFNF : 1; /*!< [1..1] Transmit FIFO not full */ - __IM uint32_t TFE : 1; /*!< [2..2] Transmit FIFO empty */ - __IM uint32_t RFNE : 1; /*!< [3..3] Receive FIFO not empty */ - __IM uint32_t RFF : 1; /*!< [4..4] Receive FIFO full */ - __IM uint32_t TXE : 1; /*!< [5..5] Transmission error */ - __IM uint32_t DCOL : 1; /*!< [6..6] Data collision error */ - uint32_t : 25; - } bit; - } SR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000002C) Interrupt mask */ - - struct { - __IOM uint32_t TXEIM : 1; /*!< [0..0] Transmit FIFO empty interrupt mask */ - __IOM uint32_t TXOIM : 1; /*!< [1..1] Transmit FIFO overflow interrupt mask */ - __IOM uint32_t RXUIM : 1; /*!< [2..2] Receive FIFO underflow interrupt mask */ - __IOM uint32_t RXOIM : 1; /*!< [3..3] Receive FIFO overflow interrupt mask */ - __IOM uint32_t RXFIM : 1; /*!< [4..4] Receive FIFO full interrupt mask */ - __IOM uint32_t MSTIM : 1; /*!< [5..5] Multi-master contention interrupt mask */ - uint32_t : 26; - } bit; - } IMR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000030) Interrupt status */ - - struct { - __IM uint32_t TXEIS : 1; /*!< [0..0] Transmit FIFO empty interrupt status */ - __IM uint32_t TXOIS : 1; /*!< [1..1] Transmit FIFO overflow interrupt status */ - __IM uint32_t RXUIS : 1; /*!< [2..2] Receive FIFO underflow interrupt status */ - __IM uint32_t RXOIS : 1; /*!< [3..3] Receive FIFO overflow interrupt status */ - __IM uint32_t RXFIS : 1; /*!< [4..4] Receive FIFO full interrupt status */ - __IM uint32_t MSTIS : 1; /*!< [5..5] Multi-master contention interrupt status */ - uint32_t : 26; - } bit; - } ISR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000034) Raw interrupt status */ - - struct { - __IM uint32_t TXEIR : 1; /*!< [0..0] Transmit FIFO empty raw interrupt status */ - __IM uint32_t TXOIR : 1; /*!< [1..1] Transmit FIFO overflow raw interrupt status */ - __IM uint32_t RXUIR : 1; /*!< [2..2] Receive FIFO underflow raw interrupt status */ - __IM uint32_t RXOIR : 1; /*!< [3..3] Receive FIFO overflow raw interrupt status */ - __IM uint32_t RXFIR : 1; /*!< [4..4] Receive FIFO full raw interrupt status */ - __IM uint32_t MSTIR : 1; /*!< [5..5] Multi-master contention raw interrupt status */ - uint32_t : 26; - } bit; - } RISR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000038) TX FIFO overflow interrupt clear */ - - struct { - __IM uint32_t TXOICR : 1; /*!< [0..0] Clear-on-read transmit FIFO overflow interrupt */ - uint32_t : 31; - } bit; - } TXOICR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000003C) RX FIFO overflow interrupt clear */ - - struct { - __IM uint32_t RXOICR : 1; /*!< [0..0] Clear-on-read receive FIFO overflow interrupt */ - uint32_t : 31; - } bit; - } RXOICR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000040) RX FIFO underflow interrupt clear */ - - struct { - __IM uint32_t RXUICR : 1; /*!< [0..0] Clear-on-read receive FIFO underflow interrupt */ - uint32_t : 31; - } bit; - } RXUICR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000044) Multi-master interrupt clear */ - - struct { - __IM uint32_t MSTICR : 1; /*!< [0..0] Clear-on-read multi-master contention interrupt */ - uint32_t : 31; - } bit; - } MSTICR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000048) Interrupt clear */ - - struct { - __IM uint32_t ICR : 1; /*!< [0..0] Clear-on-read all active interrupts */ - uint32_t : 31; - } bit; - } ICR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000004C) DMA control */ - - struct { - __IOM uint32_t RDMAE : 1; /*!< [0..0] Receive DMA enable */ - __IOM uint32_t TDMAE : 1; /*!< [1..1] Transmit DMA enable */ - uint32_t : 30; - } bit; - } DMACR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000050) DMA TX data level */ - - struct { - __IOM uint32_t DMATDL : 8; /*!< [7..0] Transmit data watermark level */ - uint32_t : 24; - } bit; - } DMATDLR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000054) DMA RX data level */ - - struct { - __IOM uint32_t DMARDL : 8; /*!< [7..0] Receive data watermark level (DMARDLR+1) */ - uint32_t : 24; - } bit; - } DMARDLR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000058) Identification register */ - - struct { - __IM uint32_t IDCODE : 32; /*!< [31..0] Peripheral dentification code */ - } bit; - } IDR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000005C) Version ID */ - - struct { - __IM uint32_t SSI_COMP_VERSION : 32; /*!< [31..0] SNPS component version (format X.YY) */ - } bit; - } SSI_VERSION_ID; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000060) Data Register 0 (of 36) */ - - struct { - __IOM uint32_t DR : 32; /*!< [31..0] First data register of 36 */ - } bit; - } DR0; + __IOM uint32_t CTRLR0; /*!< (@ 0x00000000) Control register 0 */ + __IOM uint32_t CTRLR1; /*!< (@ 0x00000004) Master Control register 1 */ + __IOM uint32_t SSIENR; /*!< (@ 0x00000008) SSI Enable */ + __IOM uint32_t MWCR; /*!< (@ 0x0000000C) Microwire Control */ + __IOM uint32_t SER; /*!< (@ 0x00000010) Slave enable */ + __IOM uint32_t BAUDR; /*!< (@ 0x00000014) Baud rate */ + __IOM uint32_t TXFTLR; /*!< (@ 0x00000018) TX FIFO threshold level */ + __IOM uint32_t RXFTLR; /*!< (@ 0x0000001C) RX FIFO threshold level */ + __IOM uint32_t TXFLR; /*!< (@ 0x00000020) TX FIFO level */ + __IOM uint32_t RXFLR; /*!< (@ 0x00000024) RX FIFO level */ + __IOM uint32_t SR; /*!< (@ 0x00000028) Status register */ + __IOM uint32_t IMR; /*!< (@ 0x0000002C) Interrupt mask */ + __IOM uint32_t ISR; /*!< (@ 0x00000030) Interrupt status */ + __IOM uint32_t RISR; /*!< (@ 0x00000034) Raw interrupt status */ + __IOM uint32_t TXOICR; /*!< (@ 0x00000038) TX FIFO overflow interrupt clear */ + __IOM uint32_t RXOICR; /*!< (@ 0x0000003C) RX FIFO overflow interrupt clear */ + __IOM uint32_t RXUICR; /*!< (@ 0x00000040) RX FIFO underflow interrupt clear */ + __IOM uint32_t MSTICR; /*!< (@ 0x00000044) Multi-master interrupt clear */ + __IOM uint32_t ICR; /*!< (@ 0x00000048) Interrupt clear */ + __IOM uint32_t DMACR; /*!< (@ 0x0000004C) DMA control */ + __IOM uint32_t DMATDLR; /*!< (@ 0x00000050) DMA TX data level */ + __IOM uint32_t DMARDLR; /*!< (@ 0x00000054) DMA RX data level */ + __IOM uint32_t IDR; /*!< (@ 0x00000058) Identification register */ + __IOM uint32_t SSI_VERSION_ID; /*!< (@ 0x0000005C) Version ID */ + __IOM uint32_t DR0; /*!< (@ 0x00000060) Data Register 0 (of 36) */ __IM uint32_t RESERVED[35]; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000F0) RX sample delay */ - - struct { - __IOM uint32_t RSD : 8; /*!< [7..0] RXD sample delay (in SCLK cycles) */ - uint32_t : 24; - } bit; - } RX_SAMPLE_DLY; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000F4) SPI control */ - - struct { - __IOM uint32_t TRANS_TYPE : 2; /*!< [1..0] Address and instruction transfer format */ - __IOM uint32_t ADDR_L : 4; /*!< [5..2] Address length (0b-60b in 4b increments) */ - uint32_t : 2; - __IOM uint32_t INST_L : 2; /*!< [9..8] Instruction length (0/4/8/16b) */ - uint32_t : 1; - __IOM uint32_t WAIT_CYCLES : 5; /*!< [15..11] Wait cycles between control frame transmit and data - reception (in SCLK cycles) */ - __IOM uint32_t SPI_DDR_EN : 1; /*!< [16..16] SPI DDR transfer enable */ - __IOM uint32_t INST_DDR_EN : 1; /*!< [17..17] Instruction DDR transfer enable */ - __IOM uint32_t SPI_RXDS_EN : 1; /*!< [18..18] Read data strobe enable */ - uint32_t : 5; - __IOM uint32_t XIP_CMD : 8; /*!< [31..24] SPI Command to send in XIP mode (INST_L = 8-bit) or - to append to Address (INST_L = 0-bit) */ - } bit; - } SPI_CTRLR0; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000F8) TX drive edge */ - - struct { - __IOM uint32_t TDE : 8; /*!< [7..0] TXD drive edge */ - uint32_t : 24; - } bit; - } TXD_DRIVE_EDGE; + __IOM uint32_t RX_SAMPLE_DLY; /*!< (@ 0x000000F0) RX sample delay */ + __IOM uint32_t SPI_CTRLR0; /*!< (@ 0x000000F4) SPI control */ + __IOM uint32_t TXD_DRIVE_EDGE; /*!< (@ 0x000000F8) TX drive edge */ } XIP_SSI_Type; /*!< Size = 252 (0xfc) */ @@ -604,27 +236,9 @@ typedef struct { /*!< (@ 0x18000000) XIP_SSI Stru */ typedef struct { /*!< (@ 0x40000000) SYSINFO Structure */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000000) JEDEC JEP-106 compliant chip identifier. */ - - struct { - __IM uint32_t MANUFACTURER : 12; /*!< [11..0] MANUFACTURER */ - __IM uint32_t PART : 16; /*!< [27..12] PART */ - __IM uint32_t REVISION : 4; /*!< [31..28] REVISION */ - } bit; - } CHIP_ID; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Platform register. Allows software to know what + __IOM uint32_t CHIP_ID; /*!< (@ 0x00000000) JEDEC JEP-106 compliant chip identifier. */ + __IOM uint32_t PLATFORM; /*!< (@ 0x00000004) Platform register. Allows software to know what environment it is running in. */ - - struct { - __IM uint32_t FPGA : 1; /*!< [0..0] FPGA */ - __IM uint32_t ASIC : 1; /*!< [1..1] ASIC */ - uint32_t : 30; - } bit; - } PLATFORM; __IM uint32_t RESERVED[14]; __IM uint32_t GITREF_RP2040; /*!< (@ 0x00000040) Git hash of the chip source. Used to identify chip version. */ @@ -646,27 +260,8 @@ typedef struct { /*!< (@ 0x40004000) SYSCFG Struc Set a bit high to enable NMI from that IRQ */ __IOM uint32_t PROC1_NMI_MASK; /*!< (@ 0x00000004) Processor core 1 NMI source mask Set a bit high to enable NMI from that IRQ */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000008) Configuration for processors */ - - struct { - __IM uint32_t PROC0_HALTED : 1; /*!< [0..0] Indication that proc0 has halted */ - __IM uint32_t PROC1_HALTED : 1; /*!< [1..1] Indication that proc1 has halted */ - uint32_t : 22; - __IOM uint32_t PROC0_DAP_INSTID : 4; /*!< [27..24] Configure proc0 DAP instance ID. - Recommend that this is NOT changed until you require debug - access in multi-chip environment - WARNING: do not set to 15 as this is reserved for RescueDP */ - __IOM uint32_t PROC1_DAP_INSTID : 4; /*!< [31..28] Configure proc1 DAP instance ID. - Recommend that this is NOT changed until you require debug - access in multi-chip environment - WARNING: do not set to 15 as this is reserved for RescueDP */ - } bit; - } PROC_CONFIG; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) For each bit, if 1, bypass the input synchronizer + __IOM uint32_t PROC_CONFIG; /*!< (@ 0x00000008) Configuration for processors */ + __IOM uint32_t PROC_IN_SYNC_BYPASS; /*!< (@ 0x0000000C) For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should @@ -675,15 +270,7 @@ typedef struct { /*!< (@ 0x40004000) SYSCFG Struc If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 0...29. */ - - struct { - __IOM uint32_t PROC_IN_SYNC_BYPASS : 30; /*!< [29..0] PROC_IN_SYNC_BYPASS */ - uint32_t : 2; - } bit; - } PROC_IN_SYNC_BYPASS; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000010) For each bit, if 1, bypass the input synchronizer + __IOM uint32_t PROC_IN_SYNC_BYPASS_HI; /*!< (@ 0x00000010) For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should @@ -693,53 +280,11 @@ typedef struct { /*!< (@ 0x40004000) SYSCFG Struc to save two cycles of input latency. This register applies to GPIO 30...35 (the QSPI IOs). */ - - struct { - __IOM uint32_t PROC_IN_SYNC_BYPASS_HI : 6;/*!< [5..0] PROC_IN_SYNC_BYPASS_HI */ - uint32_t : 26; - } bit; - } PROC_IN_SYNC_BYPASS_HI; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000014) Directly control the SWD debug port of either + __IOM uint32_t DBGFORCE; /*!< (@ 0x00000014) Directly control the SWD debug port of either processor */ - - struct { - __IM uint32_t PROC0_SWDO : 1; /*!< [0..0] Observe the value of processor 0 SWDIO output. */ - __IOM uint32_t PROC0_SWDI : 1; /*!< [1..1] Directly drive processor 0 SWDIO input, if PROC0_ATTACH - is set */ - __IOM uint32_t PROC0_SWCLK : 1; /*!< [2..2] Directly drive processor 0 SWCLK, if PROC0_ATTACH is - set */ - __IOM uint32_t PROC0_ATTACH : 1; /*!< [3..3] Attach processor 0 debug port to syscfg controls, and - disconnect it from external SWD pads. */ - __IM uint32_t PROC1_SWDO : 1; /*!< [4..4] Observe the value of processor 1 SWDIO output. */ - __IOM uint32_t PROC1_SWDI : 1; /*!< [5..5] Directly drive processor 1 SWDIO input, if PROC1_ATTACH - is set */ - __IOM uint32_t PROC1_SWCLK : 1; /*!< [6..6] Directly drive processor 1 SWCLK, if PROC1_ATTACH is - set */ - __IOM uint32_t PROC1_ATTACH : 1; /*!< [7..7] Attach processor 1 debug port to syscfg controls, and - disconnect it from external SWD pads. */ - uint32_t : 24; - } bit; - } DBGFORCE; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000018) Control power downs to memories. Set high to + __IOM uint32_t MEMPOWERDOWN; /*!< (@ 0x00000018) Control power downs to memories. Set high to power down memories. Use with extreme caution */ - - struct { - __IOM uint32_t SRAM0 : 1; /*!< [0..0] SRAM0 */ - __IOM uint32_t SRAM1 : 1; /*!< [1..1] SRAM1 */ - __IOM uint32_t SRAM2 : 1; /*!< [2..2] SRAM2 */ - __IOM uint32_t SRAM3 : 1; /*!< [3..3] SRAM3 */ - __IOM uint32_t SRAM4 : 1; /*!< [4..4] SRAM4 */ - __IOM uint32_t SRAM5 : 1; /*!< [5..5] SRAM5 */ - __IOM uint32_t USB : 1; /*!< [6..6] USB */ - __IOM uint32_t ROM : 1; /*!< [7..7] ROM */ - uint32_t : 24; - } bit; - } MEMPOWERDOWN; } SYSCFG_Type; /*!< Size = 28 (0x1c) */ @@ -754,664 +299,133 @@ typedef struct { /*!< (@ 0x40004000) SYSCFG Struc */ typedef struct { /*!< (@ 0x40008000) CLOCKS Structure */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Clock control, can be changed on-the-fly (except + __IOM uint32_t CLK_GPOUT0_CTRL; /*!< (@ 0x00000000) Clock control, can be changed on-the-fly (except for auxsrc) */ - - struct { - uint32_t : 5; - __IOM uint32_t AUXSRC : 4; /*!< [8..5] Selects the auxiliary clock source, will glitch when - switching */ - uint32_t : 1; - __IOM uint32_t KILL : 1; /*!< [10..10] Asynchronously kills the clock generator */ - __IOM uint32_t ENABLE : 1; /*!< [11..11] Starts and stops the clock generator cleanly */ - __IOM uint32_t DC50 : 1; /*!< [12..12] Enables duty cycle correction for odd divisors */ - uint32_t : 3; - __IOM uint32_t PHASE : 2; /*!< [17..16] This delays the enable signal by up to 3 cycles of - the input clock - This must be set before the clock is enabled to have any - effect */ - uint32_t : 2; - __IOM uint32_t NUDGE : 1; /*!< [20..20] An edge on this signal shifts the phase of the output - by 1 cycle of the input clock - This can be done at any time */ - uint32_t : 11; - } bit; - } CLK_GPOUT0_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Clock divisor, can be changed on-the-fly */ - - struct { - __IOM uint32_t FRAC : 8; /*!< [7..0] Fractional component of the divisor */ - __IOM uint32_t INT : 24; /*!< [31..8] Integer component of the divisor, 0 -> divide by 2^16 */ - } bit; - } CLK_GPOUT0_DIV; - __IM uint32_t CLK_GPOUT0_SELECTED; /*!< (@ 0x00000008) Indicates which src is currently selected (one-hot) */ - - union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) Clock control, can be changed on-the-fly (except + __IOM uint32_t CLK_GPOUT0_DIV; /*!< (@ 0x00000004) Clock divisor, can be changed on-the-fly */ + __IM uint32_t CLK_GPOUT0_SELECTED; /*!< (@ 0x00000008) Indicates which SRC is currently selected by + the glitchless mux (one-hot). + This slice does not have a glitchless mux + (only the AUX_SRC field is present, not + SRC) so this register is hardwired to 0x1. */ + __IOM uint32_t CLK_GPOUT1_CTRL; /*!< (@ 0x0000000C) Clock control, can be changed on-the-fly (except for auxsrc) */ - - struct { - uint32_t : 5; - __IOM uint32_t AUXSRC : 4; /*!< [8..5] Selects the auxiliary clock source, will glitch when - switching */ - uint32_t : 1; - __IOM uint32_t KILL : 1; /*!< [10..10] Asynchronously kills the clock generator */ - __IOM uint32_t ENABLE : 1; /*!< [11..11] Starts and stops the clock generator cleanly */ - __IOM uint32_t DC50 : 1; /*!< [12..12] Enables duty cycle correction for odd divisors */ - uint32_t : 3; - __IOM uint32_t PHASE : 2; /*!< [17..16] This delays the enable signal by up to 3 cycles of - the input clock - This must be set before the clock is enabled to have any - effect */ - uint32_t : 2; - __IOM uint32_t NUDGE : 1; /*!< [20..20] An edge on this signal shifts the phase of the output - by 1 cycle of the input clock - This can be done at any time */ - uint32_t : 11; - } bit; - } CLK_GPOUT1_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000010) Clock divisor, can be changed on-the-fly */ - - struct { - __IOM uint32_t FRAC : 8; /*!< [7..0] Fractional component of the divisor */ - __IOM uint32_t INT : 24; /*!< [31..8] Integer component of the divisor, 0 -> divide by 2^16 */ - } bit; - } CLK_GPOUT1_DIV; - __IM uint32_t CLK_GPOUT1_SELECTED; /*!< (@ 0x00000014) Indicates which src is currently selected (one-hot) */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000018) Clock control, can be changed on-the-fly (except + __IOM uint32_t CLK_GPOUT1_DIV; /*!< (@ 0x00000010) Clock divisor, can be changed on-the-fly */ + __IM uint32_t CLK_GPOUT1_SELECTED; /*!< (@ 0x00000014) Indicates which SRC is currently selected by + the glitchless mux (one-hot). + This slice does not have a glitchless mux + (only the AUX_SRC field is present, not + SRC) so this register is hardwired to 0x1. */ + __IOM uint32_t CLK_GPOUT2_CTRL; /*!< (@ 0x00000018) Clock control, can be changed on-the-fly (except for auxsrc) */ - - struct { - uint32_t : 5; - __IOM uint32_t AUXSRC : 4; /*!< [8..5] Selects the auxiliary clock source, will glitch when - switching */ - uint32_t : 1; - __IOM uint32_t KILL : 1; /*!< [10..10] Asynchronously kills the clock generator */ - __IOM uint32_t ENABLE : 1; /*!< [11..11] Starts and stops the clock generator cleanly */ - __IOM uint32_t DC50 : 1; /*!< [12..12] Enables duty cycle correction for odd divisors */ - uint32_t : 3; - __IOM uint32_t PHASE : 2; /*!< [17..16] This delays the enable signal by up to 3 cycles of - the input clock - This must be set before the clock is enabled to have any - effect */ - uint32_t : 2; - __IOM uint32_t NUDGE : 1; /*!< [20..20] An edge on this signal shifts the phase of the output - by 1 cycle of the input clock - This can be done at any time */ - uint32_t : 11; - } bit; - } CLK_GPOUT2_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) Clock divisor, can be changed on-the-fly */ - - struct { - __IOM uint32_t FRAC : 8; /*!< [7..0] Fractional component of the divisor */ - __IOM uint32_t INT : 24; /*!< [31..8] Integer component of the divisor, 0 -> divide by 2^16 */ - } bit; - } CLK_GPOUT2_DIV; - __IM uint32_t CLK_GPOUT2_SELECTED; /*!< (@ 0x00000020) Indicates which src is currently selected (one-hot) */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000024) Clock control, can be changed on-the-fly (except + __IOM uint32_t CLK_GPOUT2_DIV; /*!< (@ 0x0000001C) Clock divisor, can be changed on-the-fly */ + __IM uint32_t CLK_GPOUT2_SELECTED; /*!< (@ 0x00000020) Indicates which SRC is currently selected by + the glitchless mux (one-hot). + This slice does not have a glitchless mux + (only the AUX_SRC field is present, not + SRC) so this register is hardwired to 0x1. */ + __IOM uint32_t CLK_GPOUT3_CTRL; /*!< (@ 0x00000024) Clock control, can be changed on-the-fly (except for auxsrc) */ - - struct { - uint32_t : 5; - __IOM uint32_t AUXSRC : 4; /*!< [8..5] Selects the auxiliary clock source, will glitch when - switching */ - uint32_t : 1; - __IOM uint32_t KILL : 1; /*!< [10..10] Asynchronously kills the clock generator */ - __IOM uint32_t ENABLE : 1; /*!< [11..11] Starts and stops the clock generator cleanly */ - __IOM uint32_t DC50 : 1; /*!< [12..12] Enables duty cycle correction for odd divisors */ - uint32_t : 3; - __IOM uint32_t PHASE : 2; /*!< [17..16] This delays the enable signal by up to 3 cycles of - the input clock - This must be set before the clock is enabled to have any - effect */ - uint32_t : 2; - __IOM uint32_t NUDGE : 1; /*!< [20..20] An edge on this signal shifts the phase of the output - by 1 cycle of the input clock - This can be done at any time */ - uint32_t : 11; - } bit; - } CLK_GPOUT3_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000028) Clock divisor, can be changed on-the-fly */ - - struct { - __IOM uint32_t FRAC : 8; /*!< [7..0] Fractional component of the divisor */ - __IOM uint32_t INT : 24; /*!< [31..8] Integer component of the divisor, 0 -> divide by 2^16 */ - } bit; - } CLK_GPOUT3_DIV; - __IM uint32_t CLK_GPOUT3_SELECTED; /*!< (@ 0x0000002C) Indicates which src is currently selected (one-hot) */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000030) Clock control, can be changed on-the-fly (except + __IOM uint32_t CLK_GPOUT3_DIV; /*!< (@ 0x00000028) Clock divisor, can be changed on-the-fly */ + __IM uint32_t CLK_GPOUT3_SELECTED; /*!< (@ 0x0000002C) Indicates which SRC is currently selected by + the glitchless mux (one-hot). + This slice does not have a glitchless mux + (only the AUX_SRC field is present, not + SRC) so this register is hardwired to 0x1. */ + __IOM uint32_t CLK_REF_CTRL; /*!< (@ 0x00000030) Clock control, can be changed on-the-fly (except for auxsrc) */ - - struct { - __IOM uint32_t SRC : 2; /*!< [1..0] Selects the clock source glitchlessly, can be changed - on-the-fly */ - uint32_t : 3; - __IOM uint32_t AUXSRC : 2; /*!< [6..5] Selects the auxiliary clock source, will glitch when - switching */ - uint32_t : 25; - } bit; - } CLK_REF_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000034) Clock divisor, can be changed on-the-fly */ - - struct { - uint32_t : 8; - __IOM uint32_t INT : 2; /*!< [9..8] Integer component of the divisor, 0 -> divide by 2^16 */ - uint32_t : 22; - } bit; - } CLK_REF_DIV; - __IM uint32_t CLK_REF_SELECTED; /*!< (@ 0x00000038) Indicates which src is currently selected (one-hot) */ - - union { - __IOM uint32_t reg; /*!< (@ 0x0000003C) Clock control, can be changed on-the-fly (except + __IOM uint32_t CLK_REF_DIV; /*!< (@ 0x00000034) Clock divisor, can be changed on-the-fly */ + __IM uint32_t CLK_REF_SELECTED; /*!< (@ 0x00000038) Indicates which SRC is currently selected by + the glitchless mux (one-hot). + The glitchless multiplexer does not switch + instantaneously (to avoid glitches), so + software should poll this register to wait + for the switch to complete. This register + contains one decoded bit for each of the + clock sources enumerated in the CTRL SRC + field. At most one of these bits will be + set at any time, indicating that clock is + currently present at the output of the glitchless + mux. Whilst switching i */ + __IOM uint32_t CLK_SYS_CTRL; /*!< (@ 0x0000003C) Clock control, can be changed on-the-fly (except for auxsrc) */ - - struct { - __IOM uint32_t SRC : 1; /*!< [0..0] Selects the clock source glitchlessly, can be changed - on-the-fly */ - uint32_t : 4; - __IOM uint32_t AUXSRC : 3; /*!< [7..5] Selects the auxiliary clock source, will glitch when - switching */ - uint32_t : 24; - } bit; - } CLK_SYS_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000040) Clock divisor, can be changed on-the-fly */ - - struct { - __IOM uint32_t FRAC : 8; /*!< [7..0] Fractional component of the divisor */ - __IOM uint32_t INT : 24; /*!< [31..8] Integer component of the divisor, 0 -> divide by 2^16 */ - } bit; - } CLK_SYS_DIV; - __IM uint32_t CLK_SYS_SELECTED; /*!< (@ 0x00000044) Indicates which src is currently selected (one-hot) */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000048) Clock control, can be changed on-the-fly (except + __IOM uint32_t CLK_SYS_DIV; /*!< (@ 0x00000040) Clock divisor, can be changed on-the-fly */ + __IM uint32_t CLK_SYS_SELECTED; /*!< (@ 0x00000044) Indicates which SRC is currently selected by + the glitchless mux (one-hot). + The glitchless multiplexer does not switch + instantaneously (to avoid glitches), so + software should poll this register to wait + for the switch to complete. This register + contains one decoded bit for each of the + clock sources enumerated in the CTRL SRC + field. At most one of these bits will be + set at any time, indicating that clock is + currently present at the output of the glitchless + mux. Whilst switching i */ + __IOM uint32_t CLK_PERI_CTRL; /*!< (@ 0x00000048) Clock control, can be changed on-the-fly (except for auxsrc) */ - - struct { - uint32_t : 5; - __IOM uint32_t AUXSRC : 3; /*!< [7..5] Selects the auxiliary clock source, will glitch when - switching */ - uint32_t : 2; - __IOM uint32_t KILL : 1; /*!< [10..10] Asynchronously kills the clock generator */ - __IOM uint32_t ENABLE : 1; /*!< [11..11] Starts and stops the clock generator cleanly */ - uint32_t : 20; - } bit; - } CLK_PERI_CTRL; __IM uint32_t RESERVED; - __IM uint32_t CLK_PERI_SELECTED; /*!< (@ 0x00000050) Indicates which src is currently selected (one-hot) */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000054) Clock control, can be changed on-the-fly (except + __IM uint32_t CLK_PERI_SELECTED; /*!< (@ 0x00000050) Indicates which SRC is currently selected by + the glitchless mux (one-hot). + This slice does not have a glitchless mux + (only the AUX_SRC field is present, not + SRC) so this register is hardwired to 0x1. */ + __IOM uint32_t CLK_USB_CTRL; /*!< (@ 0x00000054) Clock control, can be changed on-the-fly (except for auxsrc) */ - - struct { - uint32_t : 5; - __IOM uint32_t AUXSRC : 3; /*!< [7..5] Selects the auxiliary clock source, will glitch when - switching */ - uint32_t : 2; - __IOM uint32_t KILL : 1; /*!< [10..10] Asynchronously kills the clock generator */ - __IOM uint32_t ENABLE : 1; /*!< [11..11] Starts and stops the clock generator cleanly */ - uint32_t : 4; - __IOM uint32_t PHASE : 2; /*!< [17..16] This delays the enable signal by up to 3 cycles of - the input clock - This must be set before the clock is enabled to have any - effect */ - uint32_t : 2; - __IOM uint32_t NUDGE : 1; /*!< [20..20] An edge on this signal shifts the phase of the output - by 1 cycle of the input clock - This can be done at any time */ - uint32_t : 11; - } bit; - } CLK_USB_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000058) Clock divisor, can be changed on-the-fly */ - - struct { - uint32_t : 8; - __IOM uint32_t INT : 2; /*!< [9..8] Integer component of the divisor, 0 -> divide by 2^16 */ - uint32_t : 22; - } bit; - } CLK_USB_DIV; - __IM uint32_t CLK_USB_SELECTED; /*!< (@ 0x0000005C) Indicates which src is currently selected (one-hot) */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000060) Clock control, can be changed on-the-fly (except + __IOM uint32_t CLK_USB_DIV; /*!< (@ 0x00000058) Clock divisor, can be changed on-the-fly */ + __IM uint32_t CLK_USB_SELECTED; /*!< (@ 0x0000005C) Indicates which SRC is currently selected by + the glitchless mux (one-hot). + This slice does not have a glitchless mux + (only the AUX_SRC field is present, not + SRC) so this register is hardwired to 0x1. */ + __IOM uint32_t CLK_ADC_CTRL; /*!< (@ 0x00000060) Clock control, can be changed on-the-fly (except for auxsrc) */ - - struct { - uint32_t : 5; - __IOM uint32_t AUXSRC : 3; /*!< [7..5] Selects the auxiliary clock source, will glitch when - switching */ - uint32_t : 2; - __IOM uint32_t KILL : 1; /*!< [10..10] Asynchronously kills the clock generator */ - __IOM uint32_t ENABLE : 1; /*!< [11..11] Starts and stops the clock generator cleanly */ - uint32_t : 4; - __IOM uint32_t PHASE : 2; /*!< [17..16] This delays the enable signal by up to 3 cycles of - the input clock - This must be set before the clock is enabled to have any - effect */ - uint32_t : 2; - __IOM uint32_t NUDGE : 1; /*!< [20..20] An edge on this signal shifts the phase of the output - by 1 cycle of the input clock - This can be done at any time */ - uint32_t : 11; - } bit; - } CLK_ADC_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000064) Clock divisor, can be changed on-the-fly */ - - struct { - uint32_t : 8; - __IOM uint32_t INT : 2; /*!< [9..8] Integer component of the divisor, 0 -> divide by 2^16 */ - uint32_t : 22; - } bit; - } CLK_ADC_DIV; - __IM uint32_t CLK_ADC_SELECTED; /*!< (@ 0x00000068) Indicates which src is currently selected (one-hot) */ - - union { - __IOM uint32_t reg; /*!< (@ 0x0000006C) Clock control, can be changed on-the-fly (except + __IOM uint32_t CLK_ADC_DIV; /*!< (@ 0x00000064) Clock divisor, can be changed on-the-fly */ + __IM uint32_t CLK_ADC_SELECTED; /*!< (@ 0x00000068) Indicates which SRC is currently selected by + the glitchless mux (one-hot). + This slice does not have a glitchless mux + (only the AUX_SRC field is present, not + SRC) so this register is hardwired to 0x1. */ + __IOM uint32_t CLK_RTC_CTRL; /*!< (@ 0x0000006C) Clock control, can be changed on-the-fly (except for auxsrc) */ - - struct { - uint32_t : 5; - __IOM uint32_t AUXSRC : 3; /*!< [7..5] Selects the auxiliary clock source, will glitch when - switching */ - uint32_t : 2; - __IOM uint32_t KILL : 1; /*!< [10..10] Asynchronously kills the clock generator */ - __IOM uint32_t ENABLE : 1; /*!< [11..11] Starts and stops the clock generator cleanly */ - uint32_t : 4; - __IOM uint32_t PHASE : 2; /*!< [17..16] This delays the enable signal by up to 3 cycles of - the input clock - This must be set before the clock is enabled to have any - effect */ - uint32_t : 2; - __IOM uint32_t NUDGE : 1; /*!< [20..20] An edge on this signal shifts the phase of the output - by 1 cycle of the input clock - This can be done at any time */ - uint32_t : 11; - } bit; - } CLK_RTC_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000070) Clock divisor, can be changed on-the-fly */ - - struct { - __IOM uint32_t FRAC : 8; /*!< [7..0] Fractional component of the divisor */ - __IOM uint32_t INT : 24; /*!< [31..8] Integer component of the divisor, 0 -> divide by 2^16 */ - } bit; - } CLK_RTC_DIV; - __IM uint32_t CLK_RTC_SELECTED; /*!< (@ 0x00000074) Indicates which src is currently selected (one-hot) */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000078) CLK_SYS_RESUS_CTRL */ - - struct { - __IOM uint32_t TIMEOUT : 8; /*!< [7..0] This is expressed as a number of clk_ref cycles - and must be >= 2x clk_ref_freq/min_clk_tst_freq */ - __IOM uint32_t ENABLE : 1; /*!< [8..8] Enable resus */ - uint32_t : 3; - __IOM uint32_t FRCE : 1; /*!< [12..12] Force a resus, for test purposes only */ - uint32_t : 3; - __IOM uint32_t CLEAR : 1; /*!< [16..16] For clearing the resus after the fault that triggered - it has been corrected */ - uint32_t : 15; - } bit; - } CLK_SYS_RESUS_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000007C) CLK_SYS_RESUS_STATUS */ - - struct { - __IM uint32_t RESUSSED : 1; /*!< [0..0] Clock has been resuscitated, correct the error then send - ctrl_clear=1 */ - uint32_t : 31; - } bit; - } CLK_SYS_RESUS_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000080) Reference clock frequency in kHz */ - - struct { - __IOM uint32_t FC0_REF_KHZ : 20; /*!< [19..0] FC0_REF_KHZ */ - uint32_t : 12; - } bit; - } FC0_REF_KHZ; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000084) Minimum pass frequency in kHz. This is optional. + __IOM uint32_t CLK_RTC_DIV; /*!< (@ 0x00000070) Clock divisor, can be changed on-the-fly */ + __IM uint32_t CLK_RTC_SELECTED; /*!< (@ 0x00000074) Indicates which SRC is currently selected by + the glitchless mux (one-hot). + This slice does not have a glitchless mux + (only the AUX_SRC field is present, not + SRC) so this register is hardwired to 0x1. */ + __IOM uint32_t CLK_SYS_RESUS_CTRL; /*!< (@ 0x00000078) CLK_SYS_RESUS_CTRL */ + __IOM uint32_t CLK_SYS_RESUS_STATUS; /*!< (@ 0x0000007C) CLK_SYS_RESUS_STATUS */ + __IOM uint32_t FC0_REF_KHZ; /*!< (@ 0x00000080) Reference clock frequency in kHz */ + __IOM uint32_t FC0_MIN_KHZ; /*!< (@ 0x00000084) Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags */ - - struct { - __IOM uint32_t FC0_MIN_KHZ : 25; /*!< [24..0] FC0_MIN_KHZ */ - uint32_t : 7; - } bit; - } FC0_MIN_KHZ; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000088) Maximum pass frequency in kHz. This is optional. + __IOM uint32_t FC0_MAX_KHZ; /*!< (@ 0x00000088) Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags */ - - struct { - __IOM uint32_t FC0_MAX_KHZ : 25; /*!< [24..0] FC0_MAX_KHZ */ - uint32_t : 7; - } bit; - } FC0_MAX_KHZ; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000008C) Delays the start of frequency counting to allow + __IOM uint32_t FC0_DELAY; /*!< (@ 0x0000008C) Delays the start of frequency counting to allow the mux to settle Delay is measured in multiples of the reference clock period */ - - struct { - __IOM uint32_t FC0_DELAY : 3; /*!< [2..0] FC0_DELAY */ - uint32_t : 29; - } bit; - } FC0_DELAY; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000090) The test interval is 0.98us * 2**interval, but + __IOM uint32_t FC0_INTERVAL; /*!< (@ 0x00000090) The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval The default gives a test interval of 250us */ - - struct { - __IOM uint32_t FC0_INTERVAL : 4; /*!< [3..0] FC0_INTERVAL */ - uint32_t : 28; - } bit; - } FC0_INTERVAL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000094) Clock sent to frequency counter, set to 0 when + __IOM uint32_t FC0_SRC; /*!< (@ 0x00000094) Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count */ - - struct { - __IOM uint32_t FC0_SRC : 8; /*!< [7..0] FC0_SRC */ - uint32_t : 24; - } bit; - } FC0_SRC; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000098) Frequency counter status */ - - struct { - __IM uint32_t PASS : 1; /*!< [0..0] Test passed */ - uint32_t : 3; - __IM uint32_t DONE : 1; /*!< [4..4] Test complete */ - uint32_t : 3; - __IM uint32_t RUNNING : 1; /*!< [8..8] Test running */ - uint32_t : 3; - __IM uint32_t WAITING : 1; /*!< [12..12] Waiting for test clock to start */ - uint32_t : 3; - __IM uint32_t FAIL : 1; /*!< [16..16] Test failed */ - uint32_t : 3; - __IM uint32_t SLOW : 1; /*!< [20..20] Test clock slower than expected, only valid when status_done=1 */ - uint32_t : 3; - __IM uint32_t FAST : 1; /*!< [24..24] Test clock faster than expected, only valid when status_done=1 */ - uint32_t : 3; - __IM uint32_t DIED : 1; /*!< [28..28] Test clock stopped during test */ - uint32_t : 3; - } bit; - } FC0_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000009C) Result of frequency measurement, only valid when + __IOM uint32_t FC0_STATUS; /*!< (@ 0x00000098) Frequency counter status */ + __IOM uint32_t FC0_RESULT; /*!< (@ 0x0000009C) Result of frequency measurement, only valid when status_done=1 */ - - struct { - __IM uint32_t FRAC : 5; /*!< [4..0] FRAC */ - __IM uint32_t KHZ : 25; /*!< [29..5] KHZ */ - uint32_t : 2; - } bit; - } FC0_RESULT; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000A0) enable clock in wake mode */ - - struct { - __IOM uint32_t clk_sys_clocks : 1; /*!< [0..0] clk_sys_clocks */ - __IOM uint32_t clk_adc_adc : 1; /*!< [1..1] clk_adc_adc */ - __IOM uint32_t clk_sys_adc : 1; /*!< [2..2] clk_sys_adc */ - __IOM uint32_t clk_sys_busctrl : 1; /*!< [3..3] clk_sys_busctrl */ - __IOM uint32_t clk_sys_busfabric : 1; /*!< [4..4] clk_sys_busfabric */ - __IOM uint32_t clk_sys_dma : 1; /*!< [5..5] clk_sys_dma */ - __IOM uint32_t clk_sys_i2c0 : 1; /*!< [6..6] clk_sys_i2c0 */ - __IOM uint32_t clk_sys_i2c1 : 1; /*!< [7..7] clk_sys_i2c1 */ - __IOM uint32_t clk_sys_io : 1; /*!< [8..8] clk_sys_io */ - __IOM uint32_t clk_sys_jtag : 1; /*!< [9..9] clk_sys_jtag */ - __IOM uint32_t clk_sys_vreg_and_chip_reset : 1;/*!< [10..10] clk_sys_vreg_and_chip_reset */ - __IOM uint32_t clk_sys_pads : 1; /*!< [11..11] clk_sys_pads */ - __IOM uint32_t clk_sys_pio0 : 1; /*!< [12..12] clk_sys_pio0 */ - __IOM uint32_t clk_sys_pio1 : 1; /*!< [13..13] clk_sys_pio1 */ - __IOM uint32_t clk_sys_pll_sys : 1; /*!< [14..14] clk_sys_pll_sys */ - __IOM uint32_t clk_sys_pll_usb : 1; /*!< [15..15] clk_sys_pll_usb */ - __IOM uint32_t clk_sys_psm : 1; /*!< [16..16] clk_sys_psm */ - __IOM uint32_t clk_sys_pwm : 1; /*!< [17..17] clk_sys_pwm */ - __IOM uint32_t clk_sys_resets : 1; /*!< [18..18] clk_sys_resets */ - __IOM uint32_t clk_sys_rom : 1; /*!< [19..19] clk_sys_rom */ - __IOM uint32_t clk_sys_rosc : 1; /*!< [20..20] clk_sys_rosc */ - __IOM uint32_t clk_rtc_rtc : 1; /*!< [21..21] clk_rtc_rtc */ - __IOM uint32_t clk_sys_rtc : 1; /*!< [22..22] clk_sys_rtc */ - __IOM uint32_t clk_sys_sio : 1; /*!< [23..23] clk_sys_sio */ - __IOM uint32_t clk_peri_spi0 : 1; /*!< [24..24] clk_peri_spi0 */ - __IOM uint32_t clk_sys_spi0 : 1; /*!< [25..25] clk_sys_spi0 */ - __IOM uint32_t clk_peri_spi1 : 1; /*!< [26..26] clk_peri_spi1 */ - __IOM uint32_t clk_sys_spi1 : 1; /*!< [27..27] clk_sys_spi1 */ - __IOM uint32_t clk_sys_sram0 : 1; /*!< [28..28] clk_sys_sram0 */ - __IOM uint32_t clk_sys_sram1 : 1; /*!< [29..29] clk_sys_sram1 */ - __IOM uint32_t clk_sys_sram2 : 1; /*!< [30..30] clk_sys_sram2 */ - __IOM uint32_t clk_sys_sram3 : 1; /*!< [31..31] clk_sys_sram3 */ - } bit; - } WAKE_EN0; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000A4) enable clock in wake mode */ - - struct { - __IOM uint32_t clk_sys_sram4 : 1; /*!< [0..0] clk_sys_sram4 */ - __IOM uint32_t clk_sys_sram5 : 1; /*!< [1..1] clk_sys_sram5 */ - __IOM uint32_t clk_sys_syscfg : 1; /*!< [2..2] clk_sys_syscfg */ - __IOM uint32_t clk_sys_sysinfo : 1; /*!< [3..3] clk_sys_sysinfo */ - __IOM uint32_t clk_sys_tbman : 1; /*!< [4..4] clk_sys_tbman */ - __IOM uint32_t clk_sys_timer : 1; /*!< [5..5] clk_sys_timer */ - __IOM uint32_t clk_peri_uart0 : 1; /*!< [6..6] clk_peri_uart0 */ - __IOM uint32_t clk_sys_uart0 : 1; /*!< [7..7] clk_sys_uart0 */ - __IOM uint32_t clk_peri_uart1 : 1; /*!< [8..8] clk_peri_uart1 */ - __IOM uint32_t clk_sys_uart1 : 1; /*!< [9..9] clk_sys_uart1 */ - __IOM uint32_t clk_sys_usbctrl : 1; /*!< [10..10] clk_sys_usbctrl */ - __IOM uint32_t clk_usb_usbctrl : 1; /*!< [11..11] clk_usb_usbctrl */ - __IOM uint32_t clk_sys_watchdog : 1; /*!< [12..12] clk_sys_watchdog */ - __IOM uint32_t clk_sys_xip : 1; /*!< [13..13] clk_sys_xip */ - __IOM uint32_t clk_sys_xosc : 1; /*!< [14..14] clk_sys_xosc */ - uint32_t : 17; - } bit; - } WAKE_EN1; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000A8) enable clock in sleep mode */ - - struct { - __IOM uint32_t clk_sys_clocks : 1; /*!< [0..0] clk_sys_clocks */ - __IOM uint32_t clk_adc_adc : 1; /*!< [1..1] clk_adc_adc */ - __IOM uint32_t clk_sys_adc : 1; /*!< [2..2] clk_sys_adc */ - __IOM uint32_t clk_sys_busctrl : 1; /*!< [3..3] clk_sys_busctrl */ - __IOM uint32_t clk_sys_busfabric : 1; /*!< [4..4] clk_sys_busfabric */ - __IOM uint32_t clk_sys_dma : 1; /*!< [5..5] clk_sys_dma */ - __IOM uint32_t clk_sys_i2c0 : 1; /*!< [6..6] clk_sys_i2c0 */ - __IOM uint32_t clk_sys_i2c1 : 1; /*!< [7..7] clk_sys_i2c1 */ - __IOM uint32_t clk_sys_io : 1; /*!< [8..8] clk_sys_io */ - __IOM uint32_t clk_sys_jtag : 1; /*!< [9..9] clk_sys_jtag */ - __IOM uint32_t clk_sys_vreg_and_chip_reset : 1;/*!< [10..10] clk_sys_vreg_and_chip_reset */ - __IOM uint32_t clk_sys_pads : 1; /*!< [11..11] clk_sys_pads */ - __IOM uint32_t clk_sys_pio0 : 1; /*!< [12..12] clk_sys_pio0 */ - __IOM uint32_t clk_sys_pio1 : 1; /*!< [13..13] clk_sys_pio1 */ - __IOM uint32_t clk_sys_pll_sys : 1; /*!< [14..14] clk_sys_pll_sys */ - __IOM uint32_t clk_sys_pll_usb : 1; /*!< [15..15] clk_sys_pll_usb */ - __IOM uint32_t clk_sys_psm : 1; /*!< [16..16] clk_sys_psm */ - __IOM uint32_t clk_sys_pwm : 1; /*!< [17..17] clk_sys_pwm */ - __IOM uint32_t clk_sys_resets : 1; /*!< [18..18] clk_sys_resets */ - __IOM uint32_t clk_sys_rom : 1; /*!< [19..19] clk_sys_rom */ - __IOM uint32_t clk_sys_rosc : 1; /*!< [20..20] clk_sys_rosc */ - __IOM uint32_t clk_rtc_rtc : 1; /*!< [21..21] clk_rtc_rtc */ - __IOM uint32_t clk_sys_rtc : 1; /*!< [22..22] clk_sys_rtc */ - __IOM uint32_t clk_sys_sio : 1; /*!< [23..23] clk_sys_sio */ - __IOM uint32_t clk_peri_spi0 : 1; /*!< [24..24] clk_peri_spi0 */ - __IOM uint32_t clk_sys_spi0 : 1; /*!< [25..25] clk_sys_spi0 */ - __IOM uint32_t clk_peri_spi1 : 1; /*!< [26..26] clk_peri_spi1 */ - __IOM uint32_t clk_sys_spi1 : 1; /*!< [27..27] clk_sys_spi1 */ - __IOM uint32_t clk_sys_sram0 : 1; /*!< [28..28] clk_sys_sram0 */ - __IOM uint32_t clk_sys_sram1 : 1; /*!< [29..29] clk_sys_sram1 */ - __IOM uint32_t clk_sys_sram2 : 1; /*!< [30..30] clk_sys_sram2 */ - __IOM uint32_t clk_sys_sram3 : 1; /*!< [31..31] clk_sys_sram3 */ - } bit; - } SLEEP_EN0; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000AC) enable clock in sleep mode */ - - struct { - __IOM uint32_t clk_sys_sram4 : 1; /*!< [0..0] clk_sys_sram4 */ - __IOM uint32_t clk_sys_sram5 : 1; /*!< [1..1] clk_sys_sram5 */ - __IOM uint32_t clk_sys_syscfg : 1; /*!< [2..2] clk_sys_syscfg */ - __IOM uint32_t clk_sys_sysinfo : 1; /*!< [3..3] clk_sys_sysinfo */ - __IOM uint32_t clk_sys_tbman : 1; /*!< [4..4] clk_sys_tbman */ - __IOM uint32_t clk_sys_timer : 1; /*!< [5..5] clk_sys_timer */ - __IOM uint32_t clk_peri_uart0 : 1; /*!< [6..6] clk_peri_uart0 */ - __IOM uint32_t clk_sys_uart0 : 1; /*!< [7..7] clk_sys_uart0 */ - __IOM uint32_t clk_peri_uart1 : 1; /*!< [8..8] clk_peri_uart1 */ - __IOM uint32_t clk_sys_uart1 : 1; /*!< [9..9] clk_sys_uart1 */ - __IOM uint32_t clk_sys_usbctrl : 1; /*!< [10..10] clk_sys_usbctrl */ - __IOM uint32_t clk_usb_usbctrl : 1; /*!< [11..11] clk_usb_usbctrl */ - __IOM uint32_t clk_sys_watchdog : 1; /*!< [12..12] clk_sys_watchdog */ - __IOM uint32_t clk_sys_xip : 1; /*!< [13..13] clk_sys_xip */ - __IOM uint32_t clk_sys_xosc : 1; /*!< [14..14] clk_sys_xosc */ - uint32_t : 17; - } bit; - } SLEEP_EN1; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000B0) indicates the state of the clock enable */ - - struct { - __IM uint32_t clk_sys_clocks : 1; /*!< [0..0] clk_sys_clocks */ - __IM uint32_t clk_adc_adc : 1; /*!< [1..1] clk_adc_adc */ - __IM uint32_t clk_sys_adc : 1; /*!< [2..2] clk_sys_adc */ - __IM uint32_t clk_sys_busctrl : 1; /*!< [3..3] clk_sys_busctrl */ - __IM uint32_t clk_sys_busfabric : 1; /*!< [4..4] clk_sys_busfabric */ - __IM uint32_t clk_sys_dma : 1; /*!< [5..5] clk_sys_dma */ - __IM uint32_t clk_sys_i2c0 : 1; /*!< [6..6] clk_sys_i2c0 */ - __IM uint32_t clk_sys_i2c1 : 1; /*!< [7..7] clk_sys_i2c1 */ - __IM uint32_t clk_sys_io : 1; /*!< [8..8] clk_sys_io */ - __IM uint32_t clk_sys_jtag : 1; /*!< [9..9] clk_sys_jtag */ - __IM uint32_t clk_sys_vreg_and_chip_reset : 1;/*!< [10..10] clk_sys_vreg_and_chip_reset */ - __IM uint32_t clk_sys_pads : 1; /*!< [11..11] clk_sys_pads */ - __IM uint32_t clk_sys_pio0 : 1; /*!< [12..12] clk_sys_pio0 */ - __IM uint32_t clk_sys_pio1 : 1; /*!< [13..13] clk_sys_pio1 */ - __IM uint32_t clk_sys_pll_sys : 1; /*!< [14..14] clk_sys_pll_sys */ - __IM uint32_t clk_sys_pll_usb : 1; /*!< [15..15] clk_sys_pll_usb */ - __IM uint32_t clk_sys_psm : 1; /*!< [16..16] clk_sys_psm */ - __IM uint32_t clk_sys_pwm : 1; /*!< [17..17] clk_sys_pwm */ - __IM uint32_t clk_sys_resets : 1; /*!< [18..18] clk_sys_resets */ - __IM uint32_t clk_sys_rom : 1; /*!< [19..19] clk_sys_rom */ - __IM uint32_t clk_sys_rosc : 1; /*!< [20..20] clk_sys_rosc */ - __IM uint32_t clk_rtc_rtc : 1; /*!< [21..21] clk_rtc_rtc */ - __IM uint32_t clk_sys_rtc : 1; /*!< [22..22] clk_sys_rtc */ - __IM uint32_t clk_sys_sio : 1; /*!< [23..23] clk_sys_sio */ - __IM uint32_t clk_peri_spi0 : 1; /*!< [24..24] clk_peri_spi0 */ - __IM uint32_t clk_sys_spi0 : 1; /*!< [25..25] clk_sys_spi0 */ - __IM uint32_t clk_peri_spi1 : 1; /*!< [26..26] clk_peri_spi1 */ - __IM uint32_t clk_sys_spi1 : 1; /*!< [27..27] clk_sys_spi1 */ - __IM uint32_t clk_sys_sram0 : 1; /*!< [28..28] clk_sys_sram0 */ - __IM uint32_t clk_sys_sram1 : 1; /*!< [29..29] clk_sys_sram1 */ - __IM uint32_t clk_sys_sram2 : 1; /*!< [30..30] clk_sys_sram2 */ - __IM uint32_t clk_sys_sram3 : 1; /*!< [31..31] clk_sys_sram3 */ - } bit; - } ENABLED0; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000B4) indicates the state of the clock enable */ - - struct { - __IM uint32_t clk_sys_sram4 : 1; /*!< [0..0] clk_sys_sram4 */ - __IM uint32_t clk_sys_sram5 : 1; /*!< [1..1] clk_sys_sram5 */ - __IM uint32_t clk_sys_syscfg : 1; /*!< [2..2] clk_sys_syscfg */ - __IM uint32_t clk_sys_sysinfo : 1; /*!< [3..3] clk_sys_sysinfo */ - __IM uint32_t clk_sys_tbman : 1; /*!< [4..4] clk_sys_tbman */ - __IM uint32_t clk_sys_timer : 1; /*!< [5..5] clk_sys_timer */ - __IM uint32_t clk_peri_uart0 : 1; /*!< [6..6] clk_peri_uart0 */ - __IM uint32_t clk_sys_uart0 : 1; /*!< [7..7] clk_sys_uart0 */ - __IM uint32_t clk_peri_uart1 : 1; /*!< [8..8] clk_peri_uart1 */ - __IM uint32_t clk_sys_uart1 : 1; /*!< [9..9] clk_sys_uart1 */ - __IM uint32_t clk_sys_usbctrl : 1; /*!< [10..10] clk_sys_usbctrl */ - __IM uint32_t clk_usb_usbctrl : 1; /*!< [11..11] clk_usb_usbctrl */ - __IM uint32_t clk_sys_watchdog : 1; /*!< [12..12] clk_sys_watchdog */ - __IM uint32_t clk_sys_xip : 1; /*!< [13..13] clk_sys_xip */ - __IM uint32_t clk_sys_xosc : 1; /*!< [14..14] clk_sys_xosc */ - uint32_t : 17; - } bit; - } ENABLED1; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000B8) Raw Interrupts */ - - struct { - __IM uint32_t CLK_SYS_RESUS : 1; /*!< [0..0] CLK_SYS_RESUS */ - uint32_t : 31; - } bit; - } INTR; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000BC) Interrupt Enable */ - - struct { - __IOM uint32_t CLK_SYS_RESUS : 1; /*!< [0..0] CLK_SYS_RESUS */ - uint32_t : 31; - } bit; - } INTE; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000C0) Interrupt Force */ - - struct { - __IOM uint32_t CLK_SYS_RESUS : 1; /*!< [0..0] CLK_SYS_RESUS */ - uint32_t : 31; - } bit; - } INTF; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000C4) Interrupt status after masking & forcing */ - - struct { - __IM uint32_t CLK_SYS_RESUS : 1; /*!< [0..0] CLK_SYS_RESUS */ - uint32_t : 31; - } bit; - } INTS; + __IOM uint32_t WAKE_EN0; /*!< (@ 0x000000A0) enable clock in wake mode */ + __IOM uint32_t WAKE_EN1; /*!< (@ 0x000000A4) enable clock in wake mode */ + __IOM uint32_t SLEEP_EN0; /*!< (@ 0x000000A8) enable clock in sleep mode */ + __IOM uint32_t SLEEP_EN1; /*!< (@ 0x000000AC) enable clock in sleep mode */ + __IOM uint32_t ENABLED0; /*!< (@ 0x000000B0) indicates the state of the clock enable */ + __IOM uint32_t ENABLED1; /*!< (@ 0x000000B4) indicates the state of the clock enable */ + __IOM uint32_t INTR; /*!< (@ 0x000000B8) Raw Interrupts */ + __IOM uint32_t INTE; /*!< (@ 0x000000BC) Interrupt Enable */ + __IOM uint32_t INTF; /*!< (@ 0x000000C0) Interrupt Force */ + __IOM uint32_t INTS; /*!< (@ 0x000000C4) Interrupt status after masking & forcing */ } CLOCKS_Type; /*!< Size = 200 (0xc8) */ @@ -1426,112 +440,16 @@ typedef struct { /*!< (@ 0x40008000) CLOCKS Struc */ typedef struct { /*!< (@ 0x4000C000) RESETS Structure */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Reset control. If a bit is set it means the peripheral + __IOM uint32_t RESET; /*!< (@ 0x00000000) Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted. */ - - struct { - __IOM uint32_t adc : 1; /*!< [0..0] adc */ - __IOM uint32_t busctrl : 1; /*!< [1..1] busctrl */ - __IOM uint32_t dma : 1; /*!< [2..2] dma */ - __IOM uint32_t i2c0 : 1; /*!< [3..3] i2c0 */ - __IOM uint32_t i2c1 : 1; /*!< [4..4] i2c1 */ - __IOM uint32_t io_bank0 : 1; /*!< [5..5] io_bank0 */ - __IOM uint32_t io_qspi : 1; /*!< [6..6] io_qspi */ - __IOM uint32_t jtag : 1; /*!< [7..7] jtag */ - __IOM uint32_t pads_bank0 : 1; /*!< [8..8] pads_bank0 */ - __IOM uint32_t pads_qspi : 1; /*!< [9..9] pads_qspi */ - __IOM uint32_t pio0 : 1; /*!< [10..10] pio0 */ - __IOM uint32_t pio1 : 1; /*!< [11..11] pio1 */ - __IOM uint32_t pll_sys : 1; /*!< [12..12] pll_sys */ - __IOM uint32_t pll_usb : 1; /*!< [13..13] pll_usb */ - __IOM uint32_t pwm : 1; /*!< [14..14] pwm */ - __IOM uint32_t rtc : 1; /*!< [15..15] rtc */ - __IOM uint32_t spi0 : 1; /*!< [16..16] spi0 */ - __IOM uint32_t spi1 : 1; /*!< [17..17] spi1 */ - __IOM uint32_t syscfg : 1; /*!< [18..18] syscfg */ - __IOM uint32_t sysinfo : 1; /*!< [19..19] sysinfo */ - __IOM uint32_t tbman : 1; /*!< [20..20] tbman */ - __IOM uint32_t timer : 1; /*!< [21..21] timer */ - __IOM uint32_t uart0 : 1; /*!< [22..22] uart0 */ - __IOM uint32_t uart1 : 1; /*!< [23..23] uart1 */ - __IOM uint32_t usbctrl : 1; /*!< [24..24] usbctrl */ - uint32_t : 7; - } bit; - } RESET; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Watchdog select. If a bit is set then the watchdog + __IOM uint32_t WDSEL; /*!< (@ 0x00000004) Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires. */ - - struct { - __IOM uint32_t adc : 1; /*!< [0..0] adc */ - __IOM uint32_t busctrl : 1; /*!< [1..1] busctrl */ - __IOM uint32_t dma : 1; /*!< [2..2] dma */ - __IOM uint32_t i2c0 : 1; /*!< [3..3] i2c0 */ - __IOM uint32_t i2c1 : 1; /*!< [4..4] i2c1 */ - __IOM uint32_t io_bank0 : 1; /*!< [5..5] io_bank0 */ - __IOM uint32_t io_qspi : 1; /*!< [6..6] io_qspi */ - __IOM uint32_t jtag : 1; /*!< [7..7] jtag */ - __IOM uint32_t pads_bank0 : 1; /*!< [8..8] pads_bank0 */ - __IOM uint32_t pads_qspi : 1; /*!< [9..9] pads_qspi */ - __IOM uint32_t pio0 : 1; /*!< [10..10] pio0 */ - __IOM uint32_t pio1 : 1; /*!< [11..11] pio1 */ - __IOM uint32_t pll_sys : 1; /*!< [12..12] pll_sys */ - __IOM uint32_t pll_usb : 1; /*!< [13..13] pll_usb */ - __IOM uint32_t pwm : 1; /*!< [14..14] pwm */ - __IOM uint32_t rtc : 1; /*!< [15..15] rtc */ - __IOM uint32_t spi0 : 1; /*!< [16..16] spi0 */ - __IOM uint32_t spi1 : 1; /*!< [17..17] spi1 */ - __IOM uint32_t syscfg : 1; /*!< [18..18] syscfg */ - __IOM uint32_t sysinfo : 1; /*!< [19..19] sysinfo */ - __IOM uint32_t tbman : 1; /*!< [20..20] tbman */ - __IOM uint32_t timer : 1; /*!< [21..21] timer */ - __IOM uint32_t uart0 : 1; /*!< [22..22] uart0 */ - __IOM uint32_t uart1 : 1; /*!< [23..23] uart1 */ - __IOM uint32_t usbctrl : 1; /*!< [24..24] usbctrl */ - uint32_t : 7; - } bit; - } WDSEL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000008) Reset done. If a bit is set then a reset done + __IOM uint32_t RESET_DONE; /*!< (@ 0x00000008) Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed. */ - - struct { - __IM uint32_t adc : 1; /*!< [0..0] adc */ - __IM uint32_t busctrl : 1; /*!< [1..1] busctrl */ - __IM uint32_t dma : 1; /*!< [2..2] dma */ - __IM uint32_t i2c0 : 1; /*!< [3..3] i2c0 */ - __IM uint32_t i2c1 : 1; /*!< [4..4] i2c1 */ - __IM uint32_t io_bank0 : 1; /*!< [5..5] io_bank0 */ - __IM uint32_t io_qspi : 1; /*!< [6..6] io_qspi */ - __IM uint32_t jtag : 1; /*!< [7..7] jtag */ - __IM uint32_t pads_bank0 : 1; /*!< [8..8] pads_bank0 */ - __IM uint32_t pads_qspi : 1; /*!< [9..9] pads_qspi */ - __IM uint32_t pio0 : 1; /*!< [10..10] pio0 */ - __IM uint32_t pio1 : 1; /*!< [11..11] pio1 */ - __IM uint32_t pll_sys : 1; /*!< [12..12] pll_sys */ - __IM uint32_t pll_usb : 1; /*!< [13..13] pll_usb */ - __IM uint32_t pwm : 1; /*!< [14..14] pwm */ - __IM uint32_t rtc : 1; /*!< [15..15] rtc */ - __IM uint32_t spi0 : 1; /*!< [16..16] spi0 */ - __IM uint32_t spi1 : 1; /*!< [17..17] spi1 */ - __IM uint32_t syscfg : 1; /*!< [18..18] syscfg */ - __IM uint32_t sysinfo : 1; /*!< [19..19] sysinfo */ - __IM uint32_t tbman : 1; /*!< [20..20] tbman */ - __IM uint32_t timer : 1; /*!< [21..21] timer */ - __IM uint32_t uart0 : 1; /*!< [22..22] uart0 */ - __IM uint32_t uart1 : 1; /*!< [23..23] uart1 */ - __IM uint32_t usbctrl : 1; /*!< [24..24] usbctrl */ - uint32_t : 7; - } bit; - } RESET_DONE; } RESETS_Type; /*!< Size = 12 (0xc) */ @@ -1546,108 +464,12 @@ typedef struct { /*!< (@ 0x4000C000) RESETS Struc */ typedef struct { /*!< (@ 0x40010000) PSM Structure */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Force block out of reset (i.e. power it on) */ - - struct { - __IOM uint32_t rosc : 1; /*!< [0..0] rosc */ - __IOM uint32_t xosc : 1; /*!< [1..1] xosc */ - __IOM uint32_t clocks : 1; /*!< [2..2] clocks */ - __IOM uint32_t resets : 1; /*!< [3..3] resets */ - __IOM uint32_t busfabric : 1; /*!< [4..4] busfabric */ - __IOM uint32_t rom : 1; /*!< [5..5] rom */ - __IOM uint32_t sram0 : 1; /*!< [6..6] sram0 */ - __IOM uint32_t sram1 : 1; /*!< [7..7] sram1 */ - __IOM uint32_t sram2 : 1; /*!< [8..8] sram2 */ - __IOM uint32_t sram3 : 1; /*!< [9..9] sram3 */ - __IOM uint32_t sram4 : 1; /*!< [10..10] sram4 */ - __IOM uint32_t sram5 : 1; /*!< [11..11] sram5 */ - __IOM uint32_t xip : 1; /*!< [12..12] xip */ - __IOM uint32_t vreg_and_chip_reset : 1; /*!< [13..13] vreg_and_chip_reset */ - __IOM uint32_t sio : 1; /*!< [14..14] sio */ - __IOM uint32_t proc0 : 1; /*!< [15..15] proc0 */ - __IOM uint32_t proc1 : 1; /*!< [16..16] proc1 */ - uint32_t : 15; - } bit; - } FRCE_ON; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Force into reset (i.e. power it off) */ - - struct { - __IOM uint32_t rosc : 1; /*!< [0..0] rosc */ - __IOM uint32_t xosc : 1; /*!< [1..1] xosc */ - __IOM uint32_t clocks : 1; /*!< [2..2] clocks */ - __IOM uint32_t resets : 1; /*!< [3..3] resets */ - __IOM uint32_t busfabric : 1; /*!< [4..4] busfabric */ - __IOM uint32_t rom : 1; /*!< [5..5] rom */ - __IOM uint32_t sram0 : 1; /*!< [6..6] sram0 */ - __IOM uint32_t sram1 : 1; /*!< [7..7] sram1 */ - __IOM uint32_t sram2 : 1; /*!< [8..8] sram2 */ - __IOM uint32_t sram3 : 1; /*!< [9..9] sram3 */ - __IOM uint32_t sram4 : 1; /*!< [10..10] sram4 */ - __IOM uint32_t sram5 : 1; /*!< [11..11] sram5 */ - __IOM uint32_t xip : 1; /*!< [12..12] xip */ - __IOM uint32_t vreg_and_chip_reset : 1; /*!< [13..13] vreg_and_chip_reset */ - __IOM uint32_t sio : 1; /*!< [14..14] sio */ - __IOM uint32_t proc0 : 1; /*!< [15..15] proc0 */ - __IOM uint32_t proc1 : 1; /*!< [16..16] proc1 */ - uint32_t : 15; - } bit; - } FRCE_OFF; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000008) Set to 1 if this peripheral should be reset when + __IOM uint32_t FRCE_ON; /*!< (@ 0x00000000) Force block out of reset (i.e. power it on) */ + __IOM uint32_t FRCE_OFF; /*!< (@ 0x00000004) Force into reset (i.e. power it off) */ + __IOM uint32_t WDSEL; /*!< (@ 0x00000008) Set to 1 if this peripheral should be reset when the watchdog fires. */ - - struct { - __IOM uint32_t rosc : 1; /*!< [0..0] rosc */ - __IOM uint32_t xosc : 1; /*!< [1..1] xosc */ - __IOM uint32_t clocks : 1; /*!< [2..2] clocks */ - __IOM uint32_t resets : 1; /*!< [3..3] resets */ - __IOM uint32_t busfabric : 1; /*!< [4..4] busfabric */ - __IOM uint32_t rom : 1; /*!< [5..5] rom */ - __IOM uint32_t sram0 : 1; /*!< [6..6] sram0 */ - __IOM uint32_t sram1 : 1; /*!< [7..7] sram1 */ - __IOM uint32_t sram2 : 1; /*!< [8..8] sram2 */ - __IOM uint32_t sram3 : 1; /*!< [9..9] sram3 */ - __IOM uint32_t sram4 : 1; /*!< [10..10] sram4 */ - __IOM uint32_t sram5 : 1; /*!< [11..11] sram5 */ - __IOM uint32_t xip : 1; /*!< [12..12] xip */ - __IOM uint32_t vreg_and_chip_reset : 1; /*!< [13..13] vreg_and_chip_reset */ - __IOM uint32_t sio : 1; /*!< [14..14] sio */ - __IOM uint32_t proc0 : 1; /*!< [15..15] proc0 */ - __IOM uint32_t proc1 : 1; /*!< [16..16] proc1 */ - uint32_t : 15; - } bit; - } WDSEL; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) Indicates the peripheral's registers are ready + __IOM uint32_t DONE; /*!< (@ 0x0000000C) Indicates the peripheral's registers are ready to access. */ - - struct { - __IM uint32_t rosc : 1; /*!< [0..0] rosc */ - __IM uint32_t xosc : 1; /*!< [1..1] xosc */ - __IM uint32_t clocks : 1; /*!< [2..2] clocks */ - __IM uint32_t resets : 1; /*!< [3..3] resets */ - __IM uint32_t busfabric : 1; /*!< [4..4] busfabric */ - __IM uint32_t rom : 1; /*!< [5..5] rom */ - __IM uint32_t sram0 : 1; /*!< [6..6] sram0 */ - __IM uint32_t sram1 : 1; /*!< [7..7] sram1 */ - __IM uint32_t sram2 : 1; /*!< [8..8] sram2 */ - __IM uint32_t sram3 : 1; /*!< [9..9] sram3 */ - __IM uint32_t sram4 : 1; /*!< [10..10] sram4 */ - __IM uint32_t sram5 : 1; /*!< [11..11] sram5 */ - __IM uint32_t xip : 1; /*!< [12..12] xip */ - __IM uint32_t vreg_and_chip_reset : 1; /*!< [13..13] vreg_and_chip_reset */ - __IM uint32_t sio : 1; /*!< [14..14] sio */ - __IM uint32_t proc0 : 1; /*!< [15..15] proc0 */ - __IM uint32_t proc1 : 1; /*!< [16..16] proc1 */ - uint32_t : 15; - } bit; - } DONE; } PSM_Type; /*!< Size = 16 (0x10) */ @@ -1662,2768 +484,118 @@ typedef struct { /*!< (@ 0x40010000) PSM Structur */ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Structure */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000000) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO0_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000004) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO0_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000008) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO1_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO1_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000010) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO2_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000014) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO2_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000018) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO3_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO3_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000020) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO4_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000024) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO4_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000028) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO5_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000002C) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO5_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000030) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO6_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000034) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO6_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000038) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO7_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000003C) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO7_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000040) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO8_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000044) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO8_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000048) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO9_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000004C) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO9_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000050) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO10_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000054) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO10_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000058) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO11_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000005C) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO11_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000060) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO12_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000064) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO12_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000068) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO13_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000006C) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO13_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000070) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO14_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000074) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO14_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000078) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO15_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000007C) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO15_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000080) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO16_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000084) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO16_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000088) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO17_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000008C) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO17_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000090) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO18_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000094) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO18_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000098) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO19_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000009C) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO19_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000A0) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO20_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000A4) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO20_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000A8) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO21_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000AC) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO21_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000B0) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO22_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000B4) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO22_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000B8) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO23_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000BC) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO23_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000C0) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO24_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000C4) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO24_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000C8) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO25_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000CC) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO25_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000D0) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO26_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000D4) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO26_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000D8) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO27_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000DC) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO27_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000E0) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO28_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000E4) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO28_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000E8) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO29_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000EC) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO29_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000F0) Raw Interrupts */ - - struct { - __IM uint32_t GPIO0_LEVEL_LOW : 1; /*!< [0..0] GPIO0_LEVEL_LOW */ - __IM uint32_t GPIO0_LEVEL_HIGH : 1; /*!< [1..1] GPIO0_LEVEL_HIGH */ - __IOM uint32_t GPIO0_EDGE_LOW : 1; /*!< [2..2] GPIO0_EDGE_LOW */ - __IOM uint32_t GPIO0_EDGE_HIGH : 1; /*!< [3..3] GPIO0_EDGE_HIGH */ - __IM uint32_t GPIO1_LEVEL_LOW : 1; /*!< [4..4] GPIO1_LEVEL_LOW */ - __IM uint32_t GPIO1_LEVEL_HIGH : 1; /*!< [5..5] GPIO1_LEVEL_HIGH */ - __IOM uint32_t GPIO1_EDGE_LOW : 1; /*!< [6..6] GPIO1_EDGE_LOW */ - __IOM uint32_t GPIO1_EDGE_HIGH : 1; /*!< [7..7] GPIO1_EDGE_HIGH */ - __IM uint32_t GPIO2_LEVEL_LOW : 1; /*!< [8..8] GPIO2_LEVEL_LOW */ - __IM uint32_t GPIO2_LEVEL_HIGH : 1; /*!< [9..9] GPIO2_LEVEL_HIGH */ - __IOM uint32_t GPIO2_EDGE_LOW : 1; /*!< [10..10] GPIO2_EDGE_LOW */ - __IOM uint32_t GPIO2_EDGE_HIGH : 1; /*!< [11..11] GPIO2_EDGE_HIGH */ - __IM uint32_t GPIO3_LEVEL_LOW : 1; /*!< [12..12] GPIO3_LEVEL_LOW */ - __IM uint32_t GPIO3_LEVEL_HIGH : 1; /*!< [13..13] GPIO3_LEVEL_HIGH */ - __IOM uint32_t GPIO3_EDGE_LOW : 1; /*!< [14..14] GPIO3_EDGE_LOW */ - __IOM uint32_t GPIO3_EDGE_HIGH : 1; /*!< [15..15] GPIO3_EDGE_HIGH */ - __IM uint32_t GPIO4_LEVEL_LOW : 1; /*!< [16..16] GPIO4_LEVEL_LOW */ - __IM uint32_t GPIO4_LEVEL_HIGH : 1; /*!< [17..17] GPIO4_LEVEL_HIGH */ - __IOM uint32_t GPIO4_EDGE_LOW : 1; /*!< [18..18] GPIO4_EDGE_LOW */ - __IOM uint32_t GPIO4_EDGE_HIGH : 1; /*!< [19..19] GPIO4_EDGE_HIGH */ - __IM uint32_t GPIO5_LEVEL_LOW : 1; /*!< [20..20] GPIO5_LEVEL_LOW */ - __IM uint32_t GPIO5_LEVEL_HIGH : 1; /*!< [21..21] GPIO5_LEVEL_HIGH */ - __IOM uint32_t GPIO5_EDGE_LOW : 1; /*!< [22..22] GPIO5_EDGE_LOW */ - __IOM uint32_t GPIO5_EDGE_HIGH : 1; /*!< [23..23] GPIO5_EDGE_HIGH */ - __IM uint32_t GPIO6_LEVEL_LOW : 1; /*!< [24..24] GPIO6_LEVEL_LOW */ - __IM uint32_t GPIO6_LEVEL_HIGH : 1; /*!< [25..25] GPIO6_LEVEL_HIGH */ - __IOM uint32_t GPIO6_EDGE_LOW : 1; /*!< [26..26] GPIO6_EDGE_LOW */ - __IOM uint32_t GPIO6_EDGE_HIGH : 1; /*!< [27..27] GPIO6_EDGE_HIGH */ - __IM uint32_t GPIO7_LEVEL_LOW : 1; /*!< [28..28] GPIO7_LEVEL_LOW */ - __IM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< [29..29] GPIO7_LEVEL_HIGH */ - __IOM uint32_t GPIO7_EDGE_LOW : 1; /*!< [30..30] GPIO7_EDGE_LOW */ - __IOM uint32_t GPIO7_EDGE_HIGH : 1; /*!< [31..31] GPIO7_EDGE_HIGH */ - } bit; - } INTR0; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000F4) Raw Interrupts */ - - struct { - __IM uint32_t GPIO8_LEVEL_LOW : 1; /*!< [0..0] GPIO8_LEVEL_LOW */ - __IM uint32_t GPIO8_LEVEL_HIGH : 1; /*!< [1..1] GPIO8_LEVEL_HIGH */ - __IOM uint32_t GPIO8_EDGE_LOW : 1; /*!< [2..2] GPIO8_EDGE_LOW */ - __IOM uint32_t GPIO8_EDGE_HIGH : 1; /*!< [3..3] GPIO8_EDGE_HIGH */ - __IM uint32_t GPIO9_LEVEL_LOW : 1; /*!< [4..4] GPIO9_LEVEL_LOW */ - __IM uint32_t GPIO9_LEVEL_HIGH : 1; /*!< [5..5] GPIO9_LEVEL_HIGH */ - __IOM uint32_t GPIO9_EDGE_LOW : 1; /*!< [6..6] GPIO9_EDGE_LOW */ - __IOM uint32_t GPIO9_EDGE_HIGH : 1; /*!< [7..7] GPIO9_EDGE_HIGH */ - __IM uint32_t GPIO10_LEVEL_LOW : 1; /*!< [8..8] GPIO10_LEVEL_LOW */ - __IM uint32_t GPIO10_LEVEL_HIGH : 1; /*!< [9..9] GPIO10_LEVEL_HIGH */ - __IOM uint32_t GPIO10_EDGE_LOW : 1; /*!< [10..10] GPIO10_EDGE_LOW */ - __IOM uint32_t GPIO10_EDGE_HIGH : 1; /*!< [11..11] GPIO10_EDGE_HIGH */ - __IM uint32_t GPIO11_LEVEL_LOW : 1; /*!< [12..12] GPIO11_LEVEL_LOW */ - __IM uint32_t GPIO11_LEVEL_HIGH : 1; /*!< [13..13] GPIO11_LEVEL_HIGH */ - __IOM uint32_t GPIO11_EDGE_LOW : 1; /*!< [14..14] GPIO11_EDGE_LOW */ - __IOM uint32_t GPIO11_EDGE_HIGH : 1; /*!< [15..15] GPIO11_EDGE_HIGH */ - __IM uint32_t GPIO12_LEVEL_LOW : 1; /*!< [16..16] GPIO12_LEVEL_LOW */ - __IM uint32_t GPIO12_LEVEL_HIGH : 1; /*!< [17..17] GPIO12_LEVEL_HIGH */ - __IOM uint32_t GPIO12_EDGE_LOW : 1; /*!< [18..18] GPIO12_EDGE_LOW */ - __IOM uint32_t GPIO12_EDGE_HIGH : 1; /*!< [19..19] GPIO12_EDGE_HIGH */ - __IM uint32_t GPIO13_LEVEL_LOW : 1; /*!< [20..20] GPIO13_LEVEL_LOW */ - __IM uint32_t GPIO13_LEVEL_HIGH : 1; /*!< [21..21] GPIO13_LEVEL_HIGH */ - __IOM uint32_t GPIO13_EDGE_LOW : 1; /*!< [22..22] GPIO13_EDGE_LOW */ - __IOM uint32_t GPIO13_EDGE_HIGH : 1; /*!< [23..23] GPIO13_EDGE_HIGH */ - __IM uint32_t GPIO14_LEVEL_LOW : 1; /*!< [24..24] GPIO14_LEVEL_LOW */ - __IM uint32_t GPIO14_LEVEL_HIGH : 1; /*!< [25..25] GPIO14_LEVEL_HIGH */ - __IOM uint32_t GPIO14_EDGE_LOW : 1; /*!< [26..26] GPIO14_EDGE_LOW */ - __IOM uint32_t GPIO14_EDGE_HIGH : 1; /*!< [27..27] GPIO14_EDGE_HIGH */ - __IM uint32_t GPIO15_LEVEL_LOW : 1; /*!< [28..28] GPIO15_LEVEL_LOW */ - __IM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< [29..29] GPIO15_LEVEL_HIGH */ - __IOM uint32_t GPIO15_EDGE_LOW : 1; /*!< [30..30] GPIO15_EDGE_LOW */ - __IOM uint32_t GPIO15_EDGE_HIGH : 1; /*!< [31..31] GPIO15_EDGE_HIGH */ - } bit; - } INTR1; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000F8) Raw Interrupts */ - - struct { - __IM uint32_t GPIO16_LEVEL_LOW : 1; /*!< [0..0] GPIO16_LEVEL_LOW */ - __IM uint32_t GPIO16_LEVEL_HIGH : 1; /*!< [1..1] GPIO16_LEVEL_HIGH */ - __IOM uint32_t GPIO16_EDGE_LOW : 1; /*!< [2..2] GPIO16_EDGE_LOW */ - __IOM uint32_t GPIO16_EDGE_HIGH : 1; /*!< [3..3] GPIO16_EDGE_HIGH */ - __IM uint32_t GPIO17_LEVEL_LOW : 1; /*!< [4..4] GPIO17_LEVEL_LOW */ - __IM uint32_t GPIO17_LEVEL_HIGH : 1; /*!< [5..5] GPIO17_LEVEL_HIGH */ - __IOM uint32_t GPIO17_EDGE_LOW : 1; /*!< [6..6] GPIO17_EDGE_LOW */ - __IOM uint32_t GPIO17_EDGE_HIGH : 1; /*!< [7..7] GPIO17_EDGE_HIGH */ - __IM uint32_t GPIO18_LEVEL_LOW : 1; /*!< [8..8] GPIO18_LEVEL_LOW */ - __IM uint32_t GPIO18_LEVEL_HIGH : 1; /*!< [9..9] GPIO18_LEVEL_HIGH */ - __IOM uint32_t GPIO18_EDGE_LOW : 1; /*!< [10..10] GPIO18_EDGE_LOW */ - __IOM uint32_t GPIO18_EDGE_HIGH : 1; /*!< [11..11] GPIO18_EDGE_HIGH */ - __IM uint32_t GPIO19_LEVEL_LOW : 1; /*!< [12..12] GPIO19_LEVEL_LOW */ - __IM uint32_t GPIO19_LEVEL_HIGH : 1; /*!< [13..13] GPIO19_LEVEL_HIGH */ - __IOM uint32_t GPIO19_EDGE_LOW : 1; /*!< [14..14] GPIO19_EDGE_LOW */ - __IOM uint32_t GPIO19_EDGE_HIGH : 1; /*!< [15..15] GPIO19_EDGE_HIGH */ - __IM uint32_t GPIO20_LEVEL_LOW : 1; /*!< [16..16] GPIO20_LEVEL_LOW */ - __IM uint32_t GPIO20_LEVEL_HIGH : 1; /*!< [17..17] GPIO20_LEVEL_HIGH */ - __IOM uint32_t GPIO20_EDGE_LOW : 1; /*!< [18..18] GPIO20_EDGE_LOW */ - __IOM uint32_t GPIO20_EDGE_HIGH : 1; /*!< [19..19] GPIO20_EDGE_HIGH */ - __IM uint32_t GPIO21_LEVEL_LOW : 1; /*!< [20..20] GPIO21_LEVEL_LOW */ - __IM uint32_t GPIO21_LEVEL_HIGH : 1; /*!< [21..21] GPIO21_LEVEL_HIGH */ - __IOM uint32_t GPIO21_EDGE_LOW : 1; /*!< [22..22] GPIO21_EDGE_LOW */ - __IOM uint32_t GPIO21_EDGE_HIGH : 1; /*!< [23..23] GPIO21_EDGE_HIGH */ - __IM uint32_t GPIO22_LEVEL_LOW : 1; /*!< [24..24] GPIO22_LEVEL_LOW */ - __IM uint32_t GPIO22_LEVEL_HIGH : 1; /*!< [25..25] GPIO22_LEVEL_HIGH */ - __IOM uint32_t GPIO22_EDGE_LOW : 1; /*!< [26..26] GPIO22_EDGE_LOW */ - __IOM uint32_t GPIO22_EDGE_HIGH : 1; /*!< [27..27] GPIO22_EDGE_HIGH */ - __IM uint32_t GPIO23_LEVEL_LOW : 1; /*!< [28..28] GPIO23_LEVEL_LOW */ - __IM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< [29..29] GPIO23_LEVEL_HIGH */ - __IOM uint32_t GPIO23_EDGE_LOW : 1; /*!< [30..30] GPIO23_EDGE_LOW */ - __IOM uint32_t GPIO23_EDGE_HIGH : 1; /*!< [31..31] GPIO23_EDGE_HIGH */ - } bit; - } INTR2; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000FC) Raw Interrupts */ - - struct { - __IM uint32_t GPIO24_LEVEL_LOW : 1; /*!< [0..0] GPIO24_LEVEL_LOW */ - __IM uint32_t GPIO24_LEVEL_HIGH : 1; /*!< [1..1] GPIO24_LEVEL_HIGH */ - __IOM uint32_t GPIO24_EDGE_LOW : 1; /*!< [2..2] GPIO24_EDGE_LOW */ - __IOM uint32_t GPIO24_EDGE_HIGH : 1; /*!< [3..3] GPIO24_EDGE_HIGH */ - __IM uint32_t GPIO25_LEVEL_LOW : 1; /*!< [4..4] GPIO25_LEVEL_LOW */ - __IM uint32_t GPIO25_LEVEL_HIGH : 1; /*!< [5..5] GPIO25_LEVEL_HIGH */ - __IOM uint32_t GPIO25_EDGE_LOW : 1; /*!< [6..6] GPIO25_EDGE_LOW */ - __IOM uint32_t GPIO25_EDGE_HIGH : 1; /*!< [7..7] GPIO25_EDGE_HIGH */ - __IM uint32_t GPIO26_LEVEL_LOW : 1; /*!< [8..8] GPIO26_LEVEL_LOW */ - __IM uint32_t GPIO26_LEVEL_HIGH : 1; /*!< [9..9] GPIO26_LEVEL_HIGH */ - __IOM uint32_t GPIO26_EDGE_LOW : 1; /*!< [10..10] GPIO26_EDGE_LOW */ - __IOM uint32_t GPIO26_EDGE_HIGH : 1; /*!< [11..11] GPIO26_EDGE_HIGH */ - __IM uint32_t GPIO27_LEVEL_LOW : 1; /*!< [12..12] GPIO27_LEVEL_LOW */ - __IM uint32_t GPIO27_LEVEL_HIGH : 1; /*!< [13..13] GPIO27_LEVEL_HIGH */ - __IOM uint32_t GPIO27_EDGE_LOW : 1; /*!< [14..14] GPIO27_EDGE_LOW */ - __IOM uint32_t GPIO27_EDGE_HIGH : 1; /*!< [15..15] GPIO27_EDGE_HIGH */ - __IM uint32_t GPIO28_LEVEL_LOW : 1; /*!< [16..16] GPIO28_LEVEL_LOW */ - __IM uint32_t GPIO28_LEVEL_HIGH : 1; /*!< [17..17] GPIO28_LEVEL_HIGH */ - __IOM uint32_t GPIO28_EDGE_LOW : 1; /*!< [18..18] GPIO28_EDGE_LOW */ - __IOM uint32_t GPIO28_EDGE_HIGH : 1; /*!< [19..19] GPIO28_EDGE_HIGH */ - __IM uint32_t GPIO29_LEVEL_LOW : 1; /*!< [20..20] GPIO29_LEVEL_LOW */ - __IM uint32_t GPIO29_LEVEL_HIGH : 1; /*!< [21..21] GPIO29_LEVEL_HIGH */ - __IOM uint32_t GPIO29_EDGE_LOW : 1; /*!< [22..22] GPIO29_EDGE_LOW */ - __IOM uint32_t GPIO29_EDGE_HIGH : 1; /*!< [23..23] GPIO29_EDGE_HIGH */ - uint32_t : 8; - } bit; - } INTR3; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000100) Interrupt Enable for proc0 */ - - struct { - __IOM uint32_t GPIO0_LEVEL_LOW : 1; /*!< [0..0] GPIO0_LEVEL_LOW */ - __IOM uint32_t GPIO0_LEVEL_HIGH : 1; /*!< [1..1] GPIO0_LEVEL_HIGH */ - __IOM uint32_t GPIO0_EDGE_LOW : 1; /*!< [2..2] GPIO0_EDGE_LOW */ - __IOM uint32_t GPIO0_EDGE_HIGH : 1; /*!< [3..3] GPIO0_EDGE_HIGH */ - __IOM uint32_t GPIO1_LEVEL_LOW : 1; /*!< [4..4] GPIO1_LEVEL_LOW */ - __IOM uint32_t GPIO1_LEVEL_HIGH : 1; /*!< [5..5] GPIO1_LEVEL_HIGH */ - __IOM uint32_t GPIO1_EDGE_LOW : 1; /*!< [6..6] GPIO1_EDGE_LOW */ - __IOM uint32_t GPIO1_EDGE_HIGH : 1; /*!< [7..7] GPIO1_EDGE_HIGH */ - __IOM uint32_t GPIO2_LEVEL_LOW : 1; /*!< [8..8] GPIO2_LEVEL_LOW */ - __IOM uint32_t GPIO2_LEVEL_HIGH : 1; /*!< [9..9] GPIO2_LEVEL_HIGH */ - __IOM uint32_t GPIO2_EDGE_LOW : 1; /*!< [10..10] GPIO2_EDGE_LOW */ - __IOM uint32_t GPIO2_EDGE_HIGH : 1; /*!< [11..11] GPIO2_EDGE_HIGH */ - __IOM uint32_t GPIO3_LEVEL_LOW : 1; /*!< [12..12] GPIO3_LEVEL_LOW */ - __IOM uint32_t GPIO3_LEVEL_HIGH : 1; /*!< [13..13] GPIO3_LEVEL_HIGH */ - __IOM uint32_t GPIO3_EDGE_LOW : 1; /*!< [14..14] GPIO3_EDGE_LOW */ - __IOM uint32_t GPIO3_EDGE_HIGH : 1; /*!< [15..15] GPIO3_EDGE_HIGH */ - __IOM uint32_t GPIO4_LEVEL_LOW : 1; /*!< [16..16] GPIO4_LEVEL_LOW */ - __IOM uint32_t GPIO4_LEVEL_HIGH : 1; /*!< [17..17] GPIO4_LEVEL_HIGH */ - __IOM uint32_t GPIO4_EDGE_LOW : 1; /*!< [18..18] GPIO4_EDGE_LOW */ - __IOM uint32_t GPIO4_EDGE_HIGH : 1; /*!< [19..19] GPIO4_EDGE_HIGH */ - __IOM uint32_t GPIO5_LEVEL_LOW : 1; /*!< [20..20] GPIO5_LEVEL_LOW */ - __IOM uint32_t GPIO5_LEVEL_HIGH : 1; /*!< [21..21] GPIO5_LEVEL_HIGH */ - __IOM uint32_t GPIO5_EDGE_LOW : 1; /*!< [22..22] GPIO5_EDGE_LOW */ - __IOM uint32_t GPIO5_EDGE_HIGH : 1; /*!< [23..23] GPIO5_EDGE_HIGH */ - __IOM uint32_t GPIO6_LEVEL_LOW : 1; /*!< [24..24] GPIO6_LEVEL_LOW */ - __IOM uint32_t GPIO6_LEVEL_HIGH : 1; /*!< [25..25] GPIO6_LEVEL_HIGH */ - __IOM uint32_t GPIO6_EDGE_LOW : 1; /*!< [26..26] GPIO6_EDGE_LOW */ - __IOM uint32_t GPIO6_EDGE_HIGH : 1; /*!< [27..27] GPIO6_EDGE_HIGH */ - __IOM uint32_t GPIO7_LEVEL_LOW : 1; /*!< [28..28] GPIO7_LEVEL_LOW */ - __IOM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< [29..29] GPIO7_LEVEL_HIGH */ - __IOM uint32_t GPIO7_EDGE_LOW : 1; /*!< [30..30] GPIO7_EDGE_LOW */ - __IOM uint32_t GPIO7_EDGE_HIGH : 1; /*!< [31..31] GPIO7_EDGE_HIGH */ - } bit; - } PROC0_INTE0; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000104) Interrupt Enable for proc0 */ - - struct { - __IOM uint32_t GPIO8_LEVEL_LOW : 1; /*!< [0..0] GPIO8_LEVEL_LOW */ - __IOM uint32_t GPIO8_LEVEL_HIGH : 1; /*!< [1..1] GPIO8_LEVEL_HIGH */ - __IOM uint32_t GPIO8_EDGE_LOW : 1; /*!< [2..2] GPIO8_EDGE_LOW */ - __IOM uint32_t GPIO8_EDGE_HIGH : 1; /*!< [3..3] GPIO8_EDGE_HIGH */ - __IOM uint32_t GPIO9_LEVEL_LOW : 1; /*!< [4..4] GPIO9_LEVEL_LOW */ - __IOM uint32_t GPIO9_LEVEL_HIGH : 1; /*!< [5..5] GPIO9_LEVEL_HIGH */ - __IOM uint32_t GPIO9_EDGE_LOW : 1; /*!< [6..6] GPIO9_EDGE_LOW */ - __IOM uint32_t GPIO9_EDGE_HIGH : 1; /*!< [7..7] GPIO9_EDGE_HIGH */ - __IOM uint32_t GPIO10_LEVEL_LOW : 1; /*!< [8..8] GPIO10_LEVEL_LOW */ - __IOM uint32_t GPIO10_LEVEL_HIGH : 1; /*!< [9..9] GPIO10_LEVEL_HIGH */ - __IOM uint32_t GPIO10_EDGE_LOW : 1; /*!< [10..10] GPIO10_EDGE_LOW */ - __IOM uint32_t GPIO10_EDGE_HIGH : 1; /*!< [11..11] GPIO10_EDGE_HIGH */ - __IOM uint32_t GPIO11_LEVEL_LOW : 1; /*!< [12..12] GPIO11_LEVEL_LOW */ - __IOM uint32_t GPIO11_LEVEL_HIGH : 1; /*!< [13..13] GPIO11_LEVEL_HIGH */ - __IOM uint32_t GPIO11_EDGE_LOW : 1; /*!< [14..14] GPIO11_EDGE_LOW */ - __IOM uint32_t GPIO11_EDGE_HIGH : 1; /*!< [15..15] GPIO11_EDGE_HIGH */ - __IOM uint32_t GPIO12_LEVEL_LOW : 1; /*!< [16..16] GPIO12_LEVEL_LOW */ - __IOM uint32_t GPIO12_LEVEL_HIGH : 1; /*!< [17..17] GPIO12_LEVEL_HIGH */ - __IOM uint32_t GPIO12_EDGE_LOW : 1; /*!< [18..18] GPIO12_EDGE_LOW */ - __IOM uint32_t GPIO12_EDGE_HIGH : 1; /*!< [19..19] GPIO12_EDGE_HIGH */ - __IOM uint32_t GPIO13_LEVEL_LOW : 1; /*!< [20..20] GPIO13_LEVEL_LOW */ - __IOM uint32_t GPIO13_LEVEL_HIGH : 1; /*!< [21..21] GPIO13_LEVEL_HIGH */ - __IOM uint32_t GPIO13_EDGE_LOW : 1; /*!< [22..22] GPIO13_EDGE_LOW */ - __IOM uint32_t GPIO13_EDGE_HIGH : 1; /*!< [23..23] GPIO13_EDGE_HIGH */ - __IOM uint32_t GPIO14_LEVEL_LOW : 1; /*!< [24..24] GPIO14_LEVEL_LOW */ - __IOM uint32_t GPIO14_LEVEL_HIGH : 1; /*!< [25..25] GPIO14_LEVEL_HIGH */ - __IOM uint32_t GPIO14_EDGE_LOW : 1; /*!< [26..26] GPIO14_EDGE_LOW */ - __IOM uint32_t GPIO14_EDGE_HIGH : 1; /*!< [27..27] GPIO14_EDGE_HIGH */ - __IOM uint32_t GPIO15_LEVEL_LOW : 1; /*!< [28..28] GPIO15_LEVEL_LOW */ - __IOM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< [29..29] GPIO15_LEVEL_HIGH */ - __IOM uint32_t GPIO15_EDGE_LOW : 1; /*!< [30..30] GPIO15_EDGE_LOW */ - __IOM uint32_t GPIO15_EDGE_HIGH : 1; /*!< [31..31] GPIO15_EDGE_HIGH */ - } bit; - } PROC0_INTE1; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000108) Interrupt Enable for proc0 */ - - struct { - __IOM uint32_t GPIO16_LEVEL_LOW : 1; /*!< [0..0] GPIO16_LEVEL_LOW */ - __IOM uint32_t GPIO16_LEVEL_HIGH : 1; /*!< [1..1] GPIO16_LEVEL_HIGH */ - __IOM uint32_t GPIO16_EDGE_LOW : 1; /*!< [2..2] GPIO16_EDGE_LOW */ - __IOM uint32_t GPIO16_EDGE_HIGH : 1; /*!< [3..3] GPIO16_EDGE_HIGH */ - __IOM uint32_t GPIO17_LEVEL_LOW : 1; /*!< [4..4] GPIO17_LEVEL_LOW */ - __IOM uint32_t GPIO17_LEVEL_HIGH : 1; /*!< [5..5] GPIO17_LEVEL_HIGH */ - __IOM uint32_t GPIO17_EDGE_LOW : 1; /*!< [6..6] GPIO17_EDGE_LOW */ - __IOM uint32_t GPIO17_EDGE_HIGH : 1; /*!< [7..7] GPIO17_EDGE_HIGH */ - __IOM uint32_t GPIO18_LEVEL_LOW : 1; /*!< [8..8] GPIO18_LEVEL_LOW */ - __IOM uint32_t GPIO18_LEVEL_HIGH : 1; /*!< [9..9] GPIO18_LEVEL_HIGH */ - __IOM uint32_t GPIO18_EDGE_LOW : 1; /*!< [10..10] GPIO18_EDGE_LOW */ - __IOM uint32_t GPIO18_EDGE_HIGH : 1; /*!< [11..11] GPIO18_EDGE_HIGH */ - __IOM uint32_t GPIO19_LEVEL_LOW : 1; /*!< [12..12] GPIO19_LEVEL_LOW */ - __IOM uint32_t GPIO19_LEVEL_HIGH : 1; /*!< [13..13] GPIO19_LEVEL_HIGH */ - __IOM uint32_t GPIO19_EDGE_LOW : 1; /*!< [14..14] GPIO19_EDGE_LOW */ - __IOM uint32_t GPIO19_EDGE_HIGH : 1; /*!< [15..15] GPIO19_EDGE_HIGH */ - __IOM uint32_t GPIO20_LEVEL_LOW : 1; /*!< [16..16] GPIO20_LEVEL_LOW */ - __IOM uint32_t GPIO20_LEVEL_HIGH : 1; /*!< [17..17] GPIO20_LEVEL_HIGH */ - __IOM uint32_t GPIO20_EDGE_LOW : 1; /*!< [18..18] GPIO20_EDGE_LOW */ - __IOM uint32_t GPIO20_EDGE_HIGH : 1; /*!< [19..19] GPIO20_EDGE_HIGH */ - __IOM uint32_t GPIO21_LEVEL_LOW : 1; /*!< [20..20] GPIO21_LEVEL_LOW */ - __IOM uint32_t GPIO21_LEVEL_HIGH : 1; /*!< [21..21] GPIO21_LEVEL_HIGH */ - __IOM uint32_t GPIO21_EDGE_LOW : 1; /*!< [22..22] GPIO21_EDGE_LOW */ - __IOM uint32_t GPIO21_EDGE_HIGH : 1; /*!< [23..23] GPIO21_EDGE_HIGH */ - __IOM uint32_t GPIO22_LEVEL_LOW : 1; /*!< [24..24] GPIO22_LEVEL_LOW */ - __IOM uint32_t GPIO22_LEVEL_HIGH : 1; /*!< [25..25] GPIO22_LEVEL_HIGH */ - __IOM uint32_t GPIO22_EDGE_LOW : 1; /*!< [26..26] GPIO22_EDGE_LOW */ - __IOM uint32_t GPIO22_EDGE_HIGH : 1; /*!< [27..27] GPIO22_EDGE_HIGH */ - __IOM uint32_t GPIO23_LEVEL_LOW : 1; /*!< [28..28] GPIO23_LEVEL_LOW */ - __IOM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< [29..29] GPIO23_LEVEL_HIGH */ - __IOM uint32_t GPIO23_EDGE_LOW : 1; /*!< [30..30] GPIO23_EDGE_LOW */ - __IOM uint32_t GPIO23_EDGE_HIGH : 1; /*!< [31..31] GPIO23_EDGE_HIGH */ - } bit; - } PROC0_INTE2; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000010C) Interrupt Enable for proc0 */ - - struct { - __IOM uint32_t GPIO24_LEVEL_LOW : 1; /*!< [0..0] GPIO24_LEVEL_LOW */ - __IOM uint32_t GPIO24_LEVEL_HIGH : 1; /*!< [1..1] GPIO24_LEVEL_HIGH */ - __IOM uint32_t GPIO24_EDGE_LOW : 1; /*!< [2..2] GPIO24_EDGE_LOW */ - __IOM uint32_t GPIO24_EDGE_HIGH : 1; /*!< [3..3] GPIO24_EDGE_HIGH */ - __IOM uint32_t GPIO25_LEVEL_LOW : 1; /*!< [4..4] GPIO25_LEVEL_LOW */ - __IOM uint32_t GPIO25_LEVEL_HIGH : 1; /*!< [5..5] GPIO25_LEVEL_HIGH */ - __IOM uint32_t GPIO25_EDGE_LOW : 1; /*!< [6..6] GPIO25_EDGE_LOW */ - __IOM uint32_t GPIO25_EDGE_HIGH : 1; /*!< [7..7] GPIO25_EDGE_HIGH */ - __IOM uint32_t GPIO26_LEVEL_LOW : 1; /*!< [8..8] GPIO26_LEVEL_LOW */ - __IOM uint32_t GPIO26_LEVEL_HIGH : 1; /*!< [9..9] GPIO26_LEVEL_HIGH */ - __IOM uint32_t GPIO26_EDGE_LOW : 1; /*!< [10..10] GPIO26_EDGE_LOW */ - __IOM uint32_t GPIO26_EDGE_HIGH : 1; /*!< [11..11] GPIO26_EDGE_HIGH */ - __IOM uint32_t GPIO27_LEVEL_LOW : 1; /*!< [12..12] GPIO27_LEVEL_LOW */ - __IOM uint32_t GPIO27_LEVEL_HIGH : 1; /*!< [13..13] GPIO27_LEVEL_HIGH */ - __IOM uint32_t GPIO27_EDGE_LOW : 1; /*!< [14..14] GPIO27_EDGE_LOW */ - __IOM uint32_t GPIO27_EDGE_HIGH : 1; /*!< [15..15] GPIO27_EDGE_HIGH */ - __IOM uint32_t GPIO28_LEVEL_LOW : 1; /*!< [16..16] GPIO28_LEVEL_LOW */ - __IOM uint32_t GPIO28_LEVEL_HIGH : 1; /*!< [17..17] GPIO28_LEVEL_HIGH */ - __IOM uint32_t GPIO28_EDGE_LOW : 1; /*!< [18..18] GPIO28_EDGE_LOW */ - __IOM uint32_t GPIO28_EDGE_HIGH : 1; /*!< [19..19] GPIO28_EDGE_HIGH */ - __IOM uint32_t GPIO29_LEVEL_LOW : 1; /*!< [20..20] GPIO29_LEVEL_LOW */ - __IOM uint32_t GPIO29_LEVEL_HIGH : 1; /*!< [21..21] GPIO29_LEVEL_HIGH */ - __IOM uint32_t GPIO29_EDGE_LOW : 1; /*!< [22..22] GPIO29_EDGE_LOW */ - __IOM uint32_t GPIO29_EDGE_HIGH : 1; /*!< [23..23] GPIO29_EDGE_HIGH */ - uint32_t : 8; - } bit; - } PROC0_INTE3; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000110) Interrupt Force for proc0 */ - - struct { - __IOM uint32_t GPIO0_LEVEL_LOW : 1; /*!< [0..0] GPIO0_LEVEL_LOW */ - __IOM uint32_t GPIO0_LEVEL_HIGH : 1; /*!< [1..1] GPIO0_LEVEL_HIGH */ - __IOM uint32_t GPIO0_EDGE_LOW : 1; /*!< [2..2] GPIO0_EDGE_LOW */ - __IOM uint32_t GPIO0_EDGE_HIGH : 1; /*!< [3..3] GPIO0_EDGE_HIGH */ - __IOM uint32_t GPIO1_LEVEL_LOW : 1; /*!< [4..4] GPIO1_LEVEL_LOW */ - __IOM uint32_t GPIO1_LEVEL_HIGH : 1; /*!< [5..5] GPIO1_LEVEL_HIGH */ - __IOM uint32_t GPIO1_EDGE_LOW : 1; /*!< [6..6] GPIO1_EDGE_LOW */ - __IOM uint32_t GPIO1_EDGE_HIGH : 1; /*!< [7..7] GPIO1_EDGE_HIGH */ - __IOM uint32_t GPIO2_LEVEL_LOW : 1; /*!< [8..8] GPIO2_LEVEL_LOW */ - __IOM uint32_t GPIO2_LEVEL_HIGH : 1; /*!< [9..9] GPIO2_LEVEL_HIGH */ - __IOM uint32_t GPIO2_EDGE_LOW : 1; /*!< [10..10] GPIO2_EDGE_LOW */ - __IOM uint32_t GPIO2_EDGE_HIGH : 1; /*!< [11..11] GPIO2_EDGE_HIGH */ - __IOM uint32_t GPIO3_LEVEL_LOW : 1; /*!< [12..12] GPIO3_LEVEL_LOW */ - __IOM uint32_t GPIO3_LEVEL_HIGH : 1; /*!< [13..13] GPIO3_LEVEL_HIGH */ - __IOM uint32_t GPIO3_EDGE_LOW : 1; /*!< [14..14] GPIO3_EDGE_LOW */ - __IOM uint32_t GPIO3_EDGE_HIGH : 1; /*!< [15..15] GPIO3_EDGE_HIGH */ - __IOM uint32_t GPIO4_LEVEL_LOW : 1; /*!< [16..16] GPIO4_LEVEL_LOW */ - __IOM uint32_t GPIO4_LEVEL_HIGH : 1; /*!< [17..17] GPIO4_LEVEL_HIGH */ - __IOM uint32_t GPIO4_EDGE_LOW : 1; /*!< [18..18] GPIO4_EDGE_LOW */ - __IOM uint32_t GPIO4_EDGE_HIGH : 1; /*!< [19..19] GPIO4_EDGE_HIGH */ - __IOM uint32_t GPIO5_LEVEL_LOW : 1; /*!< [20..20] GPIO5_LEVEL_LOW */ - __IOM uint32_t GPIO5_LEVEL_HIGH : 1; /*!< [21..21] GPIO5_LEVEL_HIGH */ - __IOM uint32_t GPIO5_EDGE_LOW : 1; /*!< [22..22] GPIO5_EDGE_LOW */ - __IOM uint32_t GPIO5_EDGE_HIGH : 1; /*!< [23..23] GPIO5_EDGE_HIGH */ - __IOM uint32_t GPIO6_LEVEL_LOW : 1; /*!< [24..24] GPIO6_LEVEL_LOW */ - __IOM uint32_t GPIO6_LEVEL_HIGH : 1; /*!< [25..25] GPIO6_LEVEL_HIGH */ - __IOM uint32_t GPIO6_EDGE_LOW : 1; /*!< [26..26] GPIO6_EDGE_LOW */ - __IOM uint32_t GPIO6_EDGE_HIGH : 1; /*!< [27..27] GPIO6_EDGE_HIGH */ - __IOM uint32_t GPIO7_LEVEL_LOW : 1; /*!< [28..28] GPIO7_LEVEL_LOW */ - __IOM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< [29..29] GPIO7_LEVEL_HIGH */ - __IOM uint32_t GPIO7_EDGE_LOW : 1; /*!< [30..30] GPIO7_EDGE_LOW */ - __IOM uint32_t GPIO7_EDGE_HIGH : 1; /*!< [31..31] GPIO7_EDGE_HIGH */ - } bit; - } PROC0_INTF0; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000114) Interrupt Force for proc0 */ - - struct { - __IOM uint32_t GPIO8_LEVEL_LOW : 1; /*!< [0..0] GPIO8_LEVEL_LOW */ - __IOM uint32_t GPIO8_LEVEL_HIGH : 1; /*!< [1..1] GPIO8_LEVEL_HIGH */ - __IOM uint32_t GPIO8_EDGE_LOW : 1; /*!< [2..2] GPIO8_EDGE_LOW */ - __IOM uint32_t GPIO8_EDGE_HIGH : 1; /*!< [3..3] GPIO8_EDGE_HIGH */ - __IOM uint32_t GPIO9_LEVEL_LOW : 1; /*!< [4..4] GPIO9_LEVEL_LOW */ - __IOM uint32_t GPIO9_LEVEL_HIGH : 1; /*!< [5..5] GPIO9_LEVEL_HIGH */ - __IOM uint32_t GPIO9_EDGE_LOW : 1; /*!< [6..6] GPIO9_EDGE_LOW */ - __IOM uint32_t GPIO9_EDGE_HIGH : 1; /*!< [7..7] GPIO9_EDGE_HIGH */ - __IOM uint32_t GPIO10_LEVEL_LOW : 1; /*!< [8..8] GPIO10_LEVEL_LOW */ - __IOM uint32_t GPIO10_LEVEL_HIGH : 1; /*!< [9..9] GPIO10_LEVEL_HIGH */ - __IOM uint32_t GPIO10_EDGE_LOW : 1; /*!< [10..10] GPIO10_EDGE_LOW */ - __IOM uint32_t GPIO10_EDGE_HIGH : 1; /*!< [11..11] GPIO10_EDGE_HIGH */ - __IOM uint32_t GPIO11_LEVEL_LOW : 1; /*!< [12..12] GPIO11_LEVEL_LOW */ - __IOM uint32_t GPIO11_LEVEL_HIGH : 1; /*!< [13..13] GPIO11_LEVEL_HIGH */ - __IOM uint32_t GPIO11_EDGE_LOW : 1; /*!< [14..14] GPIO11_EDGE_LOW */ - __IOM uint32_t GPIO11_EDGE_HIGH : 1; /*!< [15..15] GPIO11_EDGE_HIGH */ - __IOM uint32_t GPIO12_LEVEL_LOW : 1; /*!< [16..16] GPIO12_LEVEL_LOW */ - __IOM uint32_t GPIO12_LEVEL_HIGH : 1; /*!< [17..17] GPIO12_LEVEL_HIGH */ - __IOM uint32_t GPIO12_EDGE_LOW : 1; /*!< [18..18] GPIO12_EDGE_LOW */ - __IOM uint32_t GPIO12_EDGE_HIGH : 1; /*!< [19..19] GPIO12_EDGE_HIGH */ - __IOM uint32_t GPIO13_LEVEL_LOW : 1; /*!< [20..20] GPIO13_LEVEL_LOW */ - __IOM uint32_t GPIO13_LEVEL_HIGH : 1; /*!< [21..21] GPIO13_LEVEL_HIGH */ - __IOM uint32_t GPIO13_EDGE_LOW : 1; /*!< [22..22] GPIO13_EDGE_LOW */ - __IOM uint32_t GPIO13_EDGE_HIGH : 1; /*!< [23..23] GPIO13_EDGE_HIGH */ - __IOM uint32_t GPIO14_LEVEL_LOW : 1; /*!< [24..24] GPIO14_LEVEL_LOW */ - __IOM uint32_t GPIO14_LEVEL_HIGH : 1; /*!< [25..25] GPIO14_LEVEL_HIGH */ - __IOM uint32_t GPIO14_EDGE_LOW : 1; /*!< [26..26] GPIO14_EDGE_LOW */ - __IOM uint32_t GPIO14_EDGE_HIGH : 1; /*!< [27..27] GPIO14_EDGE_HIGH */ - __IOM uint32_t GPIO15_LEVEL_LOW : 1; /*!< [28..28] GPIO15_LEVEL_LOW */ - __IOM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< [29..29] GPIO15_LEVEL_HIGH */ - __IOM uint32_t GPIO15_EDGE_LOW : 1; /*!< [30..30] GPIO15_EDGE_LOW */ - __IOM uint32_t GPIO15_EDGE_HIGH : 1; /*!< [31..31] GPIO15_EDGE_HIGH */ - } bit; - } PROC0_INTF1; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000118) Interrupt Force for proc0 */ - - struct { - __IOM uint32_t GPIO16_LEVEL_LOW : 1; /*!< [0..0] GPIO16_LEVEL_LOW */ - __IOM uint32_t GPIO16_LEVEL_HIGH : 1; /*!< [1..1] GPIO16_LEVEL_HIGH */ - __IOM uint32_t GPIO16_EDGE_LOW : 1; /*!< [2..2] GPIO16_EDGE_LOW */ - __IOM uint32_t GPIO16_EDGE_HIGH : 1; /*!< [3..3] GPIO16_EDGE_HIGH */ - __IOM uint32_t GPIO17_LEVEL_LOW : 1; /*!< [4..4] GPIO17_LEVEL_LOW */ - __IOM uint32_t GPIO17_LEVEL_HIGH : 1; /*!< [5..5] GPIO17_LEVEL_HIGH */ - __IOM uint32_t GPIO17_EDGE_LOW : 1; /*!< [6..6] GPIO17_EDGE_LOW */ - __IOM uint32_t GPIO17_EDGE_HIGH : 1; /*!< [7..7] GPIO17_EDGE_HIGH */ - __IOM uint32_t GPIO18_LEVEL_LOW : 1; /*!< [8..8] GPIO18_LEVEL_LOW */ - __IOM uint32_t GPIO18_LEVEL_HIGH : 1; /*!< [9..9] GPIO18_LEVEL_HIGH */ - __IOM uint32_t GPIO18_EDGE_LOW : 1; /*!< [10..10] GPIO18_EDGE_LOW */ - __IOM uint32_t GPIO18_EDGE_HIGH : 1; /*!< [11..11] GPIO18_EDGE_HIGH */ - __IOM uint32_t GPIO19_LEVEL_LOW : 1; /*!< [12..12] GPIO19_LEVEL_LOW */ - __IOM uint32_t GPIO19_LEVEL_HIGH : 1; /*!< [13..13] GPIO19_LEVEL_HIGH */ - __IOM uint32_t GPIO19_EDGE_LOW : 1; /*!< [14..14] GPIO19_EDGE_LOW */ - __IOM uint32_t GPIO19_EDGE_HIGH : 1; /*!< [15..15] GPIO19_EDGE_HIGH */ - __IOM uint32_t GPIO20_LEVEL_LOW : 1; /*!< [16..16] GPIO20_LEVEL_LOW */ - __IOM uint32_t GPIO20_LEVEL_HIGH : 1; /*!< [17..17] GPIO20_LEVEL_HIGH */ - __IOM uint32_t GPIO20_EDGE_LOW : 1; /*!< [18..18] GPIO20_EDGE_LOW */ - __IOM uint32_t GPIO20_EDGE_HIGH : 1; /*!< [19..19] GPIO20_EDGE_HIGH */ - __IOM uint32_t GPIO21_LEVEL_LOW : 1; /*!< [20..20] GPIO21_LEVEL_LOW */ - __IOM uint32_t GPIO21_LEVEL_HIGH : 1; /*!< [21..21] GPIO21_LEVEL_HIGH */ - __IOM uint32_t GPIO21_EDGE_LOW : 1; /*!< [22..22] GPIO21_EDGE_LOW */ - __IOM uint32_t GPIO21_EDGE_HIGH : 1; /*!< [23..23] GPIO21_EDGE_HIGH */ - __IOM uint32_t GPIO22_LEVEL_LOW : 1; /*!< [24..24] GPIO22_LEVEL_LOW */ - __IOM uint32_t GPIO22_LEVEL_HIGH : 1; /*!< [25..25] GPIO22_LEVEL_HIGH */ - __IOM uint32_t GPIO22_EDGE_LOW : 1; /*!< [26..26] GPIO22_EDGE_LOW */ - __IOM uint32_t GPIO22_EDGE_HIGH : 1; /*!< [27..27] GPIO22_EDGE_HIGH */ - __IOM uint32_t GPIO23_LEVEL_LOW : 1; /*!< [28..28] GPIO23_LEVEL_LOW */ - __IOM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< [29..29] GPIO23_LEVEL_HIGH */ - __IOM uint32_t GPIO23_EDGE_LOW : 1; /*!< [30..30] GPIO23_EDGE_LOW */ - __IOM uint32_t GPIO23_EDGE_HIGH : 1; /*!< [31..31] GPIO23_EDGE_HIGH */ - } bit; - } PROC0_INTF2; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000011C) Interrupt Force for proc0 */ - - struct { - __IOM uint32_t GPIO24_LEVEL_LOW : 1; /*!< [0..0] GPIO24_LEVEL_LOW */ - __IOM uint32_t GPIO24_LEVEL_HIGH : 1; /*!< [1..1] GPIO24_LEVEL_HIGH */ - __IOM uint32_t GPIO24_EDGE_LOW : 1; /*!< [2..2] GPIO24_EDGE_LOW */ - __IOM uint32_t GPIO24_EDGE_HIGH : 1; /*!< [3..3] GPIO24_EDGE_HIGH */ - __IOM uint32_t GPIO25_LEVEL_LOW : 1; /*!< [4..4] GPIO25_LEVEL_LOW */ - __IOM uint32_t GPIO25_LEVEL_HIGH : 1; /*!< [5..5] GPIO25_LEVEL_HIGH */ - __IOM uint32_t GPIO25_EDGE_LOW : 1; /*!< [6..6] GPIO25_EDGE_LOW */ - __IOM uint32_t GPIO25_EDGE_HIGH : 1; /*!< [7..7] GPIO25_EDGE_HIGH */ - __IOM uint32_t GPIO26_LEVEL_LOW : 1; /*!< [8..8] GPIO26_LEVEL_LOW */ - __IOM uint32_t GPIO26_LEVEL_HIGH : 1; /*!< [9..9] GPIO26_LEVEL_HIGH */ - __IOM uint32_t GPIO26_EDGE_LOW : 1; /*!< [10..10] GPIO26_EDGE_LOW */ - __IOM uint32_t GPIO26_EDGE_HIGH : 1; /*!< [11..11] GPIO26_EDGE_HIGH */ - __IOM uint32_t GPIO27_LEVEL_LOW : 1; /*!< [12..12] GPIO27_LEVEL_LOW */ - __IOM uint32_t GPIO27_LEVEL_HIGH : 1; /*!< [13..13] GPIO27_LEVEL_HIGH */ - __IOM uint32_t GPIO27_EDGE_LOW : 1; /*!< [14..14] GPIO27_EDGE_LOW */ - __IOM uint32_t GPIO27_EDGE_HIGH : 1; /*!< [15..15] GPIO27_EDGE_HIGH */ - __IOM uint32_t GPIO28_LEVEL_LOW : 1; /*!< [16..16] GPIO28_LEVEL_LOW */ - __IOM uint32_t GPIO28_LEVEL_HIGH : 1; /*!< [17..17] GPIO28_LEVEL_HIGH */ - __IOM uint32_t GPIO28_EDGE_LOW : 1; /*!< [18..18] GPIO28_EDGE_LOW */ - __IOM uint32_t GPIO28_EDGE_HIGH : 1; /*!< [19..19] GPIO28_EDGE_HIGH */ - __IOM uint32_t GPIO29_LEVEL_LOW : 1; /*!< [20..20] GPIO29_LEVEL_LOW */ - __IOM uint32_t GPIO29_LEVEL_HIGH : 1; /*!< [21..21] GPIO29_LEVEL_HIGH */ - __IOM uint32_t GPIO29_EDGE_LOW : 1; /*!< [22..22] GPIO29_EDGE_LOW */ - __IOM uint32_t GPIO29_EDGE_HIGH : 1; /*!< [23..23] GPIO29_EDGE_HIGH */ - uint32_t : 8; - } bit; - } PROC0_INTF3; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000120) Interrupt status after masking & forcing for + __IOM uint32_t GPIO0_STATUS; /*!< (@ 0x00000000) GPIO status */ + __IOM uint32_t GPIO0_CTRL; /*!< (@ 0x00000004) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO1_STATUS; /*!< (@ 0x00000008) GPIO status */ + __IOM uint32_t GPIO1_CTRL; /*!< (@ 0x0000000C) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO2_STATUS; /*!< (@ 0x00000010) GPIO status */ + __IOM uint32_t GPIO2_CTRL; /*!< (@ 0x00000014) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO3_STATUS; /*!< (@ 0x00000018) GPIO status */ + __IOM uint32_t GPIO3_CTRL; /*!< (@ 0x0000001C) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO4_STATUS; /*!< (@ 0x00000020) GPIO status */ + __IOM uint32_t GPIO4_CTRL; /*!< (@ 0x00000024) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO5_STATUS; /*!< (@ 0x00000028) GPIO status */ + __IOM uint32_t GPIO5_CTRL; /*!< (@ 0x0000002C) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO6_STATUS; /*!< (@ 0x00000030) GPIO status */ + __IOM uint32_t GPIO6_CTRL; /*!< (@ 0x00000034) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO7_STATUS; /*!< (@ 0x00000038) GPIO status */ + __IOM uint32_t GPIO7_CTRL; /*!< (@ 0x0000003C) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO8_STATUS; /*!< (@ 0x00000040) GPIO status */ + __IOM uint32_t GPIO8_CTRL; /*!< (@ 0x00000044) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO9_STATUS; /*!< (@ 0x00000048) GPIO status */ + __IOM uint32_t GPIO9_CTRL; /*!< (@ 0x0000004C) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO10_STATUS; /*!< (@ 0x00000050) GPIO status */ + __IOM uint32_t GPIO10_CTRL; /*!< (@ 0x00000054) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO11_STATUS; /*!< (@ 0x00000058) GPIO status */ + __IOM uint32_t GPIO11_CTRL; /*!< (@ 0x0000005C) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO12_STATUS; /*!< (@ 0x00000060) GPIO status */ + __IOM uint32_t GPIO12_CTRL; /*!< (@ 0x00000064) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO13_STATUS; /*!< (@ 0x00000068) GPIO status */ + __IOM uint32_t GPIO13_CTRL; /*!< (@ 0x0000006C) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO14_STATUS; /*!< (@ 0x00000070) GPIO status */ + __IOM uint32_t GPIO14_CTRL; /*!< (@ 0x00000074) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO15_STATUS; /*!< (@ 0x00000078) GPIO status */ + __IOM uint32_t GPIO15_CTRL; /*!< (@ 0x0000007C) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO16_STATUS; /*!< (@ 0x00000080) GPIO status */ + __IOM uint32_t GPIO16_CTRL; /*!< (@ 0x00000084) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO17_STATUS; /*!< (@ 0x00000088) GPIO status */ + __IOM uint32_t GPIO17_CTRL; /*!< (@ 0x0000008C) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO18_STATUS; /*!< (@ 0x00000090) GPIO status */ + __IOM uint32_t GPIO18_CTRL; /*!< (@ 0x00000094) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO19_STATUS; /*!< (@ 0x00000098) GPIO status */ + __IOM uint32_t GPIO19_CTRL; /*!< (@ 0x0000009C) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO20_STATUS; /*!< (@ 0x000000A0) GPIO status */ + __IOM uint32_t GPIO20_CTRL; /*!< (@ 0x000000A4) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO21_STATUS; /*!< (@ 0x000000A8) GPIO status */ + __IOM uint32_t GPIO21_CTRL; /*!< (@ 0x000000AC) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO22_STATUS; /*!< (@ 0x000000B0) GPIO status */ + __IOM uint32_t GPIO22_CTRL; /*!< (@ 0x000000B4) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO23_STATUS; /*!< (@ 0x000000B8) GPIO status */ + __IOM uint32_t GPIO23_CTRL; /*!< (@ 0x000000BC) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO24_STATUS; /*!< (@ 0x000000C0) GPIO status */ + __IOM uint32_t GPIO24_CTRL; /*!< (@ 0x000000C4) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO25_STATUS; /*!< (@ 0x000000C8) GPIO status */ + __IOM uint32_t GPIO25_CTRL; /*!< (@ 0x000000CC) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO26_STATUS; /*!< (@ 0x000000D0) GPIO status */ + __IOM uint32_t GPIO26_CTRL; /*!< (@ 0x000000D4) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO27_STATUS; /*!< (@ 0x000000D8) GPIO status */ + __IOM uint32_t GPIO27_CTRL; /*!< (@ 0x000000DC) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO28_STATUS; /*!< (@ 0x000000E0) GPIO status */ + __IOM uint32_t GPIO28_CTRL; /*!< (@ 0x000000E4) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO29_STATUS; /*!< (@ 0x000000E8) GPIO status */ + __IOM uint32_t GPIO29_CTRL; /*!< (@ 0x000000EC) GPIO control including function select and overrides. */ + __IOM uint32_t INTR0; /*!< (@ 0x000000F0) Raw Interrupts */ + __IOM uint32_t INTR1; /*!< (@ 0x000000F4) Raw Interrupts */ + __IOM uint32_t INTR2; /*!< (@ 0x000000F8) Raw Interrupts */ + __IOM uint32_t INTR3; /*!< (@ 0x000000FC) Raw Interrupts */ + __IOM uint32_t PROC0_INTE0; /*!< (@ 0x00000100) Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTE1; /*!< (@ 0x00000104) Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTE2; /*!< (@ 0x00000108) Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTE3; /*!< (@ 0x0000010C) Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTF0; /*!< (@ 0x00000110) Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTF1; /*!< (@ 0x00000114) Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTF2; /*!< (@ 0x00000118) Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTF3; /*!< (@ 0x0000011C) Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTS0; /*!< (@ 0x00000120) Interrupt status after masking & forcing for proc0 */ - - struct { - __IM uint32_t GPIO0_LEVEL_LOW : 1; /*!< [0..0] GPIO0_LEVEL_LOW */ - __IM uint32_t GPIO0_LEVEL_HIGH : 1; /*!< [1..1] GPIO0_LEVEL_HIGH */ - __IM uint32_t GPIO0_EDGE_LOW : 1; /*!< [2..2] GPIO0_EDGE_LOW */ - __IM uint32_t GPIO0_EDGE_HIGH : 1; /*!< [3..3] GPIO0_EDGE_HIGH */ - __IM uint32_t GPIO1_LEVEL_LOW : 1; /*!< [4..4] GPIO1_LEVEL_LOW */ - __IM uint32_t GPIO1_LEVEL_HIGH : 1; /*!< [5..5] GPIO1_LEVEL_HIGH */ - __IM uint32_t GPIO1_EDGE_LOW : 1; /*!< [6..6] GPIO1_EDGE_LOW */ - __IM uint32_t GPIO1_EDGE_HIGH : 1; /*!< [7..7] GPIO1_EDGE_HIGH */ - __IM uint32_t GPIO2_LEVEL_LOW : 1; /*!< [8..8] GPIO2_LEVEL_LOW */ - __IM uint32_t GPIO2_LEVEL_HIGH : 1; /*!< [9..9] GPIO2_LEVEL_HIGH */ - __IM uint32_t GPIO2_EDGE_LOW : 1; /*!< [10..10] GPIO2_EDGE_LOW */ - __IM uint32_t GPIO2_EDGE_HIGH : 1; /*!< [11..11] GPIO2_EDGE_HIGH */ - __IM uint32_t GPIO3_LEVEL_LOW : 1; /*!< [12..12] GPIO3_LEVEL_LOW */ - __IM uint32_t GPIO3_LEVEL_HIGH : 1; /*!< [13..13] GPIO3_LEVEL_HIGH */ - __IM uint32_t GPIO3_EDGE_LOW : 1; /*!< [14..14] GPIO3_EDGE_LOW */ - __IM uint32_t GPIO3_EDGE_HIGH : 1; /*!< [15..15] GPIO3_EDGE_HIGH */ - __IM uint32_t GPIO4_LEVEL_LOW : 1; /*!< [16..16] GPIO4_LEVEL_LOW */ - __IM uint32_t GPIO4_LEVEL_HIGH : 1; /*!< [17..17] GPIO4_LEVEL_HIGH */ - __IM uint32_t GPIO4_EDGE_LOW : 1; /*!< [18..18] GPIO4_EDGE_LOW */ - __IM uint32_t GPIO4_EDGE_HIGH : 1; /*!< [19..19] GPIO4_EDGE_HIGH */ - __IM uint32_t GPIO5_LEVEL_LOW : 1; /*!< [20..20] GPIO5_LEVEL_LOW */ - __IM uint32_t GPIO5_LEVEL_HIGH : 1; /*!< [21..21] GPIO5_LEVEL_HIGH */ - __IM uint32_t GPIO5_EDGE_LOW : 1; /*!< [22..22] GPIO5_EDGE_LOW */ - __IM uint32_t GPIO5_EDGE_HIGH : 1; /*!< [23..23] GPIO5_EDGE_HIGH */ - __IM uint32_t GPIO6_LEVEL_LOW : 1; /*!< [24..24] GPIO6_LEVEL_LOW */ - __IM uint32_t GPIO6_LEVEL_HIGH : 1; /*!< [25..25] GPIO6_LEVEL_HIGH */ - __IM uint32_t GPIO6_EDGE_LOW : 1; /*!< [26..26] GPIO6_EDGE_LOW */ - __IM uint32_t GPIO6_EDGE_HIGH : 1; /*!< [27..27] GPIO6_EDGE_HIGH */ - __IM uint32_t GPIO7_LEVEL_LOW : 1; /*!< [28..28] GPIO7_LEVEL_LOW */ - __IM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< [29..29] GPIO7_LEVEL_HIGH */ - __IM uint32_t GPIO7_EDGE_LOW : 1; /*!< [30..30] GPIO7_EDGE_LOW */ - __IM uint32_t GPIO7_EDGE_HIGH : 1; /*!< [31..31] GPIO7_EDGE_HIGH */ - } bit; - } PROC0_INTS0; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000124) Interrupt status after masking & forcing for + __IOM uint32_t PROC0_INTS1; /*!< (@ 0x00000124) Interrupt status after masking & forcing for proc0 */ - - struct { - __IM uint32_t GPIO8_LEVEL_LOW : 1; /*!< [0..0] GPIO8_LEVEL_LOW */ - __IM uint32_t GPIO8_LEVEL_HIGH : 1; /*!< [1..1] GPIO8_LEVEL_HIGH */ - __IM uint32_t GPIO8_EDGE_LOW : 1; /*!< [2..2] GPIO8_EDGE_LOW */ - __IM uint32_t GPIO8_EDGE_HIGH : 1; /*!< [3..3] GPIO8_EDGE_HIGH */ - __IM uint32_t GPIO9_LEVEL_LOW : 1; /*!< [4..4] GPIO9_LEVEL_LOW */ - __IM uint32_t GPIO9_LEVEL_HIGH : 1; /*!< [5..5] GPIO9_LEVEL_HIGH */ - __IM uint32_t GPIO9_EDGE_LOW : 1; /*!< [6..6] GPIO9_EDGE_LOW */ - __IM uint32_t GPIO9_EDGE_HIGH : 1; /*!< [7..7] GPIO9_EDGE_HIGH */ - __IM uint32_t GPIO10_LEVEL_LOW : 1; /*!< [8..8] GPIO10_LEVEL_LOW */ - __IM uint32_t GPIO10_LEVEL_HIGH : 1; /*!< [9..9] GPIO10_LEVEL_HIGH */ - __IM uint32_t GPIO10_EDGE_LOW : 1; /*!< [10..10] GPIO10_EDGE_LOW */ - __IM uint32_t GPIO10_EDGE_HIGH : 1; /*!< [11..11] GPIO10_EDGE_HIGH */ - __IM uint32_t GPIO11_LEVEL_LOW : 1; /*!< [12..12] GPIO11_LEVEL_LOW */ - __IM uint32_t GPIO11_LEVEL_HIGH : 1; /*!< [13..13] GPIO11_LEVEL_HIGH */ - __IM uint32_t GPIO11_EDGE_LOW : 1; /*!< [14..14] GPIO11_EDGE_LOW */ - __IM uint32_t GPIO11_EDGE_HIGH : 1; /*!< [15..15] GPIO11_EDGE_HIGH */ - __IM uint32_t GPIO12_LEVEL_LOW : 1; /*!< [16..16] GPIO12_LEVEL_LOW */ - __IM uint32_t GPIO12_LEVEL_HIGH : 1; /*!< [17..17] GPIO12_LEVEL_HIGH */ - __IM uint32_t GPIO12_EDGE_LOW : 1; /*!< [18..18] GPIO12_EDGE_LOW */ - __IM uint32_t GPIO12_EDGE_HIGH : 1; /*!< [19..19] GPIO12_EDGE_HIGH */ - __IM uint32_t GPIO13_LEVEL_LOW : 1; /*!< [20..20] GPIO13_LEVEL_LOW */ - __IM uint32_t GPIO13_LEVEL_HIGH : 1; /*!< [21..21] GPIO13_LEVEL_HIGH */ - __IM uint32_t GPIO13_EDGE_LOW : 1; /*!< [22..22] GPIO13_EDGE_LOW */ - __IM uint32_t GPIO13_EDGE_HIGH : 1; /*!< [23..23] GPIO13_EDGE_HIGH */ - __IM uint32_t GPIO14_LEVEL_LOW : 1; /*!< [24..24] GPIO14_LEVEL_LOW */ - __IM uint32_t GPIO14_LEVEL_HIGH : 1; /*!< [25..25] GPIO14_LEVEL_HIGH */ - __IM uint32_t GPIO14_EDGE_LOW : 1; /*!< [26..26] GPIO14_EDGE_LOW */ - __IM uint32_t GPIO14_EDGE_HIGH : 1; /*!< [27..27] GPIO14_EDGE_HIGH */ - __IM uint32_t GPIO15_LEVEL_LOW : 1; /*!< [28..28] GPIO15_LEVEL_LOW */ - __IM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< [29..29] GPIO15_LEVEL_HIGH */ - __IM uint32_t GPIO15_EDGE_LOW : 1; /*!< [30..30] GPIO15_EDGE_LOW */ - __IM uint32_t GPIO15_EDGE_HIGH : 1; /*!< [31..31] GPIO15_EDGE_HIGH */ - } bit; - } PROC0_INTS1; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000128) Interrupt status after masking & forcing for + __IOM uint32_t PROC0_INTS2; /*!< (@ 0x00000128) Interrupt status after masking & forcing for proc0 */ - - struct { - __IM uint32_t GPIO16_LEVEL_LOW : 1; /*!< [0..0] GPIO16_LEVEL_LOW */ - __IM uint32_t GPIO16_LEVEL_HIGH : 1; /*!< [1..1] GPIO16_LEVEL_HIGH */ - __IM uint32_t GPIO16_EDGE_LOW : 1; /*!< [2..2] GPIO16_EDGE_LOW */ - __IM uint32_t GPIO16_EDGE_HIGH : 1; /*!< [3..3] GPIO16_EDGE_HIGH */ - __IM uint32_t GPIO17_LEVEL_LOW : 1; /*!< [4..4] GPIO17_LEVEL_LOW */ - __IM uint32_t GPIO17_LEVEL_HIGH : 1; /*!< [5..5] GPIO17_LEVEL_HIGH */ - __IM uint32_t GPIO17_EDGE_LOW : 1; /*!< [6..6] GPIO17_EDGE_LOW */ - __IM uint32_t GPIO17_EDGE_HIGH : 1; /*!< [7..7] GPIO17_EDGE_HIGH */ - __IM uint32_t GPIO18_LEVEL_LOW : 1; /*!< [8..8] GPIO18_LEVEL_LOW */ - __IM uint32_t GPIO18_LEVEL_HIGH : 1; /*!< [9..9] GPIO18_LEVEL_HIGH */ - __IM uint32_t GPIO18_EDGE_LOW : 1; /*!< [10..10] GPIO18_EDGE_LOW */ - __IM uint32_t GPIO18_EDGE_HIGH : 1; /*!< [11..11] GPIO18_EDGE_HIGH */ - __IM uint32_t GPIO19_LEVEL_LOW : 1; /*!< [12..12] GPIO19_LEVEL_LOW */ - __IM uint32_t GPIO19_LEVEL_HIGH : 1; /*!< [13..13] GPIO19_LEVEL_HIGH */ - __IM uint32_t GPIO19_EDGE_LOW : 1; /*!< [14..14] GPIO19_EDGE_LOW */ - __IM uint32_t GPIO19_EDGE_HIGH : 1; /*!< [15..15] GPIO19_EDGE_HIGH */ - __IM uint32_t GPIO20_LEVEL_LOW : 1; /*!< [16..16] GPIO20_LEVEL_LOW */ - __IM uint32_t GPIO20_LEVEL_HIGH : 1; /*!< [17..17] GPIO20_LEVEL_HIGH */ - __IM uint32_t GPIO20_EDGE_LOW : 1; /*!< [18..18] GPIO20_EDGE_LOW */ - __IM uint32_t GPIO20_EDGE_HIGH : 1; /*!< [19..19] GPIO20_EDGE_HIGH */ - __IM uint32_t GPIO21_LEVEL_LOW : 1; /*!< [20..20] GPIO21_LEVEL_LOW */ - __IM uint32_t GPIO21_LEVEL_HIGH : 1; /*!< [21..21] GPIO21_LEVEL_HIGH */ - __IM uint32_t GPIO21_EDGE_LOW : 1; /*!< [22..22] GPIO21_EDGE_LOW */ - __IM uint32_t GPIO21_EDGE_HIGH : 1; /*!< [23..23] GPIO21_EDGE_HIGH */ - __IM uint32_t GPIO22_LEVEL_LOW : 1; /*!< [24..24] GPIO22_LEVEL_LOW */ - __IM uint32_t GPIO22_LEVEL_HIGH : 1; /*!< [25..25] GPIO22_LEVEL_HIGH */ - __IM uint32_t GPIO22_EDGE_LOW : 1; /*!< [26..26] GPIO22_EDGE_LOW */ - __IM uint32_t GPIO22_EDGE_HIGH : 1; /*!< [27..27] GPIO22_EDGE_HIGH */ - __IM uint32_t GPIO23_LEVEL_LOW : 1; /*!< [28..28] GPIO23_LEVEL_LOW */ - __IM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< [29..29] GPIO23_LEVEL_HIGH */ - __IM uint32_t GPIO23_EDGE_LOW : 1; /*!< [30..30] GPIO23_EDGE_LOW */ - __IM uint32_t GPIO23_EDGE_HIGH : 1; /*!< [31..31] GPIO23_EDGE_HIGH */ - } bit; - } PROC0_INTS2; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000012C) Interrupt status after masking & forcing for + __IOM uint32_t PROC0_INTS3; /*!< (@ 0x0000012C) Interrupt status after masking & forcing for proc0 */ - - struct { - __IM uint32_t GPIO24_LEVEL_LOW : 1; /*!< [0..0] GPIO24_LEVEL_LOW */ - __IM uint32_t GPIO24_LEVEL_HIGH : 1; /*!< [1..1] GPIO24_LEVEL_HIGH */ - __IM uint32_t GPIO24_EDGE_LOW : 1; /*!< [2..2] GPIO24_EDGE_LOW */ - __IM uint32_t GPIO24_EDGE_HIGH : 1; /*!< [3..3] GPIO24_EDGE_HIGH */ - __IM uint32_t GPIO25_LEVEL_LOW : 1; /*!< [4..4] GPIO25_LEVEL_LOW */ - __IM uint32_t GPIO25_LEVEL_HIGH : 1; /*!< [5..5] GPIO25_LEVEL_HIGH */ - __IM uint32_t GPIO25_EDGE_LOW : 1; /*!< [6..6] GPIO25_EDGE_LOW */ - __IM uint32_t GPIO25_EDGE_HIGH : 1; /*!< [7..7] GPIO25_EDGE_HIGH */ - __IM uint32_t GPIO26_LEVEL_LOW : 1; /*!< [8..8] GPIO26_LEVEL_LOW */ - __IM uint32_t GPIO26_LEVEL_HIGH : 1; /*!< [9..9] GPIO26_LEVEL_HIGH */ - __IM uint32_t GPIO26_EDGE_LOW : 1; /*!< [10..10] GPIO26_EDGE_LOW */ - __IM uint32_t GPIO26_EDGE_HIGH : 1; /*!< [11..11] GPIO26_EDGE_HIGH */ - __IM uint32_t GPIO27_LEVEL_LOW : 1; /*!< [12..12] GPIO27_LEVEL_LOW */ - __IM uint32_t GPIO27_LEVEL_HIGH : 1; /*!< [13..13] GPIO27_LEVEL_HIGH */ - __IM uint32_t GPIO27_EDGE_LOW : 1; /*!< [14..14] GPIO27_EDGE_LOW */ - __IM uint32_t GPIO27_EDGE_HIGH : 1; /*!< [15..15] GPIO27_EDGE_HIGH */ - __IM uint32_t GPIO28_LEVEL_LOW : 1; /*!< [16..16] GPIO28_LEVEL_LOW */ - __IM uint32_t GPIO28_LEVEL_HIGH : 1; /*!< [17..17] GPIO28_LEVEL_HIGH */ - __IM uint32_t GPIO28_EDGE_LOW : 1; /*!< [18..18] GPIO28_EDGE_LOW */ - __IM uint32_t GPIO28_EDGE_HIGH : 1; /*!< [19..19] GPIO28_EDGE_HIGH */ - __IM uint32_t GPIO29_LEVEL_LOW : 1; /*!< [20..20] GPIO29_LEVEL_LOW */ - __IM uint32_t GPIO29_LEVEL_HIGH : 1; /*!< [21..21] GPIO29_LEVEL_HIGH */ - __IM uint32_t GPIO29_EDGE_LOW : 1; /*!< [22..22] GPIO29_EDGE_LOW */ - __IM uint32_t GPIO29_EDGE_HIGH : 1; /*!< [23..23] GPIO29_EDGE_HIGH */ - uint32_t : 8; - } bit; - } PROC0_INTS3; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000130) Interrupt Enable for proc1 */ - - struct { - __IOM uint32_t GPIO0_LEVEL_LOW : 1; /*!< [0..0] GPIO0_LEVEL_LOW */ - __IOM uint32_t GPIO0_LEVEL_HIGH : 1; /*!< [1..1] GPIO0_LEVEL_HIGH */ - __IOM uint32_t GPIO0_EDGE_LOW : 1; /*!< [2..2] GPIO0_EDGE_LOW */ - __IOM uint32_t GPIO0_EDGE_HIGH : 1; /*!< [3..3] GPIO0_EDGE_HIGH */ - __IOM uint32_t GPIO1_LEVEL_LOW : 1; /*!< [4..4] GPIO1_LEVEL_LOW */ - __IOM uint32_t GPIO1_LEVEL_HIGH : 1; /*!< [5..5] GPIO1_LEVEL_HIGH */ - __IOM uint32_t GPIO1_EDGE_LOW : 1; /*!< [6..6] GPIO1_EDGE_LOW */ - __IOM uint32_t GPIO1_EDGE_HIGH : 1; /*!< [7..7] GPIO1_EDGE_HIGH */ - __IOM uint32_t GPIO2_LEVEL_LOW : 1; /*!< [8..8] GPIO2_LEVEL_LOW */ - __IOM uint32_t GPIO2_LEVEL_HIGH : 1; /*!< [9..9] GPIO2_LEVEL_HIGH */ - __IOM uint32_t GPIO2_EDGE_LOW : 1; /*!< [10..10] GPIO2_EDGE_LOW */ - __IOM uint32_t GPIO2_EDGE_HIGH : 1; /*!< [11..11] GPIO2_EDGE_HIGH */ - __IOM uint32_t GPIO3_LEVEL_LOW : 1; /*!< [12..12] GPIO3_LEVEL_LOW */ - __IOM uint32_t GPIO3_LEVEL_HIGH : 1; /*!< [13..13] GPIO3_LEVEL_HIGH */ - __IOM uint32_t GPIO3_EDGE_LOW : 1; /*!< [14..14] GPIO3_EDGE_LOW */ - __IOM uint32_t GPIO3_EDGE_HIGH : 1; /*!< [15..15] GPIO3_EDGE_HIGH */ - __IOM uint32_t GPIO4_LEVEL_LOW : 1; /*!< [16..16] GPIO4_LEVEL_LOW */ - __IOM uint32_t GPIO4_LEVEL_HIGH : 1; /*!< [17..17] GPIO4_LEVEL_HIGH */ - __IOM uint32_t GPIO4_EDGE_LOW : 1; /*!< [18..18] GPIO4_EDGE_LOW */ - __IOM uint32_t GPIO4_EDGE_HIGH : 1; /*!< [19..19] GPIO4_EDGE_HIGH */ - __IOM uint32_t GPIO5_LEVEL_LOW : 1; /*!< [20..20] GPIO5_LEVEL_LOW */ - __IOM uint32_t GPIO5_LEVEL_HIGH : 1; /*!< [21..21] GPIO5_LEVEL_HIGH */ - __IOM uint32_t GPIO5_EDGE_LOW : 1; /*!< [22..22] GPIO5_EDGE_LOW */ - __IOM uint32_t GPIO5_EDGE_HIGH : 1; /*!< [23..23] GPIO5_EDGE_HIGH */ - __IOM uint32_t GPIO6_LEVEL_LOW : 1; /*!< [24..24] GPIO6_LEVEL_LOW */ - __IOM uint32_t GPIO6_LEVEL_HIGH : 1; /*!< [25..25] GPIO6_LEVEL_HIGH */ - __IOM uint32_t GPIO6_EDGE_LOW : 1; /*!< [26..26] GPIO6_EDGE_LOW */ - __IOM uint32_t GPIO6_EDGE_HIGH : 1; /*!< [27..27] GPIO6_EDGE_HIGH */ - __IOM uint32_t GPIO7_LEVEL_LOW : 1; /*!< [28..28] GPIO7_LEVEL_LOW */ - __IOM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< [29..29] GPIO7_LEVEL_HIGH */ - __IOM uint32_t GPIO7_EDGE_LOW : 1; /*!< [30..30] GPIO7_EDGE_LOW */ - __IOM uint32_t GPIO7_EDGE_HIGH : 1; /*!< [31..31] GPIO7_EDGE_HIGH */ - } bit; - } PROC1_INTE0; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000134) Interrupt Enable for proc1 */ - - struct { - __IOM uint32_t GPIO8_LEVEL_LOW : 1; /*!< [0..0] GPIO8_LEVEL_LOW */ - __IOM uint32_t GPIO8_LEVEL_HIGH : 1; /*!< [1..1] GPIO8_LEVEL_HIGH */ - __IOM uint32_t GPIO8_EDGE_LOW : 1; /*!< [2..2] GPIO8_EDGE_LOW */ - __IOM uint32_t GPIO8_EDGE_HIGH : 1; /*!< [3..3] GPIO8_EDGE_HIGH */ - __IOM uint32_t GPIO9_LEVEL_LOW : 1; /*!< [4..4] GPIO9_LEVEL_LOW */ - __IOM uint32_t GPIO9_LEVEL_HIGH : 1; /*!< [5..5] GPIO9_LEVEL_HIGH */ - __IOM uint32_t GPIO9_EDGE_LOW : 1; /*!< [6..6] GPIO9_EDGE_LOW */ - __IOM uint32_t GPIO9_EDGE_HIGH : 1; /*!< [7..7] GPIO9_EDGE_HIGH */ - __IOM uint32_t GPIO10_LEVEL_LOW : 1; /*!< [8..8] GPIO10_LEVEL_LOW */ - __IOM uint32_t GPIO10_LEVEL_HIGH : 1; /*!< [9..9] GPIO10_LEVEL_HIGH */ - __IOM uint32_t GPIO10_EDGE_LOW : 1; /*!< [10..10] GPIO10_EDGE_LOW */ - __IOM uint32_t GPIO10_EDGE_HIGH : 1; /*!< [11..11] GPIO10_EDGE_HIGH */ - __IOM uint32_t GPIO11_LEVEL_LOW : 1; /*!< [12..12] GPIO11_LEVEL_LOW */ - __IOM uint32_t GPIO11_LEVEL_HIGH : 1; /*!< [13..13] GPIO11_LEVEL_HIGH */ - __IOM uint32_t GPIO11_EDGE_LOW : 1; /*!< [14..14] GPIO11_EDGE_LOW */ - __IOM uint32_t GPIO11_EDGE_HIGH : 1; /*!< [15..15] GPIO11_EDGE_HIGH */ - __IOM uint32_t GPIO12_LEVEL_LOW : 1; /*!< [16..16] GPIO12_LEVEL_LOW */ - __IOM uint32_t GPIO12_LEVEL_HIGH : 1; /*!< [17..17] GPIO12_LEVEL_HIGH */ - __IOM uint32_t GPIO12_EDGE_LOW : 1; /*!< [18..18] GPIO12_EDGE_LOW */ - __IOM uint32_t GPIO12_EDGE_HIGH : 1; /*!< [19..19] GPIO12_EDGE_HIGH */ - __IOM uint32_t GPIO13_LEVEL_LOW : 1; /*!< [20..20] GPIO13_LEVEL_LOW */ - __IOM uint32_t GPIO13_LEVEL_HIGH : 1; /*!< [21..21] GPIO13_LEVEL_HIGH */ - __IOM uint32_t GPIO13_EDGE_LOW : 1; /*!< [22..22] GPIO13_EDGE_LOW */ - __IOM uint32_t GPIO13_EDGE_HIGH : 1; /*!< [23..23] GPIO13_EDGE_HIGH */ - __IOM uint32_t GPIO14_LEVEL_LOW : 1; /*!< [24..24] GPIO14_LEVEL_LOW */ - __IOM uint32_t GPIO14_LEVEL_HIGH : 1; /*!< [25..25] GPIO14_LEVEL_HIGH */ - __IOM uint32_t GPIO14_EDGE_LOW : 1; /*!< [26..26] GPIO14_EDGE_LOW */ - __IOM uint32_t GPIO14_EDGE_HIGH : 1; /*!< [27..27] GPIO14_EDGE_HIGH */ - __IOM uint32_t GPIO15_LEVEL_LOW : 1; /*!< [28..28] GPIO15_LEVEL_LOW */ - __IOM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< [29..29] GPIO15_LEVEL_HIGH */ - __IOM uint32_t GPIO15_EDGE_LOW : 1; /*!< [30..30] GPIO15_EDGE_LOW */ - __IOM uint32_t GPIO15_EDGE_HIGH : 1; /*!< [31..31] GPIO15_EDGE_HIGH */ - } bit; - } PROC1_INTE1; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000138) Interrupt Enable for proc1 */ - - struct { - __IOM uint32_t GPIO16_LEVEL_LOW : 1; /*!< [0..0] GPIO16_LEVEL_LOW */ - __IOM uint32_t GPIO16_LEVEL_HIGH : 1; /*!< [1..1] GPIO16_LEVEL_HIGH */ - __IOM uint32_t GPIO16_EDGE_LOW : 1; /*!< [2..2] GPIO16_EDGE_LOW */ - __IOM uint32_t GPIO16_EDGE_HIGH : 1; /*!< [3..3] GPIO16_EDGE_HIGH */ - __IOM uint32_t GPIO17_LEVEL_LOW : 1; /*!< [4..4] GPIO17_LEVEL_LOW */ - __IOM uint32_t GPIO17_LEVEL_HIGH : 1; /*!< [5..5] GPIO17_LEVEL_HIGH */ - __IOM uint32_t GPIO17_EDGE_LOW : 1; /*!< [6..6] GPIO17_EDGE_LOW */ - __IOM uint32_t GPIO17_EDGE_HIGH : 1; /*!< [7..7] GPIO17_EDGE_HIGH */ - __IOM uint32_t GPIO18_LEVEL_LOW : 1; /*!< [8..8] GPIO18_LEVEL_LOW */ - __IOM uint32_t GPIO18_LEVEL_HIGH : 1; /*!< [9..9] GPIO18_LEVEL_HIGH */ - __IOM uint32_t GPIO18_EDGE_LOW : 1; /*!< [10..10] GPIO18_EDGE_LOW */ - __IOM uint32_t GPIO18_EDGE_HIGH : 1; /*!< [11..11] GPIO18_EDGE_HIGH */ - __IOM uint32_t GPIO19_LEVEL_LOW : 1; /*!< [12..12] GPIO19_LEVEL_LOW */ - __IOM uint32_t GPIO19_LEVEL_HIGH : 1; /*!< [13..13] GPIO19_LEVEL_HIGH */ - __IOM uint32_t GPIO19_EDGE_LOW : 1; /*!< [14..14] GPIO19_EDGE_LOW */ - __IOM uint32_t GPIO19_EDGE_HIGH : 1; /*!< [15..15] GPIO19_EDGE_HIGH */ - __IOM uint32_t GPIO20_LEVEL_LOW : 1; /*!< [16..16] GPIO20_LEVEL_LOW */ - __IOM uint32_t GPIO20_LEVEL_HIGH : 1; /*!< [17..17] GPIO20_LEVEL_HIGH */ - __IOM uint32_t GPIO20_EDGE_LOW : 1; /*!< [18..18] GPIO20_EDGE_LOW */ - __IOM uint32_t GPIO20_EDGE_HIGH : 1; /*!< [19..19] GPIO20_EDGE_HIGH */ - __IOM uint32_t GPIO21_LEVEL_LOW : 1; /*!< [20..20] GPIO21_LEVEL_LOW */ - __IOM uint32_t GPIO21_LEVEL_HIGH : 1; /*!< [21..21] GPIO21_LEVEL_HIGH */ - __IOM uint32_t GPIO21_EDGE_LOW : 1; /*!< [22..22] GPIO21_EDGE_LOW */ - __IOM uint32_t GPIO21_EDGE_HIGH : 1; /*!< [23..23] GPIO21_EDGE_HIGH */ - __IOM uint32_t GPIO22_LEVEL_LOW : 1; /*!< [24..24] GPIO22_LEVEL_LOW */ - __IOM uint32_t GPIO22_LEVEL_HIGH : 1; /*!< [25..25] GPIO22_LEVEL_HIGH */ - __IOM uint32_t GPIO22_EDGE_LOW : 1; /*!< [26..26] GPIO22_EDGE_LOW */ - __IOM uint32_t GPIO22_EDGE_HIGH : 1; /*!< [27..27] GPIO22_EDGE_HIGH */ - __IOM uint32_t GPIO23_LEVEL_LOW : 1; /*!< [28..28] GPIO23_LEVEL_LOW */ - __IOM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< [29..29] GPIO23_LEVEL_HIGH */ - __IOM uint32_t GPIO23_EDGE_LOW : 1; /*!< [30..30] GPIO23_EDGE_LOW */ - __IOM uint32_t GPIO23_EDGE_HIGH : 1; /*!< [31..31] GPIO23_EDGE_HIGH */ - } bit; - } PROC1_INTE2; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000013C) Interrupt Enable for proc1 */ - - struct { - __IOM uint32_t GPIO24_LEVEL_LOW : 1; /*!< [0..0] GPIO24_LEVEL_LOW */ - __IOM uint32_t GPIO24_LEVEL_HIGH : 1; /*!< [1..1] GPIO24_LEVEL_HIGH */ - __IOM uint32_t GPIO24_EDGE_LOW : 1; /*!< [2..2] GPIO24_EDGE_LOW */ - __IOM uint32_t GPIO24_EDGE_HIGH : 1; /*!< [3..3] GPIO24_EDGE_HIGH */ - __IOM uint32_t GPIO25_LEVEL_LOW : 1; /*!< [4..4] GPIO25_LEVEL_LOW */ - __IOM uint32_t GPIO25_LEVEL_HIGH : 1; /*!< [5..5] GPIO25_LEVEL_HIGH */ - __IOM uint32_t GPIO25_EDGE_LOW : 1; /*!< [6..6] GPIO25_EDGE_LOW */ - __IOM uint32_t GPIO25_EDGE_HIGH : 1; /*!< [7..7] GPIO25_EDGE_HIGH */ - __IOM uint32_t GPIO26_LEVEL_LOW : 1; /*!< [8..8] GPIO26_LEVEL_LOW */ - __IOM uint32_t GPIO26_LEVEL_HIGH : 1; /*!< [9..9] GPIO26_LEVEL_HIGH */ - __IOM uint32_t GPIO26_EDGE_LOW : 1; /*!< [10..10] GPIO26_EDGE_LOW */ - __IOM uint32_t GPIO26_EDGE_HIGH : 1; /*!< [11..11] GPIO26_EDGE_HIGH */ - __IOM uint32_t GPIO27_LEVEL_LOW : 1; /*!< [12..12] GPIO27_LEVEL_LOW */ - __IOM uint32_t GPIO27_LEVEL_HIGH : 1; /*!< [13..13] GPIO27_LEVEL_HIGH */ - __IOM uint32_t GPIO27_EDGE_LOW : 1; /*!< [14..14] GPIO27_EDGE_LOW */ - __IOM uint32_t GPIO27_EDGE_HIGH : 1; /*!< [15..15] GPIO27_EDGE_HIGH */ - __IOM uint32_t GPIO28_LEVEL_LOW : 1; /*!< [16..16] GPIO28_LEVEL_LOW */ - __IOM uint32_t GPIO28_LEVEL_HIGH : 1; /*!< [17..17] GPIO28_LEVEL_HIGH */ - __IOM uint32_t GPIO28_EDGE_LOW : 1; /*!< [18..18] GPIO28_EDGE_LOW */ - __IOM uint32_t GPIO28_EDGE_HIGH : 1; /*!< [19..19] GPIO28_EDGE_HIGH */ - __IOM uint32_t GPIO29_LEVEL_LOW : 1; /*!< [20..20] GPIO29_LEVEL_LOW */ - __IOM uint32_t GPIO29_LEVEL_HIGH : 1; /*!< [21..21] GPIO29_LEVEL_HIGH */ - __IOM uint32_t GPIO29_EDGE_LOW : 1; /*!< [22..22] GPIO29_EDGE_LOW */ - __IOM uint32_t GPIO29_EDGE_HIGH : 1; /*!< [23..23] GPIO29_EDGE_HIGH */ - uint32_t : 8; - } bit; - } PROC1_INTE3; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000140) Interrupt Force for proc1 */ - - struct { - __IOM uint32_t GPIO0_LEVEL_LOW : 1; /*!< [0..0] GPIO0_LEVEL_LOW */ - __IOM uint32_t GPIO0_LEVEL_HIGH : 1; /*!< [1..1] GPIO0_LEVEL_HIGH */ - __IOM uint32_t GPIO0_EDGE_LOW : 1; /*!< [2..2] GPIO0_EDGE_LOW */ - __IOM uint32_t GPIO0_EDGE_HIGH : 1; /*!< [3..3] GPIO0_EDGE_HIGH */ - __IOM uint32_t GPIO1_LEVEL_LOW : 1; /*!< [4..4] GPIO1_LEVEL_LOW */ - __IOM uint32_t GPIO1_LEVEL_HIGH : 1; /*!< [5..5] GPIO1_LEVEL_HIGH */ - __IOM uint32_t GPIO1_EDGE_LOW : 1; /*!< [6..6] GPIO1_EDGE_LOW */ - __IOM uint32_t GPIO1_EDGE_HIGH : 1; /*!< [7..7] GPIO1_EDGE_HIGH */ - __IOM uint32_t GPIO2_LEVEL_LOW : 1; /*!< [8..8] GPIO2_LEVEL_LOW */ - __IOM uint32_t GPIO2_LEVEL_HIGH : 1; /*!< [9..9] GPIO2_LEVEL_HIGH */ - __IOM uint32_t GPIO2_EDGE_LOW : 1; /*!< [10..10] GPIO2_EDGE_LOW */ - __IOM uint32_t GPIO2_EDGE_HIGH : 1; /*!< [11..11] GPIO2_EDGE_HIGH */ - __IOM uint32_t GPIO3_LEVEL_LOW : 1; /*!< [12..12] GPIO3_LEVEL_LOW */ - __IOM uint32_t GPIO3_LEVEL_HIGH : 1; /*!< [13..13] GPIO3_LEVEL_HIGH */ - __IOM uint32_t GPIO3_EDGE_LOW : 1; /*!< [14..14] GPIO3_EDGE_LOW */ - __IOM uint32_t GPIO3_EDGE_HIGH : 1; /*!< [15..15] GPIO3_EDGE_HIGH */ - __IOM uint32_t GPIO4_LEVEL_LOW : 1; /*!< [16..16] GPIO4_LEVEL_LOW */ - __IOM uint32_t GPIO4_LEVEL_HIGH : 1; /*!< [17..17] GPIO4_LEVEL_HIGH */ - __IOM uint32_t GPIO4_EDGE_LOW : 1; /*!< [18..18] GPIO4_EDGE_LOW */ - __IOM uint32_t GPIO4_EDGE_HIGH : 1; /*!< [19..19] GPIO4_EDGE_HIGH */ - __IOM uint32_t GPIO5_LEVEL_LOW : 1; /*!< [20..20] GPIO5_LEVEL_LOW */ - __IOM uint32_t GPIO5_LEVEL_HIGH : 1; /*!< [21..21] GPIO5_LEVEL_HIGH */ - __IOM uint32_t GPIO5_EDGE_LOW : 1; /*!< [22..22] GPIO5_EDGE_LOW */ - __IOM uint32_t GPIO5_EDGE_HIGH : 1; /*!< [23..23] GPIO5_EDGE_HIGH */ - __IOM uint32_t GPIO6_LEVEL_LOW : 1; /*!< [24..24] GPIO6_LEVEL_LOW */ - __IOM uint32_t GPIO6_LEVEL_HIGH : 1; /*!< [25..25] GPIO6_LEVEL_HIGH */ - __IOM uint32_t GPIO6_EDGE_LOW : 1; /*!< [26..26] GPIO6_EDGE_LOW */ - __IOM uint32_t GPIO6_EDGE_HIGH : 1; /*!< [27..27] GPIO6_EDGE_HIGH */ - __IOM uint32_t GPIO7_LEVEL_LOW : 1; /*!< [28..28] GPIO7_LEVEL_LOW */ - __IOM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< [29..29] GPIO7_LEVEL_HIGH */ - __IOM uint32_t GPIO7_EDGE_LOW : 1; /*!< [30..30] GPIO7_EDGE_LOW */ - __IOM uint32_t GPIO7_EDGE_HIGH : 1; /*!< [31..31] GPIO7_EDGE_HIGH */ - } bit; - } PROC1_INTF0; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000144) Interrupt Force for proc1 */ - - struct { - __IOM uint32_t GPIO8_LEVEL_LOW : 1; /*!< [0..0] GPIO8_LEVEL_LOW */ - __IOM uint32_t GPIO8_LEVEL_HIGH : 1; /*!< [1..1] GPIO8_LEVEL_HIGH */ - __IOM uint32_t GPIO8_EDGE_LOW : 1; /*!< [2..2] GPIO8_EDGE_LOW */ - __IOM uint32_t GPIO8_EDGE_HIGH : 1; /*!< [3..3] GPIO8_EDGE_HIGH */ - __IOM uint32_t GPIO9_LEVEL_LOW : 1; /*!< [4..4] GPIO9_LEVEL_LOW */ - __IOM uint32_t GPIO9_LEVEL_HIGH : 1; /*!< [5..5] GPIO9_LEVEL_HIGH */ - __IOM uint32_t GPIO9_EDGE_LOW : 1; /*!< [6..6] GPIO9_EDGE_LOW */ - __IOM uint32_t GPIO9_EDGE_HIGH : 1; /*!< [7..7] GPIO9_EDGE_HIGH */ - __IOM uint32_t GPIO10_LEVEL_LOW : 1; /*!< [8..8] GPIO10_LEVEL_LOW */ - __IOM uint32_t GPIO10_LEVEL_HIGH : 1; /*!< [9..9] GPIO10_LEVEL_HIGH */ - __IOM uint32_t GPIO10_EDGE_LOW : 1; /*!< [10..10] GPIO10_EDGE_LOW */ - __IOM uint32_t GPIO10_EDGE_HIGH : 1; /*!< [11..11] GPIO10_EDGE_HIGH */ - __IOM uint32_t GPIO11_LEVEL_LOW : 1; /*!< [12..12] GPIO11_LEVEL_LOW */ - __IOM uint32_t GPIO11_LEVEL_HIGH : 1; /*!< [13..13] GPIO11_LEVEL_HIGH */ - __IOM uint32_t GPIO11_EDGE_LOW : 1; /*!< [14..14] GPIO11_EDGE_LOW */ - __IOM uint32_t GPIO11_EDGE_HIGH : 1; /*!< [15..15] GPIO11_EDGE_HIGH */ - __IOM uint32_t GPIO12_LEVEL_LOW : 1; /*!< [16..16] GPIO12_LEVEL_LOW */ - __IOM uint32_t GPIO12_LEVEL_HIGH : 1; /*!< [17..17] GPIO12_LEVEL_HIGH */ - __IOM uint32_t GPIO12_EDGE_LOW : 1; /*!< [18..18] GPIO12_EDGE_LOW */ - __IOM uint32_t GPIO12_EDGE_HIGH : 1; /*!< [19..19] GPIO12_EDGE_HIGH */ - __IOM uint32_t GPIO13_LEVEL_LOW : 1; /*!< [20..20] GPIO13_LEVEL_LOW */ - __IOM uint32_t GPIO13_LEVEL_HIGH : 1; /*!< [21..21] GPIO13_LEVEL_HIGH */ - __IOM uint32_t GPIO13_EDGE_LOW : 1; /*!< [22..22] GPIO13_EDGE_LOW */ - __IOM uint32_t GPIO13_EDGE_HIGH : 1; /*!< [23..23] GPIO13_EDGE_HIGH */ - __IOM uint32_t GPIO14_LEVEL_LOW : 1; /*!< [24..24] GPIO14_LEVEL_LOW */ - __IOM uint32_t GPIO14_LEVEL_HIGH : 1; /*!< [25..25] GPIO14_LEVEL_HIGH */ - __IOM uint32_t GPIO14_EDGE_LOW : 1; /*!< [26..26] GPIO14_EDGE_LOW */ - __IOM uint32_t GPIO14_EDGE_HIGH : 1; /*!< [27..27] GPIO14_EDGE_HIGH */ - __IOM uint32_t GPIO15_LEVEL_LOW : 1; /*!< [28..28] GPIO15_LEVEL_LOW */ - __IOM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< [29..29] GPIO15_LEVEL_HIGH */ - __IOM uint32_t GPIO15_EDGE_LOW : 1; /*!< [30..30] GPIO15_EDGE_LOW */ - __IOM uint32_t GPIO15_EDGE_HIGH : 1; /*!< [31..31] GPIO15_EDGE_HIGH */ - } bit; - } PROC1_INTF1; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000148) Interrupt Force for proc1 */ - - struct { - __IOM uint32_t GPIO16_LEVEL_LOW : 1; /*!< [0..0] GPIO16_LEVEL_LOW */ - __IOM uint32_t GPIO16_LEVEL_HIGH : 1; /*!< [1..1] GPIO16_LEVEL_HIGH */ - __IOM uint32_t GPIO16_EDGE_LOW : 1; /*!< [2..2] GPIO16_EDGE_LOW */ - __IOM uint32_t GPIO16_EDGE_HIGH : 1; /*!< [3..3] GPIO16_EDGE_HIGH */ - __IOM uint32_t GPIO17_LEVEL_LOW : 1; /*!< [4..4] GPIO17_LEVEL_LOW */ - __IOM uint32_t GPIO17_LEVEL_HIGH : 1; /*!< [5..5] GPIO17_LEVEL_HIGH */ - __IOM uint32_t GPIO17_EDGE_LOW : 1; /*!< [6..6] GPIO17_EDGE_LOW */ - __IOM uint32_t GPIO17_EDGE_HIGH : 1; /*!< [7..7] GPIO17_EDGE_HIGH */ - __IOM uint32_t GPIO18_LEVEL_LOW : 1; /*!< [8..8] GPIO18_LEVEL_LOW */ - __IOM uint32_t GPIO18_LEVEL_HIGH : 1; /*!< [9..9] GPIO18_LEVEL_HIGH */ - __IOM uint32_t GPIO18_EDGE_LOW : 1; /*!< [10..10] GPIO18_EDGE_LOW */ - __IOM uint32_t GPIO18_EDGE_HIGH : 1; /*!< [11..11] GPIO18_EDGE_HIGH */ - __IOM uint32_t GPIO19_LEVEL_LOW : 1; /*!< [12..12] GPIO19_LEVEL_LOW */ - __IOM uint32_t GPIO19_LEVEL_HIGH : 1; /*!< [13..13] GPIO19_LEVEL_HIGH */ - __IOM uint32_t GPIO19_EDGE_LOW : 1; /*!< [14..14] GPIO19_EDGE_LOW */ - __IOM uint32_t GPIO19_EDGE_HIGH : 1; /*!< [15..15] GPIO19_EDGE_HIGH */ - __IOM uint32_t GPIO20_LEVEL_LOW : 1; /*!< [16..16] GPIO20_LEVEL_LOW */ - __IOM uint32_t GPIO20_LEVEL_HIGH : 1; /*!< [17..17] GPIO20_LEVEL_HIGH */ - __IOM uint32_t GPIO20_EDGE_LOW : 1; /*!< [18..18] GPIO20_EDGE_LOW */ - __IOM uint32_t GPIO20_EDGE_HIGH : 1; /*!< [19..19] GPIO20_EDGE_HIGH */ - __IOM uint32_t GPIO21_LEVEL_LOW : 1; /*!< [20..20] GPIO21_LEVEL_LOW */ - __IOM uint32_t GPIO21_LEVEL_HIGH : 1; /*!< [21..21] GPIO21_LEVEL_HIGH */ - __IOM uint32_t GPIO21_EDGE_LOW : 1; /*!< [22..22] GPIO21_EDGE_LOW */ - __IOM uint32_t GPIO21_EDGE_HIGH : 1; /*!< [23..23] GPIO21_EDGE_HIGH */ - __IOM uint32_t GPIO22_LEVEL_LOW : 1; /*!< [24..24] GPIO22_LEVEL_LOW */ - __IOM uint32_t GPIO22_LEVEL_HIGH : 1; /*!< [25..25] GPIO22_LEVEL_HIGH */ - __IOM uint32_t GPIO22_EDGE_LOW : 1; /*!< [26..26] GPIO22_EDGE_LOW */ - __IOM uint32_t GPIO22_EDGE_HIGH : 1; /*!< [27..27] GPIO22_EDGE_HIGH */ - __IOM uint32_t GPIO23_LEVEL_LOW : 1; /*!< [28..28] GPIO23_LEVEL_LOW */ - __IOM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< [29..29] GPIO23_LEVEL_HIGH */ - __IOM uint32_t GPIO23_EDGE_LOW : 1; /*!< [30..30] GPIO23_EDGE_LOW */ - __IOM uint32_t GPIO23_EDGE_HIGH : 1; /*!< [31..31] GPIO23_EDGE_HIGH */ - } bit; - } PROC1_INTF2; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000014C) Interrupt Force for proc1 */ - - struct { - __IOM uint32_t GPIO24_LEVEL_LOW : 1; /*!< [0..0] GPIO24_LEVEL_LOW */ - __IOM uint32_t GPIO24_LEVEL_HIGH : 1; /*!< [1..1] GPIO24_LEVEL_HIGH */ - __IOM uint32_t GPIO24_EDGE_LOW : 1; /*!< [2..2] GPIO24_EDGE_LOW */ - __IOM uint32_t GPIO24_EDGE_HIGH : 1; /*!< [3..3] GPIO24_EDGE_HIGH */ - __IOM uint32_t GPIO25_LEVEL_LOW : 1; /*!< [4..4] GPIO25_LEVEL_LOW */ - __IOM uint32_t GPIO25_LEVEL_HIGH : 1; /*!< [5..5] GPIO25_LEVEL_HIGH */ - __IOM uint32_t GPIO25_EDGE_LOW : 1; /*!< [6..6] GPIO25_EDGE_LOW */ - __IOM uint32_t GPIO25_EDGE_HIGH : 1; /*!< [7..7] GPIO25_EDGE_HIGH */ - __IOM uint32_t GPIO26_LEVEL_LOW : 1; /*!< [8..8] GPIO26_LEVEL_LOW */ - __IOM uint32_t GPIO26_LEVEL_HIGH : 1; /*!< [9..9] GPIO26_LEVEL_HIGH */ - __IOM uint32_t GPIO26_EDGE_LOW : 1; /*!< [10..10] GPIO26_EDGE_LOW */ - __IOM uint32_t GPIO26_EDGE_HIGH : 1; /*!< [11..11] GPIO26_EDGE_HIGH */ - __IOM uint32_t GPIO27_LEVEL_LOW : 1; /*!< [12..12] GPIO27_LEVEL_LOW */ - __IOM uint32_t GPIO27_LEVEL_HIGH : 1; /*!< [13..13] GPIO27_LEVEL_HIGH */ - __IOM uint32_t GPIO27_EDGE_LOW : 1; /*!< [14..14] GPIO27_EDGE_LOW */ - __IOM uint32_t GPIO27_EDGE_HIGH : 1; /*!< [15..15] GPIO27_EDGE_HIGH */ - __IOM uint32_t GPIO28_LEVEL_LOW : 1; /*!< [16..16] GPIO28_LEVEL_LOW */ - __IOM uint32_t GPIO28_LEVEL_HIGH : 1; /*!< [17..17] GPIO28_LEVEL_HIGH */ - __IOM uint32_t GPIO28_EDGE_LOW : 1; /*!< [18..18] GPIO28_EDGE_LOW */ - __IOM uint32_t GPIO28_EDGE_HIGH : 1; /*!< [19..19] GPIO28_EDGE_HIGH */ - __IOM uint32_t GPIO29_LEVEL_LOW : 1; /*!< [20..20] GPIO29_LEVEL_LOW */ - __IOM uint32_t GPIO29_LEVEL_HIGH : 1; /*!< [21..21] GPIO29_LEVEL_HIGH */ - __IOM uint32_t GPIO29_EDGE_LOW : 1; /*!< [22..22] GPIO29_EDGE_LOW */ - __IOM uint32_t GPIO29_EDGE_HIGH : 1; /*!< [23..23] GPIO29_EDGE_HIGH */ - uint32_t : 8; - } bit; - } PROC1_INTF3; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000150) Interrupt status after masking & forcing for + __IOM uint32_t PROC1_INTE0; /*!< (@ 0x00000130) Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTE1; /*!< (@ 0x00000134) Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTE2; /*!< (@ 0x00000138) Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTE3; /*!< (@ 0x0000013C) Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTF0; /*!< (@ 0x00000140) Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTF1; /*!< (@ 0x00000144) Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTF2; /*!< (@ 0x00000148) Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTF3; /*!< (@ 0x0000014C) Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTS0; /*!< (@ 0x00000150) Interrupt status after masking & forcing for proc1 */ - - struct { - __IM uint32_t GPIO0_LEVEL_LOW : 1; /*!< [0..0] GPIO0_LEVEL_LOW */ - __IM uint32_t GPIO0_LEVEL_HIGH : 1; /*!< [1..1] GPIO0_LEVEL_HIGH */ - __IM uint32_t GPIO0_EDGE_LOW : 1; /*!< [2..2] GPIO0_EDGE_LOW */ - __IM uint32_t GPIO0_EDGE_HIGH : 1; /*!< [3..3] GPIO0_EDGE_HIGH */ - __IM uint32_t GPIO1_LEVEL_LOW : 1; /*!< [4..4] GPIO1_LEVEL_LOW */ - __IM uint32_t GPIO1_LEVEL_HIGH : 1; /*!< [5..5] GPIO1_LEVEL_HIGH */ - __IM uint32_t GPIO1_EDGE_LOW : 1; /*!< [6..6] GPIO1_EDGE_LOW */ - __IM uint32_t GPIO1_EDGE_HIGH : 1; /*!< [7..7] GPIO1_EDGE_HIGH */ - __IM uint32_t GPIO2_LEVEL_LOW : 1; /*!< [8..8] GPIO2_LEVEL_LOW */ - __IM uint32_t GPIO2_LEVEL_HIGH : 1; /*!< [9..9] GPIO2_LEVEL_HIGH */ - __IM uint32_t GPIO2_EDGE_LOW : 1; /*!< [10..10] GPIO2_EDGE_LOW */ - __IM uint32_t GPIO2_EDGE_HIGH : 1; /*!< [11..11] GPIO2_EDGE_HIGH */ - __IM uint32_t GPIO3_LEVEL_LOW : 1; /*!< [12..12] GPIO3_LEVEL_LOW */ - __IM uint32_t GPIO3_LEVEL_HIGH : 1; /*!< [13..13] GPIO3_LEVEL_HIGH */ - __IM uint32_t GPIO3_EDGE_LOW : 1; /*!< [14..14] GPIO3_EDGE_LOW */ - __IM uint32_t GPIO3_EDGE_HIGH : 1; /*!< [15..15] GPIO3_EDGE_HIGH */ - __IM uint32_t GPIO4_LEVEL_LOW : 1; /*!< [16..16] GPIO4_LEVEL_LOW */ - __IM uint32_t GPIO4_LEVEL_HIGH : 1; /*!< [17..17] GPIO4_LEVEL_HIGH */ - __IM uint32_t GPIO4_EDGE_LOW : 1; /*!< [18..18] GPIO4_EDGE_LOW */ - __IM uint32_t GPIO4_EDGE_HIGH : 1; /*!< [19..19] GPIO4_EDGE_HIGH */ - __IM uint32_t GPIO5_LEVEL_LOW : 1; /*!< [20..20] GPIO5_LEVEL_LOW */ - __IM uint32_t GPIO5_LEVEL_HIGH : 1; /*!< [21..21] GPIO5_LEVEL_HIGH */ - __IM uint32_t GPIO5_EDGE_LOW : 1; /*!< [22..22] GPIO5_EDGE_LOW */ - __IM uint32_t GPIO5_EDGE_HIGH : 1; /*!< [23..23] GPIO5_EDGE_HIGH */ - __IM uint32_t GPIO6_LEVEL_LOW : 1; /*!< [24..24] GPIO6_LEVEL_LOW */ - __IM uint32_t GPIO6_LEVEL_HIGH : 1; /*!< [25..25] GPIO6_LEVEL_HIGH */ - __IM uint32_t GPIO6_EDGE_LOW : 1; /*!< [26..26] GPIO6_EDGE_LOW */ - __IM uint32_t GPIO6_EDGE_HIGH : 1; /*!< [27..27] GPIO6_EDGE_HIGH */ - __IM uint32_t GPIO7_LEVEL_LOW : 1; /*!< [28..28] GPIO7_LEVEL_LOW */ - __IM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< [29..29] GPIO7_LEVEL_HIGH */ - __IM uint32_t GPIO7_EDGE_LOW : 1; /*!< [30..30] GPIO7_EDGE_LOW */ - __IM uint32_t GPIO7_EDGE_HIGH : 1; /*!< [31..31] GPIO7_EDGE_HIGH */ - } bit; - } PROC1_INTS0; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000154) Interrupt status after masking & forcing for + __IOM uint32_t PROC1_INTS1; /*!< (@ 0x00000154) Interrupt status after masking & forcing for proc1 */ - - struct { - __IM uint32_t GPIO8_LEVEL_LOW : 1; /*!< [0..0] GPIO8_LEVEL_LOW */ - __IM uint32_t GPIO8_LEVEL_HIGH : 1; /*!< [1..1] GPIO8_LEVEL_HIGH */ - __IM uint32_t GPIO8_EDGE_LOW : 1; /*!< [2..2] GPIO8_EDGE_LOW */ - __IM uint32_t GPIO8_EDGE_HIGH : 1; /*!< [3..3] GPIO8_EDGE_HIGH */ - __IM uint32_t GPIO9_LEVEL_LOW : 1; /*!< [4..4] GPIO9_LEVEL_LOW */ - __IM uint32_t GPIO9_LEVEL_HIGH : 1; /*!< [5..5] GPIO9_LEVEL_HIGH */ - __IM uint32_t GPIO9_EDGE_LOW : 1; /*!< [6..6] GPIO9_EDGE_LOW */ - __IM uint32_t GPIO9_EDGE_HIGH : 1; /*!< [7..7] GPIO9_EDGE_HIGH */ - __IM uint32_t GPIO10_LEVEL_LOW : 1; /*!< [8..8] GPIO10_LEVEL_LOW */ - __IM uint32_t GPIO10_LEVEL_HIGH : 1; /*!< [9..9] GPIO10_LEVEL_HIGH */ - __IM uint32_t GPIO10_EDGE_LOW : 1; /*!< [10..10] GPIO10_EDGE_LOW */ - __IM uint32_t GPIO10_EDGE_HIGH : 1; /*!< [11..11] GPIO10_EDGE_HIGH */ - __IM uint32_t GPIO11_LEVEL_LOW : 1; /*!< [12..12] GPIO11_LEVEL_LOW */ - __IM uint32_t GPIO11_LEVEL_HIGH : 1; /*!< [13..13] GPIO11_LEVEL_HIGH */ - __IM uint32_t GPIO11_EDGE_LOW : 1; /*!< [14..14] GPIO11_EDGE_LOW */ - __IM uint32_t GPIO11_EDGE_HIGH : 1; /*!< [15..15] GPIO11_EDGE_HIGH */ - __IM uint32_t GPIO12_LEVEL_LOW : 1; /*!< [16..16] GPIO12_LEVEL_LOW */ - __IM uint32_t GPIO12_LEVEL_HIGH : 1; /*!< [17..17] GPIO12_LEVEL_HIGH */ - __IM uint32_t GPIO12_EDGE_LOW : 1; /*!< [18..18] GPIO12_EDGE_LOW */ - __IM uint32_t GPIO12_EDGE_HIGH : 1; /*!< [19..19] GPIO12_EDGE_HIGH */ - __IM uint32_t GPIO13_LEVEL_LOW : 1; /*!< [20..20] GPIO13_LEVEL_LOW */ - __IM uint32_t GPIO13_LEVEL_HIGH : 1; /*!< [21..21] GPIO13_LEVEL_HIGH */ - __IM uint32_t GPIO13_EDGE_LOW : 1; /*!< [22..22] GPIO13_EDGE_LOW */ - __IM uint32_t GPIO13_EDGE_HIGH : 1; /*!< [23..23] GPIO13_EDGE_HIGH */ - __IM uint32_t GPIO14_LEVEL_LOW : 1; /*!< [24..24] GPIO14_LEVEL_LOW */ - __IM uint32_t GPIO14_LEVEL_HIGH : 1; /*!< [25..25] GPIO14_LEVEL_HIGH */ - __IM uint32_t GPIO14_EDGE_LOW : 1; /*!< [26..26] GPIO14_EDGE_LOW */ - __IM uint32_t GPIO14_EDGE_HIGH : 1; /*!< [27..27] GPIO14_EDGE_HIGH */ - __IM uint32_t GPIO15_LEVEL_LOW : 1; /*!< [28..28] GPIO15_LEVEL_LOW */ - __IM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< [29..29] GPIO15_LEVEL_HIGH */ - __IM uint32_t GPIO15_EDGE_LOW : 1; /*!< [30..30] GPIO15_EDGE_LOW */ - __IM uint32_t GPIO15_EDGE_HIGH : 1; /*!< [31..31] GPIO15_EDGE_HIGH */ - } bit; - } PROC1_INTS1; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000158) Interrupt status after masking & forcing for + __IOM uint32_t PROC1_INTS2; /*!< (@ 0x00000158) Interrupt status after masking & forcing for proc1 */ - - struct { - __IM uint32_t GPIO16_LEVEL_LOW : 1; /*!< [0..0] GPIO16_LEVEL_LOW */ - __IM uint32_t GPIO16_LEVEL_HIGH : 1; /*!< [1..1] GPIO16_LEVEL_HIGH */ - __IM uint32_t GPIO16_EDGE_LOW : 1; /*!< [2..2] GPIO16_EDGE_LOW */ - __IM uint32_t GPIO16_EDGE_HIGH : 1; /*!< [3..3] GPIO16_EDGE_HIGH */ - __IM uint32_t GPIO17_LEVEL_LOW : 1; /*!< [4..4] GPIO17_LEVEL_LOW */ - __IM uint32_t GPIO17_LEVEL_HIGH : 1; /*!< [5..5] GPIO17_LEVEL_HIGH */ - __IM uint32_t GPIO17_EDGE_LOW : 1; /*!< [6..6] GPIO17_EDGE_LOW */ - __IM uint32_t GPIO17_EDGE_HIGH : 1; /*!< [7..7] GPIO17_EDGE_HIGH */ - __IM uint32_t GPIO18_LEVEL_LOW : 1; /*!< [8..8] GPIO18_LEVEL_LOW */ - __IM uint32_t GPIO18_LEVEL_HIGH : 1; /*!< [9..9] GPIO18_LEVEL_HIGH */ - __IM uint32_t GPIO18_EDGE_LOW : 1; /*!< [10..10] GPIO18_EDGE_LOW */ - __IM uint32_t GPIO18_EDGE_HIGH : 1; /*!< [11..11] GPIO18_EDGE_HIGH */ - __IM uint32_t GPIO19_LEVEL_LOW : 1; /*!< [12..12] GPIO19_LEVEL_LOW */ - __IM uint32_t GPIO19_LEVEL_HIGH : 1; /*!< [13..13] GPIO19_LEVEL_HIGH */ - __IM uint32_t GPIO19_EDGE_LOW : 1; /*!< [14..14] GPIO19_EDGE_LOW */ - __IM uint32_t GPIO19_EDGE_HIGH : 1; /*!< [15..15] GPIO19_EDGE_HIGH */ - __IM uint32_t GPIO20_LEVEL_LOW : 1; /*!< [16..16] GPIO20_LEVEL_LOW */ - __IM uint32_t GPIO20_LEVEL_HIGH : 1; /*!< [17..17] GPIO20_LEVEL_HIGH */ - __IM uint32_t GPIO20_EDGE_LOW : 1; /*!< [18..18] GPIO20_EDGE_LOW */ - __IM uint32_t GPIO20_EDGE_HIGH : 1; /*!< [19..19] GPIO20_EDGE_HIGH */ - __IM uint32_t GPIO21_LEVEL_LOW : 1; /*!< [20..20] GPIO21_LEVEL_LOW */ - __IM uint32_t GPIO21_LEVEL_HIGH : 1; /*!< [21..21] GPIO21_LEVEL_HIGH */ - __IM uint32_t GPIO21_EDGE_LOW : 1; /*!< [22..22] GPIO21_EDGE_LOW */ - __IM uint32_t GPIO21_EDGE_HIGH : 1; /*!< [23..23] GPIO21_EDGE_HIGH */ - __IM uint32_t GPIO22_LEVEL_LOW : 1; /*!< [24..24] GPIO22_LEVEL_LOW */ - __IM uint32_t GPIO22_LEVEL_HIGH : 1; /*!< [25..25] GPIO22_LEVEL_HIGH */ - __IM uint32_t GPIO22_EDGE_LOW : 1; /*!< [26..26] GPIO22_EDGE_LOW */ - __IM uint32_t GPIO22_EDGE_HIGH : 1; /*!< [27..27] GPIO22_EDGE_HIGH */ - __IM uint32_t GPIO23_LEVEL_LOW : 1; /*!< [28..28] GPIO23_LEVEL_LOW */ - __IM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< [29..29] GPIO23_LEVEL_HIGH */ - __IM uint32_t GPIO23_EDGE_LOW : 1; /*!< [30..30] GPIO23_EDGE_LOW */ - __IM uint32_t GPIO23_EDGE_HIGH : 1; /*!< [31..31] GPIO23_EDGE_HIGH */ - } bit; - } PROC1_INTS2; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000015C) Interrupt status after masking & forcing for + __IOM uint32_t PROC1_INTS3; /*!< (@ 0x0000015C) Interrupt status after masking & forcing for proc1 */ - - struct { - __IM uint32_t GPIO24_LEVEL_LOW : 1; /*!< [0..0] GPIO24_LEVEL_LOW */ - __IM uint32_t GPIO24_LEVEL_HIGH : 1; /*!< [1..1] GPIO24_LEVEL_HIGH */ - __IM uint32_t GPIO24_EDGE_LOW : 1; /*!< [2..2] GPIO24_EDGE_LOW */ - __IM uint32_t GPIO24_EDGE_HIGH : 1; /*!< [3..3] GPIO24_EDGE_HIGH */ - __IM uint32_t GPIO25_LEVEL_LOW : 1; /*!< [4..4] GPIO25_LEVEL_LOW */ - __IM uint32_t GPIO25_LEVEL_HIGH : 1; /*!< [5..5] GPIO25_LEVEL_HIGH */ - __IM uint32_t GPIO25_EDGE_LOW : 1; /*!< [6..6] GPIO25_EDGE_LOW */ - __IM uint32_t GPIO25_EDGE_HIGH : 1; /*!< [7..7] GPIO25_EDGE_HIGH */ - __IM uint32_t GPIO26_LEVEL_LOW : 1; /*!< [8..8] GPIO26_LEVEL_LOW */ - __IM uint32_t GPIO26_LEVEL_HIGH : 1; /*!< [9..9] GPIO26_LEVEL_HIGH */ - __IM uint32_t GPIO26_EDGE_LOW : 1; /*!< [10..10] GPIO26_EDGE_LOW */ - __IM uint32_t GPIO26_EDGE_HIGH : 1; /*!< [11..11] GPIO26_EDGE_HIGH */ - __IM uint32_t GPIO27_LEVEL_LOW : 1; /*!< [12..12] GPIO27_LEVEL_LOW */ - __IM uint32_t GPIO27_LEVEL_HIGH : 1; /*!< [13..13] GPIO27_LEVEL_HIGH */ - __IM uint32_t GPIO27_EDGE_LOW : 1; /*!< [14..14] GPIO27_EDGE_LOW */ - __IM uint32_t GPIO27_EDGE_HIGH : 1; /*!< [15..15] GPIO27_EDGE_HIGH */ - __IM uint32_t GPIO28_LEVEL_LOW : 1; /*!< [16..16] GPIO28_LEVEL_LOW */ - __IM uint32_t GPIO28_LEVEL_HIGH : 1; /*!< [17..17] GPIO28_LEVEL_HIGH */ - __IM uint32_t GPIO28_EDGE_LOW : 1; /*!< [18..18] GPIO28_EDGE_LOW */ - __IM uint32_t GPIO28_EDGE_HIGH : 1; /*!< [19..19] GPIO28_EDGE_HIGH */ - __IM uint32_t GPIO29_LEVEL_LOW : 1; /*!< [20..20] GPIO29_LEVEL_LOW */ - __IM uint32_t GPIO29_LEVEL_HIGH : 1; /*!< [21..21] GPIO29_LEVEL_HIGH */ - __IM uint32_t GPIO29_EDGE_LOW : 1; /*!< [22..22] GPIO29_EDGE_LOW */ - __IM uint32_t GPIO29_EDGE_HIGH : 1; /*!< [23..23] GPIO29_EDGE_HIGH */ - uint32_t : 8; - } bit; - } PROC1_INTS3; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000160) Interrupt Enable for dormant_wake */ - - struct { - __IOM uint32_t GPIO0_LEVEL_LOW : 1; /*!< [0..0] GPIO0_LEVEL_LOW */ - __IOM uint32_t GPIO0_LEVEL_HIGH : 1; /*!< [1..1] GPIO0_LEVEL_HIGH */ - __IOM uint32_t GPIO0_EDGE_LOW : 1; /*!< [2..2] GPIO0_EDGE_LOW */ - __IOM uint32_t GPIO0_EDGE_HIGH : 1; /*!< [3..3] GPIO0_EDGE_HIGH */ - __IOM uint32_t GPIO1_LEVEL_LOW : 1; /*!< [4..4] GPIO1_LEVEL_LOW */ - __IOM uint32_t GPIO1_LEVEL_HIGH : 1; /*!< [5..5] GPIO1_LEVEL_HIGH */ - __IOM uint32_t GPIO1_EDGE_LOW : 1; /*!< [6..6] GPIO1_EDGE_LOW */ - __IOM uint32_t GPIO1_EDGE_HIGH : 1; /*!< [7..7] GPIO1_EDGE_HIGH */ - __IOM uint32_t GPIO2_LEVEL_LOW : 1; /*!< [8..8] GPIO2_LEVEL_LOW */ - __IOM uint32_t GPIO2_LEVEL_HIGH : 1; /*!< [9..9] GPIO2_LEVEL_HIGH */ - __IOM uint32_t GPIO2_EDGE_LOW : 1; /*!< [10..10] GPIO2_EDGE_LOW */ - __IOM uint32_t GPIO2_EDGE_HIGH : 1; /*!< [11..11] GPIO2_EDGE_HIGH */ - __IOM uint32_t GPIO3_LEVEL_LOW : 1; /*!< [12..12] GPIO3_LEVEL_LOW */ - __IOM uint32_t GPIO3_LEVEL_HIGH : 1; /*!< [13..13] GPIO3_LEVEL_HIGH */ - __IOM uint32_t GPIO3_EDGE_LOW : 1; /*!< [14..14] GPIO3_EDGE_LOW */ - __IOM uint32_t GPIO3_EDGE_HIGH : 1; /*!< [15..15] GPIO3_EDGE_HIGH */ - __IOM uint32_t GPIO4_LEVEL_LOW : 1; /*!< [16..16] GPIO4_LEVEL_LOW */ - __IOM uint32_t GPIO4_LEVEL_HIGH : 1; /*!< [17..17] GPIO4_LEVEL_HIGH */ - __IOM uint32_t GPIO4_EDGE_LOW : 1; /*!< [18..18] GPIO4_EDGE_LOW */ - __IOM uint32_t GPIO4_EDGE_HIGH : 1; /*!< [19..19] GPIO4_EDGE_HIGH */ - __IOM uint32_t GPIO5_LEVEL_LOW : 1; /*!< [20..20] GPIO5_LEVEL_LOW */ - __IOM uint32_t GPIO5_LEVEL_HIGH : 1; /*!< [21..21] GPIO5_LEVEL_HIGH */ - __IOM uint32_t GPIO5_EDGE_LOW : 1; /*!< [22..22] GPIO5_EDGE_LOW */ - __IOM uint32_t GPIO5_EDGE_HIGH : 1; /*!< [23..23] GPIO5_EDGE_HIGH */ - __IOM uint32_t GPIO6_LEVEL_LOW : 1; /*!< [24..24] GPIO6_LEVEL_LOW */ - __IOM uint32_t GPIO6_LEVEL_HIGH : 1; /*!< [25..25] GPIO6_LEVEL_HIGH */ - __IOM uint32_t GPIO6_EDGE_LOW : 1; /*!< [26..26] GPIO6_EDGE_LOW */ - __IOM uint32_t GPIO6_EDGE_HIGH : 1; /*!< [27..27] GPIO6_EDGE_HIGH */ - __IOM uint32_t GPIO7_LEVEL_LOW : 1; /*!< [28..28] GPIO7_LEVEL_LOW */ - __IOM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< [29..29] GPIO7_LEVEL_HIGH */ - __IOM uint32_t GPIO7_EDGE_LOW : 1; /*!< [30..30] GPIO7_EDGE_LOW */ - __IOM uint32_t GPIO7_EDGE_HIGH : 1; /*!< [31..31] GPIO7_EDGE_HIGH */ - } bit; - } DORMANT_WAKE_INTE0; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000164) Interrupt Enable for dormant_wake */ - - struct { - __IOM uint32_t GPIO8_LEVEL_LOW : 1; /*!< [0..0] GPIO8_LEVEL_LOW */ - __IOM uint32_t GPIO8_LEVEL_HIGH : 1; /*!< [1..1] GPIO8_LEVEL_HIGH */ - __IOM uint32_t GPIO8_EDGE_LOW : 1; /*!< [2..2] GPIO8_EDGE_LOW */ - __IOM uint32_t GPIO8_EDGE_HIGH : 1; /*!< [3..3] GPIO8_EDGE_HIGH */ - __IOM uint32_t GPIO9_LEVEL_LOW : 1; /*!< [4..4] GPIO9_LEVEL_LOW */ - __IOM uint32_t GPIO9_LEVEL_HIGH : 1; /*!< [5..5] GPIO9_LEVEL_HIGH */ - __IOM uint32_t GPIO9_EDGE_LOW : 1; /*!< [6..6] GPIO9_EDGE_LOW */ - __IOM uint32_t GPIO9_EDGE_HIGH : 1; /*!< [7..7] GPIO9_EDGE_HIGH */ - __IOM uint32_t GPIO10_LEVEL_LOW : 1; /*!< [8..8] GPIO10_LEVEL_LOW */ - __IOM uint32_t GPIO10_LEVEL_HIGH : 1; /*!< [9..9] GPIO10_LEVEL_HIGH */ - __IOM uint32_t GPIO10_EDGE_LOW : 1; /*!< [10..10] GPIO10_EDGE_LOW */ - __IOM uint32_t GPIO10_EDGE_HIGH : 1; /*!< [11..11] GPIO10_EDGE_HIGH */ - __IOM uint32_t GPIO11_LEVEL_LOW : 1; /*!< [12..12] GPIO11_LEVEL_LOW */ - __IOM uint32_t GPIO11_LEVEL_HIGH : 1; /*!< [13..13] GPIO11_LEVEL_HIGH */ - __IOM uint32_t GPIO11_EDGE_LOW : 1; /*!< [14..14] GPIO11_EDGE_LOW */ - __IOM uint32_t GPIO11_EDGE_HIGH : 1; /*!< [15..15] GPIO11_EDGE_HIGH */ - __IOM uint32_t GPIO12_LEVEL_LOW : 1; /*!< [16..16] GPIO12_LEVEL_LOW */ - __IOM uint32_t GPIO12_LEVEL_HIGH : 1; /*!< [17..17] GPIO12_LEVEL_HIGH */ - __IOM uint32_t GPIO12_EDGE_LOW : 1; /*!< [18..18] GPIO12_EDGE_LOW */ - __IOM uint32_t GPIO12_EDGE_HIGH : 1; /*!< [19..19] GPIO12_EDGE_HIGH */ - __IOM uint32_t GPIO13_LEVEL_LOW : 1; /*!< [20..20] GPIO13_LEVEL_LOW */ - __IOM uint32_t GPIO13_LEVEL_HIGH : 1; /*!< [21..21] GPIO13_LEVEL_HIGH */ - __IOM uint32_t GPIO13_EDGE_LOW : 1; /*!< [22..22] GPIO13_EDGE_LOW */ - __IOM uint32_t GPIO13_EDGE_HIGH : 1; /*!< [23..23] GPIO13_EDGE_HIGH */ - __IOM uint32_t GPIO14_LEVEL_LOW : 1; /*!< [24..24] GPIO14_LEVEL_LOW */ - __IOM uint32_t GPIO14_LEVEL_HIGH : 1; /*!< [25..25] GPIO14_LEVEL_HIGH */ - __IOM uint32_t GPIO14_EDGE_LOW : 1; /*!< [26..26] GPIO14_EDGE_LOW */ - __IOM uint32_t GPIO14_EDGE_HIGH : 1; /*!< [27..27] GPIO14_EDGE_HIGH */ - __IOM uint32_t GPIO15_LEVEL_LOW : 1; /*!< [28..28] GPIO15_LEVEL_LOW */ - __IOM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< [29..29] GPIO15_LEVEL_HIGH */ - __IOM uint32_t GPIO15_EDGE_LOW : 1; /*!< [30..30] GPIO15_EDGE_LOW */ - __IOM uint32_t GPIO15_EDGE_HIGH : 1; /*!< [31..31] GPIO15_EDGE_HIGH */ - } bit; - } DORMANT_WAKE_INTE1; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000168) Interrupt Enable for dormant_wake */ - - struct { - __IOM uint32_t GPIO16_LEVEL_LOW : 1; /*!< [0..0] GPIO16_LEVEL_LOW */ - __IOM uint32_t GPIO16_LEVEL_HIGH : 1; /*!< [1..1] GPIO16_LEVEL_HIGH */ - __IOM uint32_t GPIO16_EDGE_LOW : 1; /*!< [2..2] GPIO16_EDGE_LOW */ - __IOM uint32_t GPIO16_EDGE_HIGH : 1; /*!< [3..3] GPIO16_EDGE_HIGH */ - __IOM uint32_t GPIO17_LEVEL_LOW : 1; /*!< [4..4] GPIO17_LEVEL_LOW */ - __IOM uint32_t GPIO17_LEVEL_HIGH : 1; /*!< [5..5] GPIO17_LEVEL_HIGH */ - __IOM uint32_t GPIO17_EDGE_LOW : 1; /*!< [6..6] GPIO17_EDGE_LOW */ - __IOM uint32_t GPIO17_EDGE_HIGH : 1; /*!< [7..7] GPIO17_EDGE_HIGH */ - __IOM uint32_t GPIO18_LEVEL_LOW : 1; /*!< [8..8] GPIO18_LEVEL_LOW */ - __IOM uint32_t GPIO18_LEVEL_HIGH : 1; /*!< [9..9] GPIO18_LEVEL_HIGH */ - __IOM uint32_t GPIO18_EDGE_LOW : 1; /*!< [10..10] GPIO18_EDGE_LOW */ - __IOM uint32_t GPIO18_EDGE_HIGH : 1; /*!< [11..11] GPIO18_EDGE_HIGH */ - __IOM uint32_t GPIO19_LEVEL_LOW : 1; /*!< [12..12] GPIO19_LEVEL_LOW */ - __IOM uint32_t GPIO19_LEVEL_HIGH : 1; /*!< [13..13] GPIO19_LEVEL_HIGH */ - __IOM uint32_t GPIO19_EDGE_LOW : 1; /*!< [14..14] GPIO19_EDGE_LOW */ - __IOM uint32_t GPIO19_EDGE_HIGH : 1; /*!< [15..15] GPIO19_EDGE_HIGH */ - __IOM uint32_t GPIO20_LEVEL_LOW : 1; /*!< [16..16] GPIO20_LEVEL_LOW */ - __IOM uint32_t GPIO20_LEVEL_HIGH : 1; /*!< [17..17] GPIO20_LEVEL_HIGH */ - __IOM uint32_t GPIO20_EDGE_LOW : 1; /*!< [18..18] GPIO20_EDGE_LOW */ - __IOM uint32_t GPIO20_EDGE_HIGH : 1; /*!< [19..19] GPIO20_EDGE_HIGH */ - __IOM uint32_t GPIO21_LEVEL_LOW : 1; /*!< [20..20] GPIO21_LEVEL_LOW */ - __IOM uint32_t GPIO21_LEVEL_HIGH : 1; /*!< [21..21] GPIO21_LEVEL_HIGH */ - __IOM uint32_t GPIO21_EDGE_LOW : 1; /*!< [22..22] GPIO21_EDGE_LOW */ - __IOM uint32_t GPIO21_EDGE_HIGH : 1; /*!< [23..23] GPIO21_EDGE_HIGH */ - __IOM uint32_t GPIO22_LEVEL_LOW : 1; /*!< [24..24] GPIO22_LEVEL_LOW */ - __IOM uint32_t GPIO22_LEVEL_HIGH : 1; /*!< [25..25] GPIO22_LEVEL_HIGH */ - __IOM uint32_t GPIO22_EDGE_LOW : 1; /*!< [26..26] GPIO22_EDGE_LOW */ - __IOM uint32_t GPIO22_EDGE_HIGH : 1; /*!< [27..27] GPIO22_EDGE_HIGH */ - __IOM uint32_t GPIO23_LEVEL_LOW : 1; /*!< [28..28] GPIO23_LEVEL_LOW */ - __IOM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< [29..29] GPIO23_LEVEL_HIGH */ - __IOM uint32_t GPIO23_EDGE_LOW : 1; /*!< [30..30] GPIO23_EDGE_LOW */ - __IOM uint32_t GPIO23_EDGE_HIGH : 1; /*!< [31..31] GPIO23_EDGE_HIGH */ - } bit; - } DORMANT_WAKE_INTE2; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000016C) Interrupt Enable for dormant_wake */ - - struct { - __IOM uint32_t GPIO24_LEVEL_LOW : 1; /*!< [0..0] GPIO24_LEVEL_LOW */ - __IOM uint32_t GPIO24_LEVEL_HIGH : 1; /*!< [1..1] GPIO24_LEVEL_HIGH */ - __IOM uint32_t GPIO24_EDGE_LOW : 1; /*!< [2..2] GPIO24_EDGE_LOW */ - __IOM uint32_t GPIO24_EDGE_HIGH : 1; /*!< [3..3] GPIO24_EDGE_HIGH */ - __IOM uint32_t GPIO25_LEVEL_LOW : 1; /*!< [4..4] GPIO25_LEVEL_LOW */ - __IOM uint32_t GPIO25_LEVEL_HIGH : 1; /*!< [5..5] GPIO25_LEVEL_HIGH */ - __IOM uint32_t GPIO25_EDGE_LOW : 1; /*!< [6..6] GPIO25_EDGE_LOW */ - __IOM uint32_t GPIO25_EDGE_HIGH : 1; /*!< [7..7] GPIO25_EDGE_HIGH */ - __IOM uint32_t GPIO26_LEVEL_LOW : 1; /*!< [8..8] GPIO26_LEVEL_LOW */ - __IOM uint32_t GPIO26_LEVEL_HIGH : 1; /*!< [9..9] GPIO26_LEVEL_HIGH */ - __IOM uint32_t GPIO26_EDGE_LOW : 1; /*!< [10..10] GPIO26_EDGE_LOW */ - __IOM uint32_t GPIO26_EDGE_HIGH : 1; /*!< [11..11] GPIO26_EDGE_HIGH */ - __IOM uint32_t GPIO27_LEVEL_LOW : 1; /*!< [12..12] GPIO27_LEVEL_LOW */ - __IOM uint32_t GPIO27_LEVEL_HIGH : 1; /*!< [13..13] GPIO27_LEVEL_HIGH */ - __IOM uint32_t GPIO27_EDGE_LOW : 1; /*!< [14..14] GPIO27_EDGE_LOW */ - __IOM uint32_t GPIO27_EDGE_HIGH : 1; /*!< [15..15] GPIO27_EDGE_HIGH */ - __IOM uint32_t GPIO28_LEVEL_LOW : 1; /*!< [16..16] GPIO28_LEVEL_LOW */ - __IOM uint32_t GPIO28_LEVEL_HIGH : 1; /*!< [17..17] GPIO28_LEVEL_HIGH */ - __IOM uint32_t GPIO28_EDGE_LOW : 1; /*!< [18..18] GPIO28_EDGE_LOW */ - __IOM uint32_t GPIO28_EDGE_HIGH : 1; /*!< [19..19] GPIO28_EDGE_HIGH */ - __IOM uint32_t GPIO29_LEVEL_LOW : 1; /*!< [20..20] GPIO29_LEVEL_LOW */ - __IOM uint32_t GPIO29_LEVEL_HIGH : 1; /*!< [21..21] GPIO29_LEVEL_HIGH */ - __IOM uint32_t GPIO29_EDGE_LOW : 1; /*!< [22..22] GPIO29_EDGE_LOW */ - __IOM uint32_t GPIO29_EDGE_HIGH : 1; /*!< [23..23] GPIO29_EDGE_HIGH */ - uint32_t : 8; - } bit; - } DORMANT_WAKE_INTE3; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000170) Interrupt Force for dormant_wake */ - - struct { - __IOM uint32_t GPIO0_LEVEL_LOW : 1; /*!< [0..0] GPIO0_LEVEL_LOW */ - __IOM uint32_t GPIO0_LEVEL_HIGH : 1; /*!< [1..1] GPIO0_LEVEL_HIGH */ - __IOM uint32_t GPIO0_EDGE_LOW : 1; /*!< [2..2] GPIO0_EDGE_LOW */ - __IOM uint32_t GPIO0_EDGE_HIGH : 1; /*!< [3..3] GPIO0_EDGE_HIGH */ - __IOM uint32_t GPIO1_LEVEL_LOW : 1; /*!< [4..4] GPIO1_LEVEL_LOW */ - __IOM uint32_t GPIO1_LEVEL_HIGH : 1; /*!< [5..5] GPIO1_LEVEL_HIGH */ - __IOM uint32_t GPIO1_EDGE_LOW : 1; /*!< [6..6] GPIO1_EDGE_LOW */ - __IOM uint32_t GPIO1_EDGE_HIGH : 1; /*!< [7..7] GPIO1_EDGE_HIGH */ - __IOM uint32_t GPIO2_LEVEL_LOW : 1; /*!< [8..8] GPIO2_LEVEL_LOW */ - __IOM uint32_t GPIO2_LEVEL_HIGH : 1; /*!< [9..9] GPIO2_LEVEL_HIGH */ - __IOM uint32_t GPIO2_EDGE_LOW : 1; /*!< [10..10] GPIO2_EDGE_LOW */ - __IOM uint32_t GPIO2_EDGE_HIGH : 1; /*!< [11..11] GPIO2_EDGE_HIGH */ - __IOM uint32_t GPIO3_LEVEL_LOW : 1; /*!< [12..12] GPIO3_LEVEL_LOW */ - __IOM uint32_t GPIO3_LEVEL_HIGH : 1; /*!< [13..13] GPIO3_LEVEL_HIGH */ - __IOM uint32_t GPIO3_EDGE_LOW : 1; /*!< [14..14] GPIO3_EDGE_LOW */ - __IOM uint32_t GPIO3_EDGE_HIGH : 1; /*!< [15..15] GPIO3_EDGE_HIGH */ - __IOM uint32_t GPIO4_LEVEL_LOW : 1; /*!< [16..16] GPIO4_LEVEL_LOW */ - __IOM uint32_t GPIO4_LEVEL_HIGH : 1; /*!< [17..17] GPIO4_LEVEL_HIGH */ - __IOM uint32_t GPIO4_EDGE_LOW : 1; /*!< [18..18] GPIO4_EDGE_LOW */ - __IOM uint32_t GPIO4_EDGE_HIGH : 1; /*!< [19..19] GPIO4_EDGE_HIGH */ - __IOM uint32_t GPIO5_LEVEL_LOW : 1; /*!< [20..20] GPIO5_LEVEL_LOW */ - __IOM uint32_t GPIO5_LEVEL_HIGH : 1; /*!< [21..21] GPIO5_LEVEL_HIGH */ - __IOM uint32_t GPIO5_EDGE_LOW : 1; /*!< [22..22] GPIO5_EDGE_LOW */ - __IOM uint32_t GPIO5_EDGE_HIGH : 1; /*!< [23..23] GPIO5_EDGE_HIGH */ - __IOM uint32_t GPIO6_LEVEL_LOW : 1; /*!< [24..24] GPIO6_LEVEL_LOW */ - __IOM uint32_t GPIO6_LEVEL_HIGH : 1; /*!< [25..25] GPIO6_LEVEL_HIGH */ - __IOM uint32_t GPIO6_EDGE_LOW : 1; /*!< [26..26] GPIO6_EDGE_LOW */ - __IOM uint32_t GPIO6_EDGE_HIGH : 1; /*!< [27..27] GPIO6_EDGE_HIGH */ - __IOM uint32_t GPIO7_LEVEL_LOW : 1; /*!< [28..28] GPIO7_LEVEL_LOW */ - __IOM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< [29..29] GPIO7_LEVEL_HIGH */ - __IOM uint32_t GPIO7_EDGE_LOW : 1; /*!< [30..30] GPIO7_EDGE_LOW */ - __IOM uint32_t GPIO7_EDGE_HIGH : 1; /*!< [31..31] GPIO7_EDGE_HIGH */ - } bit; - } DORMANT_WAKE_INTF0; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000174) Interrupt Force for dormant_wake */ - - struct { - __IOM uint32_t GPIO8_LEVEL_LOW : 1; /*!< [0..0] GPIO8_LEVEL_LOW */ - __IOM uint32_t GPIO8_LEVEL_HIGH : 1; /*!< [1..1] GPIO8_LEVEL_HIGH */ - __IOM uint32_t GPIO8_EDGE_LOW : 1; /*!< [2..2] GPIO8_EDGE_LOW */ - __IOM uint32_t GPIO8_EDGE_HIGH : 1; /*!< [3..3] GPIO8_EDGE_HIGH */ - __IOM uint32_t GPIO9_LEVEL_LOW : 1; /*!< [4..4] GPIO9_LEVEL_LOW */ - __IOM uint32_t GPIO9_LEVEL_HIGH : 1; /*!< [5..5] GPIO9_LEVEL_HIGH */ - __IOM uint32_t GPIO9_EDGE_LOW : 1; /*!< [6..6] GPIO9_EDGE_LOW */ - __IOM uint32_t GPIO9_EDGE_HIGH : 1; /*!< [7..7] GPIO9_EDGE_HIGH */ - __IOM uint32_t GPIO10_LEVEL_LOW : 1; /*!< [8..8] GPIO10_LEVEL_LOW */ - __IOM uint32_t GPIO10_LEVEL_HIGH : 1; /*!< [9..9] GPIO10_LEVEL_HIGH */ - __IOM uint32_t GPIO10_EDGE_LOW : 1; /*!< [10..10] GPIO10_EDGE_LOW */ - __IOM uint32_t GPIO10_EDGE_HIGH : 1; /*!< [11..11] GPIO10_EDGE_HIGH */ - __IOM uint32_t GPIO11_LEVEL_LOW : 1; /*!< [12..12] GPIO11_LEVEL_LOW */ - __IOM uint32_t GPIO11_LEVEL_HIGH : 1; /*!< [13..13] GPIO11_LEVEL_HIGH */ - __IOM uint32_t GPIO11_EDGE_LOW : 1; /*!< [14..14] GPIO11_EDGE_LOW */ - __IOM uint32_t GPIO11_EDGE_HIGH : 1; /*!< [15..15] GPIO11_EDGE_HIGH */ - __IOM uint32_t GPIO12_LEVEL_LOW : 1; /*!< [16..16] GPIO12_LEVEL_LOW */ - __IOM uint32_t GPIO12_LEVEL_HIGH : 1; /*!< [17..17] GPIO12_LEVEL_HIGH */ - __IOM uint32_t GPIO12_EDGE_LOW : 1; /*!< [18..18] GPIO12_EDGE_LOW */ - __IOM uint32_t GPIO12_EDGE_HIGH : 1; /*!< [19..19] GPIO12_EDGE_HIGH */ - __IOM uint32_t GPIO13_LEVEL_LOW : 1; /*!< [20..20] GPIO13_LEVEL_LOW */ - __IOM uint32_t GPIO13_LEVEL_HIGH : 1; /*!< [21..21] GPIO13_LEVEL_HIGH */ - __IOM uint32_t GPIO13_EDGE_LOW : 1; /*!< [22..22] GPIO13_EDGE_LOW */ - __IOM uint32_t GPIO13_EDGE_HIGH : 1; /*!< [23..23] GPIO13_EDGE_HIGH */ - __IOM uint32_t GPIO14_LEVEL_LOW : 1; /*!< [24..24] GPIO14_LEVEL_LOW */ - __IOM uint32_t GPIO14_LEVEL_HIGH : 1; /*!< [25..25] GPIO14_LEVEL_HIGH */ - __IOM uint32_t GPIO14_EDGE_LOW : 1; /*!< [26..26] GPIO14_EDGE_LOW */ - __IOM uint32_t GPIO14_EDGE_HIGH : 1; /*!< [27..27] GPIO14_EDGE_HIGH */ - __IOM uint32_t GPIO15_LEVEL_LOW : 1; /*!< [28..28] GPIO15_LEVEL_LOW */ - __IOM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< [29..29] GPIO15_LEVEL_HIGH */ - __IOM uint32_t GPIO15_EDGE_LOW : 1; /*!< [30..30] GPIO15_EDGE_LOW */ - __IOM uint32_t GPIO15_EDGE_HIGH : 1; /*!< [31..31] GPIO15_EDGE_HIGH */ - } bit; - } DORMANT_WAKE_INTF1; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000178) Interrupt Force for dormant_wake */ - - struct { - __IOM uint32_t GPIO16_LEVEL_LOW : 1; /*!< [0..0] GPIO16_LEVEL_LOW */ - __IOM uint32_t GPIO16_LEVEL_HIGH : 1; /*!< [1..1] GPIO16_LEVEL_HIGH */ - __IOM uint32_t GPIO16_EDGE_LOW : 1; /*!< [2..2] GPIO16_EDGE_LOW */ - __IOM uint32_t GPIO16_EDGE_HIGH : 1; /*!< [3..3] GPIO16_EDGE_HIGH */ - __IOM uint32_t GPIO17_LEVEL_LOW : 1; /*!< [4..4] GPIO17_LEVEL_LOW */ - __IOM uint32_t GPIO17_LEVEL_HIGH : 1; /*!< [5..5] GPIO17_LEVEL_HIGH */ - __IOM uint32_t GPIO17_EDGE_LOW : 1; /*!< [6..6] GPIO17_EDGE_LOW */ - __IOM uint32_t GPIO17_EDGE_HIGH : 1; /*!< [7..7] GPIO17_EDGE_HIGH */ - __IOM uint32_t GPIO18_LEVEL_LOW : 1; /*!< [8..8] GPIO18_LEVEL_LOW */ - __IOM uint32_t GPIO18_LEVEL_HIGH : 1; /*!< [9..9] GPIO18_LEVEL_HIGH */ - __IOM uint32_t GPIO18_EDGE_LOW : 1; /*!< [10..10] GPIO18_EDGE_LOW */ - __IOM uint32_t GPIO18_EDGE_HIGH : 1; /*!< [11..11] GPIO18_EDGE_HIGH */ - __IOM uint32_t GPIO19_LEVEL_LOW : 1; /*!< [12..12] GPIO19_LEVEL_LOW */ - __IOM uint32_t GPIO19_LEVEL_HIGH : 1; /*!< [13..13] GPIO19_LEVEL_HIGH */ - __IOM uint32_t GPIO19_EDGE_LOW : 1; /*!< [14..14] GPIO19_EDGE_LOW */ - __IOM uint32_t GPIO19_EDGE_HIGH : 1; /*!< [15..15] GPIO19_EDGE_HIGH */ - __IOM uint32_t GPIO20_LEVEL_LOW : 1; /*!< [16..16] GPIO20_LEVEL_LOW */ - __IOM uint32_t GPIO20_LEVEL_HIGH : 1; /*!< [17..17] GPIO20_LEVEL_HIGH */ - __IOM uint32_t GPIO20_EDGE_LOW : 1; /*!< [18..18] GPIO20_EDGE_LOW */ - __IOM uint32_t GPIO20_EDGE_HIGH : 1; /*!< [19..19] GPIO20_EDGE_HIGH */ - __IOM uint32_t GPIO21_LEVEL_LOW : 1; /*!< [20..20] GPIO21_LEVEL_LOW */ - __IOM uint32_t GPIO21_LEVEL_HIGH : 1; /*!< [21..21] GPIO21_LEVEL_HIGH */ - __IOM uint32_t GPIO21_EDGE_LOW : 1; /*!< [22..22] GPIO21_EDGE_LOW */ - __IOM uint32_t GPIO21_EDGE_HIGH : 1; /*!< [23..23] GPIO21_EDGE_HIGH */ - __IOM uint32_t GPIO22_LEVEL_LOW : 1; /*!< [24..24] GPIO22_LEVEL_LOW */ - __IOM uint32_t GPIO22_LEVEL_HIGH : 1; /*!< [25..25] GPIO22_LEVEL_HIGH */ - __IOM uint32_t GPIO22_EDGE_LOW : 1; /*!< [26..26] GPIO22_EDGE_LOW */ - __IOM uint32_t GPIO22_EDGE_HIGH : 1; /*!< [27..27] GPIO22_EDGE_HIGH */ - __IOM uint32_t GPIO23_LEVEL_LOW : 1; /*!< [28..28] GPIO23_LEVEL_LOW */ - __IOM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< [29..29] GPIO23_LEVEL_HIGH */ - __IOM uint32_t GPIO23_EDGE_LOW : 1; /*!< [30..30] GPIO23_EDGE_LOW */ - __IOM uint32_t GPIO23_EDGE_HIGH : 1; /*!< [31..31] GPIO23_EDGE_HIGH */ - } bit; - } DORMANT_WAKE_INTF2; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000017C) Interrupt Force for dormant_wake */ - - struct { - __IOM uint32_t GPIO24_LEVEL_LOW : 1; /*!< [0..0] GPIO24_LEVEL_LOW */ - __IOM uint32_t GPIO24_LEVEL_HIGH : 1; /*!< [1..1] GPIO24_LEVEL_HIGH */ - __IOM uint32_t GPIO24_EDGE_LOW : 1; /*!< [2..2] GPIO24_EDGE_LOW */ - __IOM uint32_t GPIO24_EDGE_HIGH : 1; /*!< [3..3] GPIO24_EDGE_HIGH */ - __IOM uint32_t GPIO25_LEVEL_LOW : 1; /*!< [4..4] GPIO25_LEVEL_LOW */ - __IOM uint32_t GPIO25_LEVEL_HIGH : 1; /*!< [5..5] GPIO25_LEVEL_HIGH */ - __IOM uint32_t GPIO25_EDGE_LOW : 1; /*!< [6..6] GPIO25_EDGE_LOW */ - __IOM uint32_t GPIO25_EDGE_HIGH : 1; /*!< [7..7] GPIO25_EDGE_HIGH */ - __IOM uint32_t GPIO26_LEVEL_LOW : 1; /*!< [8..8] GPIO26_LEVEL_LOW */ - __IOM uint32_t GPIO26_LEVEL_HIGH : 1; /*!< [9..9] GPIO26_LEVEL_HIGH */ - __IOM uint32_t GPIO26_EDGE_LOW : 1; /*!< [10..10] GPIO26_EDGE_LOW */ - __IOM uint32_t GPIO26_EDGE_HIGH : 1; /*!< [11..11] GPIO26_EDGE_HIGH */ - __IOM uint32_t GPIO27_LEVEL_LOW : 1; /*!< [12..12] GPIO27_LEVEL_LOW */ - __IOM uint32_t GPIO27_LEVEL_HIGH : 1; /*!< [13..13] GPIO27_LEVEL_HIGH */ - __IOM uint32_t GPIO27_EDGE_LOW : 1; /*!< [14..14] GPIO27_EDGE_LOW */ - __IOM uint32_t GPIO27_EDGE_HIGH : 1; /*!< [15..15] GPIO27_EDGE_HIGH */ - __IOM uint32_t GPIO28_LEVEL_LOW : 1; /*!< [16..16] GPIO28_LEVEL_LOW */ - __IOM uint32_t GPIO28_LEVEL_HIGH : 1; /*!< [17..17] GPIO28_LEVEL_HIGH */ - __IOM uint32_t GPIO28_EDGE_LOW : 1; /*!< [18..18] GPIO28_EDGE_LOW */ - __IOM uint32_t GPIO28_EDGE_HIGH : 1; /*!< [19..19] GPIO28_EDGE_HIGH */ - __IOM uint32_t GPIO29_LEVEL_LOW : 1; /*!< [20..20] GPIO29_LEVEL_LOW */ - __IOM uint32_t GPIO29_LEVEL_HIGH : 1; /*!< [21..21] GPIO29_LEVEL_HIGH */ - __IOM uint32_t GPIO29_EDGE_LOW : 1; /*!< [22..22] GPIO29_EDGE_LOW */ - __IOM uint32_t GPIO29_EDGE_HIGH : 1; /*!< [23..23] GPIO29_EDGE_HIGH */ - uint32_t : 8; - } bit; - } DORMANT_WAKE_INTF3; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000180) Interrupt status after masking & forcing for + __IOM uint32_t DORMANT_WAKE_INTE0; /*!< (@ 0x00000160) Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTE1; /*!< (@ 0x00000164) Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTE2; /*!< (@ 0x00000168) Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTE3; /*!< (@ 0x0000016C) Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF0; /*!< (@ 0x00000170) Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF1; /*!< (@ 0x00000174) Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF2; /*!< (@ 0x00000178) Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF3; /*!< (@ 0x0000017C) Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTS0; /*!< (@ 0x00000180) Interrupt status after masking & forcing for dormant_wake */ - - struct { - __IM uint32_t GPIO0_LEVEL_LOW : 1; /*!< [0..0] GPIO0_LEVEL_LOW */ - __IM uint32_t GPIO0_LEVEL_HIGH : 1; /*!< [1..1] GPIO0_LEVEL_HIGH */ - __IM uint32_t GPIO0_EDGE_LOW : 1; /*!< [2..2] GPIO0_EDGE_LOW */ - __IM uint32_t GPIO0_EDGE_HIGH : 1; /*!< [3..3] GPIO0_EDGE_HIGH */ - __IM uint32_t GPIO1_LEVEL_LOW : 1; /*!< [4..4] GPIO1_LEVEL_LOW */ - __IM uint32_t GPIO1_LEVEL_HIGH : 1; /*!< [5..5] GPIO1_LEVEL_HIGH */ - __IM uint32_t GPIO1_EDGE_LOW : 1; /*!< [6..6] GPIO1_EDGE_LOW */ - __IM uint32_t GPIO1_EDGE_HIGH : 1; /*!< [7..7] GPIO1_EDGE_HIGH */ - __IM uint32_t GPIO2_LEVEL_LOW : 1; /*!< [8..8] GPIO2_LEVEL_LOW */ - __IM uint32_t GPIO2_LEVEL_HIGH : 1; /*!< [9..9] GPIO2_LEVEL_HIGH */ - __IM uint32_t GPIO2_EDGE_LOW : 1; /*!< [10..10] GPIO2_EDGE_LOW */ - __IM uint32_t GPIO2_EDGE_HIGH : 1; /*!< [11..11] GPIO2_EDGE_HIGH */ - __IM uint32_t GPIO3_LEVEL_LOW : 1; /*!< [12..12] GPIO3_LEVEL_LOW */ - __IM uint32_t GPIO3_LEVEL_HIGH : 1; /*!< [13..13] GPIO3_LEVEL_HIGH */ - __IM uint32_t GPIO3_EDGE_LOW : 1; /*!< [14..14] GPIO3_EDGE_LOW */ - __IM uint32_t GPIO3_EDGE_HIGH : 1; /*!< [15..15] GPIO3_EDGE_HIGH */ - __IM uint32_t GPIO4_LEVEL_LOW : 1; /*!< [16..16] GPIO4_LEVEL_LOW */ - __IM uint32_t GPIO4_LEVEL_HIGH : 1; /*!< [17..17] GPIO4_LEVEL_HIGH */ - __IM uint32_t GPIO4_EDGE_LOW : 1; /*!< [18..18] GPIO4_EDGE_LOW */ - __IM uint32_t GPIO4_EDGE_HIGH : 1; /*!< [19..19] GPIO4_EDGE_HIGH */ - __IM uint32_t GPIO5_LEVEL_LOW : 1; /*!< [20..20] GPIO5_LEVEL_LOW */ - __IM uint32_t GPIO5_LEVEL_HIGH : 1; /*!< [21..21] GPIO5_LEVEL_HIGH */ - __IM uint32_t GPIO5_EDGE_LOW : 1; /*!< [22..22] GPIO5_EDGE_LOW */ - __IM uint32_t GPIO5_EDGE_HIGH : 1; /*!< [23..23] GPIO5_EDGE_HIGH */ - __IM uint32_t GPIO6_LEVEL_LOW : 1; /*!< [24..24] GPIO6_LEVEL_LOW */ - __IM uint32_t GPIO6_LEVEL_HIGH : 1; /*!< [25..25] GPIO6_LEVEL_HIGH */ - __IM uint32_t GPIO6_EDGE_LOW : 1; /*!< [26..26] GPIO6_EDGE_LOW */ - __IM uint32_t GPIO6_EDGE_HIGH : 1; /*!< [27..27] GPIO6_EDGE_HIGH */ - __IM uint32_t GPIO7_LEVEL_LOW : 1; /*!< [28..28] GPIO7_LEVEL_LOW */ - __IM uint32_t GPIO7_LEVEL_HIGH : 1; /*!< [29..29] GPIO7_LEVEL_HIGH */ - __IM uint32_t GPIO7_EDGE_LOW : 1; /*!< [30..30] GPIO7_EDGE_LOW */ - __IM uint32_t GPIO7_EDGE_HIGH : 1; /*!< [31..31] GPIO7_EDGE_HIGH */ - } bit; - } DORMANT_WAKE_INTS0; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000184) Interrupt status after masking & forcing for + __IOM uint32_t DORMANT_WAKE_INTS1; /*!< (@ 0x00000184) Interrupt status after masking & forcing for dormant_wake */ - - struct { - __IM uint32_t GPIO8_LEVEL_LOW : 1; /*!< [0..0] GPIO8_LEVEL_LOW */ - __IM uint32_t GPIO8_LEVEL_HIGH : 1; /*!< [1..1] GPIO8_LEVEL_HIGH */ - __IM uint32_t GPIO8_EDGE_LOW : 1; /*!< [2..2] GPIO8_EDGE_LOW */ - __IM uint32_t GPIO8_EDGE_HIGH : 1; /*!< [3..3] GPIO8_EDGE_HIGH */ - __IM uint32_t GPIO9_LEVEL_LOW : 1; /*!< [4..4] GPIO9_LEVEL_LOW */ - __IM uint32_t GPIO9_LEVEL_HIGH : 1; /*!< [5..5] GPIO9_LEVEL_HIGH */ - __IM uint32_t GPIO9_EDGE_LOW : 1; /*!< [6..6] GPIO9_EDGE_LOW */ - __IM uint32_t GPIO9_EDGE_HIGH : 1; /*!< [7..7] GPIO9_EDGE_HIGH */ - __IM uint32_t GPIO10_LEVEL_LOW : 1; /*!< [8..8] GPIO10_LEVEL_LOW */ - __IM uint32_t GPIO10_LEVEL_HIGH : 1; /*!< [9..9] GPIO10_LEVEL_HIGH */ - __IM uint32_t GPIO10_EDGE_LOW : 1; /*!< [10..10] GPIO10_EDGE_LOW */ - __IM uint32_t GPIO10_EDGE_HIGH : 1; /*!< [11..11] GPIO10_EDGE_HIGH */ - __IM uint32_t GPIO11_LEVEL_LOW : 1; /*!< [12..12] GPIO11_LEVEL_LOW */ - __IM uint32_t GPIO11_LEVEL_HIGH : 1; /*!< [13..13] GPIO11_LEVEL_HIGH */ - __IM uint32_t GPIO11_EDGE_LOW : 1; /*!< [14..14] GPIO11_EDGE_LOW */ - __IM uint32_t GPIO11_EDGE_HIGH : 1; /*!< [15..15] GPIO11_EDGE_HIGH */ - __IM uint32_t GPIO12_LEVEL_LOW : 1; /*!< [16..16] GPIO12_LEVEL_LOW */ - __IM uint32_t GPIO12_LEVEL_HIGH : 1; /*!< [17..17] GPIO12_LEVEL_HIGH */ - __IM uint32_t GPIO12_EDGE_LOW : 1; /*!< [18..18] GPIO12_EDGE_LOW */ - __IM uint32_t GPIO12_EDGE_HIGH : 1; /*!< [19..19] GPIO12_EDGE_HIGH */ - __IM uint32_t GPIO13_LEVEL_LOW : 1; /*!< [20..20] GPIO13_LEVEL_LOW */ - __IM uint32_t GPIO13_LEVEL_HIGH : 1; /*!< [21..21] GPIO13_LEVEL_HIGH */ - __IM uint32_t GPIO13_EDGE_LOW : 1; /*!< [22..22] GPIO13_EDGE_LOW */ - __IM uint32_t GPIO13_EDGE_HIGH : 1; /*!< [23..23] GPIO13_EDGE_HIGH */ - __IM uint32_t GPIO14_LEVEL_LOW : 1; /*!< [24..24] GPIO14_LEVEL_LOW */ - __IM uint32_t GPIO14_LEVEL_HIGH : 1; /*!< [25..25] GPIO14_LEVEL_HIGH */ - __IM uint32_t GPIO14_EDGE_LOW : 1; /*!< [26..26] GPIO14_EDGE_LOW */ - __IM uint32_t GPIO14_EDGE_HIGH : 1; /*!< [27..27] GPIO14_EDGE_HIGH */ - __IM uint32_t GPIO15_LEVEL_LOW : 1; /*!< [28..28] GPIO15_LEVEL_LOW */ - __IM uint32_t GPIO15_LEVEL_HIGH : 1; /*!< [29..29] GPIO15_LEVEL_HIGH */ - __IM uint32_t GPIO15_EDGE_LOW : 1; /*!< [30..30] GPIO15_EDGE_LOW */ - __IM uint32_t GPIO15_EDGE_HIGH : 1; /*!< [31..31] GPIO15_EDGE_HIGH */ - } bit; - } DORMANT_WAKE_INTS1; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000188) Interrupt status after masking & forcing for + __IOM uint32_t DORMANT_WAKE_INTS2; /*!< (@ 0x00000188) Interrupt status after masking & forcing for dormant_wake */ - - struct { - __IM uint32_t GPIO16_LEVEL_LOW : 1; /*!< [0..0] GPIO16_LEVEL_LOW */ - __IM uint32_t GPIO16_LEVEL_HIGH : 1; /*!< [1..1] GPIO16_LEVEL_HIGH */ - __IM uint32_t GPIO16_EDGE_LOW : 1; /*!< [2..2] GPIO16_EDGE_LOW */ - __IM uint32_t GPIO16_EDGE_HIGH : 1; /*!< [3..3] GPIO16_EDGE_HIGH */ - __IM uint32_t GPIO17_LEVEL_LOW : 1; /*!< [4..4] GPIO17_LEVEL_LOW */ - __IM uint32_t GPIO17_LEVEL_HIGH : 1; /*!< [5..5] GPIO17_LEVEL_HIGH */ - __IM uint32_t GPIO17_EDGE_LOW : 1; /*!< [6..6] GPIO17_EDGE_LOW */ - __IM uint32_t GPIO17_EDGE_HIGH : 1; /*!< [7..7] GPIO17_EDGE_HIGH */ - __IM uint32_t GPIO18_LEVEL_LOW : 1; /*!< [8..8] GPIO18_LEVEL_LOW */ - __IM uint32_t GPIO18_LEVEL_HIGH : 1; /*!< [9..9] GPIO18_LEVEL_HIGH */ - __IM uint32_t GPIO18_EDGE_LOW : 1; /*!< [10..10] GPIO18_EDGE_LOW */ - __IM uint32_t GPIO18_EDGE_HIGH : 1; /*!< [11..11] GPIO18_EDGE_HIGH */ - __IM uint32_t GPIO19_LEVEL_LOW : 1; /*!< [12..12] GPIO19_LEVEL_LOW */ - __IM uint32_t GPIO19_LEVEL_HIGH : 1; /*!< [13..13] GPIO19_LEVEL_HIGH */ - __IM uint32_t GPIO19_EDGE_LOW : 1; /*!< [14..14] GPIO19_EDGE_LOW */ - __IM uint32_t GPIO19_EDGE_HIGH : 1; /*!< [15..15] GPIO19_EDGE_HIGH */ - __IM uint32_t GPIO20_LEVEL_LOW : 1; /*!< [16..16] GPIO20_LEVEL_LOW */ - __IM uint32_t GPIO20_LEVEL_HIGH : 1; /*!< [17..17] GPIO20_LEVEL_HIGH */ - __IM uint32_t GPIO20_EDGE_LOW : 1; /*!< [18..18] GPIO20_EDGE_LOW */ - __IM uint32_t GPIO20_EDGE_HIGH : 1; /*!< [19..19] GPIO20_EDGE_HIGH */ - __IM uint32_t GPIO21_LEVEL_LOW : 1; /*!< [20..20] GPIO21_LEVEL_LOW */ - __IM uint32_t GPIO21_LEVEL_HIGH : 1; /*!< [21..21] GPIO21_LEVEL_HIGH */ - __IM uint32_t GPIO21_EDGE_LOW : 1; /*!< [22..22] GPIO21_EDGE_LOW */ - __IM uint32_t GPIO21_EDGE_HIGH : 1; /*!< [23..23] GPIO21_EDGE_HIGH */ - __IM uint32_t GPIO22_LEVEL_LOW : 1; /*!< [24..24] GPIO22_LEVEL_LOW */ - __IM uint32_t GPIO22_LEVEL_HIGH : 1; /*!< [25..25] GPIO22_LEVEL_HIGH */ - __IM uint32_t GPIO22_EDGE_LOW : 1; /*!< [26..26] GPIO22_EDGE_LOW */ - __IM uint32_t GPIO22_EDGE_HIGH : 1; /*!< [27..27] GPIO22_EDGE_HIGH */ - __IM uint32_t GPIO23_LEVEL_LOW : 1; /*!< [28..28] GPIO23_LEVEL_LOW */ - __IM uint32_t GPIO23_LEVEL_HIGH : 1; /*!< [29..29] GPIO23_LEVEL_HIGH */ - __IM uint32_t GPIO23_EDGE_LOW : 1; /*!< [30..30] GPIO23_EDGE_LOW */ - __IM uint32_t GPIO23_EDGE_HIGH : 1; /*!< [31..31] GPIO23_EDGE_HIGH */ - } bit; - } DORMANT_WAKE_INTS2; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000018C) Interrupt status after masking & forcing for + __IOM uint32_t DORMANT_WAKE_INTS3; /*!< (@ 0x0000018C) Interrupt status after masking & forcing for dormant_wake */ - - struct { - __IM uint32_t GPIO24_LEVEL_LOW : 1; /*!< [0..0] GPIO24_LEVEL_LOW */ - __IM uint32_t GPIO24_LEVEL_HIGH : 1; /*!< [1..1] GPIO24_LEVEL_HIGH */ - __IM uint32_t GPIO24_EDGE_LOW : 1; /*!< [2..2] GPIO24_EDGE_LOW */ - __IM uint32_t GPIO24_EDGE_HIGH : 1; /*!< [3..3] GPIO24_EDGE_HIGH */ - __IM uint32_t GPIO25_LEVEL_LOW : 1; /*!< [4..4] GPIO25_LEVEL_LOW */ - __IM uint32_t GPIO25_LEVEL_HIGH : 1; /*!< [5..5] GPIO25_LEVEL_HIGH */ - __IM uint32_t GPIO25_EDGE_LOW : 1; /*!< [6..6] GPIO25_EDGE_LOW */ - __IM uint32_t GPIO25_EDGE_HIGH : 1; /*!< [7..7] GPIO25_EDGE_HIGH */ - __IM uint32_t GPIO26_LEVEL_LOW : 1; /*!< [8..8] GPIO26_LEVEL_LOW */ - __IM uint32_t GPIO26_LEVEL_HIGH : 1; /*!< [9..9] GPIO26_LEVEL_HIGH */ - __IM uint32_t GPIO26_EDGE_LOW : 1; /*!< [10..10] GPIO26_EDGE_LOW */ - __IM uint32_t GPIO26_EDGE_HIGH : 1; /*!< [11..11] GPIO26_EDGE_HIGH */ - __IM uint32_t GPIO27_LEVEL_LOW : 1; /*!< [12..12] GPIO27_LEVEL_LOW */ - __IM uint32_t GPIO27_LEVEL_HIGH : 1; /*!< [13..13] GPIO27_LEVEL_HIGH */ - __IM uint32_t GPIO27_EDGE_LOW : 1; /*!< [14..14] GPIO27_EDGE_LOW */ - __IM uint32_t GPIO27_EDGE_HIGH : 1; /*!< [15..15] GPIO27_EDGE_HIGH */ - __IM uint32_t GPIO28_LEVEL_LOW : 1; /*!< [16..16] GPIO28_LEVEL_LOW */ - __IM uint32_t GPIO28_LEVEL_HIGH : 1; /*!< [17..17] GPIO28_LEVEL_HIGH */ - __IM uint32_t GPIO28_EDGE_LOW : 1; /*!< [18..18] GPIO28_EDGE_LOW */ - __IM uint32_t GPIO28_EDGE_HIGH : 1; /*!< [19..19] GPIO28_EDGE_HIGH */ - __IM uint32_t GPIO29_LEVEL_LOW : 1; /*!< [20..20] GPIO29_LEVEL_LOW */ - __IM uint32_t GPIO29_LEVEL_HIGH : 1; /*!< [21..21] GPIO29_LEVEL_HIGH */ - __IM uint32_t GPIO29_EDGE_LOW : 1; /*!< [22..22] GPIO29_EDGE_LOW */ - __IM uint32_t GPIO29_EDGE_HIGH : 1; /*!< [23..23] GPIO29_EDGE_HIGH */ - uint32_t : 8; - } bit; - } DORMANT_WAKE_INTS3; } IO_BANK0_Type; /*!< Size = 400 (0x190) */ @@ -4438,581 +610,31 @@ typedef struct { /*!< (@ 0x40014000) IO_BANK0 Str */ typedef struct { /*!< (@ 0x40018000) IO_QSPI Structure */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000000) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO_QSPI_SCLK_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000004) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO_QSPI_SCLK_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000008) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO_QSPI_SS_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO_QSPI_SS_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000010) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO_QSPI_SD0_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000014) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO_QSPI_SD0_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000018) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO_QSPI_SD1_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO_QSPI_SD1_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000020) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO_QSPI_SD2_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000024) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO_QSPI_SD2_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000028) GPIO status */ - - struct { - uint32_t : 8; - __IM uint32_t OUTFROMPERI : 1; /*!< [8..8] output signal from selected peripheral, before register - override is applied */ - __IM uint32_t OUTTOPAD : 1; /*!< [9..9] output signal to pad after register override is applied */ - uint32_t : 2; - __IM uint32_t OEFROMPERI : 1; /*!< [12..12] output enable from selected peripheral, before register - override is applied */ - __IM uint32_t OETOPAD : 1; /*!< [13..13] output enable to pad after register override is applied */ - uint32_t : 3; - __IM uint32_t INFROMPAD : 1; /*!< [17..17] input signal from pad, before override is applied */ - uint32_t : 1; - __IM uint32_t INTOPERI : 1; /*!< [19..19] input signal to peripheral, after override is applied */ - uint32_t : 4; - __IM uint32_t IRQFROMPAD : 1; /*!< [24..24] interrupt from pad before override is applied */ - uint32_t : 1; - __IM uint32_t IRQTOPROC : 1; /*!< [26..26] interrupt to processors, after override is applied */ - uint32_t : 5; - } bit; - } GPIO_QSPI_SD3_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000002C) GPIO control including function select and overrides. */ - - struct { - __IOM uint32_t FUNCSEL : 5; /*!< [4..0] 0-31 -> selects pin function according to the gpio table - 31 == NULL */ - uint32_t : 3; - __IOM uint32_t OUTOVER : 2; /*!< [9..8] OUTOVER */ - uint32_t : 2; - __IOM uint32_t OEOVER : 2; /*!< [13..12] OEOVER */ - uint32_t : 2; - __IOM uint32_t INOVER : 2; /*!< [17..16] INOVER */ - uint32_t : 10; - __IOM uint32_t IRQOVER : 2; /*!< [29..28] IRQOVER */ - uint32_t : 2; - } bit; - } GPIO_QSPI_SD3_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000030) Raw Interrupts */ - - struct { - __IM uint32_t GPIO_QSPI_SCLK_LEVEL_LOW : 1;/*!< [0..0] GPIO_QSPI_SCLK_LEVEL_LOW */ - __IM uint32_t GPIO_QSPI_SCLK_LEVEL_HIGH : 1;/*!< [1..1] GPIO_QSPI_SCLK_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SCLK_EDGE_LOW : 1;/*!< [2..2] GPIO_QSPI_SCLK_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SCLK_EDGE_HIGH : 1;/*!< [3..3] GPIO_QSPI_SCLK_EDGE_HIGH */ - __IM uint32_t GPIO_QSPI_SS_LEVEL_LOW : 1;/*!< [4..4] GPIO_QSPI_SS_LEVEL_LOW */ - __IM uint32_t GPIO_QSPI_SS_LEVEL_HIGH : 1;/*!< [5..5] GPIO_QSPI_SS_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SS_EDGE_LOW : 1; /*!< [6..6] GPIO_QSPI_SS_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SS_EDGE_HIGH : 1;/*!< [7..7] GPIO_QSPI_SS_EDGE_HIGH */ - __IM uint32_t GPIO_QSPI_SD0_LEVEL_LOW : 1;/*!< [8..8] GPIO_QSPI_SD0_LEVEL_LOW */ - __IM uint32_t GPIO_QSPI_SD0_LEVEL_HIGH : 1;/*!< [9..9] GPIO_QSPI_SD0_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SD0_EDGE_LOW : 1;/*!< [10..10] GPIO_QSPI_SD0_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SD0_EDGE_HIGH : 1;/*!< [11..11] GPIO_QSPI_SD0_EDGE_HIGH */ - __IM uint32_t GPIO_QSPI_SD1_LEVEL_LOW : 1;/*!< [12..12] GPIO_QSPI_SD1_LEVEL_LOW */ - __IM uint32_t GPIO_QSPI_SD1_LEVEL_HIGH : 1;/*!< [13..13] GPIO_QSPI_SD1_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SD1_EDGE_LOW : 1;/*!< [14..14] GPIO_QSPI_SD1_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SD1_EDGE_HIGH : 1;/*!< [15..15] GPIO_QSPI_SD1_EDGE_HIGH */ - __IM uint32_t GPIO_QSPI_SD2_LEVEL_LOW : 1;/*!< [16..16] GPIO_QSPI_SD2_LEVEL_LOW */ - __IM uint32_t GPIO_QSPI_SD2_LEVEL_HIGH : 1;/*!< [17..17] GPIO_QSPI_SD2_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SD2_EDGE_LOW : 1;/*!< [18..18] GPIO_QSPI_SD2_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SD2_EDGE_HIGH : 1;/*!< [19..19] GPIO_QSPI_SD2_EDGE_HIGH */ - __IM uint32_t GPIO_QSPI_SD3_LEVEL_LOW : 1;/*!< [20..20] GPIO_QSPI_SD3_LEVEL_LOW */ - __IM uint32_t GPIO_QSPI_SD3_LEVEL_HIGH : 1;/*!< [21..21] GPIO_QSPI_SD3_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< [22..22] GPIO_QSPI_SD3_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< [23..23] GPIO_QSPI_SD3_EDGE_HIGH */ - uint32_t : 8; - } bit; - } INTR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000034) Interrupt Enable for proc0 */ - - struct { - __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_LOW : 1;/*!< [0..0] GPIO_QSPI_SCLK_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_HIGH : 1;/*!< [1..1] GPIO_QSPI_SCLK_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SCLK_EDGE_LOW : 1;/*!< [2..2] GPIO_QSPI_SCLK_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SCLK_EDGE_HIGH : 1;/*!< [3..3] GPIO_QSPI_SCLK_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SS_LEVEL_LOW : 1;/*!< [4..4] GPIO_QSPI_SS_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SS_LEVEL_HIGH : 1;/*!< [5..5] GPIO_QSPI_SS_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SS_EDGE_LOW : 1; /*!< [6..6] GPIO_QSPI_SS_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SS_EDGE_HIGH : 1;/*!< [7..7] GPIO_QSPI_SS_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SD0_LEVEL_LOW : 1;/*!< [8..8] GPIO_QSPI_SD0_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SD0_LEVEL_HIGH : 1;/*!< [9..9] GPIO_QSPI_SD0_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SD0_EDGE_LOW : 1;/*!< [10..10] GPIO_QSPI_SD0_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SD0_EDGE_HIGH : 1;/*!< [11..11] GPIO_QSPI_SD0_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SD1_LEVEL_LOW : 1;/*!< [12..12] GPIO_QSPI_SD1_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SD1_LEVEL_HIGH : 1;/*!< [13..13] GPIO_QSPI_SD1_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SD1_EDGE_LOW : 1;/*!< [14..14] GPIO_QSPI_SD1_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SD1_EDGE_HIGH : 1;/*!< [15..15] GPIO_QSPI_SD1_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SD2_LEVEL_LOW : 1;/*!< [16..16] GPIO_QSPI_SD2_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SD2_LEVEL_HIGH : 1;/*!< [17..17] GPIO_QSPI_SD2_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SD2_EDGE_LOW : 1;/*!< [18..18] GPIO_QSPI_SD2_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SD2_EDGE_HIGH : 1;/*!< [19..19] GPIO_QSPI_SD2_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SD3_LEVEL_LOW : 1;/*!< [20..20] GPIO_QSPI_SD3_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SD3_LEVEL_HIGH : 1;/*!< [21..21] GPIO_QSPI_SD3_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< [22..22] GPIO_QSPI_SD3_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< [23..23] GPIO_QSPI_SD3_EDGE_HIGH */ - uint32_t : 8; - } bit; - } PROC0_INTE; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000038) Interrupt Force for proc0 */ - - struct { - __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_LOW : 1;/*!< [0..0] GPIO_QSPI_SCLK_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_HIGH : 1;/*!< [1..1] GPIO_QSPI_SCLK_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SCLK_EDGE_LOW : 1;/*!< [2..2] GPIO_QSPI_SCLK_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SCLK_EDGE_HIGH : 1;/*!< [3..3] GPIO_QSPI_SCLK_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SS_LEVEL_LOW : 1;/*!< [4..4] GPIO_QSPI_SS_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SS_LEVEL_HIGH : 1;/*!< [5..5] GPIO_QSPI_SS_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SS_EDGE_LOW : 1; /*!< [6..6] GPIO_QSPI_SS_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SS_EDGE_HIGH : 1;/*!< [7..7] GPIO_QSPI_SS_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SD0_LEVEL_LOW : 1;/*!< [8..8] GPIO_QSPI_SD0_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SD0_LEVEL_HIGH : 1;/*!< [9..9] GPIO_QSPI_SD0_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SD0_EDGE_LOW : 1;/*!< [10..10] GPIO_QSPI_SD0_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SD0_EDGE_HIGH : 1;/*!< [11..11] GPIO_QSPI_SD0_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SD1_LEVEL_LOW : 1;/*!< [12..12] GPIO_QSPI_SD1_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SD1_LEVEL_HIGH : 1;/*!< [13..13] GPIO_QSPI_SD1_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SD1_EDGE_LOW : 1;/*!< [14..14] GPIO_QSPI_SD1_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SD1_EDGE_HIGH : 1;/*!< [15..15] GPIO_QSPI_SD1_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SD2_LEVEL_LOW : 1;/*!< [16..16] GPIO_QSPI_SD2_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SD2_LEVEL_HIGH : 1;/*!< [17..17] GPIO_QSPI_SD2_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SD2_EDGE_LOW : 1;/*!< [18..18] GPIO_QSPI_SD2_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SD2_EDGE_HIGH : 1;/*!< [19..19] GPIO_QSPI_SD2_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SD3_LEVEL_LOW : 1;/*!< [20..20] GPIO_QSPI_SD3_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SD3_LEVEL_HIGH : 1;/*!< [21..21] GPIO_QSPI_SD3_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< [22..22] GPIO_QSPI_SD3_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< [23..23] GPIO_QSPI_SD3_EDGE_HIGH */ - uint32_t : 8; - } bit; - } PROC0_INTF; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000003C) Interrupt status after masking & forcing for + __IOM uint32_t GPIO_QSPI_SCLK_STATUS; /*!< (@ 0x00000000) GPIO status */ + __IOM uint32_t GPIO_QSPI_SCLK_CTRL; /*!< (@ 0x00000004) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO_QSPI_SS_STATUS; /*!< (@ 0x00000008) GPIO status */ + __IOM uint32_t GPIO_QSPI_SS_CTRL; /*!< (@ 0x0000000C) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO_QSPI_SD0_STATUS; /*!< (@ 0x00000010) GPIO status */ + __IOM uint32_t GPIO_QSPI_SD0_CTRL; /*!< (@ 0x00000014) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO_QSPI_SD1_STATUS; /*!< (@ 0x00000018) GPIO status */ + __IOM uint32_t GPIO_QSPI_SD1_CTRL; /*!< (@ 0x0000001C) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO_QSPI_SD2_STATUS; /*!< (@ 0x00000020) GPIO status */ + __IOM uint32_t GPIO_QSPI_SD2_CTRL; /*!< (@ 0x00000024) GPIO control including function select and overrides. */ + __IOM uint32_t GPIO_QSPI_SD3_STATUS; /*!< (@ 0x00000028) GPIO status */ + __IOM uint32_t GPIO_QSPI_SD3_CTRL; /*!< (@ 0x0000002C) GPIO control including function select and overrides. */ + __IOM uint32_t INTR; /*!< (@ 0x00000030) Raw Interrupts */ + __IOM uint32_t PROC0_INTE; /*!< (@ 0x00000034) Interrupt Enable for proc0 */ + __IOM uint32_t PROC0_INTF; /*!< (@ 0x00000038) Interrupt Force for proc0 */ + __IOM uint32_t PROC0_INTS; /*!< (@ 0x0000003C) Interrupt status after masking & forcing for proc0 */ - - struct { - __IM uint32_t GPIO_QSPI_SCLK_LEVEL_LOW : 1;/*!< [0..0] GPIO_QSPI_SCLK_LEVEL_LOW */ - __IM uint32_t GPIO_QSPI_SCLK_LEVEL_HIGH : 1;/*!< [1..1] GPIO_QSPI_SCLK_LEVEL_HIGH */ - __IM uint32_t GPIO_QSPI_SCLK_EDGE_LOW : 1;/*!< [2..2] GPIO_QSPI_SCLK_EDGE_LOW */ - __IM uint32_t GPIO_QSPI_SCLK_EDGE_HIGH : 1;/*!< [3..3] GPIO_QSPI_SCLK_EDGE_HIGH */ - __IM uint32_t GPIO_QSPI_SS_LEVEL_LOW : 1;/*!< [4..4] GPIO_QSPI_SS_LEVEL_LOW */ - __IM uint32_t GPIO_QSPI_SS_LEVEL_HIGH : 1;/*!< [5..5] GPIO_QSPI_SS_LEVEL_HIGH */ - __IM uint32_t GPIO_QSPI_SS_EDGE_LOW : 1; /*!< [6..6] GPIO_QSPI_SS_EDGE_LOW */ - __IM uint32_t GPIO_QSPI_SS_EDGE_HIGH : 1;/*!< [7..7] GPIO_QSPI_SS_EDGE_HIGH */ - __IM uint32_t GPIO_QSPI_SD0_LEVEL_LOW : 1;/*!< [8..8] GPIO_QSPI_SD0_LEVEL_LOW */ - __IM uint32_t GPIO_QSPI_SD0_LEVEL_HIGH : 1;/*!< [9..9] GPIO_QSPI_SD0_LEVEL_HIGH */ - __IM uint32_t GPIO_QSPI_SD0_EDGE_LOW : 1;/*!< [10..10] GPIO_QSPI_SD0_EDGE_LOW */ - __IM uint32_t GPIO_QSPI_SD0_EDGE_HIGH : 1;/*!< [11..11] GPIO_QSPI_SD0_EDGE_HIGH */ - __IM uint32_t GPIO_QSPI_SD1_LEVEL_LOW : 1;/*!< [12..12] GPIO_QSPI_SD1_LEVEL_LOW */ - __IM uint32_t GPIO_QSPI_SD1_LEVEL_HIGH : 1;/*!< [13..13] GPIO_QSPI_SD1_LEVEL_HIGH */ - __IM uint32_t GPIO_QSPI_SD1_EDGE_LOW : 1;/*!< [14..14] GPIO_QSPI_SD1_EDGE_LOW */ - __IM uint32_t GPIO_QSPI_SD1_EDGE_HIGH : 1;/*!< [15..15] GPIO_QSPI_SD1_EDGE_HIGH */ - __IM uint32_t GPIO_QSPI_SD2_LEVEL_LOW : 1;/*!< [16..16] GPIO_QSPI_SD2_LEVEL_LOW */ - __IM uint32_t GPIO_QSPI_SD2_LEVEL_HIGH : 1;/*!< [17..17] GPIO_QSPI_SD2_LEVEL_HIGH */ - __IM uint32_t GPIO_QSPI_SD2_EDGE_LOW : 1;/*!< [18..18] GPIO_QSPI_SD2_EDGE_LOW */ - __IM uint32_t GPIO_QSPI_SD2_EDGE_HIGH : 1;/*!< [19..19] GPIO_QSPI_SD2_EDGE_HIGH */ - __IM uint32_t GPIO_QSPI_SD3_LEVEL_LOW : 1;/*!< [20..20] GPIO_QSPI_SD3_LEVEL_LOW */ - __IM uint32_t GPIO_QSPI_SD3_LEVEL_HIGH : 1;/*!< [21..21] GPIO_QSPI_SD3_LEVEL_HIGH */ - __IM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< [22..22] GPIO_QSPI_SD3_EDGE_LOW */ - __IM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< [23..23] GPIO_QSPI_SD3_EDGE_HIGH */ - uint32_t : 8; - } bit; - } PROC0_INTS; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000040) Interrupt Enable for proc1 */ - - struct { - __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_LOW : 1;/*!< [0..0] GPIO_QSPI_SCLK_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_HIGH : 1;/*!< [1..1] GPIO_QSPI_SCLK_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SCLK_EDGE_LOW : 1;/*!< [2..2] GPIO_QSPI_SCLK_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SCLK_EDGE_HIGH : 1;/*!< [3..3] GPIO_QSPI_SCLK_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SS_LEVEL_LOW : 1;/*!< [4..4] GPIO_QSPI_SS_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SS_LEVEL_HIGH : 1;/*!< [5..5] GPIO_QSPI_SS_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SS_EDGE_LOW : 1; /*!< [6..6] GPIO_QSPI_SS_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SS_EDGE_HIGH : 1;/*!< [7..7] GPIO_QSPI_SS_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SD0_LEVEL_LOW : 1;/*!< [8..8] GPIO_QSPI_SD0_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SD0_LEVEL_HIGH : 1;/*!< [9..9] GPIO_QSPI_SD0_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SD0_EDGE_LOW : 1;/*!< [10..10] GPIO_QSPI_SD0_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SD0_EDGE_HIGH : 1;/*!< [11..11] GPIO_QSPI_SD0_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SD1_LEVEL_LOW : 1;/*!< [12..12] GPIO_QSPI_SD1_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SD1_LEVEL_HIGH : 1;/*!< [13..13] GPIO_QSPI_SD1_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SD1_EDGE_LOW : 1;/*!< [14..14] GPIO_QSPI_SD1_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SD1_EDGE_HIGH : 1;/*!< [15..15] GPIO_QSPI_SD1_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SD2_LEVEL_LOW : 1;/*!< [16..16] GPIO_QSPI_SD2_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SD2_LEVEL_HIGH : 1;/*!< [17..17] GPIO_QSPI_SD2_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SD2_EDGE_LOW : 1;/*!< [18..18] GPIO_QSPI_SD2_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SD2_EDGE_HIGH : 1;/*!< [19..19] GPIO_QSPI_SD2_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SD3_LEVEL_LOW : 1;/*!< [20..20] GPIO_QSPI_SD3_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SD3_LEVEL_HIGH : 1;/*!< [21..21] GPIO_QSPI_SD3_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< [22..22] GPIO_QSPI_SD3_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< [23..23] GPIO_QSPI_SD3_EDGE_HIGH */ - uint32_t : 8; - } bit; - } PROC1_INTE; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000044) Interrupt Force for proc1 */ - - struct { - __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_LOW : 1;/*!< [0..0] GPIO_QSPI_SCLK_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_HIGH : 1;/*!< [1..1] GPIO_QSPI_SCLK_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SCLK_EDGE_LOW : 1;/*!< [2..2] GPIO_QSPI_SCLK_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SCLK_EDGE_HIGH : 1;/*!< [3..3] GPIO_QSPI_SCLK_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SS_LEVEL_LOW : 1;/*!< [4..4] GPIO_QSPI_SS_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SS_LEVEL_HIGH : 1;/*!< [5..5] GPIO_QSPI_SS_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SS_EDGE_LOW : 1; /*!< [6..6] GPIO_QSPI_SS_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SS_EDGE_HIGH : 1;/*!< [7..7] GPIO_QSPI_SS_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SD0_LEVEL_LOW : 1;/*!< [8..8] GPIO_QSPI_SD0_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SD0_LEVEL_HIGH : 1;/*!< [9..9] GPIO_QSPI_SD0_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SD0_EDGE_LOW : 1;/*!< [10..10] GPIO_QSPI_SD0_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SD0_EDGE_HIGH : 1;/*!< [11..11] GPIO_QSPI_SD0_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SD1_LEVEL_LOW : 1;/*!< [12..12] GPIO_QSPI_SD1_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SD1_LEVEL_HIGH : 1;/*!< [13..13] GPIO_QSPI_SD1_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SD1_EDGE_LOW : 1;/*!< [14..14] GPIO_QSPI_SD1_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SD1_EDGE_HIGH : 1;/*!< [15..15] GPIO_QSPI_SD1_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SD2_LEVEL_LOW : 1;/*!< [16..16] GPIO_QSPI_SD2_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SD2_LEVEL_HIGH : 1;/*!< [17..17] GPIO_QSPI_SD2_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SD2_EDGE_LOW : 1;/*!< [18..18] GPIO_QSPI_SD2_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SD2_EDGE_HIGH : 1;/*!< [19..19] GPIO_QSPI_SD2_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SD3_LEVEL_LOW : 1;/*!< [20..20] GPIO_QSPI_SD3_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SD3_LEVEL_HIGH : 1;/*!< [21..21] GPIO_QSPI_SD3_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< [22..22] GPIO_QSPI_SD3_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< [23..23] GPIO_QSPI_SD3_EDGE_HIGH */ - uint32_t : 8; - } bit; - } PROC1_INTF; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000048) Interrupt status after masking & forcing for + __IOM uint32_t PROC1_INTE; /*!< (@ 0x00000040) Interrupt Enable for proc1 */ + __IOM uint32_t PROC1_INTF; /*!< (@ 0x00000044) Interrupt Force for proc1 */ + __IOM uint32_t PROC1_INTS; /*!< (@ 0x00000048) Interrupt status after masking & forcing for proc1 */ - - struct { - __IM uint32_t GPIO_QSPI_SCLK_LEVEL_LOW : 1;/*!< [0..0] GPIO_QSPI_SCLK_LEVEL_LOW */ - __IM uint32_t GPIO_QSPI_SCLK_LEVEL_HIGH : 1;/*!< [1..1] GPIO_QSPI_SCLK_LEVEL_HIGH */ - __IM uint32_t GPIO_QSPI_SCLK_EDGE_LOW : 1;/*!< [2..2] GPIO_QSPI_SCLK_EDGE_LOW */ - __IM uint32_t GPIO_QSPI_SCLK_EDGE_HIGH : 1;/*!< [3..3] GPIO_QSPI_SCLK_EDGE_HIGH */ - __IM uint32_t GPIO_QSPI_SS_LEVEL_LOW : 1;/*!< [4..4] GPIO_QSPI_SS_LEVEL_LOW */ - __IM uint32_t GPIO_QSPI_SS_LEVEL_HIGH : 1;/*!< [5..5] GPIO_QSPI_SS_LEVEL_HIGH */ - __IM uint32_t GPIO_QSPI_SS_EDGE_LOW : 1; /*!< [6..6] GPIO_QSPI_SS_EDGE_LOW */ - __IM uint32_t GPIO_QSPI_SS_EDGE_HIGH : 1;/*!< [7..7] GPIO_QSPI_SS_EDGE_HIGH */ - __IM uint32_t GPIO_QSPI_SD0_LEVEL_LOW : 1;/*!< [8..8] GPIO_QSPI_SD0_LEVEL_LOW */ - __IM uint32_t GPIO_QSPI_SD0_LEVEL_HIGH : 1;/*!< [9..9] GPIO_QSPI_SD0_LEVEL_HIGH */ - __IM uint32_t GPIO_QSPI_SD0_EDGE_LOW : 1;/*!< [10..10] GPIO_QSPI_SD0_EDGE_LOW */ - __IM uint32_t GPIO_QSPI_SD0_EDGE_HIGH : 1;/*!< [11..11] GPIO_QSPI_SD0_EDGE_HIGH */ - __IM uint32_t GPIO_QSPI_SD1_LEVEL_LOW : 1;/*!< [12..12] GPIO_QSPI_SD1_LEVEL_LOW */ - __IM uint32_t GPIO_QSPI_SD1_LEVEL_HIGH : 1;/*!< [13..13] GPIO_QSPI_SD1_LEVEL_HIGH */ - __IM uint32_t GPIO_QSPI_SD1_EDGE_LOW : 1;/*!< [14..14] GPIO_QSPI_SD1_EDGE_LOW */ - __IM uint32_t GPIO_QSPI_SD1_EDGE_HIGH : 1;/*!< [15..15] GPIO_QSPI_SD1_EDGE_HIGH */ - __IM uint32_t GPIO_QSPI_SD2_LEVEL_LOW : 1;/*!< [16..16] GPIO_QSPI_SD2_LEVEL_LOW */ - __IM uint32_t GPIO_QSPI_SD2_LEVEL_HIGH : 1;/*!< [17..17] GPIO_QSPI_SD2_LEVEL_HIGH */ - __IM uint32_t GPIO_QSPI_SD2_EDGE_LOW : 1;/*!< [18..18] GPIO_QSPI_SD2_EDGE_LOW */ - __IM uint32_t GPIO_QSPI_SD2_EDGE_HIGH : 1;/*!< [19..19] GPIO_QSPI_SD2_EDGE_HIGH */ - __IM uint32_t GPIO_QSPI_SD3_LEVEL_LOW : 1;/*!< [20..20] GPIO_QSPI_SD3_LEVEL_LOW */ - __IM uint32_t GPIO_QSPI_SD3_LEVEL_HIGH : 1;/*!< [21..21] GPIO_QSPI_SD3_LEVEL_HIGH */ - __IM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< [22..22] GPIO_QSPI_SD3_EDGE_LOW */ - __IM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< [23..23] GPIO_QSPI_SD3_EDGE_HIGH */ - uint32_t : 8; - } bit; - } PROC1_INTS; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000004C) Interrupt Enable for dormant_wake */ - - struct { - __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_LOW : 1;/*!< [0..0] GPIO_QSPI_SCLK_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_HIGH : 1;/*!< [1..1] GPIO_QSPI_SCLK_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SCLK_EDGE_LOW : 1;/*!< [2..2] GPIO_QSPI_SCLK_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SCLK_EDGE_HIGH : 1;/*!< [3..3] GPIO_QSPI_SCLK_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SS_LEVEL_LOW : 1;/*!< [4..4] GPIO_QSPI_SS_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SS_LEVEL_HIGH : 1;/*!< [5..5] GPIO_QSPI_SS_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SS_EDGE_LOW : 1; /*!< [6..6] GPIO_QSPI_SS_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SS_EDGE_HIGH : 1;/*!< [7..7] GPIO_QSPI_SS_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SD0_LEVEL_LOW : 1;/*!< [8..8] GPIO_QSPI_SD0_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SD0_LEVEL_HIGH : 1;/*!< [9..9] GPIO_QSPI_SD0_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SD0_EDGE_LOW : 1;/*!< [10..10] GPIO_QSPI_SD0_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SD0_EDGE_HIGH : 1;/*!< [11..11] GPIO_QSPI_SD0_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SD1_LEVEL_LOW : 1;/*!< [12..12] GPIO_QSPI_SD1_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SD1_LEVEL_HIGH : 1;/*!< [13..13] GPIO_QSPI_SD1_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SD1_EDGE_LOW : 1;/*!< [14..14] GPIO_QSPI_SD1_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SD1_EDGE_HIGH : 1;/*!< [15..15] GPIO_QSPI_SD1_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SD2_LEVEL_LOW : 1;/*!< [16..16] GPIO_QSPI_SD2_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SD2_LEVEL_HIGH : 1;/*!< [17..17] GPIO_QSPI_SD2_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SD2_EDGE_LOW : 1;/*!< [18..18] GPIO_QSPI_SD2_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SD2_EDGE_HIGH : 1;/*!< [19..19] GPIO_QSPI_SD2_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SD3_LEVEL_LOW : 1;/*!< [20..20] GPIO_QSPI_SD3_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SD3_LEVEL_HIGH : 1;/*!< [21..21] GPIO_QSPI_SD3_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< [22..22] GPIO_QSPI_SD3_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< [23..23] GPIO_QSPI_SD3_EDGE_HIGH */ - uint32_t : 8; - } bit; - } DORMANT_WAKE_INTE; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000050) Interrupt Force for dormant_wake */ - - struct { - __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_LOW : 1;/*!< [0..0] GPIO_QSPI_SCLK_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SCLK_LEVEL_HIGH : 1;/*!< [1..1] GPIO_QSPI_SCLK_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SCLK_EDGE_LOW : 1;/*!< [2..2] GPIO_QSPI_SCLK_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SCLK_EDGE_HIGH : 1;/*!< [3..3] GPIO_QSPI_SCLK_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SS_LEVEL_LOW : 1;/*!< [4..4] GPIO_QSPI_SS_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SS_LEVEL_HIGH : 1;/*!< [5..5] GPIO_QSPI_SS_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SS_EDGE_LOW : 1; /*!< [6..6] GPIO_QSPI_SS_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SS_EDGE_HIGH : 1;/*!< [7..7] GPIO_QSPI_SS_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SD0_LEVEL_LOW : 1;/*!< [8..8] GPIO_QSPI_SD0_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SD0_LEVEL_HIGH : 1;/*!< [9..9] GPIO_QSPI_SD0_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SD0_EDGE_LOW : 1;/*!< [10..10] GPIO_QSPI_SD0_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SD0_EDGE_HIGH : 1;/*!< [11..11] GPIO_QSPI_SD0_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SD1_LEVEL_LOW : 1;/*!< [12..12] GPIO_QSPI_SD1_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SD1_LEVEL_HIGH : 1;/*!< [13..13] GPIO_QSPI_SD1_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SD1_EDGE_LOW : 1;/*!< [14..14] GPIO_QSPI_SD1_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SD1_EDGE_HIGH : 1;/*!< [15..15] GPIO_QSPI_SD1_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SD2_LEVEL_LOW : 1;/*!< [16..16] GPIO_QSPI_SD2_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SD2_LEVEL_HIGH : 1;/*!< [17..17] GPIO_QSPI_SD2_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SD2_EDGE_LOW : 1;/*!< [18..18] GPIO_QSPI_SD2_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SD2_EDGE_HIGH : 1;/*!< [19..19] GPIO_QSPI_SD2_EDGE_HIGH */ - __IOM uint32_t GPIO_QSPI_SD3_LEVEL_LOW : 1;/*!< [20..20] GPIO_QSPI_SD3_LEVEL_LOW */ - __IOM uint32_t GPIO_QSPI_SD3_LEVEL_HIGH : 1;/*!< [21..21] GPIO_QSPI_SD3_LEVEL_HIGH */ - __IOM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< [22..22] GPIO_QSPI_SD3_EDGE_LOW */ - __IOM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< [23..23] GPIO_QSPI_SD3_EDGE_HIGH */ - uint32_t : 8; - } bit; - } DORMANT_WAKE_INTF; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000054) Interrupt status after masking & forcing for + __IOM uint32_t DORMANT_WAKE_INTE; /*!< (@ 0x0000004C) Interrupt Enable for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTF; /*!< (@ 0x00000050) Interrupt Force for dormant_wake */ + __IOM uint32_t DORMANT_WAKE_INTS; /*!< (@ 0x00000054) Interrupt status after masking & forcing for dormant_wake */ - - struct { - __IM uint32_t GPIO_QSPI_SCLK_LEVEL_LOW : 1;/*!< [0..0] GPIO_QSPI_SCLK_LEVEL_LOW */ - __IM uint32_t GPIO_QSPI_SCLK_LEVEL_HIGH : 1;/*!< [1..1] GPIO_QSPI_SCLK_LEVEL_HIGH */ - __IM uint32_t GPIO_QSPI_SCLK_EDGE_LOW : 1;/*!< [2..2] GPIO_QSPI_SCLK_EDGE_LOW */ - __IM uint32_t GPIO_QSPI_SCLK_EDGE_HIGH : 1;/*!< [3..3] GPIO_QSPI_SCLK_EDGE_HIGH */ - __IM uint32_t GPIO_QSPI_SS_LEVEL_LOW : 1;/*!< [4..4] GPIO_QSPI_SS_LEVEL_LOW */ - __IM uint32_t GPIO_QSPI_SS_LEVEL_HIGH : 1;/*!< [5..5] GPIO_QSPI_SS_LEVEL_HIGH */ - __IM uint32_t GPIO_QSPI_SS_EDGE_LOW : 1; /*!< [6..6] GPIO_QSPI_SS_EDGE_LOW */ - __IM uint32_t GPIO_QSPI_SS_EDGE_HIGH : 1;/*!< [7..7] GPIO_QSPI_SS_EDGE_HIGH */ - __IM uint32_t GPIO_QSPI_SD0_LEVEL_LOW : 1;/*!< [8..8] GPIO_QSPI_SD0_LEVEL_LOW */ - __IM uint32_t GPIO_QSPI_SD0_LEVEL_HIGH : 1;/*!< [9..9] GPIO_QSPI_SD0_LEVEL_HIGH */ - __IM uint32_t GPIO_QSPI_SD0_EDGE_LOW : 1;/*!< [10..10] GPIO_QSPI_SD0_EDGE_LOW */ - __IM uint32_t GPIO_QSPI_SD0_EDGE_HIGH : 1;/*!< [11..11] GPIO_QSPI_SD0_EDGE_HIGH */ - __IM uint32_t GPIO_QSPI_SD1_LEVEL_LOW : 1;/*!< [12..12] GPIO_QSPI_SD1_LEVEL_LOW */ - __IM uint32_t GPIO_QSPI_SD1_LEVEL_HIGH : 1;/*!< [13..13] GPIO_QSPI_SD1_LEVEL_HIGH */ - __IM uint32_t GPIO_QSPI_SD1_EDGE_LOW : 1;/*!< [14..14] GPIO_QSPI_SD1_EDGE_LOW */ - __IM uint32_t GPIO_QSPI_SD1_EDGE_HIGH : 1;/*!< [15..15] GPIO_QSPI_SD1_EDGE_HIGH */ - __IM uint32_t GPIO_QSPI_SD2_LEVEL_LOW : 1;/*!< [16..16] GPIO_QSPI_SD2_LEVEL_LOW */ - __IM uint32_t GPIO_QSPI_SD2_LEVEL_HIGH : 1;/*!< [17..17] GPIO_QSPI_SD2_LEVEL_HIGH */ - __IM uint32_t GPIO_QSPI_SD2_EDGE_LOW : 1;/*!< [18..18] GPIO_QSPI_SD2_EDGE_LOW */ - __IM uint32_t GPIO_QSPI_SD2_EDGE_HIGH : 1;/*!< [19..19] GPIO_QSPI_SD2_EDGE_HIGH */ - __IM uint32_t GPIO_QSPI_SD3_LEVEL_LOW : 1;/*!< [20..20] GPIO_QSPI_SD3_LEVEL_LOW */ - __IM uint32_t GPIO_QSPI_SD3_LEVEL_HIGH : 1;/*!< [21..21] GPIO_QSPI_SD3_LEVEL_HIGH */ - __IM uint32_t GPIO_QSPI_SD3_EDGE_LOW : 1;/*!< [22..22] GPIO_QSPI_SD3_EDGE_LOW */ - __IM uint32_t GPIO_QSPI_SD3_EDGE_HIGH : 1;/*!< [23..23] GPIO_QSPI_SD3_EDGE_HIGH */ - uint32_t : 8; - } bit; - } DORMANT_WAKE_INTS; } IO_QSPI_Type; /*!< Size = 88 (0x58) */ @@ -5027,527 +649,39 @@ typedef struct { /*!< (@ 0x40018000) IO_QSPI Stru */ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 Structure */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Voltage select. Per bank control */ - - struct { - __IOM uint32_t VOLTAGE_SELECT : 1; /*!< [0..0] VOLTAGE_SELECT */ - uint32_t : 31; - } bit; - } VOLTAGE_SELECT; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO0; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000008) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO1; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO2; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000010) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO3; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000014) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO4; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000018) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO5; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO6; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000020) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO7; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000024) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO8; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000028) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO9; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000002C) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO10; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000030) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO11; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000034) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO12; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000038) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO13; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000003C) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO14; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000040) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO15; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000044) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO16; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000048) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO17; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000004C) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO18; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000050) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO19; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000054) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO20; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000058) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO21; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000005C) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO22; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000060) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO23; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000064) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO24; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000068) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO25; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000006C) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO26; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000070) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO27; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000074) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO28; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000078) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO29; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000007C) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } SWCLK; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000080) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } SWD; + __IOM uint32_t VOLTAGE_SELECT; /*!< (@ 0x00000000) Voltage select. Per bank control */ + __IOM uint32_t GPIO0; /*!< (@ 0x00000004) Pad control register */ + __IOM uint32_t GPIO1; /*!< (@ 0x00000008) Pad control register */ + __IOM uint32_t GPIO2; /*!< (@ 0x0000000C) Pad control register */ + __IOM uint32_t GPIO3; /*!< (@ 0x00000010) Pad control register */ + __IOM uint32_t GPIO4; /*!< (@ 0x00000014) Pad control register */ + __IOM uint32_t GPIO5; /*!< (@ 0x00000018) Pad control register */ + __IOM uint32_t GPIO6; /*!< (@ 0x0000001C) Pad control register */ + __IOM uint32_t GPIO7; /*!< (@ 0x00000020) Pad control register */ + __IOM uint32_t GPIO8; /*!< (@ 0x00000024) Pad control register */ + __IOM uint32_t GPIO9; /*!< (@ 0x00000028) Pad control register */ + __IOM uint32_t GPIO10; /*!< (@ 0x0000002C) Pad control register */ + __IOM uint32_t GPIO11; /*!< (@ 0x00000030) Pad control register */ + __IOM uint32_t GPIO12; /*!< (@ 0x00000034) Pad control register */ + __IOM uint32_t GPIO13; /*!< (@ 0x00000038) Pad control register */ + __IOM uint32_t GPIO14; /*!< (@ 0x0000003C) Pad control register */ + __IOM uint32_t GPIO15; /*!< (@ 0x00000040) Pad control register */ + __IOM uint32_t GPIO16; /*!< (@ 0x00000044) Pad control register */ + __IOM uint32_t GPIO17; /*!< (@ 0x00000048) Pad control register */ + __IOM uint32_t GPIO18; /*!< (@ 0x0000004C) Pad control register */ + __IOM uint32_t GPIO19; /*!< (@ 0x00000050) Pad control register */ + __IOM uint32_t GPIO20; /*!< (@ 0x00000054) Pad control register */ + __IOM uint32_t GPIO21; /*!< (@ 0x00000058) Pad control register */ + __IOM uint32_t GPIO22; /*!< (@ 0x0000005C) Pad control register */ + __IOM uint32_t GPIO23; /*!< (@ 0x00000060) Pad control register */ + __IOM uint32_t GPIO24; /*!< (@ 0x00000064) Pad control register */ + __IOM uint32_t GPIO25; /*!< (@ 0x00000068) Pad control register */ + __IOM uint32_t GPIO26; /*!< (@ 0x0000006C) Pad control register */ + __IOM uint32_t GPIO27; /*!< (@ 0x00000070) Pad control register */ + __IOM uint32_t GPIO28; /*!< (@ 0x00000074) Pad control register */ + __IOM uint32_t GPIO29; /*!< (@ 0x00000078) Pad control register */ + __IOM uint32_t SWCLK; /*!< (@ 0x0000007C) Pad control register */ + __IOM uint32_t SWD; /*!< (@ 0x00000080) Pad control register */ } PADS_BANK0_Type; /*!< Size = 132 (0x84) */ @@ -5562,111 +696,13 @@ typedef struct { /*!< (@ 0x4001C000) PADS_BANK0 S */ typedef struct { /*!< (@ 0x40020000) PADS_QSPI Structure */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Voltage select. Per bank control */ - - struct { - __IOM uint32_t VOLTAGE_SELECT : 1; /*!< [0..0] VOLTAGE_SELECT */ - uint32_t : 31; - } bit; - } VOLTAGE_SELECT; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO_QSPI_SCLK; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000008) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO_QSPI_SD0; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO_QSPI_SD1; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000010) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO_QSPI_SD2; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000014) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO_QSPI_SD3; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000018) Pad control register */ - - struct { - __IOM uint32_t SLEWFAST : 1; /*!< [0..0] Slew rate control. 1 = Fast, 0 = Slow */ - __IOM uint32_t SCHMITT : 1; /*!< [1..1] Enable schmitt trigger */ - __IOM uint32_t PDE : 1; /*!< [2..2] Pull down enable */ - __IOM uint32_t PUE : 1; /*!< [3..3] Pull up enable */ - __IOM uint32_t DRIVE : 2; /*!< [5..4] Drive strength. */ - __IOM uint32_t IE : 1; /*!< [6..6] Input enable */ - __IOM uint32_t OD : 1; /*!< [7..7] Output disable. Has priority over output enable from - peripherals */ - uint32_t : 24; - } bit; - } GPIO_QSPI_SS; + __IOM uint32_t VOLTAGE_SELECT; /*!< (@ 0x00000000) Voltage select. Per bank control */ + __IOM uint32_t GPIO_QSPI_SCLK; /*!< (@ 0x00000004) Pad control register */ + __IOM uint32_t GPIO_QSPI_SD0; /*!< (@ 0x00000008) Pad control register */ + __IOM uint32_t GPIO_QSPI_SD1; /*!< (@ 0x0000000C) Pad control register */ + __IOM uint32_t GPIO_QSPI_SD2; /*!< (@ 0x00000010) Pad control register */ + __IOM uint32_t GPIO_QSPI_SD3; /*!< (@ 0x00000014) Pad control register */ + __IOM uint32_t GPIO_QSPI_SS; /*!< (@ 0x00000018) Pad control register */ } PADS_QSPI_Type; /*!< Size = 28 (0x1c) */ @@ -5681,40 +717,8 @@ typedef struct { /*!< (@ 0x40020000) PADS_QSPI St */ typedef struct { /*!< (@ 0x40024000) XOSC Structure */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Crystal Oscillator Control */ - - struct { - __IOM uint32_t FREQ_RANGE : 12; /*!< [11..0] Frequency range. This resets to 0xAA0 and cannot be - changed. */ - __IOM uint32_t ENABLE : 12; /*!< [23..12] On power-up this field is initialised to DISABLE and - the chip runs from the ROSC. - If the chip has subsequently been programmed to run from - the XOSC then setting this field to DISABLE may lock-up - the chip. If this is a concern then run the clk_ref from - the ROSC and enable the clk_sys RESUS feature. - The 12-bit code is intended to give some protection against - accidental writes. An invalid setting will enable the oscillator. */ - uint32_t : 8; - } bit; - } CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Crystal Oscillator Status */ - - struct { - __IM uint32_t FREQ_RANGE : 2; /*!< [1..0] The current frequency range setting, always reads 0 */ - uint32_t : 10; - __IM uint32_t ENABLED : 1; /*!< [12..12] Oscillator is enabled but not necessarily running and - stable, resets to 0 */ - uint32_t : 11; - __IOM uint32_t BADWRITE : 1; /*!< [24..24] An invalid value has been written to CTRL_ENABLE or - CTRL_FREQ_RANGE or DORMANT */ - uint32_t : 6; - __IM uint32_t STABLE : 1; /*!< [31..31] Oscillator is running and stable */ - } bit; - } STATUS; + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Crystal Oscillator Control */ + __IOM uint32_t STATUS; /*!< (@ 0x00000004) Crystal Oscillator Status */ __IOM uint32_t DORMANT; /*!< (@ 0x00000008) Crystal Oscillator pause control This is used to save power by pausing the XOSC @@ -5725,33 +729,13 @@ typedef struct { /*!< (@ 0x40024000) XOSC Structu dormant mode WARNING: setup the irq before selecting dormant mode */ - - union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) Controls the startup delay */ - - struct { - __IOM uint32_t DELAY : 14; /*!< [13..0] in multiples of 256*xtal_period */ - uint32_t : 6; - __IOM uint32_t X4 : 1; /*!< [20..20] Multiplies the startup_delay by 4. This is of little - value to the user given that the delay can be programmed - directly */ - uint32_t : 11; - } bit; - } STARTUP; + __IOM uint32_t STARTUP; /*!< (@ 0x0000000C) Controls the startup delay */ __IM uint32_t RESERVED[3]; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) A down counter running at the xosc frequency + __IOM uint32_t COUNT; /*!< (@ 0x0000001C) A down counter running at the xosc frequency which counts to zero and stops. To start the counter write a non-zero value. Can be used for short software pauses when setting up time sensitive hardware. */ - - struct { - __IOM uint32_t COUNT : 8; /*!< [7..0] COUNT */ - uint32_t : 24; - } bit; - } COUNT; } XOSC_Type; /*!< Size = 32 (0x20) */ @@ -5766,76 +750,21 @@ typedef struct { /*!< (@ 0x40024000) XOSC Structu */ typedef struct { /*!< (@ 0x40028000) PLL_SYS Structure */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Control and Status + __IOM uint32_t CS; /*!< (@ 0x00000000) Control and Status GENERAL CONSTRAINTS: Reference clock frequency min=5MHz, max=800MHz Feedback divider min=16, max=320 - VCO frequency min=400MHz, max=1600MHz */ - - struct { - __IOM uint32_t REFDIV : 6; /*!< [5..0] Divides the PLL input reference clock. - Behaviour is undefined for div=0. - PLL output will be unpredictable during refdiv changes, - wait for lock=1 before using it. */ - uint32_t : 2; - __IOM uint32_t BYPASS : 1; /*!< [8..8] Passes the reference clock to the output instead of the - divided VCO. The VCO continues to run so the user can switch - between the reference clock and the divided VCO but the - output will glitch when doing so. */ - uint32_t : 22; - __IM uint32_t LOCK : 1; /*!< [31..31] PLL is locked */ - } bit; - } CS; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Controls the PLL power modes. */ - - struct { - __IOM uint32_t PD : 1; /*!< [0..0] PLL powerdown - To save power set high when PLL output not required. */ - uint32_t : 1; - __IOM uint32_t DSMPD : 1; /*!< [2..2] PLL DSM powerdown - Nothing is achieved by setting this low. */ - __IOM uint32_t POSTDIVPD : 1; /*!< [3..3] PLL post divider powerdown - To save power set high when PLL output not required or - bypass=1. */ - uint32_t : 1; - __IOM uint32_t VCOPD : 1; /*!< [5..5] PLL VCO powerdown - To save power set high when PLL output not required or - bypass=1. */ - uint32_t : 26; - } bit; - } PWR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000008) Feedback divisor + VCO frequency min=750MHz, max=1600MHz */ + __IOM uint32_t PWR; /*!< (@ 0x00000004) Controls the PLL power modes. */ + __IOM uint32_t FBDIV_INT; /*!< (@ 0x00000008) Feedback divisor (note: this PLL does not support fractional division) */ - - struct { - __IOM uint32_t FBDIV_INT : 12; /*!< [11..0] see ctrl reg description for constraints */ - uint32_t : 20; - } bit; - } FBDIV_INT; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) Controls the PLL post dividers for the primary + __IOM uint32_t PRIM; /*!< (@ 0x0000000C) Controls the PLL post dividers for the primary output (note: this PLL does not have a secondary output) the primary output is driven from VCO divided by postdiv1*postdiv2 */ - - struct { - uint32_t : 12; - __IOM uint32_t POSTDIV2 : 3; /*!< [14..12] divide by 1-7 */ - uint32_t : 1; - __IOM uint32_t POSTDIV1 : 3; /*!< [18..16] divide by 1-7 */ - uint32_t : 13; - } bit; - } PRIM; } PLL_SYS_Type; /*!< Size = 16 (0x10) */ @@ -5850,118 +779,16 @@ typedef struct { /*!< (@ 0x40028000) PLL_SYS Stru */ typedef struct { /*!< (@ 0x40030000) BUSCTRL Structure */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Set the priority of each master for bus arbitration. */ - - struct { - __IOM uint32_t PROC0 : 1; /*!< [0..0] 0 - low priority, 1 - high priority */ - uint32_t : 3; - __IOM uint32_t PROC1 : 1; /*!< [4..4] 0 - low priority, 1 - high priority */ - uint32_t : 3; - __IOM uint32_t DMA_R : 1; /*!< [8..8] 0 - low priority, 1 - high priority */ - uint32_t : 3; - __IOM uint32_t DMA_W : 1; /*!< [12..12] 0 - low priority, 1 - high priority */ - uint32_t : 19; - } bit; - } BUS_PRIORITY; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Bus priority acknowledge */ - - struct { - __IM uint32_t BUS_PRIORITY_ACK : 1; /*!< [0..0] Goes to 1 once all arbiters have registered the new global - priority levels. - Arbiters update their local priority when servicing a new - nonsequential access. - In normal circumstances this will happen almost immediately. */ - uint32_t : 31; - } bit; - } BUS_PRIORITY_ACK; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000008) Bus fabric performance counter 0 */ - - struct { - __IOM uint32_t PERFCTR0 : 24; /*!< [23..0] Busfabric saturating performance counter 0 - Count some event signal from the busfabric arbiters. - Write any value to clear. Select an event to count using - PERFSEL0 */ - uint32_t : 8; - } bit; - } PERFCTR0; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) Bus fabric performance event select for PERFCTR0 */ - - struct { - __IOM uint32_t PERFSEL0 : 5; /*!< [4..0] Select a performance event for PERFCTR0 */ - uint32_t : 27; - } bit; - } PERFSEL0; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000010) Bus fabric performance counter 1 */ - - struct { - __IOM uint32_t PERFCTR1 : 24; /*!< [23..0] Busfabric saturating performance counter 1 - Count some event signal from the busfabric arbiters. - Write any value to clear. Select an event to count using - PERFSEL1 */ - uint32_t : 8; - } bit; - } PERFCTR1; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000014) Bus fabric performance event select for PERFCTR1 */ - - struct { - __IOM uint32_t PERFSEL1 : 5; /*!< [4..0] Select a performance event for PERFCTR1 */ - uint32_t : 27; - } bit; - } PERFSEL1; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000018) Bus fabric performance counter 2 */ - - struct { - __IOM uint32_t PERFCTR2 : 24; /*!< [23..0] Busfabric saturating performance counter 2 - Count some event signal from the busfabric arbiters. - Write any value to clear. Select an event to count using - PERFSEL2 */ - uint32_t : 8; - } bit; - } PERFCTR2; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) Bus fabric performance event select for PERFCTR2 */ - - struct { - __IOM uint32_t PERFSEL2 : 5; /*!< [4..0] Select a performance event for PERFCTR2 */ - uint32_t : 27; - } bit; - } PERFSEL2; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000020) Bus fabric performance counter 3 */ - - struct { - __IOM uint32_t PERFCTR3 : 24; /*!< [23..0] Busfabric saturating performance counter 3 - Count some event signal from the busfabric arbiters. - Write any value to clear. Select an event to count using - PERFSEL3 */ - uint32_t : 8; - } bit; - } PERFCTR3; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000024) Bus fabric performance event select for PERFCTR3 */ - - struct { - __IOM uint32_t PERFSEL3 : 5; /*!< [4..0] Select a performance event for PERFCTR3 */ - uint32_t : 27; - } bit; - } PERFSEL3; + __IOM uint32_t BUS_PRIORITY; /*!< (@ 0x00000000) Set the priority of each master for bus arbitration. */ + __IOM uint32_t BUS_PRIORITY_ACK; /*!< (@ 0x00000004) Bus priority acknowledge */ + __IOM uint32_t PERFCTR0; /*!< (@ 0x00000008) Bus fabric performance counter 0 */ + __IOM uint32_t PERFSEL0; /*!< (@ 0x0000000C) Bus fabric performance event select for PERFCTR0 */ + __IOM uint32_t PERFCTR1; /*!< (@ 0x00000010) Bus fabric performance counter 1 */ + __IOM uint32_t PERFSEL1; /*!< (@ 0x00000014) Bus fabric performance event select for PERFCTR1 */ + __IOM uint32_t PERFCTR2; /*!< (@ 0x00000018) Bus fabric performance counter 2 */ + __IOM uint32_t PERFSEL2; /*!< (@ 0x0000001C) Bus fabric performance event select for PERFCTR2 */ + __IOM uint32_t PERFCTR3; /*!< (@ 0x00000020) Bus fabric performance counter 3 */ + __IOM uint32_t PERFSEL3; /*!< (@ 0x00000024) Bus fabric performance event select for PERFCTR3 */ } BUSCTRL_Type; /*!< Size = 40 (0x28) */ @@ -5976,516 +803,32 @@ typedef struct { /*!< (@ 0x40030000) BUSCTRL Stru */ typedef struct { /*!< (@ 0x40034000) UART0 Structure */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Data Register, UARTDR */ - - struct { - __IOM uint32_t DATA : 8; /*!< [7..0] Receive (read) data character. Transmit (write) data - character. */ - __IM uint32_t FE : 1; /*!< [8..8] Framing error. When set to 1, it indicates that the received - character did not have a valid stop bit (a valid stop bit - is 1). In FIFO mode, this error is associated with the - character at the top of the FIFO. */ - __IM uint32_t PE : 1; /*!< [9..9] Parity error. When set to 1, it indicates that the parity - of the received data character does not match the parity - that the EPS and SPS bits in the Line Control Register, - UARTLCR_H. In FIFO mode, this error is associated with - the character at the top of the FIFO. */ - __IM uint32_t BE : 1; /*!< [10..10] Break error. This bit is set to 1 if a break condition - was detected, indicating that the received data input was - held LOW for longer than a full-word transmission time - (defined as start, data, parity and stop bits). In FIFO - mode, this error is associated with the character at the - top of the FIFO. When a break occurs, only one 0 character - is loaded into the FIFO. The next character is only enabled - after the receive data input goes to a 1 (marking state), - and the next valid start bit is received. */ - __IM uint32_t OE : 1; /*!< [11..11] Overrun error. This bit is set to 1 if data is received - and the receive FIFO is already full. This is cleared to - 0 once there is an empty space in the FIFO and a new character - can be written to it. */ - uint32_t : 20; - } bit; - } UARTDR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Receive Status Register/Error Clear Register, + __IOM uint32_t UARTDR; /*!< (@ 0x00000000) Data Register, UARTDR */ + __IOM uint32_t UARTRSR; /*!< (@ 0x00000004) Receive Status Register/Error Clear Register, UARTRSR/UARTECR */ - - struct { - __IOM uint32_t FE : 1; /*!< [0..0] Framing error. When set to 1, it indicates that the received - character did not have a valid stop bit (a valid stop bit - is 1). This bit is cleared to 0 by a write to UARTECR. - In FIFO mode, this error is associated with the character - at the top of the FIFO. */ - __IOM uint32_t PE : 1; /*!< [1..1] Parity error. When set to 1, it indicates that the parity - of the received data character does not match the parity - that the EPS and SPS bits in the Line Control Register, - UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. - In FIFO mode, this error is associated with the character - at the top of the FIFO. */ - __IOM uint32_t BE : 1; /*!< [2..2] Break error. This bit is set to 1 if a break condition - was detected, indicating that the received data input was - held LOW for longer than a full-word transmission time - (defined as start, data, parity, and stop bits). This bit - is cleared to 0 after a write to UARTECR. In FIFO mode, - this error is associated with the character at the top - of the FIFO. When a break occurs, only one 0 character - is loaded into the FIFO. The next character is only enabled - after the receive data input goes to a 1 (marking state) - */ - __IOM uint32_t OE : 1; /*!< [3..3] Overrun error. This bit is set to 1 if data is received - and the FIFO is already full. This bit is cleared to 0 - by a write to UARTECR. The FIFO contents remain valid because - no more data is written when the FIFO is full, only the - contents of the shift register are overwritten. The CPU - must now read the data, to empty the FIFO. */ - uint32_t : 28; - } bit; - } UARTRSR; __IM uint32_t RESERVED[4]; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000018) Flag Register, UARTFR */ - - struct { - __IM uint32_t CTS : 1; /*!< [0..0] Clear to send. This bit is the complement of the UART - clear to send, nUARTCTS, modem status input. That is, the - bit is 1 when nUARTCTS is LOW. */ - __IM uint32_t DSR : 1; /*!< [1..1] Data set ready. This bit is the complement of the UART - data set ready, nUARTDSR, modem status input. That is, - the bit is 1 when nUARTDSR is LOW. */ - __IM uint32_t DCD : 1; /*!< [2..2] Data carrier detect. This bit is the complement of the - UART data carrier detect, nUARTDCD, modem status input. - That is, the bit is 1 when nUARTDCD is LOW. */ - __IM uint32_t BUSY : 1; /*!< [3..3] UART busy. If this bit is set to 1, the UART is busy - transmitting data. This bit remains set until the complete - byte, including all the stop bits, has been sent from the - shift register. This bit is set as soon as the transmit - FIFO becomes non-empty, regardless of whether the UART - is enabled or not. */ - __IM uint32_t RXFE : 1; /*!< [4..4] Receive FIFO empty. The meaning of this bit depends on - the state of the FEN bit in the UARTLCR_H Register. If - the FIFO is disabled, this bit is set when the receive - holding register is empty. If the FIFO is enabled, the - RXFE bit is set when the receive FIFO is empty. */ - __IM uint32_t TXFF : 1; /*!< [5..5] Transmit FIFO full. The meaning of this bit depends on - the state of the FEN bit in the UARTLCR_H Register. If - the FIFO is disabled, this bit is set when the transmit - holding register is full. If the FIFO is enabled, the TXFF - bit is set when the transmit FIFO is full. */ - __IM uint32_t RXFF : 1; /*!< [6..6] Receive FIFO full. The meaning of this bit depends on - the state of the FEN bit in the UARTLCR_H Register. If - the FIFO is disabled, this bit is set when the receive - holding register is full. If the FIFO is enabled, the RXFF - bit is set when the receive FIFO is full. */ - __IM uint32_t TXFE : 1; /*!< [7..7] Transmit FIFO empty. The meaning of this bit depends - on the state of the FEN bit in the Line Control Register, - UARTLCR_H. If the FIFO is disabled, this bit is set when - the transmit holding register is empty. If the FIFO is - enabled, the TXFE bit is set when the transmit FIFO is - empty. This bit does not indicate if there is data in the - transmit shift register. */ - __IM uint32_t RI : 1; /*!< [8..8] Ring indicator. This bit is the complement of the UART - ring indicator, nUARTRI, modem status input. That is, the - bit is 1 when nUARTRI is LOW. */ - uint32_t : 23; - } bit; - } UARTFR; + __IOM uint32_t UARTFR; /*!< (@ 0x00000018) Flag Register, UARTFR */ __IM uint32_t RESERVED1; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000020) IrDA Low-Power Counter Register, UARTILPR */ - - struct { - __IOM uint32_t ILPDVSR : 8; /*!< [7..0] 8-bit low-power divisor value. These bits are cleared - to 0 at reset. */ - uint32_t : 24; - } bit; - } UARTILPR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000024) Integer Baud Rate Register, UARTIBRD */ - - struct { - __IOM uint32_t BAUD_DIVINT : 16; /*!< [15..0] The integer baud rate divisor. These bits are cleared - to 0 on reset. */ - uint32_t : 16; - } bit; - } UARTIBRD; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000028) Fractional Baud Rate Register, UARTFBRD */ - - struct { - __IOM uint32_t BAUD_DIVFRAC : 6; /*!< [5..0] The fractional baud rate divisor. These bits are cleared - to 0 on reset. */ - uint32_t : 26; - } bit; - } UARTFBRD; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000002C) Line Control Register, UARTLCR_H */ - - struct { - __IOM uint32_t BRK : 1; /*!< [0..0] Send break. If this bit is set to 1, a low-level is continually - output on the UARTTXD output, after completing transmission - of the current character. For the proper execution of the - break command, the software must set this bit for at least - two complete frames. For normal use, this bit must be cleared - to 0. */ - __IOM uint32_t PEN : 1; /*!< [1..1] Parity enable: 0 = parity is disabled and no parity bit - added to the data frame 1 = parity checking and generation - is enabled. */ - __IOM uint32_t EPS : 1; /*!< [2..2] Even parity select. Controls the type of parity the UART - uses during transmission and reception: 0 = odd parity. - The UART generates or checks for an odd number of 1s in - the data and parity bits. 1 = even parity. The UART generates - or checks for an even number of 1s in the data and parity - bits. This bit has no effect when the PEN bit disables - parity checking and generation. */ - __IOM uint32_t STP2 : 1; /*!< [3..3] Two stop bits select. If this bit is set to 1, two stop - bits are transmitted at the end of the frame. The receive - logic does not check for two stop bits being received. */ - __IOM uint32_t FEN : 1; /*!< [4..4] Enable FIFOs: 0 = FIFOs are disabled (character mode) - that is, the FIFOs become 1-byte-deep holding registers - 1 = transmit and receive FIFO buffers are enabled (FIFO - mode). */ - __IOM uint32_t WLEN : 2; /*!< [6..5] Word length. These bits indicate the number of data bits - transmitted or received in a frame as follows: b11 = 8 - bits b10 = 7 bits b01 = 6 bits b00 = 5 bits. */ - __IOM uint32_t SPS : 1; /*!< [7..7] Stick parity select. 0 = stick parity is disabled 1 = - either: * if the EPS bit is 0 then the parity bit is transmitted - and checked as a 1 * if the EPS bit is 1 then the parity - bit is transmitted and checked as a 0. This bit has no - effect when the PEN bit disables parity checking and generation. */ - uint32_t : 24; - } bit; - } UARTLCR_H; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000030) Control Register, UARTCR */ - - struct { - __IOM uint32_t UARTEN : 1; /*!< [0..0] UART enable: 0 = UART is disabled. If the UART is disabled - in the middle of transmission or reception, it completes - the current character before stopping. 1 = the UART is - enabled. Data transmission and reception occurs for either - UART signals or SIR signals depending on the setting of - the SIREN bit. */ - __IOM uint32_t SIREN : 1; /*!< [1..1] SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains - LOW (no light pulse generated), and signal transitions - on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. - Data is transmitted and received on nSIROUT and SIRIN. - UARTTXD remains HIGH, in the marking state. Signal transitions - on UARTRXD or modem status inputs have no effect. This - bit has no effect if the UARTEN bit disables the UART. */ - __IOM uint32_t SIRLP : 1; /*!< [2..2] SIR low-power IrDA mode. This bit selects the IrDA encoding - mode. If this bit is cleared to 0, low-level bits are transmitted - as an active high pulse with a width of 3 / 16th of the - bit period. If this bit is set to 1, low-level bits are - transmitted with a pulse width that is 3 times the period - of the IrLPBaud16 input signal, regardless of the selected - bit rate. Setting this bit uses less power, but might reduce - transmission distances. */ - uint32_t : 4; - __IOM uint32_t LBE : 1; /*!< [7..7] Loopback enable. If this bit is set to 1 and the SIREN - bit is set to 1 and the SIRTEST bit in the Test Control - Register, UARTTCR is set to 1, then the nSIROUT path is - inverted, and fed through to the SIRIN path. The SIRTEST - bit in the test register must be set to 1 to override the - normal half-duplex SIR operation. This must be the requirement - for accessing the test registers during normal operation, - and SIRTEST must be cleared to 0 when loopback testing - is finished. This feature reduces the amount of ext */ - __IOM uint32_t TXE : 1; /*!< [8..8] Transmit enable. If this bit is set to 1, the transmit - section of the UART is enabled. Data transmission occurs - for either UART signals, or SIR signals depending on the - setting of the SIREN bit. When the UART is disabled in - the middle of transmission, it completes the current character - before stopping. */ - __IOM uint32_t RXE : 1; /*!< [9..9] Receive enable. If this bit is set to 1, the receive - section of the UART is enabled. Data reception occurs for - either UART signals or SIR signals depending on the setting - of the SIREN bit. When the UART is disabled in the middle - of reception, it completes the current character before - stopping. */ - __IOM uint32_t DTR : 1; /*!< [10..10] Data transmit ready. This bit is the complement of - the UART data transmit ready, nUARTDTR, modem status output. - That is, when the bit is programmed to a 1 then nUARTDTR - is LOW. */ - __IOM uint32_t RTS : 1; /*!< [11..11] Request to send. This bit is the complement of the - UART request to send, nUARTRTS, modem status output. That - is, when the bit is programmed to a 1 then nUARTRTS is - LOW. */ - __IOM uint32_t OUT1 : 1; /*!< [12..12] This bit is the complement of the UART Out1 (nUARTOut1) - modem status output. That is, when the bit is programmed - to a 1 the output is 0. For DTE this can be used as Data - Carrier Detect (DCD). */ - __IOM uint32_t OUT2 : 1; /*!< [13..13] This bit is the complement of the UART Out2 (nUARTOut2) - modem status output. That is, when the bit is programmed - to a 1, the output is 0. For DTE this can be used as Ring - Indicator (RI). */ - __IOM uint32_t RTSEN : 1; /*!< [14..14] RTS hardware flow control enable. If this bit is set - to 1, RTS hardware flow control is enabled. Data is only - requested when there is space in the receive FIFO for it - to be received. */ - __IOM uint32_t CTSEN : 1; /*!< [15..15] CTS hardware flow control enable. If this bit is set - to 1, CTS hardware flow control is enabled. Data is only - transmitted when the nUARTCTS signal is asserted. */ - uint32_t : 16; - } bit; - } UARTCR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000034) Interrupt FIFO Level Select Register, UARTIFLS */ - - struct { - __IOM uint32_t TXIFLSEL : 3; /*!< [2..0] Transmit interrupt FIFO level select. The trigger points - for the transmit interrupt are as follows: b000 = Transmit - FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes - <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full - b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit - FIFO becomes <= 7 / 8 full b101-b111 = reserved. */ - __IOM uint32_t RXIFLSEL : 3; /*!< [5..3] Receive interrupt FIFO level select. The trigger points - for the receive interrupt are as follows: b000 = Receive - FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes - >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full - b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive - FIFO becomes >= 7 / 8 full b101-b111 = reserved. */ - uint32_t : 26; - } bit; - } UARTIFLS; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000038) Interrupt Mask Set/Clear Register, UARTIMSC */ - - struct { - __IOM uint32_t RIMIM : 1; /*!< [0..0] nUARTRI modem interrupt mask. A read returns the current - mask for the UARTRIINTR interrupt. On a write of 1, the - mask of the UARTRIINTR interrupt is set. A write of 0 clears - the mask. */ - __IOM uint32_t CTSMIM : 1; /*!< [1..1] nUARTCTS modem interrupt mask. A read returns the current - mask for the UARTCTSINTR interrupt. On a write of 1, the - mask of the UARTCTSINTR interrupt is set. A write of 0 - clears the mask. */ - __IOM uint32_t DCDMIM : 1; /*!< [2..2] nUARTDCD modem interrupt mask. A read returns the current - mask for the UARTDCDINTR interrupt. On a write of 1, the - mask of the UARTDCDINTR interrupt is set. A write of 0 - clears the mask. */ - __IOM uint32_t DSRMIM : 1; /*!< [3..3] nUARTDSR modem interrupt mask. A read returns the current - mask for the UARTDSRINTR interrupt. On a write of 1, the - mask of the UARTDSRINTR interrupt is set. A write of 0 - clears the mask. */ - __IOM uint32_t RXIM : 1; /*!< [4..4] Receive interrupt mask. A read returns the current mask - for the UARTRXINTR interrupt. On a write of 1, the mask - of the UARTRXINTR interrupt is set. A write of 0 clears - the mask. */ - __IOM uint32_t TXIM : 1; /*!< [5..5] Transmit interrupt mask. A read returns the current mask - for the UARTTXINTR interrupt. On a write of 1, the mask - of the UARTTXINTR interrupt is set. A write of 0 clears - the mask. */ - __IOM uint32_t RTIM : 1; /*!< [6..6] Receive timeout interrupt mask. A read returns the current - mask for the UARTRTINTR interrupt. On a write of 1, the - mask of the UARTRTINTR interrupt is set. A write of 0 clears - the mask. */ - __IOM uint32_t FEIM : 1; /*!< [7..7] Framing error interrupt mask. A read returns the current - mask for the UARTFEINTR interrupt. On a write of 1, the - mask of the UARTFEINTR interrupt is set. A write of 0 clears - the mask. */ - __IOM uint32_t PEIM : 1; /*!< [8..8] Parity error interrupt mask. A read returns the current - mask for the UARTPEINTR interrupt. On a write of 1, the - mask of the UARTPEINTR interrupt is set. A write of 0 clears - the mask. */ - __IOM uint32_t BEIM : 1; /*!< [9..9] Break error interrupt mask. A read returns the current - mask for the UARTBEINTR interrupt. On a write of 1, the - mask of the UARTBEINTR interrupt is set. A write of 0 clears - the mask. */ - __IOM uint32_t OEIM : 1; /*!< [10..10] Overrun error interrupt mask. A read returns the current - mask for the UARTOEINTR interrupt. On a write of 1, the - mask of the UARTOEINTR interrupt is set. A write of 0 clears - the mask. */ - uint32_t : 21; - } bit; - } UARTIMSC; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000003C) Raw Interrupt Status Register, UARTRIS */ - - struct { - __IM uint32_t RIRMIS : 1; /*!< [0..0] nUARTRI modem interrupt status. Returns the raw interrupt - state of the UARTRIINTR interrupt. */ - __IM uint32_t CTSRMIS : 1; /*!< [1..1] nUARTCTS modem interrupt status. Returns the raw interrupt - state of the UARTCTSINTR interrupt. */ - __IM uint32_t DCDRMIS : 1; /*!< [2..2] nUARTDCD modem interrupt status. Returns the raw interrupt - state of the UARTDCDINTR interrupt. */ - __IM uint32_t DSRRMIS : 1; /*!< [3..3] nUARTDSR modem interrupt status. Returns the raw interrupt - state of the UARTDSRINTR interrupt. */ - __IM uint32_t RXRIS : 1; /*!< [4..4] Receive interrupt status. Returns the raw interrupt state - of the UARTRXINTR interrupt. */ - __IM uint32_t TXRIS : 1; /*!< [5..5] Transmit interrupt status. Returns the raw interrupt - state of the UARTTXINTR interrupt. */ - __IM uint32_t RTRIS : 1; /*!< [6..6] Receive timeout interrupt status. Returns the raw interrupt - state of the UARTRTINTR interrupt. a */ - __IM uint32_t FERIS : 1; /*!< [7..7] Framing error interrupt status. Returns the raw interrupt - state of the UARTFEINTR interrupt. */ - __IM uint32_t PERIS : 1; /*!< [8..8] Parity error interrupt status. Returns the raw interrupt - state of the UARTPEINTR interrupt. */ - __IM uint32_t BERIS : 1; /*!< [9..9] Break error interrupt status. Returns the raw interrupt - state of the UARTBEINTR interrupt. */ - __IM uint32_t OERIS : 1; /*!< [10..10] Overrun error interrupt status. Returns the raw interrupt - state of the UARTOEINTR interrupt. */ - uint32_t : 21; - } bit; - } UARTRIS; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000040) Masked Interrupt Status Register, UARTMIS */ - - struct { - __IM uint32_t RIMMIS : 1; /*!< [0..0] nUARTRI modem masked interrupt status. Returns the masked - interrupt state of the UARTRIINTR interrupt. */ - __IM uint32_t CTSMMIS : 1; /*!< [1..1] nUARTCTS modem masked interrupt status. Returns the masked - interrupt state of the UARTCTSINTR interrupt. */ - __IM uint32_t DCDMMIS : 1; /*!< [2..2] nUARTDCD modem masked interrupt status. Returns the masked - interrupt state of the UARTDCDINTR interrupt. */ - __IM uint32_t DSRMMIS : 1; /*!< [3..3] nUARTDSR modem masked interrupt status. Returns the masked - interrupt state of the UARTDSRINTR interrupt. */ - __IM uint32_t RXMIS : 1; /*!< [4..4] Receive masked interrupt status. Returns the masked interrupt - state of the UARTRXINTR interrupt. */ - __IM uint32_t TXMIS : 1; /*!< [5..5] Transmit masked interrupt status. Returns the masked - interrupt state of the UARTTXINTR interrupt. */ - __IM uint32_t RTMIS : 1; /*!< [6..6] Receive timeout masked interrupt status. Returns the - masked interrupt state of the UARTRTINTR interrupt. */ - __IM uint32_t FEMIS : 1; /*!< [7..7] Framing error masked interrupt status. Returns the masked - interrupt state of the UARTFEINTR interrupt. */ - __IM uint32_t PEMIS : 1; /*!< [8..8] Parity error masked interrupt status. Returns the masked - interrupt state of the UARTPEINTR interrupt. */ - __IM uint32_t BEMIS : 1; /*!< [9..9] Break error masked interrupt status. Returns the masked - interrupt state of the UARTBEINTR interrupt. */ - __IM uint32_t OEMIS : 1; /*!< [10..10] Overrun error masked interrupt status. Returns the - masked interrupt state of the UARTOEINTR interrupt. */ - uint32_t : 21; - } bit; - } UARTMIS; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000044) Interrupt Clear Register, UARTICR */ - - struct { - __IOM uint32_t RIMIC : 1; /*!< [0..0] nUARTRI modem interrupt clear. Clears the UARTRIINTR - interrupt. */ - __IOM uint32_t CTSMIC : 1; /*!< [1..1] nUARTCTS modem interrupt clear. Clears the UARTCTSINTR - interrupt. */ - __IOM uint32_t DCDMIC : 1; /*!< [2..2] nUARTDCD modem interrupt clear. Clears the UARTDCDINTR - interrupt. */ - __IOM uint32_t DSRMIC : 1; /*!< [3..3] nUARTDSR modem interrupt clear. Clears the UARTDSRINTR - interrupt. */ - __IOM uint32_t RXIC : 1; /*!< [4..4] Receive interrupt clear. Clears the UARTRXINTR interrupt. */ - __IOM uint32_t TXIC : 1; /*!< [5..5] Transmit interrupt clear. Clears the UARTTXINTR interrupt. */ - __IOM uint32_t RTIC : 1; /*!< [6..6] Receive timeout interrupt clear. Clears the UARTRTINTR - interrupt. */ - __IOM uint32_t FEIC : 1; /*!< [7..7] Framing error interrupt clear. Clears the UARTFEINTR - interrupt. */ - __IOM uint32_t PEIC : 1; /*!< [8..8] Parity error interrupt clear. Clears the UARTPEINTR interrupt. */ - __IOM uint32_t BEIC : 1; /*!< [9..9] Break error interrupt clear. Clears the UARTBEINTR interrupt. */ - __IOM uint32_t OEIC : 1; /*!< [10..10] Overrun error interrupt clear. Clears the UARTOEINTR - interrupt. */ - uint32_t : 21; - } bit; - } UARTICR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000048) DMA Control Register, UARTDMACR */ - - struct { - __IOM uint32_t RXDMAE : 1; /*!< [0..0] Receive DMA enable. If this bit is set to 1, DMA for - the receive FIFO is enabled. */ - __IOM uint32_t TXDMAE : 1; /*!< [1..1] Transmit DMA enable. If this bit is set to 1, DMA for - the transmit FIFO is enabled. */ - __IOM uint32_t DMAONERR : 1; /*!< [2..2] DMA on error. If this bit is set to 1, the DMA receive - request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled - when the UART error interrupt is asserted. */ - uint32_t : 29; - } bit; - } UARTDMACR; + __IOM uint32_t UARTILPR; /*!< (@ 0x00000020) IrDA Low-Power Counter Register, UARTILPR */ + __IOM uint32_t UARTIBRD; /*!< (@ 0x00000024) Integer Baud Rate Register, UARTIBRD */ + __IOM uint32_t UARTFBRD; /*!< (@ 0x00000028) Fractional Baud Rate Register, UARTFBRD */ + __IOM uint32_t UARTLCR_H; /*!< (@ 0x0000002C) Line Control Register, UARTLCR_H */ + __IOM uint32_t UARTCR; /*!< (@ 0x00000030) Control Register, UARTCR */ + __IOM uint32_t UARTIFLS; /*!< (@ 0x00000034) Interrupt FIFO Level Select Register, UARTIFLS */ + __IOM uint32_t UARTIMSC; /*!< (@ 0x00000038) Interrupt Mask Set/Clear Register, UARTIMSC */ + __IOM uint32_t UARTRIS; /*!< (@ 0x0000003C) Raw Interrupt Status Register, UARTRIS */ + __IOM uint32_t UARTMIS; /*!< (@ 0x00000040) Masked Interrupt Status Register, UARTMIS */ + __IOM uint32_t UARTICR; /*!< (@ 0x00000044) Interrupt Clear Register, UARTICR */ + __IOM uint32_t UARTDMACR; /*!< (@ 0x00000048) DMA Control Register, UARTDMACR */ __IM uint32_t RESERVED2[997]; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000FE0) UARTPeriphID0 Register */ - - struct { - __IM uint32_t PARTNUMBER0 : 8; /*!< [7..0] These bits read back as 0x11 */ - uint32_t : 24; - } bit; - } UARTPERIPHID0; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000FE4) UARTPeriphID1 Register */ - - struct { - __IM uint32_t PARTNUMBER1 : 4; /*!< [3..0] These bits read back as 0x0 */ - __IM uint32_t DESIGNER0 : 4; /*!< [7..4] These bits read back as 0x1 */ - uint32_t : 24; - } bit; - } UARTPERIPHID1; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000FE8) UARTPeriphID2 Register */ - - struct { - __IM uint32_t DESIGNER1 : 4; /*!< [3..0] These bits read back as 0x4 */ - __IM uint32_t REVISION : 4; /*!< [7..4] This field depends on the revision of the UART: r1p0 - 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 */ - uint32_t : 24; - } bit; - } UARTPERIPHID2; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000FEC) UARTPeriphID3 Register */ - - struct { - __IM uint32_t CONFIGURATION : 8; /*!< [7..0] These bits read back as 0x00 */ - uint32_t : 24; - } bit; - } UARTPERIPHID3; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000FF0) UARTPCellID0 Register */ - - struct { - __IM uint32_t UARTPCELLID0 : 8; /*!< [7..0] These bits read back as 0x0D */ - uint32_t : 24; - } bit; - } UARTPCELLID0; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000FF4) UARTPCellID1 Register */ - - struct { - __IM uint32_t UARTPCELLID1 : 8; /*!< [7..0] These bits read back as 0xF0 */ - uint32_t : 24; - } bit; - } UARTPCELLID1; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000FF8) UARTPCellID2 Register */ - - struct { - __IM uint32_t UARTPCELLID2 : 8; /*!< [7..0] These bits read back as 0x05 */ - uint32_t : 24; - } bit; - } UARTPCELLID2; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000FFC) UARTPCellID3 Register */ - - struct { - __IM uint32_t UARTPCELLID3 : 8; /*!< [7..0] These bits read back as 0xB1 */ - uint32_t : 24; - } bit; - } UARTPCELLID3; + __IOM uint32_t UARTPERIPHID0; /*!< (@ 0x00000FE0) UARTPeriphID0 Register */ + __IOM uint32_t UARTPERIPHID1; /*!< (@ 0x00000FE4) UARTPeriphID1 Register */ + __IOM uint32_t UARTPERIPHID2; /*!< (@ 0x00000FE8) UARTPeriphID2 Register */ + __IOM uint32_t UARTPERIPHID3; /*!< (@ 0x00000FEC) UARTPeriphID3 Register */ + __IOM uint32_t UARTPCELLID0; /*!< (@ 0x00000FF0) UARTPCellID0 Register */ + __IOM uint32_t UARTPCELLID1; /*!< (@ 0x00000FF4) UARTPCellID1 Register */ + __IOM uint32_t UARTPCELLID2; /*!< (@ 0x00000FF8) UARTPCellID2 Register */ + __IOM uint32_t UARTPCELLID3; /*!< (@ 0x00000FFC) UARTPCellID3 Register */ } UART0_Type; /*!< Size = 4096 (0x1000) */ @@ -6500,263 +843,36 @@ typedef struct { /*!< (@ 0x40034000) UART0 Struct */ typedef struct { /*!< (@ 0x4003C000) SPI0 Structure */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Control register 0, SSPCR0 on page 3-4 */ - - struct { - __IOM uint32_t DSS : 4; /*!< [3..0] Data Size Select: 0000 Reserved, undefined operation. - 0001 Reserved, undefined operation. 0010 Reserved, undefined - operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit - data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. - 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 - 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit - data. */ - __IOM uint32_t FRF : 2; /*!< [5..4] Frame format: 00 Motorola SPI frame format. 01 TI synchronous - serial frame format. 10 National Microwire frame format. - 11 Reserved, undefined operation. */ - __IOM uint32_t SPO : 1; /*!< [6..6] SSPCLKOUT polarity, applicable to Motorola SPI frame - format only. See Motorola SPI frame format on page 2-10. */ - __IOM uint32_t SPH : 1; /*!< [7..7] SSPCLKOUT phase, applicable to Motorola SPI frame format - only. See Motorola SPI frame format on page 2-10. */ - __IOM uint32_t SCR : 8; /*!< [15..8] Serial clock rate. The value SCR is used to generate - the transmit and receive bit rate of the PrimeCell SSP. - The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR - is an even value from 2-254, programmed through the SSPCPSR - register and SCR is a value from 0-255. */ - uint32_t : 16; - } bit; - } SSPCR0; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Control register 1, SSPCR1 on page 3-5 */ - - struct { - __IOM uint32_t LBM : 1; /*!< [0..0] Loop back mode: 0 Normal serial port operation enabled. - 1 Output of transmit serial shifter is connected to input - of receive serial shifter internally. */ - __IOM uint32_t SSE : 1; /*!< [1..1] Synchronous serial port enable: 0 SSP operation disabled. - 1 SSP operation enabled. */ - __IOM uint32_t MS : 1; /*!< [2..2] Master or slave mode select. This bit can be modified - only when the PrimeCell SSP is disabled, SSE=0: 0 Device - configured as master, default. 1 Device configured as slave. */ - __IOM uint32_t SOD : 1; /*!< [3..3] Slave-mode output disable. This bit is relevant only - in the slave mode, MS=1. In multiple-slave systems, it - is possible for an PrimeCell SSP master to broadcast a - message to all slaves in the system while ensuring that - only one slave drives data onto its serial output line. - In such systems the RXD lines from multiple slaves could - be tied together. To operate in such systems, the SOD bit - can be set if the PrimeCell SSP slave is not supposed to - drive the SSPTXD line: 0 SSP can drive the SSPTXD output - in sl */ - uint32_t : 28; - } bit; - } SSPCR1; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000008) Data register, SSPDR on page 3-6 */ - - struct { - __IOM uint32_t DATA : 16; /*!< [15..0] Transmit/Receive FIFO: Read Receive FIFO. Write Transmit - FIFO. You must right-justify data when the PrimeCell SSP - is programmed for a data size that is less than 16 bits. - Unused bits at the top are ignored by transmit logic. The - receive logic automatically right-justifies. */ - uint32_t : 16; - } bit; - } SSPDR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) Status register, SSPSR on page 3-7 */ - - struct { - __IM uint32_t TFE : 1; /*!< [0..0] Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. - 1 Transmit FIFO is empty. */ - __IM uint32_t TNF : 1; /*!< [1..1] Transmit FIFO not full, RO: 0 Transmit FIFO is full. - 1 Transmit FIFO is not full. */ - __IM uint32_t RNE : 1; /*!< [2..2] Receive FIFO not empty, RO: 0 Receive FIFO is empty. - 1 Receive FIFO is not empty. */ - __IM uint32_t RFF : 1; /*!< [3..3] Receive FIFO full, RO: 0 Receive FIFO is not full. 1 - Receive FIFO is full. */ - __IM uint32_t BSY : 1; /*!< [4..4] PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is - currently transmitting and/or receiving a frame or the - transmit FIFO is not empty. */ - uint32_t : 27; - } bit; - } SSPSR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000010) Clock prescale register, SSPCPSR on page 3-8 */ - - struct { - __IOM uint32_t CPSDVSR : 8; /*!< [7..0] Clock prescale divisor. Must be an even number from 2-254, - depending on the frequency of SSPCLK. The least significant - bit always returns zero on reads. */ - uint32_t : 24; - } bit; - } SSPCPSR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000014) Interrupt mask set or clear register, SSPIMSC + __IOM uint32_t SSPCR0; /*!< (@ 0x00000000) Control register 0, SSPCR0 on page 3-4 */ + __IOM uint32_t SSPCR1; /*!< (@ 0x00000004) Control register 1, SSPCR1 on page 3-5 */ + __IOM uint32_t SSPDR; /*!< (@ 0x00000008) Data register, SSPDR on page 3-6 */ + __IOM uint32_t SSPSR; /*!< (@ 0x0000000C) Status register, SSPSR on page 3-7 */ + __IOM uint32_t SSPCPSR; /*!< (@ 0x00000010) Clock prescale register, SSPCPSR on page 3-8 */ + __IOM uint32_t SSPIMSC; /*!< (@ 0x00000014) Interrupt mask set or clear register, SSPIMSC on page 3-9 */ - - struct { - __IOM uint32_t RORIM : 1; /*!< [0..0] Receive overrun interrupt mask: 0 Receive FIFO written - to while full condition interrupt is masked. 1 Receive - FIFO written to while full condition interrupt is not masked. */ - __IOM uint32_t RTIM : 1; /*!< [1..1] Receive timeout interrupt mask: 0 Receive FIFO not empty - and no read prior to timeout period interrupt is masked. - 1 Receive FIFO not empty and no read prior to timeout period - interrupt is not masked. */ - __IOM uint32_t RXIM : 1; /*!< [2..2] Receive FIFO interrupt mask: 0 Receive FIFO half full - or less condition interrupt is masked. 1 Receive FIFO half - full or less condition interrupt is not masked. */ - __IOM uint32_t TXIM : 1; /*!< [3..3] Transmit FIFO interrupt mask: 0 Transmit FIFO half empty - or less condition interrupt is masked. 1 Transmit FIFO - half empty or less condition interrupt is not masked. */ - uint32_t : 28; - } bit; - } SSPIMSC; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000018) Raw interrupt status register, SSPRIS on page + __IOM uint32_t SSPRIS; /*!< (@ 0x00000018) Raw interrupt status register, SSPRIS on page 3-10 */ - - struct { - __IM uint32_t RORRIS : 1; /*!< [0..0] Gives the raw interrupt state, prior to masking, of the - SSPRORINTR interrupt */ - __IM uint32_t RTRIS : 1; /*!< [1..1] Gives the raw interrupt state, prior to masking, of the - SSPRTINTR interrupt */ - __IM uint32_t RXRIS : 1; /*!< [2..2] Gives the raw interrupt state, prior to masking, of the - SSPRXINTR interrupt */ - __IM uint32_t TXRIS : 1; /*!< [3..3] Gives the raw interrupt state, prior to masking, of the - SSPTXINTR interrupt */ - uint32_t : 28; - } bit; - } SSPRIS; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) Masked interrupt status register, SSPMIS on page + __IOM uint32_t SSPMIS; /*!< (@ 0x0000001C) Masked interrupt status register, SSPMIS on page 3-11 */ - - struct { - __IM uint32_t RORMIS : 1; /*!< [0..0] Gives the receive over run masked interrupt status, after - masking, of the SSPRORINTR interrupt */ - __IM uint32_t RTMIS : 1; /*!< [1..1] Gives the receive timeout masked interrupt state, after - masking, of the SSPRTINTR interrupt */ - __IM uint32_t RXMIS : 1; /*!< [2..2] Gives the receive FIFO masked interrupt state, after - masking, of the SSPRXINTR interrupt */ - __IM uint32_t TXMIS : 1; /*!< [3..3] Gives the transmit FIFO masked interrupt state, after - masking, of the SSPTXINTR interrupt */ - uint32_t : 28; - } bit; - } SSPMIS; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000020) Interrupt clear register, SSPICR on page 3-11 */ - - struct { - __IOM uint32_t RORIC : 1; /*!< [0..0] Clears the SSPRORINTR interrupt */ - __IOM uint32_t RTIC : 1; /*!< [1..1] Clears the SSPRTINTR interrupt */ - uint32_t : 30; - } bit; - } SSPICR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000024) DMA control register, SSPDMACR on page 3-12 */ - - struct { - __IOM uint32_t RXDMAE : 1; /*!< [0..0] Receive DMA Enable. If this bit is set to 1, DMA for - the receive FIFO is enabled. */ - __IOM uint32_t TXDMAE : 1; /*!< [1..1] Transmit DMA Enable. If this bit is set to 1, DMA for - the transmit FIFO is enabled. */ - uint32_t : 30; - } bit; - } SSPDMACR; + __IOM uint32_t SSPICR; /*!< (@ 0x00000020) Interrupt clear register, SSPICR on page 3-11 */ + __IOM uint32_t SSPDMACR; /*!< (@ 0x00000024) DMA control register, SSPDMACR on page 3-12 */ __IM uint32_t RESERVED[1006]; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000FE0) Peripheral identification registers, SSPPeriphID0-3 + __IOM uint32_t SSPPERIPHID0; /*!< (@ 0x00000FE0) Peripheral identification registers, SSPPeriphID0-3 on page 3-13 */ - - struct { - __IM uint32_t PARTNUMBER0 : 8; /*!< [7..0] These bits read back as 0x22 */ - uint32_t : 24; - } bit; - } SSPPERIPHID0; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000FE4) Peripheral identification registers, SSPPeriphID0-3 + __IOM uint32_t SSPPERIPHID1; /*!< (@ 0x00000FE4) Peripheral identification registers, SSPPeriphID0-3 on page 3-13 */ - - struct { - __IM uint32_t PARTNUMBER1 : 4; /*!< [3..0] These bits read back as 0x0 */ - __IM uint32_t DESIGNER0 : 4; /*!< [7..4] These bits read back as 0x1 */ - uint32_t : 24; - } bit; - } SSPPERIPHID1; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000FE8) Peripheral identification registers, SSPPeriphID0-3 + __IOM uint32_t SSPPERIPHID2; /*!< (@ 0x00000FE8) Peripheral identification registers, SSPPeriphID0-3 on page 3-13 */ - - struct { - __IM uint32_t DESIGNER1 : 4; /*!< [3..0] These bits read back as 0x4 */ - __IM uint32_t REVISION : 4; /*!< [7..4] These bits return the peripheral revision */ - uint32_t : 24; - } bit; - } SSPPERIPHID2; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000FEC) Peripheral identification registers, SSPPeriphID0-3 + __IOM uint32_t SSPPERIPHID3; /*!< (@ 0x00000FEC) Peripheral identification registers, SSPPeriphID0-3 on page 3-13 */ - - struct { - __IM uint32_t CONFIGURATION : 8; /*!< [7..0] These bits read back as 0x00 */ - uint32_t : 24; - } bit; - } SSPPERIPHID3; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000FF0) PrimeCell identification registers, SSPPCellID0-3 + __IOM uint32_t SSPPCELLID0; /*!< (@ 0x00000FF0) PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ - - struct { - __IM uint32_t SSPPCELLID0 : 8; /*!< [7..0] These bits read back as 0x0D */ - uint32_t : 24; - } bit; - } SSPPCELLID0; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000FF4) PrimeCell identification registers, SSPPCellID0-3 + __IOM uint32_t SSPPCELLID1; /*!< (@ 0x00000FF4) PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ - - struct { - __IM uint32_t SSPPCELLID1 : 8; /*!< [7..0] These bits read back as 0xF0 */ - uint32_t : 24; - } bit; - } SSPPCELLID1; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000FF8) PrimeCell identification registers, SSPPCellID0-3 + __IOM uint32_t SSPPCELLID2; /*!< (@ 0x00000FF8) PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ - - struct { - __IM uint32_t SSPPCELLID2 : 8; /*!< [7..0] These bits read back as 0x05 */ - uint32_t : 24; - } bit; - } SSPPCELLID2; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000FFC) PrimeCell identification registers, SSPPCellID0-3 + __IOM uint32_t SSPPCELLID3; /*!< (@ 0x00000FFC) PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ - - struct { - __IM uint32_t SSPPCELLID3 : 8; /*!< [7..0] These bits read back as 0xB1 */ - uint32_t : 24; - } bit; - } SSPPCELLID3; } SPI0_Type; /*!< Size = 4096 (0x1000) */ @@ -6767,13 +883,80 @@ typedef struct { /*!< (@ 0x4003C000) SPI0 Structu /** - * @brief DW_apb_i2c address block (I2C0) + * @brief DW_apb_i2c address block\n\n + List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time):\n\n + IC_ULTRA_FAST_MODE ................ 0x0\n + IC_UFM_TBUF_CNT_DEFAULT ........... 0x8\n + IC_UFM_SCL_LOW_COUNT .............. 0x0008\n + IC_UFM_SCL_HIGH_COUNT ............. 0x0006\n + IC_TX_TL .......................... 0x0\n + IC_TX_CMD_BLOCK ................... 0x1\n + IC_HAS_DMA ........................ 0x1\n + IC_HAS_ASYNC_FIFO ................. 0x0\n + IC_SMBUS_ARP ...................... 0x0\n + IC_FIRST_DATA_BYTE_STATUS ......... 0x1\n + IC_INTR_IO ........................ 0x1\n + IC_MASTER_MODE .................... 0x1\n + IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1\n + IC_INTR_POL ....................... 0x1\n + IC_OPTIONAL_SAR ................... 0x0\n + IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055\n + IC_DEFAULT_SLAVE_ADDR ............. 0x055\n + IC_DEFAULT_HS_SPKLEN .............. 0x1\n + IC_FS_SCL_HIGH_COUNT .............. 0x0006\n + IC_HS_SCL_LOW_COUNT ............... 0x0008\n + IC_DEVICE_ID_VALUE ................ 0x0\n + IC_10BITADDR_MASTER ............... 0x0\n + IC_CLK_FREQ_OPTIMIZATION .......... 0x0\n + IC_DEFAULT_FS_SPKLEN .............. 0x7\n + IC_ADD_ENCODED_PARAMS ............. 0x0\n + IC_DEFAULT_SDA_HOLD ............... 0x000001\n + IC_DEFAULT_SDA_SETUP .............. 0x64\n + IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0\n + IC_CLOCK_PERIOD ................... 100\n + IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1\n + IC_RESTART_EN ..................... 0x1\n + IC_TX_CMD_BLOCK_DEFAULT ........... 0x0\n + IC_BUS_CLEAR_FEATURE .............. 0x0\n + IC_CAP_LOADING .................... 100\n + IC_FS_SCL_LOW_COUNT ............... 0x000d\n + APB_DATA_WIDTH .................... 32\n + IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n + IC_SLV_DATA_NACK_ONLY ............. 0x1\n + IC_10BITADDR_SLAVE ................ 0x0\n + IC_CLK_TYPE ....................... 0x0\n + IC_SMBUS_UDID_MSB ................. 0x0\n + IC_SMBUS_SUSPEND_ALERT ............ 0x0\n + IC_HS_SCL_HIGH_COUNT .............. 0x0006\n + IC_SLV_RESTART_DET_EN ............. 0x1\n + IC_SMBUS .......................... 0x0\n + IC_OPTIONAL_SAR_DEFAULT ........... 0x0\n + IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0\n + IC_USE_COUNTS ..................... 0x0\n + IC_RX_BUFFER_DEPTH ................ 16\n + IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n + IC_RX_FULL_HLD_BUS_EN ............. 0x1\n + IC_SLAVE_DISABLE .................. 0x1\n + IC_RX_TL .......................... 0x0\n + IC_DEVICE_ID ...................... 0x0\n + IC_HC_COUNT_VALUES ................ 0x0\n + I2C_DYNAMIC_TAR_UPDATE ............ 0\n + IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff\n + IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff\n + IC_HS_MASTER_CODE ................. 0x1\n + IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff\n + IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff\n + IC_SS_SCL_HIGH_COUNT .............. 0x0028\n + IC_SS_SCL_LOW_COUNT ............... 0x002f\n + IC_MAX_SPEED_MODE ................. 0x2\n + IC_STAT_FOR_CLK_STRETCH ........... 0x0\n + IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0\n + IC_DEFAULT_UFM_SPKLEN ............. 0x1\n + IC_TX_BUFFER_DEPTH ................ 16 (I2C0) */ typedef struct { /*!< (@ 0x40044000) I2C0 Structure */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000000) I2C Control Register. This register can be written + __IOM uint32_t IC_CON; /*!< (@ 0x00000000) I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have @@ -6783,79 +966,7 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. */ - - struct { - __IOM uint32_t MASTER_MODE : 1; /*!< [0..0] This bit controls whether the DW_apb_i2c master is enabled. - - NOTE: Software should ensure that if this bit is written - with '1' then bit 6 should also be written with a '1'. */ - __IOM uint32_t SPEED : 2; /*!< [2..1] These bits control at which speed the DW_apb_i2c operates; - its setting is relevant only if one is operating the DW_apb_i2c - in master mode. Hardware protects against illegal values - being programmed by software. These bits must be programmed - appropriately for slave mode also, as it is used to capture - correct value of spike filter as per the speed mode. - - This register should be programmed only with a value in - the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware - updates this register */ - __IOM uint32_t IC_10BITADDR_SLAVE : 1; /*!< [3..3] When acting as a slave, this bit controls whether the - DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit - addressing. The DW_apb_i2c ignores transactions that involve - 10-bit addressing; for 7-bit addressing, only the lower - 7 bits of the IC_SAR register are compared. - 1: 10-bit - addressing. The DW_apb_i2c responds to only 10-bit addressing - transfers that match the full 10 bits of the IC_SAR register. */ - __IOM uint32_t IC_10BITADDR_MASTER : 1; /*!< [4..4] Controls whether the DW_apb_i2c starts its transfers - in 7- or 10-bit addressing mode when acting as a master. - - 0: 7-bit addressing - 1: 10-bit addressing */ - __IOM uint32_t IC_RESTART_EN : 1; /*!< [5..5] Determines whether RESTART conditions may be sent when - acting as a master. Some older slaves do not support handling - RESTART conditions; however, RESTART conditions are used - in several DW_apb_i2c operations. When RESTART is disabled, - the master is prohibited from performing the following - functions: - Sending a START BYTE - Performing any high-speed - mode operation - High-speed mode operation - Performing - direction changes in combined format mode - Performing - a read operation with a 10-bit address By repla */ - __IOM uint32_t IC_SLAVE_DISABLE : 1; /*!< [6..6] This bit controls whether I2C has its slave disabled, - which means once the presetn signal is applied, then this - bit is set and the slave is disabled. - - If this bit is set (slave is disabled), DW_apb_i2c functions - only as a master and does not perform any action that requires - a slave. - - NOTE: Software should ensure that if this bit is written - with 0, then bit 0 should also be written with a 0. */ - __IOM uint32_t STOP_DET_IFADDRESSED : 1; /*!< [7..7] In slave mode: - 1'b1: issues the STOP_DET interrupt - only when it is addressed. - 1'b0: issues the STOP_DET - irrespective of whether it's addressed or not. Reset value: - 0x0 - - NOTE: During a general call address, this slave does not - issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = - 1'b1, even if the slave responds to the general call address - by generating ACK. The STOP_DET interrupt is generated - only when the transmitted address matches the slave address - (SAR). */ - __IOM uint32_t TX_EMPTY_CTRL : 1; /*!< [8..8] This bit controls the generation of the TX_EMPTY interrupt, - as described in the IC_RAW_INTR_STAT register. - - Reset value: 0x0. */ - __IOM uint32_t RX_FIFO_FULL_HLD_CTRL : 1; /*!< [9..9] This bit controls whether DW_apb_i2c should hold the - bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, - as described in the IC_RX_FULL_HLD_BUS_EN parameter. - - Reset value: 0x0. */ - __IM uint32_t STOP_DET_IF_MASTER_ACTIVE : 1;/*!< [10..10] Master issues the STOP_DET interrupt irrespective of - whether master is active or not */ - uint32_t : 21; - } bit; - } IC_CON; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000004) I2C Target Address Register + __IOM uint32_t IC_TAR; /*!< (@ 0x00000004) I2C Target Address Register This register is 12 bits wide, and bits 31:12 are reserved. This register can be @@ -6869,59 +980,10 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if - DW_ap */ - - struct { - __IOM uint32_t IC_TAR : 10; /*!< [9..0] This is the target address for any master transaction. - When transmitting a General Call, these bits are ignored. - To generate a START BYTE, the CPU needs to write only once - into these bits. - - If the IC_TAR and IC_SAR are the same, loopback exists - but the FIFOs are shared between master and slave, so full - loopback is not feasible. Only one direction loopback mode - is supported (simplex), not duplex. A master cannot transmit - to itself; it can transmit to only a slave. */ - __IOM uint32_t GC_OR_START : 1; /*!< [10..10] If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) - is set to 0, then this bit indicates whether a General - Call or START byte command is to be performed by the DW_apb_i2c. - - 0: General Call Address - after issuing a General Call, - only writes may be performed. Attempting to issue a read - command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT - register. The DW_apb_i2c remains in General Call mode until - the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE - Reset value: 0x0 */ - __IOM uint32_t SPECIAL : 1; /*!< [11..11] This bit indicates whether software performs a Device-ID - or General Call or START BYTE command. - 0: ignore bit - 10 GC_OR_START and use IC_TAR normally - 1: perform special - I2C command as specified in Device_ID or GC_OR_START bit - Reset value: 0x0 */ - uint32_t : 20; - } bit; - } IC_TAR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000008) I2C Slave Address Register */ - - struct { - __IOM uint32_t IC_SAR : 10; /*!< [9..0] The IC_SAR holds the slave address when the I2C is operating - as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. - - This register can be written only when the I2C interface - is disabled, which corresponds to the IC_ENABLE[0] register - being set to 0. Writes at other times have no effect. - - Note: The default values cannot be any of the reserved - address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. - The correct operation of the device is not guaranteed if - you */ - uint32_t : 22; - } bit; - } IC_SAR; + DW_apb_ */ + __IOM uint32_t IC_SAR; /*!< (@ 0x00000008) I2C Slave Address Register */ __IM uint32_t RESERVED; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000010) I2C Rx/Tx Data Buffer and Command Register; this + __IOM uint32_t IC_DATA_CMD; /*!< (@ 0x00000010) I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. @@ -6933,150 +995,15 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to - continue acknowledgi */ - - struct { - __IOM uint32_t DAT : 8; /*!< [7..0] This register contains the data to be transmitted or - received on the I2C bus. If you are writing to this register - and want to perform a read, bits 7:0 (DAT) are ignored - by the DW_apb_i2c. However, when you read this register, - these bits return the value of data received on the DW_apb_i2c - interface. - - Reset value: 0x0 */ - __IOM uint32_t CMD : 1; /*!< [8..8] This bit controls whether a read or a write is performed. - This bit does not control the direction when the DW_apb_i2con - acts as a slave. It controls only the direction when it - acts as a master. - - When a command is entered in the TX FIFO, this bit distinguishes - the write and read commands. In slave-receiver mode, this - bit is a 'don't care' because writes to this register are - not required. In slave-transmitter mode, a '0' indicates - that the data in IC_DATA_CMD is to be transmitted. - - */ - __IOM uint32_t STOP : 1; /*!< [9..9] This bit controls whether a STOP is issued after the - byte is sent or received. - - - 1 - STOP is issued after this byte, regardless of whether - or not the Tx FIFO is empty. If the Tx FIFO is not empty, - the master immediately tries to start a new transfer by - issuing a START and arbitrating for the bus. - 0 - STOP - is not issued after this byte, regardless of whether or - not the Tx FIFO is empty. If the Tx FIFO is not empty, - the master continues the current transfer by sending/receiving - data */ - __IOM uint32_t RESTART : 1; /*!< [10..10] This bit controls whether a RESTART is issued before - the byte is sent or received. - - 1 - If IC_RESTART_EN is 1, a RESTART is issued before the - data is sent/received (according to the value of CMD), - regardless of whether or not the transfer direction is - changing from the previous command; if IC_RESTART_EN is - 0, a STOP followed by a START is issued instead. - - 0 - If IC_RESTART_EN is 1, a RESTART is issued only if - the transfer direction is changing from the previous com */ - __IM uint32_t FIRST_DATA_BYTE : 1; /*!< [11..11] Indicates the first data byte received after the address - phase for receive transfer in Master receiver or Slave - receiver mode. - - Reset value : 0x0 - - NOTE: In case of APB_DATA_WIDTH=8, - - 1. The user has to perform two APB Reads to IC_DATA_CMD - in order to get status on 11 bit. - - 2. In order to read the 11 bit, the user has to perform - the first data byte read [7:0] (offset 0x10) and then perform - the second read [15:8] (offset 0x11) */ - uint32_t : 20; - } bit; - } IC_DATA_CMD; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000014) Standard Speed I2C Clock SCL High Count Register */ - - struct { - __IOM uint32_t IC_SS_SCL_HCNT : 16; /*!< [15..0] This register must be set before any I2C bus transaction - can take place to ensure proper I/O timing. This register - sets the SCL clock high-period count for standard speed. - For more information, refer to 'IC_CLK Frequency Configuration'. - - This register can be written only when the I2C interface - is disabled which corresponds to the IC_ENABLE[0] register - being set to 0. Writes at other times have no effect. - - The minimum valid value is 6; hardware prevents values - less */ - uint32_t : 16; - } bit; - } IC_SS_SCL_HCNT; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000018) Standard Speed I2C Clock SCL Low Count Register */ - - struct { - __IOM uint32_t IC_SS_SCL_LCNT : 16; /*!< [15..0] This register must be set before any I2C bus transaction - can take place to ensure proper I/O timing. This register - sets the SCL clock low period count for standard speed. - For more information, refer to 'IC_CLK Frequency Configuration' - - This register can be written only when the I2C interface - is disabled which corresponds to the IC_ENABLE[0] register - being set to 0. Writes at other times have no effect. - - The minimum valid value is 8; hardware prevents values - less th */ - uint32_t : 16; - } bit; - } IC_SS_SCL_LCNT; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) Fast Mode or Fast Mode Plus I2C Clock SCL High + continue acknowledging */ + __IOM uint32_t IC_SS_SCL_HCNT; /*!< (@ 0x00000014) Standard Speed I2C Clock SCL High Count Register */ + __IOM uint32_t IC_SS_SCL_LCNT; /*!< (@ 0x00000018) Standard Speed I2C Clock SCL Low Count Register */ + __IOM uint32_t IC_FS_SCL_HCNT; /*!< (@ 0x0000001C) Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register */ - - struct { - __IOM uint32_t IC_FS_SCL_HCNT : 16; /*!< [15..0] This register must be set before any I2C bus transaction - can take place to ensure proper I/O timing. This register - sets the SCL clock high-period count for fast mode or fast - mode plus. It is used in high-speed mode to send the Master - Code and START BYTE or General CALL. For more information, - refer to 'IC_CLK Frequency Configuration'. - - This register goes away and becomes read-only returning - 0s if IC_MAX_SPEED_MODE = standard. This register can be - written only when the I2C interface is */ - uint32_t : 16; - } bit; - } IC_FS_SCL_HCNT; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000020) Fast Mode or Fast Mode Plus I2C Clock SCL Low + __IOM uint32_t IC_FS_SCL_LCNT; /*!< (@ 0x00000020) Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register */ - - struct { - __IOM uint32_t IC_FS_SCL_LCNT : 16; /*!< [15..0] This register must be set before any I2C bus transaction - can take place to ensure proper I/O timing. This register - sets the SCL clock low period count for fast speed. It - is used in high-speed mode to send the Master Code and - START BYTE or General CALL. For more information, refer - to 'IC_CLK Frequency Configuration'. - - This register goes away and becomes read-only returning - 0s if IC_MAX_SPEED_MODE = standard. - - This register can be written only when the I2C interface - */ - uint32_t : 16; - } bit; - } IC_FS_SCL_LCNT; __IM uint32_t RESERVED1[2]; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000002C) I2C Interrupt Status Register + __IOM uint32_t IC_INTR_STAT; /*!< (@ 0x0000002C) I2C Interrupt Status Register Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These @@ -7084,488 +1011,32 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. */ - - struct { - __IM uint32_t R_RX_UNDER : 1; /*!< [0..0] See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER - bit. - - Reset value: 0x0 */ - __IM uint32_t R_RX_OVER : 1; /*!< [1..1] See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER - bit. - - Reset value: 0x0 */ - __IM uint32_t R_RX_FULL : 1; /*!< [2..2] See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL - bit. - - Reset value: 0x0 */ - __IM uint32_t R_TX_OVER : 1; /*!< [3..3] See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER - bit. - - Reset value: 0x0 */ - __IM uint32_t R_TX_EMPTY : 1; /*!< [4..4] See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY - bit. - - Reset value: 0x0 */ - __IM uint32_t R_RD_REQ : 1; /*!< [5..5] See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ - bit. - - Reset value: 0x0 */ - __IM uint32_t R_TX_ABRT : 1; /*!< [6..6] See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT - bit. - - Reset value: 0x0 */ - __IM uint32_t R_RX_DONE : 1; /*!< [7..7] See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE - bit. - - Reset value: 0x0 */ - __IM uint32_t R_ACTIVITY : 1; /*!< [8..8] See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY - bit. - - Reset value: 0x0 */ - __IM uint32_t R_STOP_DET : 1; /*!< [9..9] See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET - bit. - - Reset value: 0x0 */ - __IM uint32_t R_START_DET : 1; /*!< [10..10] See IC_RAW_INTR_STAT for a detailed description of - R_START_DET bit. - - Reset value: 0x0 */ - __IM uint32_t R_GEN_CALL : 1; /*!< [11..11] See IC_RAW_INTR_STAT for a detailed description of - R_GEN_CALL bit. - - Reset value: 0x0 */ - __IM uint32_t R_RESTART_DET : 1; /*!< [12..12] See IC_RAW_INTR_STAT for a detailed description of - R_RESTART_DET bit. - - Reset value: 0x0 */ - __IM uint32_t R_MASTER_ON_HOLD : 1; /*!< [13..13] See IC_RAW_INTR_STAT for a detailed description of - R_MASTER_ON_HOLD bit. - - Reset value: 0x0 */ - uint32_t : 18; - } bit; - } IC_INTR_STAT; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000030) I2C Interrupt Mask Register. + __IOM uint32_t IC_INTR_MASK; /*!< (@ 0x00000030) I2C Interrupt Mask Register. These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. */ - - struct { - __IOM uint32_t M_RX_UNDER : 1; /*!< [0..0] This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT - register. - - Reset value: 0x1 */ - __IOM uint32_t M_RX_OVER : 1; /*!< [1..1] This bit masks the R_RX_OVER interrupt in IC_INTR_STAT - register. - - Reset value: 0x1 */ - __IOM uint32_t M_RX_FULL : 1; /*!< [2..2] This bit masks the R_RX_FULL interrupt in IC_INTR_STAT - register. - - Reset value: 0x1 */ - __IOM uint32_t M_TX_OVER : 1; /*!< [3..3] This bit masks the R_TX_OVER interrupt in IC_INTR_STAT - register. - - Reset value: 0x1 */ - __IOM uint32_t M_TX_EMPTY : 1; /*!< [4..4] This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT - register. - - Reset value: 0x1 */ - __IOM uint32_t M_RD_REQ : 1; /*!< [5..5] This bit masks the R_RD_REQ interrupt in IC_INTR_STAT - register. - - Reset value: 0x1 */ - __IOM uint32_t M_TX_ABRT : 1; /*!< [6..6] This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT - register. - - Reset value: 0x1 */ - __IOM uint32_t M_RX_DONE : 1; /*!< [7..7] This bit masks the R_RX_DONE interrupt in IC_INTR_STAT - register. - - Reset value: 0x1 */ - __IOM uint32_t M_ACTIVITY : 1; /*!< [8..8] This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT - register. - - Reset value: 0x0 */ - __IOM uint32_t M_STOP_DET : 1; /*!< [9..9] This bit masks the R_STOP_DET interrupt in IC_INTR_STAT - register. - - Reset value: 0x0 */ - __IOM uint32_t M_START_DET : 1; /*!< [10..10] This bit masks the R_START_DET interrupt in IC_INTR_STAT - register. - - Reset value: 0x0 */ - __IOM uint32_t M_GEN_CALL : 1; /*!< [11..11] This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT - register. - - Reset value: 0x1 */ - __IOM uint32_t M_RESTART_DET : 1; /*!< [12..12] This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT - register. - - Reset value: 0x0 */ - __IM uint32_t M_MASTER_ON_HOLD_READ_ONLY : 1;/*!< [13..13] This M_MASTER_ON_HOLD_read_only bit masks the R_MASTER_ON_HOLD - interrupt in IC_INTR_STAT register. - - Reset value: 0x0 */ - uint32_t : 18; - } bit; - } IC_INTR_MASK; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000034) I2C Raw Interrupt Status Register + __IOM uint32_t IC_RAW_INTR_STAT; /*!< (@ 0x00000034) I2C Raw Interrupt Status Register Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. */ - - struct { - __IM uint32_t RX_UNDER : 1; /*!< [0..0] Set if the processor attempts to read the receive buffer - when it is empty by reading from the IC_DATA_CMD register. - If the module is disabled (IC_ENABLE[0]=0), this bit keeps - its level until the master or slave state machines go into - idle, and when ic_en goes to 0, this interrupt is cleared. - - Reset value: 0x0 */ - __IM uint32_t RX_OVER : 1; /*!< [1..1] Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH - and an additional byte is received from an external I2C - device. The DW_apb_i2c acknowledges this, but any data - bytes received after the FIFO is full are lost. If the - module is disabled (IC_ENABLE[0]=0), this bit keeps its - level until the master or slave state machines go into - idle, and when ic_en goes to 0, this interrupt is cleared. - - Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) - is programmed to HIG */ - __IM uint32_t RX_FULL : 1; /*!< [2..2] Set when the receive buffer reaches or goes above the - RX_TL threshold in the IC_RX_TL register. It is automatically - cleared by hardware when buffer level goes below the threshold. - If the module is disabled (IC_ENABLE[0]=0), the RX FIFO - is flushed and held in reset; therefore the RX FIFO is - not full. So this bit is cleared once the IC_ENABLE bit - 0 is programmed with a 0, regardless of the activity that - continues. - - Reset value: 0x0 */ - __IM uint32_t TX_OVER : 1; /*!< [3..3] Set during transmit if the transmit buffer is filled - to IC_TX_BUFFER_DEPTH and the processor attempts to issue - another I2C command by writing to the IC_DATA_CMD register. - When the module is disabled, this bit keeps its level until - the master or slave state machines go into idle, and when - ic_en goes to 0, this interrupt is cleared. - - Reset value: 0x0 */ - __IM uint32_t TX_EMPTY : 1; /*!< [4..4] The behavior of the TX_EMPTY interrupt status differs - based on the TX_EMPTY_CTRL selection in the IC_CON register. - - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the - transmit buffer is at or below the threshold value set - in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This - bit is set to 1 when the transmit buffer is at or below - the threshold value set in the IC_TX_TL register and the - transmission of the address/data from the internal shift - register for the most recently popped command is complet */ - __IM uint32_t RD_REQ : 1; /*!< [5..5] This bit is set to 1 when DW_apb_i2c is acting as a slave - and another I2C master is attempting to read data from - DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait - state (SCL=0) until this interrupt is serviced, which means - that the slave has been addressed by a remote master that - is asking for data to be transferred. The processor must - respond to this interrupt and then write the requested - data to the IC_DATA_CMD register. This bit is set to 0 - just after the processor reads the IC_CLR_RD_REQ registe */ - __IM uint32_t TX_ABRT : 1; /*!< [6..6] This bit indicates if DW_apb_i2c, as an I2C transmitter, - is unable to complete the intended actions on the contents - of the transmit FIFO. This situation can occur both as - an I2C master or an I2C slave, and is referred to as a - 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE - register indicates the reason why the transmit abort takes - places. - - Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO - and RX_FIFO whenever there is a transmit abort caused by - any of the eve */ - __IM uint32_t RX_DONE : 1; /*!< [7..7] When the DW_apb_i2c is acting as a slave-transmitter, - this bit is set to 1 if the master does not acknowledge - a transmitted byte. This occurs on the last byte of the - transmission, indicating that the transmission is done. - - Reset value: 0x0 */ - __IM uint32_t ACTIVITY : 1; /*!< [8..8] This bit captures DW_apb_i2c activity and stays set until - it is cleared. There are four ways to clear it: - Disabling - the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - - Reading the IC_CLR_INTR register - System reset Once this - bit is set, it stays set unless one of the four methods - is used to clear it. Even if the DW_apb_i2c module is idle, - this bit remains set until cleared, indicating that there - was activity on the bus. - - Reset value: 0x0 */ - __IM uint32_t STOP_DET : 1; /*!< [9..9] Indicates whether a STOP condition has occurred on the - I2C interface regardless of whether DW_apb_i2c is operating - in slave or master mode. - - In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), - the STOP_DET interrupt will be issued only if slave is - addressed. Note: During a general call address, this slave - does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, - even if the slave responds to the general call address - by generating ACK. The STOP_DET interrupt is generat */ - __IM uint32_t START_DET : 1; /*!< [10..10] Indicates whether a START or RESTART condition has - occurred on the I2C interface regardless of whether DW_apb_i2c - is operating in slave or master mode. - - Reset value: 0x0 */ - __IM uint32_t GEN_CALL : 1; /*!< [11..11] Set only when a General Call address is received and - it is acknowledged. It stays set until it is cleared either - by disabling DW_apb_i2c or when the CPU reads bit 0 of - the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received - data in the Rx buffer. - - Reset value: 0x0 */ - __IM uint32_t RESTART_DET : 1; /*!< [12..12] Indicates whether a RESTART condition has occurred - on the I2C interface when DW_apb_i2c is operating in Slave - mode and the slave is being addressed. Enabled only when - IC_SLV_RESTART_DET_EN=1. - - Note: However, in high-speed mode or during a START BYTE - transfer, the RESTART comes before the address field as - per the I2C protocol. In this case, the slave is not the - addressed slave when the RESTART is issued, therefore DW_apb_i2c - does not generate the RESTART_DET interrupt. - - */ - __IM uint32_t MASTER_ON_HOLD : 1; /*!< [13..13] Indicates whether master is holding the bus and TX - FIFO is empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 - and IC_EMPTYFIFO_HOLD_MASTER_EN=1. - - Reset value: 0x0 */ - uint32_t : 18; - } bit; - } IC_RAW_INTR_STAT; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000038) I2C Receive FIFO Threshold Register */ - - struct { - __IOM uint32_t RX_TL : 8; /*!< [7..0] Receive FIFO Threshold Level. - - Controls the level of entries (or above) that triggers - the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). - The valid range is 0-255, with the additional restriction - that hardware does not allow this value to be set to a - value larger than the depth of the buffer. If an attempt - is made to do that, the actual value set will be the maximum - depth of the buffer. A value of 0 sets the threshold for - 1 entry, and a value of 255 sets the threshold for 256 - */ - uint32_t : 24; - } bit; - } IC_RX_TL; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000003C) I2C Transmit FIFO Threshold Register */ - - struct { - __IOM uint32_t TX_TL : 8; /*!< [7..0] Transmit FIFO Threshold Level. - - Controls the level of entries (or below) that trigger the - TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). - The valid range is 0-255, with the additional restriction - that it may not be set to value larger than the depth of - the buffer. If an attempt is made to do that, the actual - value set will be the maximum depth of the buffer. A value - of 0 sets the threshold for 0 entries, and a value of 255 - sets the threshold for 255 entries. */ - uint32_t : 24; - } bit; - } IC_TX_TL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000040) Clear Combined and Individual Interrupt Register */ - - struct { - __IM uint32_t CLR_INTR : 1; /*!< [0..0] Read this register to clear the combined interrupt, all - individual interrupts, and the IC_TX_ABRT_SOURCE register. - This bit does not clear hardware clearable interrupts but - software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE - register for an exception to clearing IC_TX_ABRT_SOURCE. - - Reset value: 0x0 */ - uint32_t : 31; - } bit; - } IC_CLR_INTR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000044) Clear RX_UNDER Interrupt Register */ - - struct { - __IM uint32_t CLR_RX_UNDER : 1; /*!< [0..0] Read this register to clear the RX_UNDER interrupt (bit - 0) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 */ - uint32_t : 31; - } bit; - } IC_CLR_RX_UNDER; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000048) Clear RX_OVER Interrupt Register */ - - struct { - __IM uint32_t CLR_RX_OVER : 1; /*!< [0..0] Read this register to clear the RX_OVER interrupt (bit - 1) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 */ - uint32_t : 31; - } bit; - } IC_CLR_RX_OVER; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000004C) Clear TX_OVER Interrupt Register */ - - struct { - __IM uint32_t CLR_TX_OVER : 1; /*!< [0..0] Read this register to clear the TX_OVER interrupt (bit - 3) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 */ - uint32_t : 31; - } bit; - } IC_CLR_TX_OVER; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000050) Clear RD_REQ Interrupt Register */ - - struct { - __IM uint32_t CLR_RD_REQ : 1; /*!< [0..0] Read this register to clear the RD_REQ interrupt (bit - 5) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 */ - uint32_t : 31; - } bit; - } IC_CLR_RD_REQ; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000054) Clear TX_ABRT Interrupt Register */ - - struct { - __IM uint32_t CLR_TX_ABRT : 1; /*!< [0..0] Read this register to clear the TX_ABRT interrupt (bit - 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE - register. This also releases the TX FIFO from the flushed/reset - state, allowing more writes to the TX FIFO. Refer to Bit - 9 of the IC_TX_ABRT_SOURCE register for an exception to - clearing IC_TX_ABRT_SOURCE. - - Reset value: 0x0 */ - uint32_t : 31; - } bit; - } IC_CLR_TX_ABRT; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000058) Clear RX_DONE Interrupt Register */ - - struct { - __IM uint32_t CLR_RX_DONE : 1; /*!< [0..0] Read this register to clear the RX_DONE interrupt (bit - 7) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 */ - uint32_t : 31; - } bit; - } IC_CLR_RX_DONE; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000005C) Clear ACTIVITY Interrupt Register */ - - struct { - __IM uint32_t CLR_ACTIVITY : 1; /*!< [0..0] Reading this register clears the ACTIVITY interrupt if - the I2C is not active anymore. If the I2C module is still - active on the bus, the ACTIVITY interrupt bit continues - to be set. It is automatically cleared by hardware if the - module is disabled and if there is no further activity - on the bus. The value read from this register to get status - of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT - register. - - Reset value: 0x0 */ - uint32_t : 31; - } bit; - } IC_CLR_ACTIVITY; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000060) Clear STOP_DET Interrupt Register */ - - struct { - __IM uint32_t CLR_STOP_DET : 1; /*!< [0..0] Read this register to clear the STOP_DET interrupt (bit - 9) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 */ - uint32_t : 31; - } bit; - } IC_CLR_STOP_DET; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000064) Clear START_DET Interrupt Register */ - - struct { - __IM uint32_t CLR_START_DET : 1; /*!< [0..0] Read this register to clear the START_DET interrupt (bit - 10) of the IC_RAW_INTR_STAT register. - - Reset value: 0x0 */ - uint32_t : 31; - } bit; - } IC_CLR_START_DET; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000068) Clear GEN_CALL Interrupt Register */ - - struct { - __IM uint32_t CLR_GEN_CALL : 1; /*!< [0..0] Read this register to clear the GEN_CALL interrupt (bit - 11) of IC_RAW_INTR_STAT register. - - Reset value: 0x0 */ - uint32_t : 31; - } bit; - } IC_CLR_GEN_CALL; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000006C) I2C Enable Register */ - - struct { - __IOM uint32_t ENABLE : 1; /*!< [0..0] Controls whether the DW_apb_i2c is enabled. - 0: Disables - DW_apb_i2c (TX and RX FIFOs are held in an erased state) - - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c - while it is active. However, it is important that care - be taken to ensure that DW_apb_i2c is disabled properly. - A recommended procedure is described in 'Disabling DW_apb_i2c'. - - When DW_apb_i2c is disabled, the following occurs: - The - TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT - register are stil */ - __IOM uint32_t ABORT : 1; /*!< [1..1] When set, the controller initiates the transfer abort. - - 0: ABORT not initiated or ABORT done - 1: ABORT operation - in progress The software can abort the I2C transfer in - master mode by setting this bit. The software can set this - bit only when ENABLE is already set; otherwise, the controller - ignores any write to ABORT bit. The software cannot clear - the ABORT bit once set. In response to an ABORT, the controller - issues a STOP and flushes the Tx FIFO after completing - the current transfer, then sets the TX_A */ - __IOM uint32_t TX_CMD_BLOCK : 1; /*!< [2..2] In Master mode: - 1'b1: Blocks the transmission of data - on I2C bus even if Tx FIFO has data to transmit. - 1'b0: - The transmission of data starts on I2C bus automatically, - as soon as the first data is available in the Tx FIFO. - Note: To block the execution of Master commands, set the - TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) - and Master is in Idle state (IC_STATUS[5] == 0). Any further - commands put in the Tx FIFO are not executed until TX_CMD_BLOCK - bit is unset. Reset value: IC_TX_CMD_B */ - uint32_t : 29; - } bit; - } IC_ENABLE; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000070) I2C Status Register + __IOM uint32_t IC_RX_TL; /*!< (@ 0x00000038) I2C Receive FIFO Threshold Register */ + __IOM uint32_t IC_TX_TL; /*!< (@ 0x0000003C) I2C Transmit FIFO Threshold Register */ + __IOM uint32_t IC_CLR_INTR; /*!< (@ 0x00000040) Clear Combined and Individual Interrupt Register */ + __IOM uint32_t IC_CLR_RX_UNDER; /*!< (@ 0x00000044) Clear RX_UNDER Interrupt Register */ + __IOM uint32_t IC_CLR_RX_OVER; /*!< (@ 0x00000048) Clear RX_OVER Interrupt Register */ + __IOM uint32_t IC_CLR_TX_OVER; /*!< (@ 0x0000004C) Clear TX_OVER Interrupt Register */ + __IOM uint32_t IC_CLR_RD_REQ; /*!< (@ 0x00000050) Clear RD_REQ Interrupt Register */ + __IOM uint32_t IC_CLR_TX_ABRT; /*!< (@ 0x00000054) Clear TX_ABRT Interrupt Register */ + __IOM uint32_t IC_CLR_RX_DONE; /*!< (@ 0x00000058) Clear RX_DONE Interrupt Register */ + __IOM uint32_t IC_CLR_ACTIVITY; /*!< (@ 0x0000005C) Clear ACTIVITY Interrupt Register */ + __IOM uint32_t IC_CLR_STOP_DET; /*!< (@ 0x00000060) Clear STOP_DET Interrupt Register */ + __IOM uint32_t IC_CLR_START_DET; /*!< (@ 0x00000064) Clear START_DET Interrupt Register */ + __IOM uint32_t IC_CLR_GEN_CALL; /*!< (@ 0x00000068) Clear GEN_CALL Interrupt Register */ + __IOM uint32_t IC_ENABLE; /*!< (@ 0x0000006C) I2C Enable Register */ + __IOM uint32_t IC_STATUS; /*!< (@ 0x00000070) I2C Status Register This is a read-only register used to indicate the current transfer status and FIFO status. @@ -7579,47 +1050,7 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 */ - - struct { - __IM uint32_t ACTIVITY : 1; /*!< [0..0] I2C Activity Status. Reset value: 0x0 */ - __IM uint32_t TFNF : 1; /*!< [1..1] Transmit FIFO Not Full. Set when the transmit FIFO contains - one or more empty locations, and is cleared when the FIFO - is full. - 0: Transmit FIFO is full - 1: Transmit FIFO - is not full Reset value: 0x1 */ - __IM uint32_t TFE : 1; /*!< [2..2] Transmit FIFO Completely Empty. When the transmit FIFO - is completely empty, this bit is set. When it contains - one or more valid entries, this bit is cleared. This bit - field does not request an interrupt. - 0: Transmit FIFO - is not empty - 1: Transmit FIFO is empty Reset value: 0x1 */ - __IM uint32_t RFNE : 1; /*!< [3..3] Receive FIFO Not Empty. This bit is set when the receive - FIFO contains one or more entries; it is cleared when the - receive FIFO is empty. - 0: Receive FIFO is empty - 1: - Receive FIFO is not empty Reset value: 0x0 */ - __IM uint32_t RFF : 1; /*!< [4..4] Receive FIFO Completely Full. When the receive FIFO is - completely full, this bit is set. When the receive FIFO - contains one or more empty location, this bit is cleared. - - 0: Receive FIFO is not full - 1: Receive FIFO is full - Reset value: 0x0 */ - __IM uint32_t MST_ACTIVITY : 1; /*!< [5..5] Master FSM Activity Status. When the Master Finite State - Machine (FSM) is not in the IDLE state, this bit is set. - - 0: Master FSM is in IDLE state so the Master part of - DW_apb_i2c is not Active - 1: Master FSM is not in IDLE - state so the Master part of DW_apb_i2c is Active Note: - IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY - and MST_ACTIVITY bits. - - Reset value: 0x0 */ - __IM uint32_t SLV_ACTIVITY : 1; /*!< [6..6] Slave FSM Activity Status. When the Slave Finite State - Machine (FSM) is not in the IDLE state, this bit is set. - - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c - is not Active - 1: Slave FSM is not in IDLE state so the - Slave part of DW_apb_i2c is Active Reset value: 0x0 */ - uint32_t : 25; - } bit; - } IC_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000074) I2C Transmit FIFO Level Register This register + __IOM uint32_t IC_TXFLR; /*!< (@ 0x00000074) I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There @@ -7629,18 +1060,7 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO. */ - - struct { - __IM uint32_t TXFLR : 5; /*!< [4..0] Transmit FIFO Level. Contains the number of valid data - entries in the transmit FIFO. - - Reset value: 0x0 */ - uint32_t : 27; - } bit; - } IC_TXFLR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000078) I2C Receive FIFO Level Register This register + __IOM uint32_t IC_RXFLR; /*!< (@ 0x00000078) I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever @@ -7649,18 +1069,7 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO. */ - - struct { - __IM uint32_t RXFLR : 5; /*!< [4..0] Receive FIFO Level. Contains the number of valid data - entries in the receive FIFO. - - Reset value: 0x0 */ - uint32_t : 27; - } bit; - } IC_RXFLR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000007C) I2C SDA Hold Time Length Register + __IOM uint32_t IC_SDA_HOLD; /*!< (@ 0x0000007C) I2C SDA Hold Time Length Register The bits [15:0] of this register are used to control the hold time of SDA during transmit @@ -7675,23 +1084,8 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu Writes to this register succeed only when IC_ENABLE[0]=0. - The values in this register a */ - - struct { - __IOM uint32_t IC_SDA_TX_HOLD : 16; /*!< [15..0] Sets the required SDA hold time in units of ic_clk period, - when DW_apb_i2c acts as a transmitter. - - Reset value: IC_DEFAULT_SDA_HOLD[15:0]. */ - __IOM uint32_t IC_SDA_RX_HOLD : 8; /*!< [23..16] Sets the required SDA hold time in units of ic_clk - period, when DW_apb_i2c acts as a receiver. - - Reset value: IC_DEFAULT_SDA_HOLD[23:16]. */ - uint32_t : 8; - } bit; - } IC_SDA_HOLD; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000080) I2C Transmit Abort Source Register + The values in this register are */ + __IOM uint32_t IC_TX_ABRT_SOURCE; /*!< (@ 0x00000080) I2C Transmit Abort Source Register This register has 32 bits that indicate the source of the TX_ABRT bit. Except for @@ -7703,147 +1097,8 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). - Once the source of the AB */ - - struct { - __IM uint32_t ABRT_7B_ADDR_NOACK : 1; /*!< [0..0] This field indicates that the Master is in 7-bit addressing - mode and the address sent was not acknowledged by any slave. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver */ - __IM uint32_t ABRT_10ADDR1_NOACK : 1; /*!< [1..1] This field indicates that the Master is in 10-bit address - mode and the first 10-bit address byte was not acknowledged - by any slave. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver */ - __IM uint32_t ABRT_10ADDR2_NOACK : 1; /*!< [2..2] This field indicates that the Master is in 10-bit address - mode and that the second address byte of the 10-bit address - was not acknowledged by any slave. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver */ - __IM uint32_t ABRT_TXDATA_NOACK : 1; /*!< [3..3] This field indicates the master-mode only bit. When the - master receives an acknowledgement for the address, but - when it sends data byte(s) following the address, it did - not receive an acknowledge from the remote slave(s). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter */ - __IM uint32_t ABRT_GCALL_NOACK : 1; /*!< [4..4] This field indicates that DW_apb_i2c in master mode has - sent a General Call and no slave on the bus acknowledged - the General Call. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter */ - __IM uint32_t ABRT_GCALL_READ : 1; /*!< [5..5] This field indicates that DW_apb_i2c in the master mode - has sent a General Call but the user programmed the byte - following the General Call to be a read from the bus (IC_DATA_CMD[9] - is set to 1). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter */ - __IM uint32_t ABRT_HS_ACKDET : 1; /*!< [6..6] This field indicates that the Master is in High Speed - mode and the High Speed Master code was acknowledged (wrong - behavior). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master */ - __IM uint32_t ABRT_SBYTE_ACKDET : 1; /*!< [7..7] This field indicates that the Master has sent a START - Byte and the START Byte was acknowledged (wrong behavior). - - Reset value: 0x0 - - Role of DW_apb_i2c: Master */ - __IM uint32_t ABRT_HS_NORSTRT : 1; /*!< [8..8] This field indicates that the restart is disabled (IC_RESTART_EN - bit (IC_CON[5]) =0) and the user is trying to use the master - to transfer data in High Speed mode. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver */ - __IM uint32_t ABRT_SBYTE_NORSTRT : 1; /*!< [9..9] To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT - must be fixed first; restart must be enabled (IC_CON[5]=1), - the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START - bit must be cleared (IC_TAR[10]). Once the source of the - ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared - in the same manner as other bits in this register. If the - source of the ABRT_SBYTE_NORSTRT is not fixed before attempting - to clear this bit, bit 9 clears for one cycle and then - gets reasserted. When this field is set */ - __IM uint32_t ABRT_10B_RD_NORSTRT : 1; /*!< [10..10] This field indicates that the restart is disabled (IC_RESTART_EN - bit (IC_CON[5]) =0) and the master sends a read command - in 10-bit addressing mode. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Receiver */ - __IM uint32_t ABRT_MASTER_DIS : 1; /*!< [11..11] This field indicates that the User tries to initiate - a Master operation with the Master mode disabled. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Master-Receiver */ - __IM uint32_t ARB_LOST : 1; /*!< [12..12] This field specifies that the Master has lost arbitration, - or if IC_TX_ABRT_SOURCE[14] is also set, then the slave - transmitter has lost arbitration. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter */ - __IM uint32_t ABRT_SLVFLUSH_TXFIFO : 1; /*!< [13..13] This field specifies that the Slave has received a - read command and some data exists in the TX FIFO, so the - slave issues a TX_ABRT interrupt to flush old data in TX - FIFO. - - Reset value: 0x0 - - Role of DW_apb_i2c: Slave-Transmitter */ - __IM uint32_t ABRT_SLV_ARBLOST : 1; /*!< [14..14] This field indicates that a Slave has lost the bus - while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] - is set at the same time. Note: Even though the slave never - 'owns' the bus, something could go wrong on the bus. This - is a fail safe check. For instance, during a data transmission - at the low-to-high transition of SCL, if what is on the - data bus is not what is supposed to be transmitted, then - DW_apb_i2c no longer own the bus. - - Reset value: 0x0 - - Role */ - __IM uint32_t ABRT_SLVRD_INTX : 1; /*!< [15..15] 1: When the processor side responds to a slave mode - request for data to be transmitted to a remote master and - user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. - - Reset value: 0x0 - - Role of DW_apb_i2c: Slave-Transmitter */ - __IM uint32_t ABRT_USER_ABRT : 1; /*!< [16..16] This is a master-mode-only bit. Master has detected - the transfer abort (IC_ENABLE[1]) - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter */ - uint32_t : 6; - __IM uint32_t TX_FLUSH_CNT : 9; /*!< [31..23] This field indicates the number of Tx FIFO Data Commands - which are flushed due to TX_ABRT interrupt. It is cleared - whenever I2C is disabled. - - Reset value: 0x0 - - Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter */ - } bit; - } IC_TX_ABRT_SOURCE; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000084) Generate Slave Data NACK Register + Once the source of the ABRT */ + __IOM uint32_t IC_SLV_DATA_NACK_ONLY; /*!< (@ 0x00000084) Generate Slave Data NACK Register The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c @@ -7856,76 +1111,16 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu A write can occur on this register if both of the following conditions are met: - DW_apb_i2c - is disabled (IC_ENABLE */ - - struct { - __IOM uint32_t NACK : 1; /*!< [0..0] Generate NACK. This NACK generation only occurs when - DW_apb_i2c is a slave-receiver. If this register is set - to a value of 1, it can only generate a NACK after a data - byte is received; hence, the data transfer is aborted and - the data received is not pushed to the receive buffer. - - When the register is set to a value of 0, it generates - NACK/ACK, depending on normal criteria. - 1: generate NACK - after data byte received - 0: generate NACK/ACK normally - Reset value: 0x0 */ - uint32_t : 31; - } bit; - } IC_SLV_DATA_NACK_ONLY; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000088) DMA Control Register + is disabled (IC_ENABLE[0 */ + __IOM uint32_t IC_DMA_CR; /*!< (@ 0x00000088) DMA Control Register The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE. */ - - struct { - __IOM uint32_t RDMAE : 1; /*!< [0..0] Receive DMA Enable. This bit enables/disables the receive - FIFO DMA channel. Reset value: 0x0 */ - __IOM uint32_t TDMAE : 1; /*!< [1..1] Transmit DMA Enable. This bit enables/disables the transmit - FIFO DMA channel. Reset value: 0x0 */ - uint32_t : 30; - } bit; - } IC_DMA_CR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000008C) DMA Transmit Data Level Register */ - - struct { - __IOM uint32_t DMATDL : 4; /*!< [3..0] Transmit Data Level. This bit field controls the level - at which a DMA request is made by the transmit logic. It - is equal to the watermark level; that is, the dma_tx_req - signal is generated when the number of valid data entries - in the transmit FIFO is equal to or below this field value, - and TDMAE = 1. - - Reset value: 0x0 */ - uint32_t : 28; - } bit; - } IC_DMA_TDLR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000090) I2C Receive Data Level Register */ - - struct { - __IOM uint32_t DMARDL : 4; /*!< [3..0] Receive Data Level. This bit field controls the level - at which a DMA request is made by the receive logic. The - watermark level = DMARDL+1; that is, dma_rx_req is generated - when the number of valid data entries in the receive FIFO - is equal to or more than this field value + 1, and RDMAE - =1. For instance, when DMARDL is 0, then dma_rx_req is - asserted when 1 or more data entries are present in the - receive FIFO. - - Reset value: 0x0 */ - uint32_t : 28; - } bit; - } IC_DMA_RDLR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000094) I2C SDA Setup Register + __IOM uint32_t IC_DMA_TDLR; /*!< (@ 0x0000008C) DMA Transmit Data Level Register */ + __IOM uint32_t IC_DMA_RDLR; /*!< (@ 0x00000090) I2C Receive Data Level Register */ + __IOM uint32_t IC_SDA_SETUP; /*!< (@ 0x00000094) I2C SDA Setup Register This register controls the amount of time delay (in terms of number of ic_clk clock @@ -7938,19 +1133,8 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu programmed with a value equal to or greater than 2. - Writes to this register succeed only wh */ - - struct { - __IOM uint32_t SDA_SETUP : 8; /*!< [7..0] SDA Setup. It is recommended that if the required delay - is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP - should be programmed to a value of 11. IC_SDA_SETUP must - be programmed with a minimum value of 2. */ - uint32_t : 24; - } bit; - } IC_SDA_SETUP; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000098) I2C ACK General Call Register + Writes to this register succeed only when */ + __IOM uint32_t IC_ACK_GENERAL_CALL; /*!< (@ 0x00000098) I2C ACK General Call Register The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives @@ -7958,18 +1142,7 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu This register is applicable only when the DW_apb_i2c is in slave mode. */ - - struct { - __IOM uint32_t ACK_GEN_CALL : 1; /*!< [0..0] ACK General Call. When set to 1, DW_apb_i2c responds - with a ACK (by asserting ic_data_oe) when it receives a - General Call. Otherwise, DW_apb_i2c responds with a NACK - (by negating ic_data_oe). */ - uint32_t : 31; - } bit; - } IC_ACK_GENERAL_CALL; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000009C) I2C Enable Status Register + __IOM uint32_t IC_ENABLE_STATUS; /*!< (@ 0x0000009C) I2C Enable Status Register The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register @@ -7985,48 +1158,8 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu read as '0'. Note: When IC_ENABLE[0] has been set to - 0, a delay occurs for bit 0 */ - - struct { - __IM uint32_t IC_EN : 1; /*!< [0..0] ic_en Status. This bit always reflects the value driven - on the output port ic_en. - When read as 1, DW_apb_i2c - is deemed to be in an enabled state. - When read as 0, - DW_apb_i2c is deemed completely inactive. Note: The CPU - can safely read this bit anytime. When this bit is read - as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) - and SLV_DISABLED_WHILE_BUSY (bit 1). - - Reset value: 0x0 */ - __IM uint32_t SLV_DISABLED_WHILE_BUSY : 1;/*!< [1..1] Slave Disabled While Busy (Transmit, Receive). This bit - indicates if a potential or active Slave operation has - been aborted due to the setting bit 0 of the IC_ENABLE - register from 1 to 0. This bit is set when the CPU writes - a 0 to the IC_ENABLE register while: - - (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter - operation from a remote master; - - OR, - - (b) address and data bytes of the Slave-Receiver operation - from a remote master */ - __IM uint32_t SLV_RX_DATA_LOST : 1; /*!< [2..2] Slave Received Data Lost. This bit indicates if a Slave-Receiver - operation has been aborted with at least one data byte - received from an I2C transfer due to the setting bit 0 - of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is - deemed to have been actively engaged in an aborted I2C - transfer (with matching address) and the data phase of - the I2C transfer has been entered, even though a data byte - has been responded with a NACK. - - Note: If the remote I2C master terminates the transfer - */ - uint32_t : 29; - } bit; - } IC_ENABLE_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000A0) I2C SS, FS or FM+ spike suppression limit + 0, a delay occurs for bit 0 t */ + __IOM uint32_t IC_FS_SPKLEN; /*!< (@ 0x000000A0) I2C SS, FS or FM+ spike suppression limit This register is used to store the duration, measured in ic_clk cycles, of the longest @@ -8037,37 +1170,10 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu in the I2C Bus Specification. This register must be programmed with a minimum value of 1. */ - - struct { - __IOM uint32_t IC_FS_SPKLEN : 8; /*!< [7..0] This register must be set before any I2C bus transaction - can take place to ensure stable operation. This register - sets the duration, measured in ic_clk cycles, of the longest - spike in the SCL or SDA lines that will be filtered out - by the spike suppression logic. This register can be written - only when the I2C interface is disabled which corresponds - to the IC_ENABLE[0] register being set to 0. Writes at - other times have no effect. The minimum valid value is - 1; hardware prevents values less than this being */ - uint32_t : 24; - } bit; - } IC_FS_SPKLEN; __IM uint32_t RESERVED2; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000A8) Clear RESTART_DET Interrupt Register */ - - struct { - __IM uint32_t CLR_RESTART_DET : 1; /*!< [0..0] Read this register to clear the RESTART_DET interrupt - (bit 12) of IC_RAW_INTR_STAT register. - - Reset value: 0x0 */ - uint32_t : 31; - } bit; - } IC_CLR_RESTART_DET; + __IOM uint32_t IC_CLR_RESTART_DET; /*!< (@ 0x000000A8) Clear RESTART_DET Interrupt Register */ __IM uint32_t RESERVED3[18]; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000F4) Component Parameter Register 1 + __IOM uint32_t IC_COMP_PARAM_1; /*!< (@ 0x000000F4) Component Parameter Register 1 Note This register is not implemented and therefore reads as 0. If it was implemented @@ -8075,38 +1181,8 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters */ - - struct { - __IM uint32_t APB_DATA_WIDTH : 2; /*!< [1..0] APB data bus width is 32 bits */ - __IM uint32_t MAX_SPEED_MODE : 2; /*!< [3..2] MAX SPEED MODE = FAST MODE */ - __IM uint32_t HC_COUNT_VALUES : 1; /*!< [4..4] Programmable count values for each mode. */ - __IM uint32_t INTR_IO : 1; /*!< [5..5] COMBINED Interrupt outputs */ - __IM uint32_t HAS_DMA : 1; /*!< [6..6] DMA handshaking signals are enabled */ - __IM uint32_t ADD_ENCODED_PARAMS : 1; /*!< [7..7] Encoded parameters not visible */ - __IM uint32_t RX_BUFFER_DEPTH : 8; /*!< [15..8] RX Buffer Depth = 16 */ - __IM uint32_t TX_BUFFER_DEPTH : 8; /*!< [23..16] TX Buffer Depth = 16 */ - uint32_t : 8; - } bit; - } IC_COMP_PARAM_1; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000F8) I2C Component Version Register */ - - struct { - __IM uint32_t IC_COMP_VERSION : 32; /*!< [31..0] IC_COMP_VERSION */ - } bit; - } IC_COMP_VERSION; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000FC) I2C Component Type Register */ - - struct { - __IM uint32_t IC_COMP_TYPE : 32; /*!< [31..0] Designware Component Type number = 0x44_57_01_40. This - assigned unique hex value is constant and is derived from - the two ASCII letters 'DW' followed by a 16-bit unsigned - number. */ - } bit; - } IC_COMP_TYPE; + __IOM uint32_t IC_COMP_VERSION; /*!< (@ 0x000000F8) I2C Component Version Register */ + __IOM uint32_t IC_COMP_TYPE; /*!< (@ 0x000000FC) I2C Component Type Register */ } I2C0_Type; /*!< Size = 256 (0x100) */ @@ -8121,142 +1197,20 @@ typedef struct { /*!< (@ 0x40044000) I2C0 Structu */ typedef struct { /*!< (@ 0x4004C000) ADC Structure */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000000) ADC Control and Status */ - - struct { - __IOM uint32_t EN : 1; /*!< [0..0] Power on ADC and enable its clock. - 1 - enabled. 0 - disabled. */ - __IOM uint32_t TS_EN : 1; /*!< [1..1] Power on temperature sensor. 1 - enabled. 0 - disabled. */ - __IOM uint32_t START_ONCE : 1; /*!< [2..2] Start a single conversion. Self-clearing. Ignored if - start_many is asserted. */ - __IOM uint32_t START_MANY : 1; /*!< [3..3] Continuously perform conversions whilst this bit is 1. - A new conversion will start immediately after the previous - finishes. */ - uint32_t : 4; - __IM uint32_t READY : 1; /*!< [8..8] 1 if the ADC is ready to start a new conversion. Implies - any previous conversion has completed. - 0 whilst conversion in progress. */ - __IM uint32_t ERR : 1; /*!< [9..9] The most recent ADC conversion encountered an error; - result is undefined or noisy. */ - __IOM uint32_t ERR_STICKY : 1; /*!< [10..10] Some past ADC conversion encountered an error. Write - 1 to clear. */ - uint32_t : 1; - __IOM uint32_t AINSEL : 3; /*!< [14..12] Select analog mux input. Updated automatically in round-robin - mode. */ - uint32_t : 1; - __IOM uint32_t RROBIN : 5; /*!< [20..16] Round-robin sampling. 1 bit per channel. Set all bits - to 0 to disable. - Otherwise, the ADC will cycle through each enabled channel - in a round-robin fashion. - The first channel to be sampled will be the one currently - indicated by AINSEL. - AINSEL will be updated after each conversion with the newly-selected - channel. */ - uint32_t : 11; - } bit; - } CS; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Result of most recent ADC conversion */ - - struct { - __IM uint32_t RESULT : 12; /*!< [11..0] RESULT */ - uint32_t : 20; - } bit; - } RESULT; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000008) FIFO control and status */ - - struct { - __IOM uint32_t EN : 1; /*!< [0..0] If 1: write result to the FIFO after each conversion. */ - __IOM uint32_t SHIFT : 1; /*!< [1..1] If 1: FIFO results are right-shifted to be one byte in - size. Enables DMA to byte buffers. */ - __IOM uint32_t ERR : 1; /*!< [2..2] If 1: conversion error bit appears in the FIFO alongside - the result */ - __IOM uint32_t DREQ_EN : 1; /*!< [3..3] If 1: assert DMA requests when FIFO contains data */ - uint32_t : 4; - __IM uint32_t EMPTY : 1; /*!< [8..8] EMPTY */ - __IM uint32_t FULL : 1; /*!< [9..9] FULL */ - __IOM uint32_t UNDER : 1; /*!< [10..10] 1 if the FIFO has been underflowed. Write 1 to clear. */ - __IOM uint32_t OVER : 1; /*!< [11..11] 1 if the FIFO has been overflowed. Write 1 to clear. */ - uint32_t : 4; - __IM uint32_t LEVEL : 4; /*!< [19..16] The number of conversion results currently waiting - in the FIFO */ - uint32_t : 4; - __IOM uint32_t THRESH : 4; /*!< [27..24] DREQ/IRQ asserted when level >= threshold */ - uint32_t : 4; - } bit; - } FCS; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) Conversion result FIFO */ - - struct { - __IM uint32_t VAL : 12; /*!< [11..0] VAL */ - uint32_t : 3; - __IM uint32_t ERR : 1; /*!< [15..15] 1 if this particular sample experienced a conversion - error. Remains in the same location if the sample is shifted. */ - uint32_t : 16; - } bit; - } FIFO; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000010) Clock divider. If non-zero, CS_START_MANY will + __IOM uint32_t CS; /*!< (@ 0x00000000) ADC Control and Status */ + __IOM uint32_t RESULT; /*!< (@ 0x00000004) Result of most recent ADC conversion */ + __IOM uint32_t FCS; /*!< (@ 0x00000008) FIFO control and status */ + __IOM uint32_t FIFO; /*!< (@ 0x0000000C) Conversion result FIFO */ + __IOM uint32_t DIV; /*!< (@ 0x00000010) Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256 */ - - struct { - __IOM uint32_t FRAC : 8; /*!< [7..0] Fractional part of clock divisor. First-order delta-sigma. */ - __IOM uint32_t INT : 16; /*!< [23..8] Integer part of clock divisor. */ - uint32_t : 8; - } bit; - } DIV; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000014) Raw Interrupts */ - - struct { - __IM uint32_t FIFO : 1; /*!< [0..0] Triggered when the sample FIFO reaches a certain level. - This level can be programmed via the FCS_THRESH field. */ - uint32_t : 31; - } bit; - } INTR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000018) Interrupt Enable */ - - struct { - __IOM uint32_t FIFO : 1; /*!< [0..0] Triggered when the sample FIFO reaches a certain level. - This level can be programmed via the FCS_THRESH field. */ - uint32_t : 31; - } bit; - } INTE; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) Interrupt Force */ - - struct { - __IOM uint32_t FIFO : 1; /*!< [0..0] Triggered when the sample FIFO reaches a certain level. - This level can be programmed via the FCS_THRESH field. */ - uint32_t : 31; - } bit; - } INTF; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000020) Interrupt status after masking & forcing */ - - struct { - __IM uint32_t FIFO : 1; /*!< [0..0] Triggered when the sample FIFO reaches a certain level. - This level can be programmed via the FCS_THRESH field. */ - uint32_t : 31; - } bit; - } INTS; + __IOM uint32_t INTR; /*!< (@ 0x00000014) Raw Interrupts */ + __IOM uint32_t INTE; /*!< (@ 0x00000018) Interrupt Enable */ + __IOM uint32_t INTF; /*!< (@ 0x0000001C) Interrupt Force */ + __IOM uint32_t INTS; /*!< (@ 0x00000020) Interrupt status after masking & forcing */ } ADC_Type; /*!< Size = 36 (0x24) */ @@ -8271,513 +1225,79 @@ typedef struct { /*!< (@ 0x4004C000) ADC Structur */ typedef struct { /*!< (@ 0x40050000) PWM Structure */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Control and status register */ - - struct { - __IOM uint32_t EN : 1; /*!< [0..0] Enable the PWM channel. */ - __IOM uint32_t PH_CORRECT : 1; /*!< [1..1] 1: Enable phase-correct modulation. 0: Trailing-edge */ - __IOM uint32_t A_INV : 1; /*!< [2..2] Invert output A */ - __IOM uint32_t B_INV : 1; /*!< [3..3] Invert output B */ - __IOM uint32_t DIVMODE : 2; /*!< [5..4] DIVMODE */ - __IOM uint32_t PH_RET : 1; /*!< [6..6] Retard the phase of the counter by 1 count, while it - is running. - Self-clearing. Write a 1, and poll until low. Counter must - be running. */ - __IOM uint32_t PH_ADV : 1; /*!< [7..7] Advance the phase of the counter by 1 count, while it - is running. - Self-clearing. Write a 1, and poll until low. Counter must - be running - at less than full speed (div_int + div_frac / 16 > 1) */ - uint32_t : 24; - } bit; - } CH0_CSR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000004) INT and FRAC form a fixed-point fractional number. + __IOM uint32_t CH0_CSR; /*!< (@ 0x00000000) Control and status register */ + __IOM uint32_t CH0_DIV; /*!< (@ 0x00000004) INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta. */ - - struct { - __IOM uint32_t FRAC : 4; /*!< [3..0] FRAC */ - __IOM uint32_t INT : 8; /*!< [11..4] INT */ - uint32_t : 20; - } bit; - } CH0_DIV; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000008) Direct access to the PWM counter */ - - struct { - __IOM uint32_t CH0_CTR : 16; /*!< [15..0] CH0_CTR */ - uint32_t : 16; - } bit; - } CH0_CTR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) Counter compare values */ - - struct { - __IOM uint32_t A : 16; /*!< [15..0] A */ - __IOM uint32_t B : 16; /*!< [31..16] B */ - } bit; - } CH0_CC; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000010) Counter wrap value */ - - struct { - __IOM uint32_t CH0_TOP : 16; /*!< [15..0] CH0_TOP */ - uint32_t : 16; - } bit; - } CH0_TOP; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000014) Control and status register */ - - struct { - __IOM uint32_t EN : 1; /*!< [0..0] Enable the PWM channel. */ - __IOM uint32_t PH_CORRECT : 1; /*!< [1..1] 1: Enable phase-correct modulation. 0: Trailing-edge */ - __IOM uint32_t A_INV : 1; /*!< [2..2] Invert output A */ - __IOM uint32_t B_INV : 1; /*!< [3..3] Invert output B */ - __IOM uint32_t DIVMODE : 2; /*!< [5..4] DIVMODE */ - __IOM uint32_t PH_RET : 1; /*!< [6..6] Retard the phase of the counter by 1 count, while it - is running. - Self-clearing. Write a 1, and poll until low. Counter must - be running. */ - __IOM uint32_t PH_ADV : 1; /*!< [7..7] Advance the phase of the counter by 1 count, while it - is running. - Self-clearing. Write a 1, and poll until low. Counter must - be running - at less than full speed (div_int + div_frac / 16 > 1) */ - uint32_t : 24; - } bit; - } CH1_CSR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000018) INT and FRAC form a fixed-point fractional number. + __IOM uint32_t CH0_CTR; /*!< (@ 0x00000008) Direct access to the PWM counter */ + __IOM uint32_t CH0_CC; /*!< (@ 0x0000000C) Counter compare values */ + __IOM uint32_t CH0_TOP; /*!< (@ 0x00000010) Counter wrap value */ + __IOM uint32_t CH1_CSR; /*!< (@ 0x00000014) Control and status register */ + __IOM uint32_t CH1_DIV; /*!< (@ 0x00000018) INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta. */ - - struct { - __IOM uint32_t FRAC : 4; /*!< [3..0] FRAC */ - __IOM uint32_t INT : 8; /*!< [11..4] INT */ - uint32_t : 20; - } bit; - } CH1_DIV; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) Direct access to the PWM counter */ - - struct { - __IOM uint32_t CH1_CTR : 16; /*!< [15..0] CH1_CTR */ - uint32_t : 16; - } bit; - } CH1_CTR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000020) Counter compare values */ - - struct { - __IOM uint32_t A : 16; /*!< [15..0] A */ - __IOM uint32_t B : 16; /*!< [31..16] B */ - } bit; - } CH1_CC; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000024) Counter wrap value */ - - struct { - __IOM uint32_t CH1_TOP : 16; /*!< [15..0] CH1_TOP */ - uint32_t : 16; - } bit; - } CH1_TOP; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000028) Control and status register */ - - struct { - __IOM uint32_t EN : 1; /*!< [0..0] Enable the PWM channel. */ - __IOM uint32_t PH_CORRECT : 1; /*!< [1..1] 1: Enable phase-correct modulation. 0: Trailing-edge */ - __IOM uint32_t A_INV : 1; /*!< [2..2] Invert output A */ - __IOM uint32_t B_INV : 1; /*!< [3..3] Invert output B */ - __IOM uint32_t DIVMODE : 2; /*!< [5..4] DIVMODE */ - __IOM uint32_t PH_RET : 1; /*!< [6..6] Retard the phase of the counter by 1 count, while it - is running. - Self-clearing. Write a 1, and poll until low. Counter must - be running. */ - __IOM uint32_t PH_ADV : 1; /*!< [7..7] Advance the phase of the counter by 1 count, while it - is running. - Self-clearing. Write a 1, and poll until low. Counter must - be running - at less than full speed (div_int + div_frac / 16 > 1) */ - uint32_t : 24; - } bit; - } CH2_CSR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000002C) INT and FRAC form a fixed-point fractional number. + __IOM uint32_t CH1_CTR; /*!< (@ 0x0000001C) Direct access to the PWM counter */ + __IOM uint32_t CH1_CC; /*!< (@ 0x00000020) Counter compare values */ + __IOM uint32_t CH1_TOP; /*!< (@ 0x00000024) Counter wrap value */ + __IOM uint32_t CH2_CSR; /*!< (@ 0x00000028) Control and status register */ + __IOM uint32_t CH2_DIV; /*!< (@ 0x0000002C) INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta. */ - - struct { - __IOM uint32_t FRAC : 4; /*!< [3..0] FRAC */ - __IOM uint32_t INT : 8; /*!< [11..4] INT */ - uint32_t : 20; - } bit; - } CH2_DIV; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000030) Direct access to the PWM counter */ - - struct { - __IOM uint32_t CH2_CTR : 16; /*!< [15..0] CH2_CTR */ - uint32_t : 16; - } bit; - } CH2_CTR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000034) Counter compare values */ - - struct { - __IOM uint32_t A : 16; /*!< [15..0] A */ - __IOM uint32_t B : 16; /*!< [31..16] B */ - } bit; - } CH2_CC; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000038) Counter wrap value */ - - struct { - __IOM uint32_t CH2_TOP : 16; /*!< [15..0] CH2_TOP */ - uint32_t : 16; - } bit; - } CH2_TOP; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000003C) Control and status register */ - - struct { - __IOM uint32_t EN : 1; /*!< [0..0] Enable the PWM channel. */ - __IOM uint32_t PH_CORRECT : 1; /*!< [1..1] 1: Enable phase-correct modulation. 0: Trailing-edge */ - __IOM uint32_t A_INV : 1; /*!< [2..2] Invert output A */ - __IOM uint32_t B_INV : 1; /*!< [3..3] Invert output B */ - __IOM uint32_t DIVMODE : 2; /*!< [5..4] DIVMODE */ - __IOM uint32_t PH_RET : 1; /*!< [6..6] Retard the phase of the counter by 1 count, while it - is running. - Self-clearing. Write a 1, and poll until low. Counter must - be running. */ - __IOM uint32_t PH_ADV : 1; /*!< [7..7] Advance the phase of the counter by 1 count, while it - is running. - Self-clearing. Write a 1, and poll until low. Counter must - be running - at less than full speed (div_int + div_frac / 16 > 1) */ - uint32_t : 24; - } bit; - } CH3_CSR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000040) INT and FRAC form a fixed-point fractional number. + __IOM uint32_t CH2_CTR; /*!< (@ 0x00000030) Direct access to the PWM counter */ + __IOM uint32_t CH2_CC; /*!< (@ 0x00000034) Counter compare values */ + __IOM uint32_t CH2_TOP; /*!< (@ 0x00000038) Counter wrap value */ + __IOM uint32_t CH3_CSR; /*!< (@ 0x0000003C) Control and status register */ + __IOM uint32_t CH3_DIV; /*!< (@ 0x00000040) INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta. */ - - struct { - __IOM uint32_t FRAC : 4; /*!< [3..0] FRAC */ - __IOM uint32_t INT : 8; /*!< [11..4] INT */ - uint32_t : 20; - } bit; - } CH3_DIV; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000044) Direct access to the PWM counter */ - - struct { - __IOM uint32_t CH3_CTR : 16; /*!< [15..0] CH3_CTR */ - uint32_t : 16; - } bit; - } CH3_CTR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000048) Counter compare values */ - - struct { - __IOM uint32_t A : 16; /*!< [15..0] A */ - __IOM uint32_t B : 16; /*!< [31..16] B */ - } bit; - } CH3_CC; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000004C) Counter wrap value */ - - struct { - __IOM uint32_t CH3_TOP : 16; /*!< [15..0] CH3_TOP */ - uint32_t : 16; - } bit; - } CH3_TOP; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000050) Control and status register */ - - struct { - __IOM uint32_t EN : 1; /*!< [0..0] Enable the PWM channel. */ - __IOM uint32_t PH_CORRECT : 1; /*!< [1..1] 1: Enable phase-correct modulation. 0: Trailing-edge */ - __IOM uint32_t A_INV : 1; /*!< [2..2] Invert output A */ - __IOM uint32_t B_INV : 1; /*!< [3..3] Invert output B */ - __IOM uint32_t DIVMODE : 2; /*!< [5..4] DIVMODE */ - __IOM uint32_t PH_RET : 1; /*!< [6..6] Retard the phase of the counter by 1 count, while it - is running. - Self-clearing. Write a 1, and poll until low. Counter must - be running. */ - __IOM uint32_t PH_ADV : 1; /*!< [7..7] Advance the phase of the counter by 1 count, while it - is running. - Self-clearing. Write a 1, and poll until low. Counter must - be running - at less than full speed (div_int + div_frac / 16 > 1) */ - uint32_t : 24; - } bit; - } CH4_CSR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000054) INT and FRAC form a fixed-point fractional number. + __IOM uint32_t CH3_CTR; /*!< (@ 0x00000044) Direct access to the PWM counter */ + __IOM uint32_t CH3_CC; /*!< (@ 0x00000048) Counter compare values */ + __IOM uint32_t CH3_TOP; /*!< (@ 0x0000004C) Counter wrap value */ + __IOM uint32_t CH4_CSR; /*!< (@ 0x00000050) Control and status register */ + __IOM uint32_t CH4_DIV; /*!< (@ 0x00000054) INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta. */ - - struct { - __IOM uint32_t FRAC : 4; /*!< [3..0] FRAC */ - __IOM uint32_t INT : 8; /*!< [11..4] INT */ - uint32_t : 20; - } bit; - } CH4_DIV; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000058) Direct access to the PWM counter */ - - struct { - __IOM uint32_t CH4_CTR : 16; /*!< [15..0] CH4_CTR */ - uint32_t : 16; - } bit; - } CH4_CTR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000005C) Counter compare values */ - - struct { - __IOM uint32_t A : 16; /*!< [15..0] A */ - __IOM uint32_t B : 16; /*!< [31..16] B */ - } bit; - } CH4_CC; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000060) Counter wrap value */ - - struct { - __IOM uint32_t CH4_TOP : 16; /*!< [15..0] CH4_TOP */ - uint32_t : 16; - } bit; - } CH4_TOP; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000064) Control and status register */ - - struct { - __IOM uint32_t EN : 1; /*!< [0..0] Enable the PWM channel. */ - __IOM uint32_t PH_CORRECT : 1; /*!< [1..1] 1: Enable phase-correct modulation. 0: Trailing-edge */ - __IOM uint32_t A_INV : 1; /*!< [2..2] Invert output A */ - __IOM uint32_t B_INV : 1; /*!< [3..3] Invert output B */ - __IOM uint32_t DIVMODE : 2; /*!< [5..4] DIVMODE */ - __IOM uint32_t PH_RET : 1; /*!< [6..6] Retard the phase of the counter by 1 count, while it - is running. - Self-clearing. Write a 1, and poll until low. Counter must - be running. */ - __IOM uint32_t PH_ADV : 1; /*!< [7..7] Advance the phase of the counter by 1 count, while it - is running. - Self-clearing. Write a 1, and poll until low. Counter must - be running - at less than full speed (div_int + div_frac / 16 > 1) */ - uint32_t : 24; - } bit; - } CH5_CSR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000068) INT and FRAC form a fixed-point fractional number. + __IOM uint32_t CH4_CTR; /*!< (@ 0x00000058) Direct access to the PWM counter */ + __IOM uint32_t CH4_CC; /*!< (@ 0x0000005C) Counter compare values */ + __IOM uint32_t CH4_TOP; /*!< (@ 0x00000060) Counter wrap value */ + __IOM uint32_t CH5_CSR; /*!< (@ 0x00000064) Control and status register */ + __IOM uint32_t CH5_DIV; /*!< (@ 0x00000068) INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta. */ - - struct { - __IOM uint32_t FRAC : 4; /*!< [3..0] FRAC */ - __IOM uint32_t INT : 8; /*!< [11..4] INT */ - uint32_t : 20; - } bit; - } CH5_DIV; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000006C) Direct access to the PWM counter */ - - struct { - __IOM uint32_t CH5_CTR : 16; /*!< [15..0] CH5_CTR */ - uint32_t : 16; - } bit; - } CH5_CTR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000070) Counter compare values */ - - struct { - __IOM uint32_t A : 16; /*!< [15..0] A */ - __IOM uint32_t B : 16; /*!< [31..16] B */ - } bit; - } CH5_CC; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000074) Counter wrap value */ - - struct { - __IOM uint32_t CH5_TOP : 16; /*!< [15..0] CH5_TOP */ - uint32_t : 16; - } bit; - } CH5_TOP; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000078) Control and status register */ - - struct { - __IOM uint32_t EN : 1; /*!< [0..0] Enable the PWM channel. */ - __IOM uint32_t PH_CORRECT : 1; /*!< [1..1] 1: Enable phase-correct modulation. 0: Trailing-edge */ - __IOM uint32_t A_INV : 1; /*!< [2..2] Invert output A */ - __IOM uint32_t B_INV : 1; /*!< [3..3] Invert output B */ - __IOM uint32_t DIVMODE : 2; /*!< [5..4] DIVMODE */ - __IOM uint32_t PH_RET : 1; /*!< [6..6] Retard the phase of the counter by 1 count, while it - is running. - Self-clearing. Write a 1, and poll until low. Counter must - be running. */ - __IOM uint32_t PH_ADV : 1; /*!< [7..7] Advance the phase of the counter by 1 count, while it - is running. - Self-clearing. Write a 1, and poll until low. Counter must - be running - at less than full speed (div_int + div_frac / 16 > 1) */ - uint32_t : 24; - } bit; - } CH6_CSR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000007C) INT and FRAC form a fixed-point fractional number. + __IOM uint32_t CH5_CTR; /*!< (@ 0x0000006C) Direct access to the PWM counter */ + __IOM uint32_t CH5_CC; /*!< (@ 0x00000070) Counter compare values */ + __IOM uint32_t CH5_TOP; /*!< (@ 0x00000074) Counter wrap value */ + __IOM uint32_t CH6_CSR; /*!< (@ 0x00000078) Control and status register */ + __IOM uint32_t CH6_DIV; /*!< (@ 0x0000007C) INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta. */ - - struct { - __IOM uint32_t FRAC : 4; /*!< [3..0] FRAC */ - __IOM uint32_t INT : 8; /*!< [11..4] INT */ - uint32_t : 20; - } bit; - } CH6_DIV; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000080) Direct access to the PWM counter */ - - struct { - __IOM uint32_t CH6_CTR : 16; /*!< [15..0] CH6_CTR */ - uint32_t : 16; - } bit; - } CH6_CTR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000084) Counter compare values */ - - struct { - __IOM uint32_t A : 16; /*!< [15..0] A */ - __IOM uint32_t B : 16; /*!< [31..16] B */ - } bit; - } CH6_CC; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000088) Counter wrap value */ - - struct { - __IOM uint32_t CH6_TOP : 16; /*!< [15..0] CH6_TOP */ - uint32_t : 16; - } bit; - } CH6_TOP; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000008C) Control and status register */ - - struct { - __IOM uint32_t EN : 1; /*!< [0..0] Enable the PWM channel. */ - __IOM uint32_t PH_CORRECT : 1; /*!< [1..1] 1: Enable phase-correct modulation. 0: Trailing-edge */ - __IOM uint32_t A_INV : 1; /*!< [2..2] Invert output A */ - __IOM uint32_t B_INV : 1; /*!< [3..3] Invert output B */ - __IOM uint32_t DIVMODE : 2; /*!< [5..4] DIVMODE */ - __IOM uint32_t PH_RET : 1; /*!< [6..6] Retard the phase of the counter by 1 count, while it - is running. - Self-clearing. Write a 1, and poll until low. Counter must - be running. */ - __IOM uint32_t PH_ADV : 1; /*!< [7..7] Advance the phase of the counter by 1 count, while it - is running. - Self-clearing. Write a 1, and poll until low. Counter must - be running - at less than full speed (div_int + div_frac / 16 > 1) */ - uint32_t : 24; - } bit; - } CH7_CSR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000090) INT and FRAC form a fixed-point fractional number. + __IOM uint32_t CH6_CTR; /*!< (@ 0x00000080) Direct access to the PWM counter */ + __IOM uint32_t CH6_CC; /*!< (@ 0x00000084) Counter compare values */ + __IOM uint32_t CH6_TOP; /*!< (@ 0x00000088) Counter wrap value */ + __IOM uint32_t CH7_CSR; /*!< (@ 0x0000008C) Control and status register */ + __IOM uint32_t CH7_DIV; /*!< (@ 0x00000090) INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta. */ - - struct { - __IOM uint32_t FRAC : 4; /*!< [3..0] FRAC */ - __IOM uint32_t INT : 8; /*!< [11..4] INT */ - uint32_t : 20; - } bit; - } CH7_DIV; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000094) Direct access to the PWM counter */ - - struct { - __IOM uint32_t CH7_CTR : 16; /*!< [15..0] CH7_CTR */ - uint32_t : 16; - } bit; - } CH7_CTR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000098) Counter compare values */ - - struct { - __IOM uint32_t A : 16; /*!< [15..0] A */ - __IOM uint32_t B : 16; /*!< [31..16] B */ - } bit; - } CH7_CC; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000009C) Counter wrap value */ - - struct { - __IOM uint32_t CH7_TOP : 16; /*!< [15..0] CH7_TOP */ - uint32_t : 16; - } bit; - } CH7_TOP; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000A0) This register aliases the CSR_EN bits for all + __IOM uint32_t CH7_CTR; /*!< (@ 0x00000094) Direct access to the PWM counter */ + __IOM uint32_t CH7_CC; /*!< (@ 0x00000098) Counter compare values */ + __IOM uint32_t CH7_TOP; /*!< (@ 0x0000009C) Counter wrap value */ + __IOM uint32_t EN; /*!< (@ 0x000000A0) This register aliases the CSR_EN bits for all channels. Writing to this register allows multiple channels to be enabled @@ -8786,83 +1306,10 @@ typedef struct { /*!< (@ 0x40050000) PWM Structur For each channel, there is only one physical EN register bit, which can be accessed through here or CHx_CSR. */ - - struct { - __IOM uint32_t CH0 : 1; /*!< [0..0] CH0 */ - __IOM uint32_t CH1 : 1; /*!< [1..1] CH1 */ - __IOM uint32_t CH2 : 1; /*!< [2..2] CH2 */ - __IOM uint32_t CH3 : 1; /*!< [3..3] CH3 */ - __IOM uint32_t CH4 : 1; /*!< [4..4] CH4 */ - __IOM uint32_t CH5 : 1; /*!< [5..5] CH5 */ - __IOM uint32_t CH6 : 1; /*!< [6..6] CH6 */ - __IOM uint32_t CH7 : 1; /*!< [7..7] CH7 */ - uint32_t : 24; - } bit; - } EN; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000A4) Raw Interrupts */ - - struct { - __IOM uint32_t CH0 : 1; /*!< [0..0] CH0 */ - __IOM uint32_t CH1 : 1; /*!< [1..1] CH1 */ - __IOM uint32_t CH2 : 1; /*!< [2..2] CH2 */ - __IOM uint32_t CH3 : 1; /*!< [3..3] CH3 */ - __IOM uint32_t CH4 : 1; /*!< [4..4] CH4 */ - __IOM uint32_t CH5 : 1; /*!< [5..5] CH5 */ - __IOM uint32_t CH6 : 1; /*!< [6..6] CH6 */ - __IOM uint32_t CH7 : 1; /*!< [7..7] CH7 */ - uint32_t : 24; - } bit; - } INTR; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000A8) Interrupt Enable */ - - struct { - __IOM uint32_t CH0 : 1; /*!< [0..0] CH0 */ - __IOM uint32_t CH1 : 1; /*!< [1..1] CH1 */ - __IOM uint32_t CH2 : 1; /*!< [2..2] CH2 */ - __IOM uint32_t CH3 : 1; /*!< [3..3] CH3 */ - __IOM uint32_t CH4 : 1; /*!< [4..4] CH4 */ - __IOM uint32_t CH5 : 1; /*!< [5..5] CH5 */ - __IOM uint32_t CH6 : 1; /*!< [6..6] CH6 */ - __IOM uint32_t CH7 : 1; /*!< [7..7] CH7 */ - uint32_t : 24; - } bit; - } INTE; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000AC) Interrupt Force */ - - struct { - __IOM uint32_t CH0 : 1; /*!< [0..0] CH0 */ - __IOM uint32_t CH1 : 1; /*!< [1..1] CH1 */ - __IOM uint32_t CH2 : 1; /*!< [2..2] CH2 */ - __IOM uint32_t CH3 : 1; /*!< [3..3] CH3 */ - __IOM uint32_t CH4 : 1; /*!< [4..4] CH4 */ - __IOM uint32_t CH5 : 1; /*!< [5..5] CH5 */ - __IOM uint32_t CH6 : 1; /*!< [6..6] CH6 */ - __IOM uint32_t CH7 : 1; /*!< [7..7] CH7 */ - uint32_t : 24; - } bit; - } INTF; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000B0) Interrupt status after masking & forcing */ - - struct { - __IM uint32_t CH0 : 1; /*!< [0..0] CH0 */ - __IM uint32_t CH1 : 1; /*!< [1..1] CH1 */ - __IM uint32_t CH2 : 1; /*!< [2..2] CH2 */ - __IM uint32_t CH3 : 1; /*!< [3..3] CH3 */ - __IM uint32_t CH4 : 1; /*!< [4..4] CH4 */ - __IM uint32_t CH5 : 1; /*!< [5..5] CH5 */ - __IM uint32_t CH6 : 1; /*!< [6..6] CH6 */ - __IM uint32_t CH7 : 1; /*!< [7..7] CH7 */ - uint32_t : 24; - } bit; - } INTS; + __IOM uint32_t INTR; /*!< (@ 0x000000A4) Raw Interrupts */ + __IOM uint32_t INTE; /*!< (@ 0x000000A8) Interrupt Enable */ + __IOM uint32_t INTF; /*!< (@ 0x000000AC) Interrupt Force */ + __IOM uint32_t INTS; /*!< (@ 0x000000B0) Interrupt status after masking & forcing */ } PWM_Type; /*!< Size = 180 (0xb4) */ @@ -8922,92 +1369,22 @@ typedef struct { /*!< (@ 0x40054000) TIMER Struct and can be disarmed early using the ARMED status register. */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000020) Indicates the armed/disarmed status of each alarm. + __IOM uint32_t ARMED; /*!< (@ 0x00000020) Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing, but writing ones here will disarm immediately without waiting to fire. */ - - struct { - __IOM uint32_t ARMED : 4; /*!< [3..0] ARMED */ - uint32_t : 28; - } bit; - } ARMED; __IM uint32_t TIMERAWH; /*!< (@ 0x00000024) Raw read from bits 63:32 of time (no side effects) */ __IM uint32_t TIMERAWL; /*!< (@ 0x00000028) Raw read from bits 31:0 of time (no side effects) */ - - union { - __IOM uint32_t reg; /*!< (@ 0x0000002C) Set bits high to enable pause when the corresponding + __IOM uint32_t DBGPAUSE; /*!< (@ 0x0000002C) Set bits high to enable pause when the corresponding debug ports are active */ - - struct { - uint32_t : 1; - __IOM uint32_t DBG0 : 1; /*!< [1..1] Pause when processor 0 is in debug mode */ - __IOM uint32_t DBG1 : 1; /*!< [2..2] Pause when processor 1 is in debug mode */ - uint32_t : 29; - } bit; - } DBGPAUSE; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000030) Set high to pause the timer */ - - struct { - __IOM uint32_t PAUSE : 1; /*!< [0..0] PAUSE */ - uint32_t : 31; - } bit; - } PAUSE; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000034) Raw Interrupts */ - - struct { - __IOM uint32_t ALARM_0 : 1; /*!< [0..0] ALARM_0 */ - __IOM uint32_t ALARM_1 : 1; /*!< [1..1] ALARM_1 */ - __IOM uint32_t ALARM_2 : 1; /*!< [2..2] ALARM_2 */ - __IOM uint32_t ALARM_3 : 1; /*!< [3..3] ALARM_3 */ - uint32_t : 28; - } bit; - } INTR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000038) Interrupt Enable */ - - struct { - __IOM uint32_t ALARM_0 : 1; /*!< [0..0] ALARM_0 */ - __IOM uint32_t ALARM_1 : 1; /*!< [1..1] ALARM_1 */ - __IOM uint32_t ALARM_2 : 1; /*!< [2..2] ALARM_2 */ - __IOM uint32_t ALARM_3 : 1; /*!< [3..3] ALARM_3 */ - uint32_t : 28; - } bit; - } INTE; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000003C) Interrupt Force */ - - struct { - __IOM uint32_t ALARM_0 : 1; /*!< [0..0] ALARM_0 */ - __IOM uint32_t ALARM_1 : 1; /*!< [1..1] ALARM_1 */ - __IOM uint32_t ALARM_2 : 1; /*!< [2..2] ALARM_2 */ - __IOM uint32_t ALARM_3 : 1; /*!< [3..3] ALARM_3 */ - uint32_t : 28; - } bit; - } INTF; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000040) Interrupt status after masking & forcing */ - - struct { - __IM uint32_t ALARM_0 : 1; /*!< [0..0] ALARM_0 */ - __IM uint32_t ALARM_1 : 1; /*!< [1..1] ALARM_1 */ - __IM uint32_t ALARM_2 : 1; /*!< [2..2] ALARM_2 */ - __IM uint32_t ALARM_3 : 1; /*!< [3..3] ALARM_3 */ - uint32_t : 28; - } bit; - } INTS; + __IOM uint32_t PAUSE; /*!< (@ 0x00000030) Set high to pause the timer */ + __IOM uint32_t INTR; /*!< (@ 0x00000034) Raw Interrupts */ + __IOM uint32_t INTE; /*!< (@ 0x00000038) Interrupt Enable */ + __IOM uint32_t INTF; /*!< (@ 0x0000003C) Interrupt Force */ + __IOM uint32_t INTS; /*!< (@ 0x00000040) Interrupt status after masking & forcing */ } TIMER_Type; /*!< Size = 68 (0x44) */ @@ -9022,51 +1399,17 @@ typedef struct { /*!< (@ 0x40054000) TIMER Struct */ typedef struct { /*!< (@ 0x40058000) WATCHDOG Structure */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Watchdog control + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Watchdog control The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. The watchdog can be triggered in software. */ - - struct { - __IM uint32_t TIME : 24; /*!< [23..0] Indicates the number of ticks / 2 (see errata RP2040-E1) - before a watchdog reset will be triggered */ - __IOM uint32_t PAUSE_JTAG : 1; /*!< [24..24] Pause the watchdog timer when JTAG is accessing the - bus fabric */ - __IOM uint32_t PAUSE_DBG0 : 1; /*!< [25..25] Pause the watchdog timer when processor 0 is in debug - mode */ - __IOM uint32_t PAUSE_DBG1 : 1; /*!< [26..26] Pause the watchdog timer when processor 1 is in debug - mode */ - uint32_t : 3; - __IOM uint32_t ENABLE : 1; /*!< [30..30] When not enabled the watchdog timer is paused */ - __IOM uint32_t TRIGGER : 1; /*!< [31..31] Trigger a watchdog reset */ - } bit; - } CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Load the watchdog timer. The maximum setting + __IOM uint32_t LOAD; /*!< (@ 0x00000004) Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1). */ - - struct { - __OM uint32_t LOAD : 24; /*!< [23..0] LOAD */ - uint32_t : 8; - } bit; - } LOAD; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000008) Logs the reason for the last reset. Both bits + __IOM uint32_t REASON; /*!< (@ 0x00000008) Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. */ - - struct { - __IM uint32_t TIMER : 1; /*!< [0..0] TIMER */ - __IM uint32_t FORCE : 1; /*!< [1..1] FORCE */ - uint32_t : 30; - } bit; - } REASON; __IOM uint32_t SCRATCH0; /*!< (@ 0x0000000C) Scratch register. Information persists through soft reset of the chip. */ __IOM uint32_t SCRATCH1; /*!< (@ 0x00000010) Scratch register. Information persists through @@ -9083,19 +1426,7 @@ typedef struct { /*!< (@ 0x40058000) WATCHDOG Str soft reset of the chip. */ __IOM uint32_t SCRATCH7; /*!< (@ 0x00000028) Scratch register. Information persists through soft reset of the chip. */ - - union { - __IOM uint32_t reg; /*!< (@ 0x0000002C) Controls the tick generator */ - - struct { - __IOM uint32_t CYCLES : 9; /*!< [8..0] Total number of clk_tick cycles before the next tick. */ - __IOM uint32_t ENABLE : 1; /*!< [9..9] start / stop tick generation */ - __IM uint32_t RUNNING : 1; /*!< [10..10] Is the tick generator running? */ - __IM uint32_t COUNT : 9; /*!< [19..11] Count down timer: the remaining number clk_tick cycles - before the next tick is generated. */ - uint32_t : 12; - } bit; - } TICK; + __IOM uint32_t TICK; /*!< (@ 0x0000002C) Controls the tick generator */ } WATCHDOG_Type; /*!< Size = 48 (0x30) */ @@ -9110,160 +1441,20 @@ typedef struct { /*!< (@ 0x40058000) WATCHDOG Str */ typedef struct { /*!< (@ 0x4005C000) RTC Structure */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Divider minus 1 for the 1 second counter. Safe + __IOM uint32_t CLKDIV_M1; /*!< (@ 0x00000000) Divider minus 1 for the 1 second counter. Safe to change the value when RTC is not enabled. */ - - struct { - __IOM uint32_t CLKDIV_M1 : 16; /*!< [15..0] CLKDIV_M1 */ - uint32_t : 16; - } bit; - } CLKDIV_M1; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000004) RTC setup register 0 */ - - struct { - __IOM uint32_t DAY : 5; /*!< [4..0] Day of the month (1..31) */ - uint32_t : 3; - __IOM uint32_t MONTH : 4; /*!< [11..8] Month (1..12) */ - __IOM uint32_t YEAR : 12; /*!< [23..12] Year */ - uint32_t : 8; - } bit; - } SETUP_0; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000008) RTC setup register 1 */ - - struct { - __IOM uint32_t SEC : 6; /*!< [5..0] Seconds */ - uint32_t : 2; - __IOM uint32_t MIN : 6; /*!< [13..8] Minutes */ - uint32_t : 2; - __IOM uint32_t HOUR : 5; /*!< [20..16] Hours */ - uint32_t : 3; - __IOM uint32_t DOTW : 3; /*!< [26..24] Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7 */ - uint32_t : 5; - } bit; - } SETUP_1; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) RTC Control and status */ - - struct { - __IOM uint32_t RTC_ENABLE : 1; /*!< [0..0] Enable RTC */ - __IM uint32_t RTC_ACTIVE : 1; /*!< [1..1] RTC enabled (running) */ - uint32_t : 2; - __IOM uint32_t LOAD : 1; /*!< [4..4] Load RTC */ - uint32_t : 3; - __IOM uint32_t FORCE_NOTLEAPYEAR : 1; /*!< [8..8] If set, leapyear is forced off. - Useful for years divisible by 100 but not by 400 */ - uint32_t : 23; - } bit; - } CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000010) Interrupt setup register 0 */ - - struct { - __IOM uint32_t DAY : 5; /*!< [4..0] Day of the month (1..31) */ - uint32_t : 3; - __IOM uint32_t MONTH : 4; /*!< [11..8] Month (1..12) */ - __IOM uint32_t YEAR : 12; /*!< [23..12] Year */ - __IOM uint32_t DAY_ENA : 1; /*!< [24..24] Enable day matching */ - __IOM uint32_t MONTH_ENA : 1; /*!< [25..25] Enable month matching */ - __IOM uint32_t YEAR_ENA : 1; /*!< [26..26] Enable year matching */ - uint32_t : 1; - __IOM uint32_t MATCH_ENA : 1; /*!< [28..28] Global match enable. Don't change any other value while - this one is enabled */ - __IM uint32_t MATCH_ACTIVE : 1; /*!< [29..29] MATCH_ACTIVE */ - uint32_t : 2; - } bit; - } IRQ_SETUP_0; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000014) Interrupt setup register 1 */ - - struct { - __IOM uint32_t SEC : 6; /*!< [5..0] Seconds */ - uint32_t : 2; - __IOM uint32_t MIN : 6; /*!< [13..8] Minutes */ - uint32_t : 2; - __IOM uint32_t HOUR : 5; /*!< [20..16] Hours */ - uint32_t : 3; - __IOM uint32_t DOTW : 3; /*!< [26..24] Day of the week */ - uint32_t : 1; - __IOM uint32_t SEC_ENA : 1; /*!< [28..28] Enable second matching */ - __IOM uint32_t MIN_ENA : 1; /*!< [29..29] Enable minute matching */ - __IOM uint32_t HOUR_ENA : 1; /*!< [30..30] Enable hour matching */ - __IOM uint32_t DOTW_ENA : 1; /*!< [31..31] Enable day of the week matching */ - } bit; - } IRQ_SETUP_1; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000018) RTC register 1. */ - - struct { - __IM uint32_t DAY : 5; /*!< [4..0] Day of the month (1..31) */ - uint32_t : 3; - __IM uint32_t MONTH : 4; /*!< [11..8] Month (1..12) */ - __IM uint32_t YEAR : 12; /*!< [23..12] Year */ - uint32_t : 8; - } bit; - } RTC_1; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) RTC register 0 + __IOM uint32_t SETUP_0; /*!< (@ 0x00000004) RTC setup register 0 */ + __IOM uint32_t SETUP_1; /*!< (@ 0x00000008) RTC setup register 1 */ + __IOM uint32_t CTRL; /*!< (@ 0x0000000C) RTC Control and status */ + __IOM uint32_t IRQ_SETUP_0; /*!< (@ 0x00000010) Interrupt setup register 0 */ + __IOM uint32_t IRQ_SETUP_1; /*!< (@ 0x00000014) Interrupt setup register 1 */ + __IOM uint32_t RTC_1; /*!< (@ 0x00000018) RTC register 1. */ + __IOM uint32_t RTC_0; /*!< (@ 0x0000001C) RTC register 0 Read this before RTC 1! */ - - struct { - __IM uint32_t SEC : 6; /*!< [5..0] Seconds */ - uint32_t : 2; - __IM uint32_t MIN : 6; /*!< [13..8] Minutes */ - uint32_t : 2; - __IM uint32_t HOUR : 5; /*!< [20..16] Hours */ - uint32_t : 3; - __IM uint32_t DOTW : 3; /*!< [26..24] Day of the week */ - uint32_t : 5; - } bit; - } RTC_0; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000020) Raw Interrupts */ - - struct { - __IM uint32_t RTC : 1; /*!< [0..0] RTC */ - uint32_t : 31; - } bit; - } INTR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000024) Interrupt Enable */ - - struct { - __IOM uint32_t RTC : 1; /*!< [0..0] RTC */ - uint32_t : 31; - } bit; - } INTE; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000028) Interrupt Force */ - - struct { - __IOM uint32_t RTC : 1; /*!< [0..0] RTC */ - uint32_t : 31; - } bit; - } INTF; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000002C) Interrupt status after masking & forcing */ - - struct { - __IM uint32_t RTC : 1; /*!< [0..0] RTC */ - uint32_t : 31; - } bit; - } INTS; + __IOM uint32_t INTR; /*!< (@ 0x00000020) Raw Interrupts */ + __IOM uint32_t INTE; /*!< (@ 0x00000024) Interrupt Enable */ + __IOM uint32_t INTF; /*!< (@ 0x00000028) Interrupt Force */ + __IOM uint32_t INTS; /*!< (@ 0x0000002C) Interrupt status after masking & forcing */ } RTC_Type; /*!< Size = 48 (0x30) */ @@ -9278,33 +1469,8 @@ typedef struct { /*!< (@ 0x4005C000) RTC Structur */ typedef struct { /*!< (@ 0x40060000) ROSC Structure */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Ring Oscillator control */ - - struct { - __IOM uint32_t FREQ_RANGE : 12; /*!< [11..0] Controls the number of delay stages in the ROSC ring - LOW uses stages 0 to 7 - MEDIUM uses stages 0 to 5 - HIGH uses stages 0 to 3 - TOOHIGH uses stages 0 to 1 and should not be used because - its frequency exceeds design specifications - The clock output will not glitch when changing the range - up one step at a time - The clock output will glitch when changing the range down - Note: the v */ - __IOM uint32_t ENABLE : 12; /*!< [23..12] On power-up this field is initialised to ENABLE - The system clock must be switched to another source before - setting this field to DISABLE otherwise the chip will lock - up - The 12-bit code is intended to give some protection against - accidental writes. An invalid setting will enable the oscillator. */ - uint32_t : 8; - } bit; - } CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000004) The FREQA & FREQB registers control the frequency + __IOM uint32_t CTRL; /*!< (@ 0x00000000) Ring Oscillator control */ + __IOM uint32_t FREQA; /*!< (@ 0x00000004) The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined @@ -9315,40 +1481,8 @@ typedef struct { /*!< (@ 0x40060000) ROSC Structu 0 bits set is the default drive strength 1 bit set doubles the drive strength 2 bits set triples drive strength - 3 bits set quadruples */ - - struct { - __IOM uint32_t DS0 : 3; /*!< [2..0] Stage 0 drive strength */ - uint32_t : 1; - __IOM uint32_t DS1 : 3; /*!< [6..4] Stage 1 drive strength */ - uint32_t : 1; - __IOM uint32_t DS2 : 3; /*!< [10..8] Stage 2 drive strength */ - uint32_t : 1; - __IOM uint32_t DS3 : 3; /*!< [14..12] Stage 3 drive strength */ - uint32_t : 1; - __IOM uint32_t PASSWD : 16; /*!< [31..16] Set to 0x9696 to apply the settings - Any other value in this field will set all drive strengths - to 0 */ - } bit; - } FREQA; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000008) For a detailed description see freqa register */ - - struct { - __IOM uint32_t DS4 : 3; /*!< [2..0] Stage 4 drive strength */ - uint32_t : 1; - __IOM uint32_t DS5 : 3; /*!< [6..4] Stage 5 drive strength */ - uint32_t : 1; - __IOM uint32_t DS6 : 3; /*!< [10..8] Stage 6 drive strength */ - uint32_t : 1; - __IOM uint32_t DS7 : 3; /*!< [14..12] Stage 7 drive strength */ - uint32_t : 1; - __IOM uint32_t PASSWD : 16; /*!< [31..16] Set to 0x9696 to apply the settings - Any other value in this field will set all drive strengths - to 0 */ - } bit; - } FREQB; + 3 bits set quadruples dr */ + __IOM uint32_t FREQB; /*!< (@ 0x00000008) For a detailed description see freqa register */ __IOM uint32_t DORMANT; /*!< (@ 0x0000000C) Ring Oscillator pause control This is used to save power by pausing the ROSC @@ -9357,80 +1491,18 @@ typedef struct { /*!< (@ 0x40060000) ROSC Structu An invalid write will also select WAKE Warning: setup the irq before selecting dormant mode */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000010) Controls the output divider */ - - struct { - __IOM uint32_t DIV : 12; /*!< [11..0] set to 0xaa0 + div where - div = 0 divides by 32 - div = 1-31 divides by div - any other value sets div=0 and therefore divides by 32 - this register resets to div=16 */ - uint32_t : 20; - } bit; - } DIV; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000014) Controls the phase shifted output */ - - struct { - __IOM uint32_t SHIFT : 2; /*!< [1..0] phase shift the phase-shifted output by SHIFT input clocks - this can be changed on-the-fly - must be set to 0 before setting div=1 */ - __IOM uint32_t FLIP : 1; /*!< [2..2] invert the phase-shifted output - this is ignored when div=1 */ - __IOM uint32_t ENABLE : 1; /*!< [3..3] enable the phase-shifted output - this can be changed on-the-fly */ - __IOM uint32_t PASSWD : 8; /*!< [11..4] set to 0xaa0 - any other value enables the output with shift=0 */ - uint32_t : 20; - } bit; - } PHASE; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000018) Ring Oscillator Status */ - - struct { - uint32_t : 12; - __IM uint32_t ENABLED : 1; /*!< [12..12] Oscillator is enabled but not necessarily running and - stable - this resets to 0 but transitions to 1 during chip startup */ - uint32_t : 3; - __IM uint32_t DIV_RUNNING : 1; /*!< [16..16] post-divider is running - this resets to 0 but transitions to 1 during chip startup */ - uint32_t : 7; - __IOM uint32_t BADWRITE : 1; /*!< [24..24] An invalid value has been written to CTRL_ENABLE or - CTRL_FREQ_RANGE or FRFEQA or FREQB or DORMANT */ - uint32_t : 6; - __IM uint32_t STABLE : 1; /*!< [31..31] Oscillator is running and stable */ - } bit; - } STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) This just reads the state of the oscillator output + __IOM uint32_t DIV; /*!< (@ 0x00000010) Controls the output divider */ + __IOM uint32_t PHASE; /*!< (@ 0x00000014) Controls the phase shifted output */ + __IOM uint32_t STATUS; /*!< (@ 0x00000018) Ring Oscillator Status */ + __IOM uint32_t RANDOMBIT; /*!< (@ 0x0000001C) This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency */ - - struct { - __IM uint32_t RANDOMBIT : 1; /*!< [0..0] RANDOMBIT */ - uint32_t : 31; - } bit; - } RANDOMBIT; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000020) A down counter running at the ROSC frequency + __IOM uint32_t COUNT; /*!< (@ 0x00000020) A down counter running at the ROSC frequency which counts to zero and stops. To start the counter write a non-zero value. Can be used for short software pauses when setting up time sensitive hardware. */ - - struct { - __IOM uint32_t COUNT : 8; /*!< [7..0] COUNT */ - uint32_t : 24; - } bit; - } COUNT; } ROSC_Type; /*!< Size = 36 (0x24) */ @@ -9445,83 +1517,9 @@ typedef struct { /*!< (@ 0x40060000) ROSC Structu */ typedef struct { /*!< (@ 0x40064000) VREG_AND_CHIP_RESET Structure */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Voltage regulator control and status */ - - struct { - __IOM uint32_t EN : 1; /*!< [0..0] enable - 0=not enabled, 1=enabled */ - __IOM uint32_t HIZ : 1; /*!< [1..1] high impedance mode select - 0=not in high impedance mode, 1=in high impedance mode */ - uint32_t : 2; - __IOM uint32_t VSEL : 4; /*!< [7..4] output voltage select - 0000 to 0101 - 0.80V - 0110 - 0.85V - 0111 - 0.90V - 1000 - 0.95V - 1001 - 1.00V - 1010 - 1.05V - 1011 - 1.10V (default) - 1100 - 1.15V - 1101 - 1.20V - 1110 - 1.25V - 1111 - 1.30V */ - uint32_t : 4; - __IM uint32_t ROK : 1; /*!< [12..12] regulation status - 0=not in regulation, 1=in regulation */ - uint32_t : 19; - } bit; - } VREG; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000004) brown-out detection control */ - - struct { - __IOM uint32_t EN : 1; /*!< [0..0] enable - 0=not enabled, 1=enabled */ - uint32_t : 3; - __IOM uint32_t VSEL : 4; /*!< [7..4] threshold select - 0000 - 0.473V - 0001 - 0.516V - 0010 - 0.559V - 0011 - 0.602V - 0100 - 0.645V - 0101 - 0.688V - 0110 - 0.731V - 0111 - 0.774V - 1000 - 0.817V - 1001 - 0.860V (default) - 1010 - 0.903V - 1011 - 0.946V - 1100 - 0.989V - 1101 - 1.032V - 1 */ - uint32_t : 24; - } bit; - } BOD; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000008) Chip reset control and status */ - - struct { - uint32_t : 8; - __IM uint32_t HAD_POR : 1; /*!< [8..8] Last reset was from the power-on reset or brown-out detection - blocks */ - uint32_t : 7; - __IM uint32_t HAD_RUN : 1; /*!< [16..16] Last reset was from the RUN pin */ - uint32_t : 3; - __IM uint32_t HAD_PSM_RESTART : 1; /*!< [20..20] Last reset was from the debug port */ - uint32_t : 3; - __IOM uint32_t PSM_RESTART_FLAG : 1; /*!< [24..24] This is set by psm_restart from the debugger. - Its purpose is to branch bootcode to a safe mode when the - debugger has issued a psm_restart in order to recover from - a boot lock-up. - In the safe mode the debugger can repair the boot code, - clear this flag then reboot the processor. */ - uint32_t : 7; - } bit; - } CHIP_RESET; + __IOM uint32_t VREG; /*!< (@ 0x00000000) Voltage regulator control and status */ + __IOM uint32_t BOD; /*!< (@ 0x00000004) brown-out detection control */ + __IOM uint32_t CHIP_RESET; /*!< (@ 0x00000008) Chip reset control and status */ } VREG_AND_CHIP_RESET_Type; /*!< Size = 12 (0xc) */ @@ -9536,16 +1534,7 @@ typedef struct { /*!< (@ 0x40064000) VREG_AND_CHI */ typedef struct { /*!< (@ 0x4006C000) TBMAN Structure */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Indicates the type of platform in use */ - - struct { - __IM uint32_t ASIC : 1; /*!< [0..0] Indicates the platform is an ASIC */ - __IM uint32_t FPGA : 1; /*!< [1..1] Indicates the platform is an FPGA */ - uint32_t : 30; - } bit; - } PLATFORM; + __IOM uint32_t PLATFORM; /*!< (@ 0x00000000) Indicates the type of platform in use */ } TBMAN_Type; /*!< Size = 4 (0x4) */ @@ -9582,123 +1571,28 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur transfer completes. Writing this register sets the RELOAD value - for the tran */ - - union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) DMA Channel 0 Control and Status */ - - struct { - __IOM uint32_t EN : 1; /*!< [0..0] DMA Channel Enable. - When 1, the channel will respond to triggering events, - which will cause it to become BUSY and start transferring - data. When 0, the channel will ignore triggers, stop issuing - transfers, and pause the current transfer sequence (i.e. - BUSY will remain high if already high) */ - __IOM uint32_t HIGH_PRIORITY : 1; /*!< [1..1] HIGH_PRIORITY gives a channel preferential treatment - in issue scheduling: in each scheduling round, all high - priority channels are considered first, and then only a - single low priority channel, before returning to the high - priority channels. - - This only affects the order in which the DMA schedules - channels. The DMA's bus priority is not changed. If the - DMA is not saturated then a low priority channel will see - no loss of throughput. */ - __IOM uint32_t DATA_SIZE : 2; /*!< [3..2] Set the size of each bus transfer (byte/halfword/word). - READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 - bytes) with each transfer. */ - __IOM uint32_t INCR_READ : 1; /*!< [4..4] If 1, the read address increments with each transfer. - If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory - transfers. */ - __IOM uint32_t INCR_WRITE : 1; /*!< [5..5] If 1, the write address increments with each transfer. - If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral - transfers. */ - __IOM uint32_t RING_SIZE : 4; /*!< [9..6] Size of address wrap region. If 0, don't wrap. For values - n > 0, only the lower n bits of the address will change. - This wraps the address on a (1 << n) byte boundary, facilitating - access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This - can apply to either read or write addresses, based on value - of RING_SEL. */ - __IOM uint32_t RING_SEL : 1; /*!< [10..10] Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) - boundary. If 1, write addresses are wrapped. */ - __IOM uint32_t CHAIN_TO : 4; /*!< [14..11] When this channel completes, it will trigger the channel - indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this - channel)_. - Reset value is equal to channel number (0). */ - __IOM uint32_t TREQ_SEL : 6; /*!< [20..15] Select a Transfer Request signal. - The channel uses the transfer request signal to pace its - data transfer rate. Sources for TREQ signals are internal - (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ */ - __IOM uint32_t IRQ_QUIET : 1; /*!< [21..21] In QUIET mode, the channel does not generate IRQs at - the end of every transfer block. Instead, an IRQ is raised - when NULL is written to a trigger register, indicating - the end of a control block chain. - - This reduces the number of interrupts to be serviced by - the CPU when transferring a DMA chain of many small control - blocks. */ - __IOM uint32_t BSWAP : 1; /*!< [22..22] Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the - two bytes of each halfword are swapped. For word data, - the four bytes of each word are swapped to reverse order. */ - __IOM uint32_t SNIFF_EN : 1; /*!< [23..23] If 1, this channel's data transfers are visible to - the sniff hardware, and each transfer will advance the - state of the checksum. This only applies if the sniff hardware - is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- - block basis. */ - __IM uint32_t BUSY : 1; /*!< [24..24] This flag goes high when the channel starts a new transfer - sequence, and low when the last transfer of that sequence - completes. Clearing EN while BUSY is high pauses the channel, - and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), - see CHAN_ABORT. */ - uint32_t : 4; - __IOM uint32_t WRITE_ERROR : 1; /*!< [29..29] If 1, the channel received a write bus error. Write - one to clear. - WRITE_ADDR shows the approximate address where the bus - error was encountered (will not to be earlier, or more - than 5 transfers later) */ - __IOM uint32_t READ_ERROR : 1; /*!< [30..30] If 1, the channel received a read bus error. Write - one to clear. - READ_ADDR shows the approximate address where the bus error - was encountered (will not to be earlier, or more than 3 - transfers later) */ - __IM uint32_t AHB_ERROR : 1; /*!< [31..31] Logical OR of the READ_ERROR and WRITE_ERROR flags. - The channel halts when it encounters any bus error, and - always raises its channel IRQ flag. */ - } bit; - } CH0_CTRL_TRIG; - __IM uint32_t CH0_AL1_CTRL; /*!< (@ 0x00000010) Alias for channel 0 CTRL register */ - __IM uint32_t CH0_AL1_READ_ADDR; /*!< (@ 0x00000014) Alias for channel 0 READ_ADDR register */ - __IM uint32_t CH0_AL1_WRITE_ADDR; /*!< (@ 0x00000018) Alias for channel 0 WRITE_ADDR register */ - __IM uint32_t CH0_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000001C) Alias for channel 0 TRANS_COUNT register + for the transf */ + __IOM uint32_t CH0_CTRL_TRIG; /*!< (@ 0x0000000C) DMA Channel 0 Control and Status */ + __IOM uint32_t CH0_AL1_CTRL; /*!< (@ 0x00000010) Alias for channel 0 CTRL register */ + __IOM uint32_t CH0_AL1_READ_ADDR; /*!< (@ 0x00000014) Alias for channel 0 READ_ADDR register */ + __IOM uint32_t CH0_AL1_WRITE_ADDR; /*!< (@ 0x00000018) Alias for channel 0 WRITE_ADDR register */ + __IOM uint32_t CH0_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000001C) Alias for channel 0 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH0_AL2_CTRL; /*!< (@ 0x00000020) Alias for channel 0 CTRL register */ - __IM uint32_t CH0_AL2_TRANS_COUNT; /*!< (@ 0x00000024) Alias for channel 0 TRANS_COUNT register */ - __IM uint32_t CH0_AL2_READ_ADDR; /*!< (@ 0x00000028) Alias for channel 0 READ_ADDR register */ - __IM uint32_t CH0_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000002C) Alias for channel 0 WRITE_ADDR register + __IOM uint32_t CH0_AL2_CTRL; /*!< (@ 0x00000020) Alias for channel 0 CTRL register */ + __IOM uint32_t CH0_AL2_TRANS_COUNT; /*!< (@ 0x00000024) Alias for channel 0 TRANS_COUNT register */ + __IOM uint32_t CH0_AL2_READ_ADDR; /*!< (@ 0x00000028) Alias for channel 0 READ_ADDR register */ + __IOM uint32_t CH0_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000002C) Alias for channel 0 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH0_AL3_CTRL; /*!< (@ 0x00000030) Alias for channel 0 CTRL register */ - __IM uint32_t CH0_AL3_WRITE_ADDR; /*!< (@ 0x00000034) Alias for channel 0 WRITE_ADDR register */ - __IM uint32_t CH0_AL3_TRANS_COUNT; /*!< (@ 0x00000038) Alias for channel 0 TRANS_COUNT register */ - __IM uint32_t CH0_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000003C) Alias for channel 0 READ_ADDR register + __IOM uint32_t CH0_AL3_CTRL; /*!< (@ 0x00000030) Alias for channel 0 CTRL register */ + __IOM uint32_t CH0_AL3_WRITE_ADDR; /*!< (@ 0x00000034) Alias for channel 0 WRITE_ADDR register */ + __IOM uint32_t CH0_AL3_TRANS_COUNT; /*!< (@ 0x00000038) Alias for channel 0 TRANS_COUNT register */ + __IOM uint32_t CH0_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000003C) Alias for channel 0 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the @@ -9725,123 +1619,28 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur transfer completes. Writing this register sets the RELOAD value - for the tran */ - - union { - __IOM uint32_t reg; /*!< (@ 0x0000004C) DMA Channel 1 Control and Status */ - - struct { - __IOM uint32_t EN : 1; /*!< [0..0] DMA Channel Enable. - When 1, the channel will respond to triggering events, - which will cause it to become BUSY and start transferring - data. When 0, the channel will ignore triggers, stop issuing - transfers, and pause the current transfer sequence (i.e. - BUSY will remain high if already high) */ - __IOM uint32_t HIGH_PRIORITY : 1; /*!< [1..1] HIGH_PRIORITY gives a channel preferential treatment - in issue scheduling: in each scheduling round, all high - priority channels are considered first, and then only a - single low priority channel, before returning to the high - priority channels. - - This only affects the order in which the DMA schedules - channels. The DMA's bus priority is not changed. If the - DMA is not saturated then a low priority channel will see - no loss of throughput. */ - __IOM uint32_t DATA_SIZE : 2; /*!< [3..2] Set the size of each bus transfer (byte/halfword/word). - READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 - bytes) with each transfer. */ - __IOM uint32_t INCR_READ : 1; /*!< [4..4] If 1, the read address increments with each transfer. - If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory - transfers. */ - __IOM uint32_t INCR_WRITE : 1; /*!< [5..5] If 1, the write address increments with each transfer. - If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral - transfers. */ - __IOM uint32_t RING_SIZE : 4; /*!< [9..6] Size of address wrap region. If 0, don't wrap. For values - n > 0, only the lower n bits of the address will change. - This wraps the address on a (1 << n) byte boundary, facilitating - access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This - can apply to either read or write addresses, based on value - of RING_SEL. */ - __IOM uint32_t RING_SEL : 1; /*!< [10..10] Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) - boundary. If 1, write addresses are wrapped. */ - __IOM uint32_t CHAIN_TO : 4; /*!< [14..11] When this channel completes, it will trigger the channel - indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this - channel)_. - Reset value is equal to channel number (1). */ - __IOM uint32_t TREQ_SEL : 6; /*!< [20..15] Select a Transfer Request signal. - The channel uses the transfer request signal to pace its - data transfer rate. Sources for TREQ signals are internal - (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ */ - __IOM uint32_t IRQ_QUIET : 1; /*!< [21..21] In QUIET mode, the channel does not generate IRQs at - the end of every transfer block. Instead, an IRQ is raised - when NULL is written to a trigger register, indicating - the end of a control block chain. - - This reduces the number of interrupts to be serviced by - the CPU when transferring a DMA chain of many small control - blocks. */ - __IOM uint32_t BSWAP : 1; /*!< [22..22] Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the - two bytes of each halfword are swapped. For word data, - the four bytes of each word are swapped to reverse order. */ - __IOM uint32_t SNIFF_EN : 1; /*!< [23..23] If 1, this channel's data transfers are visible to - the sniff hardware, and each transfer will advance the - state of the checksum. This only applies if the sniff hardware - is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- - block basis. */ - __IM uint32_t BUSY : 1; /*!< [24..24] This flag goes high when the channel starts a new transfer - sequence, and low when the last transfer of that sequence - completes. Clearing EN while BUSY is high pauses the channel, - and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), - see CHAN_ABORT. */ - uint32_t : 4; - __IOM uint32_t WRITE_ERROR : 1; /*!< [29..29] If 1, the channel received a write bus error. Write - one to clear. - WRITE_ADDR shows the approximate address where the bus - error was encountered (will not to be earlier, or more - than 5 transfers later) */ - __IOM uint32_t READ_ERROR : 1; /*!< [30..30] If 1, the channel received a read bus error. Write - one to clear. - READ_ADDR shows the approximate address where the bus error - was encountered (will not to be earlier, or more than 3 - transfers later) */ - __IM uint32_t AHB_ERROR : 1; /*!< [31..31] Logical OR of the READ_ERROR and WRITE_ERROR flags. - The channel halts when it encounters any bus error, and - always raises its channel IRQ flag. */ - } bit; - } CH1_CTRL_TRIG; - __IM uint32_t CH1_AL1_CTRL; /*!< (@ 0x00000050) Alias for channel 1 CTRL register */ - __IM uint32_t CH1_AL1_READ_ADDR; /*!< (@ 0x00000054) Alias for channel 1 READ_ADDR register */ - __IM uint32_t CH1_AL1_WRITE_ADDR; /*!< (@ 0x00000058) Alias for channel 1 WRITE_ADDR register */ - __IM uint32_t CH1_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000005C) Alias for channel 1 TRANS_COUNT register + for the transf */ + __IOM uint32_t CH1_CTRL_TRIG; /*!< (@ 0x0000004C) DMA Channel 1 Control and Status */ + __IOM uint32_t CH1_AL1_CTRL; /*!< (@ 0x00000050) Alias for channel 1 CTRL register */ + __IOM uint32_t CH1_AL1_READ_ADDR; /*!< (@ 0x00000054) Alias for channel 1 READ_ADDR register */ + __IOM uint32_t CH1_AL1_WRITE_ADDR; /*!< (@ 0x00000058) Alias for channel 1 WRITE_ADDR register */ + __IOM uint32_t CH1_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000005C) Alias for channel 1 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH1_AL2_CTRL; /*!< (@ 0x00000060) Alias for channel 1 CTRL register */ - __IM uint32_t CH1_AL2_TRANS_COUNT; /*!< (@ 0x00000064) Alias for channel 1 TRANS_COUNT register */ - __IM uint32_t CH1_AL2_READ_ADDR; /*!< (@ 0x00000068) Alias for channel 1 READ_ADDR register */ - __IM uint32_t CH1_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000006C) Alias for channel 1 WRITE_ADDR register + __IOM uint32_t CH1_AL2_CTRL; /*!< (@ 0x00000060) Alias for channel 1 CTRL register */ + __IOM uint32_t CH1_AL2_TRANS_COUNT; /*!< (@ 0x00000064) Alias for channel 1 TRANS_COUNT register */ + __IOM uint32_t CH1_AL2_READ_ADDR; /*!< (@ 0x00000068) Alias for channel 1 READ_ADDR register */ + __IOM uint32_t CH1_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000006C) Alias for channel 1 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH1_AL3_CTRL; /*!< (@ 0x00000070) Alias for channel 1 CTRL register */ - __IM uint32_t CH1_AL3_WRITE_ADDR; /*!< (@ 0x00000074) Alias for channel 1 WRITE_ADDR register */ - __IM uint32_t CH1_AL3_TRANS_COUNT; /*!< (@ 0x00000078) Alias for channel 1 TRANS_COUNT register */ - __IM uint32_t CH1_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000007C) Alias for channel 1 READ_ADDR register + __IOM uint32_t CH1_AL3_CTRL; /*!< (@ 0x00000070) Alias for channel 1 CTRL register */ + __IOM uint32_t CH1_AL3_WRITE_ADDR; /*!< (@ 0x00000074) Alias for channel 1 WRITE_ADDR register */ + __IOM uint32_t CH1_AL3_TRANS_COUNT; /*!< (@ 0x00000078) Alias for channel 1 TRANS_COUNT register */ + __IOM uint32_t CH1_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000007C) Alias for channel 1 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the @@ -9868,123 +1667,28 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur transfer completes. Writing this register sets the RELOAD value - for the tran */ - - union { - __IOM uint32_t reg; /*!< (@ 0x0000008C) DMA Channel 2 Control and Status */ - - struct { - __IOM uint32_t EN : 1; /*!< [0..0] DMA Channel Enable. - When 1, the channel will respond to triggering events, - which will cause it to become BUSY and start transferring - data. When 0, the channel will ignore triggers, stop issuing - transfers, and pause the current transfer sequence (i.e. - BUSY will remain high if already high) */ - __IOM uint32_t HIGH_PRIORITY : 1; /*!< [1..1] HIGH_PRIORITY gives a channel preferential treatment - in issue scheduling: in each scheduling round, all high - priority channels are considered first, and then only a - single low priority channel, before returning to the high - priority channels. - - This only affects the order in which the DMA schedules - channels. The DMA's bus priority is not changed. If the - DMA is not saturated then a low priority channel will see - no loss of throughput. */ - __IOM uint32_t DATA_SIZE : 2; /*!< [3..2] Set the size of each bus transfer (byte/halfword/word). - READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 - bytes) with each transfer. */ - __IOM uint32_t INCR_READ : 1; /*!< [4..4] If 1, the read address increments with each transfer. - If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory - transfers. */ - __IOM uint32_t INCR_WRITE : 1; /*!< [5..5] If 1, the write address increments with each transfer. - If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral - transfers. */ - __IOM uint32_t RING_SIZE : 4; /*!< [9..6] Size of address wrap region. If 0, don't wrap. For values - n > 0, only the lower n bits of the address will change. - This wraps the address on a (1 << n) byte boundary, facilitating - access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This - can apply to either read or write addresses, based on value - of RING_SEL. */ - __IOM uint32_t RING_SEL : 1; /*!< [10..10] Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) - boundary. If 1, write addresses are wrapped. */ - __IOM uint32_t CHAIN_TO : 4; /*!< [14..11] When this channel completes, it will trigger the channel - indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this - channel)_. - Reset value is equal to channel number (2). */ - __IOM uint32_t TREQ_SEL : 6; /*!< [20..15] Select a Transfer Request signal. - The channel uses the transfer request signal to pace its - data transfer rate. Sources for TREQ signals are internal - (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ */ - __IOM uint32_t IRQ_QUIET : 1; /*!< [21..21] In QUIET mode, the channel does not generate IRQs at - the end of every transfer block. Instead, an IRQ is raised - when NULL is written to a trigger register, indicating - the end of a control block chain. - - This reduces the number of interrupts to be serviced by - the CPU when transferring a DMA chain of many small control - blocks. */ - __IOM uint32_t BSWAP : 1; /*!< [22..22] Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the - two bytes of each halfword are swapped. For word data, - the four bytes of each word are swapped to reverse order. */ - __IOM uint32_t SNIFF_EN : 1; /*!< [23..23] If 1, this channel's data transfers are visible to - the sniff hardware, and each transfer will advance the - state of the checksum. This only applies if the sniff hardware - is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- - block basis. */ - __IM uint32_t BUSY : 1; /*!< [24..24] This flag goes high when the channel starts a new transfer - sequence, and low when the last transfer of that sequence - completes. Clearing EN while BUSY is high pauses the channel, - and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), - see CHAN_ABORT. */ - uint32_t : 4; - __IOM uint32_t WRITE_ERROR : 1; /*!< [29..29] If 1, the channel received a write bus error. Write - one to clear. - WRITE_ADDR shows the approximate address where the bus - error was encountered (will not to be earlier, or more - than 5 transfers later) */ - __IOM uint32_t READ_ERROR : 1; /*!< [30..30] If 1, the channel received a read bus error. Write - one to clear. - READ_ADDR shows the approximate address where the bus error - was encountered (will not to be earlier, or more than 3 - transfers later) */ - __IM uint32_t AHB_ERROR : 1; /*!< [31..31] Logical OR of the READ_ERROR and WRITE_ERROR flags. - The channel halts when it encounters any bus error, and - always raises its channel IRQ flag. */ - } bit; - } CH2_CTRL_TRIG; - __IM uint32_t CH2_AL1_CTRL; /*!< (@ 0x00000090) Alias for channel 2 CTRL register */ - __IM uint32_t CH2_AL1_READ_ADDR; /*!< (@ 0x00000094) Alias for channel 2 READ_ADDR register */ - __IM uint32_t CH2_AL1_WRITE_ADDR; /*!< (@ 0x00000098) Alias for channel 2 WRITE_ADDR register */ - __IM uint32_t CH2_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000009C) Alias for channel 2 TRANS_COUNT register + for the transf */ + __IOM uint32_t CH2_CTRL_TRIG; /*!< (@ 0x0000008C) DMA Channel 2 Control and Status */ + __IOM uint32_t CH2_AL1_CTRL; /*!< (@ 0x00000090) Alias for channel 2 CTRL register */ + __IOM uint32_t CH2_AL1_READ_ADDR; /*!< (@ 0x00000094) Alias for channel 2 READ_ADDR register */ + __IOM uint32_t CH2_AL1_WRITE_ADDR; /*!< (@ 0x00000098) Alias for channel 2 WRITE_ADDR register */ + __IOM uint32_t CH2_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000009C) Alias for channel 2 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH2_AL2_CTRL; /*!< (@ 0x000000A0) Alias for channel 2 CTRL register */ - __IM uint32_t CH2_AL2_TRANS_COUNT; /*!< (@ 0x000000A4) Alias for channel 2 TRANS_COUNT register */ - __IM uint32_t CH2_AL2_READ_ADDR; /*!< (@ 0x000000A8) Alias for channel 2 READ_ADDR register */ - __IM uint32_t CH2_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000000AC) Alias for channel 2 WRITE_ADDR register + __IOM uint32_t CH2_AL2_CTRL; /*!< (@ 0x000000A0) Alias for channel 2 CTRL register */ + __IOM uint32_t CH2_AL2_TRANS_COUNT; /*!< (@ 0x000000A4) Alias for channel 2 TRANS_COUNT register */ + __IOM uint32_t CH2_AL2_READ_ADDR; /*!< (@ 0x000000A8) Alias for channel 2 READ_ADDR register */ + __IOM uint32_t CH2_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000000AC) Alias for channel 2 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH2_AL3_CTRL; /*!< (@ 0x000000B0) Alias for channel 2 CTRL register */ - __IM uint32_t CH2_AL3_WRITE_ADDR; /*!< (@ 0x000000B4) Alias for channel 2 WRITE_ADDR register */ - __IM uint32_t CH2_AL3_TRANS_COUNT; /*!< (@ 0x000000B8) Alias for channel 2 TRANS_COUNT register */ - __IM uint32_t CH2_AL3_READ_ADDR_TRIG; /*!< (@ 0x000000BC) Alias for channel 2 READ_ADDR register + __IOM uint32_t CH2_AL3_CTRL; /*!< (@ 0x000000B0) Alias for channel 2 CTRL register */ + __IOM uint32_t CH2_AL3_WRITE_ADDR; /*!< (@ 0x000000B4) Alias for channel 2 WRITE_ADDR register */ + __IOM uint32_t CH2_AL3_TRANS_COUNT; /*!< (@ 0x000000B8) Alias for channel 2 TRANS_COUNT register */ + __IOM uint32_t CH2_AL3_READ_ADDR_TRIG; /*!< (@ 0x000000BC) Alias for channel 2 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the @@ -10011,123 +1715,28 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur transfer completes. Writing this register sets the RELOAD value - for the tran */ - - union { - __IOM uint32_t reg; /*!< (@ 0x000000CC) DMA Channel 3 Control and Status */ - - struct { - __IOM uint32_t EN : 1; /*!< [0..0] DMA Channel Enable. - When 1, the channel will respond to triggering events, - which will cause it to become BUSY and start transferring - data. When 0, the channel will ignore triggers, stop issuing - transfers, and pause the current transfer sequence (i.e. - BUSY will remain high if already high) */ - __IOM uint32_t HIGH_PRIORITY : 1; /*!< [1..1] HIGH_PRIORITY gives a channel preferential treatment - in issue scheduling: in each scheduling round, all high - priority channels are considered first, and then only a - single low priority channel, before returning to the high - priority channels. - - This only affects the order in which the DMA schedules - channels. The DMA's bus priority is not changed. If the - DMA is not saturated then a low priority channel will see - no loss of throughput. */ - __IOM uint32_t DATA_SIZE : 2; /*!< [3..2] Set the size of each bus transfer (byte/halfword/word). - READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 - bytes) with each transfer. */ - __IOM uint32_t INCR_READ : 1; /*!< [4..4] If 1, the read address increments with each transfer. - If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory - transfers. */ - __IOM uint32_t INCR_WRITE : 1; /*!< [5..5] If 1, the write address increments with each transfer. - If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral - transfers. */ - __IOM uint32_t RING_SIZE : 4; /*!< [9..6] Size of address wrap region. If 0, don't wrap. For values - n > 0, only the lower n bits of the address will change. - This wraps the address on a (1 << n) byte boundary, facilitating - access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This - can apply to either read or write addresses, based on value - of RING_SEL. */ - __IOM uint32_t RING_SEL : 1; /*!< [10..10] Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) - boundary. If 1, write addresses are wrapped. */ - __IOM uint32_t CHAIN_TO : 4; /*!< [14..11] When this channel completes, it will trigger the channel - indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this - channel)_. - Reset value is equal to channel number (3). */ - __IOM uint32_t TREQ_SEL : 6; /*!< [20..15] Select a Transfer Request signal. - The channel uses the transfer request signal to pace its - data transfer rate. Sources for TREQ signals are internal - (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ */ - __IOM uint32_t IRQ_QUIET : 1; /*!< [21..21] In QUIET mode, the channel does not generate IRQs at - the end of every transfer block. Instead, an IRQ is raised - when NULL is written to a trigger register, indicating - the end of a control block chain. - - This reduces the number of interrupts to be serviced by - the CPU when transferring a DMA chain of many small control - blocks. */ - __IOM uint32_t BSWAP : 1; /*!< [22..22] Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the - two bytes of each halfword are swapped. For word data, - the four bytes of each word are swapped to reverse order. */ - __IOM uint32_t SNIFF_EN : 1; /*!< [23..23] If 1, this channel's data transfers are visible to - the sniff hardware, and each transfer will advance the - state of the checksum. This only applies if the sniff hardware - is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- - block basis. */ - __IM uint32_t BUSY : 1; /*!< [24..24] This flag goes high when the channel starts a new transfer - sequence, and low when the last transfer of that sequence - completes. Clearing EN while BUSY is high pauses the channel, - and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), - see CHAN_ABORT. */ - uint32_t : 4; - __IOM uint32_t WRITE_ERROR : 1; /*!< [29..29] If 1, the channel received a write bus error. Write - one to clear. - WRITE_ADDR shows the approximate address where the bus - error was encountered (will not to be earlier, or more - than 5 transfers later) */ - __IOM uint32_t READ_ERROR : 1; /*!< [30..30] If 1, the channel received a read bus error. Write - one to clear. - READ_ADDR shows the approximate address where the bus error - was encountered (will not to be earlier, or more than 3 - transfers later) */ - __IM uint32_t AHB_ERROR : 1; /*!< [31..31] Logical OR of the READ_ERROR and WRITE_ERROR flags. - The channel halts when it encounters any bus error, and - always raises its channel IRQ flag. */ - } bit; - } CH3_CTRL_TRIG; - __IM uint32_t CH3_AL1_CTRL; /*!< (@ 0x000000D0) Alias for channel 3 CTRL register */ - __IM uint32_t CH3_AL1_READ_ADDR; /*!< (@ 0x000000D4) Alias for channel 3 READ_ADDR register */ - __IM uint32_t CH3_AL1_WRITE_ADDR; /*!< (@ 0x000000D8) Alias for channel 3 WRITE_ADDR register */ - __IM uint32_t CH3_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x000000DC) Alias for channel 3 TRANS_COUNT register + for the transf */ + __IOM uint32_t CH3_CTRL_TRIG; /*!< (@ 0x000000CC) DMA Channel 3 Control and Status */ + __IOM uint32_t CH3_AL1_CTRL; /*!< (@ 0x000000D0) Alias for channel 3 CTRL register */ + __IOM uint32_t CH3_AL1_READ_ADDR; /*!< (@ 0x000000D4) Alias for channel 3 READ_ADDR register */ + __IOM uint32_t CH3_AL1_WRITE_ADDR; /*!< (@ 0x000000D8) Alias for channel 3 WRITE_ADDR register */ + __IOM uint32_t CH3_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x000000DC) Alias for channel 3 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH3_AL2_CTRL; /*!< (@ 0x000000E0) Alias for channel 3 CTRL register */ - __IM uint32_t CH3_AL2_TRANS_COUNT; /*!< (@ 0x000000E4) Alias for channel 3 TRANS_COUNT register */ - __IM uint32_t CH3_AL2_READ_ADDR; /*!< (@ 0x000000E8) Alias for channel 3 READ_ADDR register */ - __IM uint32_t CH3_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000000EC) Alias for channel 3 WRITE_ADDR register + __IOM uint32_t CH3_AL2_CTRL; /*!< (@ 0x000000E0) Alias for channel 3 CTRL register */ + __IOM uint32_t CH3_AL2_TRANS_COUNT; /*!< (@ 0x000000E4) Alias for channel 3 TRANS_COUNT register */ + __IOM uint32_t CH3_AL2_READ_ADDR; /*!< (@ 0x000000E8) Alias for channel 3 READ_ADDR register */ + __IOM uint32_t CH3_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000000EC) Alias for channel 3 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH3_AL3_CTRL; /*!< (@ 0x000000F0) Alias for channel 3 CTRL register */ - __IM uint32_t CH3_AL3_WRITE_ADDR; /*!< (@ 0x000000F4) Alias for channel 3 WRITE_ADDR register */ - __IM uint32_t CH3_AL3_TRANS_COUNT; /*!< (@ 0x000000F8) Alias for channel 3 TRANS_COUNT register */ - __IM uint32_t CH3_AL3_READ_ADDR_TRIG; /*!< (@ 0x000000FC) Alias for channel 3 READ_ADDR register + __IOM uint32_t CH3_AL3_CTRL; /*!< (@ 0x000000F0) Alias for channel 3 CTRL register */ + __IOM uint32_t CH3_AL3_WRITE_ADDR; /*!< (@ 0x000000F4) Alias for channel 3 WRITE_ADDR register */ + __IOM uint32_t CH3_AL3_TRANS_COUNT; /*!< (@ 0x000000F8) Alias for channel 3 TRANS_COUNT register */ + __IOM uint32_t CH3_AL3_READ_ADDR_TRIG; /*!< (@ 0x000000FC) Alias for channel 3 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the @@ -10154,123 +1763,28 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur transfer completes. Writing this register sets the RELOAD value - for the tran */ - - union { - __IOM uint32_t reg; /*!< (@ 0x0000010C) DMA Channel 4 Control and Status */ - - struct { - __IOM uint32_t EN : 1; /*!< [0..0] DMA Channel Enable. - When 1, the channel will respond to triggering events, - which will cause it to become BUSY and start transferring - data. When 0, the channel will ignore triggers, stop issuing - transfers, and pause the current transfer sequence (i.e. - BUSY will remain high if already high) */ - __IOM uint32_t HIGH_PRIORITY : 1; /*!< [1..1] HIGH_PRIORITY gives a channel preferential treatment - in issue scheduling: in each scheduling round, all high - priority channels are considered first, and then only a - single low priority channel, before returning to the high - priority channels. - - This only affects the order in which the DMA schedules - channels. The DMA's bus priority is not changed. If the - DMA is not saturated then a low priority channel will see - no loss of throughput. */ - __IOM uint32_t DATA_SIZE : 2; /*!< [3..2] Set the size of each bus transfer (byte/halfword/word). - READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 - bytes) with each transfer. */ - __IOM uint32_t INCR_READ : 1; /*!< [4..4] If 1, the read address increments with each transfer. - If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory - transfers. */ - __IOM uint32_t INCR_WRITE : 1; /*!< [5..5] If 1, the write address increments with each transfer. - If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral - transfers. */ - __IOM uint32_t RING_SIZE : 4; /*!< [9..6] Size of address wrap region. If 0, don't wrap. For values - n > 0, only the lower n bits of the address will change. - This wraps the address on a (1 << n) byte boundary, facilitating - access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This - can apply to either read or write addresses, based on value - of RING_SEL. */ - __IOM uint32_t RING_SEL : 1; /*!< [10..10] Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) - boundary. If 1, write addresses are wrapped. */ - __IOM uint32_t CHAIN_TO : 4; /*!< [14..11] When this channel completes, it will trigger the channel - indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this - channel)_. - Reset value is equal to channel number (4). */ - __IOM uint32_t TREQ_SEL : 6; /*!< [20..15] Select a Transfer Request signal. - The channel uses the transfer request signal to pace its - data transfer rate. Sources for TREQ signals are internal - (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ */ - __IOM uint32_t IRQ_QUIET : 1; /*!< [21..21] In QUIET mode, the channel does not generate IRQs at - the end of every transfer block. Instead, an IRQ is raised - when NULL is written to a trigger register, indicating - the end of a control block chain. - - This reduces the number of interrupts to be serviced by - the CPU when transferring a DMA chain of many small control - blocks. */ - __IOM uint32_t BSWAP : 1; /*!< [22..22] Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the - two bytes of each halfword are swapped. For word data, - the four bytes of each word are swapped to reverse order. */ - __IOM uint32_t SNIFF_EN : 1; /*!< [23..23] If 1, this channel's data transfers are visible to - the sniff hardware, and each transfer will advance the - state of the checksum. This only applies if the sniff hardware - is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- - block basis. */ - __IM uint32_t BUSY : 1; /*!< [24..24] This flag goes high when the channel starts a new transfer - sequence, and low when the last transfer of that sequence - completes. Clearing EN while BUSY is high pauses the channel, - and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), - see CHAN_ABORT. */ - uint32_t : 4; - __IOM uint32_t WRITE_ERROR : 1; /*!< [29..29] If 1, the channel received a write bus error. Write - one to clear. - WRITE_ADDR shows the approximate address where the bus - error was encountered (will not to be earlier, or more - than 5 transfers later) */ - __IOM uint32_t READ_ERROR : 1; /*!< [30..30] If 1, the channel received a read bus error. Write - one to clear. - READ_ADDR shows the approximate address where the bus error - was encountered (will not to be earlier, or more than 3 - transfers later) */ - __IM uint32_t AHB_ERROR : 1; /*!< [31..31] Logical OR of the READ_ERROR and WRITE_ERROR flags. - The channel halts when it encounters any bus error, and - always raises its channel IRQ flag. */ - } bit; - } CH4_CTRL_TRIG; - __IM uint32_t CH4_AL1_CTRL; /*!< (@ 0x00000110) Alias for channel 4 CTRL register */ - __IM uint32_t CH4_AL1_READ_ADDR; /*!< (@ 0x00000114) Alias for channel 4 READ_ADDR register */ - __IM uint32_t CH4_AL1_WRITE_ADDR; /*!< (@ 0x00000118) Alias for channel 4 WRITE_ADDR register */ - __IM uint32_t CH4_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000011C) Alias for channel 4 TRANS_COUNT register + for the transf */ + __IOM uint32_t CH4_CTRL_TRIG; /*!< (@ 0x0000010C) DMA Channel 4 Control and Status */ + __IOM uint32_t CH4_AL1_CTRL; /*!< (@ 0x00000110) Alias for channel 4 CTRL register */ + __IOM uint32_t CH4_AL1_READ_ADDR; /*!< (@ 0x00000114) Alias for channel 4 READ_ADDR register */ + __IOM uint32_t CH4_AL1_WRITE_ADDR; /*!< (@ 0x00000118) Alias for channel 4 WRITE_ADDR register */ + __IOM uint32_t CH4_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000011C) Alias for channel 4 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH4_AL2_CTRL; /*!< (@ 0x00000120) Alias for channel 4 CTRL register */ - __IM uint32_t CH4_AL2_TRANS_COUNT; /*!< (@ 0x00000124) Alias for channel 4 TRANS_COUNT register */ - __IM uint32_t CH4_AL2_READ_ADDR; /*!< (@ 0x00000128) Alias for channel 4 READ_ADDR register */ - __IM uint32_t CH4_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000012C) Alias for channel 4 WRITE_ADDR register + __IOM uint32_t CH4_AL2_CTRL; /*!< (@ 0x00000120) Alias for channel 4 CTRL register */ + __IOM uint32_t CH4_AL2_TRANS_COUNT; /*!< (@ 0x00000124) Alias for channel 4 TRANS_COUNT register */ + __IOM uint32_t CH4_AL2_READ_ADDR; /*!< (@ 0x00000128) Alias for channel 4 READ_ADDR register */ + __IOM uint32_t CH4_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000012C) Alias for channel 4 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH4_AL3_CTRL; /*!< (@ 0x00000130) Alias for channel 4 CTRL register */ - __IM uint32_t CH4_AL3_WRITE_ADDR; /*!< (@ 0x00000134) Alias for channel 4 WRITE_ADDR register */ - __IM uint32_t CH4_AL3_TRANS_COUNT; /*!< (@ 0x00000138) Alias for channel 4 TRANS_COUNT register */ - __IM uint32_t CH4_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000013C) Alias for channel 4 READ_ADDR register + __IOM uint32_t CH4_AL3_CTRL; /*!< (@ 0x00000130) Alias for channel 4 CTRL register */ + __IOM uint32_t CH4_AL3_WRITE_ADDR; /*!< (@ 0x00000134) Alias for channel 4 WRITE_ADDR register */ + __IOM uint32_t CH4_AL3_TRANS_COUNT; /*!< (@ 0x00000138) Alias for channel 4 TRANS_COUNT register */ + __IOM uint32_t CH4_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000013C) Alias for channel 4 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the @@ -10297,123 +1811,28 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur transfer completes. Writing this register sets the RELOAD value - for the tran */ - - union { - __IOM uint32_t reg; /*!< (@ 0x0000014C) DMA Channel 5 Control and Status */ - - struct { - __IOM uint32_t EN : 1; /*!< [0..0] DMA Channel Enable. - When 1, the channel will respond to triggering events, - which will cause it to become BUSY and start transferring - data. When 0, the channel will ignore triggers, stop issuing - transfers, and pause the current transfer sequence (i.e. - BUSY will remain high if already high) */ - __IOM uint32_t HIGH_PRIORITY : 1; /*!< [1..1] HIGH_PRIORITY gives a channel preferential treatment - in issue scheduling: in each scheduling round, all high - priority channels are considered first, and then only a - single low priority channel, before returning to the high - priority channels. - - This only affects the order in which the DMA schedules - channels. The DMA's bus priority is not changed. If the - DMA is not saturated then a low priority channel will see - no loss of throughput. */ - __IOM uint32_t DATA_SIZE : 2; /*!< [3..2] Set the size of each bus transfer (byte/halfword/word). - READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 - bytes) with each transfer. */ - __IOM uint32_t INCR_READ : 1; /*!< [4..4] If 1, the read address increments with each transfer. - If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory - transfers. */ - __IOM uint32_t INCR_WRITE : 1; /*!< [5..5] If 1, the write address increments with each transfer. - If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral - transfers. */ - __IOM uint32_t RING_SIZE : 4; /*!< [9..6] Size of address wrap region. If 0, don't wrap. For values - n > 0, only the lower n bits of the address will change. - This wraps the address on a (1 << n) byte boundary, facilitating - access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This - can apply to either read or write addresses, based on value - of RING_SEL. */ - __IOM uint32_t RING_SEL : 1; /*!< [10..10] Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) - boundary. If 1, write addresses are wrapped. */ - __IOM uint32_t CHAIN_TO : 4; /*!< [14..11] When this channel completes, it will trigger the channel - indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this - channel)_. - Reset value is equal to channel number (5). */ - __IOM uint32_t TREQ_SEL : 6; /*!< [20..15] Select a Transfer Request signal. - The channel uses the transfer request signal to pace its - data transfer rate. Sources for TREQ signals are internal - (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ */ - __IOM uint32_t IRQ_QUIET : 1; /*!< [21..21] In QUIET mode, the channel does not generate IRQs at - the end of every transfer block. Instead, an IRQ is raised - when NULL is written to a trigger register, indicating - the end of a control block chain. - - This reduces the number of interrupts to be serviced by - the CPU when transferring a DMA chain of many small control - blocks. */ - __IOM uint32_t BSWAP : 1; /*!< [22..22] Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the - two bytes of each halfword are swapped. For word data, - the four bytes of each word are swapped to reverse order. */ - __IOM uint32_t SNIFF_EN : 1; /*!< [23..23] If 1, this channel's data transfers are visible to - the sniff hardware, and each transfer will advance the - state of the checksum. This only applies if the sniff hardware - is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- - block basis. */ - __IM uint32_t BUSY : 1; /*!< [24..24] This flag goes high when the channel starts a new transfer - sequence, and low when the last transfer of that sequence - completes. Clearing EN while BUSY is high pauses the channel, - and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), - see CHAN_ABORT. */ - uint32_t : 4; - __IOM uint32_t WRITE_ERROR : 1; /*!< [29..29] If 1, the channel received a write bus error. Write - one to clear. - WRITE_ADDR shows the approximate address where the bus - error was encountered (will not to be earlier, or more - than 5 transfers later) */ - __IOM uint32_t READ_ERROR : 1; /*!< [30..30] If 1, the channel received a read bus error. Write - one to clear. - READ_ADDR shows the approximate address where the bus error - was encountered (will not to be earlier, or more than 3 - transfers later) */ - __IM uint32_t AHB_ERROR : 1; /*!< [31..31] Logical OR of the READ_ERROR and WRITE_ERROR flags. - The channel halts when it encounters any bus error, and - always raises its channel IRQ flag. */ - } bit; - } CH5_CTRL_TRIG; - __IM uint32_t CH5_AL1_CTRL; /*!< (@ 0x00000150) Alias for channel 5 CTRL register */ - __IM uint32_t CH5_AL1_READ_ADDR; /*!< (@ 0x00000154) Alias for channel 5 READ_ADDR register */ - __IM uint32_t CH5_AL1_WRITE_ADDR; /*!< (@ 0x00000158) Alias for channel 5 WRITE_ADDR register */ - __IM uint32_t CH5_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000015C) Alias for channel 5 TRANS_COUNT register + for the transf */ + __IOM uint32_t CH5_CTRL_TRIG; /*!< (@ 0x0000014C) DMA Channel 5 Control and Status */ + __IOM uint32_t CH5_AL1_CTRL; /*!< (@ 0x00000150) Alias for channel 5 CTRL register */ + __IOM uint32_t CH5_AL1_READ_ADDR; /*!< (@ 0x00000154) Alias for channel 5 READ_ADDR register */ + __IOM uint32_t CH5_AL1_WRITE_ADDR; /*!< (@ 0x00000158) Alias for channel 5 WRITE_ADDR register */ + __IOM uint32_t CH5_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000015C) Alias for channel 5 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH5_AL2_CTRL; /*!< (@ 0x00000160) Alias for channel 5 CTRL register */ - __IM uint32_t CH5_AL2_TRANS_COUNT; /*!< (@ 0x00000164) Alias for channel 5 TRANS_COUNT register */ - __IM uint32_t CH5_AL2_READ_ADDR; /*!< (@ 0x00000168) Alias for channel 5 READ_ADDR register */ - __IM uint32_t CH5_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000016C) Alias for channel 5 WRITE_ADDR register + __IOM uint32_t CH5_AL2_CTRL; /*!< (@ 0x00000160) Alias for channel 5 CTRL register */ + __IOM uint32_t CH5_AL2_TRANS_COUNT; /*!< (@ 0x00000164) Alias for channel 5 TRANS_COUNT register */ + __IOM uint32_t CH5_AL2_READ_ADDR; /*!< (@ 0x00000168) Alias for channel 5 READ_ADDR register */ + __IOM uint32_t CH5_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000016C) Alias for channel 5 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH5_AL3_CTRL; /*!< (@ 0x00000170) Alias for channel 5 CTRL register */ - __IM uint32_t CH5_AL3_WRITE_ADDR; /*!< (@ 0x00000174) Alias for channel 5 WRITE_ADDR register */ - __IM uint32_t CH5_AL3_TRANS_COUNT; /*!< (@ 0x00000178) Alias for channel 5 TRANS_COUNT register */ - __IM uint32_t CH5_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000017C) Alias for channel 5 READ_ADDR register + __IOM uint32_t CH5_AL3_CTRL; /*!< (@ 0x00000170) Alias for channel 5 CTRL register */ + __IOM uint32_t CH5_AL3_WRITE_ADDR; /*!< (@ 0x00000174) Alias for channel 5 WRITE_ADDR register */ + __IOM uint32_t CH5_AL3_TRANS_COUNT; /*!< (@ 0x00000178) Alias for channel 5 TRANS_COUNT register */ + __IOM uint32_t CH5_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000017C) Alias for channel 5 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the @@ -10440,123 +1859,28 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur transfer completes. Writing this register sets the RELOAD value - for the tran */ - - union { - __IOM uint32_t reg; /*!< (@ 0x0000018C) DMA Channel 6 Control and Status */ - - struct { - __IOM uint32_t EN : 1; /*!< [0..0] DMA Channel Enable. - When 1, the channel will respond to triggering events, - which will cause it to become BUSY and start transferring - data. When 0, the channel will ignore triggers, stop issuing - transfers, and pause the current transfer sequence (i.e. - BUSY will remain high if already high) */ - __IOM uint32_t HIGH_PRIORITY : 1; /*!< [1..1] HIGH_PRIORITY gives a channel preferential treatment - in issue scheduling: in each scheduling round, all high - priority channels are considered first, and then only a - single low priority channel, before returning to the high - priority channels. - - This only affects the order in which the DMA schedules - channels. The DMA's bus priority is not changed. If the - DMA is not saturated then a low priority channel will see - no loss of throughput. */ - __IOM uint32_t DATA_SIZE : 2; /*!< [3..2] Set the size of each bus transfer (byte/halfword/word). - READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 - bytes) with each transfer. */ - __IOM uint32_t INCR_READ : 1; /*!< [4..4] If 1, the read address increments with each transfer. - If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory - transfers. */ - __IOM uint32_t INCR_WRITE : 1; /*!< [5..5] If 1, the write address increments with each transfer. - If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral - transfers. */ - __IOM uint32_t RING_SIZE : 4; /*!< [9..6] Size of address wrap region. If 0, don't wrap. For values - n > 0, only the lower n bits of the address will change. - This wraps the address on a (1 << n) byte boundary, facilitating - access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This - can apply to either read or write addresses, based on value - of RING_SEL. */ - __IOM uint32_t RING_SEL : 1; /*!< [10..10] Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) - boundary. If 1, write addresses are wrapped. */ - __IOM uint32_t CHAIN_TO : 4; /*!< [14..11] When this channel completes, it will trigger the channel - indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this - channel)_. - Reset value is equal to channel number (6). */ - __IOM uint32_t TREQ_SEL : 6; /*!< [20..15] Select a Transfer Request signal. - The channel uses the transfer request signal to pace its - data transfer rate. Sources for TREQ signals are internal - (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ */ - __IOM uint32_t IRQ_QUIET : 1; /*!< [21..21] In QUIET mode, the channel does not generate IRQs at - the end of every transfer block. Instead, an IRQ is raised - when NULL is written to a trigger register, indicating - the end of a control block chain. - - This reduces the number of interrupts to be serviced by - the CPU when transferring a DMA chain of many small control - blocks. */ - __IOM uint32_t BSWAP : 1; /*!< [22..22] Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the - two bytes of each halfword are swapped. For word data, - the four bytes of each word are swapped to reverse order. */ - __IOM uint32_t SNIFF_EN : 1; /*!< [23..23] If 1, this channel's data transfers are visible to - the sniff hardware, and each transfer will advance the - state of the checksum. This only applies if the sniff hardware - is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- - block basis. */ - __IM uint32_t BUSY : 1; /*!< [24..24] This flag goes high when the channel starts a new transfer - sequence, and low when the last transfer of that sequence - completes. Clearing EN while BUSY is high pauses the channel, - and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), - see CHAN_ABORT. */ - uint32_t : 4; - __IOM uint32_t WRITE_ERROR : 1; /*!< [29..29] If 1, the channel received a write bus error. Write - one to clear. - WRITE_ADDR shows the approximate address where the bus - error was encountered (will not to be earlier, or more - than 5 transfers later) */ - __IOM uint32_t READ_ERROR : 1; /*!< [30..30] If 1, the channel received a read bus error. Write - one to clear. - READ_ADDR shows the approximate address where the bus error - was encountered (will not to be earlier, or more than 3 - transfers later) */ - __IM uint32_t AHB_ERROR : 1; /*!< [31..31] Logical OR of the READ_ERROR and WRITE_ERROR flags. - The channel halts when it encounters any bus error, and - always raises its channel IRQ flag. */ - } bit; - } CH6_CTRL_TRIG; - __IM uint32_t CH6_AL1_CTRL; /*!< (@ 0x00000190) Alias for channel 6 CTRL register */ - __IM uint32_t CH6_AL1_READ_ADDR; /*!< (@ 0x00000194) Alias for channel 6 READ_ADDR register */ - __IM uint32_t CH6_AL1_WRITE_ADDR; /*!< (@ 0x00000198) Alias for channel 6 WRITE_ADDR register */ - __IM uint32_t CH6_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000019C) Alias for channel 6 TRANS_COUNT register + for the transf */ + __IOM uint32_t CH6_CTRL_TRIG; /*!< (@ 0x0000018C) DMA Channel 6 Control and Status */ + __IOM uint32_t CH6_AL1_CTRL; /*!< (@ 0x00000190) Alias for channel 6 CTRL register */ + __IOM uint32_t CH6_AL1_READ_ADDR; /*!< (@ 0x00000194) Alias for channel 6 READ_ADDR register */ + __IOM uint32_t CH6_AL1_WRITE_ADDR; /*!< (@ 0x00000198) Alias for channel 6 WRITE_ADDR register */ + __IOM uint32_t CH6_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000019C) Alias for channel 6 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH6_AL2_CTRL; /*!< (@ 0x000001A0) Alias for channel 6 CTRL register */ - __IM uint32_t CH6_AL2_TRANS_COUNT; /*!< (@ 0x000001A4) Alias for channel 6 TRANS_COUNT register */ - __IM uint32_t CH6_AL2_READ_ADDR; /*!< (@ 0x000001A8) Alias for channel 6 READ_ADDR register */ - __IM uint32_t CH6_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000001AC) Alias for channel 6 WRITE_ADDR register + __IOM uint32_t CH6_AL2_CTRL; /*!< (@ 0x000001A0) Alias for channel 6 CTRL register */ + __IOM uint32_t CH6_AL2_TRANS_COUNT; /*!< (@ 0x000001A4) Alias for channel 6 TRANS_COUNT register */ + __IOM uint32_t CH6_AL2_READ_ADDR; /*!< (@ 0x000001A8) Alias for channel 6 READ_ADDR register */ + __IOM uint32_t CH6_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000001AC) Alias for channel 6 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH6_AL3_CTRL; /*!< (@ 0x000001B0) Alias for channel 6 CTRL register */ - __IM uint32_t CH6_AL3_WRITE_ADDR; /*!< (@ 0x000001B4) Alias for channel 6 WRITE_ADDR register */ - __IM uint32_t CH6_AL3_TRANS_COUNT; /*!< (@ 0x000001B8) Alias for channel 6 TRANS_COUNT register */ - __IM uint32_t CH6_AL3_READ_ADDR_TRIG; /*!< (@ 0x000001BC) Alias for channel 6 READ_ADDR register + __IOM uint32_t CH6_AL3_CTRL; /*!< (@ 0x000001B0) Alias for channel 6 CTRL register */ + __IOM uint32_t CH6_AL3_WRITE_ADDR; /*!< (@ 0x000001B4) Alias for channel 6 WRITE_ADDR register */ + __IOM uint32_t CH6_AL3_TRANS_COUNT; /*!< (@ 0x000001B8) Alias for channel 6 TRANS_COUNT register */ + __IOM uint32_t CH6_AL3_READ_ADDR_TRIG; /*!< (@ 0x000001BC) Alias for channel 6 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the @@ -10583,123 +1907,28 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur transfer completes. Writing this register sets the RELOAD value - for the tran */ - - union { - __IOM uint32_t reg; /*!< (@ 0x000001CC) DMA Channel 7 Control and Status */ - - struct { - __IOM uint32_t EN : 1; /*!< [0..0] DMA Channel Enable. - When 1, the channel will respond to triggering events, - which will cause it to become BUSY and start transferring - data. When 0, the channel will ignore triggers, stop issuing - transfers, and pause the current transfer sequence (i.e. - BUSY will remain high if already high) */ - __IOM uint32_t HIGH_PRIORITY : 1; /*!< [1..1] HIGH_PRIORITY gives a channel preferential treatment - in issue scheduling: in each scheduling round, all high - priority channels are considered first, and then only a - single low priority channel, before returning to the high - priority channels. - - This only affects the order in which the DMA schedules - channels. The DMA's bus priority is not changed. If the - DMA is not saturated then a low priority channel will see - no loss of throughput. */ - __IOM uint32_t DATA_SIZE : 2; /*!< [3..2] Set the size of each bus transfer (byte/halfword/word). - READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 - bytes) with each transfer. */ - __IOM uint32_t INCR_READ : 1; /*!< [4..4] If 1, the read address increments with each transfer. - If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory - transfers. */ - __IOM uint32_t INCR_WRITE : 1; /*!< [5..5] If 1, the write address increments with each transfer. - If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral - transfers. */ - __IOM uint32_t RING_SIZE : 4; /*!< [9..6] Size of address wrap region. If 0, don't wrap. For values - n > 0, only the lower n bits of the address will change. - This wraps the address on a (1 << n) byte boundary, facilitating - access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This - can apply to either read or write addresses, based on value - of RING_SEL. */ - __IOM uint32_t RING_SEL : 1; /*!< [10..10] Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) - boundary. If 1, write addresses are wrapped. */ - __IOM uint32_t CHAIN_TO : 4; /*!< [14..11] When this channel completes, it will trigger the channel - indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this - channel)_. - Reset value is equal to channel number (7). */ - __IOM uint32_t TREQ_SEL : 6; /*!< [20..15] Select a Transfer Request signal. - The channel uses the transfer request signal to pace its - data transfer rate. Sources for TREQ signals are internal - (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ */ - __IOM uint32_t IRQ_QUIET : 1; /*!< [21..21] In QUIET mode, the channel does not generate IRQs at - the end of every transfer block. Instead, an IRQ is raised - when NULL is written to a trigger register, indicating - the end of a control block chain. - - This reduces the number of interrupts to be serviced by - the CPU when transferring a DMA chain of many small control - blocks. */ - __IOM uint32_t BSWAP : 1; /*!< [22..22] Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the - two bytes of each halfword are swapped. For word data, - the four bytes of each word are swapped to reverse order. */ - __IOM uint32_t SNIFF_EN : 1; /*!< [23..23] If 1, this channel's data transfers are visible to - the sniff hardware, and each transfer will advance the - state of the checksum. This only applies if the sniff hardware - is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- - block basis. */ - __IM uint32_t BUSY : 1; /*!< [24..24] This flag goes high when the channel starts a new transfer - sequence, and low when the last transfer of that sequence - completes. Clearing EN while BUSY is high pauses the channel, - and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), - see CHAN_ABORT. */ - uint32_t : 4; - __IOM uint32_t WRITE_ERROR : 1; /*!< [29..29] If 1, the channel received a write bus error. Write - one to clear. - WRITE_ADDR shows the approximate address where the bus - error was encountered (will not to be earlier, or more - than 5 transfers later) */ - __IOM uint32_t READ_ERROR : 1; /*!< [30..30] If 1, the channel received a read bus error. Write - one to clear. - READ_ADDR shows the approximate address where the bus error - was encountered (will not to be earlier, or more than 3 - transfers later) */ - __IM uint32_t AHB_ERROR : 1; /*!< [31..31] Logical OR of the READ_ERROR and WRITE_ERROR flags. - The channel halts when it encounters any bus error, and - always raises its channel IRQ flag. */ - } bit; - } CH7_CTRL_TRIG; - __IM uint32_t CH7_AL1_CTRL; /*!< (@ 0x000001D0) Alias for channel 7 CTRL register */ - __IM uint32_t CH7_AL1_READ_ADDR; /*!< (@ 0x000001D4) Alias for channel 7 READ_ADDR register */ - __IM uint32_t CH7_AL1_WRITE_ADDR; /*!< (@ 0x000001D8) Alias for channel 7 WRITE_ADDR register */ - __IM uint32_t CH7_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x000001DC) Alias for channel 7 TRANS_COUNT register + for the transf */ + __IOM uint32_t CH7_CTRL_TRIG; /*!< (@ 0x000001CC) DMA Channel 7 Control and Status */ + __IOM uint32_t CH7_AL1_CTRL; /*!< (@ 0x000001D0) Alias for channel 7 CTRL register */ + __IOM uint32_t CH7_AL1_READ_ADDR; /*!< (@ 0x000001D4) Alias for channel 7 READ_ADDR register */ + __IOM uint32_t CH7_AL1_WRITE_ADDR; /*!< (@ 0x000001D8) Alias for channel 7 WRITE_ADDR register */ + __IOM uint32_t CH7_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x000001DC) Alias for channel 7 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH7_AL2_CTRL; /*!< (@ 0x000001E0) Alias for channel 7 CTRL register */ - __IM uint32_t CH7_AL2_TRANS_COUNT; /*!< (@ 0x000001E4) Alias for channel 7 TRANS_COUNT register */ - __IM uint32_t CH7_AL2_READ_ADDR; /*!< (@ 0x000001E8) Alias for channel 7 READ_ADDR register */ - __IM uint32_t CH7_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000001EC) Alias for channel 7 WRITE_ADDR register + __IOM uint32_t CH7_AL2_CTRL; /*!< (@ 0x000001E0) Alias for channel 7 CTRL register */ + __IOM uint32_t CH7_AL2_TRANS_COUNT; /*!< (@ 0x000001E4) Alias for channel 7 TRANS_COUNT register */ + __IOM uint32_t CH7_AL2_READ_ADDR; /*!< (@ 0x000001E8) Alias for channel 7 READ_ADDR register */ + __IOM uint32_t CH7_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000001EC) Alias for channel 7 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH7_AL3_CTRL; /*!< (@ 0x000001F0) Alias for channel 7 CTRL register */ - __IM uint32_t CH7_AL3_WRITE_ADDR; /*!< (@ 0x000001F4) Alias for channel 7 WRITE_ADDR register */ - __IM uint32_t CH7_AL3_TRANS_COUNT; /*!< (@ 0x000001F8) Alias for channel 7 TRANS_COUNT register */ - __IM uint32_t CH7_AL3_READ_ADDR_TRIG; /*!< (@ 0x000001FC) Alias for channel 7 READ_ADDR register + __IOM uint32_t CH7_AL3_CTRL; /*!< (@ 0x000001F0) Alias for channel 7 CTRL register */ + __IOM uint32_t CH7_AL3_WRITE_ADDR; /*!< (@ 0x000001F4) Alias for channel 7 WRITE_ADDR register */ + __IOM uint32_t CH7_AL3_TRANS_COUNT; /*!< (@ 0x000001F8) Alias for channel 7 TRANS_COUNT register */ + __IOM uint32_t CH7_AL3_READ_ADDR_TRIG; /*!< (@ 0x000001FC) Alias for channel 7 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the @@ -10726,123 +1955,28 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur transfer completes. Writing this register sets the RELOAD value - for the tran */ - - union { - __IOM uint32_t reg; /*!< (@ 0x0000020C) DMA Channel 8 Control and Status */ - - struct { - __IOM uint32_t EN : 1; /*!< [0..0] DMA Channel Enable. - When 1, the channel will respond to triggering events, - which will cause it to become BUSY and start transferring - data. When 0, the channel will ignore triggers, stop issuing - transfers, and pause the current transfer sequence (i.e. - BUSY will remain high if already high) */ - __IOM uint32_t HIGH_PRIORITY : 1; /*!< [1..1] HIGH_PRIORITY gives a channel preferential treatment - in issue scheduling: in each scheduling round, all high - priority channels are considered first, and then only a - single low priority channel, before returning to the high - priority channels. - - This only affects the order in which the DMA schedules - channels. The DMA's bus priority is not changed. If the - DMA is not saturated then a low priority channel will see - no loss of throughput. */ - __IOM uint32_t DATA_SIZE : 2; /*!< [3..2] Set the size of each bus transfer (byte/halfword/word). - READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 - bytes) with each transfer. */ - __IOM uint32_t INCR_READ : 1; /*!< [4..4] If 1, the read address increments with each transfer. - If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory - transfers. */ - __IOM uint32_t INCR_WRITE : 1; /*!< [5..5] If 1, the write address increments with each transfer. - If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral - transfers. */ - __IOM uint32_t RING_SIZE : 4; /*!< [9..6] Size of address wrap region. If 0, don't wrap. For values - n > 0, only the lower n bits of the address will change. - This wraps the address on a (1 << n) byte boundary, facilitating - access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This - can apply to either read or write addresses, based on value - of RING_SEL. */ - __IOM uint32_t RING_SEL : 1; /*!< [10..10] Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) - boundary. If 1, write addresses are wrapped. */ - __IOM uint32_t CHAIN_TO : 4; /*!< [14..11] When this channel completes, it will trigger the channel - indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this - channel)_. - Reset value is equal to channel number (8). */ - __IOM uint32_t TREQ_SEL : 6; /*!< [20..15] Select a Transfer Request signal. - The channel uses the transfer request signal to pace its - data transfer rate. Sources for TREQ signals are internal - (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ */ - __IOM uint32_t IRQ_QUIET : 1; /*!< [21..21] In QUIET mode, the channel does not generate IRQs at - the end of every transfer block. Instead, an IRQ is raised - when NULL is written to a trigger register, indicating - the end of a control block chain. - - This reduces the number of interrupts to be serviced by - the CPU when transferring a DMA chain of many small control - blocks. */ - __IOM uint32_t BSWAP : 1; /*!< [22..22] Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the - two bytes of each halfword are swapped. For word data, - the four bytes of each word are swapped to reverse order. */ - __IOM uint32_t SNIFF_EN : 1; /*!< [23..23] If 1, this channel's data transfers are visible to - the sniff hardware, and each transfer will advance the - state of the checksum. This only applies if the sniff hardware - is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- - block basis. */ - __IM uint32_t BUSY : 1; /*!< [24..24] This flag goes high when the channel starts a new transfer - sequence, and low when the last transfer of that sequence - completes. Clearing EN while BUSY is high pauses the channel, - and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), - see CHAN_ABORT. */ - uint32_t : 4; - __IOM uint32_t WRITE_ERROR : 1; /*!< [29..29] If 1, the channel received a write bus error. Write - one to clear. - WRITE_ADDR shows the approximate address where the bus - error was encountered (will not to be earlier, or more - than 5 transfers later) */ - __IOM uint32_t READ_ERROR : 1; /*!< [30..30] If 1, the channel received a read bus error. Write - one to clear. - READ_ADDR shows the approximate address where the bus error - was encountered (will not to be earlier, or more than 3 - transfers later) */ - __IM uint32_t AHB_ERROR : 1; /*!< [31..31] Logical OR of the READ_ERROR and WRITE_ERROR flags. - The channel halts when it encounters any bus error, and - always raises its channel IRQ flag. */ - } bit; - } CH8_CTRL_TRIG; - __IM uint32_t CH8_AL1_CTRL; /*!< (@ 0x00000210) Alias for channel 8 CTRL register */ - __IM uint32_t CH8_AL1_READ_ADDR; /*!< (@ 0x00000214) Alias for channel 8 READ_ADDR register */ - __IM uint32_t CH8_AL1_WRITE_ADDR; /*!< (@ 0x00000218) Alias for channel 8 WRITE_ADDR register */ - __IM uint32_t CH8_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000021C) Alias for channel 8 TRANS_COUNT register + for the transf */ + __IOM uint32_t CH8_CTRL_TRIG; /*!< (@ 0x0000020C) DMA Channel 8 Control and Status */ + __IOM uint32_t CH8_AL1_CTRL; /*!< (@ 0x00000210) Alias for channel 8 CTRL register */ + __IOM uint32_t CH8_AL1_READ_ADDR; /*!< (@ 0x00000214) Alias for channel 8 READ_ADDR register */ + __IOM uint32_t CH8_AL1_WRITE_ADDR; /*!< (@ 0x00000218) Alias for channel 8 WRITE_ADDR register */ + __IOM uint32_t CH8_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000021C) Alias for channel 8 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH8_AL2_CTRL; /*!< (@ 0x00000220) Alias for channel 8 CTRL register */ - __IM uint32_t CH8_AL2_TRANS_COUNT; /*!< (@ 0x00000224) Alias for channel 8 TRANS_COUNT register */ - __IM uint32_t CH8_AL2_READ_ADDR; /*!< (@ 0x00000228) Alias for channel 8 READ_ADDR register */ - __IM uint32_t CH8_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000022C) Alias for channel 8 WRITE_ADDR register + __IOM uint32_t CH8_AL2_CTRL; /*!< (@ 0x00000220) Alias for channel 8 CTRL register */ + __IOM uint32_t CH8_AL2_TRANS_COUNT; /*!< (@ 0x00000224) Alias for channel 8 TRANS_COUNT register */ + __IOM uint32_t CH8_AL2_READ_ADDR; /*!< (@ 0x00000228) Alias for channel 8 READ_ADDR register */ + __IOM uint32_t CH8_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000022C) Alias for channel 8 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH8_AL3_CTRL; /*!< (@ 0x00000230) Alias for channel 8 CTRL register */ - __IM uint32_t CH8_AL3_WRITE_ADDR; /*!< (@ 0x00000234) Alias for channel 8 WRITE_ADDR register */ - __IM uint32_t CH8_AL3_TRANS_COUNT; /*!< (@ 0x00000238) Alias for channel 8 TRANS_COUNT register */ - __IM uint32_t CH8_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000023C) Alias for channel 8 READ_ADDR register + __IOM uint32_t CH8_AL3_CTRL; /*!< (@ 0x00000230) Alias for channel 8 CTRL register */ + __IOM uint32_t CH8_AL3_WRITE_ADDR; /*!< (@ 0x00000234) Alias for channel 8 WRITE_ADDR register */ + __IOM uint32_t CH8_AL3_TRANS_COUNT; /*!< (@ 0x00000238) Alias for channel 8 TRANS_COUNT register */ + __IOM uint32_t CH8_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000023C) Alias for channel 8 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the @@ -10869,123 +2003,28 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur transfer completes. Writing this register sets the RELOAD value - for the tran */ - - union { - __IOM uint32_t reg; /*!< (@ 0x0000024C) DMA Channel 9 Control and Status */ - - struct { - __IOM uint32_t EN : 1; /*!< [0..0] DMA Channel Enable. - When 1, the channel will respond to triggering events, - which will cause it to become BUSY and start transferring - data. When 0, the channel will ignore triggers, stop issuing - transfers, and pause the current transfer sequence (i.e. - BUSY will remain high if already high) */ - __IOM uint32_t HIGH_PRIORITY : 1; /*!< [1..1] HIGH_PRIORITY gives a channel preferential treatment - in issue scheduling: in each scheduling round, all high - priority channels are considered first, and then only a - single low priority channel, before returning to the high - priority channels. - - This only affects the order in which the DMA schedules - channels. The DMA's bus priority is not changed. If the - DMA is not saturated then a low priority channel will see - no loss of throughput. */ - __IOM uint32_t DATA_SIZE : 2; /*!< [3..2] Set the size of each bus transfer (byte/halfword/word). - READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 - bytes) with each transfer. */ - __IOM uint32_t INCR_READ : 1; /*!< [4..4] If 1, the read address increments with each transfer. - If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory - transfers. */ - __IOM uint32_t INCR_WRITE : 1; /*!< [5..5] If 1, the write address increments with each transfer. - If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral - transfers. */ - __IOM uint32_t RING_SIZE : 4; /*!< [9..6] Size of address wrap region. If 0, don't wrap. For values - n > 0, only the lower n bits of the address will change. - This wraps the address on a (1 << n) byte boundary, facilitating - access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This - can apply to either read or write addresses, based on value - of RING_SEL. */ - __IOM uint32_t RING_SEL : 1; /*!< [10..10] Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) - boundary. If 1, write addresses are wrapped. */ - __IOM uint32_t CHAIN_TO : 4; /*!< [14..11] When this channel completes, it will trigger the channel - indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this - channel)_. - Reset value is equal to channel number (9). */ - __IOM uint32_t TREQ_SEL : 6; /*!< [20..15] Select a Transfer Request signal. - The channel uses the transfer request signal to pace its - data transfer rate. Sources for TREQ signals are internal - (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ */ - __IOM uint32_t IRQ_QUIET : 1; /*!< [21..21] In QUIET mode, the channel does not generate IRQs at - the end of every transfer block. Instead, an IRQ is raised - when NULL is written to a trigger register, indicating - the end of a control block chain. - - This reduces the number of interrupts to be serviced by - the CPU when transferring a DMA chain of many small control - blocks. */ - __IOM uint32_t BSWAP : 1; /*!< [22..22] Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the - two bytes of each halfword are swapped. For word data, - the four bytes of each word are swapped to reverse order. */ - __IOM uint32_t SNIFF_EN : 1; /*!< [23..23] If 1, this channel's data transfers are visible to - the sniff hardware, and each transfer will advance the - state of the checksum. This only applies if the sniff hardware - is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- - block basis. */ - __IM uint32_t BUSY : 1; /*!< [24..24] This flag goes high when the channel starts a new transfer - sequence, and low when the last transfer of that sequence - completes. Clearing EN while BUSY is high pauses the channel, - and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), - see CHAN_ABORT. */ - uint32_t : 4; - __IOM uint32_t WRITE_ERROR : 1; /*!< [29..29] If 1, the channel received a write bus error. Write - one to clear. - WRITE_ADDR shows the approximate address where the bus - error was encountered (will not to be earlier, or more - than 5 transfers later) */ - __IOM uint32_t READ_ERROR : 1; /*!< [30..30] If 1, the channel received a read bus error. Write - one to clear. - READ_ADDR shows the approximate address where the bus error - was encountered (will not to be earlier, or more than 3 - transfers later) */ - __IM uint32_t AHB_ERROR : 1; /*!< [31..31] Logical OR of the READ_ERROR and WRITE_ERROR flags. - The channel halts when it encounters any bus error, and - always raises its channel IRQ flag. */ - } bit; - } CH9_CTRL_TRIG; - __IM uint32_t CH9_AL1_CTRL; /*!< (@ 0x00000250) Alias for channel 9 CTRL register */ - __IM uint32_t CH9_AL1_READ_ADDR; /*!< (@ 0x00000254) Alias for channel 9 READ_ADDR register */ - __IM uint32_t CH9_AL1_WRITE_ADDR; /*!< (@ 0x00000258) Alias for channel 9 WRITE_ADDR register */ - __IM uint32_t CH9_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000025C) Alias for channel 9 TRANS_COUNT register + for the transf */ + __IOM uint32_t CH9_CTRL_TRIG; /*!< (@ 0x0000024C) DMA Channel 9 Control and Status */ + __IOM uint32_t CH9_AL1_CTRL; /*!< (@ 0x00000250) Alias for channel 9 CTRL register */ + __IOM uint32_t CH9_AL1_READ_ADDR; /*!< (@ 0x00000254) Alias for channel 9 READ_ADDR register */ + __IOM uint32_t CH9_AL1_WRITE_ADDR; /*!< (@ 0x00000258) Alias for channel 9 WRITE_ADDR register */ + __IOM uint32_t CH9_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000025C) Alias for channel 9 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH9_AL2_CTRL; /*!< (@ 0x00000260) Alias for channel 9 CTRL register */ - __IM uint32_t CH9_AL2_TRANS_COUNT; /*!< (@ 0x00000264) Alias for channel 9 TRANS_COUNT register */ - __IM uint32_t CH9_AL2_READ_ADDR; /*!< (@ 0x00000268) Alias for channel 9 READ_ADDR register */ - __IM uint32_t CH9_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000026C) Alias for channel 9 WRITE_ADDR register + __IOM uint32_t CH9_AL2_CTRL; /*!< (@ 0x00000260) Alias for channel 9 CTRL register */ + __IOM uint32_t CH9_AL2_TRANS_COUNT; /*!< (@ 0x00000264) Alias for channel 9 TRANS_COUNT register */ + __IOM uint32_t CH9_AL2_READ_ADDR; /*!< (@ 0x00000268) Alias for channel 9 READ_ADDR register */ + __IOM uint32_t CH9_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x0000026C) Alias for channel 9 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH9_AL3_CTRL; /*!< (@ 0x00000270) Alias for channel 9 CTRL register */ - __IM uint32_t CH9_AL3_WRITE_ADDR; /*!< (@ 0x00000274) Alias for channel 9 WRITE_ADDR register */ - __IM uint32_t CH9_AL3_TRANS_COUNT; /*!< (@ 0x00000278) Alias for channel 9 TRANS_COUNT register */ - __IM uint32_t CH9_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000027C) Alias for channel 9 READ_ADDR register + __IOM uint32_t CH9_AL3_CTRL; /*!< (@ 0x00000270) Alias for channel 9 CTRL register */ + __IOM uint32_t CH9_AL3_WRITE_ADDR; /*!< (@ 0x00000274) Alias for channel 9 WRITE_ADDR register */ + __IOM uint32_t CH9_AL3_TRANS_COUNT; /*!< (@ 0x00000278) Alias for channel 9 TRANS_COUNT register */ + __IOM uint32_t CH9_AL3_READ_ADDR_TRIG; /*!< (@ 0x0000027C) Alias for channel 9 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the @@ -11012,123 +2051,28 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur transfer completes. Writing this register sets the RELOAD value - for the tra */ - - union { - __IOM uint32_t reg; /*!< (@ 0x0000028C) DMA Channel 10 Control and Status */ - - struct { - __IOM uint32_t EN : 1; /*!< [0..0] DMA Channel Enable. - When 1, the channel will respond to triggering events, - which will cause it to become BUSY and start transferring - data. When 0, the channel will ignore triggers, stop issuing - transfers, and pause the current transfer sequence (i.e. - BUSY will remain high if already high) */ - __IOM uint32_t HIGH_PRIORITY : 1; /*!< [1..1] HIGH_PRIORITY gives a channel preferential treatment - in issue scheduling: in each scheduling round, all high - priority channels are considered first, and then only a - single low priority channel, before returning to the high - priority channels. - - This only affects the order in which the DMA schedules - channels. The DMA's bus priority is not changed. If the - DMA is not saturated then a low priority channel will see - no loss of throughput. */ - __IOM uint32_t DATA_SIZE : 2; /*!< [3..2] Set the size of each bus transfer (byte/halfword/word). - READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 - bytes) with each transfer. */ - __IOM uint32_t INCR_READ : 1; /*!< [4..4] If 1, the read address increments with each transfer. - If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory - transfers. */ - __IOM uint32_t INCR_WRITE : 1; /*!< [5..5] If 1, the write address increments with each transfer. - If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral - transfers. */ - __IOM uint32_t RING_SIZE : 4; /*!< [9..6] Size of address wrap region. If 0, don't wrap. For values - n > 0, only the lower n bits of the address will change. - This wraps the address on a (1 << n) byte boundary, facilitating - access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This - can apply to either read or write addresses, based on value - of RING_SEL. */ - __IOM uint32_t RING_SEL : 1; /*!< [10..10] Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) - boundary. If 1, write addresses are wrapped. */ - __IOM uint32_t CHAIN_TO : 4; /*!< [14..11] When this channel completes, it will trigger the channel - indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this - channel)_. - Reset value is equal to channel number (10). */ - __IOM uint32_t TREQ_SEL : 6; /*!< [20..15] Select a Transfer Request signal. - The channel uses the transfer request signal to pace its - data transfer rate. Sources for TREQ signals are internal - (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ */ - __IOM uint32_t IRQ_QUIET : 1; /*!< [21..21] In QUIET mode, the channel does not generate IRQs at - the end of every transfer block. Instead, an IRQ is raised - when NULL is written to a trigger register, indicating - the end of a control block chain. - - This reduces the number of interrupts to be serviced by - the CPU when transferring a DMA chain of many small control - blocks. */ - __IOM uint32_t BSWAP : 1; /*!< [22..22] Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the - two bytes of each halfword are swapped. For word data, - the four bytes of each word are swapped to reverse order. */ - __IOM uint32_t SNIFF_EN : 1; /*!< [23..23] If 1, this channel's data transfers are visible to - the sniff hardware, and each transfer will advance the - state of the checksum. This only applies if the sniff hardware - is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- - block basis. */ - __IM uint32_t BUSY : 1; /*!< [24..24] This flag goes high when the channel starts a new transfer - sequence, and low when the last transfer of that sequence - completes. Clearing EN while BUSY is high pauses the channel, - and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), - see CHAN_ABORT. */ - uint32_t : 4; - __IOM uint32_t WRITE_ERROR : 1; /*!< [29..29] If 1, the channel received a write bus error. Write - one to clear. - WRITE_ADDR shows the approximate address where the bus - error was encountered (will not to be earlier, or more - than 5 transfers later) */ - __IOM uint32_t READ_ERROR : 1; /*!< [30..30] If 1, the channel received a read bus error. Write - one to clear. - READ_ADDR shows the approximate address where the bus error - was encountered (will not to be earlier, or more than 3 - transfers later) */ - __IM uint32_t AHB_ERROR : 1; /*!< [31..31] Logical OR of the READ_ERROR and WRITE_ERROR flags. - The channel halts when it encounters any bus error, and - always raises its channel IRQ flag. */ - } bit; - } CH10_CTRL_TRIG; - __IM uint32_t CH10_AL1_CTRL; /*!< (@ 0x00000290) Alias for channel 10 CTRL register */ - __IM uint32_t CH10_AL1_READ_ADDR; /*!< (@ 0x00000294) Alias for channel 10 READ_ADDR register */ - __IM uint32_t CH10_AL1_WRITE_ADDR; /*!< (@ 0x00000298) Alias for channel 10 WRITE_ADDR register */ - __IM uint32_t CH10_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000029C) Alias for channel 10 TRANS_COUNT register + for the trans */ + __IOM uint32_t CH10_CTRL_TRIG; /*!< (@ 0x0000028C) DMA Channel 10 Control and Status */ + __IOM uint32_t CH10_AL1_CTRL; /*!< (@ 0x00000290) Alias for channel 10 CTRL register */ + __IOM uint32_t CH10_AL1_READ_ADDR; /*!< (@ 0x00000294) Alias for channel 10 READ_ADDR register */ + __IOM uint32_t CH10_AL1_WRITE_ADDR; /*!< (@ 0x00000298) Alias for channel 10 WRITE_ADDR register */ + __IOM uint32_t CH10_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x0000029C) Alias for channel 10 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH10_AL2_CTRL; /*!< (@ 0x000002A0) Alias for channel 10 CTRL register */ - __IM uint32_t CH10_AL2_TRANS_COUNT; /*!< (@ 0x000002A4) Alias for channel 10 TRANS_COUNT register */ - __IM uint32_t CH10_AL2_READ_ADDR; /*!< (@ 0x000002A8) Alias for channel 10 READ_ADDR register */ - __IM uint32_t CH10_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000002AC) Alias for channel 10 WRITE_ADDR register + __IOM uint32_t CH10_AL2_CTRL; /*!< (@ 0x000002A0) Alias for channel 10 CTRL register */ + __IOM uint32_t CH10_AL2_TRANS_COUNT; /*!< (@ 0x000002A4) Alias for channel 10 TRANS_COUNT register */ + __IOM uint32_t CH10_AL2_READ_ADDR; /*!< (@ 0x000002A8) Alias for channel 10 READ_ADDR register */ + __IOM uint32_t CH10_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000002AC) Alias for channel 10 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH10_AL3_CTRL; /*!< (@ 0x000002B0) Alias for channel 10 CTRL register */ - __IM uint32_t CH10_AL3_WRITE_ADDR; /*!< (@ 0x000002B4) Alias for channel 10 WRITE_ADDR register */ - __IM uint32_t CH10_AL3_TRANS_COUNT; /*!< (@ 0x000002B8) Alias for channel 10 TRANS_COUNT register */ - __IM uint32_t CH10_AL3_READ_ADDR_TRIG; /*!< (@ 0x000002BC) Alias for channel 10 READ_ADDR register + __IOM uint32_t CH10_AL3_CTRL; /*!< (@ 0x000002B0) Alias for channel 10 CTRL register */ + __IOM uint32_t CH10_AL3_WRITE_ADDR; /*!< (@ 0x000002B4) Alias for channel 10 WRITE_ADDR register */ + __IOM uint32_t CH10_AL3_TRANS_COUNT; /*!< (@ 0x000002B8) Alias for channel 10 TRANS_COUNT register */ + __IOM uint32_t CH10_AL3_READ_ADDR_TRIG; /*!< (@ 0x000002BC) Alias for channel 10 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the @@ -11155,286 +2099,71 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur transfer completes. Writing this register sets the RELOAD value - for the tra */ - - union { - __IOM uint32_t reg; /*!< (@ 0x000002CC) DMA Channel 11 Control and Status */ - - struct { - __IOM uint32_t EN : 1; /*!< [0..0] DMA Channel Enable. - When 1, the channel will respond to triggering events, - which will cause it to become BUSY and start transferring - data. When 0, the channel will ignore triggers, stop issuing - transfers, and pause the current transfer sequence (i.e. - BUSY will remain high if already high) */ - __IOM uint32_t HIGH_PRIORITY : 1; /*!< [1..1] HIGH_PRIORITY gives a channel preferential treatment - in issue scheduling: in each scheduling round, all high - priority channels are considered first, and then only a - single low priority channel, before returning to the high - priority channels. - - This only affects the order in which the DMA schedules - channels. The DMA's bus priority is not changed. If the - DMA is not saturated then a low priority channel will see - no loss of throughput. */ - __IOM uint32_t DATA_SIZE : 2; /*!< [3..2] Set the size of each bus transfer (byte/halfword/word). - READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 - bytes) with each transfer. */ - __IOM uint32_t INCR_READ : 1; /*!< [4..4] If 1, the read address increments with each transfer. - If 0, each read is directed to the same, initial address. - - Generally this should be disabled for peripheral-to-memory - transfers. */ - __IOM uint32_t INCR_WRITE : 1; /*!< [5..5] If 1, the write address increments with each transfer. - If 0, each write is directed to the same, initial address. - - Generally this should be disabled for memory-to-peripheral - transfers. */ - __IOM uint32_t RING_SIZE : 4; /*!< [9..6] Size of address wrap region. If 0, don't wrap. For values - n > 0, only the lower n bits of the address will change. - This wraps the address on a (1 << n) byte boundary, facilitating - access to naturally-aligned ring buffers. - - Ring sizes between 2 and 32768 bytes are possible. This - can apply to either read or write addresses, based on value - of RING_SEL. */ - __IOM uint32_t RING_SEL : 1; /*!< [10..10] Select whether RING_SIZE applies to read or write addresses. - If 0, read addresses are wrapped on a (1 << RING_SIZE) - boundary. If 1, write addresses are wrapped. */ - __IOM uint32_t CHAIN_TO : 4; /*!< [14..11] When this channel completes, it will trigger the channel - indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this - channel)_. - Reset value is equal to channel number (11). */ - __IOM uint32_t TREQ_SEL : 6; /*!< [20..15] Select a Transfer Request signal. - The channel uses the transfer request signal to pace its - data transfer rate. Sources for TREQ signals are internal - (TIMERS) or external (DREQ, a Data Request from the system). - 0x0 to 0x3a -> select DREQ n as TREQ */ - __IOM uint32_t IRQ_QUIET : 1; /*!< [21..21] In QUIET mode, the channel does not generate IRQs at - the end of every transfer block. Instead, an IRQ is raised - when NULL is written to a trigger register, indicating - the end of a control block chain. - - This reduces the number of interrupts to be serviced by - the CPU when transferring a DMA chain of many small control - blocks. */ - __IOM uint32_t BSWAP : 1; /*!< [22..22] Apply byte-swap transformation to DMA data. - For byte data, this has no effect. For halfword data, the - two bytes of each halfword are swapped. For word data, - the four bytes of each word are swapped to reverse order. */ - __IOM uint32_t SNIFF_EN : 1; /*!< [23..23] If 1, this channel's data transfers are visible to - the sniff hardware, and each transfer will advance the - state of the checksum. This only applies if the sniff hardware - is enabled, and has this channel selected. - - This allows checksum to be enabled or disabled on a per-control- - block basis. */ - __IM uint32_t BUSY : 1; /*!< [24..24] This flag goes high when the channel starts a new transfer - sequence, and low when the last transfer of that sequence - completes. Clearing EN while BUSY is high pauses the channel, - and BUSY will stay high while paused. - - To terminate a sequence early (and clear the BUSY flag), - see CHAN_ABORT. */ - uint32_t : 4; - __IOM uint32_t WRITE_ERROR : 1; /*!< [29..29] If 1, the channel received a write bus error. Write - one to clear. - WRITE_ADDR shows the approximate address where the bus - error was encountered (will not to be earlier, or more - than 5 transfers later) */ - __IOM uint32_t READ_ERROR : 1; /*!< [30..30] If 1, the channel received a read bus error. Write - one to clear. - READ_ADDR shows the approximate address where the bus error - was encountered (will not to be earlier, or more than 3 - transfers later) */ - __IM uint32_t AHB_ERROR : 1; /*!< [31..31] Logical OR of the READ_ERROR and WRITE_ERROR flags. - The channel halts when it encounters any bus error, and - always raises its channel IRQ flag. */ - } bit; - } CH11_CTRL_TRIG; - __IM uint32_t CH11_AL1_CTRL; /*!< (@ 0x000002D0) Alias for channel 11 CTRL register */ - __IM uint32_t CH11_AL1_READ_ADDR; /*!< (@ 0x000002D4) Alias for channel 11 READ_ADDR register */ - __IM uint32_t CH11_AL1_WRITE_ADDR; /*!< (@ 0x000002D8) Alias for channel 11 WRITE_ADDR register */ - __IM uint32_t CH11_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x000002DC) Alias for channel 11 TRANS_COUNT register + for the trans */ + __IOM uint32_t CH11_CTRL_TRIG; /*!< (@ 0x000002CC) DMA Channel 11 Control and Status */ + __IOM uint32_t CH11_AL1_CTRL; /*!< (@ 0x000002D0) Alias for channel 11 CTRL register */ + __IOM uint32_t CH11_AL1_READ_ADDR; /*!< (@ 0x000002D4) Alias for channel 11 READ_ADDR register */ + __IOM uint32_t CH11_AL1_WRITE_ADDR; /*!< (@ 0x000002D8) Alias for channel 11 WRITE_ADDR register */ + __IOM uint32_t CH11_AL1_TRANS_COUNT_TRIG; /*!< (@ 0x000002DC) Alias for channel 11 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH11_AL2_CTRL; /*!< (@ 0x000002E0) Alias for channel 11 CTRL register */ - __IM uint32_t CH11_AL2_TRANS_COUNT; /*!< (@ 0x000002E4) Alias for channel 11 TRANS_COUNT register */ - __IM uint32_t CH11_AL2_READ_ADDR; /*!< (@ 0x000002E8) Alias for channel 11 READ_ADDR register */ - __IM uint32_t CH11_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000002EC) Alias for channel 11 WRITE_ADDR register + __IOM uint32_t CH11_AL2_CTRL; /*!< (@ 0x000002E0) Alias for channel 11 CTRL register */ + __IOM uint32_t CH11_AL2_TRANS_COUNT; /*!< (@ 0x000002E4) Alias for channel 11 TRANS_COUNT register */ + __IOM uint32_t CH11_AL2_READ_ADDR; /*!< (@ 0x000002E8) Alias for channel 11 READ_ADDR register */ + __IOM uint32_t CH11_AL2_WRITE_ADDR_TRIG; /*!< (@ 0x000002EC) Alias for channel 11 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ - __IM uint32_t CH11_AL3_CTRL; /*!< (@ 0x000002F0) Alias for channel 11 CTRL register */ - __IM uint32_t CH11_AL3_WRITE_ADDR; /*!< (@ 0x000002F4) Alias for channel 11 WRITE_ADDR register */ - __IM uint32_t CH11_AL3_TRANS_COUNT; /*!< (@ 0x000002F8) Alias for channel 11 TRANS_COUNT register */ - __IM uint32_t CH11_AL3_READ_ADDR_TRIG; /*!< (@ 0x000002FC) Alias for channel 11 READ_ADDR register + __IOM uint32_t CH11_AL3_CTRL; /*!< (@ 0x000002F0) Alias for channel 11 CTRL register */ + __IOM uint32_t CH11_AL3_WRITE_ADDR; /*!< (@ 0x000002F4) Alias for channel 11 WRITE_ADDR register */ + __IOM uint32_t CH11_AL3_TRANS_COUNT; /*!< (@ 0x000002F8) Alias for channel 11 TRANS_COUNT register */ + __IOM uint32_t CH11_AL3_READ_ADDR_TRIG; /*!< (@ 0x000002FC) Alias for channel 11 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. */ __IM uint32_t RESERVED[64]; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000400) Interrupt Status (raw) */ - - struct { - __IM uint32_t INTR : 16; /*!< [15..0] Raw interrupt status for DMA Channels 0..15. Bit n corresponds - to channel n. Ignores any masking or forcing. Channel interrupts - can be cleared by writing a bit mask to INTR, INTS0 or - INTS1. - - Channel interrupts can be routed to either of two system-level - IRQs based on INTE0 and INTE1. - - This can be used vector different channel interrupts to - different ISRs: this might be done to allow NVIC IRQ preemption - for more time-critical channels, or to spread IRQ load - across d */ - uint32_t : 16; - } bit; - } INTR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000404) Interrupt Enables for IRQ 0 */ - - struct { - __IOM uint32_t INTE0 : 16; /*!< [15..0] Set bit n to pass interrupts from channel n to DMA IRQ - 0. */ - uint32_t : 16; - } bit; - } INTE0; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000408) Force Interrupts */ - - struct { - __IOM uint32_t INTF0 : 16; /*!< [15..0] Write 1s to force the corresponding bits in INTE0. The - interrupt remains asserted until INTF0 is cleared. */ - uint32_t : 16; - } bit; - } INTF0; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000040C) Interrupt Status for IRQ 0 */ - - struct { - __IOM uint32_t INTS0 : 16; /*!< [15..0] Indicates active channel interrupt requests which are - currently causing IRQ 0 to be asserted. - Channel interrupts can be cleared by writing a bit mask - here. */ - uint32_t : 16; - } bit; - } INTS0; + __IOM uint32_t INTR; /*!< (@ 0x00000400) Interrupt Status (raw) */ + __IOM uint32_t INTE0; /*!< (@ 0x00000404) Interrupt Enables for IRQ 0 */ + __IOM uint32_t INTF0; /*!< (@ 0x00000408) Force Interrupts */ + __IOM uint32_t INTS0; /*!< (@ 0x0000040C) Interrupt Status for IRQ 0 */ __IM uint32_t RESERVED1; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000414) Interrupt Enables for IRQ 1 */ - - struct { - __IOM uint32_t INTE1 : 16; /*!< [15..0] Set bit n to pass interrupts from channel n to DMA IRQ - 1. */ - uint32_t : 16; - } bit; - } INTE1; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000418) Force Interrupts for IRQ 1 */ - - struct { - __IOM uint32_t INTF1 : 16; /*!< [15..0] Write 1s to force the corresponding bits in INTE0. The - interrupt remains asserted until INTF0 is cleared. */ - uint32_t : 16; - } bit; - } INTF1; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000041C) Interrupt Status (masked) for IRQ 1 */ - - struct { - __IOM uint32_t INTS1 : 16; /*!< [15..0] Indicates active channel interrupt requests which are - currently causing IRQ 1 to be asserted. - Channel interrupts can be cleared by writing a bit mask - here. */ - uint32_t : 16; - } bit; - } INTS1; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000420) Pacing (X/Y) Fractional Timer + __IOM uint32_t INTE1; /*!< (@ 0x00000414) Interrupt Enables for IRQ 1 */ + __IOM uint32_t INTF1; /*!< (@ 0x00000418) Force Interrupts for IRQ 1 */ + __IOM uint32_t INTS1; /*!< (@ 0x0000041C) Interrupt Status (masked) for IRQ 1 */ + __IOM uint32_t TIMER0; /*!< (@ 0x00000420) Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. */ - - struct { - __IOM uint32_t Y : 16; /*!< [15..0] Pacing Timer Divisor. Specifies the Y value for the - (X/Y) fractional timer. */ - __IOM uint32_t X : 16; /*!< [31..16] Pacing Timer Dividend. Specifies the X value for the - (X/Y) fractional timer. */ - } bit; - } TIMER0; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000424) Pacing (X/Y) Fractional Timer + __IOM uint32_t TIMER1; /*!< (@ 0x00000424) Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. */ - - struct { - __IOM uint32_t Y : 16; /*!< [15..0] Pacing Timer Divisor. Specifies the Y value for the - (X/Y) fractional timer. */ - __IOM uint32_t X : 16; /*!< [31..16] Pacing Timer Dividend. Specifies the X value for the - (X/Y) fractional timer. */ - } bit; - } TIMER1; - __IM uint32_t RESERVED2[2]; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000430) Trigger one or more channels simultaneously */ - - struct { - __IOM uint32_t MULTI_CHAN_TRIGGER : 16; /*!< [15..0] Each bit in this register corresponds to a DMA channel. - Writing a 1 to the relevant bit is the same as writing - to that channel's trigger register; the channel will start - if it is currently enabled and not already busy. */ - uint32_t : 16; - } bit; - } MULTI_CHAN_TRIGGER; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000434) Sniffer Control */ - - struct { - __IOM uint32_t EN : 1; /*!< [0..0] Enable sniffer */ - __IOM uint32_t DMACH : 4; /*!< [4..1] DMA channel for Sniffer to observe */ - __IOM uint32_t CALC : 4; /*!< [8..5] CALC */ - __IOM uint32_t BSWAP : 1; /*!< [9..9] Locally perform a byte reverse on the sniffed data, before - feeding into checksum. - - Note that the sniff hardware is downstream of the DMA channel - byteswap performed in the read master: if channel CTRL_BSWAP - and SNIFF_CTRL_BSWAP are both enabled, their effects cancel - from the sniffer's point of view. */ - __IOM uint32_t OUT_REV : 1; /*!< [10..10] If set, the result appears bit-reversed when read. - This does not affect the way the checksum is calculated; - the result is transformed on-the-fly between the result - register and the bus. */ - __IOM uint32_t OUT_INV : 1; /*!< [11..11] If set, the result appears inverted (bitwise complement) - when read. This does not affect the way the checksum is - calculated; the result is transformed on-the-fly between - the result register and the bus. */ - uint32_t : 20; - } bit; - } SNIFF_CTRL; + __IOM uint32_t TIMER2; /*!< (@ 0x00000428) Pacing (X/Y) Fractional Timer + The pacing timer produces TREQ assertions + at a rate set by ((X/Y) * sys_clk). This + equation is evaluated every sys_clk cycles + and therefore can only generate TREQs at + a rate of 1 per sys_clk (i.e. permanent + TREQ) or less. */ + __IOM uint32_t TIMER3; /*!< (@ 0x0000042C) Pacing (X/Y) Fractional Timer + The pacing timer produces TREQ assertions + at a rate set by ((X/Y) * sys_clk). This + equation is evaluated every sys_clk cycles + and therefore can only generate TREQs at + a rate of 1 per sys_clk (i.e. permanent + TREQ) or less. */ + __IOM uint32_t MULTI_CHAN_TRIGGER; /*!< (@ 0x00000430) Trigger one or more channels simultaneously */ + __IOM uint32_t SNIFF_CTRL; /*!< (@ 0x00000434) Sniffer Control */ __IOM uint32_t SNIFF_DATA; /*!< (@ 0x00000438) Data accumulator for sniff hardware Write an initial seed value here before starting a DMA transfer on the channel indicated @@ -11443,243 +2172,320 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur from the indicated channel. Once the channel completes, the final result can be read from this register. */ - __IM uint32_t RESERVED3; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000440) Debug RAF, WAF, TDF levels */ - - struct { - __IM uint32_t TDF_LVL : 8; /*!< [7..0] Current Transfer-Data-FIFO fill level */ - __IM uint32_t WAF_LVL : 8; /*!< [15..8] Current Write-Address-FIFO fill level */ - __IM uint32_t RAF_LVL : 8; /*!< [23..16] Current Read-Address-FIFO fill level */ - uint32_t : 8; - } bit; - } FIFO_LEVELS; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000444) Abort an in-progress transfer sequence on one + __IM uint32_t RESERVED2; + __IOM uint32_t FIFO_LEVELS; /*!< (@ 0x00000440) Debug RAF, WAF, TDF levels */ + __IOM uint32_t CHAN_ABORT; /*!< (@ 0x00000444) Abort an in-progress transfer sequence on one or more channels */ - - struct { - __IOM uint32_t CHAN_ABORT : 16; /*!< [15..0] Each bit corresponds to a channel. Writing a 1 aborts - whatever transfer sequence is in progress on that channel. - The bit will remain high until any in-flight transfers - have been flushed through the address and data FIFOs. - - After writing, this register must be polled until it returns - all-zero. Until this point, it is unsafe to restart the - channel. */ - uint32_t : 16; - } bit; - } CHAN_ABORT; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000448) The number of channels this DMA instance is equipped + __IOM uint32_t N_CHANNELS; /*!< (@ 0x00000448) The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. */ - - struct { - __IM uint32_t N_CHANNELS : 5; /*!< [4..0] N_CHANNELS */ - uint32_t : 27; - } bit; - } N_CHANNELS; - __IM uint32_t RESERVED4[237]; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000800) Read: get channel DREQ counter (i.e. how many + __IM uint32_t RESERVED3[237]; + __IOM uint32_t CH0_DBG_CTDREQ; /*!< (@ 0x00000800) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. */ - - struct { - __IM uint32_t CH0_DBG_CTDREQ : 6; /*!< [5..0] CH0_DBG_CTDREQ */ - uint32_t : 26; - } bit; - } CH0_DBG_CTDREQ; __IM uint32_t CH0_DBG_TCR; /*!< (@ 0x00000804) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer */ - __IM uint32_t RESERVED5[14]; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000840) Read: get channel DREQ counter (i.e. how many + __IM uint32_t RESERVED4[14]; + __IOM uint32_t CH1_DBG_CTDREQ; /*!< (@ 0x00000840) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. */ - - struct { - __IM uint32_t CH1_DBG_CTDREQ : 6; /*!< [5..0] CH1_DBG_CTDREQ */ - uint32_t : 26; - } bit; - } CH1_DBG_CTDREQ; __IM uint32_t CH1_DBG_TCR; /*!< (@ 0x00000844) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer */ - __IM uint32_t RESERVED6[14]; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000880) Read: get channel DREQ counter (i.e. how many + __IM uint32_t RESERVED5[14]; + __IOM uint32_t CH2_DBG_CTDREQ; /*!< (@ 0x00000880) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. */ - - struct { - __IM uint32_t CH2_DBG_CTDREQ : 6; /*!< [5..0] CH2_DBG_CTDREQ */ - uint32_t : 26; - } bit; - } CH2_DBG_CTDREQ; __IM uint32_t CH2_DBG_TCR; /*!< (@ 0x00000884) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer */ - __IM uint32_t RESERVED7[14]; - - union { - __IOM uint32_t reg; /*!< (@ 0x000008C0) Read: get channel DREQ counter (i.e. how many + __IM uint32_t RESERVED6[14]; + __IOM uint32_t CH3_DBG_CTDREQ; /*!< (@ 0x000008C0) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. */ - - struct { - __IM uint32_t CH3_DBG_CTDREQ : 6; /*!< [5..0] CH3_DBG_CTDREQ */ - uint32_t : 26; - } bit; - } CH3_DBG_CTDREQ; __IM uint32_t CH3_DBG_TCR; /*!< (@ 0x000008C4) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer */ - __IM uint32_t RESERVED8[14]; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000900) Read: get channel DREQ counter (i.e. how many + __IM uint32_t RESERVED7[14]; + __IOM uint32_t CH4_DBG_CTDREQ; /*!< (@ 0x00000900) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. */ - - struct { - __IM uint32_t CH4_DBG_CTDREQ : 6; /*!< [5..0] CH4_DBG_CTDREQ */ - uint32_t : 26; - } bit; - } CH4_DBG_CTDREQ; __IM uint32_t CH4_DBG_TCR; /*!< (@ 0x00000904) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer */ - __IM uint32_t RESERVED9[14]; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000940) Read: get channel DREQ counter (i.e. how many + __IM uint32_t RESERVED8[14]; + __IOM uint32_t CH5_DBG_CTDREQ; /*!< (@ 0x00000940) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. */ - - struct { - __IM uint32_t CH5_DBG_CTDREQ : 6; /*!< [5..0] CH5_DBG_CTDREQ */ - uint32_t : 26; - } bit; - } CH5_DBG_CTDREQ; __IM uint32_t CH5_DBG_TCR; /*!< (@ 0x00000944) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer */ - __IM uint32_t RESERVED10[14]; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000980) Read: get channel DREQ counter (i.e. how many + __IM uint32_t RESERVED9[14]; + __IOM uint32_t CH6_DBG_CTDREQ; /*!< (@ 0x00000980) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. */ - - struct { - __IM uint32_t CH6_DBG_CTDREQ : 6; /*!< [5..0] CH6_DBG_CTDREQ */ - uint32_t : 26; - } bit; - } CH6_DBG_CTDREQ; __IM uint32_t CH6_DBG_TCR; /*!< (@ 0x00000984) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer */ - __IM uint32_t RESERVED11[14]; - - union { - __IOM uint32_t reg; /*!< (@ 0x000009C0) Read: get channel DREQ counter (i.e. how many + __IM uint32_t RESERVED10[14]; + __IOM uint32_t CH7_DBG_CTDREQ; /*!< (@ 0x000009C0) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. */ - - struct { - __IM uint32_t CH7_DBG_CTDREQ : 6; /*!< [5..0] CH7_DBG_CTDREQ */ - uint32_t : 26; - } bit; - } CH7_DBG_CTDREQ; __IM uint32_t CH7_DBG_TCR; /*!< (@ 0x000009C4) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer */ - __IM uint32_t RESERVED12[14]; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000A00) Read: get channel DREQ counter (i.e. how many + __IM uint32_t RESERVED11[14]; + __IOM uint32_t CH8_DBG_CTDREQ; /*!< (@ 0x00000A00) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. */ - - struct { - __IM uint32_t CH8_DBG_CTDREQ : 6; /*!< [5..0] CH8_DBG_CTDREQ */ - uint32_t : 26; - } bit; - } CH8_DBG_CTDREQ; __IM uint32_t CH8_DBG_TCR; /*!< (@ 0x00000A04) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer */ - __IM uint32_t RESERVED13[14]; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000A40) Read: get channel DREQ counter (i.e. how many + __IM uint32_t RESERVED12[14]; + __IOM uint32_t CH9_DBG_CTDREQ; /*!< (@ 0x00000A40) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. */ - - struct { - __IM uint32_t CH9_DBG_CTDREQ : 6; /*!< [5..0] CH9_DBG_CTDREQ */ - uint32_t : 26; - } bit; - } CH9_DBG_CTDREQ; __IM uint32_t CH9_DBG_TCR; /*!< (@ 0x00000A44) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer */ - __IM uint32_t RESERVED14[14]; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000A80) Read: get channel DREQ counter (i.e. how many + __IM uint32_t RESERVED13[14]; + __IOM uint32_t CH10_DBG_CTDREQ; /*!< (@ 0x00000A80) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. */ - - struct { - __IM uint32_t CH10_DBG_CTDREQ : 6; /*!< [5..0] CH10_DBG_CTDREQ */ - uint32_t : 26; - } bit; - } CH10_DBG_CTDREQ; __IM uint32_t CH10_DBG_TCR; /*!< (@ 0x00000A84) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer */ - __IM uint32_t RESERVED15[14]; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000AC0) Read: get channel DREQ counter (i.e. how many + __IM uint32_t RESERVED14[14]; + __IOM uint32_t CH11_DBG_CTDREQ; /*!< (@ 0x00000AC0) Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. */ - - struct { - __IM uint32_t CH11_DBG_CTDREQ : 6; /*!< [5..0] CH11_DBG_CTDREQ */ - uint32_t : 26; - } bit; - } CH11_DBG_CTDREQ; __IM uint32_t CH11_DBG_TCR; /*!< (@ 0x00000AC4) Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer */ } DMA_Type; /*!< Size = 2760 (0xac8) */ +/* =========================================================================================================================== */ +/* ================ USBCTRL_DPRAM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DPRAM layout for USB device. (USBCTRL_DPRAM) + */ + +typedef struct { /*!< (@ 0x50100000) USBCTRL_DPRAM Structure */ + __IOM uint32_t SETUP_PACKET_LOW; /*!< (@ 0x00000000) Bytes 0-3 of the SETUP packet from the host. */ + __IOM uint32_t SETUP_PACKET_HIGH; /*!< (@ 0x00000004) Bytes 4-7 of the setup packet from the host. */ + __IOM uint32_t EP1_IN_CONTROL; /*!< (@ 0x00000008) EP1_IN_CONTROL */ + __IOM uint32_t EP1_OUT_CONTROL; /*!< (@ 0x0000000C) EP1_OUT_CONTROL */ + __IOM uint32_t EP2_IN_CONTROL; /*!< (@ 0x00000010) EP2_IN_CONTROL */ + __IOM uint32_t EP2_OUT_CONTROL; /*!< (@ 0x00000014) EP2_OUT_CONTROL */ + __IOM uint32_t EP3_IN_CONTROL; /*!< (@ 0x00000018) EP3_IN_CONTROL */ + __IOM uint32_t EP3_OUT_CONTROL; /*!< (@ 0x0000001C) EP3_OUT_CONTROL */ + __IOM uint32_t EP4_IN_CONTROL; /*!< (@ 0x00000020) EP4_IN_CONTROL */ + __IOM uint32_t EP4_OUT_CONTROL; /*!< (@ 0x00000024) EP4_OUT_CONTROL */ + __IOM uint32_t EP5_IN_CONTROL; /*!< (@ 0x00000028) EP5_IN_CONTROL */ + __IOM uint32_t EP5_OUT_CONTROL; /*!< (@ 0x0000002C) EP5_OUT_CONTROL */ + __IOM uint32_t EP6_IN_CONTROL; /*!< (@ 0x00000030) EP6_IN_CONTROL */ + __IOM uint32_t EP6_OUT_CONTROL; /*!< (@ 0x00000034) EP6_OUT_CONTROL */ + __IOM uint32_t EP7_IN_CONTROL; /*!< (@ 0x00000038) EP7_IN_CONTROL */ + __IOM uint32_t EP7_OUT_CONTROL; /*!< (@ 0x0000003C) EP7_OUT_CONTROL */ + __IOM uint32_t EP8_IN_CONTROL; /*!< (@ 0x00000040) EP8_IN_CONTROL */ + __IOM uint32_t EP8_OUT_CONTROL; /*!< (@ 0x00000044) EP8_OUT_CONTROL */ + __IOM uint32_t EP9_IN_CONTROL; /*!< (@ 0x00000048) EP9_IN_CONTROL */ + __IOM uint32_t EP9_OUT_CONTROL; /*!< (@ 0x0000004C) EP9_OUT_CONTROL */ + __IOM uint32_t EP10_IN_CONTROL; /*!< (@ 0x00000050) EP10_IN_CONTROL */ + __IOM uint32_t EP10_OUT_CONTROL; /*!< (@ 0x00000054) EP10_OUT_CONTROL */ + __IOM uint32_t EP11_IN_CONTROL; /*!< (@ 0x00000058) EP11_IN_CONTROL */ + __IOM uint32_t EP11_OUT_CONTROL; /*!< (@ 0x0000005C) EP11_OUT_CONTROL */ + __IOM uint32_t EP12_IN_CONTROL; /*!< (@ 0x00000060) EP12_IN_CONTROL */ + __IOM uint32_t EP12_OUT_CONTROL; /*!< (@ 0x00000064) EP12_OUT_CONTROL */ + __IOM uint32_t EP13_IN_CONTROL; /*!< (@ 0x00000068) EP13_IN_CONTROL */ + __IOM uint32_t EP13_OUT_CONTROL; /*!< (@ 0x0000006C) EP13_OUT_CONTROL */ + __IOM uint32_t EP14_IN_CONTROL; /*!< (@ 0x00000070) EP14_IN_CONTROL */ + __IOM uint32_t EP14_OUT_CONTROL; /*!< (@ 0x00000074) EP14_OUT_CONTROL */ + __IOM uint32_t EP15_IN_CONTROL; /*!< (@ 0x00000078) EP15_IN_CONTROL */ + __IOM uint32_t EP15_OUT_CONTROL; /*!< (@ 0x0000007C) EP15_OUT_CONTROL */ + __IOM uint32_t EP0_IN_BUFFER_CONTROL; /*!< (@ 0x00000080) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP0_OUT_BUFFER_CONTROL; /*!< (@ 0x00000084) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP1_IN_BUFFER_CONTROL; /*!< (@ 0x00000088) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP1_OUT_BUFFER_CONTROL; /*!< (@ 0x0000008C) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP2_IN_BUFFER_CONTROL; /*!< (@ 0x00000090) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP2_OUT_BUFFER_CONTROL; /*!< (@ 0x00000094) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP3_IN_BUFFER_CONTROL; /*!< (@ 0x00000098) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP3_OUT_BUFFER_CONTROL; /*!< (@ 0x0000009C) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP4_IN_BUFFER_CONTROL; /*!< (@ 0x000000A0) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP4_OUT_BUFFER_CONTROL; /*!< (@ 0x000000A4) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP5_IN_BUFFER_CONTROL; /*!< (@ 0x000000A8) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP5_OUT_BUFFER_CONTROL; /*!< (@ 0x000000AC) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP6_IN_BUFFER_CONTROL; /*!< (@ 0x000000B0) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP6_OUT_BUFFER_CONTROL; /*!< (@ 0x000000B4) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP7_IN_BUFFER_CONTROL; /*!< (@ 0x000000B8) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP7_OUT_BUFFER_CONTROL; /*!< (@ 0x000000BC) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP8_IN_BUFFER_CONTROL; /*!< (@ 0x000000C0) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP8_OUT_BUFFER_CONTROL; /*!< (@ 0x000000C4) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP9_IN_BUFFER_CONTROL; /*!< (@ 0x000000C8) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP9_OUT_BUFFER_CONTROL; /*!< (@ 0x000000CC) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP10_IN_BUFFER_CONTROL; /*!< (@ 0x000000D0) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP10_OUT_BUFFER_CONTROL; /*!< (@ 0x000000D4) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP11_IN_BUFFER_CONTROL; /*!< (@ 0x000000D8) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP11_OUT_BUFFER_CONTROL; /*!< (@ 0x000000DC) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP12_IN_BUFFER_CONTROL; /*!< (@ 0x000000E0) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP12_OUT_BUFFER_CONTROL; /*!< (@ 0x000000E4) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP13_IN_BUFFER_CONTROL; /*!< (@ 0x000000E8) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP13_OUT_BUFFER_CONTROL; /*!< (@ 0x000000EC) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP14_IN_BUFFER_CONTROL; /*!< (@ 0x000000F0) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP14_OUT_BUFFER_CONTROL; /*!< (@ 0x000000F4) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP15_IN_BUFFER_CONTROL; /*!< (@ 0x000000F8) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ + __IOM uint32_t EP15_OUT_BUFFER_CONTROL; /*!< (@ 0x000000FC) Buffer control for both buffers of an endpoint. + Fields ending in a _1 are for buffer 1. + Fields ending in a _0 are for buffer 0. + Buffer 1 controls are only valid if the + endpoint is in double buffered mode. */ +} USBCTRL_DPRAM_Type; /*!< Size = 256 (0x100) */ + + + /* =========================================================================================================================== */ /* ================ USBCTRL_REGS ================ */ /* =========================================================================================================================== */ @@ -11690,922 +2496,88 @@ typedef struct { /*!< (@ 0x50000000) DMA Structur */ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS Structure */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000000) Device address and endpoint control */ - - struct { - __IOM uint32_t ADDRESS : 7; /*!< [6..0] In device mode, the address that the device should respond - to. Set in response to a SET_ADDR setup packet from the - host. In host mode set to the address of the device to - communicate with. */ - uint32_t : 9; - __IOM uint32_t ENDPOINT : 4; /*!< [19..16] Device endpoint to send data to. Only valid for HOST - mode. */ - uint32_t : 12; - } bit; - } ADDR_ENDP; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Interrupt endpoint 1. Only valid for HOST mode. */ - - struct { - __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ - uint32_t : 9; - __IOM uint32_t ENDPOINT : 4; /*!< [19..16] Endpoint number of the interrupt endpoint */ - uint32_t : 5; - __IOM uint32_t INTEP_DIR : 1; /*!< [25..25] Direction of the interrupt endpoint. In=0, Out=1 */ - __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device - on a full speed hub) */ - uint32_t : 5; - } bit; - } ADDR_ENDP1; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000008) Interrupt endpoint 2. Only valid for HOST mode. */ - - struct { - __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ - uint32_t : 9; - __IOM uint32_t ENDPOINT : 4; /*!< [19..16] Endpoint number of the interrupt endpoint */ - uint32_t : 5; - __IOM uint32_t INTEP_DIR : 1; /*!< [25..25] Direction of the interrupt endpoint. In=0, Out=1 */ - __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device - on a full speed hub) */ - uint32_t : 5; - } bit; - } ADDR_ENDP2; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) Interrupt endpoint 3. Only valid for HOST mode. */ - - struct { - __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ - uint32_t : 9; - __IOM uint32_t ENDPOINT : 4; /*!< [19..16] Endpoint number of the interrupt endpoint */ - uint32_t : 5; - __IOM uint32_t INTEP_DIR : 1; /*!< [25..25] Direction of the interrupt endpoint. In=0, Out=1 */ - __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device - on a full speed hub) */ - uint32_t : 5; - } bit; - } ADDR_ENDP3; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000010) Interrupt endpoint 4. Only valid for HOST mode. */ - - struct { - __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ - uint32_t : 9; - __IOM uint32_t ENDPOINT : 4; /*!< [19..16] Endpoint number of the interrupt endpoint */ - uint32_t : 5; - __IOM uint32_t INTEP_DIR : 1; /*!< [25..25] Direction of the interrupt endpoint. In=0, Out=1 */ - __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device - on a full speed hub) */ - uint32_t : 5; - } bit; - } ADDR_ENDP4; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000014) Interrupt endpoint 5. Only valid for HOST mode. */ - - struct { - __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ - uint32_t : 9; - __IOM uint32_t ENDPOINT : 4; /*!< [19..16] Endpoint number of the interrupt endpoint */ - uint32_t : 5; - __IOM uint32_t INTEP_DIR : 1; /*!< [25..25] Direction of the interrupt endpoint. In=0, Out=1 */ - __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device - on a full speed hub) */ - uint32_t : 5; - } bit; - } ADDR_ENDP5; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000018) Interrupt endpoint 6. Only valid for HOST mode. */ - - struct { - __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ - uint32_t : 9; - __IOM uint32_t ENDPOINT : 4; /*!< [19..16] Endpoint number of the interrupt endpoint */ - uint32_t : 5; - __IOM uint32_t INTEP_DIR : 1; /*!< [25..25] Direction of the interrupt endpoint. In=0, Out=1 */ - __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device - on a full speed hub) */ - uint32_t : 5; - } bit; - } ADDR_ENDP6; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) Interrupt endpoint 7. Only valid for HOST mode. */ - - struct { - __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ - uint32_t : 9; - __IOM uint32_t ENDPOINT : 4; /*!< [19..16] Endpoint number of the interrupt endpoint */ - uint32_t : 5; - __IOM uint32_t INTEP_DIR : 1; /*!< [25..25] Direction of the interrupt endpoint. In=0, Out=1 */ - __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device - on a full speed hub) */ - uint32_t : 5; - } bit; - } ADDR_ENDP7; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000020) Interrupt endpoint 8. Only valid for HOST mode. */ - - struct { - __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ - uint32_t : 9; - __IOM uint32_t ENDPOINT : 4; /*!< [19..16] Endpoint number of the interrupt endpoint */ - uint32_t : 5; - __IOM uint32_t INTEP_DIR : 1; /*!< [25..25] Direction of the interrupt endpoint. In=0, Out=1 */ - __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device - on a full speed hub) */ - uint32_t : 5; - } bit; - } ADDR_ENDP8; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000024) Interrupt endpoint 9. Only valid for HOST mode. */ - - struct { - __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ - uint32_t : 9; - __IOM uint32_t ENDPOINT : 4; /*!< [19..16] Endpoint number of the interrupt endpoint */ - uint32_t : 5; - __IOM uint32_t INTEP_DIR : 1; /*!< [25..25] Direction of the interrupt endpoint. In=0, Out=1 */ - __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device - on a full speed hub) */ - uint32_t : 5; - } bit; - } ADDR_ENDP9; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000028) Interrupt endpoint 10. Only valid for HOST mode. */ - - struct { - __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ - uint32_t : 9; - __IOM uint32_t ENDPOINT : 4; /*!< [19..16] Endpoint number of the interrupt endpoint */ - uint32_t : 5; - __IOM uint32_t INTEP_DIR : 1; /*!< [25..25] Direction of the interrupt endpoint. In=0, Out=1 */ - __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device - on a full speed hub) */ - uint32_t : 5; - } bit; - } ADDR_ENDP10; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000002C) Interrupt endpoint 11. Only valid for HOST mode. */ - - struct { - __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ - uint32_t : 9; - __IOM uint32_t ENDPOINT : 4; /*!< [19..16] Endpoint number of the interrupt endpoint */ - uint32_t : 5; - __IOM uint32_t INTEP_DIR : 1; /*!< [25..25] Direction of the interrupt endpoint. In=0, Out=1 */ - __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device - on a full speed hub) */ - uint32_t : 5; - } bit; - } ADDR_ENDP11; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000030) Interrupt endpoint 12. Only valid for HOST mode. */ - - struct { - __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ - uint32_t : 9; - __IOM uint32_t ENDPOINT : 4; /*!< [19..16] Endpoint number of the interrupt endpoint */ - uint32_t : 5; - __IOM uint32_t INTEP_DIR : 1; /*!< [25..25] Direction of the interrupt endpoint. In=0, Out=1 */ - __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device - on a full speed hub) */ - uint32_t : 5; - } bit; - } ADDR_ENDP12; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000034) Interrupt endpoint 13. Only valid for HOST mode. */ - - struct { - __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ - uint32_t : 9; - __IOM uint32_t ENDPOINT : 4; /*!< [19..16] Endpoint number of the interrupt endpoint */ - uint32_t : 5; - __IOM uint32_t INTEP_DIR : 1; /*!< [25..25] Direction of the interrupt endpoint. In=0, Out=1 */ - __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device - on a full speed hub) */ - uint32_t : 5; - } bit; - } ADDR_ENDP13; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000038) Interrupt endpoint 14. Only valid for HOST mode. */ - - struct { - __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ - uint32_t : 9; - __IOM uint32_t ENDPOINT : 4; /*!< [19..16] Endpoint number of the interrupt endpoint */ - uint32_t : 5; - __IOM uint32_t INTEP_DIR : 1; /*!< [25..25] Direction of the interrupt endpoint. In=0, Out=1 */ - __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device - on a full speed hub) */ - uint32_t : 5; - } bit; - } ADDR_ENDP14; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000003C) Interrupt endpoint 15. Only valid for HOST mode. */ - - struct { - __IOM uint32_t ADDRESS : 7; /*!< [6..0] Device address */ - uint32_t : 9; - __IOM uint32_t ENDPOINT : 4; /*!< [19..16] Endpoint number of the interrupt endpoint */ - uint32_t : 5; - __IOM uint32_t INTEP_DIR : 1; /*!< [25..25] Direction of the interrupt endpoint. In=0, Out=1 */ - __IOM uint32_t INTEP_PREAMBLE : 1; /*!< [26..26] Interrupt EP requires preamble (is a low speed device - on a full speed hub) */ - uint32_t : 5; - } bit; - } ADDR_ENDP15; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000040) Main control register */ - - struct { - __IOM uint32_t CONTROLLER_EN : 1; /*!< [0..0] Enable controller */ - __IOM uint32_t HOST_NDEVICE : 1; /*!< [1..1] Device mode = 0, Host mode = 1 */ - uint32_t : 29; - __IOM uint32_t SIM_TIMING : 1; /*!< [31..31] Reduced timings for simulation */ - } bit; - } MAIN_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000044) Set the SOF (Start of Frame) frame number in + __IOM uint32_t ADDR_ENDP; /*!< (@ 0x00000000) Device address and endpoint control */ + __IOM uint32_t ADDR_ENDP1; /*!< (@ 0x00000004) Interrupt endpoint 1. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP2; /*!< (@ 0x00000008) Interrupt endpoint 2. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP3; /*!< (@ 0x0000000C) Interrupt endpoint 3. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP4; /*!< (@ 0x00000010) Interrupt endpoint 4. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP5; /*!< (@ 0x00000014) Interrupt endpoint 5. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP6; /*!< (@ 0x00000018) Interrupt endpoint 6. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP7; /*!< (@ 0x0000001C) Interrupt endpoint 7. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP8; /*!< (@ 0x00000020) Interrupt endpoint 8. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP9; /*!< (@ 0x00000024) Interrupt endpoint 9. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP10; /*!< (@ 0x00000028) Interrupt endpoint 10. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP11; /*!< (@ 0x0000002C) Interrupt endpoint 11. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP12; /*!< (@ 0x00000030) Interrupt endpoint 12. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP13; /*!< (@ 0x00000034) Interrupt endpoint 13. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP14; /*!< (@ 0x00000038) Interrupt endpoint 14. Only valid for HOST mode. */ + __IOM uint32_t ADDR_ENDP15; /*!< (@ 0x0000003C) Interrupt endpoint 15. Only valid for HOST mode. */ + __IOM uint32_t MAIN_CTRL; /*!< (@ 0x00000040) Main control register */ + __IOM uint32_t SOF_WR; /*!< (@ 0x00000044) Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. */ - - struct { - __OM uint32_t COUNT : 11; /*!< [10..0] COUNT */ - uint32_t : 21; - } bit; - } SOF_WR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000048) Read the last SOF (Start of Frame) frame number + __IOM uint32_t SOF_RD; /*!< (@ 0x00000048) Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. */ - - struct { - __IM uint32_t COUNT : 11; /*!< [10..0] COUNT */ - uint32_t : 21; - } bit; - } SOF_RD; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000004C) SIE control register */ - - struct { - __IOM uint32_t START_TRANS : 1; /*!< [0..0] Host: Start transaction */ - __IOM uint32_t SEND_SETUP : 1; /*!< [1..1] Host: Send Setup packet */ - __IOM uint32_t SEND_DATA : 1; /*!< [2..2] Host: Send transaction (OUT from host) */ - __IOM uint32_t RECEIVE_DATA : 1; /*!< [3..3] Host: Receive transaction (IN to host) */ - __IOM uint32_t STOP_TRANS : 1; /*!< [4..4] Host: Stop transaction */ - uint32_t : 1; - __IOM uint32_t PREAMBLE_EN : 1; /*!< [6..6] Host: Preable enable for LS device on FS hub */ - uint32_t : 1; - __IOM uint32_t SOF_SYNC : 1; /*!< [8..8] Host: Delay packet(s) until after SOF */ - __IOM uint32_t SOF_EN : 1; /*!< [9..9] Host: Enable SOF generation (for full speed bus) */ - __IOM uint32_t KEEP_ALIVE_EN : 1; /*!< [10..10] Host: Enable keep alive packet (for low speed bus) */ - __IOM uint32_t VBUS_EN : 1; /*!< [11..11] Host: Enable VBUS */ - __IOM uint32_t RESUME : 1; /*!< [12..12] Device: Remote wakeup. Device can initiate its own - resume after suspend. */ - __IOM uint32_t RESET_BUS : 1; /*!< [13..13] Host: Reset bus */ - uint32_t : 1; - __IOM uint32_t PULLDOWN_EN : 1; /*!< [15..15] Host: Enable pull down resistors */ - __IOM uint32_t PULLUP_EN : 1; /*!< [16..16] Device: Enable pull up resistor */ - __IOM uint32_t RPU_OPT : 1; /*!< [17..17] Device: Pull-up strength (0=1K2, 1=2k3) */ - __IOM uint32_t TRANSCEIVER_PD : 1; /*!< [18..18] Power down bus transceiver */ - uint32_t : 5; - __IOM uint32_t DIRECT_DM : 1; /*!< [24..24] Direct control of DM */ - __IOM uint32_t DIRECT_DP : 1; /*!< [25..25] Direct control of DP */ - __IOM uint32_t DIRECT_EN : 1; /*!< [26..26] Direct bus drive enable */ - __IOM uint32_t EP0_INT_NAK : 1; /*!< [27..27] Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends - a NAK */ - __IOM uint32_t EP0_INT_2BUF : 1; /*!< [28..28] Device: Set bit in BUFF_STATUS for every 2 buffers - completed on EP0 */ - __IOM uint32_t EP0_INT_1BUF : 1; /*!< [29..29] Device: Set bit in BUFF_STATUS for every buffer completed - on EP0 */ - __IOM uint32_t EP0_DOUBLE_BUF : 1; /*!< [30..30] Device: EP0 single buffered = 0, double buffered = - 1 */ - __IOM uint32_t EP0_INT_STALL : 1; /*!< [31..31] Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends - a STALL */ - } bit; - } SIE_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000050) SIE status register */ - - struct { - __IM uint32_t VBUS_DETECTED : 1; /*!< [0..0] Device: VBUS Detected */ - uint32_t : 1; - __IM uint32_t LINE_STATE : 2; /*!< [3..2] USB bus line state */ - __IM uint32_t SUSPENDED : 1; /*!< [4..4] Bus in suspended state. Valid for device and host. Host - and device will go into suspend if neither Keep Alive / - SOF frames are enabled. */ - uint32_t : 3; - __IM uint32_t SPEED : 2; /*!< [9..8] Host: device speed. Disconnected = 00, LS = 01, FS = - 10 */ - __IM uint32_t VBUS_OVER_CURR : 1; /*!< [10..10] VBUS over current detected */ - __IOM uint32_t RESUME : 1; /*!< [11..11] Host: Device has initiated a remote resume. Device: - host has initiated a resume. */ - uint32_t : 4; - __IM uint32_t CONNECTED : 1; /*!< [16..16] Device: connected */ - __IOM uint32_t SETUP_REC : 1; /*!< [17..17] Device: Setup packet received */ - __IOM uint32_t TRANS_COMPLETE : 1; /*!< [18..18] Transaction complete. - - Raised by device if: - - * An IN or OUT packet is sent with the `LAST_BUFF` bit - set in the buffer control register - - Raised by host if: - - * A setup packet is sent when no data in or data out transaction - follows * An IN packet is received and the `LAST_BUFF` - bit is set in the buffer control register * An IN packet - is received with zero length * An OUT packet is sent and - the `LAST_BUFF` bit is set */ - __IOM uint32_t BUS_RESET : 1; /*!< [19..19] Device: bus reset received */ - uint32_t : 4; - __IOM uint32_t CRC_ERROR : 1; /*!< [24..24] CRC Error. Raised by the Serial RX engine. */ - __IOM uint32_t BIT_STUFF_ERROR : 1; /*!< [25..25] Bit Stuff Error. Raised by the Serial RX engine. */ - __IOM uint32_t RX_OVERFLOW : 1; /*!< [26..26] RX overflow is raised by the Serial RX engine if the - incoming data is too fast. */ - __IOM uint32_t RX_TIMEOUT : 1; /*!< [27..27] RX timeout is raised by both the host and device if - an ACK is not received in the maximum time specified by - the USB spec. */ - __IOM uint32_t NAK_REC : 1; /*!< [28..28] Host: NAK received */ - __IOM uint32_t STALL_REC : 1; /*!< [29..29] Host: STALL received */ - __IOM uint32_t ACK_REC : 1; /*!< [30..30] ACK received. Raised by both host and device. */ - __IOM uint32_t DATA_SEQ_ERROR : 1; /*!< [31..31] Data Sequence Error. - - The device can raise a sequence error in the following - conditions: - - * A SETUP packet is received followed by a DATA1 packet - (data phase should always be DATA0) * An OUT packet is - received from the host but doesn't match the data pid in - the buffer control register read from DPSRAM - - The host can raise a data sequence error in the following - conditions: - - * An IN packet from the device has the wrong data PID */ - } bit; - } SIE_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000054) interrupt endpoint control register */ - - struct { - uint32_t : 1; - __IOM uint32_t INT_EP_ACTIVE : 15; /*!< [15..1] Host: Enable interrupt endpoint 1 -> 15 */ - uint32_t : 16; - } bit; - } INT_EP_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000058) Buffer status register. A bit set here indicates + __IOM uint32_t SIE_CTRL; /*!< (@ 0x0000004C) SIE control register */ + __IOM uint32_t SIE_STATUS; /*!< (@ 0x00000050) SIE status register */ + __IOM uint32_t INT_EP_CTRL; /*!< (@ 0x00000054) interrupt endpoint control register */ + __IOM uint32_t BUFF_STATUS; /*!< (@ 0x00000058) Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle. */ - - struct { - __IM uint32_t EP0_IN : 1; /*!< [0..0] EP0_IN */ - __IM uint32_t EP0_OUT : 1; /*!< [1..1] EP0_OUT */ - __IM uint32_t EP1_IN : 1; /*!< [2..2] EP1_IN */ - __IM uint32_t EP1_OUT : 1; /*!< [3..3] EP1_OUT */ - __IM uint32_t EP2_IN : 1; /*!< [4..4] EP2_IN */ - __IM uint32_t EP2_OUT : 1; /*!< [5..5] EP2_OUT */ - __IM uint32_t EP3_IN : 1; /*!< [6..6] EP3_IN */ - __IM uint32_t EP3_OUT : 1; /*!< [7..7] EP3_OUT */ - __IM uint32_t EP4_IN : 1; /*!< [8..8] EP4_IN */ - __IM uint32_t EP4_OUT : 1; /*!< [9..9] EP4_OUT */ - __IM uint32_t EP5_IN : 1; /*!< [10..10] EP5_IN */ - __IM uint32_t EP5_OUT : 1; /*!< [11..11] EP5_OUT */ - __IM uint32_t EP6_IN : 1; /*!< [12..12] EP6_IN */ - __IM uint32_t EP6_OUT : 1; /*!< [13..13] EP6_OUT */ - __IM uint32_t EP7_IN : 1; /*!< [14..14] EP7_IN */ - __IM uint32_t EP7_OUT : 1; /*!< [15..15] EP7_OUT */ - __IM uint32_t EP8_IN : 1; /*!< [16..16] EP8_IN */ - __IM uint32_t EP8_OUT : 1; /*!< [17..17] EP8_OUT */ - __IM uint32_t EP9_IN : 1; /*!< [18..18] EP9_IN */ - __IM uint32_t EP9_OUT : 1; /*!< [19..19] EP9_OUT */ - __IM uint32_t EP10_IN : 1; /*!< [20..20] EP10_IN */ - __IM uint32_t EP10_OUT : 1; /*!< [21..21] EP10_OUT */ - __IM uint32_t EP11_IN : 1; /*!< [22..22] EP11_IN */ - __IM uint32_t EP11_OUT : 1; /*!< [23..23] EP11_OUT */ - __IM uint32_t EP12_IN : 1; /*!< [24..24] EP12_IN */ - __IM uint32_t EP12_OUT : 1; /*!< [25..25] EP12_OUT */ - __IM uint32_t EP13_IN : 1; /*!< [26..26] EP13_IN */ - __IM uint32_t EP13_OUT : 1; /*!< [27..27] EP13_OUT */ - __IM uint32_t EP14_IN : 1; /*!< [28..28] EP14_IN */ - __IM uint32_t EP14_OUT : 1; /*!< [29..29] EP14_OUT */ - __IM uint32_t EP15_IN : 1; /*!< [30..30] EP15_IN */ - __IM uint32_t EP15_OUT : 1; /*!< [31..31] EP15_OUT */ - } bit; - } BUFF_STATUS; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000005C) Which of the double buffers should be handled. + __IOM uint32_t BUFF_CPU_SHOULD_HANDLE; /*!< (@ 0x0000005C) Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. */ - - struct { - __IM uint32_t EP0_IN : 1; /*!< [0..0] EP0_IN */ - __IM uint32_t EP0_OUT : 1; /*!< [1..1] EP0_OUT */ - __IM uint32_t EP1_IN : 1; /*!< [2..2] EP1_IN */ - __IM uint32_t EP1_OUT : 1; /*!< [3..3] EP1_OUT */ - __IM uint32_t EP2_IN : 1; /*!< [4..4] EP2_IN */ - __IM uint32_t EP2_OUT : 1; /*!< [5..5] EP2_OUT */ - __IM uint32_t EP3_IN : 1; /*!< [6..6] EP3_IN */ - __IM uint32_t EP3_OUT : 1; /*!< [7..7] EP3_OUT */ - __IM uint32_t EP4_IN : 1; /*!< [8..8] EP4_IN */ - __IM uint32_t EP4_OUT : 1; /*!< [9..9] EP4_OUT */ - __IM uint32_t EP5_IN : 1; /*!< [10..10] EP5_IN */ - __IM uint32_t EP5_OUT : 1; /*!< [11..11] EP5_OUT */ - __IM uint32_t EP6_IN : 1; /*!< [12..12] EP6_IN */ - __IM uint32_t EP6_OUT : 1; /*!< [13..13] EP6_OUT */ - __IM uint32_t EP7_IN : 1; /*!< [14..14] EP7_IN */ - __IM uint32_t EP7_OUT : 1; /*!< [15..15] EP7_OUT */ - __IM uint32_t EP8_IN : 1; /*!< [16..16] EP8_IN */ - __IM uint32_t EP8_OUT : 1; /*!< [17..17] EP8_OUT */ - __IM uint32_t EP9_IN : 1; /*!< [18..18] EP9_IN */ - __IM uint32_t EP9_OUT : 1; /*!< [19..19] EP9_OUT */ - __IM uint32_t EP10_IN : 1; /*!< [20..20] EP10_IN */ - __IM uint32_t EP10_OUT : 1; /*!< [21..21] EP10_OUT */ - __IM uint32_t EP11_IN : 1; /*!< [22..22] EP11_IN */ - __IM uint32_t EP11_OUT : 1; /*!< [23..23] EP11_OUT */ - __IM uint32_t EP12_IN : 1; /*!< [24..24] EP12_IN */ - __IM uint32_t EP12_OUT : 1; /*!< [25..25] EP12_OUT */ - __IM uint32_t EP13_IN : 1; /*!< [26..26] EP13_IN */ - __IM uint32_t EP13_OUT : 1; /*!< [27..27] EP13_OUT */ - __IM uint32_t EP14_IN : 1; /*!< [28..28] EP14_IN */ - __IM uint32_t EP14_OUT : 1; /*!< [29..29] EP14_OUT */ - __IM uint32_t EP15_IN : 1; /*!< [30..30] EP15_IN */ - __IM uint32_t EP15_OUT : 1; /*!< [31..31] EP15_OUT */ - } bit; - } BUFF_CPU_SHOULD_HANDLE; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000060) Device only: Can be set to ignore the buffer + __IOM uint32_t EP_ABORT; /*!< (@ 0x00000060) Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register. */ - - struct { - __IOM uint32_t EP0_IN : 1; /*!< [0..0] EP0_IN */ - __IOM uint32_t EP0_OUT : 1; /*!< [1..1] EP0_OUT */ - __IOM uint32_t EP1_IN : 1; /*!< [2..2] EP1_IN */ - __IOM uint32_t EP1_OUT : 1; /*!< [3..3] EP1_OUT */ - __IOM uint32_t EP2_IN : 1; /*!< [4..4] EP2_IN */ - __IOM uint32_t EP2_OUT : 1; /*!< [5..5] EP2_OUT */ - __IOM uint32_t EP3_IN : 1; /*!< [6..6] EP3_IN */ - __IOM uint32_t EP3_OUT : 1; /*!< [7..7] EP3_OUT */ - __IOM uint32_t EP4_IN : 1; /*!< [8..8] EP4_IN */ - __IOM uint32_t EP4_OUT : 1; /*!< [9..9] EP4_OUT */ - __IOM uint32_t EP5_IN : 1; /*!< [10..10] EP5_IN */ - __IOM uint32_t EP5_OUT : 1; /*!< [11..11] EP5_OUT */ - __IOM uint32_t EP6_IN : 1; /*!< [12..12] EP6_IN */ - __IOM uint32_t EP6_OUT : 1; /*!< [13..13] EP6_OUT */ - __IOM uint32_t EP7_IN : 1; /*!< [14..14] EP7_IN */ - __IOM uint32_t EP7_OUT : 1; /*!< [15..15] EP7_OUT */ - __IOM uint32_t EP8_IN : 1; /*!< [16..16] EP8_IN */ - __IOM uint32_t EP8_OUT : 1; /*!< [17..17] EP8_OUT */ - __IOM uint32_t EP9_IN : 1; /*!< [18..18] EP9_IN */ - __IOM uint32_t EP9_OUT : 1; /*!< [19..19] EP9_OUT */ - __IOM uint32_t EP10_IN : 1; /*!< [20..20] EP10_IN */ - __IOM uint32_t EP10_OUT : 1; /*!< [21..21] EP10_OUT */ - __IOM uint32_t EP11_IN : 1; /*!< [22..22] EP11_IN */ - __IOM uint32_t EP11_OUT : 1; /*!< [23..23] EP11_OUT */ - __IOM uint32_t EP12_IN : 1; /*!< [24..24] EP12_IN */ - __IOM uint32_t EP12_OUT : 1; /*!< [25..25] EP12_OUT */ - __IOM uint32_t EP13_IN : 1; /*!< [26..26] EP13_IN */ - __IOM uint32_t EP13_OUT : 1; /*!< [27..27] EP13_OUT */ - __IOM uint32_t EP14_IN : 1; /*!< [28..28] EP14_IN */ - __IOM uint32_t EP14_OUT : 1; /*!< [29..29] EP14_OUT */ - __IOM uint32_t EP15_IN : 1; /*!< [30..30] EP15_IN */ - __IOM uint32_t EP15_OUT : 1; /*!< [31..31] EP15_OUT */ - } bit; - } EP_ABORT; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000064) Device only: Used in conjunction with `EP_ABORT`. + __IOM uint32_t EP_ABORT_DONE; /*!< (@ 0x00000064) Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register. */ - - struct { - __IOM uint32_t EP0_IN : 1; /*!< [0..0] EP0_IN */ - __IOM uint32_t EP0_OUT : 1; /*!< [1..1] EP0_OUT */ - __IOM uint32_t EP1_IN : 1; /*!< [2..2] EP1_IN */ - __IOM uint32_t EP1_OUT : 1; /*!< [3..3] EP1_OUT */ - __IOM uint32_t EP2_IN : 1; /*!< [4..4] EP2_IN */ - __IOM uint32_t EP2_OUT : 1; /*!< [5..5] EP2_OUT */ - __IOM uint32_t EP3_IN : 1; /*!< [6..6] EP3_IN */ - __IOM uint32_t EP3_OUT : 1; /*!< [7..7] EP3_OUT */ - __IOM uint32_t EP4_IN : 1; /*!< [8..8] EP4_IN */ - __IOM uint32_t EP4_OUT : 1; /*!< [9..9] EP4_OUT */ - __IOM uint32_t EP5_IN : 1; /*!< [10..10] EP5_IN */ - __IOM uint32_t EP5_OUT : 1; /*!< [11..11] EP5_OUT */ - __IOM uint32_t EP6_IN : 1; /*!< [12..12] EP6_IN */ - __IOM uint32_t EP6_OUT : 1; /*!< [13..13] EP6_OUT */ - __IOM uint32_t EP7_IN : 1; /*!< [14..14] EP7_IN */ - __IOM uint32_t EP7_OUT : 1; /*!< [15..15] EP7_OUT */ - __IOM uint32_t EP8_IN : 1; /*!< [16..16] EP8_IN */ - __IOM uint32_t EP8_OUT : 1; /*!< [17..17] EP8_OUT */ - __IOM uint32_t EP9_IN : 1; /*!< [18..18] EP9_IN */ - __IOM uint32_t EP9_OUT : 1; /*!< [19..19] EP9_OUT */ - __IOM uint32_t EP10_IN : 1; /*!< [20..20] EP10_IN */ - __IOM uint32_t EP10_OUT : 1; /*!< [21..21] EP10_OUT */ - __IOM uint32_t EP11_IN : 1; /*!< [22..22] EP11_IN */ - __IOM uint32_t EP11_OUT : 1; /*!< [23..23] EP11_OUT */ - __IOM uint32_t EP12_IN : 1; /*!< [24..24] EP12_IN */ - __IOM uint32_t EP12_OUT : 1; /*!< [25..25] EP12_OUT */ - __IOM uint32_t EP13_IN : 1; /*!< [26..26] EP13_IN */ - __IOM uint32_t EP13_OUT : 1; /*!< [27..27] EP13_OUT */ - __IOM uint32_t EP14_IN : 1; /*!< [28..28] EP14_IN */ - __IOM uint32_t EP14_OUT : 1; /*!< [29..29] EP14_OUT */ - __IOM uint32_t EP15_IN : 1; /*!< [30..30] EP15_IN */ - __IOM uint32_t EP15_OUT : 1; /*!< [31..31] EP15_OUT */ - } bit; - } EP_ABORT_DONE; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000068) Device: this bit must be set in conjunction with + __IOM uint32_t EP_STALL_ARM; /*!< (@ 0x00000068) Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received. */ - - struct { - __IOM uint32_t EP0_IN : 1; /*!< [0..0] EP0_IN */ - __IOM uint32_t EP0_OUT : 1; /*!< [1..1] EP0_OUT */ - uint32_t : 30; - } bit; - } EP_STALL_ARM; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000006C) Used by the host controller. Sets the wait time + __IOM uint32_t NAK_POLL; /*!< (@ 0x0000006C) Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK. */ - - struct { - __IOM uint32_t DELAY_LS : 10; /*!< [9..0] NAK polling interval for a low speed device */ - uint32_t : 6; - __IOM uint32_t DELAY_FS : 10; /*!< [25..16] NAK polling interval for a full speed device */ - uint32_t : 6; - } bit; - } NAK_POLL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000070) Device: bits are set when the `IRQ_ON_NAK` or + __IOM uint32_t EP_STATUS_STALL_NAK; /*!< (@ 0x00000070) Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register. */ - - struct { - __IOM uint32_t EP0_IN : 1; /*!< [0..0] EP0_IN */ - __IOM uint32_t EP0_OUT : 1; /*!< [1..1] EP0_OUT */ - __IOM uint32_t EP1_IN : 1; /*!< [2..2] EP1_IN */ - __IOM uint32_t EP1_OUT : 1; /*!< [3..3] EP1_OUT */ - __IOM uint32_t EP2_IN : 1; /*!< [4..4] EP2_IN */ - __IOM uint32_t EP2_OUT : 1; /*!< [5..5] EP2_OUT */ - __IOM uint32_t EP3_IN : 1; /*!< [6..6] EP3_IN */ - __IOM uint32_t EP3_OUT : 1; /*!< [7..7] EP3_OUT */ - __IOM uint32_t EP4_IN : 1; /*!< [8..8] EP4_IN */ - __IOM uint32_t EP4_OUT : 1; /*!< [9..9] EP4_OUT */ - __IOM uint32_t EP5_IN : 1; /*!< [10..10] EP5_IN */ - __IOM uint32_t EP5_OUT : 1; /*!< [11..11] EP5_OUT */ - __IOM uint32_t EP6_IN : 1; /*!< [12..12] EP6_IN */ - __IOM uint32_t EP6_OUT : 1; /*!< [13..13] EP6_OUT */ - __IOM uint32_t EP7_IN : 1; /*!< [14..14] EP7_IN */ - __IOM uint32_t EP7_OUT : 1; /*!< [15..15] EP7_OUT */ - __IOM uint32_t EP8_IN : 1; /*!< [16..16] EP8_IN */ - __IOM uint32_t EP8_OUT : 1; /*!< [17..17] EP8_OUT */ - __IOM uint32_t EP9_IN : 1; /*!< [18..18] EP9_IN */ - __IOM uint32_t EP9_OUT : 1; /*!< [19..19] EP9_OUT */ - __IOM uint32_t EP10_IN : 1; /*!< [20..20] EP10_IN */ - __IOM uint32_t EP10_OUT : 1; /*!< [21..21] EP10_OUT */ - __IOM uint32_t EP11_IN : 1; /*!< [22..22] EP11_IN */ - __IOM uint32_t EP11_OUT : 1; /*!< [23..23] EP11_OUT */ - __IOM uint32_t EP12_IN : 1; /*!< [24..24] EP12_IN */ - __IOM uint32_t EP12_OUT : 1; /*!< [25..25] EP12_OUT */ - __IOM uint32_t EP13_IN : 1; /*!< [26..26] EP13_IN */ - __IOM uint32_t EP13_OUT : 1; /*!< [27..27] EP13_OUT */ - __IOM uint32_t EP14_IN : 1; /*!< [28..28] EP14_IN */ - __IOM uint32_t EP14_OUT : 1; /*!< [29..29] EP14_OUT */ - __IOM uint32_t EP15_IN : 1; /*!< [30..30] EP15_IN */ - __IOM uint32_t EP15_OUT : 1; /*!< [31..31] EP15_OUT */ - } bit; - } EP_STATUS_STALL_NAK; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000074) Where to connect the USB controller. Should be + __IOM uint32_t USB_MUXING; /*!< (@ 0x00000074) Where to connect the USB controller. Should be to_phy by default. */ - - struct { - __IOM uint32_t TO_PHY : 1; /*!< [0..0] TO_PHY */ - __IOM uint32_t TO_EXTPHY : 1; /*!< [1..1] TO_EXTPHY */ - __IOM uint32_t TO_DIGITAL_PAD : 1; /*!< [2..2] TO_DIGITAL_PAD */ - __IOM uint32_t SOFTCON : 1; /*!< [3..3] SOFTCON */ - uint32_t : 28; - } bit; - } USB_MUXING; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000078) Overrides for the power signals in the event + __IOM uint32_t USB_PWR; /*!< (@ 0x00000078) Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value. */ - - struct { - __IOM uint32_t VBUS_EN : 1; /*!< [0..0] VBUS_EN */ - __IOM uint32_t VBUS_EN_OVERRIDE_EN : 1; /*!< [1..1] VBUS_EN_OVERRIDE_EN */ - __IOM uint32_t VBUS_DETECT : 1; /*!< [2..2] VBUS_DETECT */ - __IOM uint32_t VBUS_DETECT_OVERRIDE_EN : 1;/*!< [3..3] VBUS_DETECT_OVERRIDE_EN */ - __IOM uint32_t OVERCURR_DETECT : 1; /*!< [4..4] OVERCURR_DETECT */ - __IOM uint32_t OVERCURR_DETECT_EN : 1; /*!< [5..5] OVERCURR_DETECT_EN */ - uint32_t : 26; - } bit; - } USB_PWR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000007C) This register allows for direct control of the + __IOM uint32_t USBPHY_DIRECT; /*!< (@ 0x0000007C) This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit. */ - - struct { - __IOM uint32_t DP_PULLUP_HISEL : 1; /*!< [0..0] Enable the second DP pull up resistor. 0 - Pull = Rpu2; - 1 - Pull = Rpu1 + Rpu2 */ - __IOM uint32_t DP_PULLUP_EN : 1; /*!< [1..1] DP pull up enable */ - __IOM uint32_t DP_PULLDN_EN : 1; /*!< [2..2] DP pull down enable */ - uint32_t : 1; - __IOM uint32_t DM_PULLUP_HISEL : 1; /*!< [4..4] Enable the second DM pull up resistor. 0 - Pull = Rpu2; - 1 - Pull = Rpu1 + Rpu2 */ - __IOM uint32_t DM_PULLUP_EN : 1; /*!< [5..5] DM pull up enable */ - __IOM uint32_t DM_PULLDN_EN : 1; /*!< [6..6] DM pull down enable */ - uint32_t : 1; - __IOM uint32_t TX_DP_OE : 1; /*!< [8..8] Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff - pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving - If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; - 1 - DPP driving */ - __IOM uint32_t TX_DM_OE : 1; /*!< [9..9] Output enable. If TX_DIFFMODE=1, Ignored. - If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; - 1 - DPM driving */ - __IOM uint32_t TX_DP : 1; /*!< [10..10] Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff - pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP - If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable - drive. DPP=TX_DP */ - __IOM uint32_t TX_DM : 1; /*!< [11..11] Output data. TX_DIFFMODE=1, Ignored - TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. - DPM=TX_DM */ - __IOM uint32_t RX_PD : 1; /*!< [12..12] RX power down override (if override enable is set). - 1 = powered down. */ - __IOM uint32_t TX_PD : 1; /*!< [13..13] TX power down override (if override enable is set). - 1 = powered down. */ - __IOM uint32_t TX_FSSLEW : 1; /*!< [14..14] TX_FSSLEW=0: Low speed slew rate - TX_FSSLEW=1: Full speed slew rate */ - __IOM uint32_t TX_DIFFMODE : 1; /*!< [15..15] TX_DIFFMODE=0: Single ended mode - TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE - ignored) */ - __IM uint32_t RX_DD : 1; /*!< [16..16] Differential RX */ - __IM uint32_t RX_DP : 1; /*!< [17..17] DPP pin state */ - __IM uint32_t RX_DM : 1; /*!< [18..18] DPM pin state */ - __IM uint32_t DP_OVCN : 1; /*!< [19..19] DP overcurrent */ - __IM uint32_t DM_OVCN : 1; /*!< [20..20] DM overcurrent */ - __IM uint32_t DP_OVV : 1; /*!< [21..21] DP over voltage */ - __IM uint32_t DM_OVV : 1; /*!< [22..22] DM over voltage */ - uint32_t : 9; - } bit; - } USBPHY_DIRECT; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000080) Override enable for each control in usbphy_direct */ - - struct { - __IOM uint32_t DP_PULLUP_HISEL_OVERRIDE_EN : 1;/*!< [0..0] DP_PULLUP_HISEL_OVERRIDE_EN */ - __IOM uint32_t DM_PULLUP_HISEL_OVERRIDE_EN : 1;/*!< [1..1] DM_PULLUP_HISEL_OVERRIDE_EN */ - __IOM uint32_t DP_PULLUP_EN_OVERRIDE_EN : 1;/*!< [2..2] DP_PULLUP_EN_OVERRIDE_EN */ - __IOM uint32_t DP_PULLDN_EN_OVERRIDE_EN : 1;/*!< [3..3] DP_PULLDN_EN_OVERRIDE_EN */ - __IOM uint32_t DM_PULLDN_EN_OVERRIDE_EN : 1;/*!< [4..4] DM_PULLDN_EN_OVERRIDE_EN */ - __IOM uint32_t TX_DP_OE_OVERRIDE_EN : 1; /*!< [5..5] TX_DP_OE_OVERRIDE_EN */ - __IOM uint32_t TX_DM_OE_OVERRIDE_EN : 1; /*!< [6..6] TX_DM_OE_OVERRIDE_EN */ - __IOM uint32_t TX_DP_OVERRIDE_EN : 1; /*!< [7..7] TX_DP_OVERRIDE_EN */ - __IOM uint32_t TX_DM_OVERRIDE_EN : 1; /*!< [8..8] TX_DM_OVERRIDE_EN */ - __IOM uint32_t RX_PD_OVERRIDE_EN : 1; /*!< [9..9] RX_PD_OVERRIDE_EN */ - __IOM uint32_t TX_PD_OVERRIDE_EN : 1; /*!< [10..10] TX_PD_OVERRIDE_EN */ - __IOM uint32_t TX_FSSLEW_OVERRIDE_EN : 1; /*!< [11..11] TX_FSSLEW_OVERRIDE_EN */ - __IOM uint32_t DM_PULLUP_OVERRIDE_EN : 1; /*!< [12..12] DM_PULLUP_OVERRIDE_EN */ - uint32_t : 2; - __IOM uint32_t TX_DIFFMODE_OVERRIDE_EN : 1;/*!< [15..15] TX_DIFFMODE_OVERRIDE_EN */ - uint32_t : 16; - } bit; - } USBPHY_DIRECT_OVERRIDE; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000084) Used to adjust trim values of USB phy pull down + __IOM uint32_t USBPHY_DIRECT_OVERRIDE; /*!< (@ 0x00000080) Override enable for each control in usbphy_direct */ + __IOM uint32_t USBPHY_TRIM; /*!< (@ 0x00000084) Used to adjust trim values of USB phy pull down resistors. */ - - struct { - __IOM uint32_t DP_PULLDN_TRIM : 5; /*!< [4..0] Value to drive to USB PHY - DP pulldown resistor trim control - Experimental data suggests that the reset value will work, - but this register allows adjustment if required */ - uint32_t : 3; - __IOM uint32_t DM_PULLDN_TRIM : 5; /*!< [12..8] Value to drive to USB PHY - DM pulldown resistor trim control - Experimental data suggests that the reset value will work, - but this register allows adjustment if required */ - uint32_t : 19; - } bit; - } USBPHY_TRIM; __IM uint32_t RESERVED; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000008C) Raw Interrupts */ - - struct { - __IM uint32_t HOST_CONN_DIS : 1; /*!< [0..0] Host: raised when a device is connected or disconnected - (i.e. when SIE_STATUS.SPEED changes). Cleared by writing - to SIE_STATUS.SPEED */ - __IM uint32_t HOST_RESUME : 1; /*!< [1..1] Host: raised when a device wakes up the host. Cleared - by writing to SIE_STATUS.RESUME */ - __IM uint32_t HOST_SOF : 1; /*!< [2..2] Host: raised every time the host sends a SOF (Start of - Frame). Cleared by reading SOF_RD */ - __IM uint32_t TRANS_COMPLETE : 1; /*!< [3..3] Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear - by writing to this bit. */ - __IM uint32_t BUFF_STATUS : 1; /*!< [4..4] Raised when any bit in BUFF_STATUS is set. Clear by clearing - all bits in BUFF_STATUS. */ - __IM uint32_t ERROR_DATA_SEQ : 1; /*!< [5..5] Source: SIE_STATUS.DATA_SEQ_ERROR */ - __IM uint32_t ERROR_RX_TIMEOUT : 1; /*!< [6..6] Source: SIE_STATUS.RX_TIMEOUT */ - __IM uint32_t ERROR_RX_OVERFLOW : 1; /*!< [7..7] Source: SIE_STATUS.RX_OVERFLOW */ - __IM uint32_t ERROR_BIT_STUFF : 1; /*!< [8..8] Source: SIE_STATUS.BIT_STUFF_ERROR */ - __IM uint32_t ERROR_CRC : 1; /*!< [9..9] Source: SIE_STATUS.CRC_ERROR */ - __IM uint32_t STALL : 1; /*!< [10..10] Source: SIE_STATUS.STALL_REC */ - __IM uint32_t VBUS_DETECT : 1; /*!< [11..11] Source: SIE_STATUS.VBUS_DETECT */ - __IM uint32_t BUS_RESET : 1; /*!< [12..12] Source: SIE_STATUS.BUS_RESET */ - __IM uint32_t DEV_CONN_DIS : 1; /*!< [13..13] Set when the device connection state changes. Cleared - by writing to SIE_STATUS.CONNECTED */ - __IM uint32_t DEV_SUSPEND : 1; /*!< [14..14] Set when the device suspend state changes. Cleared - by writing to SIE_STATUS.SUSPENDED */ - __IM uint32_t DEV_RESUME_FROM_HOST : 1; /*!< [15..15] Set when the device receives a resume from the host. - Cleared by writing to SIE_STATUS.RESUME */ - __IM uint32_t SETUP_REQ : 1; /*!< [16..16] Device. Source: SIE_STATUS.SETUP_REC */ - __IM uint32_t DEV_SOF : 1; /*!< [17..17] Set every time the device receives a SOF (Start of - Frame) packet. Cleared by reading SOF_RD */ - __IM uint32_t ABORT_DONE : 1; /*!< [18..18] Raised when any bit in ABORT_DONE is set. Clear by - clearing all bits in ABORT_DONE. */ - __IM uint32_t EP_STALL_NAK : 1; /*!< [19..19] Raised when any bit in EP_STATUS_STALL_NAK is set. - Clear by clearing all bits in EP_STATUS_STALL_NAK. */ - uint32_t : 12; - } bit; - } INTR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000090) Interrupt Enable */ - - struct { - __IOM uint32_t HOST_CONN_DIS : 1; /*!< [0..0] Host: raised when a device is connected or disconnected - (i.e. when SIE_STATUS.SPEED changes). Cleared by writing - to SIE_STATUS.SPEED */ - __IOM uint32_t HOST_RESUME : 1; /*!< [1..1] Host: raised when a device wakes up the host. Cleared - by writing to SIE_STATUS.RESUME */ - __IOM uint32_t HOST_SOF : 1; /*!< [2..2] Host: raised every time the host sends a SOF (Start of - Frame). Cleared by reading SOF_RD */ - __IOM uint32_t TRANS_COMPLETE : 1; /*!< [3..3] Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear - by writing to this bit. */ - __IOM uint32_t BUFF_STATUS : 1; /*!< [4..4] Raised when any bit in BUFF_STATUS is set. Clear by clearing - all bits in BUFF_STATUS. */ - __IOM uint32_t ERROR_DATA_SEQ : 1; /*!< [5..5] Source: SIE_STATUS.DATA_SEQ_ERROR */ - __IOM uint32_t ERROR_RX_TIMEOUT : 1; /*!< [6..6] Source: SIE_STATUS.RX_TIMEOUT */ - __IOM uint32_t ERROR_RX_OVERFLOW : 1; /*!< [7..7] Source: SIE_STATUS.RX_OVERFLOW */ - __IOM uint32_t ERROR_BIT_STUFF : 1; /*!< [8..8] Source: SIE_STATUS.BIT_STUFF_ERROR */ - __IOM uint32_t ERROR_CRC : 1; /*!< [9..9] Source: SIE_STATUS.CRC_ERROR */ - __IOM uint32_t STALL : 1; /*!< [10..10] Source: SIE_STATUS.STALL_REC */ - __IOM uint32_t VBUS_DETECT : 1; /*!< [11..11] Source: SIE_STATUS.VBUS_DETECT */ - __IOM uint32_t BUS_RESET : 1; /*!< [12..12] Source: SIE_STATUS.BUS_RESET */ - __IOM uint32_t DEV_CONN_DIS : 1; /*!< [13..13] Set when the device connection state changes. Cleared - by writing to SIE_STATUS.CONNECTED */ - __IOM uint32_t DEV_SUSPEND : 1; /*!< [14..14] Set when the device suspend state changes. Cleared - by writing to SIE_STATUS.SUSPENDED */ - __IOM uint32_t DEV_RESUME_FROM_HOST : 1; /*!< [15..15] Set when the device receives a resume from the host. - Cleared by writing to SIE_STATUS.RESUME */ - __IOM uint32_t SETUP_REQ : 1; /*!< [16..16] Device. Source: SIE_STATUS.SETUP_REC */ - __IOM uint32_t DEV_SOF : 1; /*!< [17..17] Set every time the device receives a SOF (Start of - Frame) packet. Cleared by reading SOF_RD */ - __IOM uint32_t ABORT_DONE : 1; /*!< [18..18] Raised when any bit in ABORT_DONE is set. Clear by - clearing all bits in ABORT_DONE. */ - __IOM uint32_t EP_STALL_NAK : 1; /*!< [19..19] Raised when any bit in EP_STATUS_STALL_NAK is set. - Clear by clearing all bits in EP_STATUS_STALL_NAK. */ - uint32_t : 12; - } bit; - } INTE; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000094) Interrupt Force */ - - struct { - __IOM uint32_t HOST_CONN_DIS : 1; /*!< [0..0] Host: raised when a device is connected or disconnected - (i.e. when SIE_STATUS.SPEED changes). Cleared by writing - to SIE_STATUS.SPEED */ - __IOM uint32_t HOST_RESUME : 1; /*!< [1..1] Host: raised when a device wakes up the host. Cleared - by writing to SIE_STATUS.RESUME */ - __IOM uint32_t HOST_SOF : 1; /*!< [2..2] Host: raised every time the host sends a SOF (Start of - Frame). Cleared by reading SOF_RD */ - __IOM uint32_t TRANS_COMPLETE : 1; /*!< [3..3] Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear - by writing to this bit. */ - __IOM uint32_t BUFF_STATUS : 1; /*!< [4..4] Raised when any bit in BUFF_STATUS is set. Clear by clearing - all bits in BUFF_STATUS. */ - __IOM uint32_t ERROR_DATA_SEQ : 1; /*!< [5..5] Source: SIE_STATUS.DATA_SEQ_ERROR */ - __IOM uint32_t ERROR_RX_TIMEOUT : 1; /*!< [6..6] Source: SIE_STATUS.RX_TIMEOUT */ - __IOM uint32_t ERROR_RX_OVERFLOW : 1; /*!< [7..7] Source: SIE_STATUS.RX_OVERFLOW */ - __IOM uint32_t ERROR_BIT_STUFF : 1; /*!< [8..8] Source: SIE_STATUS.BIT_STUFF_ERROR */ - __IOM uint32_t ERROR_CRC : 1; /*!< [9..9] Source: SIE_STATUS.CRC_ERROR */ - __IOM uint32_t STALL : 1; /*!< [10..10] Source: SIE_STATUS.STALL_REC */ - __IOM uint32_t VBUS_DETECT : 1; /*!< [11..11] Source: SIE_STATUS.VBUS_DETECT */ - __IOM uint32_t BUS_RESET : 1; /*!< [12..12] Source: SIE_STATUS.BUS_RESET */ - __IOM uint32_t DEV_CONN_DIS : 1; /*!< [13..13] Set when the device connection state changes. Cleared - by writing to SIE_STATUS.CONNECTED */ - __IOM uint32_t DEV_SUSPEND : 1; /*!< [14..14] Set when the device suspend state changes. Cleared - by writing to SIE_STATUS.SUSPENDED */ - __IOM uint32_t DEV_RESUME_FROM_HOST : 1; /*!< [15..15] Set when the device receives a resume from the host. - Cleared by writing to SIE_STATUS.RESUME */ - __IOM uint32_t SETUP_REQ : 1; /*!< [16..16] Device. Source: SIE_STATUS.SETUP_REC */ - __IOM uint32_t DEV_SOF : 1; /*!< [17..17] Set every time the device receives a SOF (Start of - Frame) packet. Cleared by reading SOF_RD */ - __IOM uint32_t ABORT_DONE : 1; /*!< [18..18] Raised when any bit in ABORT_DONE is set. Clear by - clearing all bits in ABORT_DONE. */ - __IOM uint32_t EP_STALL_NAK : 1; /*!< [19..19] Raised when any bit in EP_STATUS_STALL_NAK is set. - Clear by clearing all bits in EP_STATUS_STALL_NAK. */ - uint32_t : 12; - } bit; - } INTF; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000098) Interrupt status after masking & forcing */ - - struct { - __IM uint32_t HOST_CONN_DIS : 1; /*!< [0..0] Host: raised when a device is connected or disconnected - (i.e. when SIE_STATUS.SPEED changes). Cleared by writing - to SIE_STATUS.SPEED */ - __IM uint32_t HOST_RESUME : 1; /*!< [1..1] Host: raised when a device wakes up the host. Cleared - by writing to SIE_STATUS.RESUME */ - __IM uint32_t HOST_SOF : 1; /*!< [2..2] Host: raised every time the host sends a SOF (Start of - Frame). Cleared by reading SOF_RD */ - __IM uint32_t TRANS_COMPLETE : 1; /*!< [3..3] Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear - by writing to this bit. */ - __IM uint32_t BUFF_STATUS : 1; /*!< [4..4] Raised when any bit in BUFF_STATUS is set. Clear by clearing - all bits in BUFF_STATUS. */ - __IM uint32_t ERROR_DATA_SEQ : 1; /*!< [5..5] Source: SIE_STATUS.DATA_SEQ_ERROR */ - __IM uint32_t ERROR_RX_TIMEOUT : 1; /*!< [6..6] Source: SIE_STATUS.RX_TIMEOUT */ - __IM uint32_t ERROR_RX_OVERFLOW : 1; /*!< [7..7] Source: SIE_STATUS.RX_OVERFLOW */ - __IM uint32_t ERROR_BIT_STUFF : 1; /*!< [8..8] Source: SIE_STATUS.BIT_STUFF_ERROR */ - __IM uint32_t ERROR_CRC : 1; /*!< [9..9] Source: SIE_STATUS.CRC_ERROR */ - __IM uint32_t STALL : 1; /*!< [10..10] Source: SIE_STATUS.STALL_REC */ - __IM uint32_t VBUS_DETECT : 1; /*!< [11..11] Source: SIE_STATUS.VBUS_DETECT */ - __IM uint32_t BUS_RESET : 1; /*!< [12..12] Source: SIE_STATUS.BUS_RESET */ - __IM uint32_t DEV_CONN_DIS : 1; /*!< [13..13] Set when the device connection state changes. Cleared - by writing to SIE_STATUS.CONNECTED */ - __IM uint32_t DEV_SUSPEND : 1; /*!< [14..14] Set when the device suspend state changes. Cleared - by writing to SIE_STATUS.SUSPENDED */ - __IM uint32_t DEV_RESUME_FROM_HOST : 1; /*!< [15..15] Set when the device receives a resume from the host. - Cleared by writing to SIE_STATUS.RESUME */ - __IM uint32_t SETUP_REQ : 1; /*!< [16..16] Device. Source: SIE_STATUS.SETUP_REC */ - __IM uint32_t DEV_SOF : 1; /*!< [17..17] Set every time the device receives a SOF (Start of - Frame) packet. Cleared by reading SOF_RD */ - __IM uint32_t ABORT_DONE : 1; /*!< [18..18] Raised when any bit in ABORT_DONE is set. Clear by - clearing all bits in ABORT_DONE. */ - __IM uint32_t EP_STALL_NAK : 1; /*!< [19..19] Raised when any bit in EP_STATUS_STALL_NAK is set. - Clear by clearing all bits in EP_STATUS_STALL_NAK. */ - uint32_t : 12; - } bit; - } INTS; + __IOM uint32_t INTR; /*!< (@ 0x0000008C) Raw Interrupts */ + __IOM uint32_t INTE; /*!< (@ 0x00000090) Interrupt Enable */ + __IOM uint32_t INTF; /*!< (@ 0x00000094) Interrupt Force */ + __IOM uint32_t INTS; /*!< (@ 0x00000098) Interrupt status after masking & forcing */ } USBCTRL_REGS_Type; /*!< Size = 156 (0x9c) */ @@ -12620,1108 +2592,233 @@ typedef struct { /*!< (@ 0x50110000) USBCTRL_REGS */ typedef struct { /*!< (@ 0x50200000) PIO0 Structure */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000000) PIO control register */ - - struct { - __IOM uint32_t SM_ENABLE : 4; /*!< [3..0] Enable state machine */ - __IOM uint32_t SM_RESTART : 4; /*!< [7..4] Clear internal SM state which is otherwise difficult - to access - (e.g. shift counters). Self-clearing. */ - __IOM uint32_t CLKDIV_RESTART : 4; /*!< [11..8] Force clock dividers to restart their count and clear - fractional - accumulators. Restart multiple dividers to synchronise - them. */ - uint32_t : 20; - } bit; - } CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000004) FIFO status register */ - - struct { - __IM uint32_t RXFULL : 4; /*!< [3..0] State machine RX FIFO is full */ - uint32_t : 4; - __IM uint32_t RXEMPTY : 4; /*!< [11..8] State machine RX FIFO is empty */ - uint32_t : 4; - __IM uint32_t TXFULL : 4; /*!< [19..16] State machine TX FIFO is full */ - uint32_t : 4; - __IM uint32_t TXEMPTY : 4; /*!< [27..24] State machine TX FIFO is empty */ - uint32_t : 4; - } bit; - } FSTAT; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000008) FIFO debug register */ - - struct { - __IOM uint32_t RXSTALL : 4; /*!< [3..0] State machine has stalled on full RX FIFO. Write 1 to - clear. */ - uint32_t : 4; - __IOM uint32_t RXUNDER : 4; /*!< [11..8] RX FIFO underflow has occurred. Write 1 to clear. */ - uint32_t : 4; - __IOM uint32_t TXOVER : 4; /*!< [19..16] TX FIFO overflow has occurred. Write 1 to clear. */ - uint32_t : 4; - __IOM uint32_t TXSTALL : 4; /*!< [27..24] State machine has stalled on empty TX FIFO. Write 1 - to clear. */ - uint32_t : 4; - } bit; - } FDEBUG; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000000C) FIFO levels */ - - struct { - __IM uint32_t TX0 : 4; /*!< [3..0] TX0 */ - __IM uint32_t RX0 : 4; /*!< [7..4] RX0 */ - __IM uint32_t TX1 : 4; /*!< [11..8] TX1 */ - __IM uint32_t RX1 : 4; /*!< [15..12] RX1 */ - __IM uint32_t TX2 : 4; /*!< [19..16] TX2 */ - __IM uint32_t RX2 : 4; /*!< [23..20] RX2 */ - __IM uint32_t TX3 : 4; /*!< [27..24] TX3 */ - __IM uint32_t RX3 : 4; /*!< [31..28] RX3 */ - } bit; - } FLEVEL; + __IOM uint32_t CTRL; /*!< (@ 0x00000000) PIO control register */ + __IOM uint32_t FSTAT; /*!< (@ 0x00000004) FIFO status register */ + __IOM uint32_t FDEBUG; /*!< (@ 0x00000008) FIFO debug register */ + __IOM uint32_t FLEVEL; /*!< (@ 0x0000000C) FIFO levels */ __OM uint32_t TXF0; /*!< (@ 0x00000010) Direct write access to the TX FIFO for this state machine. Each write pushes one word to the - FIFO. */ + FIFO. Attempting to write to a full FIFO + has no effect on the FIFO state or contents, + and sets the sticky FDEBUG_TXOVER error + flag for this FIFO. */ __OM uint32_t TXF1; /*!< (@ 0x00000014) Direct write access to the TX FIFO for this state machine. Each write pushes one word to the - FIFO. */ + FIFO. Attempting to write to a full FIFO + has no effect on the FIFO state or contents, + and sets the sticky FDEBUG_TXOVER error + flag for this FIFO. */ __OM uint32_t TXF2; /*!< (@ 0x00000018) Direct write access to the TX FIFO for this state machine. Each write pushes one word to the - FIFO. */ + FIFO. Attempting to write to a full FIFO + has no effect on the FIFO state or contents, + and sets the sticky FDEBUG_TXOVER error + flag for this FIFO. */ __OM uint32_t TXF3; /*!< (@ 0x0000001C) Direct write access to the TX FIFO for this state machine. Each write pushes one word to the - FIFO. */ + FIFO. Attempting to write to a full FIFO + has no effect on the FIFO state or contents, + and sets the sticky FDEBUG_TXOVER error + flag for this FIFO. */ __IM uint32_t RXF0; /*!< (@ 0x00000020) Direct read access to the RX FIFO for this state machine. Each read pops one word from the - FIFO. */ + FIFO. Attempting to read from an empty FIFO + has no effect on the FIFO state, and sets + the sticky FDEBUG_RXUNDER error flag for + this FIFO. The data returned to the system + on a read from an empty FIFO is undefined. */ __IM uint32_t RXF1; /*!< (@ 0x00000024) Direct read access to the RX FIFO for this state machine. Each read pops one word from the - FIFO. */ + FIFO. Attempting to read from an empty FIFO + has no effect on the FIFO state, and sets + the sticky FDEBUG_RXUNDER error flag for + this FIFO. The data returned to the system + on a read from an empty FIFO is undefined. */ __IM uint32_t RXF2; /*!< (@ 0x00000028) Direct read access to the RX FIFO for this state machine. Each read pops one word from the - FIFO. */ + FIFO. Attempting to read from an empty FIFO + has no effect on the FIFO state, and sets + the sticky FDEBUG_RXUNDER error flag for + this FIFO. The data returned to the system + on a read from an empty FIFO is undefined. */ __IM uint32_t RXF3; /*!< (@ 0x0000002C) Direct read access to the RX FIFO for this state machine. Each read pops one word from the - FIFO. */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000030) Interrupt request register. Write 1 to clear */ - - struct { - __IOM uint32_t IRQ : 8; /*!< [7..0] IRQ */ - uint32_t : 24; - } bit; - } IRQ; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000034) Writing a 1 to each of these bits will forcibly - assert the corresponding IRQ. - Note this is different to the INTF register: - writing here affects PIO internal - state. INTF just asserts the processor-facing - IRQ signal for testing ISRs, - and is not visible to the state machines. */ - - struct { - __OM uint32_t IRQ_FORCE : 8; /*!< [7..0] IRQ_FORCE */ - uint32_t : 24; - } bit; - } IRQ_FORCE; + FIFO. Attempting to read from an empty FIFO + has no effect on the FIFO state, and sets + the sticky FDEBUG_RXUNDER error flag for + this FIFO. The data returned to the system + on a read from an empty FIFO is undefined. */ + __IOM uint32_t IRQ; /*!< (@ 0x00000030) State machine IRQ flags register. Write 1 to + clear. There are 8 state machine IRQ flags, + which can be set, cleared, and waited on + by the state machines. There's no fixed + association between flags and state machines + -- any state machine can use any flag. + + Any of the 8 flags can be used for timing + synchronisation between state machines, + using IRQ and WAIT instructions. The lower + four of these flags are also routed out + to system-level interrupt requests, alongside + FIFO status in */ + __IOM uint32_t IRQ_FORCE; /*!< (@ 0x00000034) Writing a 1 to each of these bits will forcibly + assert the corresponding IRQ. Note this + is different to the INTF register: writing + here affects PIO internal state. INTF just + asserts the processor-facing IRQ signal + for testing ISRs, and is not visible to + the state machines. */ __IOM uint32_t INPUT_SYNC_BYPASS; /*!< (@ 0x00000038) There is a 2-flipflop synchronizer on each GPIO - input, which protects - PIO logic from metastabilities. This increases - input delay, and for fast + input, which protects PIO logic from metastabilities. + This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers - may need to be bypassed. - Each bit in this register corresponds to - one GPIO. + may need to be bypassed. Each bit in this + register corresponds to one GPIO. 0 -> input is synchronized (default) 1 -> synchronizer is bypassed If in doubt, leave this register as all zeroes. */ __IM uint32_t DBG_PADOUT; /*!< (@ 0x0000003C) Read to sample the pad output values PIO is currently - driving to the GPIOs. */ + driving to the GPIOs. On RP2040 there are + 30 GPIOs, so the two most significant bits + are hardwired to 0. */ __IM uint32_t DBG_PADOE; /*!< (@ 0x00000040) Read to sample the pad output enables (direction) - PIO is currently driving to the GPIOs. */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000044) The PIO hardware has some free parameters that + PIO is currently driving to the GPIOs. On + RP2040 there are 30 GPIOs, so the two most + significant bits are hardwired to 0. */ + __IOM uint32_t DBG_CFGINFO; /*!< (@ 0x00000044) The PIO hardware has some free parameters that may vary between chip products. These should be provided in the chip datasheet, but are also exposed here. */ - - struct { - __IM uint32_t FIFO_DEPTH : 6; /*!< [5..0] The depth of the state machine TX/RX FIFOs, measured - in words. - Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double - this depth. */ - uint32_t : 2; - __IM uint32_t SM_COUNT : 4; /*!< [11..8] The number of state machines this PIO instance is equipped - with. */ - uint32_t : 4; - __IM uint32_t IMEM_SIZE : 6; /*!< [21..16] The size of the instruction memory, measured in units - of one instruction */ - uint32_t : 10; - } bit; - } DBG_CFGINFO; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000048) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM0; /*!< (@ 0x00000048) Write-only access to instruction memory location 0 */ - - struct { - __IOM uint32_t INSTR_MEM0 : 16; /*!< [15..0] INSTR_MEM0 */ - uint32_t : 16; - } bit; - } INSTR_MEM0; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000004C) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM1; /*!< (@ 0x0000004C) Write-only access to instruction memory location 1 */ - - struct { - __IOM uint32_t INSTR_MEM1 : 16; /*!< [15..0] INSTR_MEM1 */ - uint32_t : 16; - } bit; - } INSTR_MEM1; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000050) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM2; /*!< (@ 0x00000050) Write-only access to instruction memory location 2 */ - - struct { - __IOM uint32_t INSTR_MEM2 : 16; /*!< [15..0] INSTR_MEM2 */ - uint32_t : 16; - } bit; - } INSTR_MEM2; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000054) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM3; /*!< (@ 0x00000054) Write-only access to instruction memory location 3 */ - - struct { - __IOM uint32_t INSTR_MEM3 : 16; /*!< [15..0] INSTR_MEM3 */ - uint32_t : 16; - } bit; - } INSTR_MEM3; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000058) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM4; /*!< (@ 0x00000058) Write-only access to instruction memory location 4 */ - - struct { - __IOM uint32_t INSTR_MEM4 : 16; /*!< [15..0] INSTR_MEM4 */ - uint32_t : 16; - } bit; - } INSTR_MEM4; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000005C) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM5; /*!< (@ 0x0000005C) Write-only access to instruction memory location 5 */ - - struct { - __IOM uint32_t INSTR_MEM5 : 16; /*!< [15..0] INSTR_MEM5 */ - uint32_t : 16; - } bit; - } INSTR_MEM5; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000060) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM6; /*!< (@ 0x00000060) Write-only access to instruction memory location 6 */ - - struct { - __IOM uint32_t INSTR_MEM6 : 16; /*!< [15..0] INSTR_MEM6 */ - uint32_t : 16; - } bit; - } INSTR_MEM6; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000064) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM7; /*!< (@ 0x00000064) Write-only access to instruction memory location 7 */ - - struct { - __IOM uint32_t INSTR_MEM7 : 16; /*!< [15..0] INSTR_MEM7 */ - uint32_t : 16; - } bit; - } INSTR_MEM7; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000068) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM8; /*!< (@ 0x00000068) Write-only access to instruction memory location 8 */ - - struct { - __IOM uint32_t INSTR_MEM8 : 16; /*!< [15..0] INSTR_MEM8 */ - uint32_t : 16; - } bit; - } INSTR_MEM8; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000006C) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM9; /*!< (@ 0x0000006C) Write-only access to instruction memory location 9 */ - - struct { - __IOM uint32_t INSTR_MEM9 : 16; /*!< [15..0] INSTR_MEM9 */ - uint32_t : 16; - } bit; - } INSTR_MEM9; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000070) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM10; /*!< (@ 0x00000070) Write-only access to instruction memory location 10 */ - - struct { - __IOM uint32_t INSTR_MEM10 : 16; /*!< [15..0] INSTR_MEM10 */ - uint32_t : 16; - } bit; - } INSTR_MEM10; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000074) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM11; /*!< (@ 0x00000074) Write-only access to instruction memory location 11 */ - - struct { - __IOM uint32_t INSTR_MEM11 : 16; /*!< [15..0] INSTR_MEM11 */ - uint32_t : 16; - } bit; - } INSTR_MEM11; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000078) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM12; /*!< (@ 0x00000078) Write-only access to instruction memory location 12 */ - - struct { - __IOM uint32_t INSTR_MEM12 : 16; /*!< [15..0] INSTR_MEM12 */ - uint32_t : 16; - } bit; - } INSTR_MEM12; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000007C) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM13; /*!< (@ 0x0000007C) Write-only access to instruction memory location 13 */ - - struct { - __IOM uint32_t INSTR_MEM13 : 16; /*!< [15..0] INSTR_MEM13 */ - uint32_t : 16; - } bit; - } INSTR_MEM13; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000080) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM14; /*!< (@ 0x00000080) Write-only access to instruction memory location 14 */ - - struct { - __IOM uint32_t INSTR_MEM14 : 16; /*!< [15..0] INSTR_MEM14 */ - uint32_t : 16; - } bit; - } INSTR_MEM14; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000084) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM15; /*!< (@ 0x00000084) Write-only access to instruction memory location 15 */ - - struct { - __IOM uint32_t INSTR_MEM15 : 16; /*!< [15..0] INSTR_MEM15 */ - uint32_t : 16; - } bit; - } INSTR_MEM15; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000088) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM16; /*!< (@ 0x00000088) Write-only access to instruction memory location 16 */ - - struct { - __IOM uint32_t INSTR_MEM16 : 16; /*!< [15..0] INSTR_MEM16 */ - uint32_t : 16; - } bit; - } INSTR_MEM16; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000008C) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM17; /*!< (@ 0x0000008C) Write-only access to instruction memory location 17 */ - - struct { - __IOM uint32_t INSTR_MEM17 : 16; /*!< [15..0] INSTR_MEM17 */ - uint32_t : 16; - } bit; - } INSTR_MEM17; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000090) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM18; /*!< (@ 0x00000090) Write-only access to instruction memory location 18 */ - - struct { - __IOM uint32_t INSTR_MEM18 : 16; /*!< [15..0] INSTR_MEM18 */ - uint32_t : 16; - } bit; - } INSTR_MEM18; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000094) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM19; /*!< (@ 0x00000094) Write-only access to instruction memory location 19 */ - - struct { - __IOM uint32_t INSTR_MEM19 : 16; /*!< [15..0] INSTR_MEM19 */ - uint32_t : 16; - } bit; - } INSTR_MEM19; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000098) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM20; /*!< (@ 0x00000098) Write-only access to instruction memory location 20 */ - - struct { - __IOM uint32_t INSTR_MEM20 : 16; /*!< [15..0] INSTR_MEM20 */ - uint32_t : 16; - } bit; - } INSTR_MEM20; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000009C) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM21; /*!< (@ 0x0000009C) Write-only access to instruction memory location 21 */ - - struct { - __IOM uint32_t INSTR_MEM21 : 16; /*!< [15..0] INSTR_MEM21 */ - uint32_t : 16; - } bit; - } INSTR_MEM21; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000A0) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM22; /*!< (@ 0x000000A0) Write-only access to instruction memory location 22 */ - - struct { - __IOM uint32_t INSTR_MEM22 : 16; /*!< [15..0] INSTR_MEM22 */ - uint32_t : 16; - } bit; - } INSTR_MEM22; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000A4) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM23; /*!< (@ 0x000000A4) Write-only access to instruction memory location 23 */ - - struct { - __IOM uint32_t INSTR_MEM23 : 16; /*!< [15..0] INSTR_MEM23 */ - uint32_t : 16; - } bit; - } INSTR_MEM23; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000A8) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM24; /*!< (@ 0x000000A8) Write-only access to instruction memory location 24 */ - - struct { - __IOM uint32_t INSTR_MEM24 : 16; /*!< [15..0] INSTR_MEM24 */ - uint32_t : 16; - } bit; - } INSTR_MEM24; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000AC) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM25; /*!< (@ 0x000000AC) Write-only access to instruction memory location 25 */ - - struct { - __IOM uint32_t INSTR_MEM25 : 16; /*!< [15..0] INSTR_MEM25 */ - uint32_t : 16; - } bit; - } INSTR_MEM25; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000B0) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM26; /*!< (@ 0x000000B0) Write-only access to instruction memory location 26 */ - - struct { - __IOM uint32_t INSTR_MEM26 : 16; /*!< [15..0] INSTR_MEM26 */ - uint32_t : 16; - } bit; - } INSTR_MEM26; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000B4) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM27; /*!< (@ 0x000000B4) Write-only access to instruction memory location 27 */ - - struct { - __IOM uint32_t INSTR_MEM27 : 16; /*!< [15..0] INSTR_MEM27 */ - uint32_t : 16; - } bit; - } INSTR_MEM27; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000B8) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM28; /*!< (@ 0x000000B8) Write-only access to instruction memory location 28 */ - - struct { - __IOM uint32_t INSTR_MEM28 : 16; /*!< [15..0] INSTR_MEM28 */ - uint32_t : 16; - } bit; - } INSTR_MEM28; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000BC) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM29; /*!< (@ 0x000000BC) Write-only access to instruction memory location 29 */ - - struct { - __IOM uint32_t INSTR_MEM29 : 16; /*!< [15..0] INSTR_MEM29 */ - uint32_t : 16; - } bit; - } INSTR_MEM29; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000C0) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM30; /*!< (@ 0x000000C0) Write-only access to instruction memory location 30 */ - - struct { - __IOM uint32_t INSTR_MEM30 : 16; /*!< [15..0] INSTR_MEM30 */ - uint32_t : 16; - } bit; - } INSTR_MEM30; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000C4) Write-only access to instruction memory location + __IOM uint32_t INSTR_MEM31; /*!< (@ 0x000000C4) Write-only access to instruction memory location 31 */ - - struct { - __IOM uint32_t INSTR_MEM31 : 16; /*!< [15..0] INSTR_MEM31 */ - uint32_t : 16; - } bit; - } INSTR_MEM31; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000C8) Clock divider register for state machine 0 + __IOM uint32_t SM0_CLKDIV; /*!< (@ 0x000000C8) Clock divisor register for state machine 0 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ - - struct { - uint32_t : 8; - __IOM uint32_t FRAC : 8; /*!< [15..8] Fractional part of clock divider */ - __IOM uint32_t INT : 16; /*!< [31..16] Effective frequency is sysclk/int. - Value of 0 is interpreted as max possible value */ - } bit; - } SM0_CLKDIV; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000CC) Execution/behavioural settings for state machine + __IOM uint32_t SM0_EXECCTRL; /*!< (@ 0x000000CC) Execution/behavioural settings for state machine 0 */ - - struct { - __IOM uint32_t STATUS_N : 4; /*!< [3..0] Comparison level for the MOV x, STATUS instruction */ - __IOM uint32_t STATUS_SEL : 1; /*!< [4..4] Comparison used for the MOV x, STATUS instruction. */ - uint32_t : 2; - __IOM uint32_t WRAP_BOTTOM : 5; /*!< [11..7] After reaching wrap_top, execution is wrapped to this - address. */ - __IOM uint32_t WRAP_TOP : 5; /*!< [16..12] After reaching this address, execution is wrapped to - wrap_bottom. - If the instruction is a jump, and the jump condition is - true, the jump takes priority. */ - __IOM uint32_t OUT_STICKY : 1; /*!< [17..17] Continuously assert the most recent OUT/SET to the - pins */ - __IOM uint32_t INLINE_OUT_EN : 1; /*!< [18..18] If 1, use a bit of OUT data as an auxiliary write enable - When used in conjunction with OUT_STICKY, writes with an - enable of 0 will - deassert the latest pin write. This can create useful masking/override - behaviour - due to the priority ordering of state machine pin writes - (SM0 < SM1 < ...) */ - __IOM uint32_t OUT_EN_SEL : 5; /*!< [23..19] Which data bit to use for inline OUT enable */ - __IOM uint32_t JMP_PIN : 5; /*!< [28..24] The GPIO number to use as condition for JMP PIN. Unaffected - by input mapping. */ - __IOM uint32_t SIDE_PINDIR : 1; /*!< [29..29] Side-set data is asserted to pin OEs instead of pin - values */ - __IOM uint32_t SIDE_EN : 1; /*!< [30..30] If 1, the delay MSB is used as side-set enable, rather - than a - side-set data bit. This allows instructions to perform - side-set optionally, - rather than on every instruction. */ - __IM uint32_t EXEC_STALLED : 1; /*!< [31..31] An instruction written to SMx_INSTR is stalled, and - latched by the - state machine. Will clear once the instruction completes. */ - } bit; - } SM0_EXECCTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000D0) Control behaviour of the input/output shift registers + __IOM uint32_t SM0_SHIFTCTRL; /*!< (@ 0x000000D0) Control behaviour of the input/output shift registers for state machine 0 */ - - struct { - uint32_t : 16; - __IOM uint32_t AUTOPUSH : 1; /*!< [16..16] Push automatically when the input shift register is - filled */ - __IOM uint32_t AUTOPULL : 1; /*!< [17..17] Pull automatically when the output shift register is - emptied */ - __IOM uint32_t IN_SHIFTDIR : 1; /*!< [18..18] 1 = shift input shift register to right (data enters - from left). 0 = to left. */ - __IOM uint32_t OUT_SHIFTDIR : 1; /*!< [19..19] 1 = shift out of output shift register to right. 0 - = to left. */ - __IOM uint32_t PUSH_THRESH : 5; /*!< [24..20] Number of bits shifted into RXSR before autopush or - conditional push. - Write 0 for value of 32. */ - __IOM uint32_t PULL_THRESH : 5; /*!< [29..25] Number of bits shifted out of TXSR before autopull - or conditional pull. - Write 0 for value of 32. */ - __IOM uint32_t FJOIN_TX : 1; /*!< [30..30] When 1, TX FIFO steals the RX FIFO's storage, and becomes - twice as deep. - RX FIFO is disabled as a result (always reads as both full - and empty). - FIFOs are flushed when this bit is changed. */ - __IOM uint32_t FJOIN_RX : 1; /*!< [31..31] When 1, RX FIFO steals the TX FIFO's storage, and becomes - twice as deep. - TX FIFO is disabled as a result (always reads as both full - and empty). - FIFOs are flushed when this bit is changed. */ - } bit; - } SM0_SHIFTCTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000D4) Current instruction address of state machine + __IOM uint32_t SM0_ADDR; /*!< (@ 0x000000D4) Current instruction address of state machine 0 */ - - struct { - __IM uint32_t SM0_ADDR : 5; /*!< [4..0] SM0_ADDR */ - uint32_t : 27; - } bit; - } SM0_ADDR; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000D8) Instruction currently being executed by state - machine 0 + __IOM uint32_t SM0_INSTR; /*!< (@ 0x000000D8) Read to see the instruction currently addressed + by state machine 0's program counter Write to execute an instruction immediately (including jumps) and then resume execution. */ - - struct { - __IOM uint32_t SM0_INSTR : 16; /*!< [15..0] SM0_INSTR */ - uint32_t : 16; - } bit; - } SM0_INSTR; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000DC) State machine pin control */ - - struct { - __IOM uint32_t OUT_BASE : 5; /*!< [4..0] The virtual pin corresponding to OUT bit 0 */ - __IOM uint32_t SET_BASE : 5; /*!< [9..5] The virtual pin corresponding to SET bit 0 */ - __IOM uint32_t SIDESET_BASE : 5; /*!< [14..10] The virtual pin corresponding to delay field bit 0 */ - __IOM uint32_t IN_BASE : 5; /*!< [19..15] The virtual pin corresponding to IN bit 0 */ - __IOM uint32_t OUT_COUNT : 6; /*!< [25..20] The number of pins asserted by an OUT. Value of 0 -> - 32 pins */ - __IOM uint32_t SET_COUNT : 3; /*!< [28..26] The number of pins asserted by a SET. Max of 5 */ - __IOM uint32_t SIDESET_COUNT : 3; /*!< [31..29] The number of delay bits co-opted for side-set. Inclusive - of the enable bit, if present. */ - } bit; - } SM0_PINCTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000E0) Clock divider register for state machine 1 + __IOM uint32_t SM0_PINCTRL; /*!< (@ 0x000000DC) State machine pin control */ + __IOM uint32_t SM1_CLKDIV; /*!< (@ 0x000000E0) Clock divisor register for state machine 1 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ - - struct { - uint32_t : 8; - __IOM uint32_t FRAC : 8; /*!< [15..8] Fractional part of clock divider */ - __IOM uint32_t INT : 16; /*!< [31..16] Effective frequency is sysclk/int. - Value of 0 is interpreted as max possible value */ - } bit; - } SM1_CLKDIV; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000E4) Execution/behavioural settings for state machine + __IOM uint32_t SM1_EXECCTRL; /*!< (@ 0x000000E4) Execution/behavioural settings for state machine 1 */ - - struct { - __IOM uint32_t STATUS_N : 4; /*!< [3..0] Comparison level for the MOV x, STATUS instruction */ - __IOM uint32_t STATUS_SEL : 1; /*!< [4..4] Comparison used for the MOV x, STATUS instruction. */ - uint32_t : 2; - __IOM uint32_t WRAP_BOTTOM : 5; /*!< [11..7] After reaching wrap_top, execution is wrapped to this - address. */ - __IOM uint32_t WRAP_TOP : 5; /*!< [16..12] After reaching this address, execution is wrapped to - wrap_bottom. - If the instruction is a jump, and the jump condition is - true, the jump takes priority. */ - __IOM uint32_t OUT_STICKY : 1; /*!< [17..17] Continuously assert the most recent OUT/SET to the - pins */ - __IOM uint32_t INLINE_OUT_EN : 1; /*!< [18..18] If 1, use a bit of OUT data as an auxiliary write enable - When used in conjunction with OUT_STICKY, writes with an - enable of 0 will - deassert the latest pin write. This can create useful masking/override - behaviour - due to the priority ordering of state machine pin writes - (SM0 < SM1 < ...) */ - __IOM uint32_t OUT_EN_SEL : 5; /*!< [23..19] Which data bit to use for inline OUT enable */ - __IOM uint32_t JMP_PIN : 5; /*!< [28..24] The GPIO number to use as condition for JMP PIN. Unaffected - by input mapping. */ - __IOM uint32_t SIDE_PINDIR : 1; /*!< [29..29] Side-set data is asserted to pin OEs instead of pin - values */ - __IOM uint32_t SIDE_EN : 1; /*!< [30..30] If 1, the delay MSB is used as side-set enable, rather - than a - side-set data bit. This allows instructions to perform - side-set optionally, - rather than on every instruction. */ - __IM uint32_t EXEC_STALLED : 1; /*!< [31..31] An instruction written to SMx_INSTR is stalled, and - latched by the - state machine. Will clear once the instruction completes. */ - } bit; - } SM1_EXECCTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000E8) Control behaviour of the input/output shift registers + __IOM uint32_t SM1_SHIFTCTRL; /*!< (@ 0x000000E8) Control behaviour of the input/output shift registers for state machine 1 */ - - struct { - uint32_t : 16; - __IOM uint32_t AUTOPUSH : 1; /*!< [16..16] Push automatically when the input shift register is - filled */ - __IOM uint32_t AUTOPULL : 1; /*!< [17..17] Pull automatically when the output shift register is - emptied */ - __IOM uint32_t IN_SHIFTDIR : 1; /*!< [18..18] 1 = shift input shift register to right (data enters - from left). 0 = to left. */ - __IOM uint32_t OUT_SHIFTDIR : 1; /*!< [19..19] 1 = shift out of output shift register to right. 0 - = to left. */ - __IOM uint32_t PUSH_THRESH : 5; /*!< [24..20] Number of bits shifted into RXSR before autopush or - conditional push. - Write 0 for value of 32. */ - __IOM uint32_t PULL_THRESH : 5; /*!< [29..25] Number of bits shifted out of TXSR before autopull - or conditional pull. - Write 0 for value of 32. */ - __IOM uint32_t FJOIN_TX : 1; /*!< [30..30] When 1, TX FIFO steals the RX FIFO's storage, and becomes - twice as deep. - RX FIFO is disabled as a result (always reads as both full - and empty). - FIFOs are flushed when this bit is changed. */ - __IOM uint32_t FJOIN_RX : 1; /*!< [31..31] When 1, RX FIFO steals the TX FIFO's storage, and becomes - twice as deep. - TX FIFO is disabled as a result (always reads as both full - and empty). - FIFOs are flushed when this bit is changed. */ - } bit; - } SM1_SHIFTCTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000EC) Current instruction address of state machine + __IOM uint32_t SM1_ADDR; /*!< (@ 0x000000EC) Current instruction address of state machine 1 */ - - struct { - __IM uint32_t SM1_ADDR : 5; /*!< [4..0] SM1_ADDR */ - uint32_t : 27; - } bit; - } SM1_ADDR; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000F0) Instruction currently being executed by state - machine 1 + __IOM uint32_t SM1_INSTR; /*!< (@ 0x000000F0) Read to see the instruction currently addressed + by state machine 1's program counter Write to execute an instruction immediately (including jumps) and then resume execution. */ - - struct { - __IOM uint32_t SM1_INSTR : 16; /*!< [15..0] SM1_INSTR */ - uint32_t : 16; - } bit; - } SM1_INSTR; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000F4) State machine pin control */ - - struct { - __IOM uint32_t OUT_BASE : 5; /*!< [4..0] The virtual pin corresponding to OUT bit 0 */ - __IOM uint32_t SET_BASE : 5; /*!< [9..5] The virtual pin corresponding to SET bit 0 */ - __IOM uint32_t SIDESET_BASE : 5; /*!< [14..10] The virtual pin corresponding to delay field bit 0 */ - __IOM uint32_t IN_BASE : 5; /*!< [19..15] The virtual pin corresponding to IN bit 0 */ - __IOM uint32_t OUT_COUNT : 6; /*!< [25..20] The number of pins asserted by an OUT. Value of 0 -> - 32 pins */ - __IOM uint32_t SET_COUNT : 3; /*!< [28..26] The number of pins asserted by a SET. Max of 5 */ - __IOM uint32_t SIDESET_COUNT : 3; /*!< [31..29] The number of delay bits co-opted for side-set. Inclusive - of the enable bit, if present. */ - } bit; - } SM1_PINCTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000F8) Clock divider register for state machine 2 + __IOM uint32_t SM1_PINCTRL; /*!< (@ 0x000000F4) State machine pin control */ + __IOM uint32_t SM2_CLKDIV; /*!< (@ 0x000000F8) Clock divisor register for state machine 2 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ - - struct { - uint32_t : 8; - __IOM uint32_t FRAC : 8; /*!< [15..8] Fractional part of clock divider */ - __IOM uint32_t INT : 16; /*!< [31..16] Effective frequency is sysclk/int. - Value of 0 is interpreted as max possible value */ - } bit; - } SM2_CLKDIV; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000FC) Execution/behavioural settings for state machine + __IOM uint32_t SM2_EXECCTRL; /*!< (@ 0x000000FC) Execution/behavioural settings for state machine 2 */ - - struct { - __IOM uint32_t STATUS_N : 4; /*!< [3..0] Comparison level for the MOV x, STATUS instruction */ - __IOM uint32_t STATUS_SEL : 1; /*!< [4..4] Comparison used for the MOV x, STATUS instruction. */ - uint32_t : 2; - __IOM uint32_t WRAP_BOTTOM : 5; /*!< [11..7] After reaching wrap_top, execution is wrapped to this - address. */ - __IOM uint32_t WRAP_TOP : 5; /*!< [16..12] After reaching this address, execution is wrapped to - wrap_bottom. - If the instruction is a jump, and the jump condition is - true, the jump takes priority. */ - __IOM uint32_t OUT_STICKY : 1; /*!< [17..17] Continuously assert the most recent OUT/SET to the - pins */ - __IOM uint32_t INLINE_OUT_EN : 1; /*!< [18..18] If 1, use a bit of OUT data as an auxiliary write enable - When used in conjunction with OUT_STICKY, writes with an - enable of 0 will - deassert the latest pin write. This can create useful masking/override - behaviour - due to the priority ordering of state machine pin writes - (SM0 < SM1 < ...) */ - __IOM uint32_t OUT_EN_SEL : 5; /*!< [23..19] Which data bit to use for inline OUT enable */ - __IOM uint32_t JMP_PIN : 5; /*!< [28..24] The GPIO number to use as condition for JMP PIN. Unaffected - by input mapping. */ - __IOM uint32_t SIDE_PINDIR : 1; /*!< [29..29] Side-set data is asserted to pin OEs instead of pin - values */ - __IOM uint32_t SIDE_EN : 1; /*!< [30..30] If 1, the delay MSB is used as side-set enable, rather - than a - side-set data bit. This allows instructions to perform - side-set optionally, - rather than on every instruction. */ - __IM uint32_t EXEC_STALLED : 1; /*!< [31..31] An instruction written to SMx_INSTR is stalled, and - latched by the - state machine. Will clear once the instruction completes. */ - } bit; - } SM2_EXECCTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000100) Control behaviour of the input/output shift registers + __IOM uint32_t SM2_SHIFTCTRL; /*!< (@ 0x00000100) Control behaviour of the input/output shift registers for state machine 2 */ - - struct { - uint32_t : 16; - __IOM uint32_t AUTOPUSH : 1; /*!< [16..16] Push automatically when the input shift register is - filled */ - __IOM uint32_t AUTOPULL : 1; /*!< [17..17] Pull automatically when the output shift register is - emptied */ - __IOM uint32_t IN_SHIFTDIR : 1; /*!< [18..18] 1 = shift input shift register to right (data enters - from left). 0 = to left. */ - __IOM uint32_t OUT_SHIFTDIR : 1; /*!< [19..19] 1 = shift out of output shift register to right. 0 - = to left. */ - __IOM uint32_t PUSH_THRESH : 5; /*!< [24..20] Number of bits shifted into RXSR before autopush or - conditional push. - Write 0 for value of 32. */ - __IOM uint32_t PULL_THRESH : 5; /*!< [29..25] Number of bits shifted out of TXSR before autopull - or conditional pull. - Write 0 for value of 32. */ - __IOM uint32_t FJOIN_TX : 1; /*!< [30..30] When 1, TX FIFO steals the RX FIFO's storage, and becomes - twice as deep. - RX FIFO is disabled as a result (always reads as both full - and empty). - FIFOs are flushed when this bit is changed. */ - __IOM uint32_t FJOIN_RX : 1; /*!< [31..31] When 1, RX FIFO steals the TX FIFO's storage, and becomes - twice as deep. - TX FIFO is disabled as a result (always reads as both full - and empty). - FIFOs are flushed when this bit is changed. */ - } bit; - } SM2_SHIFTCTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000104) Current instruction address of state machine + __IOM uint32_t SM2_ADDR; /*!< (@ 0x00000104) Current instruction address of state machine 2 */ - - struct { - __IM uint32_t SM2_ADDR : 5; /*!< [4..0] SM2_ADDR */ - uint32_t : 27; - } bit; - } SM2_ADDR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000108) Instruction currently being executed by state - machine 2 + __IOM uint32_t SM2_INSTR; /*!< (@ 0x00000108) Read to see the instruction currently addressed + by state machine 2's program counter Write to execute an instruction immediately (including jumps) and then resume execution. */ - - struct { - __IOM uint32_t SM2_INSTR : 16; /*!< [15..0] SM2_INSTR */ - uint32_t : 16; - } bit; - } SM2_INSTR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000010C) State machine pin control */ - - struct { - __IOM uint32_t OUT_BASE : 5; /*!< [4..0] The virtual pin corresponding to OUT bit 0 */ - __IOM uint32_t SET_BASE : 5; /*!< [9..5] The virtual pin corresponding to SET bit 0 */ - __IOM uint32_t SIDESET_BASE : 5; /*!< [14..10] The virtual pin corresponding to delay field bit 0 */ - __IOM uint32_t IN_BASE : 5; /*!< [19..15] The virtual pin corresponding to IN bit 0 */ - __IOM uint32_t OUT_COUNT : 6; /*!< [25..20] The number of pins asserted by an OUT. Value of 0 -> - 32 pins */ - __IOM uint32_t SET_COUNT : 3; /*!< [28..26] The number of pins asserted by a SET. Max of 5 */ - __IOM uint32_t SIDESET_COUNT : 3; /*!< [31..29] The number of delay bits co-opted for side-set. Inclusive - of the enable bit, if present. */ - } bit; - } SM2_PINCTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000110) Clock divider register for state machine 3 + __IOM uint32_t SM2_PINCTRL; /*!< (@ 0x0000010C) State machine pin control */ + __IOM uint32_t SM3_CLKDIV; /*!< (@ 0x00000110) Clock divisor register for state machine 3 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ - - struct { - uint32_t : 8; - __IOM uint32_t FRAC : 8; /*!< [15..8] Fractional part of clock divider */ - __IOM uint32_t INT : 16; /*!< [31..16] Effective frequency is sysclk/int. - Value of 0 is interpreted as max possible value */ - } bit; - } SM3_CLKDIV; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000114) Execution/behavioural settings for state machine + __IOM uint32_t SM3_EXECCTRL; /*!< (@ 0x00000114) Execution/behavioural settings for state machine 3 */ - - struct { - __IOM uint32_t STATUS_N : 4; /*!< [3..0] Comparison level for the MOV x, STATUS instruction */ - __IOM uint32_t STATUS_SEL : 1; /*!< [4..4] Comparison used for the MOV x, STATUS instruction. */ - uint32_t : 2; - __IOM uint32_t WRAP_BOTTOM : 5; /*!< [11..7] After reaching wrap_top, execution is wrapped to this - address. */ - __IOM uint32_t WRAP_TOP : 5; /*!< [16..12] After reaching this address, execution is wrapped to - wrap_bottom. - If the instruction is a jump, and the jump condition is - true, the jump takes priority. */ - __IOM uint32_t OUT_STICKY : 1; /*!< [17..17] Continuously assert the most recent OUT/SET to the - pins */ - __IOM uint32_t INLINE_OUT_EN : 1; /*!< [18..18] If 1, use a bit of OUT data as an auxiliary write enable - When used in conjunction with OUT_STICKY, writes with an - enable of 0 will - deassert the latest pin write. This can create useful masking/override - behaviour - due to the priority ordering of state machine pin writes - (SM0 < SM1 < ...) */ - __IOM uint32_t OUT_EN_SEL : 5; /*!< [23..19] Which data bit to use for inline OUT enable */ - __IOM uint32_t JMP_PIN : 5; /*!< [28..24] The GPIO number to use as condition for JMP PIN. Unaffected - by input mapping. */ - __IOM uint32_t SIDE_PINDIR : 1; /*!< [29..29] Side-set data is asserted to pin OEs instead of pin - values */ - __IOM uint32_t SIDE_EN : 1; /*!< [30..30] If 1, the delay MSB is used as side-set enable, rather - than a - side-set data bit. This allows instructions to perform - side-set optionally, - rather than on every instruction. */ - __IM uint32_t EXEC_STALLED : 1; /*!< [31..31] An instruction written to SMx_INSTR is stalled, and - latched by the - state machine. Will clear once the instruction completes. */ - } bit; - } SM3_EXECCTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000118) Control behaviour of the input/output shift registers + __IOM uint32_t SM3_SHIFTCTRL; /*!< (@ 0x00000118) Control behaviour of the input/output shift registers for state machine 3 */ - - struct { - uint32_t : 16; - __IOM uint32_t AUTOPUSH : 1; /*!< [16..16] Push automatically when the input shift register is - filled */ - __IOM uint32_t AUTOPULL : 1; /*!< [17..17] Pull automatically when the output shift register is - emptied */ - __IOM uint32_t IN_SHIFTDIR : 1; /*!< [18..18] 1 = shift input shift register to right (data enters - from left). 0 = to left. */ - __IOM uint32_t OUT_SHIFTDIR : 1; /*!< [19..19] 1 = shift out of output shift register to right. 0 - = to left. */ - __IOM uint32_t PUSH_THRESH : 5; /*!< [24..20] Number of bits shifted into RXSR before autopush or - conditional push. - Write 0 for value of 32. */ - __IOM uint32_t PULL_THRESH : 5; /*!< [29..25] Number of bits shifted out of TXSR before autopull - or conditional pull. - Write 0 for value of 32. */ - __IOM uint32_t FJOIN_TX : 1; /*!< [30..30] When 1, TX FIFO steals the RX FIFO's storage, and becomes - twice as deep. - RX FIFO is disabled as a result (always reads as both full - and empty). - FIFOs are flushed when this bit is changed. */ - __IOM uint32_t FJOIN_RX : 1; /*!< [31..31] When 1, RX FIFO steals the TX FIFO's storage, and becomes - twice as deep. - TX FIFO is disabled as a result (always reads as both full - and empty). - FIFOs are flushed when this bit is changed. */ - } bit; - } SM3_SHIFTCTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000011C) Current instruction address of state machine + __IOM uint32_t SM3_ADDR; /*!< (@ 0x0000011C) Current instruction address of state machine 3 */ - - struct { - __IM uint32_t SM3_ADDR : 5; /*!< [4..0] SM3_ADDR */ - uint32_t : 27; - } bit; - } SM3_ADDR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000120) Instruction currently being executed by state - machine 3 + __IOM uint32_t SM3_INSTR; /*!< (@ 0x00000120) Read to see the instruction currently addressed + by state machine 3's program counter Write to execute an instruction immediately (including jumps) and then resume execution. */ - - struct { - __IOM uint32_t SM3_INSTR : 16; /*!< [15..0] SM3_INSTR */ - uint32_t : 16; - } bit; - } SM3_INSTR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000124) State machine pin control */ - - struct { - __IOM uint32_t OUT_BASE : 5; /*!< [4..0] The virtual pin corresponding to OUT bit 0 */ - __IOM uint32_t SET_BASE : 5; /*!< [9..5] The virtual pin corresponding to SET bit 0 */ - __IOM uint32_t SIDESET_BASE : 5; /*!< [14..10] The virtual pin corresponding to delay field bit 0 */ - __IOM uint32_t IN_BASE : 5; /*!< [19..15] The virtual pin corresponding to IN bit 0 */ - __IOM uint32_t OUT_COUNT : 6; /*!< [25..20] The number of pins asserted by an OUT. Value of 0 -> - 32 pins */ - __IOM uint32_t SET_COUNT : 3; /*!< [28..26] The number of pins asserted by a SET. Max of 5 */ - __IOM uint32_t SIDESET_COUNT : 3; /*!< [31..29] The number of delay bits co-opted for side-set. Inclusive - of the enable bit, if present. */ - } bit; - } SM3_PINCTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000128) Raw Interrupts */ - - struct { - __IM uint32_t SM0_RXNEMPTY : 1; /*!< [0..0] SM0_RXNEMPTY */ - __IM uint32_t SM1_RXNEMPTY : 1; /*!< [1..1] SM1_RXNEMPTY */ - __IM uint32_t SM2_RXNEMPTY : 1; /*!< [2..2] SM2_RXNEMPTY */ - __IM uint32_t SM3_RXNEMPTY : 1; /*!< [3..3] SM3_RXNEMPTY */ - __IM uint32_t SM0_TXNFULL : 1; /*!< [4..4] SM0_TXNFULL */ - __IM uint32_t SM1_TXNFULL : 1; /*!< [5..5] SM1_TXNFULL */ - __IM uint32_t SM2_TXNFULL : 1; /*!< [6..6] SM2_TXNFULL */ - __IM uint32_t SM3_TXNFULL : 1; /*!< [7..7] SM3_TXNFULL */ - __IM uint32_t SM0 : 1; /*!< [8..8] SM0 */ - __IM uint32_t SM1 : 1; /*!< [9..9] SM1 */ - __IM uint32_t SM2 : 1; /*!< [10..10] SM2 */ - __IM uint32_t SM3 : 1; /*!< [11..11] SM3 */ - uint32_t : 20; - } bit; - } INTR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000012C) Interrupt Enable for irq0 */ - - struct { - __IOM uint32_t SM0_RXNEMPTY : 1; /*!< [0..0] SM0_RXNEMPTY */ - __IOM uint32_t SM1_RXNEMPTY : 1; /*!< [1..1] SM1_RXNEMPTY */ - __IOM uint32_t SM2_RXNEMPTY : 1; /*!< [2..2] SM2_RXNEMPTY */ - __IOM uint32_t SM3_RXNEMPTY : 1; /*!< [3..3] SM3_RXNEMPTY */ - __IOM uint32_t SM0_TXNFULL : 1; /*!< [4..4] SM0_TXNFULL */ - __IOM uint32_t SM1_TXNFULL : 1; /*!< [5..5] SM1_TXNFULL */ - __IOM uint32_t SM2_TXNFULL : 1; /*!< [6..6] SM2_TXNFULL */ - __IOM uint32_t SM3_TXNFULL : 1; /*!< [7..7] SM3_TXNFULL */ - __IOM uint32_t SM0 : 1; /*!< [8..8] SM0 */ - __IOM uint32_t SM1 : 1; /*!< [9..9] SM1 */ - __IOM uint32_t SM2 : 1; /*!< [10..10] SM2 */ - __IOM uint32_t SM3 : 1; /*!< [11..11] SM3 */ - uint32_t : 20; - } bit; - } IRQ0_INTE; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000130) Interrupt Force for irq0 */ - - struct { - __IOM uint32_t SM0_RXNEMPTY : 1; /*!< [0..0] SM0_RXNEMPTY */ - __IOM uint32_t SM1_RXNEMPTY : 1; /*!< [1..1] SM1_RXNEMPTY */ - __IOM uint32_t SM2_RXNEMPTY : 1; /*!< [2..2] SM2_RXNEMPTY */ - __IOM uint32_t SM3_RXNEMPTY : 1; /*!< [3..3] SM3_RXNEMPTY */ - __IOM uint32_t SM0_TXNFULL : 1; /*!< [4..4] SM0_TXNFULL */ - __IOM uint32_t SM1_TXNFULL : 1; /*!< [5..5] SM1_TXNFULL */ - __IOM uint32_t SM2_TXNFULL : 1; /*!< [6..6] SM2_TXNFULL */ - __IOM uint32_t SM3_TXNFULL : 1; /*!< [7..7] SM3_TXNFULL */ - __IOM uint32_t SM0 : 1; /*!< [8..8] SM0 */ - __IOM uint32_t SM1 : 1; /*!< [9..9] SM1 */ - __IOM uint32_t SM2 : 1; /*!< [10..10] SM2 */ - __IOM uint32_t SM3 : 1; /*!< [11..11] SM3 */ - uint32_t : 20; - } bit; - } IRQ0_INTF; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000134) Interrupt status after masking & forcing for + __IOM uint32_t SM3_PINCTRL; /*!< (@ 0x00000124) State machine pin control */ + __IOM uint32_t INTR; /*!< (@ 0x00000128) Raw Interrupts */ + __IOM uint32_t IRQ0_INTE; /*!< (@ 0x0000012C) Interrupt Enable for irq0 */ + __IOM uint32_t IRQ0_INTF; /*!< (@ 0x00000130) Interrupt Force for irq0 */ + __IOM uint32_t IRQ0_INTS; /*!< (@ 0x00000134) Interrupt status after masking & forcing for irq0 */ - - struct { - __IM uint32_t SM0_RXNEMPTY : 1; /*!< [0..0] SM0_RXNEMPTY */ - __IM uint32_t SM1_RXNEMPTY : 1; /*!< [1..1] SM1_RXNEMPTY */ - __IM uint32_t SM2_RXNEMPTY : 1; /*!< [2..2] SM2_RXNEMPTY */ - __IM uint32_t SM3_RXNEMPTY : 1; /*!< [3..3] SM3_RXNEMPTY */ - __IM uint32_t SM0_TXNFULL : 1; /*!< [4..4] SM0_TXNFULL */ - __IM uint32_t SM1_TXNFULL : 1; /*!< [5..5] SM1_TXNFULL */ - __IM uint32_t SM2_TXNFULL : 1; /*!< [6..6] SM2_TXNFULL */ - __IM uint32_t SM3_TXNFULL : 1; /*!< [7..7] SM3_TXNFULL */ - __IM uint32_t SM0 : 1; /*!< [8..8] SM0 */ - __IM uint32_t SM1 : 1; /*!< [9..9] SM1 */ - __IM uint32_t SM2 : 1; /*!< [10..10] SM2 */ - __IM uint32_t SM3 : 1; /*!< [11..11] SM3 */ - uint32_t : 20; - } bit; - } IRQ0_INTS; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000138) Interrupt Enable for irq1 */ - - struct { - __IOM uint32_t SM0_RXNEMPTY : 1; /*!< [0..0] SM0_RXNEMPTY */ - __IOM uint32_t SM1_RXNEMPTY : 1; /*!< [1..1] SM1_RXNEMPTY */ - __IOM uint32_t SM2_RXNEMPTY : 1; /*!< [2..2] SM2_RXNEMPTY */ - __IOM uint32_t SM3_RXNEMPTY : 1; /*!< [3..3] SM3_RXNEMPTY */ - __IOM uint32_t SM0_TXNFULL : 1; /*!< [4..4] SM0_TXNFULL */ - __IOM uint32_t SM1_TXNFULL : 1; /*!< [5..5] SM1_TXNFULL */ - __IOM uint32_t SM2_TXNFULL : 1; /*!< [6..6] SM2_TXNFULL */ - __IOM uint32_t SM3_TXNFULL : 1; /*!< [7..7] SM3_TXNFULL */ - __IOM uint32_t SM0 : 1; /*!< [8..8] SM0 */ - __IOM uint32_t SM1 : 1; /*!< [9..9] SM1 */ - __IOM uint32_t SM2 : 1; /*!< [10..10] SM2 */ - __IOM uint32_t SM3 : 1; /*!< [11..11] SM3 */ - uint32_t : 20; - } bit; - } IRQ1_INTE; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000013C) Interrupt Force for irq1 */ - - struct { - __IOM uint32_t SM0_RXNEMPTY : 1; /*!< [0..0] SM0_RXNEMPTY */ - __IOM uint32_t SM1_RXNEMPTY : 1; /*!< [1..1] SM1_RXNEMPTY */ - __IOM uint32_t SM2_RXNEMPTY : 1; /*!< [2..2] SM2_RXNEMPTY */ - __IOM uint32_t SM3_RXNEMPTY : 1; /*!< [3..3] SM3_RXNEMPTY */ - __IOM uint32_t SM0_TXNFULL : 1; /*!< [4..4] SM0_TXNFULL */ - __IOM uint32_t SM1_TXNFULL : 1; /*!< [5..5] SM1_TXNFULL */ - __IOM uint32_t SM2_TXNFULL : 1; /*!< [6..6] SM2_TXNFULL */ - __IOM uint32_t SM3_TXNFULL : 1; /*!< [7..7] SM3_TXNFULL */ - __IOM uint32_t SM0 : 1; /*!< [8..8] SM0 */ - __IOM uint32_t SM1 : 1; /*!< [9..9] SM1 */ - __IOM uint32_t SM2 : 1; /*!< [10..10] SM2 */ - __IOM uint32_t SM3 : 1; /*!< [11..11] SM3 */ - uint32_t : 20; - } bit; - } IRQ1_INTF; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000140) Interrupt status after masking & forcing for + __IOM uint32_t IRQ1_INTE; /*!< (@ 0x00000138) Interrupt Enable for irq1 */ + __IOM uint32_t IRQ1_INTF; /*!< (@ 0x0000013C) Interrupt Force for irq1 */ + __IOM uint32_t IRQ1_INTS; /*!< (@ 0x00000140) Interrupt status after masking & forcing for irq1 */ - - struct { - __IM uint32_t SM0_RXNEMPTY : 1; /*!< [0..0] SM0_RXNEMPTY */ - __IM uint32_t SM1_RXNEMPTY : 1; /*!< [1..1] SM1_RXNEMPTY */ - __IM uint32_t SM2_RXNEMPTY : 1; /*!< [2..2] SM2_RXNEMPTY */ - __IM uint32_t SM3_RXNEMPTY : 1; /*!< [3..3] SM3_RXNEMPTY */ - __IM uint32_t SM0_TXNFULL : 1; /*!< [4..4] SM0_TXNFULL */ - __IM uint32_t SM1_TXNFULL : 1; /*!< [5..5] SM1_TXNFULL */ - __IM uint32_t SM2_TXNFULL : 1; /*!< [6..6] SM2_TXNFULL */ - __IM uint32_t SM3_TXNFULL : 1; /*!< [7..7] SM3_TXNFULL */ - __IM uint32_t SM0 : 1; /*!< [8..8] SM0 */ - __IM uint32_t SM1 : 1; /*!< [9..9] SM1 */ - __IM uint32_t SM2 : 1; /*!< [10..10] SM2 */ - __IM uint32_t SM3 : 1; /*!< [11..11] SM3 */ - uint32_t : 20; - } bit; - } IRQ1_INTS; } PIO0_Type; /*!< Size = 324 (0x144) */ @@ -13740,215 +2837,26 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur __IM uint32_t CPUID; /*!< (@ 0x00000000) Processor core identifier Value is 0 when read from processor core 0, and 1 when read from processor core 1. */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000004) Input value for GPIO pins */ - - struct { - __IM uint32_t GPIO_IN : 30; /*!< [29..0] Input value for GPIO0...29 */ - uint32_t : 2; - } bit; - } GPIO_IN; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000008) Input value for QSPI pins */ - - struct { - __IM uint32_t GPIO_HI_IN : 6; /*!< [5..0] Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, - SD1, SD2, SD3 */ - uint32_t : 26; - } bit; - } GPIO_HI_IN; + __IOM uint32_t GPIO_IN; /*!< (@ 0x00000004) Input value for GPIO pins */ + __IOM uint32_t GPIO_HI_IN; /*!< (@ 0x00000008) Input value for QSPI pins */ __IM uint32_t RESERVED; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000010) GPIO output value */ - - struct { - __IOM uint32_t GPIO_OUT : 30; /*!< [29..0] Set output level (1/0 -> high/low) for GPIO0...29. - Reading back gives the last value written, NOT the input - value from the pins. - If core 0 and core 1 both write to GPIO_OUT simultaneously - (or to a SET/CLR/XOR alias), - the result is as though the write from core 0 took place - first, - and the write from core 1 was then applied to that intermediate - result. */ - uint32_t : 2; - } bit; - } GPIO_OUT; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000014) GPIO output value set */ - - struct { - __IOM uint32_t GPIO_OUT_SET : 30; /*!< [29..0] Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT - |= wdata` */ - uint32_t : 2; - } bit; - } GPIO_OUT_SET; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000018) GPIO output value clear */ - - struct { - __IOM uint32_t GPIO_OUT_CLR : 30; /*!< [29..0] Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT - &= ~wdata` */ - uint32_t : 2; - } bit; - } GPIO_OUT_CLR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000001C) GPIO output value XOR */ - - struct { - __IOM uint32_t GPIO_OUT_XOR : 30; /*!< [29..0] Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT - ^= wdata` */ - uint32_t : 2; - } bit; - } GPIO_OUT_XOR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000020) GPIO output enable */ - - struct { - __IOM uint32_t GPIO_OE : 30; /*!< [29..0] Set output enable (1/0 -> output/input) for GPIO0...29. - Reading back gives the last value written. - If core 0 and core 1 both write to GPIO_OE simultaneously - (or to a SET/CLR/XOR alias), - the result is as though the write from core 0 took place - first, - and the write from core 1 was then applied to that intermediate - result. */ - uint32_t : 2; - } bit; - } GPIO_OE; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000024) GPIO output enable set */ - - struct { - __IOM uint32_t GPIO_OE_SET : 30; /*!< [29..0] Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE - |= wdata` */ - uint32_t : 2; - } bit; - } GPIO_OE_SET; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000028) GPIO output enable clear */ - - struct { - __IOM uint32_t GPIO_OE_CLR : 30; /*!< [29..0] Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE - &= ~wdata` */ - uint32_t : 2; - } bit; - } GPIO_OE_CLR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000002C) GPIO output enable XOR */ - - struct { - __IOM uint32_t GPIO_OE_XOR : 30; /*!< [29..0] Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE - ^= wdata` */ - uint32_t : 2; - } bit; - } GPIO_OE_XOR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000030) QSPI output value */ - - struct { - __IOM uint32_t GPIO_HI_OUT : 6; /*!< [5..0] Set output level (1/0 -> high/low) for QSPI IO0...5. - Reading back gives the last value written, NOT the input - value from the pins. - If core 0 and core 1 both write to GPIO_HI_OUT simultaneously - (or to a SET/CLR/XOR alias), - the result is as though the write from core 0 took place - first, - and the write from core 1 was then applied to that intermediate - result. */ - uint32_t : 26; - } bit; - } GPIO_HI_OUT; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000034) QSPI output value set */ - - struct { - __IOM uint32_t GPIO_HI_OUT_SET : 6; /*!< [5..0] Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT - |= wdata` */ - uint32_t : 26; - } bit; - } GPIO_HI_OUT_SET; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000038) QSPI output value clear */ - - struct { - __IOM uint32_t GPIO_HI_OUT_CLR : 6; /*!< [5..0] Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT - &= ~wdata` */ - uint32_t : 26; - } bit; - } GPIO_HI_OUT_CLR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000003C) QSPI output value XOR */ - - struct { - __IOM uint32_t GPIO_HI_OUT_XOR : 6; /*!< [5..0] Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT - ^= wdata` */ - uint32_t : 26; - } bit; - } GPIO_HI_OUT_XOR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000040) QSPI output enable */ - - struct { - __IOM uint32_t GPIO_HI_OE : 6; /*!< [5..0] Set output enable (1/0 -> output/input) for QSPI IO0...5. - Reading back gives the last value written. - If core 0 and core 1 both write to GPIO_HI_OE simultaneously - (or to a SET/CLR/XOR alias), - the result is as though the write from core 0 took place - first, - and the write from core 1 was then applied to that intermediate - result. */ - uint32_t : 26; - } bit; - } GPIO_HI_OE; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000044) QSPI output enable set */ - - struct { - __IOM uint32_t GPIO_HI_OE_SET : 6; /*!< [5..0] Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE - |= wdata` */ - uint32_t : 26; - } bit; - } GPIO_HI_OE_SET; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000048) QSPI output enable clear */ - - struct { - __IOM uint32_t GPIO_HI_OE_CLR : 6; /*!< [5..0] Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE - &= ~wdata` */ - uint32_t : 26; - } bit; - } GPIO_HI_OE_CLR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000004C) QSPI output enable XOR */ - - struct { - __IOM uint32_t GPIO_HI_OE_XOR : 6; /*!< [5..0] Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE - ^= wdata` */ - uint32_t : 26; - } bit; - } GPIO_HI_OE_XOR; - - union { - __IOM uint32_t reg; /*!< (@ 0x00000050) Status register for inter-core FIFOs (mailboxes). + __IOM uint32_t GPIO_OUT; /*!< (@ 0x00000010) GPIO output value */ + __IOM uint32_t GPIO_OUT_SET; /*!< (@ 0x00000014) GPIO output value set */ + __IOM uint32_t GPIO_OUT_CLR; /*!< (@ 0x00000018) GPIO output value clear */ + __IOM uint32_t GPIO_OUT_XOR; /*!< (@ 0x0000001C) GPIO output value XOR */ + __IOM uint32_t GPIO_OE; /*!< (@ 0x00000020) GPIO output enable */ + __IOM uint32_t GPIO_OE_SET; /*!< (@ 0x00000024) GPIO output enable set */ + __IOM uint32_t GPIO_OE_CLR; /*!< (@ 0x00000028) GPIO output enable clear */ + __IOM uint32_t GPIO_OE_XOR; /*!< (@ 0x0000002C) GPIO output enable XOR */ + __IOM uint32_t GPIO_HI_OUT; /*!< (@ 0x00000030) QSPI output value */ + __IOM uint32_t GPIO_HI_OUT_SET; /*!< (@ 0x00000034) QSPI output value set */ + __IOM uint32_t GPIO_HI_OUT_CLR; /*!< (@ 0x00000038) QSPI output value clear */ + __IOM uint32_t GPIO_HI_OUT_XOR; /*!< (@ 0x0000003C) QSPI output value XOR */ + __IOM uint32_t GPIO_HI_OE; /*!< (@ 0x00000040) QSPI output enable */ + __IOM uint32_t GPIO_HI_OE_SET; /*!< (@ 0x00000044) QSPI output enable set */ + __IOM uint32_t GPIO_HI_OE_CLR; /*!< (@ 0x00000048) QSPI output enable clear */ + __IOM uint32_t GPIO_HI_OE_XOR; /*!< (@ 0x0000004C) QSPI output enable XOR */ + __IOM uint32_t FIFO_ST; /*!< (@ 0x00000050) Status register for inter-core FIFOs (mailboxes). There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. @@ -13960,20 +2868,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur (TX). The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its - FIF */ - - struct { - __IM uint32_t VLD : 1; /*!< [0..0] Value is 1 if this core's RX FIFO is not empty (i.e. - if FIFO_RD is valid) */ - __IM uint32_t RDY : 1; /*!< [1..1] Value is 1 if this core's TX FIFO is not full (i.e. if - FIFO_WR is ready for more data) */ - __IOM uint32_t WOF : 1; /*!< [2..2] Sticky flag indicating the TX FIFO was written when full. - This write was ignored by the FIFO. */ - __IOM uint32_t ROE : 1; /*!< [3..3] Sticky flag indicating the RX FIFO was read when empty. - This read was ignored by the FIFO. */ - uint32_t : 28; - } bit; - } FIFO_ST; + FIFO_ */ __OM uint32_t FIFO_WR; /*!< (@ 0x00000054) Write access to this core's TX FIFO */ __IM uint32_t FIFO_RD; /*!< (@ 0x00000058) Read access to this core's RX FIFO */ __IM uint32_t SPINLOCK_ST; /*!< (@ 0x0000005C) Spinlock state @@ -13994,7 +2889,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur i.e. the q in `p / q`. Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. - UDIVIDEND/SDIVIDEND are aliases of the same + UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an unsigned calculation, and the S alias starts a signed calculation. */ @@ -14015,7 +2910,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. Reading from QUOTIENT clears the CSR_DIRTY - flag, so */ + flag, so sh */ __IOM uint32_t DIV_REMAINDER; /*!< (@ 0x00000074) Divider result remainder The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low. @@ -14026,29 +2921,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur halts any in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. */ - - union { - __IOM uint32_t reg; /*!< (@ 0x00000078) Control and status register for divider. */ - - struct { - __IM uint32_t READY : 1; /*!< [0..0] Reads as 0 when a calculation is in progress, 1 otherwise. - Writing an operand (xDIVIDEND, xDIVISOR) will immediately - start a new calculation, no - matter if one is already in progress. - Writing to a result register will immediately terminate - any in-progress calculation - and set the READY and DIRTY flags. */ - __IM uint32_t DIRTY : 1; /*!< [1..1] Changes to 1 when any register is written, and back to - 0 when QUOTIENT is read. - Software can use this flag to make save/restore more efficient - (skip if not DIRTY). - If the flag is used in this way, it's recommended to either - read QUOTIENT only, - or REMAINDER and then QUOTIENT, to prevent data loss on - context switch. */ - uint32_t : 30; - } bit; - } DIV_CSR; + __IOM uint32_t DIV_CSR; /*!< (@ 0x00000078) Control and status register for divider. */ __IM uint32_t RESERVED1; __IOM uint32_t INTERP0_ACCUM0; /*!< (@ 0x00000080) Read/write access to accumulator 0 */ __IOM uint32_t INTERP0_ACCUM1; /*!< (@ 0x00000084) Read/write access to accumulator 1 */ @@ -14067,107 +2940,15 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur state (PEEK). */ __IM uint32_t INTERP0_PEEK_FULL; /*!< (@ 0x000000A8) Read FULL result, without altering any internal state (PEEK). */ - - union { - __IOM uint32_t reg; /*!< (@ 0x000000AC) Control register for lane 0 */ - - struct { - __IOM uint32_t SHIFT : 5; /*!< [4..0] Logical right-shift applied to accumulator before masking */ - __IOM uint32_t MASK_LSB : 5; /*!< [9..5] The least-significant bit allowed to pass by the mask - (inclusive) */ - __IOM uint32_t MASK_MSB : 5; /*!< [14..10] The most-significant bit allowed to pass by the mask - (inclusive) - Setting MSB < LSB may cause chip to turn inside-out */ - __IOM uint32_t SIGNED : 1; /*!< [15..15] If SIGNED is set, the shifted and masked accumulator - value is sign-extended to 32 bits - before adding to BASE0, and LANE0 PEEK/POP appear extended - to 32 bits when read by processor. */ - __IOM uint32_t CROSS_INPUT : 1; /*!< [16..16] If 1, feed the opposite lane's accumulator into this - lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux - is before the shift+mask bypass) */ - __IOM uint32_t CROSS_RESULT : 1; /*!< [17..17] If 1, feed the opposite lane's result into this lane's - accumulator on POP. */ - __IOM uint32_t ADD_RAW : 1; /*!< [18..18] If 1, mask + shift is bypassed for LANE0 result. This - does not affect FULL result. */ - __IOM uint32_t FORCE_MSB : 2; /*!< [20..19] ORed into bits 29:28 of the lane result presented to - the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using - a lane to generate sequence - of pointers into flash or SRAM. */ - __IOM uint32_t BLEND : 1; /*!< [21..21] Only present on INTERP0 on each core. If BLEND mode - is enabled: - - LANE1 result is a linear interpolation between BASE0 - and BASE1, controlled - by the 8 LSBs of lane 1 shift and mask value (a fractional - number between - 0 and 255/256ths) - - LANE0 result does not have BASE0 added (yields only the - 8 LSBs of lane 1 shift+mask value) - - FULL result does not have lane 1 shift+mask value added - (BASE2 + lane 0 shift+mask) - */ - uint32_t : 1; - __IM uint32_t OVERF0 : 1; /*!< [23..23] Indicates if any masked-off MSBs in ACCUM0 are set. */ - __IM uint32_t OVERF1 : 1; /*!< [24..24] Indicates if any masked-off MSBs in ACCUM1 are set. */ - __IM uint32_t OVERF : 1; /*!< [25..25] Set if either OVERF0 or OVERF1 is set. */ - uint32_t : 6; - } bit; - } INTERP0_CTRL_LANE0; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000B0) Control register for lane 1 */ - - struct { - __IOM uint32_t SHIFT : 5; /*!< [4..0] Logical right-shift applied to accumulator before masking */ - __IOM uint32_t MASK_LSB : 5; /*!< [9..5] The least-significant bit allowed to pass by the mask - (inclusive) */ - __IOM uint32_t MASK_MSB : 5; /*!< [14..10] The most-significant bit allowed to pass by the mask - (inclusive) - Setting MSB < LSB may cause chip to turn inside-out */ - __IOM uint32_t SIGNED : 1; /*!< [15..15] If SIGNED is set, the shifted and masked accumulator - value is sign-extended to 32 bits - before adding to BASE1, and LANE1 PEEK/POP appear extended - to 32 bits when read by processor. */ - __IOM uint32_t CROSS_INPUT : 1; /*!< [16..16] If 1, feed the opposite lane's accumulator into this - lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux - is before the shift+mask bypass) */ - __IOM uint32_t CROSS_RESULT : 1; /*!< [17..17] If 1, feed the opposite lane's result into this lane's - accumulator on POP. */ - __IOM uint32_t ADD_RAW : 1; /*!< [18..18] If 1, mask + shift is bypassed for LANE1 result. This - does not affect FULL result. */ - __IOM uint32_t FORCE_MSB : 2; /*!< [20..19] ORed into bits 29:28 of the lane result presented to - the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using - a lane to generate sequence - of pointers into flash or SRAM. */ - uint32_t : 11; - } bit; - } INTERP0_CTRL_LANE1; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000B4) Values written here are atomically added to ACCUM0 + __IOM uint32_t INTERP0_CTRL_LANE0; /*!< (@ 0x000000AC) Control register for lane 0 */ + __IOM uint32_t INTERP0_CTRL_LANE1; /*!< (@ 0x000000B0) Control register for lane 1 */ + __IOM uint32_t INTERP0_ACCUM0_ADD; /*!< (@ 0x000000B4) Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added). */ - - struct { - __IOM uint32_t INTERP0_ACCUM0_ADD : 24; /*!< [23..0] INTERP0_ACCUM0_ADD */ - uint32_t : 8; - } bit; - } INTERP0_ACCUM0_ADD; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000B8) Values written here are atomically added to ACCUM1 + __IOM uint32_t INTERP0_ACCUM1_ADD; /*!< (@ 0x000000B8) Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added). */ - - struct { - __IOM uint32_t INTERP0_ACCUM1_ADD : 24; /*!< [23..0] INTERP0_ACCUM1_ADD */ - uint32_t : 8; - } bit; - } INTERP0_ACCUM1_ADD; - __IOM uint32_t INTERP0_BASE_1AND0; /*!< (@ 0x000000BC) On write, the lower 16 bits go to BASE0, upper + __OM uint32_t INTERP0_BASE_1AND0; /*!< (@ 0x000000BC) On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. */ @@ -14188,105 +2969,19 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur state (PEEK). */ __IM uint32_t INTERP1_PEEK_FULL; /*!< (@ 0x000000E8) Read FULL result, without altering any internal state (PEEK). */ - - union { - __IOM uint32_t reg; /*!< (@ 0x000000EC) Control register for lane 0 */ - - struct { - __IOM uint32_t SHIFT : 5; /*!< [4..0] Logical right-shift applied to accumulator before masking */ - __IOM uint32_t MASK_LSB : 5; /*!< [9..5] The least-significant bit allowed to pass by the mask - (inclusive) */ - __IOM uint32_t MASK_MSB : 5; /*!< [14..10] The most-significant bit allowed to pass by the mask - (inclusive) - Setting MSB < LSB may cause chip to turn inside-out */ - __IOM uint32_t SIGNED : 1; /*!< [15..15] If SIGNED is set, the shifted and masked accumulator - value is sign-extended to 32 bits - before adding to BASE0, and LANE0 PEEK/POP appear extended - to 32 bits when read by processor. */ - __IOM uint32_t CROSS_INPUT : 1; /*!< [16..16] If 1, feed the opposite lane's accumulator into this - lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux - is before the shift+mask bypass) */ - __IOM uint32_t CROSS_RESULT : 1; /*!< [17..17] If 1, feed the opposite lane's result into this lane's - accumulator on POP. */ - __IOM uint32_t ADD_RAW : 1; /*!< [18..18] If 1, mask + shift is bypassed for LANE0 result. This - does not affect FULL result. */ - __IOM uint32_t FORCE_MSB : 2; /*!< [20..19] ORed into bits 29:28 of the lane result presented to - the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using - a lane to generate sequence - of pointers into flash or SRAM. */ - uint32_t : 1; - __IOM uint32_t CLAMP : 1; /*!< [22..22] Only present on INTERP1 on each core. If CLAMP mode - is enabled: - - LANE0 result is shifted and masked ACCUM0, clamped by - a lower bound of - BASE0 and an upper bound of BASE1. - - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED */ - __IM uint32_t OVERF0 : 1; /*!< [23..23] Indicates if any masked-off MSBs in ACCUM0 are set. */ - __IM uint32_t OVERF1 : 1; /*!< [24..24] Indicates if any masked-off MSBs in ACCUM1 are set. */ - __IM uint32_t OVERF : 1; /*!< [25..25] Set if either OVERF0 or OVERF1 is set. */ - uint32_t : 6; - } bit; - } INTERP1_CTRL_LANE0; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000F0) Control register for lane 1 */ - - struct { - __IOM uint32_t SHIFT : 5; /*!< [4..0] Logical right-shift applied to accumulator before masking */ - __IOM uint32_t MASK_LSB : 5; /*!< [9..5] The least-significant bit allowed to pass by the mask - (inclusive) */ - __IOM uint32_t MASK_MSB : 5; /*!< [14..10] The most-significant bit allowed to pass by the mask - (inclusive) - Setting MSB < LSB may cause chip to turn inside-out */ - __IOM uint32_t SIGNED : 1; /*!< [15..15] If SIGNED is set, the shifted and masked accumulator - value is sign-extended to 32 bits - before adding to BASE1, and LANE1 PEEK/POP appear extended - to 32 bits when read by processor. */ - __IOM uint32_t CROSS_INPUT : 1; /*!< [16..16] If 1, feed the opposite lane's accumulator into this - lane's shift + mask hardware. - Takes effect even if ADD_RAW is set (the CROSS_INPUT mux - is before the shift+mask bypass) */ - __IOM uint32_t CROSS_RESULT : 1; /*!< [17..17] If 1, feed the opposite lane's result into this lane's - accumulator on POP. */ - __IOM uint32_t ADD_RAW : 1; /*!< [18..18] If 1, mask + shift is bypassed for LANE1 result. This - does not affect FULL result. */ - __IOM uint32_t FORCE_MSB : 2; /*!< [20..19] ORed into bits 29:28 of the lane result presented to - the processor on the bus. - No effect on the internal 32-bit datapath. Handy for using - a lane to generate sequence - of pointers into flash or SRAM. */ - uint32_t : 11; - } bit; - } INTERP1_CTRL_LANE1; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000F4) Values written here are atomically added to ACCUM0 + __IOM uint32_t INTERP1_CTRL_LANE0; /*!< (@ 0x000000EC) Control register for lane 0 */ + __IOM uint32_t INTERP1_CTRL_LANE1; /*!< (@ 0x000000F0) Control register for lane 1 */ + __IOM uint32_t INTERP1_ACCUM0_ADD; /*!< (@ 0x000000F4) Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added). */ - - struct { - __IOM uint32_t INTERP1_ACCUM0_ADD : 24; /*!< [23..0] INTERP1_ACCUM0_ADD */ - uint32_t : 8; - } bit; - } INTERP1_ACCUM0_ADD; - - union { - __IOM uint32_t reg; /*!< (@ 0x000000F8) Values written here are atomically added to ACCUM1 + __IOM uint32_t INTERP1_ACCUM1_ADD; /*!< (@ 0x000000F8) Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added). */ - - struct { - __IOM uint32_t INTERP1_ACCUM1_ADD : 24; /*!< [23..0] INTERP1_ACCUM1_ADD */ - uint32_t : 8; - } bit; - } INTERP1_ACCUM1_ADD; - __IOM uint32_t INTERP1_BASE_1AND0; /*!< (@ 0x000000FC) On write, the lower 16 bits go to BASE0, upper + __OM uint32_t INTERP1_BASE_1AND0; /*!< (@ 0x000000FC) On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. */ - __IM uint32_t SPINLOCK0; /*!< (@ 0x00000100) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK0; /*!< (@ 0x00000100) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14296,7 +2991,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK1; /*!< (@ 0x00000104) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK1; /*!< (@ 0x00000104) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14306,7 +3001,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK2; /*!< (@ 0x00000108) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK2; /*!< (@ 0x00000108) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14316,7 +3011,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK3; /*!< (@ 0x0000010C) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK3; /*!< (@ 0x0000010C) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14326,7 +3021,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK4; /*!< (@ 0x00000110) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK4; /*!< (@ 0x00000110) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14336,7 +3031,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK5; /*!< (@ 0x00000114) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK5; /*!< (@ 0x00000114) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14346,7 +3041,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK6; /*!< (@ 0x00000118) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK6; /*!< (@ 0x00000118) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14356,7 +3051,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK7; /*!< (@ 0x0000011C) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK7; /*!< (@ 0x0000011C) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14366,7 +3061,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK8; /*!< (@ 0x00000120) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK8; /*!< (@ 0x00000120) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14376,7 +3071,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK9; /*!< (@ 0x00000124) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK9; /*!< (@ 0x00000124) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14386,7 +3081,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK10; /*!< (@ 0x00000128) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK10; /*!< (@ 0x00000128) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14396,7 +3091,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK11; /*!< (@ 0x0000012C) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK11; /*!< (@ 0x0000012C) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14406,7 +3101,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK12; /*!< (@ 0x00000130) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK12; /*!< (@ 0x00000130) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14416,7 +3111,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK13; /*!< (@ 0x00000134) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK13; /*!< (@ 0x00000134) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14426,7 +3121,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK14; /*!< (@ 0x00000138) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK14; /*!< (@ 0x00000138) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14436,7 +3131,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK15; /*!< (@ 0x0000013C) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK15; /*!< (@ 0x0000013C) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14446,7 +3141,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK16; /*!< (@ 0x00000140) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK16; /*!< (@ 0x00000140) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14456,7 +3151,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK17; /*!< (@ 0x00000144) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK17; /*!< (@ 0x00000144) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14466,7 +3161,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK18; /*!< (@ 0x00000148) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK18; /*!< (@ 0x00000148) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14476,7 +3171,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK19; /*!< (@ 0x0000014C) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK19; /*!< (@ 0x0000014C) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14486,7 +3181,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK20; /*!< (@ 0x00000150) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK20; /*!< (@ 0x00000150) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14496,7 +3191,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK21; /*!< (@ 0x00000154) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK21; /*!< (@ 0x00000154) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14506,7 +3201,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK22; /*!< (@ 0x00000158) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK22; /*!< (@ 0x00000158) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14516,7 +3211,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK23; /*!< (@ 0x0000015C) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK23; /*!< (@ 0x0000015C) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14526,7 +3221,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK24; /*!< (@ 0x00000160) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK24; /*!< (@ 0x00000160) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14536,7 +3231,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK25; /*!< (@ 0x00000164) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK25; /*!< (@ 0x00000164) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14546,7 +3241,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK26; /*!< (@ 0x00000168) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK26; /*!< (@ 0x00000168) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14556,7 +3251,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK27; /*!< (@ 0x0000016C) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK27; /*!< (@ 0x0000016C) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14566,7 +3261,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK28; /*!< (@ 0x00000170) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK28; /*!< (@ 0x00000170) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14576,7 +3271,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK29; /*!< (@ 0x00000174) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK29; /*!< (@ 0x00000174) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14586,7 +3281,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK30; /*!< (@ 0x00000178) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK30; /*!< (@ 0x00000178) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14596,7 +3291,7 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. */ - __IM uint32_t SPINLOCK31; /*!< (@ 0x0000017C) Reading from a spinlock address will: + __IOM uint32_t SPINLOCK31; /*!< (@ 0x0000017C) Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock @@ -14621,34 +3316,9 @@ typedef struct { /*!< (@ 0xD0000000) SIO Structur typedef struct { /*!< (@ 0xE0000000) PPB Structure */ __IM uint32_t RESERVED[14340]; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000E010) Use the SysTick Control and Status Register to + __IOM uint32_t SYST_CSR; /*!< (@ 0x0000E010) Use the SysTick Control and Status Register to enable the SysTick features. */ - - struct { - __IOM uint32_t ENABLE : 1; /*!< [0..0] Enable SysTick counter: - 0 = Counter disabled. - 1 = Counter enabled. */ - __IOM uint32_t TICKINT : 1; /*!< [1..1] Enables SysTick exception request: - 0 = Counting down to zero does not assert the SysTick exception - request. - 1 = Counting down to zero to asserts the SysTick exception - request. */ - __IOM uint32_t CLKSOURCE : 1; /*!< [2..2] SysTick clock source. Always reads as one if SYST_CALIB - reports NOREF. - Selects the SysTick timer clock source: - 0 = External reference clock. - 1 = Processor clock. */ - uint32_t : 13; - __IM uint32_t COUNTFLAG : 1; /*!< [16..16] Returns 1 if timer counted to 0 since last time this - was read. Clears on read by application or debugger. */ - uint32_t : 15; - } bit; - } SYST_CSR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000E014) Use the SysTick Reload Value Register to specify + __IOM uint32_t SYST_RVR; /*!< (@ 0x0000E014) Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. @@ -14659,50 +3329,15 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur is UNKNOWN. To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD - value of N-1. For example, if the */ - - struct { - __IOM uint32_t RELOAD : 24; /*!< [23..0] Value to load into the SysTick Current Value Register - when the counter reaches 0. */ - uint32_t : 8; - } bit; - } SYST_RVR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000E018) Use the SysTick Current Value Register to find + value of N-1. For example, if the S */ + __IOM uint32_t SYST_CVR; /*!< (@ 0x0000E018) Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN. */ - - struct { - __IOM uint32_t CURRENT : 24; /*!< [23..0] Reads return the current value of the SysTick counter. - This register is write-clear. Writing to it with any value - clears the register to 0. Clearing this register also clears - the COUNTFLAG bit of the SysTick Control and Status Register. */ - uint32_t : 8; - } bit; - } SYST_CVR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000E01C) Use the SysTick Calibration Value Register to + __IOM uint32_t SYST_CALIB; /*!< (@ 0x0000E01C) Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply. */ - - struct { - __IM uint32_t TENMS : 24; /*!< [23..0] An optional Reload value to be used for 10ms (100Hz) - timing, subject to system clock skew errors. If the value - reads as 0, the calibration value is not known. */ - uint32_t : 6; - __IM uint32_t SKEW : 1; /*!< [30..30] If reads as 1, the calibration value for 10ms is inexact - (due to clock frequency). */ - __IM uint32_t NOREF : 1; /*!< [31..31] If reads as 1, the Reference clock is not provided - - the CLKSOURCE bit of the SysTick Control and Status register - will be forced to 1 and cannot be cleared to 0. */ - } bit; - } SYST_CALIB; __IM uint32_t RESERVED1[56]; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000E100) Use the Interrupt Set-Enable Register to enable + __IOM uint32_t NVIC_ISER; /*!< (@ 0x0000E100) Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled. If a pending interrupt is enabled, the NVIC @@ -14711,75 +3346,19 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. */ - - struct { - __IOM uint32_t SETENA : 32; /*!< [31..0] Interrupt set-enable bits. - Write: - 0 = No effect. - 1 = Enable interrupt. - Read: - 0 = Interrupt disabled. - 1 = Interrupt enabled. */ - } bit; - } NVIC_ISER; __IM uint32_t RESERVED2[31]; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000E180) Use the Interrupt Clear-Enable Registers to disable + __IOM uint32_t NVIC_ICER; /*!< (@ 0x0000E180) Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled. */ - - struct { - __IOM uint32_t CLRENA : 32; /*!< [31..0] Interrupt clear-enable bits. - Write: - 0 = No effect. - 1 = Disable interrupt. - Read: - 0 = Interrupt disabled. - 1 = Interrupt enabled. */ - } bit; - } NVIC_ICER; __IM uint32_t RESERVED3[31]; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000E200) The NVIC_ISPR forces interrupts into the pending + __IOM uint32_t NVIC_ISPR; /*!< (@ 0x0000E200) The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending. */ - - struct { - __IOM uint32_t SETPEND : 32; /*!< [31..0] Interrupt set-pending bits. - Write: - 0 = No effect. - 1 = Changes interrupt state to pending. - Read: - 0 = Interrupt is not pending. - 1 = Interrupt is pending. - Note: Writing 1 to the NVIC_ISPR bit corresponding to: - An interrupt that is pending has no effect. - A disabled interrupt sets the state of that interrupt to - pending. */ - } bit; - } NVIC_ISPR; __IM uint32_t RESERVED4[31]; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000E280) Use the Interrupt Clear-Pending Register to clear + __IOM uint32_t NVIC_ICPR; /*!< (@ 0x0000E280) Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending. */ - - struct { - __IOM uint32_t CLRPEND : 32; /*!< [31..0] Interrupt clear-pending bits. - Write: - 0 = No effect. - 1 = Removes pending state and interrupt. - Read: - 0 = Interrupt is not pending. - 1 = Interrupt is pending. */ - } bit; - } NVIC_ICPR; __IM uint32_t RESERVED5[95]; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000E400) Use the Interrupt Priority Registers to assign + __IOM uint32_t NVIC_IPR0; /*!< (@ 0x0000E400) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. @@ -14787,483 +3366,96 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur not affect the active state of the corresponding interrupt. These registers are only word-accessible */ - - struct { - uint32_t : 6; - __IOM uint32_t IP_0 : 2; /*!< [7..6] Priority of interrupt 0 */ - uint32_t : 6; - __IOM uint32_t IP_1 : 2; /*!< [15..14] Priority of interrupt 1 */ - uint32_t : 6; - __IOM uint32_t IP_2 : 2; /*!< [23..22] Priority of interrupt 2 */ - uint32_t : 6; - __IOM uint32_t IP_3 : 2; /*!< [31..30] Priority of interrupt 3 */ - } bit; - } NVIC_IPR0; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000E404) Use the Interrupt Priority Registers to assign + __IOM uint32_t NVIC_IPR1; /*!< (@ 0x0000E404) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. */ - - struct { - uint32_t : 6; - __IOM uint32_t IP_4 : 2; /*!< [7..6] Priority of interrupt 4 */ - uint32_t : 6; - __IOM uint32_t IP_5 : 2; /*!< [15..14] Priority of interrupt 5 */ - uint32_t : 6; - __IOM uint32_t IP_6 : 2; /*!< [23..22] Priority of interrupt 6 */ - uint32_t : 6; - __IOM uint32_t IP_7 : 2; /*!< [31..30] Priority of interrupt 7 */ - } bit; - } NVIC_IPR1; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000E408) Use the Interrupt Priority Registers to assign + __IOM uint32_t NVIC_IPR2; /*!< (@ 0x0000E408) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. */ - - struct { - uint32_t : 6; - __IOM uint32_t IP_8 : 2; /*!< [7..6] Priority of interrupt 8 */ - uint32_t : 6; - __IOM uint32_t IP_9 : 2; /*!< [15..14] Priority of interrupt 9 */ - uint32_t : 6; - __IOM uint32_t IP_10 : 2; /*!< [23..22] Priority of interrupt 10 */ - uint32_t : 6; - __IOM uint32_t IP_11 : 2; /*!< [31..30] Priority of interrupt 11 */ - } bit; - } NVIC_IPR2; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000E40C) Use the Interrupt Priority Registers to assign + __IOM uint32_t NVIC_IPR3; /*!< (@ 0x0000E40C) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. */ - - struct { - uint32_t : 6; - __IOM uint32_t IP_12 : 2; /*!< [7..6] Priority of interrupt 12 */ - uint32_t : 6; - __IOM uint32_t IP_13 : 2; /*!< [15..14] Priority of interrupt 13 */ - uint32_t : 6; - __IOM uint32_t IP_14 : 2; /*!< [23..22] Priority of interrupt 14 */ - uint32_t : 6; - __IOM uint32_t IP_15 : 2; /*!< [31..30] Priority of interrupt 15 */ - } bit; - } NVIC_IPR3; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000E410) Use the Interrupt Priority Registers to assign + __IOM uint32_t NVIC_IPR4; /*!< (@ 0x0000E410) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. */ - - struct { - uint32_t : 6; - __IOM uint32_t IP_16 : 2; /*!< [7..6] Priority of interrupt 16 */ - uint32_t : 6; - __IOM uint32_t IP_17 : 2; /*!< [15..14] Priority of interrupt 17 */ - uint32_t : 6; - __IOM uint32_t IP_18 : 2; /*!< [23..22] Priority of interrupt 18 */ - uint32_t : 6; - __IOM uint32_t IP_19 : 2; /*!< [31..30] Priority of interrupt 19 */ - } bit; - } NVIC_IPR4; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000E414) Use the Interrupt Priority Registers to assign + __IOM uint32_t NVIC_IPR5; /*!< (@ 0x0000E414) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. */ - - struct { - uint32_t : 6; - __IOM uint32_t IP_20 : 2; /*!< [7..6] Priority of interrupt 20 */ - uint32_t : 6; - __IOM uint32_t IP_21 : 2; /*!< [15..14] Priority of interrupt 21 */ - uint32_t : 6; - __IOM uint32_t IP_22 : 2; /*!< [23..22] Priority of interrupt 22 */ - uint32_t : 6; - __IOM uint32_t IP_23 : 2; /*!< [31..30] Priority of interrupt 23 */ - } bit; - } NVIC_IPR5; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000E418) Use the Interrupt Priority Registers to assign + __IOM uint32_t NVIC_IPR6; /*!< (@ 0x0000E418) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. */ - - struct { - uint32_t : 6; - __IOM uint32_t IP_24 : 2; /*!< [7..6] Priority of interrupt 24 */ - uint32_t : 6; - __IOM uint32_t IP_25 : 2; /*!< [15..14] Priority of interrupt 25 */ - uint32_t : 6; - __IOM uint32_t IP_26 : 2; /*!< [23..22] Priority of interrupt 26 */ - uint32_t : 6; - __IOM uint32_t IP_27 : 2; /*!< [31..30] Priority of interrupt 27 */ - } bit; - } NVIC_IPR6; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000E41C) Use the Interrupt Priority Registers to assign + __IOM uint32_t NVIC_IPR7; /*!< (@ 0x0000E41C) Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. */ - - struct { - uint32_t : 6; - __IOM uint32_t IP_28 : 2; /*!< [7..6] Priority of interrupt 28 */ - uint32_t : 6; - __IOM uint32_t IP_29 : 2; /*!< [15..14] Priority of interrupt 29 */ - uint32_t : 6; - __IOM uint32_t IP_30 : 2; /*!< [23..22] Priority of interrupt 30 */ - uint32_t : 6; - __IOM uint32_t IP_31 : 2; /*!< [31..30] Priority of interrupt 31 */ - } bit; - } NVIC_IPR7; __IM uint32_t RESERVED6[568]; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000ED00) Read the CPU ID Base Register to determine: the + __IOM uint32_t CPUID; /*!< (@ 0x0000ED00) Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core. */ - - struct { - __IM uint32_t REVISION : 4; /*!< [3..0] Minor revision number m in the rnpm revision status: - 0x1 = Patch 1. */ - __IM uint32_t PARTNO : 12; /*!< [15..4] Number of processor within family: 0xC60 = Cortex-M0+ */ - __IM uint32_t ARCHITECTURE : 4; /*!< [19..16] Constant that defines the architecture of the processor: - 0xC = ARMv6-M architecture. */ - __IM uint32_t VARIANT : 4; /*!< [23..20] Major revision number n in the rnpm revision status: - 0x0 = Revision 0. */ - __IM uint32_t IMPLEMENTER : 8; /*!< [31..24] Implementor code: 0x41 = ARM */ - } bit; - } CPUID; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000ED04) Use the Interrupt Control State Register to set + __IOM uint32_t ICSR; /*!< (@ 0x0000ED04) Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception. */ - - struct { - __IM uint32_t VECTACTIVE : 9; /*!< [8..0] Active exception number field. Reset clears the VECTACTIVE - field. */ - uint32_t : 3; - __IM uint32_t VECTPENDING : 9; /*!< [20..12] Indicates the exception number for the highest priority - pending exception: 0 = no pending exceptions. Non zero - = The pending state includes the effect of memory-mapped - enable and mask registers. It does not include the PRIMASK - special-purpose register qualifier. */ - uint32_t : 1; - __IM uint32_t ISRPENDING : 1; /*!< [22..22] External interrupt pending flag */ - __IM uint32_t ISRPREEMPT : 1; /*!< [23..23] The system can only access this bit when the core is - halted. It indicates that a pending interrupt is to be - taken in the next running cycle. If C_MASKINTS is clear - in the Debug Halting Control and Status Register, the interrupt - is serviced. */ - uint32_t : 1; - __IOM uint32_t PENDSTCLR : 1; /*!< [25..25] SysTick exception clear-pending bit. - Write: - 0 = No effect. - 1 = Removes the pending state from the SysTick exception. - This bit is WO. On a register read its value is Unknown. */ - __IOM uint32_t PENDSTSET : 1; /*!< [26..26] SysTick exception set-pending bit. - Write: - 0 = No effect. - 1 = Changes SysTick exception state to pending. - Read: - 0 = SysTick exception is not pending. - 1 = SysTick exception is pending. */ - __IOM uint32_t PENDSVCLR : 1; /*!< [27..27] PendSV clear-pending bit. - Write: - 0 = No effect. - 1 = Removes the pending state from the PendSV exception. */ - __IOM uint32_t PENDSVSET : 1; /*!< [28..28] PendSV set-pending bit. - Write: - 0 = No effect. - 1 = Changes PendSV exception state to pending. - Read: - 0 = PendSV exception is not pending. - 1 = PendSV exception is pending. - Writing 1 to this bit is the only way to set the PendSV - exception state to pending. */ - uint32_t : 2; - __IOM uint32_t NMIPENDSET : 1; /*!< [31..31] Setting this bit will activate an NMI. Since NMI is - the highest priority exception, it will activate as soon - as it is registered. - NMI set-pending bit. - Write: - 0 = No effect. - 1 = Changes NMI exception state to pending. - Read: - 0 = NMI exception is not pending. - 1 = NMI exception is pending. - Because NMI is the highest-priority exception, normally - the processor */ - } bit; - } ICSR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000ED08) The VTOR holds the vector table offset address. */ - - struct { - uint32_t : 8; - __IOM uint32_t TBLOFF : 24; /*!< [31..8] Bits [31:8] of the indicate the vector table offset - address. */ - } bit; - } VTOR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000ED0C) Use the Application Interrupt and Reset Control + __IOM uint32_t VTOR; /*!< (@ 0x0000ED08) The VTOR holds the vector table offset address. */ + __IOM uint32_t AIRCR; /*!< (@ 0x0000ED0C) Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset. */ - - struct { - uint32_t : 1; - __IOM uint32_t VECTCLRACTIVE : 1; /*!< [1..1] Clears all active state information for fixed and configurable - exceptions. This bit: is self-clearing, can only be set - by the DAP when the core is halted. When set: clears all - active exception status of the processor, forces a return - to Thread mode, forces an IPSR of 0. A debugger must re-initialize - the stack. */ - __IOM uint32_t SYSRESETREQ : 1; /*!< [2..2] Writing 1 to this bit causes the SYSRESETREQ signal to - the outer system to be asserted to request a reset. The - intention is to force a large system reset of all major - components except for debug. The C_HALT bit in the DHCSR - is cleared as a result of the system reset requested. The - debugger does not lose contact with the device. */ - uint32_t : 12; - __IM uint32_t ENDIANESS : 1; /*!< [15..15] Data endianness implemented: - 0 = Little-endian. */ - __IOM uint32_t VECTKEY : 16; /*!< [31..16] Register key: - Reads as Unknown - On writes, write 0x05FA to VECTKEY, otherwise the write - is ignored. */ - } bit; - } AIRCR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000ED10) System Control Register. Use the System Control + __IOM uint32_t SCR; /*!< (@ 0x0000ED10) System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states. */ - - struct { - uint32_t : 1; - __IOM uint32_t SLEEPONEXIT : 1; /*!< [1..1] Indicates sleep-on-exit when returning from Handler mode - to Thread mode: - 0 = Do not sleep when returning to Thread mode. - 1 = Enter sleep, or deep sleep, on return from an ISR to - Thread mode. - Setting this bit to 1 enables an interrupt driven application - to avoid returning to an empty main application. */ - __IOM uint32_t SLEEPDEEP : 1; /*!< [2..2] Controls whether the processor uses sleep or deep sleep - as its low power mode: - 0 = Sleep. - 1 = Deep sleep. */ - uint32_t : 1; - __IOM uint32_t SEVONPEND : 1; /*!< [4..4] Send Event on Pending bit: - 0 = Only enabled interrupts or events can wakeup the processor, - disabled interrupts are excluded. - 1 = Enabled events and all interrupts, including disabled - interrupts, can wakeup the processor. - When an event or interrupt becomes pending, the event signal - wakes up the processor from WFE. If the - processor is not waiting for an event, the event is registered - and affects the next WFE. - The */ - uint32_t : 27; - } bit; - } SCR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000ED14) The Configuration and Control Register permanently + __IOM uint32_t CCR; /*!< (@ 0x0000ED14) The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault. */ - - struct { - uint32_t : 3; - __IM uint32_t UNALIGN_TRP : 1; /*!< [3..3] Always reads as one, indicates that all unaligned accesses - generate a HardFault. */ - uint32_t : 5; - __IM uint32_t STKALIGN : 1; /*!< [9..9] Always reads as one, indicates 8-byte stack alignment - on exception entry. On exception entry, the processor uses - bit[9] of the stacked PSR to indicate the stack alignment. - On return from the exception it uses this stacked bit to - restore the correct stack alignment. */ - uint32_t : 22; - } bit; - } CCR; __IM uint32_t RESERVED7; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000ED1C) System handlers are a special class of exception + __IOM uint32_t SHPR2; /*!< (@ 0x0000ED1C) System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall. */ - - struct { - uint32_t : 30; - __IOM uint32_t PRI_11 : 2; /*!< [31..30] Priority of system handler 11, SVCall */ - } bit; - } SHPR2; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000ED20) System handlers are a special class of exception + __IOM uint32_t SHPR3; /*!< (@ 0x0000ED20) System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick. */ - - struct { - uint32_t : 22; - __IOM uint32_t PRI_14 : 2; /*!< [23..22] Priority of system handler 14, PendSV */ - uint32_t : 6; - __IOM uint32_t PRI_15 : 2; /*!< [31..30] Priority of system handler 15, SysTick */ - } bit; - } SHPR3; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000ED24) Use the System Handler Control and State Register + __IOM uint32_t SHCSR; /*!< (@ 0x0000ED24) Use the System Handler Control and State Register to determine or clear the pending status of SVCall. */ - - struct { - uint32_t : 15; - __IOM uint32_t SVCALLPENDED : 1; /*!< [15..15] Reads as 1 if SVCall is Pending. Write 1 to set pending - SVCall, write 0 to clear pending SVCall. */ - uint32_t : 16; - } bit; - } SHCSR; __IM uint32_t RESERVED8[26]; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000ED90) Read the MPU Type Register to determine if the + __IOM uint32_t MPU_TYPE; /*!< (@ 0x0000ED90) Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports. */ - - struct { - __IM uint32_t SEPARATE : 1; /*!< [0..0] Indicates support for separate instruction and data address - maps. Reads as 0 as ARMv6-M only supports a unified MPU. */ - uint32_t : 7; - __IM uint32_t DREGION : 8; /*!< [15..8] Number of regions supported by the MPU. */ - __IM uint32_t IREGION : 8; /*!< [23..16] Instruction region. Reads as zero as ARMv6-M only supports - a unified MPU. */ - uint32_t : 8; - } bit; - } MPU_TYPE; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000ED94) Use the MPU Control Register to enable and disable + __IOM uint32_t MPU_CTRL; /*!< (@ 0x0000ED94) Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs. */ - - struct { - __IOM uint32_t ENABLE : 1; /*!< [0..0] Enables the MPU. If the MPU is disabled, privileged and - unprivileged accesses use the default memory map. - 0 = MPU disabled. - 1 = MPU enabled. */ - __IOM uint32_t HFNMIENA : 1; /*!< [1..1] Controls the use of the MPU for HardFaults and NMIs. - Setting this bit when ENABLE is clear results in UNPREDICTABLE - behaviour. - When the MPU is enabled: - 0 = MPU is disabled during HardFault and NMI handlers, - regardless of the value of the ENABLE bit. - 1 = the MPU is enabled during HardFault and NMI handlers. */ - __IOM uint32_t PRIVDEFENA : 1; /*!< [2..2] Controls whether the default memory map is enabled as - a background region for privileged accesses. This bit is - ignored when ENABLE is clear. - 0 = If the MPU is enabled, disables use of the default - memory map. Any memory access to a location not - covered by any enabled region causes a fault. - 1 = If the MPU is enabled, enables use of the default memory - map as a background region for privileged software accesses. - When enabled, the bac */ - uint32_t : 29; - } bit; - } MPU_CTRL; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000ED98) Use the MPU Region Number Register to select + __IOM uint32_t MPU_RNR; /*!< (@ 0x0000ED98) Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR. */ - - struct { - __IOM uint32_t REGION : 4; /*!< [3..0] Indicates the MPU region referenced by the MPU_RBAR and - MPU_RASR registers. - The MPU supports 8 memory regions, so the permitted values - of this field are 0-7. */ - uint32_t : 28; - } bit; - } MPU_RNR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000ED9C) Read the MPU Region Base Address Register to + __IOM uint32_t MPU_RBAR; /*!< (@ 0x0000ED9C) Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated. */ - - struct { - __IOM uint32_t REGION : 4; /*!< [3..0] On writes, specifies the number of the region whose base - address to update provided VALID is set written as 1. On - reads, returns bits [3:0] of MPU_RNR. */ - __IOM uint32_t VALID : 1; /*!< [4..4] On writes, indicates whether the write must update the - base address of the region identified by the REGION field, - updating the MPU_RNR to indicate this new region. - Write: - 0 = MPU_RNR not changed, and the processor: - Updates the base address for the region specified in the - MPU_RNR. - Ignores the value of the REGION field. - 1 = The processor: - Updates the value of the MPU_RNR to the value of the REG */ - uint32_t : 3; - __IOM uint32_t ADDR : 24; /*!< [31..8] Base address of the region. */ - } bit; - } MPU_RBAR; - - union { - __IOM uint32_t reg; /*!< (@ 0x0000EDA0) Use the MPU Region Attribute and Size Register + __IOM uint32_t MPU_RASR; /*!< (@ 0x0000EDA0) Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region. */ - - struct { - __IOM uint32_t ENABLE : 1; /*!< [0..0] Enables the region. */ - __IOM uint32_t SIZE : 5; /*!< [5..1] Indicates the region size. Region size in bytes = 2^(SIZE+1). - The minimum permitted value is 7 (b00111) = 256Bytes */ - uint32_t : 2; - __IOM uint32_t SRD : 8; /*!< [15..8] Subregion Disable. For regions of 256 bytes or larger, - each bit of this field controls whether one of the eight - equal subregions is enabled. */ - __IOM uint32_t ATTRS : 16; /*!< [31..16] The MPU Region Attribute field. Use to define the region - attribute control. - 28 = XN: Instruction access disable bit: - 0 = Instruction fetches enabled. - 1 = Instruction fetches disabled. - 26:24 = AP: Access permission field - 18 = S: Shareable bit - 17 = C: Cacheable bit - 16 = B: Bufferable bit */ - } bit; - } MPU_RASR; } PPB_Type; /*!< Size = 60836 (0xeda4) */ @@ -15309,6 +3501,7 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur #define VREG_AND_CHIP_RESET_BASE 0x40064000UL #define TBMAN_BASE 0x4006C000UL #define DMA_BASE 0x50000000UL +#define USBCTRL_DPRAM_BASE 0x50100000UL #define USBCTRL_REGS_BASE 0x50110000UL #define PIO0_BASE 0x50200000UL #define PIO1_BASE 0x50300000UL @@ -15357,6 +3550,7 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur #define VREG_AND_CHIP_RESET ((VREG_AND_CHIP_RESET_Type*) VREG_AND_CHIP_RESET_BASE) #define TBMAN ((TBMAN_Type*) TBMAN_BASE) #define DMA ((DMA_Type*) DMA_BASE) +#define USBCTRL_DPRAM ((USBCTRL_DPRAM_Type*) USBCTRL_DPRAM_BASE) #define USBCTRL_REGS ((USBCTRL_REGS_Type*) USBCTRL_REGS_BASE) #define PIO0 ((PIO0_Type*) PIO0_BASE) #define PIO1 ((PIO0_Type*) PIO1_BASE) @@ -21503,8 +9697,6 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur #define I2C0_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_Pos (0UL) /*!< IC_FS_SCL_LCNT (Bit 0) */ #define I2C0_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_Msk (0xffffUL) /*!< IC_FS_SCL_LCNT (Bitfield-Mask: 0xffff) */ /* ===================================================== IC_INTR_STAT ====================================================== */ -#define I2C0_IC_INTR_STAT_R_MASTER_ON_HOLD_Pos (13UL) /*!< R_MASTER_ON_HOLD (Bit 13) */ -#define I2C0_IC_INTR_STAT_R_MASTER_ON_HOLD_Msk (0x2000UL) /*!< R_MASTER_ON_HOLD (Bitfield-Mask: 0x01) */ #define I2C0_IC_INTR_STAT_R_RESTART_DET_Pos (12UL) /*!< R_RESTART_DET (Bit 12) */ #define I2C0_IC_INTR_STAT_R_RESTART_DET_Msk (0x1000UL) /*!< R_RESTART_DET (Bitfield-Mask: 0x01) */ #define I2C0_IC_INTR_STAT_R_GEN_CALL_Pos (11UL) /*!< R_GEN_CALL (Bit 11) */ @@ -21532,8 +9724,6 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur #define I2C0_IC_INTR_STAT_R_RX_UNDER_Pos (0UL) /*!< R_RX_UNDER (Bit 0) */ #define I2C0_IC_INTR_STAT_R_RX_UNDER_Msk (0x1UL) /*!< R_RX_UNDER (Bitfield-Mask: 0x01) */ /* ===================================================== IC_INTR_MASK ====================================================== */ -#define I2C0_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_Pos (13UL) /*!< M_MASTER_ON_HOLD_READ_ONLY (Bit 13) */ -#define I2C0_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_Msk (0x2000UL) /*!< M_MASTER_ON_HOLD_READ_ONLY (Bitfield-Mask: 0x01) */ #define I2C0_IC_INTR_MASK_M_RESTART_DET_Pos (12UL) /*!< M_RESTART_DET (Bit 12) */ #define I2C0_IC_INTR_MASK_M_RESTART_DET_Msk (0x1000UL) /*!< M_RESTART_DET (Bitfield-Mask: 0x01) */ #define I2C0_IC_INTR_MASK_M_GEN_CALL_Pos (11UL) /*!< M_GEN_CALL (Bit 11) */ @@ -21561,8 +9751,6 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur #define I2C0_IC_INTR_MASK_M_RX_UNDER_Pos (0UL) /*!< M_RX_UNDER (Bit 0) */ #define I2C0_IC_INTR_MASK_M_RX_UNDER_Msk (0x1UL) /*!< M_RX_UNDER (Bitfield-Mask: 0x01) */ /* =================================================== IC_RAW_INTR_STAT ==================================================== */ -#define I2C0_IC_RAW_INTR_STAT_MASTER_ON_HOLD_Pos (13UL) /*!< MASTER_ON_HOLD (Bit 13) */ -#define I2C0_IC_RAW_INTR_STAT_MASTER_ON_HOLD_Msk (0x2000UL) /*!< MASTER_ON_HOLD (Bitfield-Mask: 0x01) */ #define I2C0_IC_RAW_INTR_STAT_RESTART_DET_Pos (12UL) /*!< RESTART_DET (Bit 12) */ #define I2C0_IC_RAW_INTR_STAT_RESTART_DET_Msk (0x1000UL) /*!< RESTART_DET (Bitfield-Mask: 0x01) */ #define I2C0_IC_RAW_INTR_STAT_GEN_CALL_Pos (11UL) /*!< GEN_CALL (Bit 11) */ @@ -23081,6 +11269,16 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur #define DMA_TIMER1_X_Msk (0xffff0000UL) /*!< X (Bitfield-Mask: 0xffff) */ #define DMA_TIMER1_Y_Pos (0UL) /*!< Y (Bit 0) */ #define DMA_TIMER1_Y_Msk (0xffffUL) /*!< Y (Bitfield-Mask: 0xffff) */ +/* ======================================================== TIMER2 ========================================================= */ +#define DMA_TIMER2_X_Pos (16UL) /*!< X (Bit 16) */ +#define DMA_TIMER2_X_Msk (0xffff0000UL) /*!< X (Bitfield-Mask: 0xffff) */ +#define DMA_TIMER2_Y_Pos (0UL) /*!< Y (Bit 0) */ +#define DMA_TIMER2_Y_Msk (0xffffUL) /*!< Y (Bitfield-Mask: 0xffff) */ +/* ======================================================== TIMER3 ========================================================= */ +#define DMA_TIMER3_X_Pos (16UL) /*!< X (Bit 16) */ +#define DMA_TIMER3_X_Msk (0xffff0000UL) /*!< X (Bitfield-Mask: 0xffff) */ +#define DMA_TIMER3_Y_Pos (0UL) /*!< Y (Bit 0) */ +#define DMA_TIMER3_Y_Msk (0xffffUL) /*!< Y (Bitfield-Mask: 0xffff) */ /* ================================================== MULTI_CHAN_TRIGGER =================================================== */ #define DMA_MULTI_CHAN_TRIGGER_MULTI_CHAN_TRIGGER_Pos (0UL) /*!< MULTI_CHAN_TRIGGER (Bit 0) */ #define DMA_MULTI_CHAN_TRIGGER_MULTI_CHAN_TRIGGER_Msk (0xffffUL) /*!< MULTI_CHAN_TRIGGER (Bitfield-Mask: 0xffff) */ @@ -23161,6 +11359,1398 @@ typedef struct { /*!< (@ 0xE0000000) PPB Structur /* ===================================================== CH11_DBG_TCR ====================================================== */ +/* =========================================================================================================================== */ +/* ================ USBCTRL_DPRAM ================ */ +/* =========================================================================================================================== */ + +/* =================================================== SETUP_PACKET_LOW ==================================================== */ +#define USBCTRL_DPRAM_SETUP_PACKET_LOW_WVALUE_Pos (16UL) /*!< WVALUE (Bit 16) */ +#define USBCTRL_DPRAM_SETUP_PACKET_LOW_WVALUE_Msk (0xffff0000UL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +#define USBCTRL_DPRAM_SETUP_PACKET_LOW_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ +#define USBCTRL_DPRAM_SETUP_PACKET_LOW_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ +#define USBCTRL_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ +#define USBCTRL_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ +/* =================================================== SETUP_PACKET_HIGH =================================================== */ +#define USBCTRL_DPRAM_SETUP_PACKET_HIGH_WLENGTH_Pos (16UL) /*!< WLENGTH (Bit 16) */ +#define USBCTRL_DPRAM_SETUP_PACKET_HIGH_WLENGTH_Msk (0xffff0000UL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +#define USBCTRL_DPRAM_SETUP_PACKET_HIGH_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ +#define USBCTRL_DPRAM_SETUP_PACKET_HIGH_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP1_IN_CONTROL ===================================================== */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP1_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP2_IN_CONTROL ===================================================== */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP2_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP3_IN_CONTROL ===================================================== */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP3_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP4_IN_CONTROL ===================================================== */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP4_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP5_IN_CONTROL ===================================================== */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP5_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP6_IN_CONTROL ===================================================== */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP6_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP7_IN_CONTROL ===================================================== */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP7_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP8_IN_CONTROL ===================================================== */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP8_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP9_IN_CONTROL ===================================================== */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP9_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP10_IN_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* =================================================== EP10_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP11_IN_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* =================================================== EP11_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP12_IN_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* =================================================== EP12_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP13_IN_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* =================================================== EP13_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP14_IN_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* =================================================== EP14_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ==================================================== EP15_IN_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* =================================================== EP15_OUT_CONTROL ==================================================== */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_Pos (30UL) /*!< DOUBLE_BUFFERED (Bit 30) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_Msk (0x40000000UL) /*!< DOUBLE_BUFFERED (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_Pos (29UL) /*!< INTERRUPT_PER_BUFF (Bit 29) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_Msk (0x20000000UL) /*!< INTERRUPT_PER_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Pos (28UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bit 28) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_Msk (0x10000000UL) /*!< INTERRUPT_PER_DOUBLE_BUFF (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_Pos (26UL) /*!< ENDPOINT_TYPE (Bit 26) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_Msk (0xc000000UL) /*!< ENDPOINT_TYPE (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_Pos (17UL) /*!< INTERRUPT_ON_STALL (Bit 17) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_Msk (0x20000UL) /*!< INTERRUPT_ON_STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_Pos (16UL) /*!< INTERRUPT_ON_NAK (Bit 16) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_Msk (0x10000UL) /*!< INTERRUPT_ON_NAK (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_Pos (0UL) /*!< BUFFER_ADDRESS (Bit 0) */ +#define USBCTRL_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_Msk (0xffffUL) /*!< BUFFER_ADDRESS (Bitfield-Mask: 0xffff) */ +/* ================================================= EP0_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP0_OUT_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================= EP1_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP1_OUT_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================= EP2_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP2_OUT_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================= EP3_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP3_OUT_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================= EP4_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP4_OUT_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================= EP5_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP5_OUT_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================= EP6_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP6_OUT_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================= EP7_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP7_OUT_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================= EP8_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP8_OUT_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================= EP9_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP9_OUT_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP10_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP10_OUT_BUFFER_CONTROL ================================================ */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP11_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP11_OUT_BUFFER_CONTROL ================================================ */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP12_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP12_OUT_BUFFER_CONTROL ================================================ */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP13_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP13_OUT_BUFFER_CONTROL ================================================ */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP14_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP14_OUT_BUFFER_CONTROL ================================================ */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP15_IN_BUFFER_CONTROL ================================================= */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ +/* ================================================ EP15_OUT_BUFFER_CONTROL ================================================ */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_Pos (31UL) /*!< FULL_1 (Bit 31) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_Msk (0x80000000UL) /*!< FULL_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_Pos (30UL) /*!< LAST_1 (Bit 30) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_Msk (0x40000000UL) /*!< LAST_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_Pos (29UL) /*!< PID_1 (Bit 29) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_Msk (0x20000000UL) /*!< PID_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Pos (27UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bit 27) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Msk (0x18000000UL) /*!< DOUBLE_BUFFER_ISO_OFFSET (Bitfield-Mask: 0x03) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_Pos (26UL) /*!< AVAILABLE_1 (Bit 26) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_Msk (0x4000000UL) /*!< AVAILABLE_1 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_Pos (16UL) /*!< LENGTH_1 (Bit 16) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_Msk (0x3ff0000UL) /*!< LENGTH_1 (Bitfield-Mask: 0x3ff) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_Pos (15UL) /*!< FULL_0 (Bit 15) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_Msk (0x8000UL) /*!< FULL_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_Pos (14UL) /*!< LAST_0 (Bit 14) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_Msk (0x4000UL) /*!< LAST_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_Pos (13UL) /*!< PID_0 (Bit 13) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_Msk (0x2000UL) /*!< PID_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_Pos (12UL) /*!< RESET (Bit 12) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_Msk (0x1000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_Pos (11UL) /*!< STALL (Bit 11) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_Msk (0x800UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_Pos (10UL) /*!< AVAILABLE_0 (Bit 10) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_Msk (0x400UL) /*!< AVAILABLE_0 (Bitfield-Mask: 0x01) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_Pos (0UL) /*!< LENGTH_0 (Bit 0) */ +#define USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_Msk (0x3ffUL) /*!< LENGTH_0 (Bitfield-Mask: 0x3ff) */ + + /* =========================================================================================================================== */ /* ================ USBCTRL_REGS ================ */ /* =========================================================================================================================== */ @@ -27665,12 +17255,108 @@ typedef enum { /*!< XOSC_STATUS_FREQ_RANGE /* =================================================== BUS_PRIORITY_ACK ==================================================== */ /* ======================================================= PERFCTR0 ======================================================== */ /* ======================================================= PERFSEL0 ======================================================== */ +/* =========================================== BUSCTRL PERFSEL0 PERFSEL0 [0..4] ============================================ */ +typedef enum { /*!< BUSCTRL_PERFSEL0_PERFSEL0 */ + BUSCTRL_PERFSEL0_PERFSEL0_apb_contested = 0, /*!< apb_contested : apb_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_apb = 1, /*!< apb : apb */ + BUSCTRL_PERFSEL0_PERFSEL0_fastperi_contested = 2,/*!< fastperi_contested : fastperi_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_fastperi = 3, /*!< fastperi : fastperi */ + BUSCTRL_PERFSEL0_PERFSEL0_sram5_contested = 4,/*!< sram5_contested : sram5_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_sram5 = 5, /*!< sram5 : sram5 */ + BUSCTRL_PERFSEL0_PERFSEL0_sram4_contested = 6,/*!< sram4_contested : sram4_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_sram4 = 7, /*!< sram4 : sram4 */ + BUSCTRL_PERFSEL0_PERFSEL0_sram3_contested = 8,/*!< sram3_contested : sram3_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_sram3 = 9, /*!< sram3 : sram3 */ + BUSCTRL_PERFSEL0_PERFSEL0_sram2_contested = 10,/*!< sram2_contested : sram2_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_sram2 = 11, /*!< sram2 : sram2 */ + BUSCTRL_PERFSEL0_PERFSEL0_sram1_contested = 12,/*!< sram1_contested : sram1_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_sram1 = 13, /*!< sram1 : sram1 */ + BUSCTRL_PERFSEL0_PERFSEL0_sram0_contested = 14,/*!< sram0_contested : sram0_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_sram0 = 15, /*!< sram0 : sram0 */ + BUSCTRL_PERFSEL0_PERFSEL0_xip_main_contested = 16,/*!< xip_main_contested : xip_main_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_xip_main = 17, /*!< xip_main : xip_main */ + BUSCTRL_PERFSEL0_PERFSEL0_rom_contested = 18, /*!< rom_contested : rom_contested */ + BUSCTRL_PERFSEL0_PERFSEL0_rom = 19, /*!< rom : rom */ +} BUSCTRL_PERFSEL0_PERFSEL0_Enum; + /* ======================================================= PERFCTR1 ======================================================== */ /* ======================================================= PERFSEL1 ======================================================== */ +/* =========================================== BUSCTRL PERFSEL1 PERFSEL1 [0..4] ============================================ */ +typedef enum { /*!< BUSCTRL_PERFSEL1_PERFSEL1 */ + BUSCTRL_PERFSEL1_PERFSEL1_apb_contested = 0, /*!< apb_contested : apb_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_apb = 1, /*!< apb : apb */ + BUSCTRL_PERFSEL1_PERFSEL1_fastperi_contested = 2,/*!< fastperi_contested : fastperi_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_fastperi = 3, /*!< fastperi : fastperi */ + BUSCTRL_PERFSEL1_PERFSEL1_sram5_contested = 4,/*!< sram5_contested : sram5_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_sram5 = 5, /*!< sram5 : sram5 */ + BUSCTRL_PERFSEL1_PERFSEL1_sram4_contested = 6,/*!< sram4_contested : sram4_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_sram4 = 7, /*!< sram4 : sram4 */ + BUSCTRL_PERFSEL1_PERFSEL1_sram3_contested = 8,/*!< sram3_contested : sram3_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_sram3 = 9, /*!< sram3 : sram3 */ + BUSCTRL_PERFSEL1_PERFSEL1_sram2_contested = 10,/*!< sram2_contested : sram2_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_sram2 = 11, /*!< sram2 : sram2 */ + BUSCTRL_PERFSEL1_PERFSEL1_sram1_contested = 12,/*!< sram1_contested : sram1_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_sram1 = 13, /*!< sram1 : sram1 */ + BUSCTRL_PERFSEL1_PERFSEL1_sram0_contested = 14,/*!< sram0_contested : sram0_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_sram0 = 15, /*!< sram0 : sram0 */ + BUSCTRL_PERFSEL1_PERFSEL1_xip_main_contested = 16,/*!< xip_main_contested : xip_main_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_xip_main = 17, /*!< xip_main : xip_main */ + BUSCTRL_PERFSEL1_PERFSEL1_rom_contested = 18, /*!< rom_contested : rom_contested */ + BUSCTRL_PERFSEL1_PERFSEL1_rom = 19, /*!< rom : rom */ +} BUSCTRL_PERFSEL1_PERFSEL1_Enum; + /* ======================================================= PERFCTR2 ======================================================== */ /* ======================================================= PERFSEL2 ======================================================== */ +/* =========================================== BUSCTRL PERFSEL2 PERFSEL2 [0..4] ============================================ */ +typedef enum { /*!< BUSCTRL_PERFSEL2_PERFSEL2 */ + BUSCTRL_PERFSEL2_PERFSEL2_apb_contested = 0, /*!< apb_contested : apb_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_apb = 1, /*!< apb : apb */ + BUSCTRL_PERFSEL2_PERFSEL2_fastperi_contested = 2,/*!< fastperi_contested : fastperi_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_fastperi = 3, /*!< fastperi : fastperi */ + BUSCTRL_PERFSEL2_PERFSEL2_sram5_contested = 4,/*!< sram5_contested : sram5_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_sram5 = 5, /*!< sram5 : sram5 */ + BUSCTRL_PERFSEL2_PERFSEL2_sram4_contested = 6,/*!< sram4_contested : sram4_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_sram4 = 7, /*!< sram4 : sram4 */ + BUSCTRL_PERFSEL2_PERFSEL2_sram3_contested = 8,/*!< sram3_contested : sram3_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_sram3 = 9, /*!< sram3 : sram3 */ + BUSCTRL_PERFSEL2_PERFSEL2_sram2_contested = 10,/*!< sram2_contested : sram2_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_sram2 = 11, /*!< sram2 : sram2 */ + BUSCTRL_PERFSEL2_PERFSEL2_sram1_contested = 12,/*!< sram1_contested : sram1_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_sram1 = 13, /*!< sram1 : sram1 */ + BUSCTRL_PERFSEL2_PERFSEL2_sram0_contested = 14,/*!< sram0_contested : sram0_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_sram0 = 15, /*!< sram0 : sram0 */ + BUSCTRL_PERFSEL2_PERFSEL2_xip_main_contested = 16,/*!< xip_main_contested : xip_main_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_xip_main = 17, /*!< xip_main : xip_main */ + BUSCTRL_PERFSEL2_PERFSEL2_rom_contested = 18, /*!< rom_contested : rom_contested */ + BUSCTRL_PERFSEL2_PERFSEL2_rom = 19, /*!< rom : rom */ +} BUSCTRL_PERFSEL2_PERFSEL2_Enum; + /* ======================================================= PERFCTR3 ======================================================== */ /* ======================================================= PERFSEL3 ======================================================== */ +/* =========================================== BUSCTRL PERFSEL3 PERFSEL3 [0..4] ============================================ */ +typedef enum { /*!< BUSCTRL_PERFSEL3_PERFSEL3 */ + BUSCTRL_PERFSEL3_PERFSEL3_apb_contested = 0, /*!< apb_contested : apb_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_apb = 1, /*!< apb : apb */ + BUSCTRL_PERFSEL3_PERFSEL3_fastperi_contested = 2,/*!< fastperi_contested : fastperi_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_fastperi = 3, /*!< fastperi : fastperi */ + BUSCTRL_PERFSEL3_PERFSEL3_sram5_contested = 4,/*!< sram5_contested : sram5_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_sram5 = 5, /*!< sram5 : sram5 */ + BUSCTRL_PERFSEL3_PERFSEL3_sram4_contested = 6,/*!< sram4_contested : sram4_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_sram4 = 7, /*!< sram4 : sram4 */ + BUSCTRL_PERFSEL3_PERFSEL3_sram3_contested = 8,/*!< sram3_contested : sram3_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_sram3 = 9, /*!< sram3 : sram3 */ + BUSCTRL_PERFSEL3_PERFSEL3_sram2_contested = 10,/*!< sram2_contested : sram2_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_sram2 = 11, /*!< sram2 : sram2 */ + BUSCTRL_PERFSEL3_PERFSEL3_sram1_contested = 12,/*!< sram1_contested : sram1_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_sram1 = 13, /*!< sram1 : sram1 */ + BUSCTRL_PERFSEL3_PERFSEL3_sram0_contested = 14,/*!< sram0_contested : sram0_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_sram0 = 15, /*!< sram0 : sram0 */ + BUSCTRL_PERFSEL3_PERFSEL3_xip_main_contested = 16,/*!< xip_main_contested : xip_main_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_xip_main = 17, /*!< xip_main : xip_main */ + BUSCTRL_PERFSEL3_PERFSEL3_rom_contested = 18, /*!< rom_contested : rom_contested */ + BUSCTRL_PERFSEL3_PERFSEL3_rom = 19, /*!< rom : rom */ +} BUSCTRL_PERFSEL3_PERFSEL3_Enum; + /* =========================================================================================================================== */ @@ -27831,12 +17517,6 @@ typedef enum { /*!< I2C0_IC_DATA_CMD_CMD /* ==================================================== IC_FS_SCL_HCNT ===================================================== */ /* ==================================================== IC_FS_SCL_LCNT ===================================================== */ /* ===================================================== IC_INTR_STAT ====================================================== */ -/* ====================================== I2C0 IC_INTR_STAT R_MASTER_ON_HOLD [13..13] ====================================== */ -typedef enum { /*!< I2C0_IC_INTR_STAT_R_MASTER_ON_HOLD */ - I2C0_IC_INTR_STAT_R_MASTER_ON_HOLD_INACTIVE = 0,/*!< INACTIVE : R_MASTER_ON_HOLD interrupt is inactive */ - I2C0_IC_INTR_STAT_R_MASTER_ON_HOLD_ACTIVE = 1,/*!< ACTIVE : R_MASTER_ON_HOLD interrupt is active */ -} I2C0_IC_INTR_STAT_R_MASTER_ON_HOLD_Enum; - /* ======================================= I2C0 IC_INTR_STAT R_RESTART_DET [12..12] ======================================== */ typedef enum { /*!< I2C0_IC_INTR_STAT_R_RESTART_DET */ I2C0_IC_INTR_STAT_R_RESTART_DET_INACTIVE = 0, /*!< INACTIVE : R_RESTART_DET interrupt is inactive */ @@ -27916,12 +17596,6 @@ typedef enum { /*!< I2C0_IC_INTR_STAT_R_RX_UNDE } I2C0_IC_INTR_STAT_R_RX_UNDER_Enum; /* ===================================================== IC_INTR_MASK ====================================================== */ -/* ================================= I2C0 IC_INTR_MASK M_MASTER_ON_HOLD_READ_ONLY [13..13] ================================= */ -typedef enum { /*!< I2C0_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY */ - I2C0_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_ENABLED = 0,/*!< ENABLED : MASTER_ON_HOLD interrupt is masked */ - I2C0_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_DISABLED = 1,/*!< DISABLED : MASTER_ON_HOLD interrupt is unmasked */ -} I2C0_IC_INTR_MASK_M_MASTER_ON_HOLD_READ_ONLY_Enum; - /* ======================================= I2C0 IC_INTR_MASK M_RESTART_DET [12..12] ======================================== */ typedef enum { /*!< I2C0_IC_INTR_MASK_M_RESTART_DET */ I2C0_IC_INTR_MASK_M_RESTART_DET_ENABLED = 0, /*!< ENABLED : RESTART_DET interrupt is masked */ @@ -28001,12 +17675,6 @@ typedef enum { /*!< I2C0_IC_INTR_MASK_M_RX_UNDE } I2C0_IC_INTR_MASK_M_RX_UNDER_Enum; /* =================================================== IC_RAW_INTR_STAT ==================================================== */ -/* ===================================== I2C0 IC_RAW_INTR_STAT MASTER_ON_HOLD [13..13] ===================================== */ -typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_MASTER_ON_HOLD */ - I2C0_IC_RAW_INTR_STAT_MASTER_ON_HOLD_INACTIVE = 0,/*!< INACTIVE : MASTER_ON_HOLD interrupt is inactive */ - I2C0_IC_RAW_INTR_STAT_MASTER_ON_HOLD_ACTIVE = 1,/*!< ACTIVE : MASTER_ON_HOLD interrupt is active */ -} I2C0_IC_RAW_INTR_STAT_MASTER_ON_HOLD_Enum; - /* ====================================== I2C0 IC_RAW_INTR_STAT RESTART_DET [12..12] ======================================= */ typedef enum { /*!< I2C0_IC_RAW_INTR_STAT_RESTART_DET */ I2C0_IC_RAW_INTR_STAT_RESTART_DET_INACTIVE = 0,/*!< INACTIVE : RESTART_DET interrupt is inactive */ @@ -29060,6 +18728,8 @@ typedef enum { /*!< DMA_CH11_CTRL_TRIG_DATA_SIZ /* ========================================================= INTS1 ========================================================= */ /* ======================================================== TIMER0 ========================================================= */ /* ======================================================== TIMER1 ========================================================= */ +/* ======================================================== TIMER2 ========================================================= */ +/* ======================================================== TIMER3 ========================================================= */ /* ================================================== MULTI_CHAN_TRIGGER =================================================== */ /* ====================================================== SNIFF_CTRL ======================================================= */ /* ============================================== DMA SNIFF_CTRL CALC [5..8] =============================================== */ @@ -29105,6 +18775,572 @@ typedef enum { /*!< DMA_SNIFF_CTRL_CALC /* ===================================================== CH11_DBG_TCR ====================================================== */ +/* =========================================================================================================================== */ +/* ================ USBCTRL_DPRAM ================ */ +/* =========================================================================================================================== */ + +/* =================================================== SETUP_PACKET_LOW ==================================================== */ +/* =================================================== SETUP_PACKET_HIGH =================================================== */ +/* ==================================================== EP1_IN_CONTROL ===================================================== */ +/* ================================== USBCTRL_DPRAM EP1_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP1_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP1_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP2_IN_CONTROL ===================================================== */ +/* ================================== USBCTRL_DPRAM EP2_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP2_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP2_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP3_IN_CONTROL ===================================================== */ +/* ================================== USBCTRL_DPRAM EP3_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP3_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP3_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP4_IN_CONTROL ===================================================== */ +/* ================================== USBCTRL_DPRAM EP4_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP4_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP4_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP5_IN_CONTROL ===================================================== */ +/* ================================== USBCTRL_DPRAM EP5_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP5_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP5_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP6_IN_CONTROL ===================================================== */ +/* ================================== USBCTRL_DPRAM EP6_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP6_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP6_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP7_IN_CONTROL ===================================================== */ +/* ================================== USBCTRL_DPRAM EP7_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP7_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP7_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP8_IN_CONTROL ===================================================== */ +/* ================================== USBCTRL_DPRAM EP8_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP8_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP8_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP9_IN_CONTROL ===================================================== */ +/* ================================== USBCTRL_DPRAM EP9_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP9_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP9_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP10_IN_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP10_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* =================================================== EP10_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP10_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP11_IN_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP11_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* =================================================== EP11_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP11_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP12_IN_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP12_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* =================================================== EP12_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP12_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP13_IN_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP13_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* =================================================== EP13_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP13_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP14_IN_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP14_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* =================================================== EP14_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP14_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ==================================================== EP15_IN_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP15_IN_CONTROL ENDPOINT_TYPE [26..27] ================================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_Enum; + +/* =================================================== EP15_OUT_CONTROL ==================================================== */ +/* ================================= USBCTRL_DPRAM EP15_OUT_CONTROL ENDPOINT_TYPE [26..27] ================================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE */ + USBCTRL_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_Control = 0,/*!< Control : Control */ + USBCTRL_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_Isochronous = 1,/*!< Isochronous : Isochronous */ + USBCTRL_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_Bulk = 2,/*!< Bulk : Bulk */ + USBCTRL_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_Interrupt = 3,/*!< Interrupt : Interrupt */ +} USBCTRL_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_Enum; + +/* ================================================= EP0_IN_BUFFER_CONTROL ================================================= */ +/* ========================= USBCTRL_DPRAM EP0_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP0_OUT_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP0_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================= EP1_IN_BUFFER_CONTROL ================================================= */ +/* ========================= USBCTRL_DPRAM EP1_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP1_OUT_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP1_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================= EP2_IN_BUFFER_CONTROL ================================================= */ +/* ========================= USBCTRL_DPRAM EP2_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP2_OUT_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP2_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================= EP3_IN_BUFFER_CONTROL ================================================= */ +/* ========================= USBCTRL_DPRAM EP3_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP3_OUT_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP3_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================= EP4_IN_BUFFER_CONTROL ================================================= */ +/* ========================= USBCTRL_DPRAM EP4_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP4_OUT_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP4_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================= EP5_IN_BUFFER_CONTROL ================================================= */ +/* ========================= USBCTRL_DPRAM EP5_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP5_OUT_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP5_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================= EP6_IN_BUFFER_CONTROL ================================================= */ +/* ========================= USBCTRL_DPRAM EP6_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP6_OUT_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP6_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================= EP7_IN_BUFFER_CONTROL ================================================= */ +/* ========================= USBCTRL_DPRAM EP7_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP7_OUT_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP7_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================= EP8_IN_BUFFER_CONTROL ================================================= */ +/* ========================= USBCTRL_DPRAM EP8_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP8_OUT_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP8_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================= EP9_IN_BUFFER_CONTROL ================================================= */ +/* ========================= USBCTRL_DPRAM EP9_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP9_OUT_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP9_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP10_IN_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP10_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP10_OUT_BUFFER_CONTROL ================================================ */ +/* ======================== USBCTRL_DPRAM EP10_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ======================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP11_IN_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP11_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP11_OUT_BUFFER_CONTROL ================================================ */ +/* ======================== USBCTRL_DPRAM EP11_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ======================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP12_IN_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP12_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP12_OUT_BUFFER_CONTROL ================================================ */ +/* ======================== USBCTRL_DPRAM EP12_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ======================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP13_IN_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP13_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP13_OUT_BUFFER_CONTROL ================================================ */ +/* ======================== USBCTRL_DPRAM EP13_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ======================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP14_IN_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP14_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP14_OUT_BUFFER_CONTROL ================================================ */ +/* ======================== USBCTRL_DPRAM EP14_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ======================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP15_IN_BUFFER_CONTROL ================================================= */ +/* ======================== USBCTRL_DPRAM EP15_IN_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ========================= */ +typedef enum { /*!< USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + +/* ================================================ EP15_OUT_BUFFER_CONTROL ================================================ */ +/* ======================== USBCTRL_DPRAM EP15_OUT_BUFFER_CONTROL DOUBLE_BUFFER_ISO_OFFSET [27..28] ======================== */ +typedef enum { /*!< USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET */ + USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_128 = 0,/*!< 128 : 128 */ + USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_256 = 1,/*!< 256 : 256 */ + USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_512 = 2,/*!< 512 : 512 */ + USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_1024 = 3,/*!< 1024 : 1024 */ +} USBCTRL_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_Enum; + + + /* =========================================================================================================================== */ /* ================ USBCTRL_REGS ================ */ /* =========================================================================================================================== */ diff --git a/cpu/rpx0xx/periph/gpio.c b/cpu/rpx0xx/periph/gpio.c index 483ed44722..96afefd06b 100644 --- a/cpu/rpx0xx/periph/gpio.c +++ b/cpu/rpx0xx/periph/gpio.c @@ -42,8 +42,8 @@ static void *_args[GPIO_PIN_NUMOF]; int gpio_init(gpio_t pin, gpio_mode_t mode) { assert(pin < GPIO_PIN_NUMOF); - SIO->GPIO_OE_CLR.reg = 1LU << pin; - SIO->GPIO_OUT_CLR.reg = 1LU << pin; + SIO->GPIO_OE_CLR = 1LU << pin; + SIO->GPIO_OUT_CLR = 1LU << pin; switch (mode) { case GPIO_IN: @@ -98,7 +98,7 @@ int gpio_init(gpio_t pin, gpio_mode_t mode) gpio_set_pad_config(pin, pad_config); gpio_set_io_config(pin, io_config); } - SIO->GPIO_OE_SET.reg = 1LU << pin; + SIO->GPIO_OE_SET = 1LU << pin; break; default: return -ENOTSUP; @@ -108,27 +108,27 @@ int gpio_init(gpio_t pin, gpio_mode_t mode) int gpio_read(gpio_t pin) { - if (SIO->GPIO_OE.reg & (1LU << pin)) { + if (SIO->GPIO_OE & (1LU << pin)) { /* pin is output: */ - return SIO->GPIO_OUT.reg & (1LU << pin); + return SIO->GPIO_OUT & (1LU << pin); } /* pin is input: */ - return SIO->GPIO_IN.reg & (1LU << pin); + return SIO->GPIO_IN & (1LU << pin); } void gpio_set(gpio_t pin) { - SIO->GPIO_OUT_SET.reg = 1LU << pin; + SIO->GPIO_OUT_SET = 1LU << pin; } void gpio_clear(gpio_t pin) { - SIO->GPIO_OUT_CLR.reg = 1LU << pin; + SIO->GPIO_OUT_CLR = 1LU << pin; } void gpio_toggle(gpio_t pin) { - SIO->GPIO_OUT_XOR.reg = 1LU << pin; + SIO->GPIO_OUT_XOR = 1LU << pin; } void gpio_write(gpio_t pin, int value) @@ -144,8 +144,8 @@ void gpio_write(gpio_t pin, int value) #ifdef MODULE_PERIPH_GPIO_IRQ static void _irq_enable(gpio_t pin, unsigned flank) { - volatile uint32_t *irq_enable_regs = &IO_BANK0->PROC0_INTE0.reg; - volatile uint32_t *irq_ack_regs = &IO_BANK0->INTR0.reg; + volatile uint32_t *irq_enable_regs = &IO_BANK0->PROC0_INTE0; + volatile uint32_t *irq_ack_regs = &IO_BANK0->INTR0; /* There are 4 bits to control IRQs per pin, hence the configuration is split across multiple * I/O registers. The following calculates the position the four bits matching the given pin, * where idx refers to the I/O register and shift_amount to the position in the I/O register. @@ -201,15 +201,15 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, gpio_cb_t cb void isr_io_bank0(void) { unsigned offset = 0; - volatile uint32_t *irq_status_regs = &IO_BANK0->PROC0_INTS0.reg; - volatile uint32_t *irq_ack_regs = &IO_BANK0->INTR0.reg; + volatile uint32_t *irq_status_regs = &IO_BANK0->PROC0_INTS0; + volatile uint32_t *irq_ack_regs = &IO_BANK0->INTR0; DEBUG("[rp0x00] GPIO IRQ mask: %08x, %08x, %08x, %08x\n", - (unsigned)IO_BANK0->PROC0_INTE0.reg, (unsigned)IO_BANK0->PROC0_INTE1.reg, - (unsigned)IO_BANK0->PROC0_INTE2.reg, (unsigned)IO_BANK0->PROC0_INTE3.reg); + (unsigned)IO_BANK0->PROC0_INTE0, (unsigned)IO_BANK0->PROC0_INTE1, + (unsigned)IO_BANK0->PROC0_INTE2, (unsigned)IO_BANK0->PROC0_INTE3); DEBUG("[rp0x00] GPIO IRQ status: %08x, %08x, %08x, %08x\n", - (unsigned)IO_BANK0->PROC0_INTS0.reg, (unsigned)IO_BANK0->PROC0_INTS1.reg, - (unsigned)IO_BANK0->PROC0_INTS2.reg, (unsigned)IO_BANK0->PROC0_INTS3.reg); + (unsigned)IO_BANK0->PROC0_INTS0, (unsigned)IO_BANK0->PROC0_INTS1, + (unsigned)IO_BANK0->PROC0_INTS2, (unsigned)IO_BANK0->PROC0_INTS3); /* There are four IRQ status bits per pin, so there is info for 8 pins per I/O register. * We will iterate over all IRQ status I/O registers in the outer loop, and over all 8 pins diff --git a/cpu/rpx0xx/periph/timer.c b/cpu/rpx0xx/periph/timer.c index e47a6c4bda..cbf89763b1 100644 --- a/cpu/rpx0xx/periph/timer.c +++ b/cpu/rpx0xx/periph/timer.c @@ -88,14 +88,14 @@ static inline void _irq_enable(tim_t dev) { for (uint8_t i = 0; i < timer_config[dev].ch_numof; i++) { NVIC_EnableIRQ(timer_config[dev].ch[i].irqn); - io_reg_atomic_set(&DEV(dev)->INTE.reg, (1U << i)); + io_reg_atomic_set(&DEV(dev)->INTE, (1U << i)); } } static void _isr(tim_t dev, int channel) { /* clear latched interrupt */ - io_reg_atomic_clear(&DEV(dev)->INTR.reg, 1U << channel); + io_reg_atomic_clear(&DEV(dev)->INTR, 1U << channel); if (_timer_is_periodic(dev, channel)) { if (_timer_reset_on_match(dev, channel)) { @@ -118,7 +118,8 @@ int timer_init(tim_t dev, uint32_t freq, timer_cb_t cb, void *arg) } /* The timer must run at 1000000 Hz (µs precision) because the number of cycles per µs is shared with the watchdog. - The reference clock (clk_ref) is divided by WATCHDOG->TICK.bits.CYCLES + The reference clock (clk_ref) is divided by + (WATCHDOG->TICK & WATCHDOC_TICK_CYCLES_Mask) to generate µs ticks. */ assert(freq == US_PER_SEC); (void)freq; @@ -126,7 +127,7 @@ int timer_init(tim_t dev, uint32_t freq, timer_cb_t cb, void *arg) _timer_ctx_arg[dev] = arg; periph_reset(RESETS_RESET_timer_Msk); periph_reset_done(RESETS_RESET_timer_Msk); - io_reg_write_dont_corrupt(&WATCHDOG->TICK.reg, + io_reg_write_dont_corrupt(&WATCHDOG->TICK, (CLOCK_XOSC / MHZ(1)) << WATCHDOG_TICK_CYCLES_Pos, WATCHDOG_TICK_CYCLES_Msk); _irq_enable(dev); @@ -205,7 +206,7 @@ int timer_clear(tim_t dev, int channel) return -EINVAL; } /* ARMED bits are write clear */ - io_reg_atomic_set(&DEV(dev)->ARMED.reg, (1 << channel)); + io_reg_atomic_set(&DEV(dev)->ARMED, (1 << channel)); unsigned state = irq_disable(); _timer_disable_periodic(dev, channel); irq_restore(state); @@ -223,13 +224,13 @@ unsigned int timer_read(tim_t dev) void timer_start(tim_t dev) { assert(dev < TIMER_NUMOF); - io_reg_atomic_clear(&DEV(dev)->PAUSE.reg, (1 << TIMER_PAUSE_PAUSE_Pos)); + io_reg_atomic_clear(&DEV(dev)->PAUSE, (1 << TIMER_PAUSE_PAUSE_Pos)); } void timer_stop(tim_t dev) { assert(dev < TIMER_NUMOF); - io_reg_atomic_set(&DEV(dev)->PAUSE.reg, (1 << TIMER_PAUSE_PAUSE_Pos)); + io_reg_atomic_set(&DEV(dev)->PAUSE, (1 << TIMER_PAUSE_PAUSE_Pos)); } /* timer 0 IRQ0 */ diff --git a/cpu/rpx0xx/periph/uart.c b/cpu/rpx0xx/periph/uart.c index 26b7e6fcca..23ed6b2ed2 100644 --- a/cpu/rpx0xx/periph/uart.c +++ b/cpu/rpx0xx/periph/uart.c @@ -48,7 +48,7 @@ static uint32_t uartcr; void _irq_enable(uart_t uart) { UART0_Type *dev = uart_config[uart].dev; - dev->UARTIMSC.reg = UART0_UARTIMSC_RXIM_Msk; + dev->UARTIMSC = UART0_UARTIMSC_RXIM_Msk; NVIC_EnableIRQ(uart_config[uart].irqn); } @@ -72,8 +72,8 @@ void _set_symbolrate(uart_t uart, uint32_t baud) baud_fbrd = ((baud_rate_div & 0x7f) + 1) / 2; } - dev->UARTIBRD.reg = baud_ibrd; - dev->UARTFBRD.reg = baud_fbrd; + dev->UARTIBRD = baud_ibrd; + dev->UARTFBRD = baud_fbrd; } int uart_mode(uart_t uart, uart_data_bits_t data_bits, uart_parity_t uart_parity, @@ -82,7 +82,7 @@ int uart_mode(uart_t uart, uart_data_bits_t data_bits, uart_parity_t uart_parity assert((unsigned)uart < UART_NUMOF); UART0_Type *dev = uart_config[uart].dev; - io_reg_atomic_clear(&dev->UARTCR.reg, + io_reg_atomic_clear(&dev->UARTCR, UART0_UARTCR_UARTEN_Msk | UART0_UARTCR_TXE_Msk | UART0_UARTCR_RXE_Msk); /* Beware of strange hardware bug: If the configuration bitmask is prepared in register and @@ -91,26 +91,26 @@ int uart_mode(uart_t uart, uart_data_bits_t data_bits, uart_parity_t uart_parity * next char send out. If the configuration is updated in multiple bus accesses, it will apply * directly to the next char. So: Double check e.g. with tests/periph_uart_mode after touching * the initialization code here */ - dev->UARTLCR_H.reg = (uint32_t)data_bits << UART0_UARTLCR_H_WLEN_Pos; + dev->UARTLCR_H = (uint32_t)data_bits << UART0_UARTLCR_H_WLEN_Pos; if (stop_bits == UART_STOP_BITS_2) { - io_reg_atomic_set(&dev->UARTLCR_H.reg, UART0_UARTLCR_H_STP2_Msk); + io_reg_atomic_set(&dev->UARTLCR_H, UART0_UARTLCR_H_STP2_Msk); } switch (uart_parity) { case UART_PARITY_NONE: break; case UART_PARITY_EVEN: - io_reg_atomic_set(&dev->UARTLCR_H.reg, UART0_UARTLCR_H_EPS_Msk | UART0_UARTLCR_H_PEN_Msk); + io_reg_atomic_set(&dev->UARTLCR_H, UART0_UARTLCR_H_EPS_Msk | UART0_UARTLCR_H_PEN_Msk); break; case UART_PARITY_ODD: - io_reg_atomic_set(&dev->UARTLCR_H.reg, UART0_UARTLCR_H_PEN_Msk); + io_reg_atomic_set(&dev->UARTLCR_H, UART0_UARTLCR_H_PEN_Msk); break; default: return UART_NOMODE; } - io_reg_atomic_set(&dev->UARTCR.reg, + io_reg_atomic_set(&dev->UARTCR, UART0_UARTCR_UARTEN_Msk | UART0_UARTCR_TXE_Msk | UART0_UARTCR_RXE_Msk); return UART_OK; @@ -148,7 +148,7 @@ void uart_deinit_pins(uart_t uart) { assert((unsigned)uart < UART_NUMOF); gpio_reset_all_config(uart_config[uart].tx_pin); - SIO->GPIO_OE_CLR.reg = 1LU << uart_config[uart].tx_pin; + SIO->GPIO_OE_CLR = 1LU << uart_config[uart].tx_pin; if (ctx[uart].rx_cb) { gpio_reset_all_config(uart_config[uart].rx_pin); } @@ -167,10 +167,10 @@ void uart_poweron(uart_t uart) _poweron(uart); UART0_Type *dev = uart_config[uart].dev; /* restore configuration registers */ - dev->UARTIBRD.reg = uartibrd; - dev->UARTFBRD.reg = uartfbrd; - dev->UARTLCR_H.reg = uartlcr_h; - dev->UARTCR.reg = uartcr; + dev->UARTIBRD = uartibrd; + dev->UARTFBRD = uartfbrd; + dev->UARTLCR_H = uartlcr_h; + dev->UARTCR = uartcr; /* restore IRQs, if needed */ if (ctx[uart].rx_cb != NULL) { _irq_enable(uart); @@ -183,10 +183,10 @@ void uart_poweroff(uart_t uart) assert((unsigned)uart < UART_NUMOF); UART0_Type *dev = uart_config[uart].dev; /* backup configuration registers */ - uartibrd = dev->UARTIBRD.reg; - uartfbrd = dev->UARTFBRD.reg; - uartlcr_h = dev->UARTLCR_H.reg; - uartcr = dev->UARTCR.reg; + uartibrd = dev->UARTIBRD; + uartfbrd = dev->UARTFBRD; + uartlcr_h = dev->UARTLCR_H; + uartcr = dev->UARTCR; /* disconnect GPIOs and power off peripheral */ uart_deinit_pins(uart); periph_reset((uart) ? RESETS_RESET_uart1_Msk : RESETS_RESET_uart0_Msk); @@ -217,10 +217,10 @@ int uart_init(uart_t uart, uint32_t baud, uart_rx_cb_t rx_cb, void *arg) if (rx_cb != NULL) { _irq_enable(uart); /* clear any pending data and IRQ to avoid receiving a garbage char */ - uint32_t status = dev->UARTRIS.reg; - dev->UARTICR.reg = status; - (void)dev->UARTDR.reg; - io_reg_atomic_set(&dev->UARTCR.reg, UART0_UARTCR_RXE_Msk); + uint32_t status = dev->UARTRIS; + dev->UARTICR = status; + (void)dev->UARTDR; + io_reg_atomic_set(&dev->UARTCR, UART0_UARTCR_RXE_Msk); } return UART_OK; @@ -232,8 +232,8 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len) UART0_Type *dev = uart_config[uart].dev; for (size_t i = 0; i < len; i++) { - dev->UARTDR.reg = data[i]; - while (!(dev->UARTRIS.reg & UART0_UARTRIS_TXRIS_Msk)) { } + dev->UARTDR = data[i]; + while (!(dev->UARTRIS & UART0_UARTRIS_TXRIS_Msk)) { } } } @@ -253,11 +253,11 @@ void isr_handler(uint8_t num) { UART0_Type *dev = uart_config[num].dev; - uint32_t status = dev->UARTMIS.reg; - dev->UARTICR.reg = status; + uint32_t status = dev->UARTMIS; + dev->UARTICR = status; if (status & UART0_UARTMIS_RXMIS_Msk) { - uint32_t data = dev->UARTDR.reg; + uint32_t data = dev->UARTDR; if (data & (UART0_UARTDR_BE_Msk | UART0_UARTDR_PE_Msk | UART0_UARTDR_FE_Msk)) { DEBUG_PUTS("[rpx0xx] uart RX error (parity, break, or framing error"); } diff --git a/cpu/rpx0xx/pll.c b/cpu/rpx0xx/pll.c index ce78350706..33c9de7a11 100644 --- a/cpu/rpx0xx/pll.c +++ b/cpu/rpx0xx/pll.c @@ -44,22 +44,22 @@ static void _pll_start(PLL_SYS_Type *pll, uint8_t ref_div, assert(post_div_2 <= PLL_POSTDIV_MAX); /* program reference clock divider */ - io_reg_write_dont_corrupt(&pll->CS.reg, ref_div << PLL_SYS_CS_REFDIV_Pos, + io_reg_write_dont_corrupt(&pll->CS, ref_div << PLL_SYS_CS_REFDIV_Pos, PLL_SYS_CS_REFDIV_Msk); /* program feedback divider */ - io_reg_write_dont_corrupt(&pll->FBDIV_INT.reg, + io_reg_write_dont_corrupt(&pll->FBDIV_INT, vco_feedback_scale << PLL_SYS_FBDIV_INT_FBDIV_INT_Pos, PLL_SYS_FBDIV_INT_FBDIV_INT_Msk); /* turn on the main power */ - io_reg_atomic_clear(&pll->PWR.reg, (1U << PLL_SYS_PWR_VCOPD_Pos) + io_reg_atomic_clear(&pll->PWR, (1U << PLL_SYS_PWR_VCOPD_Pos) | (1U << PLL_SYS_PWR_DSMPD_Pos) | (1U << PLL_SYS_PWR_PD_Pos)); /* wait for VCO to lock (i.e. keep its output stable) */ - while (!pll->CS.bit.LOCK) { } + while (!(pll->CS & PLL_SYS_CS_LOCK_Msk)) { } /* set up post divisors and turn them on */ - pll->PRIM.reg = (post_div_1 << PLL_SYS_PRIM_POSTDIV1_Pos) + pll->PRIM = (post_div_1 << PLL_SYS_PRIM_POSTDIV1_Pos) | (post_div_2 << PLL_SYS_PRIM_POSTDIV2_Pos); - io_reg_atomic_clear(&pll->PWR.reg, 1U << PLL_SYS_PWR_POSTDIVPD_Pos); + io_reg_atomic_clear(&pll->PWR, 1U << PLL_SYS_PWR_POSTDIVPD_Pos); } /** @@ -72,7 +72,7 @@ static void _pll_stop(PLL_SYS_Type *pll) | (1U << PLL_SYS_PWR_POSTDIVPD_Pos) | (1U << PLL_SYS_PWR_DSMPD_Pos) | (1U << PLL_SYS_PWR_PD_Pos); - io_reg_atomic_set(&pll->PWR.reg, reg); + io_reg_atomic_set(&pll->PWR, reg); } void pll_start_sys(uint8_t ref_div, diff --git a/cpu/rpx0xx/rosc.c b/cpu/rpx0xx/rosc.c index 9783efa91b..77b997d092 100644 --- a/cpu/rpx0xx/rosc.c +++ b/cpu/rpx0xx/rosc.c @@ -31,19 +31,19 @@ void rosc_start(void) { /* set drive strengths to default 0 */ - io_reg_atomic_clear(&ROSC->FREQA.reg, ROSC_FREQA_PASSWD_Msk); - io_reg_atomic_clear(&ROSC->FREQB.reg, ROSC_FREQB_PASSWD_Msk); + io_reg_atomic_clear(&ROSC->FREQA, ROSC_FREQA_PASSWD_Msk); + io_reg_atomic_clear(&ROSC->FREQB, ROSC_FREQB_PASSWD_Msk); /* apply settings with magic value 0x9696 */ const uint32_t magic = 0x9696U; - io_reg_write_dont_corrupt(&ROSC->FREQA.reg, magic << ROSC_FREQA_PASSWD_Pos, + io_reg_write_dont_corrupt(&ROSC->FREQA, magic << ROSC_FREQA_PASSWD_Pos, ROSC_FREQA_PASSWD_Msk); - io_reg_write_dont_corrupt(&ROSC->FREQB.reg, magic << ROSC_FREQB_PASSWD_Pos, + io_reg_write_dont_corrupt(&ROSC->FREQB, magic << ROSC_FREQB_PASSWD_Pos, ROSC_FREQB_PASSWD_Msk); /* default divider is 16 */ - io_reg_write_dont_corrupt(&ROSC->DIV.reg, 16 << ROSC_DIV_DIV_Pos, ROSC_DIV_DIV_Msk); - io_reg_atomic_set(&ROSC->CTRL.reg, ROSC_CTRL_ENABLE_ENABLE << ROSC_CTRL_ENABLE_Pos); - while (!ROSC->STATUS.bit.STABLE) { } + io_reg_write_dont_corrupt(&ROSC->DIV, 16 << ROSC_DIV_DIV_Pos, ROSC_DIV_DIV_Msk); + io_reg_atomic_set(&ROSC->CTRL, ROSC_CTRL_ENABLE_ENABLE << ROSC_CTRL_ENABLE_Pos); + while (!(ROSC->STATUS & ROSC_STATUS_STABLE_Msk)) { } } /** @@ -53,5 +53,5 @@ void rosc_start(void) */ void rosc_stop(void) { - io_reg_atomic_set(&ROSC->CTRL.reg, ROSC_CTRL_ENABLE_DISABLE << ROSC_CTRL_ENABLE_Pos); + io_reg_atomic_set(&ROSC->CTRL, ROSC_CTRL_ENABLE_DISABLE << ROSC_CTRL_ENABLE_Pos); } diff --git a/cpu/rpx0xx/xosc.c b/cpu/rpx0xx/xosc.c index 4d22b59018..ddf522d5ef 100644 --- a/cpu/rpx0xx/xosc.c +++ b/cpu/rpx0xx/xosc.c @@ -34,15 +34,15 @@ void xosc_start(uint32_t f_ref) { assert(f_ref == MHZ(12)); uint32_t delay = _xosc_conf_sartup_delay(f_ref, 1); - io_reg_write_dont_corrupt(&XOSC->STARTUP.reg, delay << XOSC_STARTUP_DELAY_Pos, + io_reg_write_dont_corrupt(&XOSC->STARTUP, delay << XOSC_STARTUP_DELAY_Pos, XOSC_STARTUP_DELAY_Msk); - io_reg_write_dont_corrupt(&XOSC->CTRL.reg, XOSC_CTRL_ENABLE_ENABLE << XOSC_CTRL_ENABLE_Pos, + io_reg_write_dont_corrupt(&XOSC->CTRL, XOSC_CTRL_ENABLE_ENABLE << XOSC_CTRL_ENABLE_Pos, XOSC_CTRL_ENABLE_Msk); - while (!XOSC->STATUS.bit.STABLE) { } + while (!(XOSC->STATUS & XOSC_STATUS_STABLE_Msk)) { } } void xosc_stop(void) { - io_reg_write_dont_corrupt(&XOSC->CTRL.reg, XOSC_CTRL_ENABLE_DISABLE << XOSC_CTRL_ENABLE_Pos, + io_reg_write_dont_corrupt(&XOSC->CTRL, XOSC_CTRL_ENABLE_DISABLE << XOSC_CTRL_ENABLE_Pos, XOSC_CTRL_ENABLE_Msk); } From f979730730226f0ea160a78837eaf97d04927695 Mon Sep 17 00:00:00 2001 From: Gunar Schorcht Date: Fri, 24 Mar 2023 07:40:23 +0100 Subject: [PATCH 09/10] cpu/gd32v: fix gpio_read in periph_gpio --- cpu/gd32v/periph/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cpu/gd32v/periph/gpio.c b/cpu/gd32v/periph/gpio.c index 9bae397c40..36ce51f474 100644 --- a/cpu/gd32v/periph/gpio.c +++ b/cpu/gd32v/periph/gpio.c @@ -165,7 +165,7 @@ int gpio_read(gpio_t pin) GPIO_Type *port = _port(pin); unsigned pin_num = _pin_num(pin); - if (_pin_is_output(port, pin)) { + if (_pin_is_output(port, pin_num)) { /* pin is output */ return (port->OCTL & (1 << pin_num)); } From f7b039f58914a19a68b665074a0ed9fe220aa48d Mon Sep 17 00:00:00 2001 From: Gunar Schorcht Date: Fri, 24 Mar 2023 08:11:23 +0100 Subject: [PATCH 10/10] boards/sipeed-longan-nano: add BOOT as user button --- boards/sipeed-longan-nano/doc.txt | 8 ++++---- boards/sipeed-longan-nano/include/board.h | 9 +++++++++ boards/sipeed-longan-nano/include/gpio_params.h | 5 +++++ 3 files changed, 18 insertions(+), 4 deletions(-) diff --git a/boards/sipeed-longan-nano/doc.txt b/boards/sipeed-longan-nano/doc.txt index 01d87b335e..5e052c7f3b 100644 --- a/boards/sipeed-longan-nano/doc.txt +++ b/boards/sipeed-longan-nano/doc.txt @@ -67,9 +67,9 @@ by pins. | ADC_LINE(5) | PB1 | ADC01_IN9 | TFT RST | N/A if TFT is used | | ADC_LINE(6) | PA6 | ADC01_IN6 | | N/A if TFT is used | | ADC_LINE(7) | PA7 | ADC01_IN7 | | N/A if TFT is used | -| ADC_LINE(8) | PA8 | ADC01_IN4 | | N/A if TFT is used | -| ADC_LINE(9) | PA9 | ADC01_IN5 | | N/A if TFT is used | -| BTN0 | PA0 | BOOT0 | BOOT | | +| ADC_LINE(8) | PA4 | ADC01_IN4 | | N/A if TFT is used | +| ADC_LINE(9) | PA5 | ADC01_IN5 | | N/A if TFT is used | +| BTN0 | PA8 | BOOT0 | BOOT | | | DAC_LINE(0) | PA4 | DAC0 | | N/A if TFT is used | | DAC_LINE(1) | PA5 | DAC1 | | N/A if TFT is used | | GPIO_PIN(1, 2) | PB2 | | TFT CS | | @@ -105,7 +105,7 @@ by pins. | PA5 | TFT SCL | SPI_DEV(1) SCLK | ADC_LINE(9)* | DAC_LINE(1)* | | PA6 | | SPI_DEV(1) MISO | ADC_LINE(6)* | | | PA7 | TFT SDA | SPI_DEV(1) MOSI | ADC_LINE(7)* | | -| PA8 | | | | | +| PA8 | BOOT | | | BTN0 | | PA9 | | UART_DEV(0) TX | | | | PA10 | | UART_DEV(0) RX | | | | PA11 | USB D- | | | | diff --git a/boards/sipeed-longan-nano/include/board.h b/boards/sipeed-longan-nano/include/board.h index f57ffc94fe..eb498afae0 100644 --- a/boards/sipeed-longan-nano/include/board.h +++ b/boards/sipeed-longan-nano/include/board.h @@ -26,6 +26,15 @@ extern "C" { #endif +/** + * @name Button pin definitions + * @{ + */ +#define BTN0_PIN GPIO_PIN(PORT_A, 8) +#define BTN0_MODE GPIO_IN +#define BTN0_INT_FLANK GPIO_RISING +/** @} */ + /** * @name LED (on-board) configuration * @{ diff --git a/boards/sipeed-longan-nano/include/gpio_params.h b/boards/sipeed-longan-nano/include/gpio_params.h index 9925466fb0..5b88d09c00 100644 --- a/boards/sipeed-longan-nano/include/gpio_params.h +++ b/boards/sipeed-longan-nano/include/gpio_params.h @@ -31,6 +31,11 @@ extern "C" { */ static const saul_gpio_params_t saul_gpio_params[] = { + { + .name = "BOOT", + .pin = BTN0_PIN, + .mode = BTN0_MODE, + }, { .name = "LED RED", .pin = LED0_PIN,