RIOT-OS/RIOT
RIOT-OS/RIOT
1
0
Fork 0
mirror of https://github.com/RIOT-OS/RIOT.git synced 2025-01-18 12:52:44 +01:00
Code Releases Activity

drivers/at86rf215: prefix configuration defines with CONFIG_

Browse Source
This commit is contained in:
Benjamin Valentin 2020-06-03 16:44:50 +02:00 committed by Benjamin Valentin
parent 3a1ee4983c
commit 4e9420bffc
2 changed files with 26 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/at86rf215/at86rf215.c
View File

@ -66,9 +66,9 @@ void at86rf215_reset_and_cfg(at86rf215_t *dev)
luid_get_eui64((eui64_t *)&dev->netdev.long_addr);
if (is_subGHz(dev)) {
dev->netdev.chan = AT86RF215_DEFAULT_SUBGHZ_CHANNEL;
dev->netdev.chan = CONFIG_AT86RF215_DEFAULT_SUBGHZ_CHANNEL;
} else {
dev->netdev.chan = AT86RF215_DEFAULT_CHANNEL;
dev->netdev.chan = CONFIG_AT86RF215_DEFAULT_CHANNEL;
}
dev->netdev.pan = CONFIG_IEEE802154_DEFAULT_PANID;
@ -144,14 +144,14 @@ if (!IS_ACTIVE(CONFIG_AT86RF215_USE_CLOCK_OUTPUT)){
at86rf215_reg_write(dev, dev->BBC->RG_AMCS, reg);
if (AT86RF215_DEFAULT_PHY_MODE == IEEE802154_PHY_OQPSK) {
if (CONFIG_AT86RF215_DEFAULT_PHY_MODE == IEEE802154_PHY_OQPSK) {
at86rf215_configure_legacy_OQPSK(dev, 0);
}
if (AT86RF215_DEFAULT_PHY_MODE == IEEE802154_PHY_MR_OQPSK) {
at86rf215_configure_OQPSK(dev, AT86RF215_DEFAULT_MR_OQPSK_CHIPS,
AT86RF215_DEFAULT_MR_OQPSK_RATE);
if (CONFIG_AT86RF215_DEFAULT_PHY_MODE == IEEE802154_PHY_MR_OQPSK) {
at86rf215_configure_OQPSK(dev, CONFIG_AT86RF215_DEFAULT_MR_OQPSK_CHIPS,
CONFIG_AT86RF215_DEFAULT_MR_OQPSK_RATE);
}
if (AT86RF215_DEFAULT_PHY_MODE == IEEE802154_PHY_MR_OFDM) {
if (CONFIG_AT86RF215_DEFAULT_PHY_MODE == IEEE802154_PHY_MR_OFDM) {
at86rf215_configure_OFDM(dev, CONFIG_AT86RF215_DEFAULT_MR_OFDM_OPT,
CONFIG_AT86RF215_DEFAULT_MR_OFDM_MCS);
}
@ -169,7 +169,7 @@ if (!IS_ACTIVE(CONFIG_AT86RF215_USE_CLOCK_OUTPUT)){
at86rf215_set_pan(dev, 0, dev->netdev.pan);
/* set default TX power */
at86rf215_set_txpower(dev, AT86RF215_DEFAULT_TXPOWER);
at86rf215_set_txpower(dev, CONFIG_AT86RF215_DEFAULT_TXPOWER);
/* start listening for incoming packets */
at86rf215_rf_cmd(dev, CMD_RF_RX);

28
drivers/include/at86rf215.h
View File

@ -100,22 +100,26 @@ enum {
*/
#define CONFIG_AT86RF215_TRIM_VAL (0)
#endif
/** @} */
/**
* @name Channel configuration
* @{
*/
#define AT86RF215_DEFAULT_CHANNEL (CONFIG_IEEE802154_DEFAULT_CHANNEL)
#define AT86RF215_DEFAULT_SUBGHZ_CHANNEL (CONFIG_IEEE802154_DEFAULT_SUBGHZ_CHANNEL)
#ifndef CONFIG_AT86RF215_DEFAULT_CHANNEL
#define CONFIG_AT86RF215_DEFAULT_CHANNEL (CONFIG_IEEE802154_DEFAULT_CHANNEL)
#endif
#ifndef CONFIG_AT86RF215_DEFAULT_SUBGHZ_CHANNEL
#define CONFIG_AT86RF215_DEFAULT_SUBGHZ_CHANNEL (CONFIG_IEEE802154_DEFAULT_SUBGHZ_CHANNEL)
#endif
/** @} */
/**
* @name Default PHY Mode
* @{
*/
#ifndef AT86RF215_DEFAULT_PHY_MODE
#define AT86RF215_DEFAULT_PHY_MODE (IEEE802154_PHY_OQPSK)
#ifndef CONFIG_AT86RF215_DEFAULT_PHY_MODE
#define CONFIG_AT86RF215_DEFAULT_PHY_MODE (IEEE802154_PHY_OQPSK)
#endif
/** @} */
@ -123,8 +127,8 @@ enum {
* @name Default MR-O-QPSK Chip Rate
* @{
*/
#ifndef AT86RF215_DEFAULT_MR_OQPSK_CHIPS
#define AT86RF215_DEFAULT_MR_OQPSK_CHIPS (AT86RF215_FCHIP_1000)
#ifndef CONFIG_AT86RF215_DEFAULT_MR_OQPSK_CHIPS
#define CONFIG_AT86RF215_DEFAULT_MR_OQPSK_CHIPS (AT86RF215_FCHIP_1000)
#endif
/** @} */
@ -132,8 +136,8 @@ enum {
* @name Default MR-O-QPSK Rate Mode
* @{
*/
#ifndef AT86RF215_DEFAULT_MR_OQPSK_RATE
#define AT86RF215_DEFAULT_MR_OQPSK_RATE (2)
#ifndef CONFIG_AT86RF215_DEFAULT_MR_OQPSK_RATE
#define CONFIG_AT86RF215_DEFAULT_MR_OQPSK_RATE (2)
#endif
/** @} */
@ -158,7 +162,11 @@ enum {
/**
* @brief Default TX power (0dBm)
*/
#define AT86RF215_DEFAULT_TXPOWER (CONFIG_IEEE802154_DEFAULT_TXPOWER)
#ifndef CONFIG_AT86RF215_DEFAULT_TXPOWER
#define CONFIG_AT86RF215_DEFAULT_TXPOWER (CONFIG_IEEE802154_DEFAULT_TXPOWER)
#endif
/** @} */
/**
* @name Flags for device internal states (see datasheet)