From 4d65bc8e0ab46dcc2eeb11e0deffb6af61f47871 Mon Sep 17 00:00:00 2001
From: Leandro Lanzieri <leandro.lanzieri@haw-hamburg.de>
Date: Wed, 10 Jun 2020 13:11:32 +0200
Subject: [PATCH] cpu: Rename CPU_ARCH to CPU_CORE

---
 boards/common/silabs/drivers/aem/Makefile     |  2 +-
 core/include/panic.h                          |  4 ++--
 cpu/cc2538/Makefile.features                  |  2 +-
 cpu/cc26x0/Makefile.features                  |  2 +-
 cpu/cc26x2_cc13x2/Makefile.features           |  2 +-
 cpu/cortexm_common/Makefile.features          | 21 +++++++++++++++-
 cpu/cortexm_common/Makefile.include           |  2 +-
 cpu/cortexm_common/cortexm_init.c             | 10 ++++----
 cpu/cortexm_common/include/cpu.h              |  8 +++----
 cpu/cortexm_common/include/vectors_cortexm.h  |  4 ++--
 cpu/cortexm_common/mpu.c                      |  2 +-
 cpu/cortexm_common/thread_arch.c              | 20 ++++++++--------
 cpu/cortexm_common/vectors_cortexm.c          | 22 ++++++++---------
 cpu/efm32/Makefile.dep                        |  2 +-
 cpu/efm32/Makefile.features                   |  2 +-
 cpu/ezr32wg/Makefile.features                 |  2 +-
 cpu/kinetis/kinetis-info.mk                   |  6 ++---
 cpu/lm4f120/Makefile.features                 |  2 +-
 cpu/lpc1768/Makefile.features                 |  2 +-
 cpu/mips_pic32mx/Makefile.features            |  3 ++-
 cpu/mips_pic32mz/Makefile.features            |  3 ++-
 cpu/nrf51/Makefile.features                   |  2 +-
 cpu/nrf52/Makefile.features                   |  2 +-
 cpu/sam3/Makefile.features                    |  2 +-
 cpu/samd21/Makefile.features                  |  2 +-
 cpu/samd5x/Makefile.features                  |  2 +-
 cpu/saml1x/Makefile.features                  |  2 +-
 cpu/saml21/Makefile.features                  |  2 +-
 cpu/stm32/stm32_info.mk                       | 12 +++++-----
 dist/tools/buildsystem_sanity_check/check.sh  |  1 +
 makefiles/arch/cortexm.inc.mk                 | 24 +++++++++----------
 makefiles/dependencies_debug.inc.mk           |  2 +-
 makefiles/info-global.inc.mk                  |  1 +
 makefiles/vars.inc.mk                         |  3 ++-
 pkg/micro-ecc/Makefile.include                |  2 +-
 pkg/openthread/Makefile.include               |  2 +-
 pkg/qDSA/Makefile.dep                         |  2 +-
 pkg/qDSA/Makefile.include                     |  4 ++--
 pkg/relic/Makefile.include                    |  2 +-
 pkg/tensorflow-lite/Makefile.include          |  2 +-
 tests/mtd_flashpage/main.c                    |  2 +-
 tests/pkg_c25519/Makefile                     |  2 +-
 .../unittests/tests-core/tests-core-atomic.c  |  2 +-
 43 files changed, 112 insertions(+), 88 deletions(-)

diff --git a/boards/common/silabs/drivers/aem/Makefile b/boards/common/silabs/drivers/aem/Makefile
index 280864279c..715856541d 100644
--- a/boards/common/silabs/drivers/aem/Makefile
+++ b/boards/common/silabs/drivers/aem/Makefile
@@ -1,6 +1,6 @@
 MODULE = silabs_aem
 
-ifeq ($(CPU_ARCH),cortex-m0plus)
+ifeq ($(CPU_CORE),cortex-m0plus)
   $(error AEM is not available for the Cortex M0+)
 endif
 
diff --git a/core/include/panic.h b/core/include/panic.h
index 7e17f82fd2..4a22c48a5b 100644
--- a/core/include/panic.h
+++ b/core/include/panic.h
@@ -40,8 +40,8 @@ typedef enum {
 #ifdef MODULE_CORTEXM_COMMON
     PANIC_NMI_HANDLER,          /**< non maskable interrupt */
     PANIC_HARD_FAULT,           /**< hard fault */
-#if defined(CPU_ARCH_CORTEX_M3) || defined(CPU_ARCH_CORTEX_M4) || \
-    defined(CPU_ARCH_CORTEX_M4F) || defined(CPU_ARCH_CORTEX_M7)
+#if defined(CPU_CORE_CORTEX_M3) || defined(CPU_CORE_CORTEX_M4) || \
+    defined(CPU_CORE_CORTEX_M4F) || defined(CPU_CORE_CORTEX_M7)
     PANIC_MEM_MANAGE,           /**< memory controller interrupt */
     PANIC_BUS_FAULT,            /**< bus fault */
     PANIC_USAGE_FAULT,          /**< undefined instruction or unaligned access */
diff --git a/cpu/cc2538/Makefile.features b/cpu/cc2538/Makefile.features
index 10c9ca7571..46d084bb7c 100644
--- a/cpu/cc2538/Makefile.features
+++ b/cpu/cc2538/Makefile.features
@@ -1,4 +1,4 @@
-CPU_ARCH = cortex-m3
+CPU_CORE = cortex-m3
 
 FEATURES_PROVIDED += periph_cpuid
 FEATURES_PROVIDED += periph_gpio periph_gpio_irq
diff --git a/cpu/cc26x0/Makefile.features b/cpu/cc26x0/Makefile.features
index d2a863032e..20bf4b721c 100644
--- a/cpu/cc26x0/Makefile.features
+++ b/cpu/cc26x0/Makefile.features
@@ -1,4 +1,4 @@
-CPU_ARCH = cortex-m3
+CPU_CORE = cortex-m3
 
 FEATURES_PROVIDED += cortexm_mpu
 
diff --git a/cpu/cc26x2_cc13x2/Makefile.features b/cpu/cc26x2_cc13x2/Makefile.features
index 1f6134e83d..035bc3608a 100644
--- a/cpu/cc26x2_cc13x2/Makefile.features
+++ b/cpu/cc26x2_cc13x2/Makefile.features
@@ -1,4 +1,4 @@
-CPU_ARCH = cortex-m4f
+CPU_CORE = cortex-m4f
 
 FEATURES_PROVIDED += cortexm_mpu
 
diff --git a/cpu/cortexm_common/Makefile.features b/cpu/cortexm_common/Makefile.features
index 9d1d3d8f40..1b312edae8 100644
--- a/cpu/cortexm_common/Makefile.features
+++ b/cpu/cortexm_common/Makefile.features
@@ -8,6 +8,25 @@ FEATURES_PROVIDED += cpu_check_address
 FEATURES_PROVIDED += ssp
 
 # cortex-m4f and cortex-m7 provide FPU support
-ifneq (,$(filter $(CPU_ARCH),cortex-m4f cortex-m7))
+ifneq (,$(filter $(CPU_CORE),cortex-m4f cortex-m7))
   FEATURES_PROVIDED += cortexm_fpu
 endif
+
+# Set CPU_ARCH depending on the CPU_CORE
+ifeq ($(CPU_CORE),cortex-m0)
+  CPU_ARCH := armv6m
+else ifeq ($(CPU_CORE),cortex-m0plus)
+  CPU_ARCH := armv6m
+else ifeq ($(CPU_CORE),cortex-m3)
+  CPU_ARCH := armv7m
+else ifeq ($(CPU_CORE),cortex-m4)
+  CPU_ARCH := armv7m
+else ifeq ($(CPU_CORE),cortex-m4f)
+  CPU_ARCH := armv7m
+else ifeq ($(CPU_CORE),cortex-m7)
+  CPU_ARCH := armv7m
+else ifeq ($(CPU_CORE),cortex-m23)
+  CPU_ARCH := armv8m
+else
+  $(error Unkwnown cortexm core: $(CPU_CORE))
+endif
diff --git a/cpu/cortexm_common/Makefile.include b/cpu/cortexm_common/Makefile.include
index 2d220a8f79..d9a50e93f3 100644
--- a/cpu/cortexm_common/Makefile.include
+++ b/cpu/cortexm_common/Makefile.include
@@ -53,7 +53,7 @@ LINKFLAGS += $(if $(FW_ROM_LEN),$(LINKFLAGPREFIX)--defsym=_fw_rom_length=$(FW_RO
 # The values defined here are a theoretical maximum, in practice most cpu's
 # CPU_IRQ_NUMOF value is around 100, in these cases the value can be reduced
 # accordingly in the cpu Makefile.include, e.g: `kinetis/Makefile.include`
-ifneq (,$(filter cortex-m2% cortex-m4% cortex-m3% cortex-m7%,$(CPU_ARCH)))
+ifneq (,$(filter cortex-m2% cortex-m4% cortex-m3% cortex-m7%,$(CPU_CORE)))
   RIOTBOOT_HDR_LEN ?= 0x400
 else
   RIOTBOOT_HDR_LEN ?= 0x100
diff --git a/cpu/cortexm_common/cortexm_init.c b/cpu/cortexm_common/cortexm_init.c
index c20ecc939a..1b3803ff59 100644
--- a/cpu/cortexm_common/cortexm_init.c
+++ b/cpu/cortexm_common/cortexm_init.c
@@ -68,9 +68,9 @@ void cortexm_init(void)
     cortexm_init_fpu();
 
     /* configure the vector table location to internal flash */
-#if defined(CPU_ARCH_CORTEX_M3) || defined(CPU_ARCH_CORTEX_M4) || \
-    defined(CPU_ARCH_CORTEX_M4F) || defined(CPU_ARCH_CORTEX_M7) || \
-    (defined(CPU_ARCH_CORTEX_M0PLUS) || defined(CPU_ARCH_CORTEX_M23) \
+#if defined(CPU_CORE_CORTEX_M3) || defined(CPU_CORE_CORTEX_M4) || \
+    defined(CPU_CORE_CORTEX_M4F) || defined(CPU_CORE_CORTEX_M7) || \
+    (defined(CPU_CORE_CORTEX_M0PLUS) || defined(CPU_CORE_CORTEX_M23) \
     && (__VTOR_PRESENT == 1))
     SCB->VTOR = (uint32_t)&_isr_vectors;
 #endif
@@ -81,8 +81,8 @@ void cortexm_init(void)
 
 bool cpu_check_address(volatile const char *address)
 {
-#if defined(CPU_ARCH_CORTEX_M3) || defined(CPU_ARCH_CORTEX_M4) || \
-    defined(CPU_ARCH_CORTEX_M4F) || defined(CPU_ARCH_CORTEX_M7)
+#if defined(CPU_CORE_CORTEX_M3) || defined(CPU_CORE_CORTEX_M4) || \
+    defined(CPU_CORE_CORTEX_M4F) || defined(CPU_CORE_CORTEX_M7)
     static const uint32_t BFARVALID_MASK = (0x80 << SCB_CFSR_BUSFAULTSR_Pos);
 
     bool is_valid = true;
diff --git a/cpu/cortexm_common/include/cpu.h b/cpu/cortexm_common/include/cpu.h
index 117cec92d5..ca895972e5 100644
--- a/cpu/cortexm_common/include/cpu.h
+++ b/cpu/cortexm_common/include/cpu.h
@@ -99,7 +99,7 @@ void cortexm_init(void);
 static inline void cortexm_init_fpu(void)
 {
     /* initialize the FPU on Cortex-M4F CPUs */
-#if defined(CPU_ARCH_CORTEX_M4F) || defined(CPU_ARCH_CORTEX_M7)
+#if defined(CPU_CORE_CORTEX_M4F) || defined(CPU_CORE_CORTEX_M7)
     /* give full access to the FPU */
     SCB->CPACR |= (uint32_t)CORTEXM_SCB_CPACR_FPU_ACCESS_FULL;
 #endif
@@ -226,9 +226,9 @@ static inline void cpu_jump_to_image(uint32_t image_address)
 
 /* The following register is only present for
    Cortex-M0+, -M3, -M4, -M7 and -M23 CPUs */
-#if defined(CPU_ARCH_CORTEX_M0PLUS) || defined(CPU_ARCH_CORTEX_M3) || \
-    defined(CPU_ARCH_CORTEX_M4) || defined(CPU_ARCH_CORTEX_M4F) || \
-    defined(CPU_ARCH_CORTEX_M7) || defined(CPU_ARCH_CORTEX_M23)
+#if defined(CPU_CORE_CORTEX_M0PLUS) || defined(CPU_CORE_CORTEX_M3) || \
+    defined(CPU_CORE_CORTEX_M4) || defined(CPU_CORE_CORTEX_M4F) || \
+    defined(CPU_CORE_CORTEX_M7) || defined(CPU_CORE_CORTEX_M23)
 static inline uint32_t cpu_get_image_baseaddr(void)
 {
     return SCB->VTOR;
diff --git a/cpu/cortexm_common/include/vectors_cortexm.h b/cpu/cortexm_common/include/vectors_cortexm.h
index d0957dc277..9b44518fc0 100644
--- a/cpu/cortexm_common/include/vectors_cortexm.h
+++ b/cpu/cortexm_common/include/vectors_cortexm.h
@@ -92,8 +92,8 @@ void nmi_default(void);
 void hard_fault_default(void);
 
 /* The following four exceptions are only present for Cortex-M3 and -M4 CPUs */
-#if defined(CPU_ARCH_CORTEX_M3) || defined(CPU_ARCH_CORTEX_M4) || \
-    defined(CPU_ARCH_CORTEX_M4F) || defined(CPU_ARCH_CORTEX_M7)
+#if defined(CPU_CORE_CORTEX_M3) || defined(CPU_CORE_CORTEX_M4) || \
+    defined(CPU_CORE_CORTEX_M4F) || defined(CPU_CORE_CORTEX_M7)
 /**
  * @brief   Memory management exception handler
  *
diff --git a/cpu/cortexm_common/mpu.c b/cpu/cortexm_common/mpu.c
index 2154b794dc..db35863ee9 100644
--- a/cpu/cortexm_common/mpu.c
+++ b/cpu/cortexm_common/mpu.c
@@ -60,7 +60,7 @@ bool mpu_enabled(void) {
 
 int mpu_configure(uint_fast8_t region, uintptr_t base, uint_fast32_t attr) {
 /* Todo enable MPU support for Cortex-M23/M33 */
-#if __MPU_PRESENT && !defined(CPU_ARCH_CORTEX_M23)
+#if __MPU_PRESENT && !defined(CPU_CORE_CORTEX_M23)
     MPU->RNR  = region;
     MPU->RBAR = base & MPU_RBAR_ADDR_Msk;
     MPU->RASR = attr | MPU_RASR_ENABLE_Msk;
diff --git a/cpu/cortexm_common/thread_arch.c b/cpu/cortexm_common/thread_arch.c
index d4d5b02478..8f5c9e1abd 100644
--- a/cpu/cortexm_common/thread_arch.c
+++ b/cpu/cortexm_common/thread_arch.c
@@ -190,8 +190,8 @@ char *thread_stack_init(thread_task_func_t task_func,
      * For the Cortex-M3 and Cortex-M4 we write them continuously onto the stack
      * as they can be read/written continuously by stack instructions. */
 
-#if defined(CPU_ARCH_CORTEX_M0) || defined(CPU_ARCH_CORTEX_M0PLUS) \
-    || defined(CPU_ARCH_CORTEX_M23)
+#if defined(CPU_CORE_CORTEX_M0) || defined(CPU_CORE_CORTEX_M0PLUS) \
+    || defined(CPU_CORE_CORTEX_M23)
     /* start with r7 - r4 */
     for (int i = 7; i >= 4; i--) {
         stk--;
@@ -297,8 +297,8 @@ void __attribute__((naked)) __attribute__((used)) isr_pendsv(void) {
     "beq select_and_restore_context   \n" /*   goto select_and_restore_context */
 
     "mrs    r0, psp                   \n" /* get stack pointer from user mode */
-#if defined(CPU_ARCH_CORTEX_M0) || defined(CPU_ARCH_CORTEX_M0PLUS) \
-    || defined(CPU_ARCH_CORTEX_M23)
+#if defined(CPU_CORE_CORTEX_M0) || defined(CPU_CORE_CORTEX_M0PLUS) \
+    || defined(CPU_CORE_CORTEX_M23)
     "push   {r1}                      \n" /* push sched_active_thread */
     "mov    r12, sp                   \n" /* remember the exception SP */
     "mov    sp, r0                    \n" /* set user mode SP as active SP */
@@ -315,7 +315,7 @@ void __attribute__((naked)) __attribute__((used)) isr_pendsv(void) {
     "mov    sp, r12                   \n"
     "pop    {r1}                      \n" /* r1 = sched_active_thread */
 #else
-#if (defined(CPU_ARCH_CORTEX_M4F) || defined(CPU_ARCH_CORTEX_M7)) && defined(MODULE_CORTEXM_FPU)
+#if (defined(CPU_CORE_CORTEX_M4F) || defined(CPU_CORE_CORTEX_M7)) && defined(MODULE_CORTEXM_FPU)
     "tst    lr, #0x10                 \n"
     "it     eq                        \n"
     "vstmdbeq r0!, {s16-s31}          \n" /* save FPU registers if FPU is used */
@@ -332,8 +332,8 @@ void __attribute__((naked)) __attribute__((used)) isr_pendsv(void) {
     "bl     sched_run                 \n" /* perform scheduling */
 
     /* restore now current thread context */
-#if defined(CPU_ARCH_CORTEX_M0) || defined(CPU_ARCH_CORTEX_M0PLUS) \
-    || defined(CPU_ARCH_CORTEX_M23)
+#if defined(CPU_CORE_CORTEX_M0) || defined(CPU_CORE_CORTEX_M0PLUS) \
+    || defined(CPU_CORE_CORTEX_M23)
     "mov    lr, sp                    \n" /* save MSR stack pointer for later */
     "ldr    r0, =sched_active_thread  \n" /* load address of current TCB */
     "ldr    r0, [r0]                  \n" /* dereference TCB */
@@ -358,7 +358,7 @@ void __attribute__((naked)) __attribute__((used)) isr_pendsv(void) {
     "ldr    r1, [r0]                  \n" /* load tcb->sp to register 1 */
     "ldmia  r1!, {r0}                 \n" /* restore exception return value */
     "ldmia  r1!, {r4-r11}             \n" /* restore other registers */
-#if (defined(CPU_ARCH_CORTEX_M4F) || defined(CPU_ARCH_CORTEX_M7)) && defined(MODULE_CORTEXM_FPU)
+#if (defined(CPU_CORE_CORTEX_M4F) || defined(CPU_CORE_CORTEX_M7)) && defined(MODULE_CORTEXM_FPU)
     "tst    r0, #0x10                 \n"
     "it     eq                        \n"
     "vldmiaeq r1!, {s16-s31}          \n" /* load FPU registers if saved */
@@ -383,8 +383,8 @@ void __attribute__((naked)) __attribute__((used)) isr_svc(void)
      * svc is only used by threads, saving a couple of instructions. /Kaspar
      */
 
-#if defined(CPU_ARCH_CORTEX_M0) || defined(CPU_ARCH_CORTEX_M0PLUS) \
-    || defined(CPU_ARCH_CORTEX_M23)
+#if defined(CPU_CORE_CORTEX_M0) || defined(CPU_CORE_CORTEX_M0PLUS) \
+    || defined(CPU_CORE_CORTEX_M23)
     __asm__ volatile (
     ".thumb_func            \n"
     "movs   r0, #4          \n" /* if bit4(lr) == 1):       */
diff --git a/cpu/cortexm_common/vectors_cortexm.c b/cpu/cortexm_common/vectors_cortexm.c
index bd7cc9e3d1..5f39c5c552 100644
--- a/cpu/cortexm_common/vectors_cortexm.c
+++ b/cpu/cortexm_common/vectors_cortexm.c
@@ -240,7 +240,7 @@ __attribute__((naked)) void hard_fault_default(void)
         " use_psp:                          \n" /* else {                     */
         "mrs r0, psp                        \n" /*   r0 = psp                 */
         " out:                              \n" /* }                          */
-#if (defined(CPU_ARCH_CORTEX_M0) || defined(CPU_ARCH_CORTEX_M0PLUS)) \
+#if (defined(CPU_CORE_CORTEX_M0) || defined(CPU_CORE_CORTEX_M0PLUS)) \
     && defined(MODULE_CPU_CHECK_ADDRESS)
         /* catch intended HardFaults on Cortex-M0 to probe memory addresses */
         "ldr     r1, [r0, #0x04]            \n" /* read R1 from the stack        */
@@ -258,8 +258,8 @@ __attribute__((naked)) void hard_fault_default(void)
         "bx      lr                         \n" /* exit the exception handler    */
         " regular_handler:                  \n"
 #endif
-#if defined(CPU_ARCH_CORTEX_M0) || defined(CPU_ARCH_CORTEX_M0PLUS) \
-    || defined(CPU_ARCH_CORTEX_M23)
+#if defined(CPU_CORE_CORTEX_M0) || defined(CPU_CORE_CORTEX_M0PLUS) \
+    || defined(CPU_CORE_CORTEX_M23)
         "push {r4-r7}                       \n" /* save r4..r7 to the stack   */
         "mov r3, r8                         \n" /*                            */
         "mov r4, r9                         \n" /*                            */
@@ -279,8 +279,8 @@ __attribute__((naked)) void hard_fault_default(void)
     );
 }
 
-#if defined(CPU_ARCH_CORTEX_M0) || defined(CPU_ARCH_CORTEX_M0PLUS) \
-    || defined(CPU_ARCH_CORTEX_M23)
+#if defined(CPU_CORE_CORTEX_M0) || defined(CPU_CORE_CORTEX_M0PLUS) \
+    || defined(CPU_CORE_CORTEX_M23)
 /* Cortex-M0, Cortex-M0+ and Cortex-M23 lack the extended fault status
    registers found in Cortex-M3 and above. */
 #define CPU_HAS_EXTENDED_FAULT_REGISTERS 0
@@ -388,8 +388,8 @@ __attribute__((used)) void hard_fault_handler(uint32_t* sp, uint32_t corrupted,
             "mov lr, r1\n"
             "mov sp, %[orig_sp]\n"
             "mov r1, %[extra_stack]\n"
-#if defined(CPU_ARCH_CORTEX_M0) || defined(CPU_ARCH_CORTEX_M0PLUS) \
-    || defined(CPU_ARCH_CORTEX_M23)
+#if defined(CPU_CORE_CORTEX_M0) || defined(CPU_CORE_CORTEX_M0PLUS) \
+    || defined(CPU_CORE_CORTEX_M23)
             "ldm r1!, {r4-r7}\n"
             "mov r8, r4\n"
             "mov r9, r5\n"
@@ -422,8 +422,8 @@ void hard_fault_default(void)
 
 #endif /* DEVELHELP */
 
-#if defined(CPU_ARCH_CORTEX_M3) || defined(CPU_ARCH_CORTEX_M4) || \
-    defined(CPU_ARCH_CORTEX_M4F) || defined(CPU_ARCH_CORTEX_M7)
+#if defined(CPU_CORE_CORTEX_M3) || defined(CPU_CORE_CORTEX_M4) || \
+    defined(CPU_CORE_CORTEX_M4F) || defined(CPU_CORE_CORTEX_M7)
 void mem_manage_default(void)
 {
     core_panic(PANIC_MEM_MANAGE, "MEM MANAGE HANDLER");
@@ -489,8 +489,8 @@ ISR_VECTOR(0) const cortexm_base_t cortex_vector_base = {
         #endif  /* CORTEXM_VECTOR_RESERVED_0X28 */
 
         /* additional vectors used by M3, M4(F), and M7 */
-#if defined(CPU_ARCH_CORTEX_M3) || defined(CPU_ARCH_CORTEX_M4) || \
-    defined(CPU_ARCH_CORTEX_M4F) || defined(CPU_ARCH_CORTEX_M7)
+#if defined(CPU_CORE_CORTEX_M3) || defined(CPU_CORE_CORTEX_M4) || \
+    defined(CPU_CORE_CORTEX_M4F) || defined(CPU_CORE_CORTEX_M7)
         /* [-12] memory manage exception */
         [ 3] = mem_manage_default,
         /* [-11] bus fault exception */
diff --git a/cpu/efm32/Makefile.dep b/cpu/efm32/Makefile.dep
index 20ee155ce0..49c79d26d6 100644
--- a/cpu/efm32/Makefile.dep
+++ b/cpu/efm32/Makefile.dep
@@ -13,7 +13,7 @@ USEPKG += gecko_sdk
 USEMODULE += pm_layered
 
 # CMSIS-DSP is needed for arm_math.h on Cortex-M0+ architectures
-ifeq ($(CPU_ARCH),cortex-m0plus)
+ifeq ($(CPU_CORE),cortex-m0plus)
   USEPKG += cmsis-dsp
 endif
 
diff --git a/cpu/efm32/Makefile.features b/cpu/efm32/Makefile.features
index ac11c70577..86270ad515 100644
--- a/cpu/efm32/Makefile.features
+++ b/cpu/efm32/Makefile.features
@@ -1,7 +1,7 @@
 include $(RIOTCPU)/efm32/efm32-info.mk
 include $(RIOTCPU)/efm32/efm32-features.mk
 
-CPU_ARCH = $(EFM32_ARCHITECTURE)
+CPU_CORE = $(EFM32_ARCHITECTURE)
 
 FEATURES_PROVIDED += arch_efm32
 FEATURES_PROVIDED += cortexm_mpu
diff --git a/cpu/ezr32wg/Makefile.features b/cpu/ezr32wg/Makefile.features
index 343e1f208d..0f2f633a3a 100644
--- a/cpu/ezr32wg/Makefile.features
+++ b/cpu/ezr32wg/Makefile.features
@@ -1,4 +1,4 @@
-CPU_ARCH = cortex-m4f
+CPU_CORE = cortex-m4f
 
 FEATURES_PROVIDED += cortexm_mpu
 FEATURES_PROVIDED += periph_cpuid
diff --git a/cpu/kinetis/kinetis-info.mk b/cpu/kinetis/kinetis-info.mk
index 8ca1b14cea..06e24890a2 100644
--- a/cpu/kinetis/kinetis-info.mk
+++ b/cpu/kinetis/kinetis-info.mk
@@ -31,16 +31,16 @@ export KINETIS_SPEED := $(word 11, $(KINETIS_INFO))
 
 ifeq ($(KINETIS_CORE), Z)
   # Cortex-M0+
-  CPU_ARCH = cortex-m0plus
+  CPU_CORE = cortex-m0plus
   CPU_FAMILY = klx
 else ifeq ($(KINETIS_CORE), D)
   # Cortex-M4
-  CPU_ARCH = cortex-m4
+  CPU_CORE = cortex-m4
   CPU_FAMILY = kx
 else ifeq ($(KINETIS_CORE), F)
   # Cortex-M4F or Cortex-M7
   # TODO: Add floating point support
-  CPU_ARCH = cortex-m4
+  CPU_CORE = cortex-m4
   CPU_FAMILY = kx
 endif
 
diff --git a/cpu/lm4f120/Makefile.features b/cpu/lm4f120/Makefile.features
index 15ef943f2c..2dd54603d1 100644
--- a/cpu/lm4f120/Makefile.features
+++ b/cpu/lm4f120/Makefile.features
@@ -1,4 +1,4 @@
-CPU_ARCH = cortex-m4f
+CPU_CORE = cortex-m4f
 
 FEATURES_PROVIDED += cortexm_mpu
 
diff --git a/cpu/lpc1768/Makefile.features b/cpu/lpc1768/Makefile.features
index 738302a045..398a22da3a 100644
--- a/cpu/lpc1768/Makefile.features
+++ b/cpu/lpc1768/Makefile.features
@@ -1,4 +1,4 @@
-CPU_ARCH = cortex-m3
+CPU_CORE = cortex-m3
 # This CPU only implements one CPU_MODEL with the same name
 CPU_MODEL = lpc1768
 
diff --git a/cpu/mips_pic32mx/Makefile.features b/cpu/mips_pic32mx/Makefile.features
index a4f97354ef..e5f5a66f47 100644
--- a/cpu/mips_pic32mx/Makefile.features
+++ b/cpu/mips_pic32mx/Makefile.features
@@ -1,4 +1,5 @@
-CPU_ARCH = m4k
+CPU_ARCH = mips32
+CPU_CORE = m4k
 CPU_FAM = pic32mx
 
 -include $(RIOTCPU)/mips_pic32_common/Makefile.features
diff --git a/cpu/mips_pic32mz/Makefile.features b/cpu/mips_pic32mz/Makefile.features
index 2b5ef760f2..2881bec744 100644
--- a/cpu/mips_pic32mz/Makefile.features
+++ b/cpu/mips_pic32mz/Makefile.features
@@ -1,4 +1,5 @@
-CPU_ARCH = m5101
+CPU_ARCH = mips32
+CPU_CORE = m5101
 CPU_FAM = pic32mz
 
 FEATURES_PROVIDED += periph_hwrng
diff --git a/cpu/nrf51/Makefile.features b/cpu/nrf51/Makefile.features
index 32e53e90ce..c73c309f7f 100644
--- a/cpu/nrf51/Makefile.features
+++ b/cpu/nrf51/Makefile.features
@@ -1,4 +1,4 @@
-CPU_ARCH = cortex-m0
+CPU_CORE = cortex-m0
 CPU_FAM  = nrf51
 
 -include $(RIOTCPU)/nrf5x_common/Makefile.features
diff --git a/cpu/nrf52/Makefile.features b/cpu/nrf52/Makefile.features
index e429f3cbe9..b53dfdc582 100644
--- a/cpu/nrf52/Makefile.features
+++ b/cpu/nrf52/Makefile.features
@@ -1,4 +1,4 @@
-CPU_ARCH = cortex-m4f
+CPU_CORE = cortex-m4f
 CPU_FAM  = nrf52
 
 # The ADC does not depend on any board configuration, so always available
diff --git a/cpu/sam3/Makefile.features b/cpu/sam3/Makefile.features
index 642671c077..77b4c805a7 100644
--- a/cpu/sam3/Makefile.features
+++ b/cpu/sam3/Makefile.features
@@ -1,4 +1,4 @@
-CPU_ARCH = cortex-m3
+CPU_CORE = cortex-m3
 CPU_FAM  = sam3
 
 FEATURES_PROVIDED += cortexm_mpu
diff --git a/cpu/samd21/Makefile.features b/cpu/samd21/Makefile.features
index e57847cd7e..0f283eb987 100644
--- a/cpu/samd21/Makefile.features
+++ b/cpu/samd21/Makefile.features
@@ -1,4 +1,4 @@
-CPU_ARCH = cortex-m0plus
+CPU_CORE = cortex-m0plus
 CPU_FAM  = samd21
 
 FEATURES_PROVIDED += puf_sram
diff --git a/cpu/samd5x/Makefile.features b/cpu/samd5x/Makefile.features
index de7c61abc3..d2bcf5a8d9 100644
--- a/cpu/samd5x/Makefile.features
+++ b/cpu/samd5x/Makefile.features
@@ -1,4 +1,4 @@
-CPU_ARCH = cortex-m4f
+CPU_CORE = cortex-m4f
 CPU_FAM  = samd5x
 
 FEATURES_PROVIDED += periph_hwrng
diff --git a/cpu/saml1x/Makefile.features b/cpu/saml1x/Makefile.features
index 33527b32db..74b904eb6e 100644
--- a/cpu/saml1x/Makefile.features
+++ b/cpu/saml1x/Makefile.features
@@ -1,4 +1,4 @@
-CPU_ARCH = cortex-m23
+CPU_CORE = cortex-m23
 CPU_FAM  = saml1x
 
 FEATURES_PROVIDED += cortexm_mpu
diff --git a/cpu/saml21/Makefile.features b/cpu/saml21/Makefile.features
index d8e6b4ac12..3e4b0d6fa8 100644
--- a/cpu/saml21/Makefile.features
+++ b/cpu/saml21/Makefile.features
@@ -1,4 +1,4 @@
-CPU_ARCH = cortex-m0plus
+CPU_CORE = cortex-m0plus
 CPU_FAM  = saml21
 
 # The SAMR30 line of MCUs does not contain a TRNG
diff --git a/cpu/stm32/stm32_info.mk b/cpu/stm32/stm32_info.mk
index 8b6359d66d..effb8e25af 100644
--- a/cpu/stm32/stm32_info.mk
+++ b/cpu/stm32/stm32_info.mk
@@ -13,17 +13,17 @@ STM32_RAMMOD   = $(word 8, $(STM32_INFO))
 CPU_FAM = $(call lowercase,$(STM32_TYPE)$(STM32_FAMILY))
 
 ifeq (f0,$(CPU_FAM))
-  CPU_ARCH = cortex-m0
+  CPU_CORE = cortex-m0
 else ifneq (,$(filter $(CPU_FAM),f1 f2 l1))
-  CPU_ARCH = cortex-m3
+  CPU_CORE = cortex-m3
 else ifneq (,$(filter $(CPU_FAM),f3 f4 l4))
-  CPU_ARCH = cortex-m4f
+  CPU_CORE = cortex-m4f
 else ifeq (wb,$(CPU_FAM))
-  CPU_ARCH = cortex-m4
+  CPU_CORE = cortex-m4
 else ifeq (f7,$(CPU_FAM))
-  CPU_ARCH = cortex-m7
+  CPU_CORE = cortex-m7
 else ifeq (l0,$(CPU_FAM))
-  CPU_ARCH = cortex-m0plus
+  CPU_CORE = cortex-m0plus
 else
   $(error Not supported CPU family: 'stm32$(CPU_FAM)')
 endif
diff --git a/dist/tools/buildsystem_sanity_check/check.sh b/dist/tools/buildsystem_sanity_check/check.sh
index 92b6e7acc4..9974e3470a 100755
--- a/dist/tools/buildsystem_sanity_check/check.sh
+++ b/dist/tools/buildsystem_sanity_check/check.sh
@@ -111,6 +111,7 @@ UNEXPORTED_VARIABLES+=('JLINK_PRE_FLASH' 'JLINK_RESET_FILE')
 EXPORTED_VARIABLES_ONLY_IN_VARS=()
 EXPORTED_VARIABLES_ONLY_IN_VARS+=('APPDEPS')
 EXPORTED_VARIABLES_ONLY_IN_VARS+=('CPU_ARCH')
+EXPORTED_VARIABLES_ONLY_IN_VARS+=('CPU_CORE')
 EXPORTED_VARIABLES_ONLY_IN_VARS+=('CPU_FAM')
 EXPORTED_VARIABLES_ONLY_IN_VARS+=('NATIVEINCLUDES')
 EXPORTED_VARIABLES_ONLY_IN_VARS+=('UNDEF')
diff --git a/makefiles/arch/cortexm.inc.mk b/makefiles/arch/cortexm.inc.mk
index 2305ed4cc5..72977c948a 100644
--- a/makefiles/arch/cortexm.inc.mk
+++ b/makefiles/arch/cortexm.inc.mk
@@ -14,7 +14,7 @@ ifneq (llvm,$(TOOLCHAIN))
   CFLAGS += -mno-thumb-interwork
 
   # work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85606
-  ifneq (,$(filter cortex-m0%,$(CPU_ARCH)))
+  ifeq (armv6m,$(CPU_ARCH))
     CFLAGS_CPU += -march=armv6s-m
   endif
 endif
@@ -58,12 +58,12 @@ ifneq (1,$(BUILD_IN_DOCKER))
 endif # BUILD_IN_DOCKER
 
 CFLAGS += -DCPU_MODEL_$(call uppercase_and_underscore,$(CPU_MODEL))
-CFLAGS += -DCPU_ARCH_$(call uppercase_and_underscore,$(CPU_ARCH))
+CFLAGS += -DCPU_CORE_$(call uppercase_and_underscore,$(CPU_CORE))
 
 # Add corresponding FPU CFLAGS
 # clang assumes there is an FPU, no CFLAGS necessary
 ifneq (llvm, $(TOOLCHAIN))
-  ifeq ($(CPU_ARCH),cortex-m7)
+  ifeq ($(CPU_CORE),cortex-m7)
     _CORTEX_HW_FPU_CFLAGS = -mfloat-abi=hard -mfpu=fpv5-sp-d16
   else
     _CORTEX_HW_FPU_CFLAGS = -mfloat-abi=hard -mfpu=fpv4-sp-d16
@@ -73,28 +73,28 @@ endif
 # NOTE: This can be turned into normal conditional syntax once #9913 is fixed
 CFLAGS_FPU ?= $(if $(filter cortexm_fpu,$(USEMODULE)),$(_CORTEX_HW_FPU_CFLAGS),-mfloat-abi=soft)
 
-ifeq ($(CPU_ARCH),cortex-m4f)
+ifeq ($(CPU_CORE),cortex-m4f)
   MCPU = cortex-m4
 else
-  MCPU ?= $(CPU_ARCH)
+  MCPU ?= $(CPU_CORE)
 endif
 
 # CMSIS DSP needs to know about the CPU core
 ifneq (,$(filter cmsis-dsp,$(USEPKG)))
   # definition needed to use cmsis-dsp headers
-  ifeq ($(CPU_ARCH),cortex-m0)
+  ifeq ($(CPU_CORE),cortex-m0)
     CFLAGS += -DARM_MATH_CM0
-  else ifeq ($(CPU_ARCH),cortex-m0plus)
+  else ifeq ($(CPU_CORE),cortex-m0plus)
     CFLAGS += -DARM_MATH_CM0PLUS
-  else ifeq ($(CPU_ARCH),cortex-m3)
+  else ifeq ($(CPU_CORE),cortex-m3)
     CFLAGS += -DARM_MATH_CM3
-  else ifeq ($(CPU_ARCH),cortex-m4)
+  else ifeq ($(CPU_CORE),cortex-m4)
     CFLAGS += -DARM_MATH_CM4
-  else ifeq ($(CPU_ARCH),cortex-m4f)
+  else ifeq ($(CPU_CORE),cortex-m4f)
     CFLAGS += -DARM_MATH_CM4
-  else ifeq ($(CPU_ARCH),cortex-m7)
+  else ifeq ($(CPU_CORE),cortex-m7)
     CFLAGS += -DARM_MATH_CM7
-  else ifeq ($(CPU_ARCH),cortex-m23)
+  else ifeq ($(CPU_CORE),cortex-m23)
     CFLAGS += -DARM_MATH_CM23
   endif
 endif
diff --git a/makefiles/dependencies_debug.inc.mk b/makefiles/dependencies_debug.inc.mk
index a81280b7a4..c1444e4954 100644
--- a/makefiles/dependencies_debug.inc.mk
+++ b/makefiles/dependencies_debug.inc.mk
@@ -49,7 +49,7 @@ FEATURES_PROVIDED_KCONFIG = $(call lowercase,$(patsubst CONFIG_HAS_%,%,$(filter
 DEPENDENCY_DEBUG_OUTPUT_DIR ?= $(CURDIR)
 
 # Save variables that are used for parsing dependencies
-_DEPS_DEBUG_VARS += BOARD CPU CPU_MODEL CPU_ARCH CPU_FAM
+_DEPS_DEBUG_VARS += BOARD CPU CPU_MODEL CPU_FAM CPU_CORE CPU_ARCH
 _DEPS_DEBUG_VARS += FEATURES_PROVIDED _FEATURES_PROVIDED_SORTED
 _DEPS_DEBUG_VARS += FEATURES_REQUIRED _FEATURES_REQUIRED_SORTED
 _DEPS_DEBUG_VARS += FEATURES_REQUIRED_ANY _FEATURES_REQUIRED_ANY_SORTED
diff --git a/makefiles/info-global.inc.mk b/makefiles/info-global.inc.mk
index 29745c301a..84e4624799 100644
--- a/makefiles/info-global.inc.mk
+++ b/makefiles/info-global.inc.mk
@@ -40,6 +40,7 @@ define board_unsatisfied_features
   undefine CPU
   undefine CPU_MODEL
   undefine CPU_ARCH
+  undefine CPU_CORE
   undefine CPU_FAM
 
   include $(RIOTBASE)/Makefile.features
diff --git a/makefiles/vars.inc.mk b/makefiles/vars.inc.mk
index e9523e3cd2..78a6ca294f 100644
--- a/makefiles/vars.inc.mk
+++ b/makefiles/vars.inc.mk
@@ -12,7 +12,8 @@ export APPLICATION_MODULE    # The application module name.
 export BOARD                 # The board to compile the application for.
 export CPU                   # The CPU, set by the board's Makefile.features.
 export CPU_MODEL             # The specific identifier of the used CPU, used for some CPU implementations to differentiate between different memory layouts. Set by the board's Makefile.features.
-export CPU_ARCH              # The specific identifier of the core present in the CPU, used currently only for ARM CPU's. Needed for depency resolution.
+export CPU_CORE              # The specific identifier of the core present in the CPU. Needed for depency resolution.
+export CPU_ARCH              # The specific identifier of the architecture of the core defined in CPU_CORE.
 export CPU_FAM               # An intermediate identifier between CPU and CPU_MODEL that represents a sub-group of a Manufacturers CPU's.
 export MCU                   # The MCU, set by the board's Makefile.include, or defaulted to the same value as CPU.
 export INCLUDES              # The extra include paths, set by the various Makefile.include files.
diff --git a/pkg/micro-ecc/Makefile.include b/pkg/micro-ecc/Makefile.include
index a40d330c1d..a8206c73cf 100644
--- a/pkg/micro-ecc/Makefile.include
+++ b/pkg/micro-ecc/Makefile.include
@@ -1,6 +1,6 @@
 INCLUDES += -I$(PKGDIRBASE)/micro-ecc
 
-ifneq (,$(filter cortex-m0%,$(CPU_ARCH)))
+ifneq (,$(filter cortex-m0%,$(CPU_CORE)))
   # LLVM/clang can't handle the inline assembler instructions on M0 in this
   # package
   TOOLCHAINS_BLACKLIST += llvm
diff --git a/pkg/openthread/Makefile.include b/pkg/openthread/Makefile.include
index d399a8f902..5121661545 100644
--- a/pkg/openthread/Makefile.include
+++ b/pkg/openthread/Makefile.include
@@ -8,7 +8,7 @@ ifneq (,$(filter openthread_contrib,$(USEMODULE)))
   DIRS += $(OPENTHREAD_DIR)/contrib/netdev
 endif
 
-ifneq (,$(filter cortex-m0% cortex-m3%,$(CPU_ARCH)))
+ifneq (,$(filter cortex-m0% cortex-m3%,$(CPU_CORE)))
   # There are problem with unused `-mcpu...` arguments in clang and with
   # ranlib + LLVM/clang in this package with Cortex-M0 and M3
   TOOLCHAINS_BLACKLIST += llvm
diff --git a/pkg/qDSA/Makefile.dep b/pkg/qDSA/Makefile.dep
index b19f9fa6fd..851378b13b 100644
--- a/pkg/qDSA/Makefile.dep
+++ b/pkg/qDSA/Makefile.dep
@@ -1,4 +1,4 @@
-ifneq (,$(filter cortex-m23 cortex-m0%,$(CPU_ARCH)))
+ifneq (,$(filter cortex-m23 cortex-m0%,$(CPU_CORE)))
   USEMODULE += qDSA_asm
 endif
 
diff --git a/pkg/qDSA/Makefile.include b/pkg/qDSA/Makefile.include
index 693af41c0b..eb4f8db468 100644
--- a/pkg/qDSA/Makefile.include
+++ b/pkg/qDSA/Makefile.include
@@ -1,4 +1,4 @@
-ifneq (,$(filter cortex-m23 cortex-m0%,$(CPU_ARCH)))
+ifneq (,$(filter cortex-m23 cortex-m0%,$(CPU_CORE)))
   QDSA_IMPL ?= arm
 else
 ifneq (,$(filter atmega_common,$(USEMODULE)))
@@ -12,7 +12,7 @@ export QDSA_IMPL
 
 INCLUDES += -I$(PKGDIRBASE)/qDSA/$(QDSA_IMPL)
 
-ifeq (cortex-m0plus,$(CPU_ARCH))
+ifeq (cortex-m0plus,$(CPU_CORE))
   # There are problems with the LLVM assembler and the Cortex-M0+ instruction
   # set with this package
   TOOLCHAINS_BLACKLIST += llvm
diff --git a/pkg/relic/Makefile.include b/pkg/relic/Makefile.include
index 5dc828d0ec..218bdfd82c 100644
--- a/pkg/relic/Makefile.include
+++ b/pkg/relic/Makefile.include
@@ -1,6 +1,6 @@
 INCLUDES += -I$(PKGDIRBASE)/relic/include
 
-ifneq (,$(filter cortex-m%,$(CPU_ARCH)))
+ifneq (,$(filter cortex-m%,$(CPU_CORE)))
   # relic package package is not using system includes right now, so
   # many newlib headers (not even stdio.h) are not found.
   # Fixed in #9821 for jerryscript, should be applicable here too.
diff --git a/pkg/tensorflow-lite/Makefile.include b/pkg/tensorflow-lite/Makefile.include
index aee56bfccd..ae3f8bde6f 100644
--- a/pkg/tensorflow-lite/Makefile.include
+++ b/pkg/tensorflow-lite/Makefile.include
@@ -1,6 +1,6 @@
 INCLUDES += -I$(PKGDIRBASE)/tensorflow-lite
 
-ifneq (,$(filter cortex-m%,$(CPU_ARCH)))
+ifneq (,$(filter cortex-m%,$(CPU_CORE)))
   # LLVM/clang triggers a hard fault on Cortex-M
   TOOLCHAINS_BLACKLIST += llvm
 endif
diff --git a/tests/mtd_flashpage/main.c b/tests/mtd_flashpage/main.c
index 62e3a2438f..25cca3572d 100644
--- a/tests/mtd_flashpage/main.c
+++ b/tests/mtd_flashpage/main.c
@@ -144,7 +144,7 @@ static void test_mtd_write_read(void)
     TEST_ASSERT_EQUAL_INT(-EINVAL, ret);
 
     /* Only Cortex-M0 doesn't allow unaligned reads */
-#if defined(CPU_ARCH_CORTEX_M0)
+#if defined(CPU_CORE_CORTEX_M0)
     ret = mtd_read(dev, buf_read, TEST_ADDRESS1 + sizeof(buf_empty), sizeof(buf_read));
     TEST_ASSERT_EQUAL_INT(-EINVAL, ret);
 #endif
diff --git a/tests/pkg_c25519/Makefile b/tests/pkg_c25519/Makefile
index b2d770f2f0..6ebadea0db 100644
--- a/tests/pkg_c25519/Makefile
+++ b/tests/pkg_c25519/Makefile
@@ -7,7 +7,7 @@ USEPKG += c25519
 include $(RIOTBASE)/Makefile.include
 
 # c25519 takes up to 1.5K in stack, almost independent of the platform
-ifneq (,$(filter cortex-%,$(CPU_ARCH)))
+ifneq (,$(filter cortex-%,$(CPU_CORE)))
   CFLAGS += -DTHREAD_STACKSIZE_MAIN=\(THREAD_STACKSIZE_DEFAULT+THREAD_EXTRA_STACKSIZE_PRINTF\)
 else
 ifneq (,$(filter atmega_common,$(USEMODULE)))
diff --git a/tests/unittests/tests-core/tests-core-atomic.c b/tests/unittests/tests-core/tests-core-atomic.c
index ffccd07928..98f6f6cc84 100644
--- a/tests/unittests/tests-core/tests-core-atomic.c
+++ b/tests/unittests/tests-core/tests-core-atomic.c
@@ -27,7 +27,7 @@ static void test_atomic_flag(void)
 }
 
 /* Prevent compiler optimization for SAML1X because of gcc internal bug */
-#ifdef CPU_ARCH_CORTEX_M23
+#ifdef CPU_CORE_CORTEX_M23
 #pragma GCC push_options
 #pragma GCC optimize ("O0")
 #endif