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cpu/sam3x8e: adapted to centralized cpu conf

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This commit is contained in:
Hauke Petersen 2015-05-27 23:06:52 +02:00
parent a97cdaaf8d
commit 4d3b147122
3 changed files with 10 additions and 38 deletions
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5
cpu/sam3x8e/cpu.c
View File

@ -26,7 +26,6 @@ void cpu_init(void)
{ {
/* disable the watchdog timer */ /* disable the watchdog timer */
WDT->WDT_MR |= WDT_MR_WDDIS; WDT->WDT_MR |= WDT_MR_WDDIS;
/* initialize the Cortex-M core */
/* set PendSV interrupt priority to lowest possible value */ cortexm_init();
NVIC_SetPriority(PendSV_IRQn, 0xff);
} }

35
cpu/sam3x8e/include/cpu_conf.h
View File

@ -25,41 +25,14 @@ extern "C" {
#endif #endif
/** /**
* @name Kernel configuration * @brief ARM Cortex-M specific CPU configuration
*
* TODO: measure and adjust for the cortex-m3
* @{ * @{
*/ */
#define THREAD_EXTRA_STACKSIZE_PRINTF (2500) #define CPU_DEFAULT_IRQ_PRIO (1U)
#define CPU_IRQ_NUMOF (45U)
#ifndef THREAD_STACKSIZE_DEFAULT #define CPU_FLASH_BASE IFLASH0_ADDR
#define THREAD_STACKSIZE_DEFAULT (2500)
#endif
#define THREAD_STACKSIZE_IDLE (512)
/** @} */ /** @} */
/**
* @name UART0 buffer size definition for compatibility reasons
*
* TODO: remove once the remodeling of the uart0 driver is done
* @{
*/
#ifndef UART0_BUFSIZE
#define UART0_BUFSIZE (128)
#endif
/** @} */
/**
* @brief Definition of different panic modes
*/
typedef enum {
HARD_FAULT,
BUS_FAULT,
USAGE_FAULT,
DUMMY_HANDLER
} panic_t;
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

8
cpu/sam3x8e/startup.c
View File

@ -80,7 +80,7 @@ void reset_handler(void)
*/ */
void dummy_handler(void) void dummy_handler(void)
{ {
core_panic(DUMMY_HANDLER, "DUMMY HANDLER"); core_panic(PANIC_DUMMY_HANDLER, "DUMMY HANDLER");
} }
void isr_nmi(void) void isr_nmi(void)
@ -100,17 +100,17 @@ void isr_debug_mon(void)
void isr_hard_fault(void) void isr_hard_fault(void)
{ {
core_panic(HARD_FAULT, "HARD FAULT"); core_panic(PANIC_HARD_FAULT, "HARD FAULT");
} }
void isr_bus_fault(void) void isr_bus_fault(void)
{ {
core_panic(BUS_FAULT, "BUS FAULT"); core_panic(PANIC_BUS_FAULT, "BUS FAULT");
} }
void isr_usage_fault(void) void isr_usage_fault(void)
{ {
core_panic(USAGE_FAULT, "USAGE FAULT"); core_panic(PANIC_USAGE_FAULT, "USAGE FAULT");
} }
/* Cortex-M specific interrupt vectors */ /* Cortex-M specific interrupt vectors */