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Merge pull request #16433 from ant9000/pr_saml21_coreclock_enhancements

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SAML21 CPU: support 4MHz, 8MHz, 12MHz CORE_CORECLOCK choices
This commit is contained in:
Dylan Laduranty 2021-05-04 21:41:54 +02:00 committed by GitHub
commit 4af37a7751
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1 changed files with 16 additions and 6 deletions
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22
cpu/saml21/cpu.c
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@ -244,11 +244,23 @@ void cpu_init(void)
while (GCLK->CTRLA.reg & GCLK_CTRLA_SWRST) {} while (GCLK->CTRLA.reg & GCLK_CTRLA_SWRST) {}
while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) {} while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) {}
#if (CLOCK_CORECLOCK > 12000000U)
PM->PLCFG.reg = PM_PLCFG_PLSEL_PL2; PM->PLCFG.reg = PM_PLCFG_PLSEL_PL2;
while (!PM->INTFLAG.bit.PLRDY) {} while (!PM->INTFLAG.bit.PLRDY) {}
#endif
/* set OSC16M to 16MHz */ /* set OSC16M according to CLOCK_CORECLOCK */
OSCCTRL->OSC16MCTRL.bit.FSEL = 3; #if (CLOCK_CORECLOCK == 48000000U) || (CLOCK_CORECLOCK == 16000000U)
OSCCTRL->OSC16MCTRL.bit.FSEL = OSCCTRL_OSC16MCTRL_FSEL_16_Val;
#elif (CLOCK_CORECLOCK == 12000000U)
OSCCTRL->OSC16MCTRL.bit.FSEL = OSCCTRL_OSC16MCTRL_FSEL_12_Val;
#elif (CLOCK_CORECLOCK == 8000000U)
OSCCTRL->OSC16MCTRL.bit.FSEL = OSCCTRL_OSC16MCTRL_FSEL_8_Val;
#elif (CLOCK_CORECLOCK == 4000000U)
OSCCTRL->OSC16MCTRL.bit.FSEL = OSCCTRL_OSC16MCTRL_FSEL_4_Val;
#else
#error "Please select a valid CPU frequency"
#endif
OSCCTRL->OSC16MCTRL.bit.ONDEMAND = 1; OSCCTRL->OSC16MCTRL.bit.ONDEMAND = 1;
OSCCTRL->OSC16MCTRL.bit.RUNSTDBY = 0; OSCCTRL->OSC16MCTRL.bit.RUNSTDBY = 0;
@ -264,12 +276,10 @@ void cpu_init(void)
_dfll_setup(); _dfll_setup();
/* Setup GCLK generators */ /* Setup GCLK generators */
#if (CLOCK_CORECLOCK == 16000000U) #if USE_DFLL
_gclk_setup(SAM0_GCLK_MAIN, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC16M);
#elif (CLOCK_CORECLOCK == 48000000U)
_gclk_setup(SAM0_GCLK_MAIN, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL48M); _gclk_setup(SAM0_GCLK_MAIN, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL48M);
#else #else
#error "Please select a valid CPU frequency" _gclk_setup(SAM0_GCLK_MAIN, GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC16M);
#endif #endif
/* Ensure APB Backup domain clock is within the 6MHZ limit, BUPDIV value /* Ensure APB Backup domain clock is within the 6MHZ limit, BUPDIV value