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many typo fixes

Browse Source 
Signed-off-by: Francois Berder <18538310+francois-berder@users.noreply.github.com>
This commit is contained in:
Francois Berder 2019-09-14 14:47:10 +01:00 committed by Kaspar Schleiser
parent ab94b7c8ad
commit 4a31f94cfc
166 changed files with 296 additions and 296 deletions
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2
core/include/byteorder.h
View File

@ -367,7 +367,7 @@ static inline le_uint64_t byteorder_btolll(be_uint64_t v)
}
/**
* @brief Swaps the byteorder according to the endianess
* @brief Swaps the byteorder according to the endianness
*/
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
# define _byteorder_swap(V, T) (byteorder_swap##T((V)))

4
core/include/thread.h
View File

@ -348,10 +348,10 @@ kernel_pid_t thread_create(char *stack,
const char *name);
/**
* @brief Retreive a thread control block by PID.
* @brief Retrieve a thread control block by PID.
* @details This is a bound-checked variant of accessing `sched_threads[pid]` directly.
* If you know that the PID is valid, then don't use this function.
* @param[in] pid Thread to retreive.
* @param[in] pid Thread to retrieve.
* @return `NULL` if the PID is invalid or there is no such thread.
*/
volatile thread_t *thread_get(kernel_pid_t pid);

4
core/rmutex.c
View File

@ -51,7 +51,7 @@ static int _lock(rmutex_t *rmutex, int trylock)
* mutex_lock(). However the read access to owner is not
* locked, and owner can be changed by a thread that is
* holding the lock (e.g.: holder unlocks the mutex, new
* holder aquired the lock). The atomic access strategy
* holder acquired the lock). The atomic access strategy
* 'relaxed' ensures, that the value of rmutex->owner is read
* consistent.
*
@ -72,7 +72,7 @@ static int _lock(rmutex_t *rmutex, int trylock)
* Note for Case 2:
*
* Because the mutex rmutex->owner is only written be the
* owner (me), rmutex->owner stays constant througout the
* owner (me), rmutex->owner stays constant throughout the
* complete call and rmutex->refcount is protected
* (read/write) by the mutex.
*/

2
cpu/atmega_common/thread_arch.c
View File

@ -172,7 +172,7 @@ char *thread_stack_init(thread_task_func_t task_func, void *arg,
* @brief thread_stack_print prints the stack to stdout.
* It depends on getting the correct values for stack_start, stack_size and sp
* from sched_active_thread.
* Maybe it would be good to change that to way that is less dependant on
* Maybe it would be good to change that to way that is less dependent on
* getting correct values elsewhere (since it is a debugging tool and in the
* presence of bugs the data may be corrupted).
*/

4
cpu/cc2538/periph/adc.c
View File

@ -43,7 +43,7 @@ int adc_init(adc_t line)
/* stop random number generator, and set STSEL = 1 */
soc_adc->ADCCON1 = (SOC_ADC_ADCCON1_STSEL_M | SOC_ADC_ADCCON1_RCTRL_M);
/* disable any DMA, continous ADC settings */
/* disable any DMA, continuous ADC settings */
soc_adc->ADCCON2 = 0x0;
/* configure ADC GPIO as analog input */
gpio_init(adc_config[line], GPIO_IN_ANALOG);
@ -79,7 +79,7 @@ int adc_sample(adc_t line, adc_res_t res)
return -1;
}
/**
* @attention CC2538 ADC supports differential comparision of two analog
* @attention CC2538 ADC supports differential comparison of two analog
* GPIO inputs, hence negative values are possible. RIOT currently allows
* positive ADC output only. Thus, reduce shift by one to compensate and
* get full value range according to ADC resolution. E.g. 10 Bit resultion

2
cpu/cc2538/periph/timer.c
View File

@ -187,7 +187,7 @@ int timer_clear(tim_t tim, int channel)
if ( (tim >= TIMER_NUMOF) || (channel >= (int)timer_config[tim].chn) ) {
return -1;
}
/* clear interupt flags */
/* clear interrupt flags */
dev(tim)->IMR &= ~(chn_isr_cfg[channel].flag);
return 0;

4
cpu/cortexm_common/cortexm_init.c
View File

@ -93,7 +93,7 @@ bool cpu_check_address(volatile const char *address)
*address;
/* Check BFARVALID flag */
if ((SCB->CFSR & BFARVALID_MASK) != 0) {
/* Bus Fault occured reading the address */
/* Bus Fault occurred reading the address */
is_valid = false;
}
@ -110,7 +110,7 @@ bool cpu_check_address(volatile const char *address)
__asm__ volatile (
"movs r5, #1 \n" /* R5 will be set to 0 by HardFault handler */
/* to indicate HardFault has occured */
/* to indicate HardFault has occurred */
"ldr r1, =0xDEADF00D \n" /* set magic number */
"ldr r2, =0xCAFEBABE \n" /* 2nd magic to be sure */
"ldrb r3, %1 \n" /* probe address */

4
cpu/efm32/periph/i2c.c
View File

@ -191,7 +191,7 @@ int i2c_read_regs(i2c_t dev, uint16_t address, uint16_t reg,
return -EOPNOTSUPP;
}
/* Handle endianess of register if 16 bit */
/* Handle endianness of register if 16 bit */
if (flags & I2C_REG16) {
reg_end = htons(reg); /* Make sure register is in big-endian on I2C bus */
}
@ -237,7 +237,7 @@ int i2c_write_regs(i2c_t dev, uint16_t address, uint16_t reg,
return -EOPNOTSUPP;
}
/* Handle endianess of register if 16 bit */
/* Handle endianness of register if 16 bit */
if (flags & I2C_REG16) {
reg_end = htons(reg); /* Make sure register is in big-endian on I2C bus */
}

2
cpu/esp32/cxx/cxa_guard.cpp
View File

@ -75,7 +75,7 @@ namespace __cxxabiv1
assert(0);
}
/* mark the initialization in process and aquire */
/* mark the initialization in process and acquire */
_gt->pending = 1;
critical_exit();

2
cpu/esp32/ld/esp32.common.ld
View File

@ -85,7 +85,7 @@ SECTIONS
.iram0.text :
{
/* Code marked as runnning out of IRAM */
/* Code marked as running out of IRAM */
_iram_text_start = ABSOLUTE(.);
*(.iram1 .iram1.*)

2
cpu/esp32/periph/i2c_sw.c
View File

@ -472,7 +472,7 @@ static /* IRAM */ int _i2c_start_cond(_i2c_bus_t* bus)
/* SDA = passive HIGH (floating and pulled-up) */
_i2c_sda_high (bus);
/* t_VD;DAT not neccessary */
/* t_VD;DAT not necessary */
/* _i2c_delay (bus); */
/* SCL = passive HIGH (floating and pulled-up) */

8
cpu/esp32/periph/pwm.c
View File

@ -41,7 +41,7 @@
#define PWM_CLK (160000000UL) /* base clock of PWM devices */
#define PWM_CPS_MAX (10000000UL) /* maximum cycles per second supported */
#define PWM_CPS_MIN (2500UL) /* minumum cycles per second supported */
#define PWM_CPS_MIN (2500UL) /* minimum cycles per second supported */
#define PWM_TIMER_MOD_FREEZE 0 /* timer is disabled */
#define PWM_TIMER_MOD_UP 1 /* timer counts up */
@ -54,7 +54,7 @@
#define PWM_TIMER_STARTS_STOPS_AT_TEZ 3 /* PWM starts and stops at next TEZ */
#define PWM_TIMER_STARTS_STOPS_AT_TEP 4 /* PWM starts and stops at next TEP */
#define PWM_TIMER_UPDATE_IMMIDIATE 0 /* update period immediatly */
#define PWM_TIMER_UPDATE_IMMIDIATE 0 /* update period immediately */
#define PWM_TIMER_UPDATE_AT_TEZ 1 /* update period at TEZ */
#define PWM_TIMER_UPDATE_AT_SYNC 2 /* update period at sync */
#define PWM_TIMER_UPDATE_AT_TEZ_SYNC 3 /* update period at TEZ and sync */
@ -319,7 +319,7 @@ static void _pwm_start(pwm_t pwm)
uint32_t cps = period * freq;
/* maximum number of timer clock cycles per second (freq*period) must not
be greater than PWM_CPS_MAX, reduce the freq if neccessary and keep
be greater than PWM_CPS_MAX, reduce the freq if necessary and keep
the resolution */
if (cps > PWM_CPS_MAX) {
freq = PWM_CPS_MAX / period;
@ -328,7 +328,7 @@ static void _pwm_start(pwm_t pwm)
__func__, freq);
}
/* minimum number of timer clock cycles per second (freq*period) must not
be less than PWM_CPS_MIN, increase the freq if neccessary and keep
be less than PWM_CPS_MIN, increase the freq if necessary and keep
the resolution */
else if (cps < PWM_CPS_MIN) {
freq = PWM_CPS_MIN / period;

4
cpu/esp32/periph/rtc.c
View File

@ -21,7 +21,7 @@
/*
* If RTC_TIMER_USED is 0, the microsecond system timer is used to emulate an
* RTC, otherwise the RTC timer is used. Advantage of using RTC over sytem
* RTC, otherwise the RTC timer is used. Advantage of using RTC over system
* timer is that it also continues in deep sleep and after software reset.
*/
#define RTC_TIMER_USED 1
@ -175,7 +175,7 @@ int rtc_set_alarm(struct tm *time, rtc_alarm_cb_t cb, void *arg)
/*
* RTC doesn't provide alarm functionality in active mode. At least
* the RTC main timer seems not to work. Therefore we always use the
* system timer for alarms. The Advantage of using RTC over sytem timer
* system timer for alarms. The Advantage of using RTC over system timer
* is that it also continues in deep sleep and after software reset.
*/
#if 0 /* TODO should be RTC_TIMER_USED */

4
cpu/esp32/periph/spi.c
View File

@ -49,7 +49,7 @@
#define FSPI_MISO GPIO7
#define FSPI_MOSI GPIO8
/** stucture which decribes all properties of one SPI bus */
/** structure which describes all properties of one SPI bus */
struct _spi_bus_t {
spi_dev_t* regs; /* pointer to register data struct of the SPI device */
uint8_t mod; /* peripheral hardware module of the SPI interface */
@ -180,7 +180,7 @@ static void _spi_init_internal (spi_t bus)
_spi[bus].regs->ctrl.fastrd_mode = 0;
_spi[bus].regs->ctrl.wp = 0;
/* aquire and release to set default parameters */
/* acquire and release to set default parameters */
spi_acquire(bus, GPIO_UNDEF, SPI_MODE_0, SPI_CLK_1MHZ);
spi_release(bus);
}

2
cpu/esp32/periph/timer.c
View File

@ -173,7 +173,7 @@ void IRAM hw_timer_handler(void* arg)
(void)arg;
/* since all timer interrupt sources are routed to the same cpu interrupt */
/* signal, we can't use arg to identify the timer wich caused the it */
/* signal, we can't use arg to identify the timer which caused the it */
irq_isr_enter();

2
cpu/esp32/startup.c
View File

@ -208,7 +208,7 @@ static void IRAM system_clk_init (void)
/* set SLOW_CLK to internal low power clock of 150 kHz */
rtc_select_slow_clk(RTC_SLOW_FREQ_RTC);
/* wait until UART is idle to avoid loosing output */
/* wait until UART is idle to avoid losing output */
uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
ets_printf("Switching system clocks can lead to some unreadable characters\n");
ets_printf("This message is usually not visible at the console\n");

4
cpu/esp32/syscalls.c
View File

@ -433,8 +433,8 @@ void system_wdt_init (void)
TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE; /* disable write protection */
TIMERG0.wdt_config0.stg0 = TIMG_WDT_STG_SEL_INT; /* stage0 timeout: interrupt */
TIMERG0.wdt_config0.stg1 = TIMG_WDT_STG_SEL_RESET_SYSTEM; /* stage1 timeout: sys reset */
TIMERG0.wdt_config0.sys_reset_length = 7; /* sys reset signal lenght: 3.2 us */
TIMERG0.wdt_config0.cpu_reset_length = 7; /* sys reset signal lenght: 3.2 us */
TIMERG0.wdt_config0.sys_reset_length = 7; /* sys reset signal length: 3.2 us */
TIMERG0.wdt_config0.cpu_reset_length = 7; /* sys reset signal length: 3.2 us */
TIMERG0.wdt_config0.edge_int_en = 0;
TIMERG0.wdt_config0.level_int_en = 1;

2
cpu/esp32/thread_arch.c
View File

@ -140,7 +140,7 @@ char* thread_stack_init(thread_task_func_t task_func, void *arg, void *stack_sta
/* Clear whole stack with a known value to assist debugging */
#if !defined(DEVELHELP) && !defined(SCHED_TEST_STACK)
/* Unfortunatly, this affects thread_measure_stack_free function */
/* Unfortunately, this affects thread_measure_stack_free function */
memset(stack_start, 0, stack_size);
#else
memset(sp, 0, XT_STK_FRMSZ + XT_CP_SIZE);

2
cpu/esp_common/esp-now/esp_now_netdev.h
View File

@ -61,7 +61,7 @@ extern "C" {
extern const netdev_driver_t esp_now_driver;
/**
* @brief Header with neccesary flags for ESP-NOW packets
* @brief Header with necessary flags for ESP-NOW packets
*/
typedef struct __attribute__((packed))
{

6
cpu/fe310/periph/gpio.c
View File

@ -115,7 +115,7 @@ void gpio_isr(int num)
isr_ctx[pin].cb(isr_ctx[pin].arg);
}
/* Clear interupt */
/* Clear interrupt */
switch (isr_flank[pin]) {
case GPIO_FALLING:
GPIO_REG(GPIO_FALL_IP) |= (1 << pin);
@ -169,7 +169,7 @@ void gpio_irq_enable(gpio_t pin)
return;
}
/* Enable interupt for pin */
/* Enable interrupt for pin */
switch (isr_flank[pin]) {
case GPIO_FALLING:
GPIO_REG(GPIO_FALL_IE) |= (1 << pin);
@ -196,7 +196,7 @@ void gpio_irq_disable(gpio_t pin)
return;
}
/* Disable interupt for pin */
/* Disable interrupt for pin */
switch (isr_flank[pin]) {
case GPIO_FALLING:
GPIO_REG(GPIO_FALL_IE) &= ~(1 << pin);

2
cpu/kinetis/dist/check-fcfield.sh vendored
View File

@ -35,7 +35,7 @@ get_fc_field()
elif [ ${1##*.} = hex ]; then
"${OBJDUMP}" --start-address=${FCFIELD_START} --stop-address=${FCFIELD_END} ${1} -s
else
echo "Unkown file extension: ${1##*.}"
echo "Unknown file extension: ${1##*.}"
exit 1
fi
}

2
cpu/kinetis/include/vectors_kinetis.h
View File

@ -92,7 +92,7 @@ void isr_dma14_dma30(void); /**< DMA channel 14, 30 transfer complete interrupt
void isr_dma15_dma31(void); /**< DMA channel 15, 31 transfer complete interrupt handler */
void isr_dma_error(void); /**< DMA Error interrupt handler */
void isr_enet_1588_timer(void); /**< Ethernet MAC IEEE 1588 timer interrupt handler */
void isr_enet_error(void); /**< Ethernet MAC error and miscelaneous interrupt handler */
void isr_enet_error(void); /**< Ethernet MAC error and miscellaneous interrupt handler */
void isr_enet_receive(void); /**< Ethernet MAC receive interrupt handler */
void isr_enet_transmit(void); /**< Ethernet MAC transmit interrupt handler */
void isr_ftfa(void); /**< FTFA Command complete interrupt handler */

2
cpu/kinetis/vectors.c
View File

@ -366,7 +366,7 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
[ENET_1588_Timer_IRQn] = isr_enet_1588_timer, /* Ethernet MAC IEEE 1588 Timer Interrupt */
[ENET_Transmit_IRQn] = isr_enet_transmit, /* Ethernet MAC Transmit Interrupt */
[ENET_Receive_IRQn] = isr_enet_receive, /* Ethernet MAC Receive Interrupt */
[ENET_Error_IRQn ] = isr_enet_error, /* Ethernet MAC Error and miscelaneous Interrupt */
[ENET_Error_IRQn ] = isr_enet_error, /* Ethernet MAC Error and miscellaneous Interrupt */
#endif
#ifdef LPUART0
[LPUART0_IRQn ] = isr_lpuart0, /* LPUART0 status/error interrupt */

2
cpu/lm4f120/periph/uart.c
View File

@ -137,7 +137,7 @@ void isr_uart0(void)
ulStatus = ROM_UARTIntStatus(UART0_BASE, true);
ROM_UARTIntClear(UART0_BASE, ulStatus);
/* Are we interrupted due to a recieved character */
/* Are we interrupted due to a received character */
if(ulStatus & (UART_INT_RX | UART_INT_RT))
{
while(ROM_UARTCharsAvail(UART0_BASE))

4
cpu/lpc2387/lpc23xx-iap.c
View File

@ -196,9 +196,9 @@ uint32_t blank_check_sector(uint32_t tmp_sect1, uint32_t tmp_sect2)
* affected sectors are automatically protected again once the copy command is
* successfully executed. the boot sector cannot be written by this command.
* Command: 51
* Param0: (DST) Destination Flash adress where data bytes are to be written.
* Param0: (DST) Destination Flash address where data bytes are to be written.
* This address should be a 512 byte boundary.
* Param1: (SRC) Source RAM adress from which data byre are to be read.
* Param1: (SRC) Source RAM address from which data byre are to be read.
* Param2: Number of bytes to be written. Should be 512 | 1024 | 4096 | 8192.
* Param3: System Clock Frequency (CCLK) in KHz.
*

14
cpu/lpc2387/mci/lpc2387-mci.c
View File

@ -29,7 +29,7 @@
#define MCLK_RW 18000000UL /* MCICLK for data transfer (PCLK divided by even number) */
/* This MCI driver assumes that MCLK_RW is CCLK/4 or slower. If block buffer underrun/overrun
/ occured due to any interrupt by higher priority process or slow external memory, increasing
/ occurred due to any interrupt by higher priority process or slow external memory, increasing
/ N_BUF or decreasing MCLK_RW will solve it. */
@ -130,7 +130,7 @@ void Isr_MCI(void)
}
}
}
else { /* An MCI error occured (not DataBlockEnd) */
else { /* An MCI error occurred (not DataBlockEnd) */
xs |= 8;
}
@ -729,7 +729,7 @@ diskio_result_t mci_read(unsigned char *buff, unsigned long sector, unsigned cha
}
if (XferStat & 0xC) {
break; /* Abort if any error has occured */
break; /* Abort if any error has occurred */
}
copy_al2un(buff, DmaBuff[rp], 512); /* Pop an block */
@ -737,7 +737,7 @@ diskio_result_t mci_read(unsigned char *buff, unsigned long sector, unsigned cha
XferRp = rp = (rp + 1) % N_BUF; /* Next DMA buffer */
if (XferStat & 0xC) {
break; /* Abort if overrun has occured */
break; /* Abort if overrun has occurred */
}
buff += 512; /* Next user buffer address */
@ -830,14 +830,14 @@ diskio_result_t mci_write(const unsigned char *buff, unsigned long sector, unsig
}
if (XferStat & 0xC) {
break; /* Abort if block underrun or any MCI error has occured */
break; /* Abort if block underrun or any MCI error has occurred */
}
copy_un2al(DmaBuff[wp], (unsigned char *)(unsigned int)buff, 512); /* Push a block */
XferWp = wp = (wp + 1) % N_BUF; /* Next DMA buffer */
if (XferStat & 0xC) {
break; /* Abort if block underrun has occured */
break; /* Abort if block underrun has occurred */
}
count--;
@ -847,7 +847,7 @@ diskio_result_t mci_write(const unsigned char *buff, unsigned long sector, unsig
while (!(XferStat & 0xC)) {} /* Wait for all blocks sent (block underrun) */
if (XferStat & 0x8) {
count = 1; /* Abort if any MCI error has occured */
count = 1; /* Abort if any MCI error has occurred */
}
stop_transfer(); /* Close data path */

2
cpu/lpc2387/periph/rtc.c
View File

@ -127,7 +127,7 @@ int rtc_set_alarm(struct tm *localt, rtc_alarm_cb_t cb, void *arg)
RTC_ALDOY = localt->tm_yday;
RTC_ALMON = localt->tm_mon + 1;
RTC_ALYEAR = localt->tm_year;
RTC_AMR = 0; /* set wich alarm fields to check */
RTC_AMR = 0; /* set which alarm fields to check */
DEBUG("alarm set %2lu.%2lu.%4lu %2lu:%2lu:%2lu\n",
RTC_ALDOM, RTC_ALMON, RTC_ALYEAR, RTC_ALHOUR, RTC_ALMIN, RTC_ALSEC);

4
cpu/mips32r2_common/newlib_syscalls_mips_uhi/syscalls.c
View File

@ -70,7 +70,7 @@ void _exit(int n)
exit(n);
/* cppcheck-suppress unreachableCode
* (reason: pm_off spins indefinately after pulling the plug) */
* (reason: pm_off spins indefinitely after pulling the plug) */
pm_off();
}
@ -127,7 +127,7 @@ pid_t _getpid_r(struct _reent *ptr)
* @param sig signal number to pass to process
*
* @return -1 on error
* @return 0 on sucess
* @return 0 on success
*/
__attribute__ ((weak))
int _kill_r(struct _reent *r, pid_t pid, int sig)

2
cpu/mips32r2_common/periph/pm.c
View File

@ -24,7 +24,7 @@
void pm_set_lowest(void)
{
/* Dont wait if interrupts are not enabled - we would never return!*/
/* Don't wait if interrupts are not enabled - we would never return!*/
if (mips32_get_c0(C0_STATUS) & SR_IE) {
__asm volatile ("wait");
}

6
cpu/mips32r2_common/thread_arch.c
View File

@ -315,9 +315,9 @@ _mips_handle_exception(struct gpctx *ctx, int exception)
/*
* The toolchain Exception restore code just wholesale copies the
* status register from the context back to the register loosing
* any changes that may have occured, 'status' is really global state
* You dont enable interrupts on one thread and not another...
* status register from the context back to the register losing
* any changes that may have occurred, 'status' is really global state
* You don't enable interrupts on one thread and not another...
* So we just copy the current status value into the saved value
* so nothing changes on the restore
*/

2
cpu/mips_pic32_common/reset_mod.S
View File

@ -240,5 +240,5 @@ LEAF(__boot_debug_exception)
ehb
deret
1:
b 1b #Spin indefinately
b 1b #Spin indefinitely
END(__boot_debug_exception)

2
cpu/msp430_common/include/sys/cdefs.h
View File

@ -456,7 +456,7 @@ extern "C" {
*
* * These are meant to be used in places that are run `a lot'.
* It is wasteful to make predictions in code that is run
* seldomly (e.g. at subsystem initialization time) as the
* seldom (e.g. at subsystem initialization time) as the
* basic block reordering that this affects can often generate
* larger code.
*/

2
cpu/msp430_common/include/sys/features.h
View File

@ -235,7 +235,7 @@ extern "C" {
*
* In all cases above, "enabled by default" means either by defining
* _DEFAULT_SOURCE, or by not defining any of the public feature test macros.
* Defining _GNU_SOURCE makes all of the above avaliable.
* Defining _GNU_SOURCE makes all of the above available.
*/
#ifdef _ATFILE_SOURCE

2
cpu/native/socket_zep/socket_zep.c
View File

@ -214,7 +214,7 @@ static int _recv(netdev_t *netdev, void *buf, size_t len, void *info)
}
if (((sizeof(zep_v2_data_hdr_t) + zep->length) != (unsigned)size) ||
(zep->length > len) || (zep->chan != dev->netdev.chan) ||
/* TODO promiscous mode */
/* TODO promiscuous mode */
_dst_not_me(dev, payload)) {
/* TODO: check checksum */
return -1;

2
cpu/nrf51/periph/pwm.c
View File

@ -124,7 +124,7 @@ void pwm_set(pwm_t dev, uint8_t channel, uint16_t value)
assert((dev == 0) && (channel == 0));
/*
* make sure duty cycle is set at the beggining of each period
* make sure duty cycle is set at the beginning of each period
* ensure to stop the timer as soon as possible
*/
PWM_TIMER->TASKS_STOP = 1;

2
cpu/nrf52/periph/i2c.c
View File

@ -133,7 +133,7 @@ int i2c_write_regs(i2c_t dev, uint16_t addr, uint16_t reg,
}
/* the nrf52's TWI device does not support to do two consecutive transfers
* without a repeated start condition in between. So we have to put all data
* to be transfered into a temporary buffer
* to be transferred into a temporary buffer
*
* CAUTION: this might become critical when transferring large blocks of
* data as the temporary buffer is allocated on the stack... */

2
cpu/nrf52/radio/nrf802154/nrf802154.c
View File

@ -336,7 +336,7 @@ static int _recv(netdev_t *dev, void *buf, size_t len, void *info)
radio_info->lqi = (uint8_t)(hwlqi > UINT8_MAX/ED_RSSISCALE
? UINT8_MAX
: hwlqi * ED_RSSISCALE);
/* Calculate RSSI by substracting the offset from the datasheet.
/* Calculate RSSI by subtracting the offset from the datasheet.
* Intentionally using a different calculation than the one from
* figure 122 of the v1.1 product specification. This appears to
* match real world performance better */

2
cpu/nrf5x_common/radio/nrfble/nrfble.c
View File

@ -247,7 +247,7 @@ static int _nrfble_init(netdev_t *dev)
NRF_RADIO->RXADDRESSES = 0x01UL;
/* load driver specific configuration */
NRF_RADIO->MODE = CONF_MODE;
/* configure data fields and packet length whitening and endianess */
/* configure data fields and packet length whitening and endianness */
NRF_RADIO->PCNF0 = ((CONF_S1 << RADIO_PCNF0_S1LEN_Pos) |
(CONF_S0 << RADIO_PCNF0_S0LEN_Pos) |
(CONF_LEN << RADIO_PCNF0_LFLEN_Pos));

2
cpu/nrf5x_common/radio/nrfmin/nrfmin.c
View File

@ -425,7 +425,7 @@ static int nrfmin_init(netdev_t *dev)
/* and listen to logical addresses 0 and 1 */
/* workaround errata nrf52832 3.41 [143] */
NRF_RADIO->RXADDRESSES = 0x10003UL;
/* configure data fields and packet length whitening and endianess */
/* configure data fields and packet length whitening and endianness */
NRF_RADIO->PCNF0 = ((CONF_S1 << RADIO_PCNF0_S1LEN_Pos) |
(CONF_S0 << RADIO_PCNF0_S0LEN_Pos) |
(CONF_LEN << RADIO_PCNF0_LFLEN_Pos));

2
cpu/sam0_common/periph/rtc.c
View File

@ -15,7 +15,7 @@
* @brief Low-level RTC driver implementation
*
* @author Baptiste Clenet <bapclenet@gmail.com>
* @autor ported to SAML21 by FWX <FWX@dialine.fr>
* @author ported to SAML21 by FWX <FWX@dialine.fr>
* @}
*/

2
cpu/sam0_common/periph/timer.c
View File

@ -195,7 +195,7 @@ unsigned int timer_read(tim_t tim)
/* request syncronisation */
#ifdef TC_CTRLBSET_CMD_READSYNC_Val
dev(tim)->CTRLBSET.reg = TC_CTRLBSET_CMD_READSYNC;
/* work aroud a possible hardware bug where it takes some
/* work around a possible hardware bug where it takes some
cycles for the timer peripheral to set the SYNCBUSY/READSYNC bit
after writing the READSYNC bit

2
cpu/sam3/periph/cpuid.c
View File

@ -33,7 +33,7 @@
__attribute__ ((section (".ramfunc")))
void cpuid_get(void *id)
{
uint32_t cpuid[4]; /* 128 bits sam3 unique indentifier */
uint32_t cpuid[4]; /* 128 bits sam3 unique identifier */
/*
Reading SAM3 Unique Identifier process (P 19.3.3.8):

2
cpu/samd21/cpu.c
View File

@ -109,7 +109,7 @@ static void clk_init(void)
SYSCTRL_XOSC32K_STARTUP(6) |
SYSCTRL_XOSC32K_RUNSTDBY;
/* Enable with Seperate Call */
/* Enable with Separate Call */
SYSCTRL->XOSC32K.bit.ENABLE = 1;
/* reset the GCLK module so it is in a known state */

2
cpu/stm32_common/include/periph_cpu_common.h
View File

@ -663,7 +663,7 @@ void dma_init(void);
* @param[in] mode DMA mode
* @param[in] flags DMA configuration
*
* @return < 0 on error, the number of transfered bytes otherwise
* @return < 0 on error, the number of transferred bytes otherwise
*/
int dma_transfer(dma_t dma, int chan, const volatile void *src, volatile void *dst, size_t len,
dma_mode_t mode, uint8_t flags);

4
cpu/stm32_common/periph/i2c_1.c
View File

@ -170,7 +170,7 @@ int i2c_write_regs(i2c_t dev, uint16_t addr, uint16_t reg,
if (i2c->ISR & I2C_ISR_BUSY) {
return -EAGAIN;
}
/* Handle endianess of register if 16 bit */
/* Handle endianness of register if 16 bit */
if (flags & I2C_REG16) {
reg = htons(reg); /* Make sure register is in big-endian on I2C bus */
}
@ -405,7 +405,7 @@ static inline void irq_handler(i2c_t dev)
I2C_TypeDef *i2c = i2c_config[dev].dev;
unsigned state = i2c->ISR;
DEBUG("\n\n### I2C ERROR OCCURED ###\n");
DEBUG("\n\n### I2C ERROR OCCURRED ###\n");
DEBUG("status: %08x\n", state);
if (state & I2C_ISR_OVR) {
DEBUG("OVR\n");

2
cpu/stm32_common/periph/i2c_2.c
View File

@ -436,7 +436,7 @@ static inline void irq_handler(i2c_t dev)
assert(i2c != NULL);
unsigned state = i2c->SR1;
DEBUG("\n\n### I2C ERROR OCCURED ###\n");
DEBUG("\n\n### I2C ERROR OCCURRED ###\n");
DEBUG("status: %08x\n", state);
if (state & I2C_SR1_OVR) {
DEBUG("OVR\n");

2
cpu/stm32_common/periph/qdec.c
View File

@ -156,7 +156,7 @@ static int32_t _qdec_read(qdec_t qdec, uint8_t reset)
/* Restore IRQ */
irq_restore(irq_save);
/* Substract offset before return */
/* Subtract offset before return */
count -= dev(qdec)->ARR / 2;
/* Return count minus offset */

4
cpu/stm32f1/periph/rtt.c
View File

@ -91,7 +91,7 @@ void rtt_clear_overflow_cb(void)
uint32_t rtt_get_counter(void)
{
/* wait for syncronization */
/* wait for synchronization */
while (!(RTT_DEV->CRL & RTT_FLAG_RSF)) {}
return (((uint32_t)RTT_DEV->CNTH << 16 ) | (uint32_t)(RTT_DEV->CNTL));
@ -111,7 +111,7 @@ void rtt_set_counter(uint32_t counter)
uint32_t rtt_get_alarm(void)
{
/* wait for syncronization */
/* wait for synchronization */
while (!(RTT_DEV->CRL & RTT_FLAG_RSF)) {}
return (((uint32_t)RTT_DEV->ALRH << 16 ) | (uint32_t)(RTT_DEV->ALRL));

2
cpu/stm32l4/periph/adc.c
View File

@ -37,7 +37,7 @@
/* on stm32-l476rg all ADC clocks are are enabled by this bit
further clock config is possible over CKMODE[1:0] bits in ADC_CCR reg */
#define ADC_CLK_EN_MASK (RCC_AHB2ENR_ADCEN)
/* refering to Datasheet Section 6.3.18 (ADC characteristics) the minimum
/* referring to Datasheet Section 6.3.18 (ADC characteristics) the minimum
achievable sampling rate is 4.21 Msps (12 Bit resolution on slow channel)
we use that worst case for configuring the sampling time to be sure it
works on all channels.

2
dist/tools/coccinelle/README.md vendored
View File

@ -46,7 +46,7 @@ piping coccinelle's output into patch:
Specifying BRANCH, FILES and/or a specific patch file works here, too.
Beware that some of our semantic patch files might just *find* occurences of
Beware that some of our semantic patch files might just *find* occurrences of
bad code or style! Not all semantic patches output useful diffs.
## My PR has coccinelle warnings/errors!

8
dist/tools/goodfet/goodfet.bsl vendored
View File

@ -1047,7 +1047,7 @@ class BootStrapLoader(LowLevel):
sys.stderr.flush()
#send the password
self.bslTxRx(self.BSL_TXPWORD, #Command: Transmit Password
0xffe0, #Address of interupt vectors
0xffe0, #Address of interrupt vectors
0x0020, #Number of bytes
passwd, #password
wait=wait) #if wait is 1, try to sync forever
@ -1098,7 +1098,7 @@ class BootStrapLoader(LowLevel):
if DEBUG:
sys.stderr.write("Autodetect successful: %04x -> %s\n" % (dev_id, self.cpu))
else:
sys.stderr.write("Autodetect failed! Unkown ID: %04x. Trying to continue anyway.\n" % dev_id)
sys.stderr.write("Autodetect failed! Unknown ID: %04x. Trying to continue anyway.\n" % dev_id)
self.cpu = F1x #assume something and try anyway..
sys.stderr.write("Current bootstrap loader version: %x.%x (Device ID: %04x)\n" % (bslVerHi, bslVerLo, dev_id))
@ -1200,7 +1200,7 @@ class BootStrapLoader(LowLevel):
self.txPasswd(self.passwd)
#update version info
#verison only valid for the internal ones, but it also makes sure
#version only valid for the internal ones, but it also makes sure
#that the patches are not applied if the user d/ls one
self.bslVer = 0x0150
@ -1306,7 +1306,7 @@ goodfet.bsl -e -p foo.hex
sys.stderr.flush()
self.bslTxRx(self.BSL_CHANGEBAUD, #Command: change baudrate
a, l) #args are coded in adr and len
time.sleep(0.010) #recomended delay
time.sleep(0.010) #recommended delay
self.serialport.baudrate = baudrate
def actionReadBSLVersion(self):

2
dist/tools/tunslip/tunslip.c vendored
View File

@ -71,7 +71,7 @@ struct ip {
u_int16_t ip_id; /* identification */
u_int16_t ip_off; /* fragment offset field */
#define IP_RF 0x8000 /* reserved fragment flag */
#define IP_DF 0x4000 /* dont fragment flag */
#define IP_DF 0x4000 /* don't fragment flag */
#define IP_MF 0x2000 /* more fragments flag */
#define IP_OFFMASK 0x1fff /* mask for fragmenting bits */
u_int8_t ip_ttl; /* time to live */

2
doc/doxygen/riot.doxyfile
View File

@ -1670,7 +1670,7 @@ EXTRA_PACKAGES =
# following commands have a special meaning inside the header: $title,
# $datetime, $date, $doxygenversion, $projectname, $projectnumber,
# $projectbrief, $projectlogo. Doxygen will replace $title with the empy string,
# for the replacement values of the other commands the user is refered to
# for the replacement values of the other commands the user is referred to
# HTML_HEADER.
# This tag requires that the tag GENERATE_LATEX is set to YES.

6
drivers/ad7746/ad7746.c
View File

@ -51,7 +51,7 @@ static const unsigned char _vt_sr_times[] = {
*
* @return AD7746_OK on success
* @return AD7746_NODATA if no data is available
* @return AD7746_I2C on error getting a reponse
* @return AD7746_I2C on error getting a response
*/
static int _read_capacitance(ad7746_t *dev, int *value,
ad7746_cap_input_t input);
@ -67,7 +67,7 @@ static int _read_capacitance(ad7746_t *dev, int *value,
*
* @return AD7746_OK on success
* @return AD7746_NODATA if no data is available
* @return AD7746_I2C on error getting a reponse
* @return AD7746_I2C on error getting a response
*/
static int _read_voltage_temp(ad7746_t *dev, int *value, ad7746_vt_mode_t mode);
@ -83,7 +83,7 @@ static int _read_voltage_temp(ad7746_t *dev, int *value, ad7746_vt_mode_t mode);
*
* @return AD7746_OK on success
* @return AD7746_NODATA if no data is available
* @return AD7746_I2C on error getting a reponse
* @return AD7746_I2C on error getting a response
*/
static int _read_raw_ch(const ad7746_t *dev, uint8_t ch, uint32_t *raw);

4
drivers/ads101x/ads101x.c
View File

@ -133,11 +133,11 @@ int ads101x_read_raw(const ads101x_t *dev, int16_t *raw)
/* Read control register */
i2c_read_regs(DEV, ADDR, ADS101X_CONF_ADDR, &regs, 2, 0x0);
/* Tell the ADC to aquire a single-shot sample */
/* Tell the ADC to acquire a single-shot sample */
regs[0] |= ADS101X_CONF_OS_CONV;
i2c_write_regs(DEV, ADDR, ADS101X_CONF_ADDR, &regs, 2, 0x0);
/* Wait for the sample to be aquired */
/* Wait for the sample to be acquired */
xtimer_usleep(ADS101X_READ_DELAY);
/* Read the sample */

2
drivers/bmx055/bmx055.c
View File

@ -138,7 +138,7 @@ int bmx055_init(bmx055_t *dev, const bmx055_params_t *params)
/* Init Gyroscope
*
* The prefered way to bring the module to normal mode is using softreset.
* The preferred way to bring the module to normal mode is using softreset.
* However, a softreset brings the module into an unknown state and
* deadlocks it. Hence it is not the way to go and normal mode is entered
* by writing into power mode control register.

4
drivers/ccs811/ccs811.c
View File

@ -485,7 +485,7 @@ static int _reg_read(const ccs811_t *dev, uint8_t reg, uint8_t *data, uint32_t l
int res = CCS811_OK;
if (i2c_acquire(dev->params.i2c_dev) != CCS811_OK) {
DEBUG_DEV("could not aquire I2C bus", dev);
DEBUG_DEV("could not acquire I2C bus", dev);
return -CCS811_ERROR_I2C;
}
@ -546,7 +546,7 @@ static int _reg_write(const ccs811_t *dev, uint8_t reg, uint8_t *data, uint32_t
}
if (i2c_acquire(dev->params.i2c_dev)) {
DEBUG_DEV("could not aquire I2C bus", dev);
DEBUG_DEV("could not acquire I2C bus", dev);
return -CCS811_ERROR_I2C;
}

2
drivers/ccs811/doc.txt
View File

@ -55,7 +55,7 @@ to get CCS811 working.
### <a name="supported"> Supported Features </a> &nbsp;&nbsp; [[TOC](#toc)]
@note There are two driver module versions, the `ccs811` module
wich provides only basic functionality and the `ccs811_full`
which provides only basic functionality and the `ccs811_full`
module with additional functionality.
The `ccs811_full` module includes the `ccs811` module

2
drivers/ccs811/include/ccs811_regs.h
View File

@ -52,7 +52,7 @@ extern "C" {
* @name Status register bits (#CCS811_REG_STATUS)
* @{
*/
#define CCS811_STATUS_ERROR (0x01) /**< error occured, details in CCS811_REG_ERROR */
#define CCS811_STATUS_ERROR (0x01) /**< error occurred, details in CCS811_REG_ERROR */
#define CCS811_STATUS_DATA_RDY (0x08) /**< new data sample available in ALG_RESULT_DATA */
#define CCS811_STATUS_APP_VALID (0x10) /**< valid application firmware loaded */
#define CCS811_STATUS_FW_MODE (0x80) /**< firmware is in application mode */

2
drivers/dynamixel/include/dynamixel_reader.h
View File

@ -123,7 +123,7 @@ static inline uint16_t dynamixel_reader_get_crc(const dynamixel_reader_t *reader
*
* @param[in] reader the packet reader
*
* @return the addess of the begining of the payload
* @return the addess of the beginning of the payload
*/
static inline const uint8_t *dynamixel_reader_status_get_payload(const dynamixel_reader_t *reader)
{

2
drivers/dynamixel/include/dynamixel_writer.h
View File

@ -52,7 +52,7 @@ void dynamixel_writer_init(dynamixel_writer_t *writer, uint8_t *buffer, size_t l
*
* @param[out] writer the packet writer
*
* @return the begining address of the buffer
* @return the beginning address of the buffer
*/
const uint8_t *dynamixel_writer_get_data(const dynamixel_writer_t *writer);

6
drivers/enc28j60/enc28j60.c
View File

@ -250,7 +250,7 @@ static void mac_set(enc28j60_t *dev, uint8_t *mac)
static void on_int(void *arg)
{
/* disable gobal interupt enable bit to avoid loosing interupts */
/* disable gobal interrupt enable bit to avoid losing interupts */
cmd_bfc((enc28j60_t *)arg, REG_EIE, -1, EIE_INTIE);
netdev_t *netdev = (netdev_t *)arg;
@ -331,7 +331,7 @@ static int nd_recv(netdev_t *netdev, void *buf, size_t max_len, void *info)
cmd_w_addr(dev, ADDR_READ_PTR, ERXRDPT_TO_NEXT(rx_rd_ptr));
/* read packet header */
cmd_rbm(dev, head, 6);
/* TODO: care for endianess */
/* TODO: care for endianness */
next = (uint16_t)((head[1] << 8) | head[0]);
size = (uint16_t)((head[3] << 8) | head[2]) - 4; /* discard CRC */
@ -493,7 +493,7 @@ static void nd_isr(netdev_t *netdev)
}
eir = cmd_rcr(dev, REG_EIR, -1);
}
/* enable gobal interupt enable bit again */
/* enable gobal interrupt enable bit again */
cmd_bfs(dev, REG_EIE, -1, EIE_INTIE);
}

2
drivers/encx24j600/include/encx24j600_internal.h
View File

@ -31,7 +31,7 @@ typedef struct __attribute__((packed)) encx24j600_frame_hdr {
uint16_t rx_next_ptr; /**< ptr to next packet whithin devices memory */
/* Receive Status Vector */
uint16_t frame_len; /**< lenght of ethernet frame including 4 bytes
uint16_t frame_len; /**< length of ethernet frame including 4 bytes
checksum */
uint32_t flags; /**< random flag field just mentioned for the
sake of documentation completeness */

6
drivers/feetech/include/feetech_reader.h
View File

@ -157,7 +157,7 @@ static inline uint8_t feetech_reader_get_instr(const feetech_reader_t *reader)
*
* @param[in] reader the packet reader
*
* @return the addess of the begining of the payload
* @return the addess of the beginning of the payload
*/
static inline const uint8_t *feetech_reader_response_get_payload(const feetech_reader_t *reader)
{
@ -181,7 +181,7 @@ static inline size_t feetech_reader_response_get_payload_size(const feetech_read
*
* @param[in] reader the packet reader
*
* @return the begining addess of the payload
* @return the beginning addess of the payload
*/
static inline const uint8_t *feetech_reader_write_get_payload(const feetech_reader_t *reader)
{
@ -285,7 +285,7 @@ uint8_t feetech_reader_sync_write_item_get_id(const feetech_reader_t *reader, ui
* @param[in] reader the packet reader
* @param[in] index the item index
*
* @return the begining addess of the payload
* @return the beginning addess of the payload
*/
const uint8_t *feetech_reader_sync_write_item_get_payload(const feetech_reader_t *reader, uint8_t index);

2
drivers/feetech/include/feetech_writer.h
View File

@ -53,7 +53,7 @@ void feetech_writer_init(feetech_writer_t *writer, uint8_t *buffer, size_t buffe
*
* @param[out] writer the packet writer
*
* @return the begining address of the buffer
* @return the beginning address of the buffer
*/
const uint8_t *feetech_writer_get_data(const feetech_writer_t *writer);

4
drivers/include/ad7746.h
View File

@ -179,7 +179,7 @@ int ad7746_init(ad7746_t *dev, const ad7746_params_t *params);
* away. The time until new data is available will depend on the
* @ref ad7746_params_t::cap_sample_rate "sample rate" of the channel.
*
* @param[in, out] dev device decriptor
* @param[in, out] dev device descriptor
* @param[out] value read value in fF
*
* @return AD7746_OK on success
@ -197,7 +197,7 @@ int ad7746_read_capacitance_1(ad7746_t *dev, int *value);
* away. The time until new data is available will depend on the
* @ref ad7746_params_t::cap_sample_rate "sample rate" of the channel.
*
* @param[in, out] dev device decriptor
* @param[in, out] dev device descriptor
* @param[out] value read value in fF
*
* @return AD7746_OK on success

2
drivers/include/at30tse75x.h
View File

@ -118,7 +118,7 @@ typedef enum {
/**
* @brief Operation mode
*
* The device can run in continous or one-shot mode. While in one-shot mode it
* The device can run in continuous or one-shot mode. While in one-shot mode it
* is effectively shutdown and only wakes up to perform a single measurement.
* When in comparator or interrupt mode, the device samples contiously the
* temperature and sets the ALERT pin according to the chosen mode.

2
drivers/include/bmp180.h
View File

@ -92,7 +92,7 @@ enum {
*
* @return BMP180_OK on success
* @return -BMP180_ERR_NODEV if not a BMP180 at given address
* @return -BMP180_ERR_NOCAL if an error occured when reading calibration values
* @return -BMP180_ERR_NOCAL if an error occurred when reading calibration values
*/
int bmp180_init(bmp180_t *dev, const bmp180_params_t *params);

2
drivers/include/diskio.h
View File

@ -68,7 +68,7 @@ typedef enum {
} diskio_sta_t;
/**
* @name Command code for disk_ioctrl fucntion
* @name Command code for disk_ioctrl function
* @{
*/

2
drivers/include/ds18.h
View File

@ -107,7 +107,7 @@ int ds18_read(const ds18_t *dev, int16_t *temperature);
* @brief convenience fuction for triggering a conversion and reading the
* value
*
* @note This function will block for the convertion time. The current
* @note This function will block for the conversion time. The current
* implementation of the driver uses 12-bit resolution, so this time is 750 ms.
*
* @param[in] dev device descriptor

8
drivers/include/ds75lx.h
View File

@ -71,7 +71,7 @@ enum {
* @param[in] params Initialization parameters
*
* @return DS75LX_OK on success
* @return -DS75LX_ERR_I2C if an error occured when reading/writing
* @return -DS75LX_ERR_I2C if an error occurred when reading/writing
*/
int ds75lx_init(ds75lx_t *dev, const ds75lx_params_t *params);
@ -82,7 +82,7 @@ int ds75lx_init(ds75lx_t *dev, const ds75lx_params_t *params);
* @param[out] temperature Temperature in c°C
*
* @return DS75LX_OK on success
* @return -DS75LX_ERR_I2C if an error occured when reading/writing
* @return -DS75LX_ERR_I2C if an error occurred when reading/writing
*/
int ds75lx_read_temperature(const ds75lx_t *dev, int16_t *temperature);
@ -92,7 +92,7 @@ int ds75lx_read_temperature(const ds75lx_t *dev, int16_t *temperature);
* @param[in] dev Device descriptor of DS75LX device
*
* @return DS75LX_OK on success
* @return -DS75LX_ERR_I2C if an error occured when reading/writing
* @return -DS75LX_ERR_I2C if an error occurred when reading/writing
*/
int ds75lx_wakeup(const ds75lx_t *dev);
@ -102,7 +102,7 @@ int ds75lx_wakeup(const ds75lx_t *dev);
* @param[in] dev Device descriptor of DS75LX device
*
* @return DS75LX_OK on success
* @return -DS75LX_ERR_I2C if an error occured when reading/writing
* @return -DS75LX_ERR_I2C if an error occurred when reading/writing
*/
int ds75lx_shutdown(const ds75lx_t *dev);

8
drivers/include/dsp0401.h
View File

@ -68,10 +68,10 @@ typedef struct {
* @param[in] params Device parameters to use
*
* @return DSP0401_OK if everything is good
* @return -DSP0401_ERR_CLK_GPIO if an error occured during CLK GPIO initialization
* @return -DSP0401_ERR_SDI_GPIO if an error occured during SDI GPIO initialization
* @return -DSP0401_ERR_LAT_GPIO if an error occured during LAT GPIO initialization
* @return -DSP0401_ERR_PWM if an error occured during PWM initialization
* @return -DSP0401_ERR_CLK_GPIO if an error occurred during CLK GPIO initialization
* @return -DSP0401_ERR_SDI_GPIO if an error occurred during SDI GPIO initialization
* @return -DSP0401_ERR_LAT_GPIO if an error occurred during LAT GPIO initialization
* @return -DSP0401_ERR_PWM if an error occurred during PWM initialization
*/
int dsp0401_init(dsp0401_t *dev, const dsp0401_params_t *params);

2
drivers/include/io1_xplained.h
View File

@ -32,7 +32,7 @@
* @{
*
* @file
* @brief Device driver interface for the Atmel IO1 Xplained extention.
* @brief Device driver interface for the Atmel IO1 Xplained extension.
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/

16
drivers/include/mtd.h
View File

@ -168,11 +168,11 @@ int mtd_init(mtd_dev_t *mtd);
* @param[in] count the number of bytes to read
*
* @return the number of byte actually read
* @return < 0 if an error occured
* @return < 0 if an error occurred
* @return -ENODEV if @p mtd is not a valid device
* @return -ENOTSUP if operation is not supported on @p mtd
* @return -EOVERFLOW if @p addr or @p count are not valid, i.e. outside memory
* @return -EIO if I/O error occured
* @return -EIO if I/O error occurred
*/
int mtd_read(mtd_dev_t *mtd, void *dest, uint32_t addr, uint32_t count);
@ -189,12 +189,12 @@ int mtd_read(mtd_dev_t *mtd, void *dest, uint32_t addr, uint32_t count);
* @param[in] count the number of bytes to write
*
* @return the number of byte actually written
* @return < 0 if an error occured
* @return < 0 if an error occurred
* @return -ENODEV if @p mtd is not a valid device
* @return -ENOTSUP if operation is not supported on @p mtd
* @return -EOVERFLOW if @p addr or @p count are not valid, i.e. outside memory,
* or overlapping two pages
* @return -EIO if I/O error occured
* @return -EIO if I/O error occurred
* @return -EINVAL if parameters are invalid (invalid alignment for instance)
*/
int mtd_write(mtd_dev_t *mtd, const void *src, uint32_t addr, uint32_t count);
@ -209,11 +209,11 @@ int mtd_write(mtd_dev_t *mtd, const void *src, uint32_t addr, uint32_t count);
* @param[in] count the number of bytes to erase
*
* @return 0 if erase successful
* @return < 0 if an error occured
* @return < 0 if an error occurred
* @return -ENODEV if @p mtd is not a valid device
* @return -ENOTSUP if operation is not supported on @p mtd
* @return -EOVERFLOW if @p addr or @p count are not valid, i.e. outside memory
* @return -EIO if I/O error occured
* @return -EIO if I/O error occurred
*/
int mtd_erase(mtd_dev_t *mtd, uint32_t addr, uint32_t count);
@ -224,10 +224,10 @@ int mtd_erase(mtd_dev_t *mtd, uint32_t addr, uint32_t count);
* @param[in] power the power mode to set
*
* @return 0 if power mode successfully set
* @return < 0 if an error occured
* @return < 0 if an error occurred
* @return -ENODEV if @p mtd is not a valid device
* @return -ENOTSUP if operation or @p power state is not supported on @p mtd
* @return -EIO if I/O error occured
* @return -EIO if I/O error occurred
*/
int mtd_power(mtd_dev_t *mtd, enum mtd_power_state power);

8
drivers/include/net/netdev/ieee802154.h
View File

@ -42,7 +42,7 @@ extern "C" {
#define NETDEV_IEEE802154_SEND_MASK (0x0028) /**< flags to take for send packets */
#define NETDEV_IEEE802154_RAW (0x0002) /**< pass raw frame to upper layer */
/**
* @brief use long source addres (set) or short source address (unset)
* @brief use long source address (set) or short source address (unset)
*/
#define NETDEV_IEEE802154_SRC_MODE_LONG (0x0004)
/**
@ -180,16 +180,16 @@ int netdev_ieee802154_set(netdev_ieee802154_t *dev, netopt_t opt, const void *va
size_t value_len);
/**
* @brief This funtion compares destination address and pan id with addresses
* @brief This function compares destination address and pan id with addresses
* and pan id of the device
*
* this funciton is meant top be used by drivers that do not support address
* this function is meant top be used by drivers that do not support address
* filtering in hw
*
* @param[in] dev network device descriptor
* @param[in] mhr mac header
*
* @return 0 successfull if packet is for the device
* @return 0 successful if packet is for the device
* @return 1 fails if packet is not for the device or pan
*/
int netdev_ieee802154_dst_filter(netdev_ieee802154_t *dev, const uint8_t *mhr);

4
drivers/include/nrf24l01p.h
View File

@ -199,7 +199,7 @@ void nrf24l01p_transmit(const nrf24l01p_t *dev);
* @param[in] answer Buffer to receive bytes to.
* @param[in] size Number of bytes to transfer. For nrf24l01+ in general 32.
*
* @return Number of bytes that were transfered.
* @return Number of bytes that were transferred.
* @return -1 on error.
*/
int nrf24l01p_read_payload(const nrf24l01p_t *dev, char *answer, unsigned int size);
@ -277,7 +277,7 @@ void nrf24l01p_stop(const nrf24l01p_t *dev);
* @param[in] data Buffer to preload.
* @param[in] size Number of bytes in buffer. For nrf24l01+ e.g. 32
*
* @return Number of bytes that were transfered.
* @return Number of bytes that were transferred.
* @return -1 on error.
*/
int nrf24l01p_preload(const nrf24l01p_t *dev, char *data, unsigned int size);

2
drivers/include/periph/gpio_util.h
View File

@ -28,7 +28,7 @@ extern "C" {
/**
* @brief Shift in a byte from data_pin, create clock pulses on clock_pin
*
* This funtion has the same functionality as the Arduino shiftIn() in Advanced
* This function has the same functionality as the Arduino shiftIn() in Advanced
* I/O.
*
* @param[in] data_pin Pin to read data from

2
drivers/include/periph/hwrng.h
View File

@ -52,7 +52,7 @@ extern "C" {
*
* On some platforms, the random number generator needs some global
* initialization before it can be used. This should happen in this function
* if it would impose too much overhead to do this everytime the hwrng_read
* if it would impose too much overhead to do this every time the hwrng_read
* function is called. The device should however be put into power-off mode
* after initialization and will be powered on and of when hwrng_read is called.
*/

8
drivers/include/rn2xx3.h
View File

@ -300,7 +300,7 @@ int rn2xx3_wait_response(rn2xx3_t *dev);
* @return RN2XX3_REPLY_TX_MAC_ERR when MAC transmission failed
* @return RN2XX3_REPLY_TX_MAC_RX when received downlink data from server
* @return RN2XX3_REPLY_TX_INVALID_DATA_LEN when Application payload is too large
* @return RN2XX3_REPLY_JOIN_ACCEPTED when the join procedure succeded
* @return RN2XX3_REPLY_JOIN_ACCEPTED when the join procedure succeeded
* @return RN2XX3_REPLY_JOIN_DENIED when the join procedure failed
* @return RN2XX3_REPLY_OTHER when an unknown reply is received
*/
@ -317,7 +317,7 @@ int rn2xx3_wait_reply(rn2xx3_t *dev, uint8_t timeout);
* @return RN2XX3_ERR_NO_FREE_CH if channels are busy
* @return RN2XX3_ERR_SILENT if device is in Silent state
* @return RN2XX3_ERR_BUSY if MAC layer is in idle state
* @return RN2XX3_ERR_MAC_PAUSED if MAC layed is paused
* @return RN2XX3_ERR_MAC_PAUSED if MAC laid is paused
* @return RN2XX3_REPLY_TX_INVALID_DATA_LEN if payload is too large
* @return RN2XX3_REPLY_TX_MAC_ERR when MAC transmission failed
* @return RN2XX3_REPLY_TX_MAC_RX when received downlink data from server
@ -335,8 +335,8 @@ int rn2xx3_mac_tx(rn2xx3_t *dev, uint8_t *payload, uint8_t payload_len);
* @return RN2XX3_ERR_NO_FREE_CH if channels are busy
* @return RN2XX3_ERR_SILENT if device is in Silent state
* @return RN2XX3_ERR_BUSY if MAC layer is in idle state
* @return RN2XX3_ERR_MAC_PAUSED if MAC layed is paused
* @return RN2XX3_REPLY_JOIN_ACCEPTED when the join procedure succeded
* @return RN2XX3_ERR_MAC_PAUSED if MAC laid is paused
* @return RN2XX3_REPLY_JOIN_ACCEPTED when the join procedure succeeded
* @return RN2XX3_REPLY_JOIN_DENIED when the join procedure failed
*/
int rn2xx3_mac_join_network(rn2xx3_t *dev, loramac_join_mode_t mode);

16
drivers/include/sdcard_spi.h
View File

@ -187,7 +187,7 @@ typedef struct {
typedef struct {
sdcard_spi_params_t params; /**< parameters for pin and spi config */
spi_clk_t spi_clk; /**< active SPI clock speed */
bool use_block_addr; /**< true if block adressing (vs. byte adressing) is used */
bool use_block_addr; /**< true if block addressing (vs. byte addressing) is used */
bool init_done; /**< set to true once the init procedure completed successfully */
sd_version_t card_type; /**< version of SD-card */
int csd_structure; /**< version of the CSD register structure */
@ -206,7 +206,7 @@ typedef struct {
* @param[in] params parameters for this device (pins and spi device are initialized by this driver)
*
* @return 0 if the card could be initialized successfully
* @return false if an error occured while initializing the card
* @return false if an error occurred while initializing the card
*/
int sdcard_spi_init(sdcard_spi_t *card, const sdcard_spi_params_t *params);
@ -214,10 +214,10 @@ int sdcard_spi_init(sdcard_spi_t *card, const sdcard_spi_params_t *params);
* @brief Reads data blocks (usually multiples of 512 Bytes) from card to buffer.
*
* @param[in] card Initialized sd-card struct
* @param[in] blockaddr Start adress to read from. Independet of the actual adressing scheme of
* the used card the adress needs to be given as block address
* @param[in] blockaddr Start address to read from. Independent of the actual addressing scheme of
* the used card the address needs to be given as block address
* (e.g. 0, 1, 2... NOT: 0, 512... ). The driver takes care of mapping to
* byte adressing if needed.
* byte addressing if needed.
* @param[out] data Buffer to store the read data in. The user is responsible for providing a
* suitable buffer size.
* @param[in] blocksize Size of data blocks. For now only 512 byte blocks are supported because
@ -237,10 +237,10 @@ int sdcard_spi_read_blocks(sdcard_spi_t *card, int blockaddr, uint8_t *data, int
* @brief Writes data blocks (usually multiples of 512 Bytes) from buffer to card.
*
* @param[in] card Initialized sd-card struct
* @param[in] blockaddr Start adress to read from. Independet of the actual adressing scheme of
* the used card the adress needs to be given as block address
* @param[in] blockaddr Start address to read from. Independent of the actual addressing scheme of
* the used card the address needs to be given as block address
* (e.g. 0, 1, 2... NOT: 0, 512... ). The driver takes care of mapping to
* byte adressing if needed.
* byte addressing if needed.
* @param[out] data Buffer that contains the data to be sent.
* @param[in] blocksize Size of data blocks. For now only 512 byte blocks are supported because
* only older (SDSC) cards support variable blocksizes anyway.

20
drivers/include/sds011.h
View File

@ -141,7 +141,7 @@ void sds011_power_off(const sds011_t *dev);
* @return SDS011_OK on success
* @return SDS011_INVALID_RESPONSE when response doesn't match the request
* @return SDS011_INVALID_CHKSUM when response checksum is invalid
* @return SDS011_ERROR when other error occured
* @return SDS011_ERROR when other error occurred
*
* @pre @p dev != NULL
* @pre @p data != NULL
@ -161,7 +161,7 @@ int sds011_read(sds011_t *dev, sds011_data_t *data);
* @param[in] ctx context pointer that will be handed to the callback
*
* @return SDS011_OK on success
* @return SDS011_ERROR when error occured
* @return SDS011_ERROR when error occurred
*
* @pre @p dev != NULL
*/
@ -177,7 +177,7 @@ int sds011_register_callback(sds011_t *dev, sds011_callback_t cb, void *ctx);
* @return SDS011_OK on success
* @return SDS011_INVALID_RESPONSE when response doesn't match the request
* @return SDS011_INVALID_CHKSUM when response checksum is invalid
* @return SDS011_ERROR when other error occured
* @return SDS011_ERROR when other error occurred
*
* @pre @p dev != NULL
*/
@ -196,7 +196,7 @@ int sds011_get_reporting_mode(sds011_t *dev, sds011_reporting_mode_t *mode);
* @return SDS011_OK on success
* @return SDS011_INVALID_RESPONSE when response doesn't match the request
* @return SDS011_INVALID_CHKSUM when response checksum is invalid
* @return SDS011_ERROR when other error occured
* @return SDS011_ERROR when other error occurred
*
* @pre @p dev != NULL
*/
@ -212,7 +212,7 @@ int sds011_set_reporting_mode(sds011_t *dev, sds011_reporting_mode_t mode);
* @return SDS011_OK on success
* @return SDS011_INVALID_RESPONSE when response doesn't match the request
* @return SDS011_INVALID_CHKSUM when response checksum is invalid
* @return SDS011_ERROR when other error occured
* @return SDS011_ERROR when other error occurred
*
* @pre @p dev != NULL
*/
@ -228,7 +228,7 @@ int sds011_get_working_mode(sds011_t *dev, sds011_working_mode_t *mode);
* @return SDS011_OK on success
* @return SDS011_INVALID_RESPONSE when response doesn't match the request
* @return SDS011_INVALID_CHKSUM when response checksum is invalid
* @return SDS011_ERROR when other error occured
* @return SDS011_ERROR when other error occurred
*
* @pre @p dev != NULL
*/
@ -243,7 +243,7 @@ int sds011_set_working_mode(sds011_t *dev, sds011_working_mode_t mode);
* @return SDS011_OK on success
* @return SDS011_INVALID_RESPONSE when response doesn't match the request
* @return SDS011_INVALID_CHKSUM when response checksum is invalid
* @return SDS011_ERROR when other error occured
* @return SDS011_ERROR when other error occurred
*
* @pre @p dev != NULL
*/
@ -264,7 +264,7 @@ int sds011_get_working_period(sds011_t *dev, uint8_t *minutes);
* @return SDS011_OK on success
* @return SDS011_INVALID_RESPONSE when response doesn't match the request
* @return SDS011_INVALID_CHKSUM when response checksum is invalid
* @return SDS011_ERROR when other error occured
* @return SDS011_ERROR when other error occurred
*
* @pre @p dev != NULL
*/
@ -281,7 +281,7 @@ int sds011_set_working_period(sds011_t *dev, uint8_t minutes);
* @return SDS011_OK on success
* @return SDS011_INVALID_RESPONSE when response doesn't match the request
* @return SDS011_INVALID_CHKSUM when response checksum is invalid
* @return SDS011_ERROR when other error occured
* @return SDS011_ERROR when other error occurred
*
* @pre @p dev != NULL
* @pre @p year != NULL
@ -303,7 +303,7 @@ int sds011_get_fw_version(sds011_t *dev, uint8_t *year, uint8_t *mon, uint8_t *d
* @return SDS011_OK on success
* @return SDS011_INVALID_RESPONSE when response doesn't match the request
* @return SDS011_INVALID_CHKSUM when response checksum is invalid
* @return SDS011_ERROR when other error occured
* @return SDS011_ERROR when other error occurred
*
* @pre @p dev != NULL
*/

2
drivers/include/si70xx.h
View File

@ -36,7 +36,7 @@ extern "C" {
enum {
SI70XX_OK, /**< All OK */
SI70XX_ERR_NODEV, /**< No valid device found on I2C bus */
SI70XX_ERR_I2C, /**< An error occured when reading/writing on I2C bus */
SI70XX_ERR_I2C, /**< An error occurred when reading/writing on I2C bus */
};
/**

6
drivers/kw2xrf/include/kw2xrf_getset.h
View File

@ -122,10 +122,10 @@ uint16_t kw2xrf_get_addr_short(kw2xrf_t *dev);
uint64_t kw2xrf_get_addr_long(kw2xrf_t *dev);
/**
* @brief Get CCA threshhold of a given device
* @brief Get CCA threshold of a given device
*
* @param[in] dev kw2xrf device descriptor
* @return current CCA threshhold
* @return current CCA threshold
*/
int8_t kw2xrf_get_cca_threshold(kw2xrf_t *dev);
@ -171,7 +171,7 @@ int16_t kw2xrf_get_rssi(uint32_t value);
netopt_state_t kw2xrf_get_status(kw2xrf_t *dev);
/**
* @brief Enable continous CCA
* @brief Enable continuous CCA
*
* @param[in] dev kw2xrf device descriptor
*

2
drivers/lis3mdl/include/lis3mdl-internal.h
View File

@ -40,7 +40,7 @@ extern "C" {
/** @} */
/**
* @name LIS3DML controll register
* @name LIS3DML control register
* @{
*/
#define LIS3MDL_CTRL_REG1 (0x20)

2
drivers/mrf24j40/include/mrf24j40_internal.h
View File

@ -31,7 +31,7 @@ extern "C" {
/**
* @brief initialization as decribed in datasheet
* @brief initialization as described in datasheet
*
* @param[in] dev device to initialize
*

4
drivers/mrf24j40/mrf24j40_netdev.c
View File

@ -542,7 +542,7 @@ static void _isr(netdev_t *netdev)
/* update pending bits */
mrf24j40_update_tasks(dev);
DEBUG("[mrf24j40] INTERRUPT (pending: %x),\n", dev->pending);
/* Transmit interrupt occured */
/* Transmit interrupt occurred */
if (dev->pending & MRF24J40_TASK_TX_READY) {
dev->pending &= ~(MRF24J40_TASK_TX_READY);
DEBUG("[mrf24j40] EVT - TX_END\n");
@ -569,7 +569,7 @@ static void _isr(netdev_t *netdev)
}
#endif
}
/* Receive interrupt occured */
/* Receive interrupt occurred */
if (dev->pending & MRF24J40_TASK_RX_READY) {
DEBUG("[mrf24j40] EVT - RX_END\n");
if ((dev->netdev.flags & MRF24J40_OPT_TELL_RX_END)) {

4
drivers/nrf24l01p/nrf24l01p.c
View File

@ -106,7 +106,7 @@ int nrf24l01p_init(nrf24l01p_t *dev, spi_t spi, gpio_t ce, gpio_t cs, gpio_t irq
return status;
}
/* Setup adress width */
/* Setup address width */
status = nrf24l01p_set_address_width(dev, NRF24L01P_AW_5BYTE);
if (status < 0) {
@ -148,7 +148,7 @@ int nrf24l01p_init(nrf24l01p_t *dev, spi_t spi, gpio_t ce, gpio_t cs, gpio_t irq
return status;
}
/* Set RX Adress */
/* Set RX Address */
status = nrf24l01p_set_rx_address(dev, NRF24L01P_PIPE0, INITIAL_RX_ADDRESS, INITIAL_ADDRESS_WIDTH);
if (status < 0) {

4
drivers/periph_common/i2c.c
View File

@ -44,7 +44,7 @@ int i2c_read_regs(i2c_t dev, uint16_t addr, uint16_t reg,
return -EOPNOTSUPP;
}
/* Handle endianess of register if 16 bit */
/* Handle endianness of register if 16 bit */
if (flags & I2C_REG16) {
reg_end = htons(reg); /* Make sure register is in big-endian on I2C bus */
}
@ -88,7 +88,7 @@ int i2c_write_regs(i2c_t dev, uint16_t addr, uint16_t reg,
return -EOPNOTSUPP;
}
/* Handle endianess of register if 16 bit */
/* Handle endianness of register if 16 bit */
if (flags & I2C_REG16) {
reg_end = htons(reg); /* Make sure register is in big-endian on I2C bus */
}

8
drivers/sdcard_spi/include/sdcard_spi_internal.h
View File

@ -179,10 +179,10 @@ typedef enum {
* (for CMDX this parameter is simply the integer value X).
* @param[in] argument The argument for the given cmd. As described by "7.3.1.1 Command Format".
* This argument is transmitted byte wise with most significant byte first.
* @param[in] max_retry Specifies how often the command should be retried if an error occures.
* @param[in] max_retry Specifies how often the command should be retried if an error occurs.
* Use 0 to try only once, -1 to try forever, or n to retry n times.
*
* @return R1 response of the command if no (low-level) communication error occured
* @return R1 response of the command if no (low-level) communication error occurred
* @return SD_INVALID_R1_RESPONSE if either waiting for the card to enter
* not-busy-state timed out or spi communication failed
*/
@ -197,10 +197,10 @@ uint8_t sdcard_spi_send_cmd(sdcard_spi_t *card, uint8_t sd_cmd_idx, uint32_t arg
* (for ACMDX this parameter is simply the integer value X).
* @param[in] argument The argument for the given cmd. As described by "7.3.1.1 Command Format".
* This argument is transmitted byte wise with most significant byte first.
* @param[in] max_retry Specifies how often the command should be retried if an error occures.
* @param[in] max_retry Specifies how often the command should be retried if an error occurs.
* Use 0 to try only once, -1 to try forever, or n to retry n times.
*
* @return R1 response of the command if no (low-level) communication error occured
* @return R1 response of the command if no (low-level) communication error occurred
* @return SD_INVALID_R1_RESPONSE if either waiting for the card to enter
* not-busy-state timed out or spi communication failed
*/

6
drivers/sdcard_spi/sdcard_spi.c
View File

@ -254,13 +254,13 @@ static sd_init_fsm_state_t _init_sd_fsm_step(sdcard_spi_t *card, sd_init_fsm_sta
DEBUG("OCR: POWER UP ROUTINE FINISHED\n");
/* if sd card is sdhc */
if ((ocr & OCR_CCS) != 0) {
DEBUG("OCR: CARD TYPE IS SDHC (SD_V2 with block adressing)\n");
DEBUG("OCR: CARD TYPE IS SDHC (SD_V2 with block addressing)\n");
card->use_block_addr = true;
_unselect_card_spi(card);
return SD_INIT_READ_CID;
}
DEBUG("OCR: CARD TYPE IS SDSC (SD_v2 with byte adressing)\n");
DEBUG("OCR: CARD TYPE IS SDSC (SD_v2 with byte addressing)\n");
card->use_block_addr = false;
return SD_INIT_SEND_CMD16;
}
@ -284,7 +284,7 @@ static sd_init_fsm_state_t _init_sd_fsm_step(sdcard_spi_t *card, sd_init_fsm_sta
DEBUG("SD_INIT_SEND_CMD16\n");
uint8_t r1_16 = sdcard_spi_send_cmd(card, SD_CMD_16, SD_HC_BLOCK_SIZE, INIT_CMD_RETRY_CNT);
if (R1_VALID(r1_16) && !R1_ERROR(r1_16)) {
DEBUG("CARD TYPE IS SDSC (SD_V1 with byte adressing)\n");
DEBUG("CARD TYPE IS SDSC (SD_V1 with byte addressing)\n");
_unselect_card_spi(card);
return SD_INIT_READ_CID;
}

4
drivers/sht3x/sht3x.c
View File

@ -288,7 +288,7 @@ static int _send_command(sht3x_dev_t* dev, uint16_t cmd)
DEBUG_DEV("send command 0x%02x%02x", dev, data[0], data[1]);
if (i2c_acquire(dev->i2c_dev) != 0) {
DEBUG_DEV ("could not aquire I2C bus", dev);
DEBUG_DEV ("could not acquire I2C bus", dev);
return -SHT3X_ERROR_I2C;
}
@ -310,7 +310,7 @@ static int _read_data(sht3x_dev_t* dev, uint8_t *data, uint8_t len)
int res = SHT3X_OK;
if (i2c_acquire(dev->i2c_dev) != 0) {
DEBUG_DEV ("could not aquire I2C bus", dev);
DEBUG_DEV ("could not acquire I2C bus", dev);
return -SHT3X_ERROR_I2C;
}

2
drivers/sx127x/sx127x_getset.c
View File

@ -159,7 +159,7 @@ uint32_t sx127x_get_time_on_air(const sx127x_t *dev, uint8_t pkt_len)
bw = 500e3;
break;
default:
DEBUG("Invalid bandwith: %d\n", dev->settings.lora.bandwidth);
DEBUG("Invalid bandwidth: %d\n", dev->settings.lora.bandwidth);
break;
}

2
drivers/uart_half_duplex/include/uart_half_duplex.h
View File

@ -90,7 +90,7 @@ enum {
* @return UART_HALF_DUPLEX_OK if everything is in order
* @return UART_HALF_DUPLEX_NODEV if invalid UART device was given
* @return UART_HALF_DUPLEX_NOBAUD if given baudrate is not applicable
* @return UART_HALF_DUPLEX_INTERR if an other internal error occured
* @return UART_HALF_DUPLEX_INTERR if an other internal error occurred
* @return UART_HALF_DUPLEX_NOMODE if the given mode is not applicable
* @return UART_HALF_DUPLEX_NOBUFF if an invalid buffer was given
*/

2
examples/emcute_mqttsn/README.md
View File

@ -2,7 +2,7 @@
This application demonstrates the usage of the emCute (MQTT-SN) module in RIOT.
## Setup
For using this example, two prerequisites have to be fullfilled:
For using this example, two prerequisites have to be fulfilled:
1. You need a running MQTT broker that supports MQTT-SN or a running MQTT-SN
gateway that is connected to a running MQTT broker

2
examples/gnrc_tftp/tftp_client.c
View File

@ -105,7 +105,7 @@ static int _tftp_client_data_cb(uint32_t offset, void *data, size_t data_len)
static void _tftp_client_stop_cb(tftp_event_t event, const char *msg)
{
/* decode the stop event received */
const char *cause = "UNKOWN";
const char *cause = "UNKNOWN";
if (event == TFTP_SUCCESS) {
cause = "SUCCESS";

2
examples/gnrc_tftp/tftp_server.c
View File

@ -112,7 +112,7 @@ static int _tftp_server_data_cb(uint32_t offset, void *data, size_t data_len)
static void _tftp_server_stop_cb(tftp_event_t event, const char *msg)
{
/* decode the stop event received */
const char *cause = "UNKOWN";
const char *cause = "UNKNOWN";
if (event == TFTP_SUCCESS) {
cause = "SUCCESS";

2
makefiles/buildtests.inc.mk
View File

@ -23,7 +23,7 @@ buildtest:
$${RESULT}
# Define 'buildtest-indocker' completely executed inside the container.
# It prevents starting one container per compilation wich is slower but it
# It prevents starting one container per compilation which is slower but it
# could hide errors where the host toolchain would be used
ifeq ($(BUILD_IN_DOCKER),1)
buildtest-indocker: ..in-docker-container

2
sys/arduino/sketches.inc.mk
View File

@ -30,5 +30,5 @@ _ARDUINO_SKETCHES_MAKEFILE := $(lastword $(MAKEFILE_LIST))
$(SKETCH_MODULE_DIR)/$(SKETCH_CPP): $(_ARDUINO_SKETCHES_MAKEFILE)
$(SKETCH_MODULE_DIR)/Makefile: $(_ARDUINO_SKETCHES_MAKEFILE)
# HACK Rebuild cpp files everytime in case one of the `SKETCHES` is deleted
# HACK Rebuild cpp files every time in case one of the `SKETCHES` is deleted
$(SKETCH_MODULE_DIR)/$(SKETCH_CPP): FORCE

2
sys/bitfield/bitfield.c
View File

@ -10,7 +10,7 @@
* @{
*
* @file
* @brief Bitfield auxillary functions
* @brief Bitfield auxiliary functions
*
* @author Kaspar Schleiser <kaspar@schleiser.de>
*

6
sys/cpp11-compat/include/riot/detail/thread_util.hpp
View File

@ -80,7 +80,7 @@ inline auto apply_args(F& f, detail::int_list<Is...>, Tuple&& tup)
}
/**
* @brief Prefix the argument tuple with additonal arguments.
* @brief Prefix the argument tuple with additional arguments.
* In this case the tuple is empty.
*/
template <class F, class Tuple, class... Ts>
@ -90,7 +90,7 @@ inline auto apply_args_prefixed(F& f, detail::int_list<>, Tuple&, Ts&&... args)
}
/**
* @brief Prefix the argument tuple with additonal arguments.
* @brief Prefix the argument tuple with additional arguments.
* In this case the tuple is contains arguments.
*/
template <class F, long... Is, class Tuple, class... Ts>
@ -101,7 +101,7 @@ inline auto apply_args_prefixed(F& f, detail::int_list<Is...>, Tuple& tup,
}
/**
* @brief Suffix the tuple with additonal arguments.
* @brief Suffix the tuple with additional arguments.
*/
template <class F, long... Is, class Tuple, class... Ts>
inline auto apply_args_suffxied(F& f, detail::int_list<Is...>, Tuple& tup,

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