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boards: use common condiguration headers for cc2538 boards

This commit is contained in:
Francisco Molina 2020-03-24 09:27:59 +01:00
parent 194af687a0
commit 493a56ee87
No known key found for this signature in database
GPG Key ID: 3E94EAC3DBDEEDA8
6 changed files with 18 additions and 204 deletions

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@ -31,3 +31,6 @@ DEBUGGER_FLAGS = $(BINDIR) $(ELFFILE)
RESET_FLAGS ?= $(BINDIR)
OBJDUMPFLAGS += --disassemble --source --disassembler-options=force-thumb
# include common cc2538 includes
INCLUDES += -I$(RIOTBOARD)/common/cc2538/include

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@ -22,79 +22,13 @@
#include "cpu.h"
#include "periph_cpu.h"
#include "cfg_clk_default.h"
#include "cfg_timer_default.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock system configuration
* @{
*/
/*
* 0: use internal 32KHz RCOSC
* 1: use external 32KHz XOSC
*/
#ifndef SYS_CTRL_OSC32K_USE_XTAL
#define SYS_CTRL_OSC32K_USE_XTAL (1)
#endif
/*
* 0: use internal 16MHz RCOSC
* 1: use external 32MHz XOSC, required for RF operation
*/
#ifndef SYS_CTRL_OSC_USE_XTAL
#define SYS_CTRL_OSC_USE_XTAL (1)
#endif
#if SYS_CTRL_OSC_USE_XTAL
#define CLOCK_OSC (XOSC32M_FREQ)
#else
#define CLOCK_OSC (RCOSC16M_FREQ)
#endif
#if SYS_CTRL_OSC32K_USE_XTAL
#define CLOCK_OSC32K (XOSC32K_FREQ) /* XCOSC frequency */
#else
#define CLOCK_OSC32K (RCOSC32K_FREQ) /* XCOSC frequency */
#endif
/* System clock frequency 32MHz */
#define CLOCK_CORECLOCK (CLOCK_OSC)
/* I/O clock rate setting 16MHz */
#define CLOCK_IO (CLOCK_OSC / 2)
/** @} */
/**
* @name Timer configuration
*
* General purpose timers (GPT[0-3]) are configured consecutively and in order
* (without gaps) starting from GPT0, i.e. if multiple timers are enabled.
*
* @{
*/
static const timer_conf_t timer_config[] = {
{
.chn = 2,
.cfg = GPTMCFG_16_BIT_TIMER, /* required for XTIMER */
},
{
.chn = 1,
.cfg = GPTMCFG_32_BIT_TIMER,
},
{
.chn = 2,
.cfg = GPTMCFG_16_BIT_TIMER,
},
{
.chn = 1,
.cfg = GPTMCFG_32_BIT_TIMER,
},
};
#define TIMER_NUMOF ARRAY_SIZE(timer_config)
#define TIMER_IRQ_PRIO 1
/** @} */
/**
* @name UART configuration
* @{

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@ -29,3 +29,6 @@ else ifeq ($(PROGRAMMER),jlink)
endif
OBJDUMPFLAGS += --disassemble --source --disassembler-options=force-thumb
# include common cc2538 includes
INCLUDES += -I$(RIOTBOARD)/common/cc2538/include

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@ -25,78 +25,13 @@
#include "cc2538_gpio.h"
#include "periph_cpu.h"
#include "cfg_clk_default.h"
#include "cfg_timer_default.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock system configuration
* @{
*/
/*
* 0: use internal 32KHz RCOSC
* 1: use external 32KHz XOSC
*/
#ifndef SYS_CTRL_OSC32K_USE_XTAL
#define SYS_CTRL_OSC32K_USE_XTAL (1)
#endif
/*
* 0: use internal 16MHz RCOSC
* 1: use external 32MHz XOSC, required for RF operation
*/
#ifndef SYS_CTRL_OSC_USE_XTAL
#define SYS_CTRL_OSC_USE_XTAL (1)
#endif
#if SYS_CTRL_OSC_USE_XTAL
#define CLOCK_OSC (XOSC32M_FREQ)
#else
#define CLOCK_OSC (RCOSC16M_FREQ)
#endif
#if SYS_CTRL_OSC32K_USE_XTAL
#define CLOCK_OSC32K (XOSC32K_FREQ) /* XCOSC frequency */
#else
#define CLOCK_OSC32K (RCOSC32K_FREQ) /* XCOSC frequency */
#endif
/* System clock frequency 32MHz */
#define CLOCK_CORECLOCK (CLOCK_OSC)
/* I/O clock rate setting 16MHz */
#define CLOCK_IO (CLOCK_OSC / 2)
/** @} */
/**
* @name Timer configuration
*
* General purpose timers (GPT[0-3]) are configured consecutively and
* in order (without gaps) starting from GPT0, i.e. if multiple timers are enabled.
*
* @{
*/
static const timer_conf_t timer_config[] = {
{
.chn = 2,
.cfg = GPTMCFG_16_BIT_TIMER, /* required for XTIMER */
},
{
.chn = 1,
.cfg = GPTMCFG_32_BIT_TIMER,
},
{
.chn = 2,
.cfg = GPTMCFG_16_BIT_TIMER,
},
{
.chn = 1,
.cfg = GPTMCFG_32_BIT_TIMER,
},
};
#define TIMER_NUMOF ARRAY_SIZE(timer_config)
#define TIMER_IRQ_PRIO 1
/** @} */
/**
* @name ADC configuration
* @{

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@ -18,3 +18,6 @@ else ifeq ($(PROGRAMMER),cc2538-bsl)
PROG_BAUD ?= 460800
include $(RIOTMAKE)/tools/cc2538-bsl.inc.mk
endif
# include common cc2538 includes
INCLUDES += -I$(RIOTBOARD)/common/cc2538/include

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@ -23,77 +23,13 @@
#include "cc2538_gpio.h"
#include "periph_cpu.h"
#include "cfg_clk_default.h"
#include "cfg_timer_default.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock system configuration
* @{
*/
/*
* 0: use internal 32KHz RCOSC
* 1: use external 32KHz XOSC
*/
#ifndef SYS_CTRL_OSC32K_USE_XTAL
#define SYS_CTRL_OSC32K_USE_XTAL (1)
#endif
/*
* 0: use internal 16MHz RCOSC
* 1: use external 32MHz XOSC, required for RF operation
*/
#ifndef SYS_CTRL_OSC_USE_XTAL
#define SYS_CTRL_OSC_USE_XTAL (1)
#endif
#if SYS_CTRL_OSC_USE_XTAL
#define CLOCK_OSC (XOSC32M_FREQ)
#else
#define CLOCK_OSC (RCOSC16M_FREQ)
#endif
#if SYS_CTRL_OSC32K_USE_XTAL
#define CLOCK_OSC32K (XOSC32K_FREQ) /* XCOSC frequency */
#else
#define CLOCK_OSC32K (RCOSC32K_FREQ) /* XCOSC frequency */
#endif
/* System clock frequency 32MHz */
#define CLOCK_CORECLOCK (CLOCK_OSC)
/* I/O clock rate setting 16MHz */
#define CLOCK_IO (CLOCK_OSC / 2)
/** @} */
/**
* @name Timer configuration
*
* General purpose timers (GPT[0-3]) are configured consecutively and in order
* (without gaps) starting from GPT0, i.e. if multiple timers are enabled.
*
* @{
*/
static const timer_conf_t timer_config[] = {
{
.chn = 2,
.cfg = GPTMCFG_16_BIT_TIMER, /* required for XTIMER */
},
{
.chn = 1,
.cfg = GPTMCFG_32_BIT_TIMER,
},
{
.chn = 2,
.cfg = GPTMCFG_16_BIT_TIMER,
},
{
.chn = 1,
.cfg = GPTMCFG_32_BIT_TIMER,
},
};
#define TIMER_NUMOF ARRAY_SIZE(timer_config)
#define TIMER_IRQ_PRIO 1
/** @} */
/**
* @name ADC configuration
* @{