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https://github.com/RIOT-OS/RIOT.git
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boards: use common condiguration headers for cc2538 boards
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194af687a0
commit
493a56ee87
@ -31,3 +31,6 @@ DEBUGGER_FLAGS = $(BINDIR) $(ELFFILE)
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RESET_FLAGS ?= $(BINDIR)
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OBJDUMPFLAGS += --disassemble --source --disassembler-options=force-thumb
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# include common cc2538 includes
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INCLUDES += -I$(RIOTBOARD)/common/cc2538/include
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@ -22,79 +22,13 @@
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#include "cpu.h"
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#include "periph_cpu.h"
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#include "cfg_clk_default.h"
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#include "cfg_timer_default.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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/*
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* 0: use internal 32KHz RCOSC
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* 1: use external 32KHz XOSC
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*/
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#ifndef SYS_CTRL_OSC32K_USE_XTAL
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#define SYS_CTRL_OSC32K_USE_XTAL (1)
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#endif
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/*
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* 0: use internal 16MHz RCOSC
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* 1: use external 32MHz XOSC, required for RF operation
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*/
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#ifndef SYS_CTRL_OSC_USE_XTAL
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#define SYS_CTRL_OSC_USE_XTAL (1)
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#endif
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#if SYS_CTRL_OSC_USE_XTAL
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#define CLOCK_OSC (XOSC32M_FREQ)
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#else
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#define CLOCK_OSC (RCOSC16M_FREQ)
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#endif
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#if SYS_CTRL_OSC32K_USE_XTAL
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#define CLOCK_OSC32K (XOSC32K_FREQ) /* XCOSC frequency */
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#else
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#define CLOCK_OSC32K (RCOSC32K_FREQ) /* XCOSC frequency */
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#endif
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/* System clock frequency 32MHz */
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#define CLOCK_CORECLOCK (CLOCK_OSC)
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/* I/O clock rate setting 16MHz */
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#define CLOCK_IO (CLOCK_OSC / 2)
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/** @} */
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/**
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* @name Timer configuration
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*
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* General purpose timers (GPT[0-3]) are configured consecutively and in order
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* (without gaps) starting from GPT0, i.e. if multiple timers are enabled.
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*
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.chn = 2,
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.cfg = GPTMCFG_16_BIT_TIMER, /* required for XTIMER */
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},
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{
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.chn = 1,
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.cfg = GPTMCFG_32_BIT_TIMER,
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},
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{
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.chn = 2,
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.cfg = GPTMCFG_16_BIT_TIMER,
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},
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{
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.chn = 1,
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.cfg = GPTMCFG_32_BIT_TIMER,
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},
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};
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#define TIMER_NUMOF ARRAY_SIZE(timer_config)
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#define TIMER_IRQ_PRIO 1
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/** @} */
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/**
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* @name UART configuration
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* @{
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@ -29,3 +29,6 @@ else ifeq ($(PROGRAMMER),jlink)
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endif
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OBJDUMPFLAGS += --disassemble --source --disassembler-options=force-thumb
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# include common cc2538 includes
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INCLUDES += -I$(RIOTBOARD)/common/cc2538/include
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@ -25,78 +25,13 @@
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#include "cc2538_gpio.h"
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#include "periph_cpu.h"
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#include "cfg_clk_default.h"
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#include "cfg_timer_default.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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/*
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* 0: use internal 32KHz RCOSC
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* 1: use external 32KHz XOSC
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*/
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#ifndef SYS_CTRL_OSC32K_USE_XTAL
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#define SYS_CTRL_OSC32K_USE_XTAL (1)
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#endif
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/*
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* 0: use internal 16MHz RCOSC
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* 1: use external 32MHz XOSC, required for RF operation
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*/
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#ifndef SYS_CTRL_OSC_USE_XTAL
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#define SYS_CTRL_OSC_USE_XTAL (1)
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#endif
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#if SYS_CTRL_OSC_USE_XTAL
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#define CLOCK_OSC (XOSC32M_FREQ)
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#else
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#define CLOCK_OSC (RCOSC16M_FREQ)
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#endif
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#if SYS_CTRL_OSC32K_USE_XTAL
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#define CLOCK_OSC32K (XOSC32K_FREQ) /* XCOSC frequency */
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#else
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#define CLOCK_OSC32K (RCOSC32K_FREQ) /* XCOSC frequency */
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#endif
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/* System clock frequency 32MHz */
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#define CLOCK_CORECLOCK (CLOCK_OSC)
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/* I/O clock rate setting 16MHz */
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#define CLOCK_IO (CLOCK_OSC / 2)
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/** @} */
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/**
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* @name Timer configuration
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*
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* General purpose timers (GPT[0-3]) are configured consecutively and
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* in order (without gaps) starting from GPT0, i.e. if multiple timers are enabled.
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*
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.chn = 2,
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.cfg = GPTMCFG_16_BIT_TIMER, /* required for XTIMER */
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},
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{
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.chn = 1,
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.cfg = GPTMCFG_32_BIT_TIMER,
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},
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{
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.chn = 2,
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.cfg = GPTMCFG_16_BIT_TIMER,
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},
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{
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.chn = 1,
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.cfg = GPTMCFG_32_BIT_TIMER,
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},
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};
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#define TIMER_NUMOF ARRAY_SIZE(timer_config)
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#define TIMER_IRQ_PRIO 1
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/** @} */
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/**
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* @name ADC configuration
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* @{
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@ -18,3 +18,6 @@ else ifeq ($(PROGRAMMER),cc2538-bsl)
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PROG_BAUD ?= 460800
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include $(RIOTMAKE)/tools/cc2538-bsl.inc.mk
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endif
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# include common cc2538 includes
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INCLUDES += -I$(RIOTBOARD)/common/cc2538/include
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@ -23,77 +23,13 @@
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#include "cc2538_gpio.h"
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#include "periph_cpu.h"
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#include "cfg_clk_default.h"
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#include "cfg_timer_default.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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/*
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* 0: use internal 32KHz RCOSC
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* 1: use external 32KHz XOSC
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*/
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#ifndef SYS_CTRL_OSC32K_USE_XTAL
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#define SYS_CTRL_OSC32K_USE_XTAL (1)
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#endif
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/*
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* 0: use internal 16MHz RCOSC
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* 1: use external 32MHz XOSC, required for RF operation
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*/
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#ifndef SYS_CTRL_OSC_USE_XTAL
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#define SYS_CTRL_OSC_USE_XTAL (1)
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#endif
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#if SYS_CTRL_OSC_USE_XTAL
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#define CLOCK_OSC (XOSC32M_FREQ)
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#else
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#define CLOCK_OSC (RCOSC16M_FREQ)
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#endif
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#if SYS_CTRL_OSC32K_USE_XTAL
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#define CLOCK_OSC32K (XOSC32K_FREQ) /* XCOSC frequency */
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#else
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#define CLOCK_OSC32K (RCOSC32K_FREQ) /* XCOSC frequency */
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#endif
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/* System clock frequency 32MHz */
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#define CLOCK_CORECLOCK (CLOCK_OSC)
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/* I/O clock rate setting 16MHz */
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#define CLOCK_IO (CLOCK_OSC / 2)
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/** @} */
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/**
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* @name Timer configuration
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*
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* General purpose timers (GPT[0-3]) are configured consecutively and in order
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* (without gaps) starting from GPT0, i.e. if multiple timers are enabled.
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*
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.chn = 2,
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.cfg = GPTMCFG_16_BIT_TIMER, /* required for XTIMER */
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},
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{
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.chn = 1,
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.cfg = GPTMCFG_32_BIT_TIMER,
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},
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{
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.chn = 2,
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.cfg = GPTMCFG_16_BIT_TIMER,
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},
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{
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.chn = 1,
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.cfg = GPTMCFG_32_BIT_TIMER,
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},
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};
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#define TIMER_NUMOF ARRAY_SIZE(timer_config)
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#define TIMER_IRQ_PRIO 1
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/** @} */
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/**
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* @name ADC configuration
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* @{
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