RIOT-OS/RIOT
RIOT-OS/RIOT
1
0
Fork 0
mirror of https://github.com/RIOT-OS/RIOT.git synced 2024-12-29 04:50:03 +01:00
Code Releases Activity

cpu/nrf52-9160: add periph_spi_init_gpio

Browse Source
This commit is contained in:
Francisco Molina 2022-01-18 15:08:46 +01:00
parent 8db513a8f6
commit 4906353cfe
9 changed files with 60 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
cpu/nrf52/Kconfig
View File

@ -17,6 +17,7 @@ config CPU_FAM_NRF52
select HAS_CORTEXM_MPU
select HAS_CPU_NRF52
select HAS_PERIPH_I2C_RECONFIGURE
select HAS_PERIPH_SPI_GPIO_MODE
## CPU Models
config CPU_MODEL_NRF52805XXAA

4
cpu/nrf52/Makefile.dep
View File

@ -32,5 +32,9 @@ ifneq (,$(filter saul_nrf_vddh,$(USEMODULE)))
FEATURES_REQUIRED += periph_adc
endif
ifneq (,$(filter periph_spi,$(USEMODULE)))
USEMODULE += periph_spi_gpio_mode
endif
include $(RIOTCPU)/nrf5x_common/Makefile.dep
include $(RIOTCPU)/cortexm_common/Makefile.dep

1
cpu/nrf52/Makefile.features
View File

@ -24,6 +24,7 @@ FEATURES_PROVIDED += ble_nimble_netif
FEATURES_PROVIDED += cortexm_mpu
FEATURES_PROVIDED += periph_i2c_reconfigure
FEATURES_PROVIDED += periph_spi_gpio_mode
# On top of the default 1Mbit PHY mode, all nrf52 support the 2MBit PHY mode,
# and the 52840 does further support the coded PHYs

1
cpu/nrf52/periph/Kconfig
View File

@ -15,6 +15,7 @@ config MODULE_PERIPH_UART_NONBLOCKING
config MODULE_PERIPH_SPI
depends on HAS_PERIPH_SPI
select MODULE_PERIPH_GPIO_IRQ if CPU_MODEL_NRF52832XXAA && HAS_PERIPH_GPIO_IRQ
select MODULE_PERIPH_SPI_GPIO_MODE if MODULE_PERIPH_SPI && HAS_PERIPH_SPI_GPIO_MODE
config MODULE_SAUL_NRF_VDDH
bool "Internal Voltage Sensor"

30
cpu/nrf5x_common/periph/spi_nrf52_nrf9160.c
View File

@ -135,11 +135,35 @@ void spi_init(spi_t bus)
spi_init_pins(bus);
}
int spi_init_with_gpio_mode(spi_t bus, const spi_gpio_mode_t* mode)
{
assert(bus < SPI_NUMOF);
if (gpio_is_valid(spi_config[bus].mosi)) {
gpio_init(spi_config[bus].miso, mode->mosi);
}
if (gpio_is_valid(spi_config[bus].miso)) {
gpio_init(spi_config[bus].mosi, mode->miso);
}
if (gpio_is_valid(spi_config[bus].sclk)) {
/* clk_pin will be muxed during acquire / release */
gpio_init(spi_config[bus].sclk, mode->sclk);
}
return 0;
}
void spi_init_pins(spi_t bus)
{
gpio_init(spi_config[bus].sclk, GPIO_OUT);
gpio_init(spi_config[bus].mosi, GPIO_OUT);
gpio_init(spi_config[bus].miso, GPIO_IN);
const spi_gpio_mode_t gpio_modes = {
.mosi = GPIO_OUT,
.sclk = GPIO_OUT,
.miso = GPIO_IN,
};
spi_init_with_gpio_mode(bus, &gpio_modes);
/* select pins for the SPI device */
SPI_SCKSEL = spi_config[bus].sclk;
SPI_MOSISEL = spi_config[bus].mosi;

2
cpu/nrf9160/Kconfig
View File

@ -14,6 +14,7 @@ config CPU_FAM_NRF9160
select HAS_PERIPH_GPIO_IRQ
select HAS_PERIPH_TIMER_PERIODIC
select HAS_PERIPH_UART_MODECFG
select HAS_PERIPH_SPI_GPIO_MODE
## CPU Models
config CPU_MODEL_NRF9160
@ -38,5 +39,6 @@ config HAS_CPU_NRF9160
Indicates that the current cpu is 'nrf9160'.
rsource "vectors/Kconfig"
rsource "periph/Kconfig"
source "$(RIOTCPU)/nrf5x_common/Kconfig"

4
cpu/nrf9160/Makefile.dep
View File

@ -1,4 +1,8 @@
USEMODULE += nrf9160_vectors
ifneq (,$(filter periph_spi,$(USEMODULE)))
USEMODULE += periph_spi_gpio_mode
endif
include $(RIOTCPU)/nrf5x_common/Makefile.dep
include $(RIOTCPU)/cortexm_common/Makefile.dep

2
cpu/nrf9160/Makefile.features
View File

@ -1,4 +1,6 @@
CPU_CORE = cortex-m33
CPU_FAM = nrf9160
FEATURES_PROVIDED += periph_spi_gpio_mode
include $(RIOTCPU)/nrf5x_common/Makefile.features

18
cpu/nrf9160/periph/Kconfig Normal file
View File

@ -0,0 +1,18 @@
# Copyright (c) 2022 Inria
#
# This file is subject to the terms and conditions of the GNU Lesser
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.
#
if TEST_KCONFIG
config MODULE_PERIPH_SPI
depends on HAS_PERIPH_SPI
select MODULE_PERIPH_SPI_GPIO_MODE if MODULE_PERIPH_SPI && HAS_PERIPH_SPI_GPIO_MODE
config MODULE_SAUL_NRF_VDDH
bool "Internal Voltage Sensor"
depends on HAS_PERIPH_ADC
endif # TEST_KCONFIG