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Merge pull request #17302 from aabadie/pr/cpu/stm32_usb_l4

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cpu/stm32: enable USB OTG FS on high end L4
This commit is contained in:
Dylan Laduranty 2021-12-01 20:56:07 +01:00 committed by GitHub
commit 48e71b2d8c
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GPG Key ID: 4AEE18F83AFDEB23
17 changed files with 22 additions and 2 deletions
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1
boards/b-l475e-iot01a/Kconfig
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@ -22,6 +22,7 @@ config BOARD_B_L475E_IOT01A
select HAS_PERIPH_SPI
select HAS_PERIPH_TIMER
select HAS_PERIPH_UART
select HAS_PERIPH_USBDEV
# Put other features for this board (in alphabetical order)
select HAS_RIOTBOOT

1
boards/b-l475e-iot01a/Makefile.features
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@ -10,6 +10,7 @@ FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_usbdev
# Put other features for this board (in alphabetical order)
FEATURES_PROVIDED += riotboot

1
boards/b-l475e-iot01a/include/periph_conf.h
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@ -27,6 +27,7 @@
#include "periph_cpu.h"
#include "clk_conf.h"
#include "cfg_rtt_default.h"
#include "cfg_usb_otg_fs.h"
#ifdef __cplusplus
extern "C" {

1
boards/nucleo-l496zg/Kconfig
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@ -23,6 +23,7 @@ config BOARD_NUCLEO_L496ZG
select HAS_PERIPH_SPI
select HAS_PERIPH_TIMER
select HAS_PERIPH_UART
select HAS_PERIPH_USBDEV
select MODULE_PERIPH_LPUART if MODULE_STDIO_UART && HAS_PERIPH_LPUART

1
boards/nucleo-l496zg/Makefile.features
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@ -9,6 +9,7 @@ FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart periph_lpuart
FEATURES_PROVIDED += periph_usbdev
# Put other features for this board (in alphabetical order)
FEATURES_PROVIDED += riotboot

1
boards/nucleo-l496zg/include/periph_conf.h
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@ -28,6 +28,7 @@
#include "clk_conf.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_rtt_default.h"
#include "cfg_usb_otg_fs.h"
#ifdef __cplusplus
extern "C" {

1
boards/nucleo-l4r5zi/Kconfig
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@ -22,6 +22,7 @@ config BOARD_NUCLEO_L4R5ZI
select HAS_PERIPH_SPI
select HAS_PERIPH_TIMER
select HAS_PERIPH_UART
select HAS_PERIPH_USBDEV
select MODULE_PERIPH_LPUART if MODULE_STDIO_UART && HAS_PERIPH_LPUART

1
boards/nucleo-l4r5zi/Makefile.features
View File

@ -9,6 +9,7 @@ FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_usbdev
# Put other features for this board (in alphabetical order)
FEATURES_PROVIDED += riotboot

1
boards/nucleo-l4r5zi/include/periph_conf.h
View File

@ -28,6 +28,7 @@
#include "clk_conf.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_rtt_default.h"
#include "cfg_usb_otg_fs.h"
#ifdef __cplusplus
extern "C" {

1
boards/p-l496g-cell02/Kconfig
View File

@ -21,6 +21,7 @@ config BOARD_P_L496G_CELL02
select HAS_PERIPH_SPI
select HAS_PERIPH_TIMER
select HAS_PERIPH_UART
select HAS_PERIPH_USBDEV
# Clock configuration
select BOARD_HAS_LSE

1
boards/p-l496g-cell02/Makefile.features
View File

@ -10,3 +10,4 @@ FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_usbdev

1
boards/p-l496g-cell02/include/periph_conf.h
View File

@ -28,6 +28,7 @@
#include "clk_conf.h"
#include "cfg_rtt_default.h"
#include "cfg_timer_tim2.h"
#include "cfg_usb_otg_fs.h"
#ifdef __cplusplus
extern "C" {

1
boards/stm32l476g-disco/Kconfig
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@ -18,6 +18,7 @@ config BOARD_STM32L476G_DISCO
select HAS_PERIPH_RTT
select HAS_PERIPH_TIMER
select HAS_PERIPH_UART
select HAS_PERIPH_USBDEV
# Put other features for this board (in alphabetical order)
select HAS_RIOTBOOT

1
boards/stm32l476g-disco/Makefile.features
View File

@ -6,6 +6,7 @@ FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
FEATURES_PROVIDED += periph_usbdev
# Put other features for this board (in alphabetical order)
FEATURES_PROVIDED += riotboot

1
boards/stm32l476g-disco/include/periph_conf.h
View File

@ -27,6 +27,7 @@
#include "periph_cpu.h"
#include "clk_conf.h"
#include "cfg_rtt_default.h"
#include "cfg_usb_otg_fs.h"
#ifdef __cplusplus
extern "C" {

5
cpu/stm32/periph/usbdev.c
View File

@ -616,6 +616,11 @@ static void _usbdev_init(usbdev_t *dev)
stm32_usb_otg_fshs_t *usbdev = (stm32_usb_otg_fshs_t *)dev;
const stm32_usb_otg_fshs_config_t *conf = usbdev->config;
#if defined(PWR_CR2_USV) /* on L4 */
/* Validate USB Supply */
PWR->CR2 |= PWR_CR2_USV;
#endif
/* Enable the clock to the peripheral */
periph_clk_en(conf->ahb, conf->rcc_mask);

4
cpu/stm32/stmclk/stmclk_l4wx.c
View File

@ -347,8 +347,8 @@
#define CLOCK48MHZ_SELECT (0)
#endif
/* Only periph_hwrng requires 48MHz for the moment */
#if IS_USED(MODULE_PERIPH_HWRNG)
/* periph_hwrng and periph_usbdev require a 48MHz clock source */
#if IS_USED(MODULE_PERIPH_HWRNG) || IS_USED(MODULE_PERIPH_USBDEV)
#if !IS_ACTIVE(CLOCK48MHZ_USE_PLLQ) && !IS_ACTIVE(CLOCK48MHZ_USE_MSI)
#error "No 48MHz clock source available, HWRNG cannot work"
#endif