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cc2538: fix pedantic compiler warnings

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This commit is contained in:
Oleg Hahm 2015-11-28 14:18:48 +01:00
parent d92ec1d11e
commit 4780b5cba1
10 changed files with 83 additions and 80 deletions
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4
cpu/cc2538/cpu.c
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@ -75,10 +75,10 @@ static void cpu_clock_init(void)
#endif #endif
/* Configure the clock settings: */ /* Configure the clock settings: */
SYS_CTRL->CLOCK_CTRL = CLOCK_CTRL_VALUE; SYS_CTRL->cc2538_sys_ctrl_clk_ctrl.CLOCK_CTRL = CLOCK_CTRL_VALUE;
/* Wait for the new clock settings to take effect: */ /* Wait for the new clock settings to take effect: */
while ( (SYS_CTRL->CLOCK_STA ^ CLOCK_CTRL_VALUE) & CLOCK_STA_MASK ); while ((SYS_CTRL->cc2538_sys_ctrl_clk_sta.CLOCK_STA ^ CLOCK_CTRL_VALUE) & CLOCK_STA_MASK);
#if SYS_CTRL_OSC32K_USE_XTAL #if SYS_CTRL_OSC32K_USE_XTAL
/* Wait for the 32-kHz crystal oscillator to stabilize: */ /* Wait for the 32-kHz crystal oscillator to stabilize: */

14
cpu/cc2538/include/cc2538-uart.h
View File

@ -34,7 +34,7 @@ typedef struct {
union { union {
cc2538_reg_t RSR; /**< UART receive status and error clear */ cc2538_reg_t RSR; /**< UART receive status and error clear */
cc2538_reg_t ECR; /**< UART receive status and error clear */ cc2538_reg_t ECR; /**< UART receive status and error clear */
}; } cc2538_uart_dr;
cc2538_reg_t RESERVED1[4]; /**< Reserved addresses */ cc2538_reg_t RESERVED1[4]; /**< Reserved addresses */
@ -50,7 +50,7 @@ typedef struct {
cc2538_reg_t TXFE : 1; /**< UART transmit FIFO empty */ cc2538_reg_t TXFE : 1; /**< UART transmit FIFO empty */
cc2538_reg_t RESERVED1 : 24; /**< Reserved bits */ cc2538_reg_t RESERVED1 : 24; /**< Reserved bits */
} FRbits; } FRbits;
}; } cc2538_uart_fr;
cc2538_reg_t RESERVED2; /**< Reserved byte */ cc2538_reg_t RESERVED2; /**< Reserved byte */
cc2538_reg_t ILPR; /**< UART IrDA Low-Power Register */ cc2538_reg_t ILPR; /**< UART IrDA Low-Power Register */
@ -69,7 +69,7 @@ typedef struct {
cc2538_reg_t SPS : 1; /**< UART stick parity select */ cc2538_reg_t SPS : 1; /**< UART stick parity select */
cc2538_reg_t RESERVED : 24; /**< Reserved bits */ cc2538_reg_t RESERVED : 24; /**< Reserved bits */
} LCRHbits; } LCRHbits;
}; } cc2538_uart_lcrh;
union { union {
cc2538_reg_t CTL; /**< UART Control */ cc2538_reg_t CTL; /**< UART Control */
@ -89,7 +89,7 @@ typedef struct {
cc2538_reg_t CTSEN : 1; /**< U1CTS Hardware flow control enable */ cc2538_reg_t CTSEN : 1; /**< U1CTS Hardware flow control enable */
cc2538_reg_t RESERVED13 : 16; /**< Reserved bits */ cc2538_reg_t RESERVED13 : 16; /**< Reserved bits */
} CTLbits; } CTLbits;
}; } cc2538_uart_ctl;
union { union {
cc2538_reg_t IFLS; /**< UART interrupt FIFO Level Select */ cc2538_reg_t IFLS; /**< UART interrupt FIFO Level Select */
@ -98,7 +98,7 @@ typedef struct {
cc2538_reg_t RXIFLSEL : 3; /**< UART receive interrupt FIFO level select */ cc2538_reg_t RXIFLSEL : 3; /**< UART receive interrupt FIFO level select */
cc2538_reg_t RESERVED : 26; /**< Reserved bits */ cc2538_reg_t RESERVED : 26; /**< Reserved bits */
} IFLSbits; } IFLSbits;
}; } cc2538_uart_ifls;
union { union {
cc2538_reg_t IM; /**< UART Interrupt Mask */ cc2538_reg_t IM; /**< UART Interrupt Mask */
@ -118,7 +118,7 @@ typedef struct {
cc2538_reg_t LME5IM : 1; /**< LIN mode edge 5 interrupt mask */ cc2538_reg_t LME5IM : 1; /**< LIN mode edge 5 interrupt mask */
cc2538_reg_t RESERVED1 : 16; /**< Reserved bits */ cc2538_reg_t RESERVED1 : 16; /**< Reserved bits */
} IMbits; } IMbits;
}; } cc2538_uart_im;
cc2538_reg_t RIS; /**< UART Raw Interrupt Status */ cc2538_reg_t RIS; /**< UART Raw Interrupt Status */
@ -140,7 +140,7 @@ typedef struct {
cc2538_reg_t LME5MIS : 1; /**< LIN mode edge 5 masked interrupt status */ cc2538_reg_t LME5MIS : 1; /**< LIN mode edge 5 masked interrupt status */
cc2538_reg_t RESERVED10 : 16; /**< Reserved bits */ cc2538_reg_t RESERVED10 : 16; /**< Reserved bits */
} MISbits; } MISbits;
}; } cc2538_uart_mis;
cc2538_reg_t ICR; /**< UART Interrupt Clear Register */ cc2538_reg_t ICR; /**< UART Interrupt Clear Register */
cc2538_reg_t DMACTL; /**< UART DMA Control */ cc2538_reg_t DMACTL; /**< UART DMA Control */

6
cpu/cc2538/include/gptimer.h
View File

@ -64,7 +64,7 @@ typedef struct {
cc2538_reg_t TAPLO : 1; /**< Legacy PWM operation */ cc2538_reg_t TAPLO : 1; /**< Legacy PWM operation */
cc2538_reg_t RESERVED5 : 20; /**< Reserved bits */ cc2538_reg_t RESERVED5 : 20; /**< Reserved bits */
} TAMRbits; } TAMRbits;
}; } cc2538_gptimer_tamr;
union { union {
cc2538_reg_t TBMR; /**< GPTIMER Timer B mode */ cc2538_reg_t TBMR; /**< GPTIMER Timer B mode */
@ -82,7 +82,7 @@ typedef struct {
cc2538_reg_t TBPLO : 1; /**< Legacy PWM operation */ cc2538_reg_t TBPLO : 1; /**< Legacy PWM operation */
cc2538_reg_t RESERVED6 : 20; /**< Reserved bits */ cc2538_reg_t RESERVED6 : 20; /**< Reserved bits */
} TBMRbits; } TBMRbits;
}; } cc2538_gptimer_tbmr;
union { union {
cc2538_reg_t CTL; /**< GPTIMER Control */ cc2538_reg_t CTL; /**< GPTIMER Control */
@ -102,7 +102,7 @@ typedef struct {
cc2538_reg_t TBPWML : 1; /**< GPTM Timer B PWM output level */ cc2538_reg_t TBPWML : 1; /**< GPTM Timer B PWM output level */
cc2538_reg_t RESERVED4 : 17; /**< Reserved bits */ cc2538_reg_t RESERVED4 : 17; /**< Reserved bits */
} CTLbits; } CTLbits;
}; } cc2538_gptimer_ctl;
cc2538_reg_t SYNC; /**< GPTIMER Synchronize */ cc2538_reg_t SYNC; /**< GPTIMER Synchronize */
cc2538_reg_t RESERVED2; /**< Reserved word */ cc2538_reg_t RESERVED2; /**< Reserved word */

4
cpu/cc2538/include/rfcore.h
View File

@ -89,7 +89,7 @@ typedef struct {
cc2538_reg_t RSSI_VALID : 1; /**< RSSI value is valid */ cc2538_reg_t RSSI_VALID : 1; /**< RSSI value is valid */
cc2538_reg_t RESERVED : 31; /**< Reserved bits */ cc2538_reg_t RESERVED : 31; /**< Reserved bits */
} XREG_RSSISTATbits; } XREG_RSSISTATbits;
}; } cc2538_rfcore_xreg_rssistat;
cc2538_reg_t XREG_RXFIRST; /**< RF First byte in RX FIFO */ cc2538_reg_t XREG_RXFIRST; /**< RF First byte in RX FIFO */
cc2538_reg_t XREG_RXFIFOCNT; /**< RF Number of bytes in RX FIFO */ cc2538_reg_t XREG_RXFIFOCNT; /**< RF Number of bytes in RX FIFO */
@ -112,7 +112,7 @@ typedef struct {
cc2538_reg_t QRND : 1; /**< Random bit from the Q channel of the receiver */ cc2538_reg_t QRND : 1; /**< Random bit from the Q channel of the receiver */
cc2538_reg_t RESERVED : 30; /**< Reserved bits */ cc2538_reg_t RESERVED : 30; /**< Reserved bits */
} XREG_RFRNDbits; } XREG_RFRNDbits;
}; } cc2538_rfcore_xreg_rfrnd;
cc2538_reg_t XREG_MDMCTRL0; /**< RF Controls modem */ cc2538_reg_t XREG_MDMCTRL0; /**< RF Controls modem */
cc2538_reg_t XREG_MDMCTRL1; /**< RF Controls modem */ cc2538_reg_t XREG_MDMCTRL1; /**< RF Controls modem */

2
cpu/cc2538/include/soc-adc.h
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@ -39,7 +39,7 @@ typedef struct {
cc2538_reg_t EOC : 1; /**< End of conversion */ cc2538_reg_t EOC : 1; /**< End of conversion */
cc2538_reg_t RESERVED1 : 24; /**< Reserved bits */ cc2538_reg_t RESERVED1 : 24; /**< Reserved bits */
} ADCCON1bits; } ADCCON1bits;
}; } cc2538_adc_adccon1;
cc2538_reg_t ADCCON2; /**< ADC Control Register 2 */ cc2538_reg_t ADCCON2; /**< ADC Control Register 2 */
cc2538_reg_t ADCCON3; /**< ADC Control Register 3 */ cc2538_reg_t ADCCON3; /**< ADC Control Register 3 */

14
cpu/cc2538/include/sys-ctrl.h
View File

@ -45,7 +45,7 @@ typedef struct {
cc2538_reg_t OSC32K_CADIS : 1; /**< Disable calibration 32-kHz RC oscillator */ cc2538_reg_t OSC32K_CADIS : 1; /**< Disable calibration 32-kHz RC oscillator */
cc2538_reg_t RESERVED5 : 6; /**< Reserved bits */ cc2538_reg_t RESERVED5 : 6; /**< Reserved bits */
} CLOCK_CTRLbits; } CLOCK_CTRLbits;
}; } cc2538_sys_ctrl_clk_ctrl;
union { union {
cc2538_reg_t CLOCK_STA; /**< Clock status register */ cc2538_reg_t CLOCK_STA; /**< Clock status register */
@ -66,7 +66,7 @@ typedef struct {
cc2538_reg_t SYNC_32K : 1; /**< 32-kHz clock source synced to undivided system clock (16 or 32 MHz) */ cc2538_reg_t SYNC_32K : 1; /**< 32-kHz clock source synced to undivided system clock (16 or 32 MHz) */
cc2538_reg_t RESERVED9 : 5; /**< Reserved bits */ cc2538_reg_t RESERVED9 : 5; /**< Reserved bits */
} CLOCK_STAbits; } CLOCK_STAbits;
}; } cc2538_sys_ctrl_clk_sta;
cc2538_reg_t RCGCGPT; /**< Module clocks for GPT[3:0] when the CPU is in active (run) mode */ cc2538_reg_t RCGCGPT; /**< Module clocks for GPT[3:0] when the CPU is in active (run) mode */
cc2538_reg_t SCGCGPT; /**< Module clocks for GPT[3:0] when the CPU is in sleep mode */ cc2538_reg_t SCGCGPT; /**< Module clocks for GPT[3:0] when the CPU is in sleep mode */
@ -84,7 +84,7 @@ typedef struct {
cc2538_reg_t UART1 : 1; /**< Enable UART1 clock in active (run) mode */ cc2538_reg_t UART1 : 1; /**< Enable UART1 clock in active (run) mode */
cc2538_reg_t RESERVED : 30; /**< Reserved bits */ cc2538_reg_t RESERVED : 30; /**< Reserved bits */
} RCGCUARTbits; } RCGCUARTbits;
}; } cc2538_sys_ctrl_unnamed1;
union { union {
cc2538_reg_t SCGCUART; /**< Module clocks for UART[1:0] when the CPU is in sleep mode */ cc2538_reg_t SCGCUART; /**< Module clocks for UART[1:0] when the CPU is in sleep mode */
@ -93,7 +93,7 @@ typedef struct {
cc2538_reg_t UART1 : 1; /**< Enable UART1 clock in sleep mode */ cc2538_reg_t UART1 : 1; /**< Enable UART1 clock in sleep mode */
cc2538_reg_t RESERVED : 30; /**< Reserved bits */ cc2538_reg_t RESERVED : 30; /**< Reserved bits */
} SCGCUARTbits; } SCGCUARTbits;
}; } cc2538_sys_ctrl_unnamed2;
union { union {
cc2538_reg_t DCGCUART; /**< Module clocks for UART[1:0] when the CPU is in PM0 */ cc2538_reg_t DCGCUART; /**< Module clocks for UART[1:0] when the CPU is in PM0 */
@ -102,7 +102,7 @@ typedef struct {
cc2538_reg_t UART1 : 1; /**< Enable UART1 clock in PM0 */ cc2538_reg_t UART1 : 1; /**< Enable UART1 clock in PM0 */
cc2538_reg_t RESERVED : 30; /**< Reserved bits */ cc2538_reg_t RESERVED : 30; /**< Reserved bits */
} DCGCUARTbits; } DCGCUARTbits;
}; } cc2538_sys_ctrl_unnamed3;
cc2538_reg_t SRUART; /**< Reset for UART[1:0]. */ cc2538_reg_t SRUART; /**< Reset for UART[1:0]. */
cc2538_reg_t RCGCI2C; /**< Module clocks for I2C when the CPU is in active (run) mode */ cc2538_reg_t RCGCI2C; /**< Module clocks for I2C when the CPU is in active (run) mode */
@ -134,7 +134,9 @@ typedef struct {
/** /**
* @brief Compute the current system clock frequency based on the SYS_CTRL register states * @brief Compute the current system clock frequency based on the SYS_CTRL register states
*/ */
#define sys_clock_freq() ( (SYS_CTRL->CLOCK_CTRLbits.OSC? RCOSC16M_FREQ : XOSC32M_FREQ) >> SYS_CTRL->CLOCK_CTRLbits.SYS_DIV ) #define sys_clock_freq() ((SYS_CTRL->cc2538_sys_ctrl_clk_ctrl.CLOCK_CTRLbits.OSC ? \
RCOSC16M_FREQ : XOSC32M_FREQ) >> \
SYS_CTRL->cc2538_sys_ctrl_clk_ctrl.CLOCK_CTRLbits.SYS_DIV )
#ifdef __cplusplus #ifdef __cplusplus
} /* end extern "C" */ } /* end extern "C" */

1
cpu/cc2538/lpm_arch.c
View File

@ -26,6 +26,7 @@ void lpm_arch_init(void)
enum lpm_mode lpm_arch_set(enum lpm_mode target) enum lpm_mode lpm_arch_set(enum lpm_mode target)
{ {
(void) target;
return 0; return 0;
} }

11
cpu/cc2538/periph/random.c
View File

@ -33,7 +33,7 @@ void random_init(void)
int i; int i;
/* Make sure the RNG is on */ /* Make sure the RNG is on */
SOC_ADC->ADCCON1bits.RCTRL = 0; SOC_ADC->cc2538_adc_adccon1.ADCCON1bits.RCTRL = 0;
/* Enable clock for the RF Core */ /* Enable clock for the RF Core */
SYS_CTRL_RCGCRFC = 1; SYS_CTRL_RCGCRFC = 1;
@ -52,7 +52,7 @@ void random_init(void)
* have died out. A convenient way to do this is to wait for the RSSI-valid * have died out. A convenient way to do this is to wait for the RSSI-valid
* signal to go high." * signal to go high."
*/ */
while (!RFCORE->XREG_RSSISTATbits.RSSI_VALID); while (!RFCORE->cc2538_rfcore_xreg_rssistat.XREG_RSSISTATbits.RSSI_VALID);
/* /*
* Form the seed by concatenating bits from IF_ADC in the RF receive path. * Form the seed by concatenating bits from IF_ADC in the RF receive path.
@ -62,7 +62,7 @@ void random_init(void)
*/ */
for (i = 0; (i < 8) || (seed == 0) || (seed == 0x8003); i++) { for (i = 0; (i < 8) || (seed == 0) || (seed == 0x8003); i++) {
seed <<= 2; seed <<= 2;
seed ^= RFCORE->XREG_RFRND; seed ^= RFCORE->cc2538_rfcore_xreg_rfrnd.XREG_RFRND;
} }
/* Seed the high byte first: */ /* Seed the high byte first: */
@ -77,11 +77,10 @@ void random_init(void)
int random_read(char *buf, unsigned int num) int random_read(char *buf, unsigned int num)
{ {
int count; unsigned count;
for (count = 0; count < num; ) { for (count = 0; count < num; ) {
/* Clock the RNG LSFR once: */ /* Clock the RNG LSFR once: */
SOC_ADC->ADCCON1bits.RCTRL = 1; SOC_ADC->cc2538_adc_adccon1.ADCCON1bits.RCTRL = 1;
/* Read up to 2 bytes of random data: */ /* Read up to 2 bytes of random data: */
buf[count++] = SOC_ADC_RNDL; buf[count++] = SOC_ADC_RNDL;

44
cpu/cc2538/periph/timer.c
View File

@ -86,11 +86,11 @@ int timer_init(tim_t dev, unsigned int ticks_per_us, void (*callback)(int))
SYS_CTRL_RCGCGPT |= (1 << gptimer_num); SYS_CTRL_RCGCGPT |= (1 << gptimer_num);
/* Disable this timer before configuring it: */ /* Disable this timer before configuring it: */
gptimer->CTL = 0; gptimer->cc2538_gptimer_ctl.CTL = 0;
gptimer->CFG = GPTMCFG_16_BIT_TIMER; gptimer->CFG = GPTMCFG_16_BIT_TIMER;
gptimer->TAMR = GPTIMER_PERIODIC_MODE; gptimer->cc2538_gptimer_tamr.TAMR = GPTIMER_PERIODIC_MODE;
gptimer->TAMRbits.TACDIR = 1; /**< Count up */ gptimer->cc2538_gptimer_tamr.TAMRbits.TACDIR = 1; /**< Count up */
/* Set the prescale register for the desired frequency: */ /* Set the prescale register for the desired frequency: */
gptimer->TAPR = RCOSC16M_FREQ / (ticks_per_us * USEC_PER_SEC) - 1; gptimer->TAPR = RCOSC16M_FREQ / (ticks_per_us * USEC_PER_SEC) - 1;
@ -99,7 +99,7 @@ int timer_init(tim_t dev, unsigned int ticks_per_us, void (*callback)(int))
timer_irq_enable(dev); timer_irq_enable(dev);
/* Enable the timer: */ /* Enable the timer: */
gptimer->CTLbits.TAEN = 1; gptimer->cc2538_gptimer_ctl.CTLbits.TAEN = 1;
return 0; return 0;
} }
@ -191,11 +191,11 @@ int timer_clear(tim_t dev, int channel)
switch (channel) { switch (channel) {
case 0: case 0:
gptimer->CTLbits.TAEN = 0; gptimer->cc2538_gptimer_ctl.CTLbits.TAEN = 0;
break; break;
case 1: case 1:
gptimer->CTLbits.TBEN = 0; gptimer->cc2538_gptimer_ctl.CTLbits.TBEN = 0;
break; break;
default: default:
@ -243,26 +243,26 @@ void timer_stop(tim_t dev)
switch (dev) { switch (dev) {
#if TIMER_0_EN #if TIMER_0_EN
case TIMER_0: case TIMER_0:
TIMER_0_DEV->CTLbits.TAEN = 0; TIMER_0_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 0;
TIMER_0_DEV->CTLbits.TBEN = 0; TIMER_0_DEV->cc2538_gptimer_ctl.CTLbits.TBEN = 0;
break; break;
#endif #endif
#if TIMER_1_EN #if TIMER_1_EN
case TIMER_1: case TIMER_1:
TIMER_1_DEV->CTLbits.TAEN = 0; TIMER_1_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 0;
TIMER_1_DEV->CTLbits.TBEN = 0; TIMER_1_DEV->cc2538_gptimer_ctl.CTLbits.TBEN = 0;
break; break;
#endif #endif
#if TIMER_2_EN #if TIMER_2_EN
case TIMER_2: case TIMER_2:
TIMER_2_DEV->CTLbits.TAEN = 0; TIMER_2_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 0;
TIMER_2_DEV->CTLbits.TBEN = 0; TIMER_2_DEV->cc2538_gptimer_ctl.CTLbits.TBEN = 0;
break; break;
#endif #endif
#if TIMER_3_EN #if TIMER_3_EN
case TIMER_3: case TIMER_3:
TIMER_3_DEV->CTLbits.TAEN = 0; TIMER_3_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 0;
TIMER_3_DEV->CTLbits.TBEN = 0; TIMER_3_DEV->cc2538_gptimer_ctl.CTLbits.TBEN = 0;
break; break;
#endif #endif
@ -276,26 +276,26 @@ void timer_start(tim_t dev)
switch (dev) { switch (dev) {
#if TIMER_0_EN #if TIMER_0_EN
case TIMER_0: case TIMER_0:
TIMER_0_DEV->CTLbits.TAEN = 1; TIMER_0_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 1;
TIMER_0_DEV->CTLbits.TBEN = 1; TIMER_0_DEV->cc2538_gptimer_ctl.CTLbits.TBEN = 1;
break; break;
#endif #endif
#if TIMER_1_EN #if TIMER_1_EN
case TIMER_1: case TIMER_1:
TIMER_1_DEV->CTLbits.TAEN = 1; TIMER_1_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 1;
TIMER_1_DEV->CTLbits.TBEN = 1; TIMER_1_DEV->cc2538_gptimer_ctl.CTLbits.TBEN = 1;
break; break;
#endif #endif
#if TIMER_2_EN #if TIMER_2_EN
case TIMER_2: case TIMER_2:
TIMER_2_DEV->CTLbits.TAEN = 1; TIMER_2_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 1;
TIMER_2_DEV->CTLbits.TBEN = 1; TIMER_2_DEV->cc2538_gptimer_ctl.CTLbits.TBEN = 1;
break; break;
#endif #endif
#if TIMER_3_EN #if TIMER_3_EN
case TIMER_3: case TIMER_3:
TIMER_3_DEV->CTLbits.TAEN = 1; TIMER_3_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 1;
TIMER_3_DEV->CTLbits.TBEN = 1; TIMER_3_DEV->cc2538_gptimer_ctl.CTLbits.TBEN = 1;
break; break;
#endif #endif

63
cpu/cc2538/periph/uart.c
View File

@ -77,23 +77,23 @@ cc2538_uart_t * const UART1 = (cc2538_uart_t *)0x4000d000;
static void reset(cc2538_uart_t *u) static void reset(cc2538_uart_t *u)
{ {
/* Make sure the UART is disabled before trying to configure it */ /* Make sure the UART is disabled before trying to configure it */
u->CTLbits.UARTEN = 0; u->cc2538_uart_ctl.CTLbits.UARTEN = 0;
u->CTLbits.RXE = 1; u->cc2538_uart_ctl.CTLbits.RXE = 1;
u->CTLbits.TXE = 1; u->cc2538_uart_ctl.CTLbits.TXE = 1;
u->CTLbits.HSE = UART_CTL_HSE_VALUE; u->cc2538_uart_ctl.CTLbits.HSE = UART_CTL_HSE_VALUE;
/* Clear error status */ /* Clear error status */
u->ECR = 0xFF; u->cc2538_uart_dr.ECR = 0xFF;
/* Flush FIFOs by clearing LCHR.FEN */ /* Flush FIFOs by clearing LCHR.FEN */
u->LCRHbits.FEN = 0; u->cc2538_uart_lcrh.LCRHbits.FEN = 0;
/* Restore LCHR configuration */ /* Restore LCHR configuration */
u->LCRHbits.FEN = 1; u->cc2538_uart_lcrh.LCRHbits.FEN = 1;
/* UART Enable */ /* UART Enable */
u->CTLbits.UARTEN = 1; u->cc2538_uart_ctl.CTLbits.UARTEN = 1;
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
@ -104,11 +104,11 @@ void UART_0_ISR(void)
/* Store the current MIS and clear all flags early, except the RTM flag. /* Store the current MIS and clear all flags early, except the RTM flag.
* This will clear itself when we read out the entire FIFO contents */ * This will clear itself when we read out the entire FIFO contents */
mis = UART_0_DEV->MIS; mis = UART_0_DEV->cc2538_uart_mis.MIS;
UART_0_DEV->ICR = 0x0000FFBF; UART_0_DEV->ICR = 0x0000FFBF;
while (UART_0_DEV->FRbits.RXFE == 0) { while (UART_0_DEV->cc2538_uart_fr.FRbits.RXFE == 0) {
uart_config[0].rx_cb(uart_config[0].arg, UART_0_DEV->DR); uart_config[0].rx_cb(uart_config[0].arg, UART_0_DEV->DR);
} }
@ -246,7 +246,7 @@ static int init_base(uart_t uart, uint32_t baudrate)
SYS_CTRL_DCGCUART |= (1 << uart_num); SYS_CTRL_DCGCUART |= (1 << uart_num);
/* Make sure the UART is disabled before trying to configure it */ /* Make sure the UART is disabled before trying to configure it */
u->CTL = 0; u->cc2538_uart_ctl.CTL = 0;
/* Run on SYS_DIV */ /* Run on SYS_DIV */
u->CC = 0; u->CC = 0;
@ -257,14 +257,14 @@ static int init_base(uart_t uart, uint32_t baudrate)
IOC_PXX_SEL[UART_1_RTS_PIN] = UART1_RTS; IOC_PXX_SEL[UART_1_RTS_PIN] = UART1_RTS;
gpio_hardware_control(UART_1_RTS_PIN); gpio_hardware_control(UART_1_RTS_PIN);
IOC_PXX_OVER[UART_1_RTS_PIN] = IOC_OVERRIDE_OE; IOC_PXX_OVER[UART_1_RTS_PIN] = IOC_OVERRIDE_OE;
u->CTLbits.RTSEN = 1; u->cc2538_uart_ctl.CTLbits.RTSEN = 1;
#endif #endif
#ifdef UART_1_CTS_PIN #ifdef UART_1_CTS_PIN
IOC_UARTCTS_UART1 = UART_1_CTS_PIN; IOC_UARTCTS_UART1 = UART_1_CTS_PIN;
gpio_hardware_control(UART_1_CTS_PIN); gpio_hardware_control(UART_1_CTS_PIN);
IOC_PXX_OVER[UART_1_CTS_PIN] = IOC_OVERRIDE_DIS; IOC_PXX_OVER[UART_1_CTS_PIN] = IOC_OVERRIDE_DIS;
u->CTLbits.CTSEN = 1; u->cc2538_uart_ctl.CTLbits.CTSEN = 1;
#endif #endif
} }
@ -279,20 +279,20 @@ static int init_base(uart_t uart, uint32_t baudrate)
* Acknowledge RX and RX Timeout * Acknowledge RX and RX Timeout
* Acknowledge Framing, Overrun and Break Errors * Acknowledge Framing, Overrun and Break Errors
*/ */
u->IM = 0; u->cc2538_uart_im.IM = 0;
u->IMbits.RXIM = 1; /**< UART receive interrupt mask */ u->cc2538_uart_im.IMbits.RXIM = 1; /**< UART receive interrupt mask */
u->IMbits.RTIM = 1; /**< UART receive time-out interrupt mask */ u->cc2538_uart_im.IMbits.RTIM = 1; /**< UART receive time-out interrupt mask */
u->IMbits.OEIM = 1; /**< UART overrun error interrupt mask */ u->cc2538_uart_im.IMbits.OEIM = 1; /**< UART overrun error interrupt mask */
u->IMbits.BEIM = 1; /**< UART break error interrupt mask */ u->cc2538_uart_im.IMbits.BEIM = 1; /**< UART break error interrupt mask */
u->IMbits.FEIM = 1; /**< UART framing error interrupt mask */ u->cc2538_uart_im.IMbits.FEIM = 1; /**< UART framing error interrupt mask */
/* Set FIFO interrupt levels: */ /* Set FIFO interrupt levels: */
u->IFLSbits.RXIFLSEL = FIFO_LEVEL_1_8TH; u->cc2538_uart_ifls.IFLSbits.RXIFLSEL = FIFO_LEVEL_1_8TH;
u->IFLSbits.TXIFLSEL = FIFO_LEVEL_4_8TH; u->cc2538_uart_ifls.IFLSbits.TXIFLSEL = FIFO_LEVEL_4_8TH;
u->CTLbits.RXE = 1; u->cc2538_uart_ctl.CTLbits.RXE = 1;
u->CTLbits.TXE = 1; u->cc2538_uart_ctl.CTLbits.TXE = 1;
u->CTLbits.HSE = UART_CTL_HSE_VALUE; u->cc2538_uart_ctl.CTLbits.HSE = UART_CTL_HSE_VALUE;
/* Set the divisor for the baud rate generator */ /* Set the divisor for the baud rate generator */
uint32_t divisor = sys_clock_freq(); uint32_t divisor = sys_clock_freq();
@ -303,13 +303,13 @@ static int init_base(uart_t uart, uint32_t baudrate)
u->FBRD = divisor & DIVFRAC_MASK; u->FBRD = divisor & DIVFRAC_MASK;
/* Configure line control for 8-bit, no parity, 1 stop bit and enable */ /* Configure line control for 8-bit, no parity, 1 stop bit and enable */
u->LCRH = 0; u->cc2538_uart_lcrh.LCRH = 0;
u->LCRHbits.WLEN = UART_WORD_LENGTH - 5; u->cc2538_uart_lcrh.LCRHbits.WLEN = UART_WORD_LENGTH - 5;
u->LCRHbits.FEN = 1; /**< Enable FIFOs */ u->cc2538_uart_lcrh.LCRHbits.FEN = 1; /**< Enable FIFOs */
u->LCRHbits.PEN = 0; /**< No parity */ u->cc2538_uart_lcrh.LCRHbits.PEN = 0; /**< No parity */
/* UART Enable */ /* UART Enable */
u->CTLbits.UARTEN = 1; u->cc2538_uart_ctl.CTLbits.UARTEN = 1;
return 0; return 0;
#endif /* UART_0_EN || UART_1_EN */ #endif /* UART_0_EN || UART_1_EN */
@ -336,17 +336,18 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
/* Block if the TX FIFO is full */ /* Block if the TX FIFO is full */
for (size_t i = 0; i < len; i++) { for (size_t i = 0; i < len; i++) {
while (u->FRbits.TXFF); while (u->cc2538_uart_fr.FRbits.TXFF);
u->DR = data[i]; u->DR = data[i];
} }
} }
void uart_poweron(uart_t uart) void uart_poweron(uart_t uart)
{ {
(void) uart;
} }
void uart_poweroff(uart_t uart) void uart_poweroff(uart_t uart)
{ {
(void) uart;
} }