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Merge pull request #14898 from aabadie/pr/cpu/stm32gx_clock_cleanup

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cpu/stm32gx: cleanup clock initialization
This commit is contained in:
Alexandre Abadie 2020-10-20 18:25:36 +02:00 committed by GitHub
commit 4723260b16
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GPG Key ID: 4AEE18F83AFDEB23
9 changed files with 161 additions and 135 deletions
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15
boards/common/stm32/Kconfig.g0
View File

@ -24,28 +24,25 @@ config USE_CLOCK_HSI
endchoice
if USE_CLOCK_PLL
config CLOCK_PLL_M
int "M: PLLIN division factor"
int "M: PLLIN division factor" if USE_CLOCK_PLL
default 1
range 1 8
config CLOCK_PLL_N
int "N: PLLIN multiply factor"
int "N: PLLIN multiply factor" if USE_CLOCK_PLL
default 20
range 8 86
config CLOCK_PLL_R
int "Q: VCO division factor"
int "Q: VCO division factor" if USE_CLOCK_PLL
default 6 if BOARD_HAS_HSE
default 5 if !BOARD_HAS_HSE
default 5
range 2 8
endif
choice
bool "HSISYS division factor"
bool "HSISYS division factor" if USE_CLOCK_HSI
default CLOCK_HSISYS_DIV_1
depends on USE_CLOCK_HSI
config CLOCK_HSISYS_DIV_1
bool "Divide HSISYS by 1"
@ -75,7 +72,7 @@ endchoice
config CLOCK_HSISYS_DIV
int
default 1 if CLOCK_HSISYS_DIV_1
default 1
default 2 if CLOCK_HSISYS_DIV_2
default 4 if CLOCK_HSISYS_DIV_4
default 8 if CLOCK_HSISYS_DIV_8

10
boards/common/stm32/Kconfig.g4
View File

@ -24,20 +24,19 @@ config USE_CLOCK_HSI
endchoice
if USE_CLOCK_PLL
config CLOCK_PLL_M
int "M: Division factor for the main PLL input clock"
int "M: Division factor for the main PLL input clock" if USE_CLOCK_PLL
default 6 if BOARD_HAS_HSE
default 4 if !BOARD_HAS_HSE
default 4
range 1 16
config CLOCK_PLL_N
int "N: Multiply factor for the VCO"
int "N: Multiply factor for the VCO" if USE_CLOCK_PLL
default 40
range 8 127
choice
bool "R: Main PLL division factor for PLL 'R' clock (system clock)"
bool "R: Main PLL division factor for PLL 'R' clock (system clock)" if USE_CLOCK_PLL
default PLL_R_DIV_2
config PLL_R_DIV_2
@ -60,7 +59,6 @@ config CLOCK_PLL_R
default 4 if PLL_R_DIV_4
default 6 if PLL_R_DIV_6
default 8 if PLL_R_DIV_8
endif
choice
bool "APB1 prescaler (division factor of HCLK to produce PCLK1)"

53
boards/common/stm32/include/g0/cfg_clock_default.h
View File

@ -37,50 +37,50 @@ extern "C" {
/* Select the desired system clock source between PLL, HSE or HSI */
#ifndef CONFIG_USE_CLOCK_PLL
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#define CONFIG_USE_CLOCK_PLL (0)
#define CONFIG_USE_CLOCK_PLL 0
#else
#define CONFIG_USE_CLOCK_PLL (1) /* Use PLL by default */
#define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */
#endif
#endif /* CONFIG_USE_CLOCK_PLL */
#ifndef CONFIG_USE_CLOCK_HSE
#define CONFIG_USE_CLOCK_HSE (0)
#define CONFIG_USE_CLOCK_HSE 0
#endif /* CONFIG_USE_CLOCK_HSE */
#ifndef CONFIG_USE_CLOCK_HSI
#define CONFIG_USE_CLOCK_HSI (0)
#define CONFIG_USE_CLOCK_HSI 0
#endif /* CONFIG_USE_CLOCK_HSI */
#if CONFIG_USE_CLOCK_PLL && \
(CONFIG_USE_CLOCK_HSE || CONFIG_USE_CLOCK_HSI)
#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
#error "Cannot use PLL as clock source with other clock configurations"
#endif
#if CONFIG_USE_CLOCK_HSE && \
(CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_HSI)
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
#error "Cannot use HSE as clock source with other clock configurations"
#endif
#if CONFIG_USE_CLOCK_HSI && \
(CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_HSE)
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE))
#error "Cannot use HSI as clock source with other clock configurations"
#endif
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE (0)
#define CONFIG_BOARD_HAS_HSE 0
#endif
#ifndef CLOCK_HSE
#define CLOCK_HSE MHZ(24)
#endif
#if CONFIG_BOARD_HAS_HSE && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48))
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48))
#error "HSE clock frequency must be between 4MHz and 48MHz"
#endif
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE (0)
#define CONFIG_BOARD_HAS_LSE 0
#endif
#if CONFIG_BOARD_HAS_LSE
#if IS_ACTIVE(CONFIG_BOARD_HAS_LSE)
#define CLOCK_LSE (1)
#else
#define CLOCK_LSE (0)
@ -88,19 +88,16 @@ extern "C" {
#define CLOCK_HSI MHZ(16)
#if CONFIG_USE_CLOCK_HSI
#ifndef CONFIG_CLOCK_HSISYS_DIV
#define CONFIG_CLOCK_HSISYS_DIV (1)
#endif
#define CLOCK_CORECLOCK (CLOCK_HSI / CONFIG_CLOCK_HSISYS_DIV)
#elif CONFIG_USE_CLOCK_HSE
#if CONFIG_BOARD_HAS_HSE == 0
#error "The board doesn't provide an HSE oscillator"
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#define CLOCK_PLL_SRC (CLOCK_HSE)
#else /* CLOCK_HSI */
#define CLOCK_PLL_SRC (CLOCK_HSI)
#endif
#define CLOCK_CORECLOCK (CLOCK_HSE)
#elif CONFIG_USE_CLOCK_PLL
/* The following parameters configure a 64MHz system clock with HSI as input clock */
#ifndef CONFIG_CLOCK_PLL_M
#define CONFIG_CLOCK_PLL_M (1)
@ -111,11 +108,17 @@ extern "C" {
#ifndef CONFIG_CLOCK_PLL_R
#define CONFIG_CLOCK_PLL_R (5)
#endif
#if CONFIG_BOARD_HAS_HSE
#define CLOCK_PLL_SRC (CLOCK_HSE)
#else /* CLOCK_HSI */
#define CLOCK_PLL_SRC (CLOCK_HSI)
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#define CLOCK_CORECLOCK (CLOCK_HSI / CONFIG_CLOCK_HSISYS_DIV)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#error "The board doesn't provide an HSE oscillator"
#endif
#define CLOCK_CORECLOCK (CLOCK_HSE)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
#define CLOCK_CORECLOCK \
((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_R
#if CLOCK_CORECLOCK > MHZ(64)

58
boards/common/stm32/include/g4/cfg_clock_default.h
View File

@ -31,49 +31,49 @@ extern "C" {
*/
#ifndef CONFIG_USE_CLOCK_PLL
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#define CONFIG_USE_CLOCK_PLL (0)
#define CONFIG_USE_CLOCK_PLL 0
#else
#define CONFIG_USE_CLOCK_PLL (1) /* Use PLL by default */
#define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */
#endif
#endif /* CONFIG_USE_CLOCK_PLL */
#ifndef CONFIG_USE_CLOCK_HSE
#define CONFIG_USE_CLOCK_HSE (0)
#define CONFIG_USE_CLOCK_HSE 0
#endif /* CONFIG_USE_CLOCK_HSE */
#ifndef CONFIG_USE_CLOCK_HSI
#define CONFIG_USE_CLOCK_HSI (0)
#define CONFIG_USE_CLOCK_HSI 0
#endif /* CONFIG_USE_CLOCK_HSI */
#if CONFIG_USE_CLOCK_PLL && \
(CONFIG_USE_CLOCK_HSE || CONFIG_USE_CLOCK_HSI)
#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
#error "Cannot use PLL as clock source with other clock configurations"
#endif
#if CONFIG_USE_CLOCK_HSE && \
(CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_HSI)
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI))
#error "Cannot use HSE as clock source with other clock configurations"
#endif
#if CONFIG_USE_CLOCK_HSI && \
(CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_HSE)
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && \
(IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE))
#error "Cannot use HSI as clock source with other clock configurations"
#endif
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE (0)
#define CONFIG_BOARD_HAS_HSE 0
#endif
#ifndef CLOCK_HSE
#define CLOCK_HSE MHZ(24)
#endif
#if CONFIG_BOARD_HAS_HSE && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48))
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48))
#error "HSE clock frequency must be between 4MHz and 48MHz"
#endif
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE (0)
#define CONFIG_BOARD_HAS_LSE 0
#endif
#if CONFIG_BOARD_HAS_LSE
#if IS_ACTIVE(CONFIG_BOARD_HAS_LSE)
#define CLOCK_LSE (1)
#else
#define CLOCK_LSE (0)
@ -81,16 +81,12 @@ extern "C" {
#define CLOCK_HSI MHZ(16)
#if CONFIG_USE_CLOCK_HSI
#define CLOCK_CORECLOCK (CLOCK_HSI)
#elif CONFIG_USE_CLOCK_HSE
#if CONFIG_BOARD_HAS_HSE == 0
#error "The board doesn't provide an HSE oscillator"
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#define CLOCK_PLL_SRC (CLOCK_HSE)
#else /* CLOCK_HSI */
#define CLOCK_PLL_SRC (CLOCK_HSI)
#endif
#define CLOCK_CORECLOCK (CLOCK_HSE)
#elif CONFIG_USE_CLOCK_PLL
/* The following parameters configure a 170MHz system clock with HSI16 as input clock */
#ifndef CONFIG_CLOCK_PLL_M
#define CONFIG_CLOCK_PLL_M (4)
@ -101,11 +97,17 @@ extern "C" {
#ifndef CONFIG_CLOCK_PLL_R
#define CONFIG_CLOCK_PLL_R (2)
#endif
#if CONFIG_BOARD_HAS_HSE
#define CLOCK_PLL_SRC (CLOCK_HSE)
#else /* CLOCK_HSI */
#define CLOCK_PLL_SRC (CLOCK_HSI)
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
#define CLOCK_CORECLOCK (CLOCK_HSI)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#error "The board doesn't provide an HSE oscillator"
#endif
#define CLOCK_CORECLOCK (CLOCK_HSE)
#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
#define CLOCK_CORECLOCK \
((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_R
#if CLOCK_CORECLOCK > MHZ(170)
@ -118,11 +120,11 @@ extern "C" {
#ifndef CONFIG_CLOCK_APB1_DIV
#define CONFIG_CLOCK_APB1_DIV (1)
#endif
#define CLOCK_APB1 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV) /* max: 170MHz */
#define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* max: 170MHz */
#ifndef CONFIG_CLOCK_APB2_DIV
#define CONFIG_CLOCK_APB2_DIV (1)
#endif
#define CLOCK_APB2 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB2_DIV) /* max: 170MHz */
#define CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* max: 170MHz */
#ifdef __cplusplus
}

2
boards/nucleo-g070rb/include/periph_conf.h
View File

@ -23,7 +23,7 @@
/* Add specific clock configuration (HSE, LSE) for this board here */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE (1)
#define CONFIG_BOARD_HAS_LSE 1
#endif
#include "g0/cfg_clock_default.h"

2
boards/nucleo-g071rb/include/periph_conf.h
View File

@ -21,7 +21,7 @@
/* Add specific clock configuration (HSE, LSE) for this board here */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE (1)
#define CONFIG_BOARD_HAS_LSE 1
#endif
#include "g0/cfg_clock_default.h"

4
boards/nucleo-g431rb/include/periph_conf.h
View File

@ -21,11 +21,11 @@
/* Add specific clock configuration (HSE, LSE) for this board here */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE (1)
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides a 24MHz HSE oscillator */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE (1)
#define CONFIG_BOARD_HAS_HSE 1
#endif
/* By default, configure a 170MHz SYSCLK with PLL using HSE as input clock */
#ifndef CONFIG_CLOCK_PLL_M

4
boards/nucleo-g474re/include/periph_conf.h
View File

@ -21,11 +21,11 @@
/* Add specific clock configuration (HSE, LSE) for this board here */
#ifndef CONFIG_BOARD_HAS_LSE
#define CONFIG_BOARD_HAS_LSE (1)
#define CONFIG_BOARD_HAS_LSE 1
#endif
/* This board provides a 24MHz HSE oscillator */
#ifndef CONFIG_BOARD_HAS_HSE
#define CONFIG_BOARD_HAS_HSE (1)
#define CONFIG_BOARD_HAS_HSE 1
#endif
/* By default, configure a 80MHz SYSCLK with PLL using HSE as input clock */
#ifndef CONFIG_CLOCK_PLL_M

148
cpu/stm32/stmclk/stmclk_gx.c
View File

@ -37,7 +37,6 @@
#define PLL_R_MAX (8)
#endif
#if CONFIG_USE_CLOCK_PLL
#if (CONFIG_CLOCK_PLL_M < PLL_M_MIN || CONFIG_CLOCK_PLL_M > PLL_M_MAX)
#error "PLL configuration: PLL M value is out of range"
#endif
@ -58,7 +57,7 @@
#define PLL_R (((CONFIG_CLOCK_PLL_R >> 1) - 1) << RCC_PLLCFGR_PLLR_Pos)
#endif
#if CONFIG_BOARD_HAS_HSE
#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
#define PLL_IN CLOCK_HSE
#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE
#else
@ -66,14 +65,11 @@
#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSI
#endif
#endif /* CONFIG_USE_CLOCK_PLL */
#if defined(CPU_FAM_STM32G0)
#define RCC_CFGR_SW_HSI (0)
#define RCC_CFGR_SW_HSE (RCC_CFGR_SW_0)
#define RCC_CFGR_SW_PLL (RCC_CFGR_SW_1)
#if CONFIG_USE_CLOCK_HSI
#if CONFIG_CLOCK_HSISYS_DIV == 1
#define CLOCK_HSI_DIV (0)
#elif CONFIG_CLOCK_HSISYS_DIV == 2
@ -91,7 +87,6 @@
#elif CONFIG_CLOCK_HSISYS_DIV == 128
#define CLOCK_HSI_DIV (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_1 | RCC_CR_HSIDIV_0)
#endif
#endif /* CONFIG_USE_CLOCK_HSI */
#define CLOCK_AHB_DIV (0)
@ -136,6 +131,40 @@
#endif
#endif /* CPU_FAM_STM32G4 */
/* Check whether PLL must be enabled:
- When PLLCLK is used as SYSCLK
*/
#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
#define CLOCK_ENABLE_PLL 1
#else
#define CLOCK_ENABLE_PLL 0
#endif
/* Check whether HSE is required:
- When HSE is used as SYSCLK
- When PLL is used as SYSCLK and the board provides HSE (since HSE will be
used as PLL input clock)
*/
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || \
(IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && IS_ACTIVE(CONFIG_USE_CLOCK_PLL))
#define CLOCK_ENABLE_HSE 1
#else
#define CLOCK_ENABLE_HSE 0
#endif
/* Check whether HSI is required:
- When HSI is used as SYSCLK
- When PLL is used as SYSCLK and the board doesn't provide HSE (since HSI will be
used as PLL input clock)
*/
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) || \
(!IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && IS_ACTIVE(CONFIG_USE_CLOCK_PLL))
#define CLOCK_ENABLE_HSI 1
#else
#define CLOCK_ENABLE_HSI 0
#endif
/** Determine the required flash wait states from the core clock frequency */
#if defined(CPU_FAM_STM32G0)
#if CLOCK_CORECLOCK >= 48000000
@ -191,73 +220,70 @@ void stmclk_init_sysclk(void)
/* disable all active clocks except HSI -> resets the clk configuration */
RCC->CR = RCC_CR_HSION;
#if CLOCK_LSE
stmclk_enable_lfclk();
#endif
#if CONFIG_USE_CLOCK_HSI && defined(CPU_FAM_STM32G0)
/* configure HSISYS divider, only available on G0 */
RCC->CR |= CLOCK_HSI_DIV;
while (!(RCC->CR & RCC_CR_HSIRDY)) {}
#elif CONFIG_USE_CLOCK_HSE
/* if configured, we need to enable the HSE clock now */
RCC->CR |= RCC_CR_HSEON;
while (!(RCC->CR & RCC_CR_HSERDY)) {}
#if defined(CPU_FAM_STM32G0)
RCC->CFGR = (RCC_CFGR_SW_HSE | CLOCK_AHB_DIV | CLOCK_APB1_DIV);
if (IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && CONFIG_CLOCK_HSISYS_DIV != 1) {
/* configure HSISYS divider, only available on G0 */
RCC->CR |= CLOCK_HSI_DIV;
while (!(RCC->CR & RCC_CR_HSIRDY)) {}
}
#endif
/* Enable HSE if required */
if (IS_ACTIVE(CLOCK_ENABLE_HSE)) {
RCC->CR |= RCC_CR_HSEON;
while (!(RCC->CR & RCC_CR_HSERDY)) {}
}
/* Enable PLL if required */
if (IS_ACTIVE(CLOCK_ENABLE_PLL)) {
RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_R | RCC_PLLCFGR_PLLREN);
RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY)) {}
}
/* Configure SYSCLK */
if (IS_ACTIVE(CONFIG_USE_CLOCK_HSE)) {
#if defined(CPU_FAM_STM32G0)
RCC->CFGR = (RCC_CFGR_SW_HSE | CLOCK_AHB_DIV | CLOCK_APB1_DIV);
#elif defined(CPU_FAM_STM32G4)
RCC->CFGR = (RCC_CFGR_SW_HSE | CLOCK_AHB_DIV | CLOCK_APB1_DIV | CLOCK_APB2_DIV);
RCC->CFGR = (RCC_CFGR_SW_HSE | CLOCK_AHB_DIV | CLOCK_APB1_DIV | CLOCK_APB2_DIV);
#endif
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSE) {}
#elif CONFIG_USE_CLOCK_PLL
#if CONFIG_BOARD_HAS_HSE
/* if configured, we need to enable the HSE clock now */
RCC->CR |= RCC_CR_HSEON;
while (!(RCC->CR & RCC_CR_HSERDY)) {}
#endif
/* now we can safely configure and start the PLL */
RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_R | RCC_PLLCFGR_PLLREN);
RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY)) {}
#if CLOCK_AHB > MHZ(80)
/* Divide HCLK by before enabling the PLL */
RCC->CFGR |= RCC_CFGR_HPRE_DIV2;
RCC->CFGR |= RCC_CFGR_SW_HSE;
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSE) {}
}
else if (IS_ACTIVE(CONFIG_USE_CLOCK_PLL)) {
#if defined(CPU_FAM_STM32G4)
if (CLOCK_AHB > MHZ(80)) {
/* Divide HCLK by 2 before enabling the PLL */
RCC->CFGR |= RCC_CFGR_HPRE_DIV2;
}
#endif
/* now that the PLL is running, we use it as system clock */
RCC->CFGR |= RCC_CFGR_SW_PLL;
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {}
/* now that the PLL is running, we use it as system clock */
RCC->CFGR |= RCC_CFGR_SW_PLL;
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {}
#if CLOCK_AHB > MHZ(80)
/* Wait 1us before switching back to full speed */
/* Use volatile to prevent the compiler from optimizing the loop */
volatile uint8_t count = CLOCK_CORECLOCK / MHZ(1);
while (count--) {}
RCC->CFGR &= ~RCC_CFGR_HPRE_DIV2;
#if defined(CPU_FAM_STM32G4)
if (CLOCK_AHB > MHZ(80)) {
/* Wait 1us before switching back to full speed */
/* Use volatile to prevent the compiler from optimizing the loop */
volatile uint8_t count = CLOCK_CORECLOCK / MHZ(1);
while (count--) {}
RCC->CFGR &= ~RCC_CFGR_HPRE_DIV2;
}
#endif
}
#endif
if (!IS_ACTIVE(CLOCK_ENABLE_HSI)) {
/* Disable HSI only if not used */
stmclk_disable_hsi();
}
stmclk_disable_hsi();
irq_restore(is);
#ifdef MODULE_PERIPH_HWRNG
#if IS_USED(MODULE_PERIPH_HWRNG)
/* HWRNG is clocked by HSI48 so enable this clock when the peripheral is used */
RCC->CRRCR |= RCC_CRRCR_HSI48ON;
while (!(RCC->CRRCR & RCC_CRRCR_HSI48RDY)) {}
#endif
#ifdef MODULE_PERIPH_RTT
/* Ensure LPTIM1 clock source (LSI or LSE) is correctly reset when initializing
the clock, this is particularly useful after waking up from deep sleep */
#if CLOCK_LSE
RCC->CCIPR |= RCC_CCIPR_LPTIM1SEL_0 | RCC_CCIPR_LPTIM1SEL_1;
#else
RCC->CCIPR |= RCC_CCIPR_LPTIM1SEL_0;
#endif /* CLOCK_LSE */
#endif /* MODULE_PERIPH_RTT */
irq_restore(is);
}