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boards: fix CLOCK_PLL_PREDIV on stm32f1xx boards

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This commit is contained in:
Vincent Dupont 2018-01-23 11:49:42 +01:00
parent 21bbfbed1d
commit 4647659ea8
4 changed files with 91 additions and 111 deletions
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47
boards/fox/include/periph_conf.h
View File

@ -26,37 +26,32 @@ extern "C" {
#endif
/**
* @name Clock system configuration
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
**/
/* high speed clock configuration:
* 0 := use internal HSI oscillator (always 8MHz)
* HSE frequency value := use external HSE oscillator with given freq [in Hz]
* must be 4000000 <= value <= 16000000 */
#define CLOCK_HSE (16000000U)
/* low speed clock configuration:
* 0 := use internal LSI oscillator (~40kHz)
* 1 := use extern LSE oscillator, always 32.768kHz */
#define CLOCK_LSE (1)
/* targeted system clock speed [in Hz], must be <= 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* PLL configuration, set both values to zero to disable PLL usage. The values
* must be set to satisfy the following equation:
* CORECLOCK := CLOCK_SOURCE / PLL_DIV * PLL_MUL
* with
* 1 <= CLOCK_PLL_DIV <= 2
* 2 <= CLOCK_PLL_MUL <= 17 */
#define CLOCK_PLL_DIV (2)
#define CLOCK_PLL_MUL (9)
/* AHB and APBx bus clock configuration, keep in mind the following constraints:
* ABP1 <= 36MHz
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (16000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1U)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (2)
#define CLOCK_PLL_MUL (9)
/** @} */
/**

47
boards/maple-mini/include/periph_conf.h
View File

@ -26,37 +26,32 @@ extern "C" {
#endif
/**
* @name Clock system configuration
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
**/
/* high speed clock configuration:
* 0 := use internal HSI oscillator (always 8MHz)
* HSE frequency value := use external HSE oscillator with given freq [in Hz]
* must be 4000000 <= value <= 16000000 */
#define CLOCK_HSE (8000000U)
/* low speed clock configuration:
* 0 := use internal LSI oscillator (~40kHz)
* 1 := use extern LSE oscillator, always 32.768kHz */
#define CLOCK_LSE (0)
/* targeted system clock speed [in Hz], must be <= 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* PLL configuration, set both values to zero to disable PLL usage. The values
* must be set to satisfy the following equation:
* CORECLOCK := CLOCK_SOURCE / PLL_DIV * PLL_MUL
* with
* 1 <= CLOCK_PLL_DIV <= 2
* 2 <= CLOCK_PLL_MUL <= 17 */
#define CLOCK_PLL_DIV (1)
#define CLOCK_PLL_MUL (9)
/* AHB and APBx bus clock configuration, keep in mind the following constraints:
* ABP1 <= 36MHz
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (0U)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (9)
/** @} */
/**

47
boards/opencm904/include/periph_conf.h
View File

@ -26,37 +26,32 @@ extern "C" {
#endif
/**
* @name Clock system configuration
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
**/
/* high speed clock configuration:
* 0 := use internal HSI oscillator (always 8MHz)
* HSE frequency value := use external HSE oscillator with given freq [in Hz]
* must be 4000000 <= value <= 16000000 */
#define CLOCK_HSE (8000000U)
/* low speed clock configuration:
* 0 := use internal LSI oscillator (~40kHz)
* 1 := use extern LSE oscillator, always 32.768kHz */
#define CLOCK_LSE (0)
/* targeted system clock speed [in Hz], must be <= 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* PLL configuration, set both values to zero to disable PLL usage. The values
* must be set to satisfy the following equation:
* CORECLOCK := CLOCK_SOURCE / PLL_DIV * PLL_MUL
* with
* 1 <= CLOCK_PLL_DIV <= 2
* 2 <= CLOCK_PLL_MUL <= 17 */
#define CLOCK_PLL_DIV (1)
#define CLOCK_PLL_MUL (9)
/* AHB and APBx bus clock configuration, keep in mind the following constraints:
* ABP1 <= 36MHz
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (0U)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (9)
/** @} */
/**

61
boards/spark-core/include/periph_conf.h
View File

@ -25,39 +25,34 @@
extern "C" {
#endif
/**
* @name Clock system configuration
* @{
**/
/* high speed clock configuration:
* 0 := use internal HSI oscillator (always 8MHz)
* HSE frequency value := use external HSE oscillator with given freq [in Hz]
* must be 4000000 <= value <= 16000000 */
#define CLOCK_HSE (8000000U)
/* low speed clock configuration:
* 0 := use internal LSI oscillator (~40kHz)
* 1 := use extern LSE oscillator, always 32.768kHz */
#define CLOCK_LSE (0)
/* targeted system clock speed [in Hz], must be <= 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* PLL configuration, set both values to zero to disable PLL usage. The values
* must be set to satisfy the following equation:
* CORECLOCK := CLOCK_SOURCE / PLL_DIV * PLL_MUL
* with
* 1 <= CLOCK_PLL_DIV <= 2
* 2 <= CLOCK_PLL_MUL <= 17 */
#define CLOCK_PLL_DIV (1)
#define CLOCK_PLL_MUL (9)
/* AHB and APBx bus clock configuration, keep in mind the following constraints:
* ABP1 <= 36MHz
*/
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
/** @} */
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 72MHz */
#define CLOCK_CORECLOCK (72000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (0U)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
/* PLL factors */
#define CLOCK_PLL_PREDIV (1)
#define CLOCK_PLL_MUL (9)
/** @} */
/**
* @name Timer configuration