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Merge pull request #6207 from haukepetersen/opt_sam3_pwm
cpu/sam3: reworked PWM driver
This commit is contained in:
Peter Kietzmann
GitHub
commit
4520d87121
@ -112,34 +112,18 @@ static const uart_conf_t uart_config[] = {
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/** @} */
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/** @} */
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/**
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/**
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* @name PWM configuration
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* @brief PWM configuration
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* @{
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* @{
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*/
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*/
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#define PWM_NUMOF (1U)
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static const pwm_chan_conf_t pwm_chan[] = {
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#define PWM_0_EN (1)
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{ .pin = GPIO_PIN(PC, 21), .hwchan = 4, },
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#define PWM_MAX_VALUE (0xffff)
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{ .pin = GPIO_PIN(PC, 22), .hwchan = 5, },
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#define PWM_MAX_CHANNELS (4U)
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{ .pin = GPIO_PIN(PC, 23), .hwchan = 6, },
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{ .pin = GPIO_PIN(PC, 24), .hwchan = 7, }
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};
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/* PWM_0 configuration */
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#define PWM_NUMOF (1U)
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#define PWM_0_DEV PWM
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#define PWM_CHAN_NUMOF (sizeof(pwm_chan) / sizeof(pwm_chan[0]))
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#define PWM_0_PID ID_PWM
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#define PWM_0_CHANNELS (4U)
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#define PWM_0_DEV_CH0 (&(PWM_0_DEV->PWM_CH_NUM[4]))
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#define PWM_0_ENA_CH0 PWM_ENA_CHID4
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#define PWM_0_PORT_CH0 PIOC
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#define PWM_0_PIN_CH0 PIO_PC21B_PWML4
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#define PWM_0_DEV_CH1 (&(PWM_0_DEV->PWM_CH_NUM[5]))
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#define PWM_0_ENA_CH1 PWM_ENA_CHID5
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#define PWM_0_PORT_CH1 PIOC
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#define PWM_0_PIN_CH1 PIO_PC22B_PWML5
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#define PWM_0_DEV_CH2 (&(PWM_0_DEV->PWM_CH_NUM[6]))
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#define PWM_0_ENA_CH2 PWM_ENA_CHID6
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#define PWM_0_PORT_CH2 PIOC
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#define PWM_0_PIN_CH2 PIO_PC23B_PWML6
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#define PWM_0_DEV_CH3 (&(PWM_0_DEV->PWM_CH_NUM[7]))
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#define PWM_0_ENA_CH3 PWM_ENA_CHID7
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#define PWM_0_PORT_CH3 PIOC
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#define PWM_0_PIN_CH3 PIO_PC24B_PWML7
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/** @} */
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/** @} */
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#ifdef __cplusplus
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#ifdef __cplusplus
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@ -149,6 +149,22 @@ typedef struct {
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uint8_t irqn; /**< interrupt number of the device */
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uint8_t irqn; /**< interrupt number of the device */
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} uart_conf_t;
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} uart_conf_t;
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/**
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* @brief PWM channel configuration data
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*/
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typedef struct {
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gpio_t pin; /**< GPIO pin connected to the channel */
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uint8_t hwchan; /**< the HW channel used for a logical channel */
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} pwm_chan_conf_t;
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/**
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* @brief Configure the given GPIO pin to be used with the given MUX setting
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*
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* @param[in] pin GPIO pin to configure
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* @param[in] mux MUX setting to use
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*/
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void gpio_init_mux(gpio_t pin, gpio_mux_t mux);
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#ifdef __cplusplus
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#ifdef __cplusplus
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}
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}
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#endif
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#endif
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@ -242,6 +242,17 @@ int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
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return 0;
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return 0;
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}
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}
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void gpio_init_mux(gpio_t pin, gpio_mux_t mux)
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{
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/* power on the corresponding port */
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PMC->PMC_PCER0 = (1 << (_port_num(pin) + 11));
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/* give peripheral control over the pin */
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_port(pin)->PIO_PDR = (1 << _pin_num(pin));
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/* and configure the MUX */
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_port(pin)->PIO_ABSR &= ~(1 << _pin_num(pin));
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_port(pin)->PIO_ABSR |= (mux << _pin_num(pin));
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}
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void gpio_irq_enable(gpio_t pin)
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void gpio_irq_enable(gpio_t pin)
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{
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{
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NVIC_EnableIRQ((1 << (_port_num(pin) + PIOA_IRQn)));
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NVIC_EnableIRQ((1 << (_port_num(pin) + PIOA_IRQn)));
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@ -1,9 +1,10 @@
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/*
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/*
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* Copyright (C) 2015 Hamburg University of Applied Sciences
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* Copyright (C) 2015 Hamburg University of Applied Sciences
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* 2016 Freie Universität Berlin
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*
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* This file is subject to the terms and conditions of the GNU Lesser
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* General Public License v2.1. See the file LICENSE in the top level
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* details.
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* directory for more details.
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*/
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*/
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/**
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/**
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@ -13,268 +14,135 @@
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* @file
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* @file
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* @brief CPU specific low-level PWM driver implementation for the SAM3X8E
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* @brief CPU specific low-level PWM driver implementation for the SAM3X8E
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*
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*
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* The SAM3 has only support for a single PWM device, so we accept only
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* PWM_DEV(0) for this driver.
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*
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* @author Andreas "Paul" Pauli <andreas.pauli@haw-hamburg.de>
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* @author Andreas "Paul" Pauli <andreas.pauli@haw-hamburg.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*
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*
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* @}
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* @}
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*/
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*/
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#include <stdint.h>
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#include "board.h"
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#include "cpu.h"
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#include "periph_conf.h"
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#include "assert.h"
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#include "periph/pwm.h"
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#include "periph/gpio.h"
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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/* guard file in case no PWM device is defined */
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/* guard file in case no PWM device is defined */
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#if (PWM_0_EN || PWM_1_EN)
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#if defined(PWM_NUMOF) && defined(PWM_CHAN_NUMOF)
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/* pull the PWM header inside the guards for now. Guards will be removed on
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#define PREA_MAX (10U)
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* adapting this driver implementation... */
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#include "periph/pwm.h"
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#define MCK_DIV_LB_MAX (10U)
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static uint16_t pwm_period;
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static uint8_t pwm_chan_mask;
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uint32_t pwm_init(pwm_t dev, pwm_mode_t mode, uint32_t freq, uint16_t res)
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uint32_t pwm_init(pwm_t dev, pwm_mode_t mode, uint32_t freq, uint16_t res)
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{
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{
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uint32_t pwm_clk = 0; /* Desired/real pwm_clock */
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uint32_t pwm_clk = freq * res; /* Desired/real pwm_clock */
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uint32_t diva = 1; /* Candidate for 8bit divider */
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uint32_t diva = 1; /* Candidate for 8bit divider */
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uint32_t prea = 0; /* Candidate for clock select */
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uint32_t prea = 0; /* Candidate for clock select */
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if (dev != PWM_0) {
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/* check for valid device and mode (left-aligned PWM only so far) */
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if ((dev != PWM_DEV(0)) || (mode != PWM_LEFT)) {
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return 0;
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return 0;
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}
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}
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/*
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/* check if target frequency and resolution is applicable */
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* Mode check.
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if (pwm_clk > CLOCK_CORECLOCK) {
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* Only PW_LEFT -which is hw default- supported for now.
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return 0;
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}
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/* calculate pre-scalers for targeted frequency and resolution:
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* clk = CORECLOCK / (2 ^ prea) / diva
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* width prea := [0, 10] and diva [1, 255]
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*/
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*/
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switch (mode) {
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while ((diva = (CLOCK_CORECLOCK / pwm_clk / (1 << prea))) > 255) {
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case PWM_LEFT:
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++prea;
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break;
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}
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/* make sure PREA does not exceed its limit */
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case PWM_RIGHT:
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if (prea > PREA_MAX) {
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case PWM_CENTER:
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return 0;
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default:
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return 0;
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}
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}
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/* Should check if "|log_2 frequency|+|log_2 resolution| <= 32" */
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/* activate PWM block by enabling it's clock. */
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pwm_clk = freq * res;
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/*
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* The pwm provides 11 prescaled clocks with (MCK/2^prea | prea=[0,10])
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* and a divider (diva) with a denominator range [1,255] in line.
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*/
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if (CLOCK_CORECLOCK < pwm_clk) { /* Have to cut down resulting frequency. */
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freq = CLOCK_CORECLOCK / res;
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}
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else { /* Estimate prescaler and divider. */
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diva = CLOCK_CORECLOCK / pwm_clk;
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while ((prea < MCK_DIV_LB_MAX) && (~0xff & diva)) {
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prea = prea + 1;
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diva = diva >> 1;
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}
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freq = CLOCK_CORECLOCK / ((res * diva) << prea);
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}
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/* Activate PWM block by enabling it's clock. */
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PMC->PMC_PCER1 = PMC_PCER1_PID36;
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PMC->PMC_PCER1 = PMC_PCER1_PID36;
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/* disable all channels to allow CPRD updates. */
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PWM->PWM_DIS = 0xff;
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/* configure clock generator */
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PWM->PWM_CLK = PWM_CLK_PREA(prea) | PWM_CLK_DIVA(diva);
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/* remember the used resolution (for cropping inputs later) */
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pwm_period = res - 1;
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/* Unlock User Interface */
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/* setup the configured channels */
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PWM_0_DEV->PWM_WPCR = PWM_ENA_CHID0;
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pwm_chan_mask = 0;
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for (unsigned i = 0; i < PWM_CHAN_NUMOF; i++) {
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/* configure the use pin */
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gpio_init_mux(pwm_chan[i].pin, GPIO_MUX_B);
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/* and setup the channel */
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pwm_chan_mask |= (1 << pwm_chan[i].hwchan);
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PWM->PWM_CH_NUM[pwm_chan[i].hwchan].PWM_CMR = PWM_CMR_CPRE_CLKA;
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PWM->PWM_CH_NUM[pwm_chan[i].hwchan].PWM_CPRD = pwm_period;
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PWM->PWM_CH_NUM[pwm_chan[i].hwchan].PWM_CDTY = 0;
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}
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/* Disable all channels to allow CPRD updates. */
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/* enable all configured channels */
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PWM_0_DEV->PWM_DIS = 0xff;
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PWM->PWM_ENA = pwm_chan_mask;
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/* Step 2. Configure clock generator */
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/* and return the actual configured frequency */
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PWM_0_DEV->PWM_CLK = PWM_CLK_PREA(prea) | PWM_CLK_DIVA(diva) |
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return (CLOCK_CORECLOCK / (1 << prea) / diva / res);
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(~(PWM_CLK_PREA_Msk | PWM_CLK_DIVA_Msk) &
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PWM_0_DEV->PWM_CLK);
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/* +++++++++++ Configure and init channels +++++++++++++++ */
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/* Set clock source, resolution, duty-cycle and enable */
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#if PWM_0_CHANNELS > 0
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PWM_0_DEV_CH0->PWM_CMR = PWM_CMR_CPRE_CLKA;
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PWM_0_DEV_CH0->PWM_CPRD = res - 1;
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PWM_0_DEV_CH0->PWM_CDTY = 0;
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PWM_0_DEV->PWM_ENA = PWM_0_ENA_CH0;
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#endif
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#if PWM_0_CHANNELS > 1
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PWM_0_DEV_CH1->PWM_CMR = PWM_CMR_CPRE_CLKA;
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PWM_0_DEV_CH1->PWM_CPRD = res - 1;
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PWM_0_DEV_CH1->PWM_CDTY = 0;
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PWM_0_DEV->PWM_ENA = PWM_0_ENA_CH1;
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#endif
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#if PWM_0_CHANNELS > 2
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PWM_0_DEV_CH2->PWM_CMR = PWM_CMR_CPRE_CLKA;
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PWM_0_DEV_CH2->PWM_CPRD = res - 1;
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PWM_0_DEV_CH2->PWM_CDTY = 0;
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PWM_0_DEV->PWM_ENA = PWM_0_ENA_CH2;
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#endif
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#if PWM_0_CHANNELS > 3
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PWM_0_DEV_CH3->PWM_CMR = PWM_CMR_CPRE_CLKA;
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PWM_0_DEV_CH3->PWM_CPRD = res - 1;
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PWM_0_DEV_CH3->PWM_CDTY = 0;
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PWM_0_DEV->PWM_ENA = PWM_0_ENA_CH3;
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#endif
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/* +++++++++++ Configure and init channels ready++++++++++ */
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/*
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* Disable GPIO and set peripheral A/B ("0/1") for pwm channel pins.
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*/
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#if PWM_0_CHANNELS > 0
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PWM_0_PORT_CH0->PIO_PDR |= PWM_0_PIN_CH0;
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PWM_0_PORT_CH0->PIO_ABSR |= PWM_0_PIN_CH0;
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#endif
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#if PWM_0_CHANNELS > 1
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PWM_0_PORT_CH1->PIO_PDR |= PWM_0_PIN_CH1;
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PWM_0_PORT_CH1->PIO_ABSR |= PWM_0_PIN_CH1;
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#endif
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#if PWM_0_CHANNELS > 2
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PWM_0_PORT_CH2->PIO_PDR |= PWM_0_PIN_CH2;
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PWM_0_PORT_CH2->PIO_ABSR |= PWM_0_PIN_CH2;
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#endif
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#if PWM_0_CHANNELS > 3
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PWM_0_PORT_CH3->PIO_PDR |= PWM_0_PIN_CH3;
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PWM_0_PORT_CH3->PIO_ABSR |= PWM_0_PIN_CH3;
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#endif
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return freq;
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}
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}
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uint8_t pwm_channels(pwm_t dev)
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uint8_t pwm_channels(pwm_t pwm)
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{
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{
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if (dev == 0) {
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assert(pwm == PWM_DEV(0));
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return PWM_0_CHANNELS;
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return (uint8_t)PWM_CHAN_NUMOF;
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}
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return 0;
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}
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}
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/*
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/*
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* Update duty-cycle in channel with value.
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* Update duty-cycle in channel with value.
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* If value is larger than resolution set by pwm_init() it is cropped.
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* If value is larger than resolution set by pwm_init() it is cropped.
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*/
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*/
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void pwm_set(pwm_t dev, uint8_t channel, uint16_t value)
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void pwm_set(pwm_t pwm, uint8_t channel, uint16_t value)
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{
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{
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assert((pwm == PWM_DEV(0)) && (channel < PWM_CHAN_NUMOF));
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uint32_t period = 0; /* Store pwm period */
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/* clip and set new value */
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PwmCh_num *chan = (void *)0; /* Addressed channel. */
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value = (value > pwm_period) ? pwm_period : value;
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PWM->PWM_CH_NUM[pwm_chan[channel].hwchan].PWM_CDTYUPD = value;
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switch (dev) {
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#if PWM_0_EN
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case PWM_0:
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break;
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#endif
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default:
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return;
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}
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switch (channel) {
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#if PWM_0_CHANNELS > 0
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case 0:
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chan = PWM_0_DEV_CH0;
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break;
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#endif
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#if PWM_0_CHANNELS > 1
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case 1:
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chan = PWM_0_DEV_CH1;
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break;
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#endif
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#if PWM_0_CHANNELS > 2
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case 2:
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chan = PWM_0_DEV_CH2;
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break;
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#endif
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#if PWM_0_CHANNELS > 3
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case 3:
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chan = PWM_0_DEV_CH3;
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break;
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#endif
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default:
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (chan) {
|
|
||||||
period = chan->PWM_CPRD & PWM_CPRD_CPRD_Msk;
|
|
||||||
|
|
||||||
|
|
||||||
if (value < period) {
|
|
||||||
chan->PWM_CDTYUPD = value;
|
|
||||||
}
|
|
||||||
else { /* Value Out of range. Clip silent as required by interface. */
|
|
||||||
chan->PWM_CDTYUPD = period;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
void pwm_start(pwm_t pwm)
|
||||||
* Continue operation.
|
|
||||||
*/
|
|
||||||
void pwm_start(pwm_t dev)
|
|
||||||
{
|
{
|
||||||
switch (dev) {
|
assert(pwm == PWM_DEV(0));
|
||||||
#if PWM_0_EN
|
PWM->PWM_ENA = pwm_chan_mask;
|
||||||
|
|
||||||
case PWM_0:
|
|
||||||
PMC->PMC_PCER1 |= PMC_PCER1_PID36;
|
|
||||||
break;
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
void pwm_stop(pwm_t pwm)
|
||||||
* Stop operation and set output to 0.
|
|
||||||
*/
|
|
||||||
void pwm_stop(pwm_t dev)
|
|
||||||
{
|
{
|
||||||
switch (dev) {
|
assert(pwm == PWM_DEV(0));
|
||||||
#if PWM_0_EN
|
PWM->PWM_ENA = 0;
|
||||||
|
|
||||||
case PWM_0:
|
|
||||||
PMC->PMC_PCDR1 |= PMC_PCDR1_PID36;
|
|
||||||
break;
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* The device is reactivated by by clocking the device block.
|
* The device is reactivated by by clocking the device block.
|
||||||
* Operation continues where it has been stopped by poweroff.
|
* Operation continues where it has been stopped by poweroff.
|
||||||
*/
|
*/
|
||||||
void pwm_poweron(pwm_t dev)
|
void pwm_poweron(pwm_t pwm)
|
||||||
{
|
{
|
||||||
switch (dev) {
|
assert(pwm == PWM_DEV(0));
|
||||||
#if PWM_0_EN
|
PMC->PMC_PCER1 = PMC_PCDR1_PID36;
|
||||||
|
|
||||||
case PWM_0:
|
|
||||||
PMC->PMC_PCER1 |= PMC_PCER1_PID36;
|
|
||||||
break;
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* The device is set to power saving mode by disabling the clock.
|
* The device is set to power saving mode by disabling the clock.
|
||||||
*/
|
*/
|
||||||
void pwm_poweroff(pwm_t dev)
|
void pwm_poweroff(pwm_t pwm)
|
||||||
{
|
{
|
||||||
switch (dev) {
|
assert(pwm == PWM_DEV(0));
|
||||||
#if PWM_0_EN
|
PMC->PMC_PCDR1 = PMC_PCDR1_PID36;
|
||||||
|
|
||||||
case PWM_0:
|
|
||||||
PMC->PMC_PCDR1 |= PMC_PCDR1_PID36;
|
|
||||||
break;
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* (PWM_0_EN || PWM_1_EN) */
|
#endif /* PWM_NUMOF && PWM_CHAN_NUMOF */
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user