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https://github.com/RIOT-OS/RIOT.git
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Merge pull request #20100 from maribu/cpu/stm32/periph/i2c_2.c
cpu/stm32: fix periph_i2c for F1, F2, L1 and F4 families
This commit is contained in:
Marian Buschsieweke
GitHub
commit
4370d93226
@ -39,7 +39,6 @@
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#include <errno.h>
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#include "cpu.h"
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#include "irq.h"
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#include "mutex.h"
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#include "pm_layered.h"
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#include "panic.h"
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@ -48,7 +47,9 @@
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#include "periph/gpio.h"
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#include "periph_conf.h"
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/* Some DEBUG statements may cause delays that alter i2c functionality */
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/* Some DEBUG statements may cause delays that alter i2c functionality.
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* E.g. on STM32F1 the delay can cause issues in the state machine that
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* prevent communication. Using faster stdio than UART can mitigate this. */
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#define ENABLE_DEBUG 0
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#include "debug.h"
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@ -69,6 +70,9 @@ static int _stop(I2C_TypeDef *dev);
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static int _is_sr1_mask_set(I2C_TypeDef *i2c, uint32_t mask, uint8_t flags);
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static inline int _wait_for_bus(I2C_TypeDef *i2c);
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static void _init_pins(i2c_t dev);
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static void _deinit_pins(i2c_t dev);
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static void _disable_periph(i2c_t dev);
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static void _enable_periph(i2c_t dev);
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/**
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* @brief Array holding one pre-initialized mutex for each I2C device
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@ -106,13 +110,12 @@ void i2c_init(i2c_t dev)
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_init(dev);
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}
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#endif
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_disable_periph(dev);
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}
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static void _init_pins(i2c_t dev)
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{
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/* configure pins */
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gpio_init(i2c_config[dev].scl_pin, GPIO_OD_PU);
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gpio_init(i2c_config[dev].sda_pin, GPIO_OD_PU);
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#ifdef CPU_FAM_STM32F1
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/* This is needed in case the remapped pins are used */
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if (i2c_config[dev].scl_pin == GPIO_PIN(PORT_B, 8) ||
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@ -125,11 +128,61 @@ static void _init_pins(i2c_t dev)
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gpio_init_af(i2c_config[dev].scl_pin, GPIO_AF_OUT_OD);
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gpio_init_af(i2c_config[dev].sda_pin, GPIO_AF_OUT_OD);
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#else
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gpio_init(i2c_config[dev].scl_pin, GPIO_OD_PU);
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gpio_init(i2c_config[dev].sda_pin, GPIO_OD_PU);
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gpio_init_af(i2c_config[dev].scl_pin, i2c_config[dev].scl_af);
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gpio_init_af(i2c_config[dev].sda_pin, i2c_config[dev].sda_af);
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#endif
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}
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static void _deinit_pins(i2c_t dev)
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{
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/* Releasing pins as open drain and as set, so that the pull ups can pull
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* the signal high. If we would release the pins as push-pull output, this
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* could be unpleasant when an I2C device drives the signal low (e.g. for
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* clock stretching) while the MCU would driving the same signal high.
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*/
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gpio_set(i2c_config[dev].scl_pin);
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gpio_set(i2c_config[dev].sda_pin);
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gpio_init(i2c_config[dev].scl_pin, GPIO_OD);
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gpio_init(i2c_config[dev].sda_pin, GPIO_OD);
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}
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static void _disable_periph(i2c_t dev)
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{
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/* Clearing PE will not abort ongoing transfer, but only kick in when any
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* current transfer is done. So we can do this at any point in time */
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i2c_config[dev].dev->CR1 &= ~(I2C_CR1_PE);
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/* Wait for bus being cleared */
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_wait_for_bus(i2c_config[dev].dev);
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/* On STM32F1: Detach pins from I2C peripheral before disabling the clock
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* to it, otherwise SCL and SDA will be driven down and lots of battery
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* charge is used to heat up the pull up resistors */
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if (IS_ACTIVE(CPU_FAM_STM32F1)) {
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_deinit_pins(dev);
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}
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/* Finally, disable the clock to the I2C peripheral */
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periph_clk_dis(i2c_config[dev].bus, i2c_config[dev].rcc_mask);
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}
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static void _enable_periph(i2c_t dev)
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{
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/* First, clock the I2C peripheral so that registers can be written to */
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periph_clk_en(i2c_config[dev].bus, i2c_config[dev].rcc_mask);
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/* On STM32F1: We had to detach pins to work around a h/w limitations, so
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* re-attach them now */
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if (IS_ACTIVE(CPU_FAM_STM32F1)) {
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_init_pins(dev);
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}
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/* Finally: Enable peripheral again */
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i2c_config[dev].dev->CR1 |= I2C_CR1_PE;
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}
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static void _i2c_init(I2C_TypeDef *i2c, uint32_t clk, uint32_t ccr)
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{
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/* disable device and set ACK bit */
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@ -179,6 +232,9 @@ static void _init(i2c_t dev)
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/* configure device */
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_i2c_init(i2c, i2c_config[dev].clk, ccr);
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/* go to low power */
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_disable_periph(dev);
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}
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void i2c_acquire(i2c_t dev)
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@ -192,22 +248,14 @@ void i2c_acquire(i2c_t dev)
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pm_block(STM32_PM_STOP);
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#endif
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periph_clk_en(i2c_config[dev].bus, i2c_config[dev].rcc_mask);
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/* enable device */
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i2c_config[dev].dev->CR1 |= I2C_CR1_PE;
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_enable_periph(dev);
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}
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void i2c_release(i2c_t dev)
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{
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assert(dev < I2C_NUMOF);
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/* disable device */
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i2c_config[dev].dev->CR1 &= ~(I2C_CR1_PE);
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_wait_for_bus(i2c_config[dev].dev);
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periph_clk_dis(i2c_config[dev].bus, i2c_config[dev].rcc_mask);
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_disable_periph(dev);
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#ifdef STM32_PM_STOP
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/* unblock STOP mode */
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@ -223,7 +271,7 @@ int i2c_read_bytes(i2c_t dev, uint16_t address, void *data, size_t length,
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assert(dev < I2C_NUMOF);
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I2C_TypeDef *i2c = i2c_config[dev].dev;
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DEBUG("[i2c] read_bytes: Starting\n");
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DEBUG_PUTS("[i2c] i2c_read_bytes(): Starting");
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/* Do not support repeated start reading
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* The repeated start read requires the bus to be busy (I2C_SR2_BUSY == 1)
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@ -260,11 +308,12 @@ int i2c_read_bytes(i2c_t dev, uint16_t address, void *data, size_t length,
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/* Wait for reception to complete */
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ret = _is_sr1_mask_set(i2c, I2C_SR1_RXNE, flags);
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if (ret < 0) {
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DEBUG_PUTS("[i2c] i2c_read_bytes(): Waiting for I2C_SR1_RXNE failed");
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return ret;
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}
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((uint8_t*)data)[i] = i2c->DR;
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}
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DEBUG("[i2c] read_bytes: Finished reading bytes\n");
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DEBUG_PUTS("[i2c] i2c_read_bytes(): Finished reading bytes");
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if (flags & I2C_NOSTOP) {
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return 0;
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}
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@ -280,7 +329,7 @@ int i2c_write_bytes(i2c_t dev, uint16_t address, const void *data,
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I2C_TypeDef *i2c = i2c_config[dev].dev;
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assert(i2c != NULL);
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DEBUG("[i2c] write_bytes: Starting\n");
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DEBUG_PUTS("[i2c] i2c_write_bytes(): Starting");
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/* Length is 0 in start since we don't need to preset the stop bit */
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ret = _i2c_start(i2c, (address << 1) | I2C_FLAG_WRITE, flags, 0);
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if (ret < 0) {
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@ -292,17 +341,19 @@ int i2c_write_bytes(i2c_t dev, uint16_t address, const void *data,
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/* Send out data bytes */
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for (size_t i = 0; i < length; i++) {
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DEBUG("[i2c] write_bytes: Waiting for TX reg to be free\n");
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DEBUG_PUTS("[i2c] i2c_write_bytes(): Waiting for TX reg to be free");
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ret = _is_sr1_mask_set(i2c, I2C_SR1_TXE, flags);
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if (ret < 0) {
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DEBUG_PUTS("[i2c] i2c_write_bytes(): Waiting for I2C_SR1_TXE failed");
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return ret;
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}
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DEBUG("[i2c] write_bytes: TX is free so send byte\n");
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DEBUG_PUTS("[i2c] i2c_write_bytes(): TX is free so send byte");
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i2c->DR = ((uint8_t*)data)[i];
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}
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/* Wait for tx reg to be empty so other calls will no interfere */
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ret = _is_sr1_mask_set(i2c, I2C_SR1_TXE, flags);
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if (ret < 0) {
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DEBUG_PUTS("[i2c] i2c_write_bytes(): Waiting for I2C_SR1_TXE failed");
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return ret;
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}
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if (flags & I2C_NOSTOP) {
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@ -310,12 +361,12 @@ int i2c_write_bytes(i2c_t dev, uint16_t address, const void *data,
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}
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else {
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/* End transmission */
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DEBUG("[i2c] write_bytes: Ending transmission\n");
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DEBUG_PUTS("[i2c] i2c_write_bytes(): Ending transmission");
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ret = _stop(i2c);
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if (ret < 0) {
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return ret;
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}
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DEBUG("[i2c] write_bytes: STOP condition was send out\n");
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DEBUG_PUTS("[i2c] i2c_write_bytes(): STOP condition was send out");
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}
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return _wait_for_bus(i2c);
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@ -335,18 +386,19 @@ static int _i2c_start(I2C_TypeDef *i2c, uint8_t address_byte, uint8_t flags,
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i2c->SR1 &= ~ERROR_FLAG;
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if (!(flags & I2C_NOSTART)) {
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DEBUG("[i2c] start: Generate start condition\n");
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DEBUG_PUTS("[i2c] _i2c_start(): Generate start condition");
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/* Generate start condition */
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i2c->CR1 |= I2C_CR1_START | I2C_CR1_ACK;
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/* Wait for SB flag to be set */
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int ret = _is_sr1_mask_set(i2c, I2C_SR1_SB, flags & ~I2C_NOSTOP);
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if (ret < 0) {
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DEBUG_PUTS("[i2c] _i2c_start(): Waiting for I2C_SR1_SB failed");
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return ret;
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}
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DEBUG("[i2c] start: Start condition generated\n");
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DEBUG_PUTS("[i2c] _i2c_start(): Start condition generated");
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DEBUG("[i2c] start: Generating address\n");
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DEBUG_PUTS("[i2c] _i2c_start(): Generating address");
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/* Send address and read/write flag */
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i2c->DR = (address_byte);
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if (!(flags & I2C_NOSTOP) && length == 1) {
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@ -356,6 +408,7 @@ static int _i2c_start(I2C_TypeDef *i2c, uint8_t address_byte, uint8_t flags,
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ret = _is_sr1_mask_set(i2c, I2C_SR1_ADDR, flags & ~I2C_NOSTOP);
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if (ret == -EIO) {
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/* Since NACK happened during start it means no device connected */
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DEBUG_PUTS("[i2c] _i2c_start(): Address NACKED");
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return -ENXIO;
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}
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/* Needed to clear address bit */
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@ -364,7 +417,12 @@ static int _i2c_start(I2C_TypeDef *i2c, uint8_t address_byte, uint8_t flags,
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/* Stop must also be sent before final read */
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i2c->CR1 |= (I2C_CR1_STOP);
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}
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DEBUG("[i2c] start: Address generated\n");
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if (ret) {
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DEBUG_PUTS("[i2c] _i2c_start(): Waiting for I2C_SR1_ADDR failed");
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}
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else {
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DEBUG_PUTS("[i2c] _i2c_start(): Address generated");
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}
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return ret;
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}
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return 0;
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@ -377,7 +435,7 @@ static int _is_sr1_mask_set(I2C_TypeDef *i2c, uint32_t mask, uint8_t flags)
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while (tick--) {
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uint32_t sr1 = i2c->SR1;
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if (sr1 & I2C_SR1_AF) {
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DEBUG("[i2c] is_sr1_mask_set: NACK received\n");
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DEBUG_PUTS("[i2c] _is_sr1_mask_set(): NACK received");
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i2c->SR1 &= ~ERROR_FLAG;
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if (!(flags & I2C_NOSTOP)) {
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_stop(i2c);
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@ -385,7 +443,7 @@ static int _is_sr1_mask_set(I2C_TypeDef *i2c, uint32_t mask, uint8_t flags)
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return -EIO;
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}
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if ((sr1 & I2C_SR1_ARLO) || (sr1 & I2C_SR1_BERR)) {
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DEBUG("[i2c] is_sr1_mask_set: arb lost or bus ERROR_FLAG\n");
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DEBUG_PUTS("[i2c] _is_sr1_mask_set(): arb lost or bus ERROR_FLAG");
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i2c->SR1 &= ~ERROR_FLAG;
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_stop(i2c);
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return -EAGAIN;
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@ -401,25 +459,28 @@ static int _is_sr1_mask_set(I2C_TypeDef *i2c, uint32_t mask, uint8_t flags)
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*/
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i2c->SR1 &= ~ERROR_FLAG;
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_stop(i2c);
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DEBUG_PUTS("[i2c] _is_sr1_mask_set(): Timed out");
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return -ETIMEDOUT;
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}
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static int _stop(I2C_TypeDef *i2c)
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{
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/* send STOP condition */
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DEBUG("[i2c] stop: Generate stop condition\n");
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DEBUG_PUTS("[i2c] _stop(): Generate stop condition");
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i2c->CR1 &= ~(I2C_CR1_ACK);
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i2c->CR1 |= I2C_CR1_STOP;
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uint16_t tick = TICK_TIMEOUT;
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while ((i2c->CR1 & I2C_CR1_STOP) && tick--) {}
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if (!tick) {
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DEBUG_PUTS("[i2c] _stop(): Stop condition timed out");
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return -ETIMEDOUT;
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}
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DEBUG("[i2c] stop: Stop condition succeeded\n");
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DEBUG_PUTS("[i2c] _stop(): Stop condition succeeded");
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if (_wait_for_bus(i2c) < 0) {
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DEBUG_PUTS("[i2c] _stop(): Bus free timed out");
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return -ETIMEDOUT;
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}
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DEBUG("[i2c] stop: Bus is free\n");
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DEBUG_PUTS("[i2c] _stop(): Bus is free");
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return 0;
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}
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@ -428,6 +489,7 @@ static inline int _wait_for_bus(I2C_TypeDef *i2c)
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uint16_t tick = TICK_TIMEOUT;
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while ((i2c->SR2 & I2C_SR2_BUSY) && tick--) {}
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if (!tick) {
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DEBUG_PUTS("[i2c] _wait_for_bus(): Timed out");
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return -ETIMEDOUT;
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}
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return 0;
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@ -443,28 +505,28 @@ static inline void irq_handler(i2c_t dev)
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assert(i2c != NULL);
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unsigned state = i2c->SR1;
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DEBUG("\n\n### I2C ERROR OCCURRED ###\n");
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DEBUG_PUTS("\n\n### I2C ERROR OCCURRED ###");
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DEBUG("status: %08x\n", state);
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if (state & I2C_SR1_OVR) {
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DEBUG("OVR\n");
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DEBUG_PUTS("OVR");
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}
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if (state & I2C_SR1_AF) {
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DEBUG("AF\n");
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DEBUG_PUTS("AF");
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}
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if (state & I2C_SR1_ARLO) {
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DEBUG("ARLO\n");
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DEBUG_PUTS("ARLO");
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}
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if (state & I2C_SR1_BERR) {
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DEBUG("BERR\n");
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DEBUG_PUTS("BERR");
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}
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if (state & I2C_SR1_PECERR) {
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DEBUG("PECERR\n");
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DEBUG_PUTS("PECERR");
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}
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if (state & I2C_SR1_TIMEOUT) {
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DEBUG("TIMEOUT\n");
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DEBUG_PUTS("TIMEOUT");
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}
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if (state & I2C_SR1_SMBALERT) {
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DEBUG("SMBALERT\n");
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DEBUG_PUTS("SMBALERT");
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}
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core_panic(PANIC_GENERAL_ERROR, "I2C FAULT");
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}
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