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cpu/efm32/uart: add series 2 periph driver
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Jue
parent
2b1a260c43
commit
42c9a3c9f1
@ -456,7 +456,9 @@ typedef struct {
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void *dev; /**< UART, USART or LEUART device used */
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gpio_t rx_pin; /**< pin used for RX */
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gpio_t tx_pin; /**< pin used for TX */
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#if defined(_SILICON_LABS_32B_SERIES_0) || defined(_SILICON_LABS_32B_SERIES_1) || defined(DOXYGEN)
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uint32_t loc; /**< location of UART pins */
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#endif
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CMU_Clock_TypeDef cmu; /**< the device CMU channel */
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IRQn_Type irq; /**< the devices base IRQ channel */
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} uart_conf_t;
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@ -18,6 +18,15 @@ ifneq (,$(filter periph_rtt,$(USEMODULE)))
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endif
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endif
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# Select the correct implementation for `periph_uart`
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ifneq (,$(filter periph_uart,$(USEMODULE)))
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ifeq (2,$(EFM32_SERIES))
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SRC += uart_series2.c
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else ifneq (,$(filter $(EFM32_SERIES),0 1))
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SRC += uart_series01.c
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endif
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endif
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# Select the correct implementation for `periph_wdt`
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ifneq (,$(filter periph_wdt,$(USEMODULE)))
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ifeq (0,$(EFM32_SERIES))
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275
cpu/efm32/periph/uart_series2.c
Normal file
275
cpu/efm32/periph/uart_series2.c
Normal file
@ -0,0 +1,275 @@
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/*
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* Copyright (C) 2022 SSV Software Systems GmbH
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_efm32
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* @ingroup drivers_periph_uart
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* @{
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*
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* @file
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* @brief Low-level UART driver implementation.
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*
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* @author Juergen Fitschen <me@jue.yt>
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* @}
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*/
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#include <assert.h>
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#include "cpu.h"
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#include "periph/uart.h"
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#include "periph/gpio.h"
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#include "pm_layered.h"
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#include "bitarithm.h"
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#include "em_eusart.h"
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/**
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* @brief Allocate memory to store the callback functions
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*/
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static uart_isr_ctx_t isr_ctx[UART_NUMOF];
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/**
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* @brief Marks blocked_pm_mode entry valid
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*/
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#define PM_MODE_SHALL_BLOCK BIT7
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#define PM_MODE_BLOCKED BIT6
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/**
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* @brief Mask for storing the pm mode
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*/
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#define PM_MODE_MASK (BIT6 - 1)
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#if IS_ACTIVE(MODULE_PM_LAYERED)
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/**
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* @brief Keep track of currently blocked blocked_pm_mode
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*/
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static uint8_t blocked_pm_mode[UART_NUMOF];
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static inline void _clear_pm_mode(uart_t dev)
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{
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/* unblock previously blocked mode */
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if (blocked_pm_mode[dev] & PM_MODE_BLOCKED) {
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pm_unblock(blocked_pm_mode[dev] & PM_MODE_MASK);
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CLRBIT(blocked_pm_mode[dev], PM_MODE_BLOCKED);
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}
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}
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static inline void _set_pm_mode(uart_t dev)
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{
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/* Check if we shall block any pm mode at all */
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if (!(blocked_pm_mode[dev] & PM_MODE_SHALL_BLOCK)) {
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return;
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}
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/* block minimum required pm mode */
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if (!(blocked_pm_mode[dev] & PM_MODE_BLOCKED)) {
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pm_block(blocked_pm_mode[dev] & PM_MODE_MASK);
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SETBIT(blocked_pm_mode[dev], PM_MODE_BLOCKED);
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}
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}
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static inline void _setup_pm_mode(uart_t dev, uint8_t mode)
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{
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assert(!(blocked_pm_mode[dev] & PM_MODE_BLOCKED));
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blocked_pm_mode[dev] = mode;
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}
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#else /* !IS_ACTIVE(MODULE_PM_LAYERED) */
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static inline void _clear_pm_mode(uart_t dev) { (void) dev; }
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static inline void _set_pm_mode(uart_t dev) { (void) dev; }
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static inline void _setup_pm_mode(uart_t dev, uint8_t mode) { (void) dev; (void) mode; }
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#endif /* !IS_ACTIVE(MODULE_PM_LAYERED) */
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#define GET_PIN(x) (x & 0xf)
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#define GET_PORT(x) (x >> 4)
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int uart_init(uart_t dev, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
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{
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/* check if device is valid */
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if (dev >= UART_NUMOF) {
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return -1;
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}
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/* save interrupt callback context */
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isr_ctx[dev].rx_cb = rx_cb;
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isr_ctx[dev].arg = arg;
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EUSART_TypeDef *uart = (EUSART_TypeDef *) uart_config[dev].dev;
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/* select and enable clock */
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CMU_ClockEnable(uart_config[dev].cmu, true);
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/* initialize the pins */
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gpio_init(uart_config[dev].rx_pin, GPIO_IN_PU);
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gpio_init(uart_config[dev].tx_pin, GPIO_OUT | 1); /* 1 for high */
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/* reset and initialize peripheral */
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/* the clock source defines whether the periph is initialized in LF or HF mode */
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CMU_Select_TypeDef src = CMU_ClockSelectGet(uart_config[dev].cmu);
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if ((src == cmuSelect_LFRCO) ||
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(src == cmuSelect_ULFRCO) ||
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(src == cmuSelect_LFXO)) {
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EUSART_UartInit_TypeDef init = EUSART_UART_INIT_DEFAULT_LF;
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init.enable = eusartDisable;
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init.baudrate = baudrate;
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EUSART_UartInitLf(uart, &init);
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} else {
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EUSART_UartInit_TypeDef init = EUSART_UART_INIT_DEFAULT_HF;
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init.enable = eusartDisable;
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init.baudrate = baudrate;
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EUSART_UartInitHf(uart, &init);
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}
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/* route pings to eusart periph */
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GPIO->EUSARTROUTE[EUSART_NUM(uart)].TXROUTE =
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(GET_PORT(uart_config[dev].tx_pin) << _GPIO_EUSART_TXROUTE_PORT_SHIFT) |
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(GET_PIN(uart_config[dev].tx_pin) << _GPIO_EUSART_TXROUTE_PIN_SHIFT);
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GPIO->EUSARTROUTE[EUSART_NUM(uart)].RXROUTE =
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(GET_PORT(uart_config[dev].rx_pin) << _GPIO_EUSART_RXROUTE_PORT_SHIFT) |
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(GET_PIN(uart_config[dev].rx_pin) << _GPIO_EUSART_RXROUTE_PIN_SHIFT);
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GPIO->EUSARTROUTE[EUSART_NUM(uart)].ROUTEEN =
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(GPIO_EUSART_ROUTEEN_RXPEN | GPIO_EUSART_ROUTEEN_TXPEN);
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/* clear previously set pm_mode */
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_clear_pm_mode(dev);
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_setup_pm_mode(dev, 0);
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/* enable the interrupt */
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if (rx_cb) {
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/* If we want to receive data from the UART,
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* we have to make sure to stick with the right pm mode! */
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switch (src) {
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case cmuSelect_ULFRCO:
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/* NOP ... EM3 is the lowest available pm mode */
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break;
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case cmuSelect_LFRCO:
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case cmuSelect_LFXO:
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/* We must stay in EM2 for LFXO / LFRCO -> block EM3*/
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_setup_pm_mode(dev, PM_MODE_SHALL_BLOCK | EFM32_PM_MODE_EM3);
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break;
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default:
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/* We must stay in EM0/1 for all other clock -> block EM2*/
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_setup_pm_mode(dev, PM_MODE_SHALL_BLOCK | EFM32_PM_MODE_EM2);
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}
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/* Enable RX FIFO Level IRQ */
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/* CFG1->RXFIW is set to one frame after reset */
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EUSART_IntEnable(uart, EUSART_IEN_RXFL);
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NVIC_ClearPendingIRQ(uart_config[dev].irq);
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NVIC_EnableIRQ(uart_config[dev].irq);
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}
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uart_poweron(dev);
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return 0;
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}
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void uart_poweron(uart_t dev)
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{
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EUSART_TypeDef *uart = uart_config[dev].dev;
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CMU_ClockEnable(uart_config[dev].cmu, true);
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/* enable tx */
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EUSART_Enable_TypeDef enable = eusartEnableTx;
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/* enable rx if needed */
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if (isr_ctx[dev].rx_cb) {
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enable |= eusartEnableRx;
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}
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EUSART_Enable(uart, enable);
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/* block power mode */
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_set_pm_mode(dev);
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}
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void uart_poweroff(uart_t dev)
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{
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EUSART_TypeDef *uart = uart_config[dev].dev;
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/* unblock power mode */
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_clear_pm_mode(dev);
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/* disable tx and rx */
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EUSART_Enable(uart, eusartDisable);
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CMU_ClockEnable(uart_config[dev].cmu, false);
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}
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void uart_write(uart_t dev, const uint8_t *data, size_t len)
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{
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EUSART_TypeDef *uart = uart_config[dev].dev;
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/* When the system goes into EM2 or EM3, all EUSARTs located in PD1 will be
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* disabled automatically. We can detect this by querying the transmitter
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* enable bit and re-enable the EUSART on-the-fly. */
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if (!(uart->STATUS & EUSART_STATUS_TXENS)) {
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uart_poweron(dev);
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}
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while (len--) {
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EUSART_Tx(uart, *(data++));
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}
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/* spin until transmission is complete */
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while (!(EUSART_StatusGet(uart) & EUSART_STATUS_TXC)) {}
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}
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static void rx_irq(uart_t dev)
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{
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EUSART_TypeDef *uart = uart_config[dev].dev;
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if (EUSART_IntGetEnabled(uart) & EUSART_IF_RXFL) {
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while (EUSART_StatusGet(uart) & EUSART_STATUS_RXFL) {
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uint8_t c = EUSART_Rx(uart);
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if (isr_ctx[dev].rx_cb) {
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isr_ctx[dev].rx_cb(isr_ctx[dev].arg, c);
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}
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}
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EUSART_IntClear(uart, EUSART_IF_RXFL);
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}
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cortexm_isr_end();
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}
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#ifdef UART_0_ISR_RX
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void UART_0_ISR_RX(void)
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{
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rx_irq(0);
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}
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#endif
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#ifdef UART_1_ISR_RX
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void UART_1_ISR_RX(void)
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{
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rx_irq(1);
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}
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#endif
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#ifdef UART_2_ISR_RX
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void UART_2_ISR_RX(void)
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{
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rx_irq(2);
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}
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#endif
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#ifdef UART_3_ISR_RX
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void UART_3_ISR_RX(void)
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{
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rx_irq(3);
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}
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#endif
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#ifdef UART_4_ISR_RX
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void UART_4_ISR_RX(void)
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{
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rx_irq(4);
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}
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#endif
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