mirror of
https://github.com/RIOT-OS/RIOT.git
synced 2025-01-18 12:52:44 +01:00
cpu/cc2538/periph/timer overhaul
* Use the 32-bit counter mode. * Apply frequency scaling for non-16 MHz frequencies.
This commit is contained in:
parent
92a16a50dd
commit
4176d04b02
@ -39,7 +39,7 @@ extern "C" {
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/* Timer 0 configuration */
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/* Timer 0 configuration */
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#define TIMER_0_DEV GPTIMER0
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#define TIMER_0_DEV GPTIMER0
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#define TIMER_0_CHANNELS NUM_CHANNELS_PER_GPTIMER
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#define TIMER_0_CHANNELS 1
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#define TIMER_0_MAX_VALUE 0xffffffff
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#define TIMER_0_MAX_VALUE 0xffffffff
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#define TIMER_0_IRQn_1 GPTIMER_0A_IRQn
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#define TIMER_0_IRQn_1 GPTIMER_0A_IRQn
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#define TIMER_0_IRQn_2 GPTIMER_0B_IRQn
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#define TIMER_0_IRQn_2 GPTIMER_0B_IRQn
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@ -48,7 +48,7 @@ extern "C" {
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/* Timer 1 configuration */
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/* Timer 1 configuration */
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#define TIMER_1_DEV GPTIMER1
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#define TIMER_1_DEV GPTIMER1
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#define TIMER_1_CHANNELS NUM_CHANNELS_PER_GPTIMER
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#define TIMER_1_CHANNELS 1
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#define TIMER_1_MAX_VALUE 0xffffffff
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#define TIMER_1_MAX_VALUE 0xffffffff
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#define TIMER_1_IRQn_1 GPTIMER_1A_IRQn
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#define TIMER_1_IRQn_1 GPTIMER_1A_IRQn
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#define TIMER_1_IRQn_2 GPTIMER_1B_IRQn
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#define TIMER_1_IRQn_2 GPTIMER_1B_IRQn
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@ -57,7 +57,7 @@ extern "C" {
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/* Timer 2 configuration */
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/* Timer 2 configuration */
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#define TIMER_2_DEV GPTIMER2
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#define TIMER_2_DEV GPTIMER2
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#define TIMER_2_CHANNELS NUM_CHANNELS_PER_GPTIMER
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#define TIMER_2_CHANNELS 1
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#define TIMER_2_MAX_VALUE 0xffffffff
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#define TIMER_2_MAX_VALUE 0xffffffff
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#define TIMER_2_IRQn_1 GPTIMER_2A_IRQn
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#define TIMER_2_IRQn_1 GPTIMER_2A_IRQn
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#define TIMER_2_IRQn_2 GPTIMER_2B_IRQn
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#define TIMER_2_IRQn_2 GPTIMER_2B_IRQn
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@ -66,7 +66,7 @@ extern "C" {
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/* Timer 3 configuration */
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/* Timer 3 configuration */
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#define TIMER_3_DEV GPTIMER3
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#define TIMER_3_DEV GPTIMER3
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#define TIMER_3_CHANNELS NUM_CHANNELS_PER_GPTIMER
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#define TIMER_3_CHANNELS 1
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#define TIMER_3_MAX_VALUE 0xffffffff
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#define TIMER_3_MAX_VALUE 0xffffffff
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#define TIMER_3_IRQn_1 GPTIMER_3A_IRQn
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#define TIMER_3_IRQn_1 GPTIMER_3A_IRQn
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#define TIMER_3_IRQn_2 GPTIMER_3B_IRQn
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#define TIMER_3_IRQn_2 GPTIMER_3B_IRQn
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@ -43,7 +43,7 @@
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/* Timer 0 configuration */
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/* Timer 0 configuration */
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#define TIMER_0_DEV GPTIMER0
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#define TIMER_0_DEV GPTIMER0
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#define TIMER_0_CHANNELS NUM_CHANNELS_PER_GPTIMER
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#define TIMER_0_CHANNELS 1
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#define TIMER_0_MAX_VALUE 0xffffffff
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#define TIMER_0_MAX_VALUE 0xffffffff
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#define TIMER_0_IRQn_1 GPTIMER_0A_IRQn
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#define TIMER_0_IRQn_1 GPTIMER_0A_IRQn
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#define TIMER_0_IRQn_2 GPTIMER_0B_IRQn
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#define TIMER_0_IRQn_2 GPTIMER_0B_IRQn
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@ -52,7 +52,7 @@
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/* Timer 1 configuration */
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/* Timer 1 configuration */
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#define TIMER_1_DEV GPTIMER1
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#define TIMER_1_DEV GPTIMER1
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#define TIMER_1_CHANNELS NUM_CHANNELS_PER_GPTIMER
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#define TIMER_1_CHANNELS 1
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#define TIMER_1_MAX_VALUE 0xffffffff
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#define TIMER_1_MAX_VALUE 0xffffffff
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#define TIMER_1_IRQn_1 GPTIMER_1A_IRQn
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#define TIMER_1_IRQn_1 GPTIMER_1A_IRQn
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#define TIMER_1_IRQn_2 GPTIMER_1B_IRQn
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#define TIMER_1_IRQn_2 GPTIMER_1B_IRQn
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@ -61,7 +61,7 @@
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/* Timer 2 configuration */
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/* Timer 2 configuration */
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#define TIMER_2_DEV GPTIMER2
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#define TIMER_2_DEV GPTIMER2
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#define TIMER_2_CHANNELS NUM_CHANNELS_PER_GPTIMER
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#define TIMER_2_CHANNELS 1
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#define TIMER_2_MAX_VALUE 0xffffffff
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#define TIMER_2_MAX_VALUE 0xffffffff
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#define TIMER_2_IRQn_1 GPTIMER_2A_IRQn
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#define TIMER_2_IRQn_1 GPTIMER_2A_IRQn
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#define TIMER_2_IRQn_2 GPTIMER_2B_IRQn
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#define TIMER_2_IRQn_2 GPTIMER_2B_IRQn
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@ -70,7 +70,7 @@
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/* Timer 3 configuration */
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/* Timer 3 configuration */
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#define TIMER_3_DEV GPTIMER3
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#define TIMER_3_DEV GPTIMER3
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#define TIMER_3_CHANNELS NUM_CHANNELS_PER_GPTIMER
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#define TIMER_3_CHANNELS 1
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#define TIMER_3_MAX_VALUE 0xffffffff
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#define TIMER_3_MAX_VALUE 0xffffffff
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#define TIMER_3_IRQn_1 GPTIMER_3A_IRQn
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#define TIMER_3_IRQn_1 GPTIMER_3A_IRQn
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#define TIMER_3_IRQn_2 GPTIMER_3B_IRQn
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#define TIMER_3_IRQn_2 GPTIMER_3B_IRQn
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@ -46,7 +46,7 @@
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/* Timer 0 configuration */
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/* Timer 0 configuration */
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#define TIMER_0_DEV GPTIMER0
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#define TIMER_0_DEV GPTIMER0
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#define TIMER_0_CHANNELS NUM_CHANNELS_PER_GPTIMER
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#define TIMER_0_CHANNELS 1
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#define TIMER_0_MAX_VALUE 0xffffffff
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#define TIMER_0_MAX_VALUE 0xffffffff
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#define TIMER_0_IRQn_1 GPTIMER_0A_IRQn
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#define TIMER_0_IRQn_1 GPTIMER_0A_IRQn
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#define TIMER_0_IRQn_2 GPTIMER_0B_IRQn
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#define TIMER_0_IRQn_2 GPTIMER_0B_IRQn
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@ -55,7 +55,7 @@
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/* Timer 1 configuration */
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/* Timer 1 configuration */
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#define TIMER_1_DEV GPTIMER1
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#define TIMER_1_DEV GPTIMER1
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#define TIMER_1_CHANNELS NUM_CHANNELS_PER_GPTIMER
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#define TIMER_1_CHANNELS 1
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#define TIMER_1_MAX_VALUE 0xffffffff
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#define TIMER_1_MAX_VALUE 0xffffffff
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#define TIMER_1_IRQn_1 GPTIMER_1A_IRQn
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#define TIMER_1_IRQn_1 GPTIMER_1A_IRQn
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#define TIMER_1_IRQn_2 GPTIMER_1B_IRQn
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#define TIMER_1_IRQn_2 GPTIMER_1B_IRQn
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@ -64,7 +64,7 @@
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/* Timer 2 configuration */
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/* Timer 2 configuration */
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#define TIMER_2_DEV GPTIMER2
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#define TIMER_2_DEV GPTIMER2
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#define TIMER_2_CHANNELS NUM_CHANNELS_PER_GPTIMER
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#define TIMER_2_CHANNELS 1
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#define TIMER_2_MAX_VALUE 0xffffffff
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#define TIMER_2_MAX_VALUE 0xffffffff
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#define TIMER_2_IRQn_1 GPTIMER_2A_IRQn
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#define TIMER_2_IRQn_1 GPTIMER_2A_IRQn
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#define TIMER_2_IRQn_2 GPTIMER_2B_IRQn
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#define TIMER_2_IRQn_2 GPTIMER_2B_IRQn
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@ -73,7 +73,7 @@
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/* Timer 3 configuration */
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/* Timer 3 configuration */
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#define TIMER_3_DEV GPTIMER3
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#define TIMER_3_DEV GPTIMER3
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#define TIMER_3_CHANNELS NUM_CHANNELS_PER_GPTIMER
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#define TIMER_3_CHANNELS 1
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#define TIMER_3_MAX_VALUE 0xffffffff
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#define TIMER_3_MAX_VALUE 0xffffffff
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#define TIMER_3_IRQn_1 GPTIMER_3A_IRQn
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#define TIMER_3_IRQn_1 GPTIMER_3A_IRQn
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#define TIMER_3_IRQn_2 GPTIMER_3B_IRQn
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#define TIMER_3_IRQn_2 GPTIMER_3B_IRQn
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@ -28,12 +28,16 @@
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#include "periph/timer.h"
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#include "periph/timer.h"
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#include "periph_conf.h"
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#include "periph_conf.h"
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#define USEC_PER_SEC 1000000 /**< Conversion factor between seconds and microseconds */
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#define TIMER_A_IRQ_MASK 0x000000ff
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#define TIMER_B_IRQ_MASK 0x0000ff00
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#define NUM_CHANNELS 1
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/**
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/**
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* @brief Timer state memory
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* @brief Timer state memory
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*/
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*/
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static timer_isr_ctx_t config[TIMER_NUMOF];
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static timer_isr_ctx_t config[TIMER_NUMOF];
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static unsigned long config_freq[TIMER_NUMOF];
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/**
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/**
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@ -78,6 +82,7 @@ int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg)
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/* Save the callback function: */
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/* Save the callback function: */
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config[dev].cb = cb;
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config[dev].cb = cb;
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config[dev].arg = arg;
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config[dev].arg = arg;
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config_freq[dev] = freq;
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/* Enable the clock for this timer: */
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/* Enable the clock for this timer: */
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SYS_CTRL_RCGCGPT |= (1 << gptimer_num);
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SYS_CTRL_RCGCGPT |= (1 << gptimer_num);
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@ -85,12 +90,10 @@ int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg)
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/* Disable this timer before configuring it: */
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/* Disable this timer before configuring it: */
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gptimer->cc2538_gptimer_ctl.CTL = 0;
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gptimer->cc2538_gptimer_ctl.CTL = 0;
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gptimer->CFG = GPTMCFG_16_BIT_TIMER;
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gptimer->CFG = GPTMCFG_32_BIT_TIMER;
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gptimer->cc2538_gptimer_tamr.TAMR = GPTIMER_PERIODIC_MODE;
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gptimer->cc2538_gptimer_tamr.TAMR = GPTIMER_PERIODIC_MODE;
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gptimer->cc2538_gptimer_tamr.TAMRbits.TACDIR = 1; /**< Count up */
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gptimer->cc2538_gptimer_tamr.TAMRbits.TACDIR = 1; /**< Count up */
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gptimer->cc2538_gptimer_tamr.TAMRbits.TAMIE = 1; /**< Enable the Timer A Match Interrupt */
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/* Set the prescale register for the desired frequency: */
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gptimer->TAPR = (RCOSC16M_FREQ / freq) - 1;
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/* Enable interrupts for given timer: */
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/* Enable interrupts for given timer: */
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timer_irq_enable(dev);
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timer_irq_enable(dev);
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@ -102,14 +105,13 @@ int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg)
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}
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}
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int timer_set(tim_t dev, int channel, unsigned int timeout)
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int timer_set(tim_t dev, int channel, unsigned int timeout)
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{
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return timer_set_absolute(dev, channel, timer_read(dev) + timeout);
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}
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int timer_set_absolute(tim_t dev, int channel, unsigned int value)
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{
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{
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cc2538_gptimer_t *gptimer;
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cc2538_gptimer_t *gptimer;
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if (channel >= NUM_CHANNELS) {
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return -1;
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}
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/* get timer base register address */
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/* get timer base register address */
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switch (dev) {
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switch (dev) {
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#if TIMER_0_EN
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#if TIMER_0_EN
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@ -138,19 +140,63 @@ int timer_set_absolute(tim_t dev, int channel, unsigned int value)
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}
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}
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/* set timeout value */
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/* set timeout value */
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switch (channel) {
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gptimer->ICR = TIMER_A_IRQ_MASK; /**< Clear any pending interrupt status */
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case 0:
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gptimer->TAILR = value;
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break;
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case 1:
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uint64_t scaled_value = timeout;
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gptimer->TBILR = value;
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scaled_value *= RCOSC16M_FREQ;
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break;
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scaled_value /= config_freq[dev];
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gptimer->TAMATCHR = gptimer->TAV + scaled_value;
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gptimer->cc2538_gptimer_imr.IMRbits.TAMIM = 1; /**< Enable the Timer A Match Interrupt */
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return 1;
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}
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int timer_set_absolute(tim_t dev, int channel, unsigned int value)
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{
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cc2538_gptimer_t *gptimer;
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if (channel >= NUM_CHANNELS) {
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return -1;
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}
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/* get timer base register address */
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switch (dev) {
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#if TIMER_0_EN
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case TIMER_0:
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gptimer = TIMER_0_DEV;
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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gptimer = TIMER_1_DEV;
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break;
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#endif
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#if TIMER_2_EN
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case TIMER_2:
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gptimer = TIMER_2_DEV;
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break;
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#endif
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#if TIMER_3_EN
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case TIMER_3:
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gptimer = TIMER_3_DEV;
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break;
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#endif
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case TIMER_UNDEFINED:
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default:
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default:
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return -1;
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return -1;
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}
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}
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/* set timeout value */
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gptimer->ICR = TIMER_A_IRQ_MASK; /**< Clear any pending interrupt status */
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uint64_t scaled_value = value;
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scaled_value *= config_freq[dev];
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scaled_value /= RCOSC16M_FREQ;
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gptimer->TAMATCHR = (scaled_value > UINT32_MAX)? UINT32_MAX : scaled_value;
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gptimer->cc2538_gptimer_imr.IMRbits.TAMIM = 1; /**< Enable the Timer A Match Interrupt */
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return 1;
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return 1;
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}
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}
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{
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{
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cc2538_gptimer_t *gptimer;
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cc2538_gptimer_t *gptimer;
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if (channel >= NUM_CHANNELS) {
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return -1;
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}
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/* get timer base register address */
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/* get timer base register address */
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switch (dev) {
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switch (dev) {
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#if TIMER_0_EN
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#if TIMER_0_EN
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return -1;
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return -1;
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}
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}
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switch (channel) {
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gptimer->cc2538_gptimer_imr.IMR = 0;
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case 0:
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gptimer->cc2538_gptimer_ctl.CTLbits.TAEN = 0;
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break;
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case 1:
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gptimer->cc2538_gptimer_ctl.CTLbits.TBEN = 0;
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break;
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default:
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return -1;
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}
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return 1;
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return 1;
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}
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}
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@ -211,19 +250,19 @@ unsigned int timer_read(tim_t dev)
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switch (dev) {
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switch (dev) {
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#if TIMER_0_EN
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#if TIMER_0_EN
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case TIMER_0:
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case TIMER_0:
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return TIMER_0_DEV->TAR;
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return (uint64_t)TIMER_0_DEV->TAV * config_freq[TIMER_0] / RCOSC16M_FREQ;
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#endif
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#endif
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#if TIMER_1_EN
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#if TIMER_1_EN
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case TIMER_1:
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case TIMER_1:
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return TIMER_1_DEV->TAR;
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return (uint64_t)TIMER_1_DEV->TAV * config_freq[TIMER_1] / RCOSC16M_FREQ;
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#endif
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#endif
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#if TIMER_2_EN
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#if TIMER_2_EN
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case TIMER_2:
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case TIMER_2:
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return TIMER_2_DEV->TAR;
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return (uint64_t)TIMER_2_DEV->TAV * config_freq[TIMER_2] / RCOSC16M_FREQ;
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#endif
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#endif
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#if TIMER_3_EN
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#if TIMER_3_EN
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case TIMER_3:
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case TIMER_3:
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return TIMER_3_DEV->TAR;
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return (uint64_t)TIMER_3_DEV->TAV * config_freq[TIMER_3] / RCOSC16M_FREQ;
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#endif
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#endif
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case TIMER_UNDEFINED:
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case TIMER_UNDEFINED:
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@ -241,25 +280,21 @@ void timer_stop(tim_t dev)
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#if TIMER_0_EN
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#if TIMER_0_EN
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case TIMER_0:
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case TIMER_0:
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TIMER_0_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 0;
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TIMER_0_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 0;
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TIMER_0_DEV->cc2538_gptimer_ctl.CTLbits.TBEN = 0;
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||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
#if TIMER_1_EN
|
#if TIMER_1_EN
|
||||||
case TIMER_1:
|
case TIMER_1:
|
||||||
TIMER_1_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 0;
|
TIMER_1_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 0;
|
||||||
TIMER_1_DEV->cc2538_gptimer_ctl.CTLbits.TBEN = 0;
|
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
#if TIMER_2_EN
|
#if TIMER_2_EN
|
||||||
case TIMER_2:
|
case TIMER_2:
|
||||||
TIMER_2_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 0;
|
TIMER_2_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 0;
|
||||||
TIMER_2_DEV->cc2538_gptimer_ctl.CTLbits.TBEN = 0;
|
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
#if TIMER_3_EN
|
#if TIMER_3_EN
|
||||||
case TIMER_3:
|
case TIMER_3:
|
||||||
TIMER_3_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 0;
|
TIMER_3_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 0;
|
||||||
TIMER_3_DEV->cc2538_gptimer_ctl.CTLbits.TBEN = 0;
|
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
@ -274,25 +309,21 @@ void timer_start(tim_t dev)
|
|||||||
#if TIMER_0_EN
|
#if TIMER_0_EN
|
||||||
case TIMER_0:
|
case TIMER_0:
|
||||||
TIMER_0_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 1;
|
TIMER_0_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 1;
|
||||||
TIMER_0_DEV->cc2538_gptimer_ctl.CTLbits.TBEN = 1;
|
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
#if TIMER_1_EN
|
#if TIMER_1_EN
|
||||||
case TIMER_1:
|
case TIMER_1:
|
||||||
TIMER_1_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 1;
|
TIMER_1_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 1;
|
||||||
TIMER_1_DEV->cc2538_gptimer_ctl.CTLbits.TBEN = 1;
|
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
#if TIMER_2_EN
|
#if TIMER_2_EN
|
||||||
case TIMER_2:
|
case TIMER_2:
|
||||||
TIMER_2_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 1;
|
TIMER_2_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 1;
|
||||||
TIMER_2_DEV->cc2538_gptimer_ctl.CTLbits.TBEN = 1;
|
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
#if TIMER_3_EN
|
#if TIMER_3_EN
|
||||||
case TIMER_3:
|
case TIMER_3:
|
||||||
TIMER_3_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 1;
|
TIMER_3_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 1;
|
||||||
TIMER_3_DEV->cc2538_gptimer_ctl.CTLbits.TBEN = 1;
|
|
||||||
break;
|
break;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
@ -390,11 +421,13 @@ static inline void irq_handler(int tim, int chan)
|
|||||||
#if TIMER_0_EN
|
#if TIMER_0_EN
|
||||||
void TIMER_0_ISR_1(void)
|
void TIMER_0_ISR_1(void)
|
||||||
{
|
{
|
||||||
|
TIMER_0_DEV->ICR = TIMER_A_IRQ_MASK;
|
||||||
irq_handler(0, 0);
|
irq_handler(0, 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
void TIMER_0_ISR_2(void)
|
void TIMER_0_ISR_2(void)
|
||||||
{
|
{
|
||||||
|
TIMER_0_DEV->ICR = TIMER_B_IRQ_MASK;
|
||||||
irq_handler(0, 1);
|
irq_handler(0, 1);
|
||||||
}
|
}
|
||||||
#endif /* TIMER_0_EN */
|
#endif /* TIMER_0_EN */
|
||||||
@ -402,11 +435,13 @@ void TIMER_0_ISR_2(void)
|
|||||||
#if TIMER_1_EN
|
#if TIMER_1_EN
|
||||||
void TIMER_1_ISR_1(void)
|
void TIMER_1_ISR_1(void)
|
||||||
{
|
{
|
||||||
|
TIMER_1_DEV->ICR = TIMER_A_IRQ_MASK;
|
||||||
irq_handler(1, 0);
|
irq_handler(1, 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
void TIMER_1_ISR_2(void)
|
void TIMER_1_ISR_2(void)
|
||||||
{
|
{
|
||||||
|
TIMER_1_DEV->ICR = TIMER_B_IRQ_MASK;
|
||||||
irq_handler(1, 1);
|
irq_handler(1, 1);
|
||||||
}
|
}
|
||||||
#endif /* TIMER_1_EN */
|
#endif /* TIMER_1_EN */
|
||||||
@ -414,11 +449,13 @@ void TIMER_1_ISR_2(void)
|
|||||||
#if TIMER_2_EN
|
#if TIMER_2_EN
|
||||||
void TIMER_2_ISR_1(void)
|
void TIMER_2_ISR_1(void)
|
||||||
{
|
{
|
||||||
|
TIMER_2_DEV->ICR = TIMER_A_IRQ_MASK;
|
||||||
irq_handler(2, 0);
|
irq_handler(2, 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
void TIMER_2_ISR_2(void)
|
void TIMER_2_ISR_2(void)
|
||||||
{
|
{
|
||||||
|
TIMER_2_DEV->ICR = TIMER_B_IRQ_MASK;
|
||||||
irq_handler(2, 1);
|
irq_handler(2, 1);
|
||||||
}
|
}
|
||||||
#endif /* TIMER_2_EN */
|
#endif /* TIMER_2_EN */
|
||||||
@ -426,11 +463,13 @@ void TIMER_2_ISR_2(void)
|
|||||||
#if TIMER_3_EN
|
#if TIMER_3_EN
|
||||||
void TIMER_3_ISR_1(void)
|
void TIMER_3_ISR_1(void)
|
||||||
{
|
{
|
||||||
|
TIMER_3_DEV->ICR = TIMER_A_IRQ_MASK;
|
||||||
irq_handler(3, 0);
|
irq_handler(3, 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
void TIMER_3_ISR_2(void)
|
void TIMER_3_ISR_2(void)
|
||||||
{
|
{
|
||||||
|
TIMER_3_DEV->ICR = TIMER_B_IRQ_MASK;
|
||||||
irq_handler(3, 1);
|
irq_handler(3, 1);
|
||||||
}
|
}
|
||||||
#endif /* TIMER_3_EN */
|
#endif /* TIMER_3_EN */
|
||||||
|
Loading…
Reference in New Issue
Block a user