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Merge pull request #18562 from MrKevinWeiss/pr/removemips

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cpu/mips: Remove all mips
This commit is contained in:
Kaspar Schleiser 2022-09-30 10:47:09 +02:00 committed by GitHub
commit 3ee3d1b9ac
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124 changed files with 23 additions and 84798 deletions
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4
.github/labeler.yml vendored
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@ -143,10 +143,6 @@
"Platform: ESP":
- "cpu/esp*/**/*"
"Platform: MIPS":
- "cpu/mips*/**/*"
- "makefiles/arch/mips.inc.mk"
"Platform: MSP":
- "cpu/msp*/**/*"
- "makefiles/arch/msp430.inc.mk"

4
.github/workflows/tools-buildtest.yml vendored
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@ -39,10 +39,6 @@ jobs:
uses: aabadie/riot-action@v1
with:
cmd: make -C dist/tools/edbg
- name: Build pic32prog standalone
uses: aabadie/riot-action@v1
with:
cmd: make -C dist/tools/pic32prog
- name: Build setsid standalone
uses: aabadie/riot-action@v1
with:

2
.murdock
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@ -132,8 +132,6 @@ tests/ieee802154_hal
# Eventually this list will be removed...
#
: ${TEST_KCONFIG_BOARD_BLOCKLIST:="
6lowpan-clicker
pic32-wifire
"}
# This list will force all boards that are not in the TEST_KCONFIG_BOARD_BLOCKLIST

1
CODEOWNERS
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@ -53,7 +53,6 @@
/cpu/fe310/ @aabadie @kaspar030 @bergzand
/cpu/kinetis/ @fjmolinas
/cpu/lpc2387/ @benpicco @maribu
/cpu/mips*/ @kaspar030 @francois-berder
/cpu/msp430*/ @kaspar030 @gschorcht
/cpu/nrf*/ @aabadie @haukepetersen
/cpu/nrf52/radio/nrf802154/ @bergzand @SemjonKerner @jia200x

9
LOSTANDFOUND.md
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@ -42,6 +42,15 @@ This way, their names are never removed from the RIOT repository.
# Removed Features
### cpu/mips* [6cad5d24771ba6199228351a11b5062cd2e9b36d]
Author:
- Neil Jones <Neil.Jones@imgtec.com>
Reasons for removal:
- Not maintained anymore
- Current state is not very useful and nobody claimed to use it
### pkg/libcoap [d83d08f0995a88f399e70a7d07b44dd780082436]
Author:

2
README.md
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@ -61,7 +61,7 @@ but not limited to:
* a preemptive, tickless scheduler with priorities
* flexible memory management
* high resolution, long-term timers
* support 100+ boards based on AVR, MSP430, ESP8266, ESP32, MIPS, RISC-V,
* support 100+ boards based on AVR, MSP430, ESP8266, ESP32, RISC-V,
ARM7 and ARM Cortex-M
* the native port allows to run RIOT as-is on Linux, BSD, and MacOS. Multiple
instances of RIOT running on a single machine can also be interconnected via

15
boards/6lowpan-clicker/Kconfig
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@ -1,15 +0,0 @@
# Copyright (c) 2020 HAW Hamburg
#
# This file is subject to the terms and conditions of the GNU Lesser
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.
config BOARD
default "6lowpan-clicker" if BOARD_6LOWPAN_CLICKER
config BOARD_6LOWPAN_CLICKER
bool
default y
select CPU_MODEL_P32MX470F512H
select HAS_PERIPH_TIMER
select HAS_PERIPH_UART

2
boards/6lowpan-clicker/Makefile
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@ -1,2 +0,0 @@
MODULE = board
include $(RIOTBASE)/Makefile.base

5
boards/6lowpan-clicker/Makefile.dep
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@ -1,5 +0,0 @@
ifneq (,$(filter saul_default,$(USEMODULE)))
USEMODULE += saul_gpio
endif
USEMODULE += newlib_syscalls_mips_uhi

6
boards/6lowpan-clicker/Makefile.features
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@ -1,6 +0,0 @@
CPU = mips_pic32mx
CPU_MODEL = p32mx470f512h
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart

15
boards/6lowpan-clicker/Makefile.include
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@ -1,15 +0,0 @@
# use pic32prog by default to program this board
PROGRAMMER ?= pic32prog
PROGRAMMERS_SUPPORTED += pic32prog
ifeq ($(PROGRAMMER),pic32prog)
# pic32prog
#
# For PICkit3:
#
# * Connect the chipKIT-Wi-Fire to USB
# * Connect the PICkit3 to ICSP holes
# * https://docs.creatordev.io/wifire/guides/wifire-programming/
# * The triangle `▶` goes into the port number 1 (a hole with a square around it)
# opposite side of the JP1 ICSP text.
FLASHFILE ?= $(HEXFILE)
endif

20
boards/6lowpan-clicker/clicker.c
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@ -1,20 +0,0 @@
/*
* Copyright(C) 2016,2017, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
#include "board.h"
#include "periph/gpio.h"
extern void dummy(void);
void board_init(void)
{
/* Stop the linker from throwing away the PIC32 config register settings */
dummy();
}

95
boards/6lowpan-clicker/doc.txt
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@ -1,95 +0,0 @@
/**
@defgroup boards_6lowpan-clicker MikroE 6LoWPAN Clicker
@ingroup boards
@brief Support for the MikroE 6LoWPAN Clicker
@deprecated Will not be available after the 2022.07 release. This includes
all MIPS based boards and cpus.
## Overview
The `6lowpan clicker` is an evaluation board by Mikroe featuring a
PIC32MX470F512H, a 6lowpan radio (CA810) by Cascoda and a Mikrobus
socket for expansion boards.
More general information on the board and related documentation can be found
[here](https://www.mikroe.com/clicker-6lowpan). Schematics for the board can be
found in the [manual](https://download.mikroe.com/documents/starter-boards/clicker/6lowpan/6lowpan-clicker-manual-v100.pdf).
## Hardware
### MCU
| MCU | PIC32MX470F512H |
|:---------- |:-------------------- |
| Family | PIC32MX (MIPS M4K) |
| Vendor | Microchip |
| RAM | 128KiB |
| Flash | 512KiB |
| Frequency | 120MHz |
| FPU | no |
| Timers | 5 (all 16-bit) |
| ADCs | 1x 28-channel 10-bit |
| USB 2.0 | 1 |
| UARTs | 4 |
| SPIs | 2 |
| I2Cs | 2 |
| RTC | yes |
| RNG | no |
| Vcc | 2.3V - 3.6V |
| Datasheet | [Datasheet](http://ww1.microchip.com/downloads/en/DeviceDoc/PIC32MX330350370430450470_Datasheet_DS60001185H.pdf) |
### User Interface
2 Buttons:
| NAME | T1 | T2 |
|:----- |:--- |:--- |
| Pin | RE7 | RB0 |
2 LEDs:
| NAME | LD1 | LD2 |
| ----- | --- | --- |
| Color | red | red |
| Pin | RB1 | RB2 |
## Implementation Status
| Device | ID | Supported | Comments |
|:---------------- |:--------------- |:--------- |:---------------------- |
| MCU | pic32mx470f512h | partly | |
| Low-level driver | GPIO | partly | gpio_irq not supported |
| | ADC | no | |
| | PWM | no | |
| | UART | yes | |
| | I2C | no | |
| | SPI | no | |
| | USB | no | |
| | RTT | no | |
| | RTC | no | |
| | Timer | no | |
## Using UART
This board doesn't open an UART or serial interface through the USB
automatically, and the USB device driver hasn't been implemented to RIOT.
Therefore, to open an UART interface one has to connect a usb/ttl converter to
the UART3 pins RF5 (RX) and RF4 (TX) available on the Mikrobus socket.
## Flashing the device
There are two ways to flash the MCU:
* Using MPLAB-IPE and a PICkit 3 (The RIOT build generates a hexfile
compatible with MPLAB-IPE)
* Using pic32prog and a PICkit 2 or a PICkit 3 (other devices might be
supported by pic32prog but were not tested). This is the preferred option
as it makes possible to flash the device using `make flash` command.
## Supported Toolchains
For using the 6lowpan-clicker board we strongly recommend the usage of the
[Codescape GNU Tools](https://codescape.mips.com) toolchain.
*/

77
boards/6lowpan-clicker/include/board.h
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@ -1,77 +0,0 @@
/*
* Copyright(C) 2016,2017, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
/**
* @ingroup boards_6lowpan-clicker
* @details
* see:
* https://www.mikroe.com/clicker-6lowpan
* For more information on the board.
*
* @{
*
* @file
* @brief board configuration for the MikroE 6LoWPAN Clicker
*
* @author Neil Jones <Neil.Jones@imgtec.com>
*/
#ifndef BOARD_H
#define BOARD_H
#include "cpu.h"
#include "periph_conf.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Set how many increments of the count register per uS
* needed by the timer code.
*/
#define TICKS_PER_US (48)
/**
* @name LED pin configuration
* @{
*/
#define LED1_PIN GPIO_PIN(PORT_B, 1)
#define LED2_PIN GPIO_PIN(PORT_B, 2)
#define LED1_MASK (1 << 1)
#define LED2_MASK (1 << 2)
#define LED1_ON (LATBSET = LED1_MASK)
#define LED1_OFF (LATBCLR = LED1_MASK)
#define LED1_TOGGLE (LATBINV = LED1_MASK)
#define LED2_ON (LATBSET = LED2_MASK)
#define LED2_OFF (LATBCLR = LED2_MASK)
#define LED2_TOGGLE (LATBINV = LED2_MASK)
/** @} */
/**
* @name Button pin configuration
* @{
*/
#define BTN0_PIN GPIO_PIN(PORT_E, 7)
#define BTN0_MODE GPIO_IN
#define BTN1_PIN GPIO_PIN(PORT_B, 0)
#define BTN1_MODE GPIO_IN
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* BOARD_H */
/** @} */

61
boards/6lowpan-clicker/include/gpio_params.h
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@ -1,61 +0,0 @@
/*
* Copyright (C) 2020 Francois Berder
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_6lowpan-clicker
* @{
*
* @file
* @brief Configuration of SAUL mapped GPIO pins
*
* @author Francois Berder <fberder@outlook.fr>
*/
#ifndef GPIO_PARAMS_H
#define GPIO_PARAMS_H
#include "board.h"
#include "saul/periph.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief GPIO configuration
*/
static const saul_gpio_params_t saul_gpio_params[] =
{
{
.name = "LD1",
.pin = LED1_PIN,
.mode = GPIO_OUT,
},
{
.name = "LD2",
.pin = LED2_PIN,
.mode = GPIO_OUT,
},
{
.name = "T1",
.pin = BTN0_PIN,
.mode = BTN0_MODE,
},
{
.name = "T2",
.pin = BTN1_PIN,
.mode = BTN1_MODE,
},
};
#ifdef __cplusplus
}
#endif
#endif /* GPIO_PARAMS_H */
/** @} */

82
boards/6lowpan-clicker/include/periph_conf.h
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@ -1,82 +0,0 @@
/*
* Copyright(C) 2016,2017, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
/**
* @ingroup boards_6lowpan-clicker
* @{
*
* @file
* @brief peripheral configuration for the MikroE 6LoWPAN Clicker
*
* @author Neil Jones <Neil.Jones@imgtec.com>
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#include "cpu.h"
#include "macros/units.h"
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock configurations
* @{
*/
/**
* @brief The peripheral clock is required for the UART Baud rate calculation
* It is configured by the 'config' registers (see pic32_config_settings.c)
* Note 120MHz is the max F for this device.
*/
#define PERIPHERAL_CLOCK MHZ(96)
#define CLOCK_CORECLOCK MHZ(120)
/** @} */
/**
* @name Timer definitions
* @{
*/
#define TIMER_NUMOF (1)
#define TIMER_0_CHANNELS (3)
/** @} */
/**
* @name UART Definitions
* @{
*/
static const uart_conf_t uart_config[] = {
{ /* UART port available on MikroBus */
.base = (volatile unsigned int *)_UART3_BASE_ADDRESS,
.clock = PERIPHERAL_CLOCK,
.rx_pin = GPIO_PIN(PORT_F, 5),
.tx_pin = GPIO_PIN(PORT_F, 4),
.rx_mux_reg = &U3RXR,
.tx_mux_reg = &RPF4R,
.rx_af = GPIO_AF2,
.tx_af = GPIO_AF1,
.vector = _UART_3_VECTOR,
.irq = _UART3_RX_IRQ,
},
};
#define UART_0_ISR (isr_usart3)
#define UART_NUMOF ((unsigned int)ARRAY_SIZE(uart_config))
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */
/** @} */

114
boards/6lowpan-clicker/pic32_config_settings.c
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@ -1,114 +0,0 @@
/*
* Copyright(C) 2016,2017, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
#include <stdint.h>
#include "vendor/p32mx470f512h.h"
/*
* DEVCFG3 @ 0x1FC02FF0
*
*
* USERID
* FSRSSEL 7 Assign IPL 7 to a shadow register set.
* PMDLIWAY 1
* IOL1WAY 1
* FUSBIDIO OFF USB USBID Selection Controlled by Port Function
* FVBUSONIO ON VBUSON pin is controlled by the USB module function
*/
volatile uint32_t _DEVCFG3 __attribute__((used, section(".devcfg3"))) =
0x0 /* unused bits must be 0 */
| (_DEVCFG3_USERID_MASK & 0xFFFF << _DEVCFG3_USERID_POSITION)
| (_DEVCFG3_FSRSSEL_MASK & 7 << _DEVCFG3_FSRSSEL_POSITION)
| (_DEVCFG3_PMDL1WAY_MASK & 1 << _DEVCFG3_PMDL1WAY_POSITION)
| (_DEVCFG3_IOL1WAY_MASK & 1 << _DEVCFG3_IOL1WAY_POSITION)
| (_DEVCFG3_FUSBIDIO_MASK & 0 << _DEVCFG3_FUSBIDIO_POSITION)
| (_DEVCFG3_FVBUSONIO_MASK & 1 << _DEVCFG3_FVBUSONIO_POSITION);
/* Note this sets the PLL to 96MHz (8/2 * 24) which is only supported by 3xx
* and 4xx parts and assumes an 8MHz XTAL.
*
* 1xx/2xx/53x/57x only support 50MHz (use 8/2 x 24 / 2 = 48Mhz)
* 5xx/6xx/7xx only support 80Mhz (use 8/2 * 20 = 80MHz).
*
*
* DEVCFG2 @ 0x1FC02FF4 (
*
* FPLLIDIV DIV_2 System PLL Input Divider 2x Divider
* FPLLMUL 24x System PLL Multiplier PLL Multiply by 24, 8/2 x 24 = 96MHz
* UPLLIDIV DIV_12x USB PLL divider
* UPLLEN OFF USB PLL disabled
* FPLLODIV DIV_1 System PLL Output Clock Divider 1x Divider
*/
volatile uint32_t _DEVCFG2 __attribute__ ((used, section(".devcfg2"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG2_FPLLIDIV_MASK | 1 << _DEVCFG2_FPLLIDIV_POSITION)
& (~_DEVCFG2_FPLLMUL_MASK | 7 << _DEVCFG2_FPLLMUL_POSITION)
& (~_DEVCFG2_UPLLIDIV_MASK | 7 << _DEVCFG2_UPLLIDIV_POSITION)
& (~_DEVCFG2_UPLLEN_MASK | 0 << _DEVCFG2_UPLLEN_POSITION)
& (~_DEVCFG2_FPLLODIV_MASK | 0 << _DEVCFG2_FPLLODIV_POSITION);
/*
* DEVCFG1 @ 0x1FC02FF8
*
* FNOSC PRIPLL Oscillator Selection Bits Primary Osc w/PLL (XT+,HS+,EC+PLL)
* FSOSCEN ON Secondary Oscillator Enable Enabled
* IESO ON Internal/External Switch Over Enabled
* OSCIOFNC OFF CLKO Output Signal Active on the OSCO Pin Disabled
* FPBDIV DIV_1 Peripheral Clock Divisor Pb_Clk is Sys_Clk/1
* FCKSM CSDCMD Clock Switching and Monitor Selection Clock Switch Disable, FSCM Disabled
* WDTPS PS2 Watchdog Timer Postscaler 1:2
* WINDIS OFF Watchdog Timer Window Enable Watchdog Timer is in Non-Window Mode
* FWDTEN OFF Watchdog Timer Enable WDT Disabled (SWDTEN Bit Controls)
* FWDTWINSZ 25%
*/
volatile uint32_t _DEVCFG1 __attribute__ ((used, section(".devcfg1"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG1_FNOSC_MASK | 3 << _DEVCFG1_FNOSC_POSITION)
& (~_DEVCFG1_FSOSCEN_MASK | 1 << _DEVCFG1_FSOSCEN_POSITION)
& (~_DEVCFG1_IESO_MASK | 1 << _DEVCFG1_IESO_POSITION)
& (~_DEVCFG1_POSCMOD_MASK | 1 << _DEVCFG1_POSCMOD_POSITION)
& (~_DEVCFG1_OSCIOFNC_MASK | 1 << _DEVCFG1_OSCIOFNC_POSITION)
& (~_DEVCFG1_FPBDIV_MASK | 0 << _DEVCFG1_FPBDIV_POSITION)
& (~_DEVCFG1_FCKSM_MASK | 3 << _DEVCFG1_FCKSM_POSITION)
& (~_DEVCFG1_WDTPS_MASK | 1 << _DEVCFG1_WDTPS_POSITION)
& (~_DEVCFG1_WINDIS_MASK | 0 << _DEVCFG1_WINDIS_POSITION)
& (~_DEVCFG1_FWDTEN_MASK | 0 << _DEVCFG1_FWDTEN_POSITION)
& (~_DEVCFG1_FWDTWINSZ_MASK | 3 << _DEVCFG1_FWDTWINSZ_POSITION);
/*
* DEVCFG0 @ 0x1FC02FFC
*
* DEBUG OFF Background Debugger Enable Debugger is disabled
* JTAGEN ON JTAG Enable JTAG Port Enabled
* ICESEL ICS_PGx1 CE/ICD Comm Channel Select Communicate on PGEC1/PGED1
* PWP OFF Program Flash Write Protect Disable
* BWP OFF Boot Flash Write Protect bit Protection Disabled
* CP OFF Code Protect Protection Disabled
*/
volatile uint32_t _DEVCFG0 __attribute__ ((used, section(".devcfg0"))) =
0x7fffffff /* unused bits must be 1 except MSB which is 0 for some odd reason */
& (~_DEVCFG0_DEBUG_MASK | 3 << _DEVCFG0_DEBUG_POSITION)
& (~_DEVCFG0_JTAGEN_MASK | 1 << _DEVCFG0_JTAGEN_POSITION)
& (~_DEVCFG0_ICESEL_MASK | 3 << _DEVCFG0_ICESEL_POSITION)
& (~_DEVCFG0_PWP_MASK | 0xff << _DEVCFG0_PWP_POSITION)
& (~_DEVCFG0_BWP_MASK | 1 << _DEVCFG0_BWP_POSITION)
& (~_DEVCFG0_CP_MASK | 1 << _DEVCFG0_CP_POSITION);
/*
* Without a reference to this function from elsewhere LD throws the whole
* compile unit away even though the data is 'volatile' and 'used' !!!
*/
void dummy(void)
{
(void)1;
}

15
boards/pic32-wifire/Kconfig
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@ -1,15 +0,0 @@
# Copyright (c) 2020 HAW Hamburg
#
# This file is subject to the terms and conditions of the GNU Lesser
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.
config BOARD
default "pic32-wifire" if BOARD_PIC32_WIFIRE
config BOARD_PIC32_WIFIRE
bool
default y
select CPU_MODEL_P32MZ2048EFG100
select HAS_PERIPH_TIMER
select HAS_PERIPH_UART

2
boards/pic32-wifire/Makefile
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@ -1,2 +0,0 @@
MODULE = board
include $(RIOTBASE)/Makefile.base

5
boards/pic32-wifire/Makefile.dep
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@ -1,5 +0,0 @@
ifneq (,$(filter saul_default,$(USEMODULE)))
USEMODULE += saul_gpio
endif
USEMODULE += newlib_syscalls_mips_uhi

6
boards/pic32-wifire/Makefile.features
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@ -1,6 +0,0 @@
CPU = mips_pic32mz
CPU_MODEL = p32mz2048efg100
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart

22
boards/pic32-wifire/Makefile.include
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@ -1,22 +0,0 @@
PORT_LINUX ?= /dev/ttyUSB0
# use pic32prog by default to program this board
PROGRAMMER ?= pic32prog
PROGRAMMERS_SUPPORTED += pic32prog jlink
ifeq ($(PROGRAMMER),pic32prog)
# pic32prog
#
# For PICkit3:
#
# * Connect the chipKIT-Wi-Fire to USB
# * Connect the PICkit3 to ICSP holes
# * https://docs.creatordev.io/wifire/guides/wifire-programming/
# * The triangle `▶` goes into the port number 1 (a hole with a square around it)
# opposite side of the JP1 ICSP text.
FLASHFILE ?= $(HEXFILE)
else ifeq ($(PROGRAMMER),jlink)
FLASHFILE ?= $(HEXFILE)
JLINK_DEVICE = PIC32MZ2048EFG100
JLINK_IF = JTAG
endif

93
boards/pic32-wifire/doc.txt
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/**
@defgroup boards_pic32-wifire Digilent PIC32 WiFire
@ingroup boards
@brief Support for the Digilent PIC32 WiFire
@deprecated Will not be available after the 2022.07 release. This includes
all MIPS based boards and cpus.
## Overview
The ChipKit Wifire is a development board by Digilent featuring a PIC32MZ and a Wifi module (MRF24WG0MA).
General information about the board can be found [here](https://store.digilentinc.com/wi-fire-wifi-enabled-pic32mz-microcontroller-board/)
Please do not use board rev A or B as they use a different MCU (PIC32MZ2048ECG100).
Additional documents:
* [Schematics](https://reference.digilentinc.com/_media/reference/microprocessor/wi-fire/chipkit_wifire_sch.pdf) for the Wifire board rev C
* [Schematics](https://reference.digilentinc.com/_media/reference/microprocessor/wi-fire/wifire_sch.pdf) for the Wifire board rev D
* [Reference manual](https://reference.digilentinc.com/_media/reference/microprocessor/wi-fire/wi-fire_rm_revd.pdf) for the Wifire board rev D
## Hardware
### MCU
| MCU | PIC32MZ2048EFG100 |
|:---------- |:-------------------- |
| Family | PIC32MZ (MIPS M5150) |
| Vendor | Microchip |
| RAM | 512Kb |
| Flash | 2048Kb |
| Frequency | 200MHz |
| FPU | yes |
| Timers | 9 (all 16-bit) |
| ADCs | 1x 40-channel 12-bit |
| USB 2.0 | 1 |
| UARTs | 6 |
| SPIs | 6 |
| I2Cs | 5 |
| RTC | yes |
| RNG | yes |
| Vcc | 2.1V - 3.6V |
| Datasheet | [Datasheet](http://ww1.microchip.com/downloads/en/DeviceDoc/PIC32MZ%20EF%20Family%20Datasheet_DS60001320G.pdf) |
### User Interface
3 Buttons:
| NAME | Reset | T1 | T2 |
|:----- |:------ |:--- |:--- |
| Pin | nReset | RA5 | RA4 |
4 LEDs:
| NAME | LD1 | LD2 | LD3 | LD4 |
| ----- | ----- | ----- | ----- | ----- |
| Color | green | green | green | green |
| Pin | RG6 | RD4 | RB11 | RG15 |
## Implementation Status
| Device | ID | Supported | Comments |
|:---------------- |:--------------- |:--------- |:---------------------- |
| MCU | pic32mz2048efg100 | partly | |
| Low-level driver | GPIO | partly | gpio_irq not supported |
| | ADC | no | |
| | PWM | no | |
| | UART | yes | |
| | I2C | no | |
| | SPI | no | |
| | USB | no | |
| | RTT | no | |
| | RTC | no | |
| | RNG | yes | |
| | Timer | no | |
## Using UART
This board opens a serial interface through the USB automatically.
## Flashing the device
There are three ways to flash the MCU:
* Using MPLAB-IPE and a PICkit 3 (The RIOT build generates a hexfile
compatible with MPLAB-IPE)
* Using pic32prog and a PICkit 2 or a PICkit 3 (other devices might be
supported by pic32prog but were not tested).
* Using a SEGGER J-Link probe. JTAG pins are available on the JP3 connector.
## Supported Toolchains
For using the pic32-wifire board we strongly recommend the usage of the
[Codescape GNU Tools](https://codescape.mips.com) toolchain.
*/

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/*
* Copyright(C) 2017, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
/**
* @ingroup boards_pic32-wifire
* @details
* See:
* http://store.digilentinc.com/chipkit-wi-fire-wifi-enabled-mz-microcontroller-board/
* for more information on the board.
*
* @{
*
* @file
* @brief board configuration for the Digilent PIC32 WiFire
*
* @author Neil Jones <Neil.Jones@imgtec.com>
*/
#ifndef BOARD_H
#define BOARD_H
#include "periph_conf.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Set how many increments of the count register per uS
* needed by the timer code.
*/
#define TICKS_PER_US (100)
/**
* @name LED pin configuration
* @{
*/
#define LED1_PIN GPIO_PIN(PORT_G, 6)
#define LED2_PIN GPIO_PIN(PORT_D, 4)
#define LED3_PIN GPIO_PIN(PORT_B, 11)
#define LED4_PIN GPIO_PIN(PORT_G, 15)
#define LED1_MASK (1 << 6)
#define LED2_MASK (1 << 4)
#define LED3_MASK (1 << 11)
#define LED4_MASK (1 << 15)
#define LED1_ON (LATGSET = LED1_MASK)
#define LED1_OFF (LATGCLR = LED1_MASK)
#define LED1_TOGGLE (LATGINV = LED1_MASK)
#define LED2_ON (LATDSET = LED2_MASK)
#define LED2_OFF (LATDCLR = LED2_MASK)
#define LED2_TOGGLE (LATDINV = LED2_MASK)
#define LED3_ON (LATBSET = LED3_MASK)
#define LED3_OFF (LATBCLR = LED3_MASK)
#define LED3_TOGGLE (LATBINV = LED3_MASK)
#define LED4_ON (LATGSET = LED4_MASK)
#define LED4_OFF (LATGCLR = LED4_MASK)
#define LED4_TOGGLE (LATGINV = LED4_MASK)
/** @} */
/**
* @name Button pin configuration
* @{
*/
#define BTN0_PIN GPIO_PIN(PORT_A, 5)
#define BTN0_MODE GPIO_IN
#define BTN1_PIN GPIO_PIN(PORT_A, 4)
#define BTN1_MODE GPIO_IN
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* BOARD_H */
/** @} */

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/*
* Copyright (C) 2020 Francois Berder
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_pic32-wifire
* @{
*
* @file
* @brief Configuration of SAUL mapped GPIO pins
*
* @author Francois Berder <fberder@outlook.fr>
*/
#ifndef GPIO_PARAMS_H
#define GPIO_PARAMS_H
#include "board.h"
#include "saul/periph.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief GPIO configuration
*/
static const saul_gpio_params_t saul_gpio_params[] =
{
{
.name = "LD1",
.pin = LED1_PIN,
.mode = GPIO_OUT,
},
{
.name = "LD2",
.pin = LED2_PIN,
.mode = GPIO_OUT,
},
{
.name = "LD3",
.pin = LED3_PIN,
.mode = GPIO_OUT,
},
{
.name = "LD4",
.pin = LED4_PIN,
.mode = GPIO_OUT,
},
{
.name = "BTN1",
.pin = BTN0_PIN,
.mode = BTN0_MODE,
},
{
.name = "BTN2",
.pin = BTN1_PIN,
.mode = BTN1_MODE,
},
};
#ifdef __cplusplus
}
#endif
#endif /* GPIO_PARAMS_H */
/** @} */

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/*
* Copyright(C) 2016,2017, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
/**
* @ingroup boards_pic32-wifire
* @{
*
* @file
* @brief peripheral configuration for the Digilent PIC32 WiFire
*
* @author Neil Jones <Neil.Jones@imgtec.com>
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#include "cpu.h"
#include "macros/units.h"
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock configurations
* @{
*/
/**
* @brief The peripheral clock is required for the UART Baud rate calculation
* It is configured by the 'config' registers (see pic32_config_settings.c)
*/
#define PERIPHERAL_CLOCK MHZ(100)
#define CLOCK_CORECLOCK MHZ(200)
/** @} */
/**
* @name Timer definitions
* @{
*/
#define TIMER_NUMOF (1)
#define TIMER_0_CHANNELS (3)
/** @} */
/**
* @name UART Definitions
* @{
*/
static const uart_conf_t uart_config[] = {
{ /* Virtual COM port */
.base = (volatile unsigned int *)_UART4_BASE_ADDRESS,
.clock = PERIPHERAL_CLOCK,
.rx_pin = GPIO_PIN(PORT_F, 2),
.tx_pin = GPIO_PIN(PORT_F, 8),
.rx_mux_reg = &U4RXR,
.tx_mux_reg = &RPF8R,
.rx_af = GPIO_AF11,
.tx_af = GPIO_AF2,
.vector = _UART4_RX_VECTOR,
},
};
#define UART_0_ISR (isr_usart4)
#define UART_NUMOF ((unsigned int)ARRAY_SIZE(uart_config))
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */
/** @} */

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/*
* Copyright(C) 2016,2017, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
#include <stdint.h>
#include "vendor/p32mz2048efg100.h"
/*
* Note banked access only applies to MZ part MX only has 1 set of registers
* similar to the MZ's lower alias.Thus when working with MX parts comment
* out the *_B* entries, note the address in the comments are different for MX
* too so a different linker script is required between MX and MZ to place
* these registers at the correct addresses. MM parts have completely different
* config registers, so this file is not applicable.
*
* Note when programming via Microchip IPE (tested using a Pickit-3) entries
* need to exist in the programming file for both the lower alias and the
* config1 configuration spaces (starting at 0x1FC0FFC0 and 0x1FC4FFC0)
* hence the duplicate entries in different sections allowing the linker to
* place them at different addresses.
*/
/*
* DEVCFG3_LA @ 0x1FC0FFC0 (lower alias)
* ADEVFGC3_LA @ 0x1FC0FF40 (alternate devcfg3 in lower alias)
* DEVCFG3_B1 @ 0x1FC4FFC0 (config space 1)
* ADEVCFG3_B1 @ 0x1FC4FF40 (alternate devcfg3 in config space 1)
* DEVCFG3_B2 @ 0x1FC6FFC0 (config space 1)
* ADEVCFG3_B2 @ 0x1FC6FF40 (alternate devcfg3 in config space 2)
*
*
* USERID
* FMIIEN OFF Ethernet RMII/MII Enable RMII Enabled
* FETHIO ON Ethernet I/O Pin Select Default Ethernet I/O
* PGL1WAY OFF Permission Group Lock One Way Configuration Allow multiple reconfigurations
* PMDL1WAY OFF Peripheral Module Disable Configuration Allow multiple reconfigurations
* IOL1WAY OFF Peripheral Pin Select Configuration Allow multiple reconfigurations
* FUSBIDIO OFF USB USBID Selection Controlled by Port Function
*/
volatile uint32_t DEVCFG3_LA __attribute__((used, section(".devcfg3_la"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG3_USERID_MASK | 0xFFFF << _DEVCFG3_USERID_POSITION)
& (~_DEVCFG3_FMIIEN_MASK | 0 << _DEVCFG3_FMIIEN_POSITION)
& (~_DEVCFG3_FETHIO_MASK | 1 << _DEVCFG3_FETHIO_POSITION)
& (~_DEVCFG3_PGL1WAY_MASK | 0 << _DEVCFG3_PGL1WAY_POSITION)
& (~_DEVCFG3_PMDL1WAY_MASK | 0 << _DEVCFG3_PMDL1WAY_POSITION)
& (~_DEVCFG3_IOL1WAY_MASK | 0 << _DEVCFG3_IOL1WAY_POSITION)
& (~_DEVCFG3_FUSBIDIO_MASK | 0 << _DEVCFG3_FUSBIDIO_POSITION);
volatile uint32_t ADEVCFG3_LA __attribute__((used, section(".adevcfg3_la"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG3_USERID_MASK | 0xFFFF << _DEVCFG3_USERID_POSITION)
& (~_DEVCFG3_FMIIEN_MASK | 0 << _DEVCFG3_FMIIEN_POSITION)
& (~_DEVCFG3_FETHIO_MASK | 1 << _DEVCFG3_FETHIO_POSITION)
& (~_DEVCFG3_PGL1WAY_MASK | 0 << _DEVCFG3_PGL1WAY_POSITION)
& (~_DEVCFG3_PMDL1WAY_MASK | 0 << _DEVCFG3_PMDL1WAY_POSITION)
& (~_DEVCFG3_IOL1WAY_MASK | 0 << _DEVCFG3_IOL1WAY_POSITION)
& (~_DEVCFG3_FUSBIDIO_MASK | 0 << _DEVCFG3_FUSBIDIO_POSITION);
volatile uint32_t DEVCFG3_B1 __attribute__((used, section(".devcfg3_b1"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG3_USERID_MASK | 0xFFFF << _DEVCFG3_USERID_POSITION)
& (~_DEVCFG3_FMIIEN_MASK | 0 << _DEVCFG3_FMIIEN_POSITION)
& (~_DEVCFG3_FETHIO_MASK | 1 << _DEVCFG3_FETHIO_POSITION)
& (~_DEVCFG3_PGL1WAY_MASK | 0 << _DEVCFG3_PGL1WAY_POSITION)
& (~_DEVCFG3_PMDL1WAY_MASK | 0 << _DEVCFG3_PMDL1WAY_POSITION)
& (~_DEVCFG3_IOL1WAY_MASK | 0 << _DEVCFG3_IOL1WAY_POSITION)
& (~_DEVCFG3_FUSBIDIO_MASK | 0 << _DEVCFG3_FUSBIDIO_POSITION);
volatile uint32_t ADEVCFG3_B1 __attribute__((used, section(".adevcfg3_b1"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG3_USERID_MASK | 0xFFFF << _DEVCFG3_USERID_POSITION)
& (~_DEVCFG3_FMIIEN_MASK | 0 << _DEVCFG3_FMIIEN_POSITION)
& (~_DEVCFG3_FETHIO_MASK | 1 << _DEVCFG3_FETHIO_POSITION)
& (~_DEVCFG3_PGL1WAY_MASK | 0 << _DEVCFG3_PGL1WAY_POSITION)
& (~_DEVCFG3_PMDL1WAY_MASK | 0 << _DEVCFG3_PMDL1WAY_POSITION)
& (~_DEVCFG3_IOL1WAY_MASK | 0 << _DEVCFG3_IOL1WAY_POSITION)
& (~_DEVCFG3_FUSBIDIO_MASK | 0 << _DEVCFG3_FUSBIDIO_POSITION);
/*
* Not needed by default:
* volatile uint32_t DEVCFG3_B2 __attribute__((used,section(".devcfg3_b2")))
* = DEVCFG3_LA;
* volatile uint32_t ADEVCFG3_B2 __attribute__((used,section(".adevcfg3_la")))
* = DEVCFG3_LA;
*
*/
/*
* DEVCFG2_LA @ 0x1FC0FFC4 (lower alias)
* ADEVFGC2_LA @ 0x1FC0FF44 (alternate devcfg2 in lower alias)
* DEVCFG2_B1 @ 0x1FC4FFC4 (config space 1)
* ADEVCFG2_B1 @ 0x1FC4FF44 (alternate devcfg2 in config space 1)
* DEVCFG2_B2 @ 0x1FC6FFC4 (config space 1)
* ADEVCFG2_B2 @ 0x1FC6FF44 (alternate devcfg2 in config space 2)
*
* 24MHz OSC / 3 * 50 / 2 = 200MHz
*
* FPLLIDIV DIV_3 System PLL Input Divider 3x Divider
* FPLLRNG RANGE_5_10_MHZ System PLL Input Range 5-10 MHz Input
* FPLLICLK PLL_POSC System PLL Input Clock Selection POSC is input to the System PLL
* FPLLMULT MUL_50 System PLL Multiplier PLL Multiply by 50
* FPLLODIV DIV_2 System PLL Output Clock Divider 2x Divider
* UPLLFSEL FREQ_24MHZ USB PLL Input Frequency Selection USB PLL input is 24 MHz
*/
volatile uint32_t DEVCFG2_LA __attribute__ ((used, section(".devcfg2_la"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG2_FPLLIDIV_MASK | 2 << _DEVCFG2_FPLLIDIV_POSITION)
& (~_DEVCFG2_FPLLRNG_MASK | 0x1 << _DEVCFG2_FPLLRNG_POSITION)
& (~_DEVCFG2_FPLLICLK_MASK | 0x0 << _DEVCFG2_FPLLICLK_POSITION)
& (~_DEVCFG2_FPLLMULT_MASK | 49 << _DEVCFG2_FPLLMULT_POSITION)
& (~_DEVCFG2_FPLLODIV_MASK | 1 << _DEVCFG2_FPLLODIV_POSITION)
& (~_DEVCFG2_UPLLFSEL_MASK | 0x1 << _DEVCFG2_UPLLFSEL_POSITION);
volatile uint32_t ADEVCFG2_LA __attribute__ ((used, section(".adevcfg2_la"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG2_FPLLIDIV_MASK | 2 << _DEVCFG2_FPLLIDIV_POSITION)
& (~_DEVCFG2_FPLLRNG_MASK | 0x1 << _DEVCFG2_FPLLRNG_POSITION)
& (~_DEVCFG2_FPLLICLK_MASK | 0x0 << _DEVCFG2_FPLLICLK_POSITION)
& (~_DEVCFG2_FPLLMULT_MASK | 49 << _DEVCFG2_FPLLMULT_POSITION)
& (~_DEVCFG2_FPLLODIV_MASK | 1 << _DEVCFG2_FPLLODIV_POSITION)
& (~_DEVCFG2_UPLLFSEL_MASK | 0x1 << _DEVCFG2_UPLLFSEL_POSITION);
volatile uint32_t DEVCFG2_B1 __attribute__ ((used, section(".devcfg2_b1"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG2_FPLLIDIV_MASK | 2 << _DEVCFG2_FPLLIDIV_POSITION)
& (~_DEVCFG2_FPLLRNG_MASK | 0x1 << _DEVCFG2_FPLLRNG_POSITION)
& (~_DEVCFG2_FPLLICLK_MASK | 0x0 << _DEVCFG2_FPLLICLK_POSITION)
& (~_DEVCFG2_FPLLMULT_MASK | 49 << _DEVCFG2_FPLLMULT_POSITION)
& (~_DEVCFG2_FPLLODIV_MASK | 1 << _DEVCFG2_FPLLODIV_POSITION)
& (~_DEVCFG2_UPLLFSEL_MASK | 0x1 << _DEVCFG2_UPLLFSEL_POSITION);
volatile uint32_t ADEVCFG2_B1 __attribute__ ((used, section(".adevcfg2_b1"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG2_FPLLIDIV_MASK | 2 << _DEVCFG2_FPLLIDIV_POSITION)
& (~_DEVCFG2_FPLLRNG_MASK | 0x1 << _DEVCFG2_FPLLRNG_POSITION)
& (~_DEVCFG2_FPLLICLK_MASK | 0x0 << _DEVCFG2_FPLLICLK_POSITION)
& (~_DEVCFG2_FPLLMULT_MASK | 49 << _DEVCFG2_FPLLMULT_POSITION)
& (~_DEVCFG2_FPLLODIV_MASK | 1 << _DEVCFG2_FPLLODIV_POSITION)
& (~_DEVCFG2_UPLLFSEL_MASK | 0x1 << _DEVCFG2_UPLLFSEL_POSITION);
/* Not needed by default: */
/* uint32_t DEVCFG2_B2 __attribute__ ((section(".devcfg2_b2"))) = DEVCFG2_LA; */
/* uint32_t ADEVCFG2_B2 __attribute__ ((section(".adevcfg2_b2"))) = DEVCFG2_LA; */
/*
* DEVCFG1_LA @ 0x1FC0FFC8 (lower alias)
* ADEVFGC1_LA @ 0x1FC0FF48 (alternate devcfg1 in lower alias)
* DEVCFG1_B1 @ 0x1FC4FFC8 (config space 1)
* ADEVCFG1_B1 @ 0x1FC4FF48 (alternate devcfg1 in config space 1)
* DEVCFG1_B2 @ 0x1FC6FFC8 (config space 1)
* ADEVCFG1_B2 @ 0x1FC6FF48 (alternate devcfg1 in config space 2)
*
* FNOSC SPLL Oscillator Selection Bits System PLL
* DMTINTV WIN_127_128 DMT Count Window Interval Window/Interval value is 127/128 counter value
* FSOSCEN OFF Secondary Oscillator Enable Disable SOSC
* IESO ON Internal/External Switch Over Enabled
* POSCMOD EC Primary Oscillator Configuration External clock mode
* OSCIOFNC OFF CLKO Output Signal Active on the OSCO Pin Disabled (1)
* FCKSM CSDCMD Clock Switching and Monitor Selection Clock Switch Disabled, FSCM Disabled
* WDTPS PS1048576 Watchdog Timer Postscaler 1:1048576
* WDTSPGM STOP Watchdog Timer Stop During Flash Programming WDT stops during Flash programming
* WINDIS NORMAL Watchdog Timer Window Mode Watchdog Timer is in non-Window mode
* FWDTEN OFF Watchdog Timer Enable WDT Disabled
* FWDTWINSZ WINSZ_25 Watchdog Timer Window Size Window size is 25%
* DMTCNT DMT8 Deadman Timer Count Selection 2^8 (256)
* FDMTEN OFF Deadman Timer Enable Deadman Timer is disabled
*/
volatile uint32_t DEVCFG1_LA __attribute__ ((used, section(".devcfg1_la"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG1_FNOSC_MASK | 0x1 << _DEVCFG1_FNOSC_POSITION)
& (~_DEVCFG1_DMTINTV_MASK | 0x7 << _DEVCFG1_DMTINTV_POSITION)
& (~_DEVCFG1_FSOSCEN_MASK | 0 << _DEVCFG1_FSOSCEN_POSITION)
& (~_DEVCFG1_IESO_MASK | 1 << _DEVCFG1_IESO_POSITION)
& (~_DEVCFG1_POSCMOD_MASK | 0x0 << _DEVCFG1_POSCMOD_POSITION)
& (~_DEVCFG1_OSCIOFNC_MASK | 1 << _DEVCFG1_OSCIOFNC_POSITION)
& (~_DEVCFG1_FCKSM_MASK | 0x0 << _DEVCFG1_FCKSM_POSITION)
& (~_DEVCFG1_WDTPS_MASK | 0x14 << _DEVCFG1_WDTPS_POSITION)
& (~_DEVCFG1_WDTSPGM_MASK | 1 << _DEVCFG1_WDTSPGM_POSITION)
& (~_DEVCFG1_WINDIS_MASK | 1 << _DEVCFG1_WINDIS_POSITION)
& (~_DEVCFG1_FWDTEN_MASK | 0 << _DEVCFG1_FWDTEN_POSITION)
& (~_DEVCFG1_FWDTWINSZ_MASK | 0x3 << _DEVCFG1_FWDTWINSZ_POSITION)
& (~_DEVCFG1_DMTCNT_MASK | 0x0 << _DEVCFG1_DMTCNT_POSITION)
& (~_DEVCFG1_FDMTEN_MASK | 0 << _DEVCFG1_FDMTEN_POSITION);
volatile uint32_t ADEVCFG1_LA __attribute__ ((used, section(".adevcfg1_la"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG1_FNOSC_MASK | 0x1 << _DEVCFG1_FNOSC_POSITION)
& (~_DEVCFG1_DMTINTV_MASK | 0x7 << _DEVCFG1_DMTINTV_POSITION)
& (~_DEVCFG1_FSOSCEN_MASK | 0 << _DEVCFG1_FSOSCEN_POSITION)
& (~_DEVCFG1_IESO_MASK | 1 << _DEVCFG1_IESO_POSITION)
& (~_DEVCFG1_POSCMOD_MASK | 0x0 << _DEVCFG1_POSCMOD_POSITION)
& (~_DEVCFG1_OSCIOFNC_MASK | 1 << _DEVCFG1_OSCIOFNC_POSITION)
& (~_DEVCFG1_FCKSM_MASK | 0x0 << _DEVCFG1_FCKSM_POSITION)
& (~_DEVCFG1_WDTPS_MASK | 0x14 << _DEVCFG1_WDTPS_POSITION)
& (~_DEVCFG1_WDTSPGM_MASK | 1 << _DEVCFG1_WDTSPGM_POSITION)
& (~_DEVCFG1_WINDIS_MASK | 1 << _DEVCFG1_WINDIS_POSITION)
& (~_DEVCFG1_FWDTEN_MASK | 0 << _DEVCFG1_FWDTEN_POSITION)
& (~_DEVCFG1_FWDTWINSZ_MASK | 0x3 << _DEVCFG1_FWDTWINSZ_POSITION)
& (~_DEVCFG1_DMTCNT_MASK | 0x0 << _DEVCFG1_DMTCNT_POSITION)
& (~_DEVCFG1_FDMTEN_MASK | 0 << _DEVCFG1_FDMTEN_POSITION);
volatile uint32_t DEVCFG1_B1 __attribute__ ((used, section(".devcfg1_b1"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG1_FNOSC_MASK | 0x1 << _DEVCFG1_FNOSC_POSITION)
& (~_DEVCFG1_DMTINTV_MASK | 0x7 << _DEVCFG1_DMTINTV_POSITION)
& (~_DEVCFG1_FSOSCEN_MASK | 0 << _DEVCFG1_FSOSCEN_POSITION)
& (~_DEVCFG1_IESO_MASK | 1 << _DEVCFG1_IESO_POSITION)
& (~_DEVCFG1_POSCMOD_MASK | 0x0 << _DEVCFG1_POSCMOD_POSITION)
& (~_DEVCFG1_OSCIOFNC_MASK | 1 << _DEVCFG1_OSCIOFNC_POSITION)
& (~_DEVCFG1_FCKSM_MASK | 0x0 << _DEVCFG1_FCKSM_POSITION)
& (~_DEVCFG1_WDTPS_MASK | 0x14 << _DEVCFG1_WDTPS_POSITION)
& (~_DEVCFG1_WDTSPGM_MASK | 1 << _DEVCFG1_WDTSPGM_POSITION)
& (~_DEVCFG1_WINDIS_MASK | 1 << _DEVCFG1_WINDIS_POSITION)
& (~_DEVCFG1_FWDTEN_MASK | 0 << _DEVCFG1_FWDTEN_POSITION)
& (~_DEVCFG1_FWDTWINSZ_MASK | 0x3 << _DEVCFG1_FWDTWINSZ_POSITION)
& (~_DEVCFG1_DMTCNT_MASK | 0x0 << _DEVCFG1_DMTCNT_POSITION)
& (~_DEVCFG1_FDMTEN_MASK | 0 << _DEVCFG1_FDMTEN_POSITION);
volatile uint32_t ADEVCFG1_B1 __attribute__ ((used, section(".adevcfg1_b1"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG1_FNOSC_MASK | 0x1 << _DEVCFG1_FNOSC_POSITION)
& (~_DEVCFG1_DMTINTV_MASK | 0x7 << _DEVCFG1_DMTINTV_POSITION)
& (~_DEVCFG1_FSOSCEN_MASK | 0 << _DEVCFG1_FSOSCEN_POSITION)
& (~_DEVCFG1_IESO_MASK | 1 << _DEVCFG1_IESO_POSITION)
& (~_DEVCFG1_POSCMOD_MASK | 0x0 << _DEVCFG1_POSCMOD_POSITION)
& (~_DEVCFG1_OSCIOFNC_MASK | 1 << _DEVCFG1_OSCIOFNC_POSITION)
& (~_DEVCFG1_FCKSM_MASK | 0x0 << _DEVCFG1_FCKSM_POSITION)
& (~_DEVCFG1_WDTPS_MASK | 0x14 << _DEVCFG1_WDTPS_POSITION)
& (~_DEVCFG1_WDTSPGM_MASK | 1 << _DEVCFG1_WDTSPGM_POSITION)
& (~_DEVCFG1_WINDIS_MASK | 1 << _DEVCFG1_WINDIS_POSITION)
& (~_DEVCFG1_FWDTEN_MASK | 0 << _DEVCFG1_FWDTEN_POSITION)
& (~_DEVCFG1_FWDTWINSZ_MASK | 0x3 << _DEVCFG1_FWDTWINSZ_POSITION)
& (~_DEVCFG1_DMTCNT_MASK | 0x0 << _DEVCFG1_DMTCNT_POSITION)
& (~_DEVCFG1_FDMTEN_MASK | 0 << _DEVCFG1_FDMTEN_POSITION);
/* Not needed by default: */
/* uint32_t DEVCFG1_B2 __attribute__ ((section(".devcfg1_b2"))) = DEVCFG1_LA; */
/* uint32_t ADEVCFG1_B2 __attribute__ ((section(".adevcfg1_b2"))) = DEVCFG1_LA */
/*
* DEVCFG0_LA @ 0x1FC0FFCC (lower alias)
* ADEVFGC0_LA @ 0x1FC0FF4C (alternate devcfg0 in lower alias)
* DEVCFG0_B1 @ 0x1FC4FFCC (config space 1)
* ADEVCFG0_B1 @ 0x1FC4FF4C (alternate devcfg0 in config space 1)
* DEVCFG0_B2 @ 0x1FC6FFCC (config space 1)
* ADEVCFG0_B2 @ 0x1FC6FF4C (alternate devcfg0 in config space 2)
*
* DEBUG OFF Background Debugger Enable Debugger is disabled
* JTAGEN ON JTAG Enable JTAG Port Enabled
* ICESEL ICS_PGx2 ICE/ICD Comm Channel Select Communicate on PGEC2/PGED2
* TRCEN ON Trace Enable Trace features in the CPU are disabled
* BOOTISA MIPS32 Boot ISA Selection Boot code and Exception code is MIPS32
* FECCCON OFF_UNLOCKED Dynamic Flash ECC Configuration ECC and Dynamic ECC are disabled (ECCCON bits are writable)
* FSLEEP OFF Flash Sleep Mode Flash is powered down when the device is in Sleep mode
* DBGPER PG_ALL Debug Mode CPU Access Permission Allow CPU access to all permission regions
* SMCLR MCLR_NORM Soft Master Clear Enable bit MCLR pin generates a normal system Reset
* SOSCGAIN GAIN_2X Secondary Oscillator Gain Control bits 2x gain setting
* SOSCBOOST ON Secondary Oscillator Boost Kick Start Enable bit Boost the kick start of the oscillator
* POSCGAIN GAIN_2X Primary Oscillator Gain Control bits 2x gain setting
* POSCBOOST ON Primary Oscillator Boost Kick Start Enable bit Boost the kick start of the oscillator
* EJTAGBEN NORMAL EJTAG Boot Normal EJTAG functionality
*/
volatile uint32_t DEVCFG0_LA __attribute__ ((used, section(".devcfg0_la"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG0_DEBUG_MASK | 0x3 << _DEVCFG0_DEBUG_POSITION)
& (~_DEVCFG0_JTAGEN_MASK | 0x1 << _DEVCFG0_JTAGEN_POSITION)
& (~_DEVCFG0_ICESEL_MASK | 0x2 << _DEVCFG0_ICESEL_POSITION)
& (~_DEVCFG0_TRCEN_MASK | 0x1 << _DEVCFG0_TRCEN_POSITION)
& (~_DEVCFG0_BOOTISA_MASK | 0x1 << _DEVCFG0_BOOTISA_POSITION)
& (~_DEVCFG0_FECCCON_MASK | 0x3 << _DEVCFG0_FECCCON_POSITION)
& (~_DEVCFG0_FSLEEP_MASK | 0x1 << _DEVCFG0_FSLEEP_POSITION)
& (~_DEVCFG0_DBGPER_MASK | 0x7 << _DEVCFG0_DBGPER_POSITION)
& (~_DEVCFG0_SMCLR_MASK | 0x1 << _DEVCFG0_SMCLR_POSITION)
& (~_DEVCFG0_SOSCGAIN_MASK | 0x2 << _DEVCFG0_SOSCGAIN_POSITION)
& (~_DEVCFG0_SOSCBOOST_MASK | 0x1 << _DEVCFG0_SOSCBOOST_POSITION)
& (~_DEVCFG0_POSCGAIN_MASK | 0x2 << _DEVCFG0_POSCGAIN_POSITION)
& (~_DEVCFG0_POSCBOOST_MASK | 0x1 << _DEVCFG0_POSCBOOST_POSITION)
& (~_DEVCFG0_EJTAGBEN_MASK | 0x1 << _DEVCFG0_EJTAGBEN_POSITION);
volatile uint32_t ADEVCFG0_LA __attribute__ ((used, section(".adevcfg0_la"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG0_DEBUG_MASK | 0x3 << _DEVCFG0_DEBUG_POSITION)
& (~_DEVCFG0_JTAGEN_MASK | 0x1 << _DEVCFG0_JTAGEN_POSITION)
& (~_DEVCFG0_ICESEL_MASK | 0x2 << _DEVCFG0_ICESEL_POSITION)
& (~_DEVCFG0_TRCEN_MASK | 0x1 << _DEVCFG0_TRCEN_POSITION)
& (~_DEVCFG0_BOOTISA_MASK | 0x1 << _DEVCFG0_BOOTISA_POSITION)
& (~_DEVCFG0_FECCCON_MASK | 0x3 << _DEVCFG0_FECCCON_POSITION)
& (~_DEVCFG0_FSLEEP_MASK | 0x1 << _DEVCFG0_FSLEEP_POSITION)
& (~_DEVCFG0_DBGPER_MASK | 0x7 << _DEVCFG0_DBGPER_POSITION)
& (~_DEVCFG0_SMCLR_MASK | 0x1 << _DEVCFG0_SMCLR_POSITION)
& (~_DEVCFG0_SOSCGAIN_MASK | 0x2 << _DEVCFG0_SOSCGAIN_POSITION)
& (~_DEVCFG0_SOSCBOOST_MASK | 0x1 << _DEVCFG0_SOSCBOOST_POSITION)
& (~_DEVCFG0_POSCGAIN_MASK | 0x2 << _DEVCFG0_POSCGAIN_POSITION)
& (~_DEVCFG0_POSCBOOST_MASK | 0x1 << _DEVCFG0_POSCBOOST_POSITION)
& (~_DEVCFG0_EJTAGBEN_MASK | 0x1 << _DEVCFG0_EJTAGBEN_POSITION);
volatile uint32_t DEVCFG0_B1 __attribute__ ((used, section(".devcfg0_b1"))) =
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG0_DEBUG_MASK | 0x3 << _DEVCFG0_DEBUG_POSITION)
& (~_DEVCFG0_JTAGEN_MASK | 0x1 << _DEVCFG0_JTAGEN_POSITION)
& (~_DEVCFG0_ICESEL_MASK | 0x2 << _DEVCFG0_ICESEL_POSITION)
& (~_DEVCFG0_TRCEN_MASK | 0x1 << _DEVCFG0_TRCEN_POSITION)
& (~_DEVCFG0_BOOTISA_MASK | 0x1 << _DEVCFG0_BOOTISA_POSITION)
& (~_DEVCFG0_FECCCON_MASK | 0x3 << _DEVCFG0_FECCCON_POSITION)
& (~_DEVCFG0_FSLEEP_MASK | 0x1 << _DEVCFG0_FSLEEP_POSITION)
& (~_DEVCFG0_DBGPER_MASK | 0x7 << _DEVCFG0_DBGPER_POSITION)
& (~_DEVCFG0_SMCLR_MASK | 0x1 << _DEVCFG0_SMCLR_POSITION)
& (~_DEVCFG0_SOSCGAIN_MASK | 0x2 << _DEVCFG0_SOSCGAIN_POSITION)
& (~_DEVCFG0_SOSCBOOST_MASK | 0x1 << _DEVCFG0_SOSCBOOST_POSITION)
& (~_DEVCFG0_POSCGAIN_MASK | 0x2 << _DEVCFG0_POSCGAIN_POSITION)
& (~_DEVCFG0_POSCBOOST_MASK | 0x1 << _DEVCFG0_POSCBOOST_POSITION)
& (~_DEVCFG0_EJTAGBEN_MASK | 0x1 << _DEVCFG0_EJTAGBEN_POSITION);
volatile uint32_t ADEVCFG0_B1 __attribute__ ((used, section(".adevcfg0_b1")))=
0xffffffff /* unused bits must be 1 */
& (~_DEVCFG0_DEBUG_MASK | 0x3 << _DEVCFG0_DEBUG_POSITION)
& (~_DEVCFG0_JTAGEN_MASK | 0x1 << _DEVCFG0_JTAGEN_POSITION)
& (~_DEVCFG0_ICESEL_MASK | 0x2 << _DEVCFG0_ICESEL_POSITION)
& (~_DEVCFG0_TRCEN_MASK | 0x1 << _DEVCFG0_TRCEN_POSITION)
& (~_DEVCFG0_BOOTISA_MASK | 0x1 << _DEVCFG0_BOOTISA_POSITION)
& (~_DEVCFG0_FECCCON_MASK | 0x3 << _DEVCFG0_FECCCON_POSITION)
& (~_DEVCFG0_FSLEEP_MASK | 0x1 << _DEVCFG0_FSLEEP_POSITION)
& (~_DEVCFG0_DBGPER_MASK | 0x7 << _DEVCFG0_DBGPER_POSITION)
& (~_DEVCFG0_SMCLR_MASK | 0x1 << _DEVCFG0_SMCLR_POSITION)
& (~_DEVCFG0_SOSCGAIN_MASK | 0x2 << _DEVCFG0_SOSCGAIN_POSITION)
& (~_DEVCFG0_SOSCBOOST_MASK | 0x1 << _DEVCFG0_SOSCBOOST_POSITION)
& (~_DEVCFG0_POSCGAIN_MASK | 0x2 << _DEVCFG0_POSCGAIN_POSITION)
& (~_DEVCFG0_POSCBOOST_MASK | 0x1 << _DEVCFG0_POSCBOOST_POSITION)
& (~_DEVCFG0_EJTAGBEN_MASK | 0x1 << _DEVCFG0_EJTAGBEN_POSITION);
/*
* uint32_t DEVCFG0_B2 __attribute__ ((section(".devcfg0_b2")))
* = 0xFFFFF7D7;
* uint32_t ADEVCFG0_B2 __attribute__ ((section(".adevcfg0_b2")))
* = 0xFFFFF7D7;
*
*/
/*
* DEVCP0_LA @ 0x1FC0FFDC (lower alias)
* ADEVCP0_LA @ 0x1FC0FF5C (alternate devcp0 in lower alias)
* DEVCP0_B1 @ 0x1FC4FFDC (config space 1)
* ADEVCP0_B1 @ 0x1FC4FF5C (alternate devcp0 in config space 1)
* DEVCP0_B2 @ 0x1FC6FFDC (config space 1)
* ADEVCP0_B2 @ 0x1FC6FF5C (alternate devcp0 in config space 2
*
* CP OFF Code Protect Protection Disabled, unused bits must be 1.
*/
volatile uint32_t DEVCP0_LA __attribute__ ((used, section(".devcp0_la"))) =
0xFFFFFFFF | _DEVCP0_CP_MASK;
volatile uint32_t ADEVCP0_LA __attribute__ ((used, section(".adevcp0_la"))) =
0xFFFFFFFF | _DEVCP0_CP_MASK;
volatile uint32_t DEVCP0_B1 __attribute__ ((used, section(".devcp0_b1"))) =
0xFFFFFFFF | _DEVCP0_CP_MASK;
volatile uint32_t ADEVCP0_B1 __attribute__ ((used, section(".adevcp0_b1"))) =
0xFFFFFFFF | _DEVCP0_CP_MASK;
/* not needed by default */
/* uint32_t DEVCP0_B2 __attribute__ ((section(".devcp0_b1"))) = 0xFFFFFFFF; */
/* uint32_t ADEVCP0_B2 __attribute__ ((section(".adevcp0_b1"))) = 0xFFFFFFFF; */
/*
* SEQ_B1[0..3] @ 1FC0FFF0
* SEQ_B1[0..3] @ 1FC4FFF0
*
* TSEQ Boot Flash True Sequence Number
* CSEQ Boot Flash Complement Sequence Number
*/
volatile uint32_t SEQ_LA[4] __attribute__ ((used, section(".seq_la"))) =
{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF };
volatile uint32_t SEQ_B1[4] __attribute__ ((used, section(".seq_b1"))) =
{ 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF };
/*
* Not needed by default:
* uint32_t SEQ_B2[4] __attribute__ ((section(".seq_b2"))) =
* {0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF};
*/
/*
* STUPIDLY Microchip has hard coded the MSB bit of devsign to 0, So even if
* you erase the whole device, everything returns 0xFFFFFFF except this 1
* register (and its alternate) which return 0x7FFFFFF!!
*
* We set it in the output image so verification doesn't fail
*
* DEVSIGN0 @ 0xBFC0FFEC
* ADEVSIGN0 @ 0xBFC0FF6C
*
*/
volatile uint32_t DEVSIGN_LA __attribute__ ((used, section(".devsign_la"))) = 0x7FFFFFFF;
volatile uint32_t ADEVSIGN_LA __attribute__ ((used, section(".adevsign_la"))) = 0x7FFFFFFF;
volatile uint32_t DEVSIGN_B1 __attribute__ ((used, section(".devsign_b1"))) = 0x7FFFFFFF;
volatile uint32_t ADEVSIGN_B1 __attribute__ ((used, section(".adevsign_b1"))) = 0x7FFFFFFF;
volatile uint32_t DEVSIGN_B2 __attribute__ ((used, section(".devsign_b2"))) = 0x7FFFFFFF;
volatile uint32_t ADEVSIGN_B2 __attribute__ ((used, section(".adevsign_b2"))) = 0x7FFFFFFF;
/*
* Without a reference to this function from elsewhere LD throws the whole
* compile unit away even though the data is 'volatile' and 'used' !!!
*/
void dummy(void)
{
(void)1;
}

24
boards/pic32-wifire/wifire.c
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@ -1,24 +0,0 @@
/*
* Copyright(C) 2016,2017, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
#include <stdint.h>
#include "periph/gpio.h"
#include "periph/hwrng.h"
#include "bitarithm.h"
#include "board.h"
#include "cpu.h"
extern void dummy(void);
void board_init(void)
{
/* Stop the linker from throwing away the PIC32 config register settings */
dummy();
}

38
cpu/mips32r2_common/Kconfig
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@ -1,38 +0,0 @@
# Copyright (c) 2020 HAW Hamburg
#
# This file is subject to the terms and conditions of the GNU Lesser
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.
#
config CPU_ARCH_MIPS32R2
bool
select HAS_ARCH_32BIT
select HAS_ARCH_MIPS32R2
select HAS_NEWLIB
select HAS_CPP
select HAS_LIBSTDCPP
select HAS_PERIPH_PM
select MODULE_MALLOC_THREAD_SAFE if TEST_KCONFIG
config CPU_CORE_M4K
bool
select CPU_ARCH_MIPS32R2
config CPU_CORE_M5101
bool
select CPU_ARCH_MIPS32R2
## Declaration of specific features
config HAS_ARCH_MIPS32R2
bool
help
Indicates that the current architecture is 'mips32r2'.
## Common CPU symbols
config CPU_ARCH
default "mips32r2" if CPU_ARCH_MIPS32R2
config CPU_CORE
default "m4k" if CPU_CORE_M4K
default "m5101" if CPU_CORE_M5101

9
cpu/mips32r2_common/Makefile
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@ -1,9 +0,0 @@
MODULE = mips32r2_common
DIRS = periph
ifneq (,$(filter newlib_syscalls_mips_uhi,$(USEMODULE)))
DIRS += newlib_syscalls_mips_uhi
endif
include $(RIOTBASE)/Makefile.base

14
cpu/mips32r2_common/Makefile.dep
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@ -1,14 +0,0 @@
USEMODULE += mips32r2_common
USEMODULE += mips32r2_common_periph
FEATURES_REQUIRED += newlib
# mips32 needs periph_timer for its gettimeofday() implementation
FEATURES_REQUIRED += periph_timer
#Use RIOT to handle syscalls (default)
ifeq (,$(filter newlib_syscalls_mips_uhi,$(USEMODULE)))
USEMODULE += newlib_syscalls_default
endif
# Make calls to malloc and friends thread-safe
USEMODULE += malloc_thread_safe

8
cpu/mips32r2_common/Makefile.features
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@ -1,8 +0,0 @@
CPU_ARCH = mips32r2
FEATURES_PROVIDED += arch_32bit
FEATURES_PROVIDED += arch_mips32r2
FEATURES_PROVIDED += newlib
FEATURES_PROVIDED += cpp
FEATURES_PROVIDED += libstdcpp
FEATURES_PROVIDED += periph_pm

6
cpu/mips32r2_common/Makefile.include
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@ -1,6 +0,0 @@
INCLUDES += -I$(RIOTCPU)/mips32r2_common/include
ifneq (,$(filter newlib_syscalls_mips_uhi,$(USEMODULE)))
CFLAGS += -DHAVE_HEAP_STATS
LINKFLAGS += -luhi
endif

120
cpu/mips32r2_common/cpu.c
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@ -1,120 +0,0 @@
/*
* Copyright 2016, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
#include <mips/hal.h>
#include <mips/m32c0.h>
#include <mips/regdef.h>
#include <mips/asm.h>
#include <stdio.h>
#include <string.h>
#include <assert.h>
#include <malloc.h>
#include "periph/uart.h"
#include "periph/timer.h"
#include "periph/init.h"
#include "panic.h"
#include "stdio_base.h"
#include "kernel_init.h"
#include "cpu.h"
#include "board.h"
void mips_start(void);
extern void _fini(void);
extern void atexit(void (*)(void));
extern void _init(void);
extern void exit(int);
#ifdef FLASH_XIP
extern char _rom_data_copy __attribute__((section("data")));
extern char _fdata __attribute__((section("data")));
extern char _edata __attribute__((section("data")));
#endif
/*
* Note the mips toolchain crt expects to jump to main but RIOT wants the user
* code to start at main for some perverse reason, but thankfully the crt
* does provide this hook function which gets called fairly close to the jump
* to main, thus if we finish off the job of the crt here and never returns
* we can support this madness.
*/
void software_init_hook(void)
{
#ifdef FLASH_XIP
/* copy initialized data from its LMA to VMA */
memcpy(&_fdata, &_rom_data_copy, (int)&_edata - (int)&_fdata);
#endif
atexit(_fini);
_init();
mips_start();
exit(-1);
}
void cpu_init(void)
{
/* initialize stdio*/
stdio_init();
/* trigger static peripheral initialization */
periph_init();
}
void mips_start(void)
{
cpu_init();
board_init();
/* kernel_init */
kernel_init();
}
void panic_arch(void)
{
printf("\nPANIC!\n");
assert(0);
while (1) {
}
}
#ifdef MODULE_NEWLIB_SYSCALLS_DEFAULT
void heap_stats(void)
{
puts("heap statistics are not supported for newlib_syscalls_default");
}
#else
extern char _end[]; /* defined in linker script */
void heap_stats(void)
{
void *ram_base;
void *ram_extent;
unsigned long heap_size;
_get_ram_range (&ram_base, &ram_extent);
/* If the _end symbol is within the RAM then use _end. */
if ((void*)_end > ram_base && (void*)_end < ram_extent) {
heap_size = ram_extent - (void*)_end;
}
else {
heap_size = ram_extent - ram_base;
}
struct mallinfo minfo = mallinfo();
printf("heap: %lu (used %lu, free %lu) [bytes]\n",
heap_size, minfo.uordblks, heap_size - minfo.uordblks);
}
#endif

37
cpu/mips32r2_common/include/architecture_arch.h
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@ -1,37 +0,0 @@
/*
* Copyright (C) 2020 Otto-von-Guericke-Universität Magdeburg
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_mips32r2_common
* @{
*
* @file
* @brief Architecture details
*
* @author Marian Buschsieweke <marian.buschsieweke@ovgu.de>
*
*/
#ifndef ARCHITECTURE_ARCH_H
#define ARCHITECTURE_ARCH_H
#ifdef __cplusplus
extern "C" {
#endif
/* Doc is provided centrally in architecture.h, hide this from Doxygen */
#ifndef DOXYGEN
#define ARCHITECTURE_WORD_BITS (32U)
#endif /* DOXYGEN */
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* ARCHITECTURE_ARCH_H */

76
cpu/mips32r2_common/include/atomic_utils_arch.h
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@ -1,76 +0,0 @@
/*
* Copyright (C) 2020 Otto-von-Guericke-Universität Magdeburg
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_mips32r2_common
*
* @{
*
* @file
* @brief Implementation of fast atomic utility functions
* @author Marian Buschsieweke <marian.buschsieweke@ovgu.de>
*/
#ifndef ATOMIC_UTILS_ARCH_H
#define ATOMIC_UTILS_ARCH_H
#ifndef DOXYGEN
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/* clang provides no built-in atomic access to regular variables */
#ifndef __clang__
#define HAS_ATOMIC_LOAD_U8
static inline uint8_t atomic_load_u8(const volatile uint8_t *var)
{
return __atomic_load_1(var, __ATOMIC_SEQ_CST);
}
#define HAS_ATOMIC_LOAD_U16
static inline uint16_t atomic_load_u16(const volatile uint16_t *var)
{
return __atomic_load_2(var, __ATOMIC_SEQ_CST);
}
#define HAS_ATOMIC_LOAD_U32
static inline uint32_t atomic_load_u32(const volatile uint32_t *var)
{
return __atomic_load_4(var, __ATOMIC_SEQ_CST);
}
#define HAS_ATOMIC_STORE_U8
static inline void atomic_store_u8(volatile uint8_t *dest, uint8_t val)
{
__atomic_store_1(dest, val, __ATOMIC_SEQ_CST);
}
#define HAS_ATOMIC_STORE_U16
static inline void atomic_store_u16(volatile uint16_t *dest, uint16_t val)
{
__atomic_store_2(dest, val, __ATOMIC_SEQ_CST);
}
#define HAS_ATOMIC_STORE_U32
static inline void atomic_store_u32(volatile uint32_t *dest, uint32_t val)
{
__atomic_store_4(dest, val, __ATOMIC_SEQ_CST);
}
#endif /* __clang__ */
#ifdef __cplusplus
}
#endif
#endif /* DOXYGEN */
#endif /* ATOMIC_UTILS_ARCH_H */
/** @} */

71
cpu/mips32r2_common/include/c11_atomics_compat_cpu.hpp
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@ -1,71 +0,0 @@
/* This file was automatically generated using ./dist/tools/generate_c11_atomics_cpp_compat_header/generate_c11_atomics_cpp_compat_header.sh */
#pragma once
#define ATOMIC_BOOL_SIZE (1U)
#define ATOMIC_BOOL_SAME_SIZED_TYPE uint8_t
#define ATOMIC_CHAR_SIZE (1U)
#define ATOMIC_CHAR_SAME_SIZED_TYPE uint8_t
#define ATOMIC_SCHAR_SIZE (1U)
#define ATOMIC_SCHAR_SAME_SIZED_TYPE uint8_t
#define ATOMIC_UCHAR_SIZE (1U)
#define ATOMIC_UCHAR_SAME_SIZED_TYPE uint8_t
#define ATOMIC_SHORT_SIZE (2U)
#define ATOMIC_SHORT_SAME_SIZED_TYPE uint16_t
#define ATOMIC_USHORT_SIZE (2U)
#define ATOMIC_USHORT_SAME_SIZED_TYPE uint16_t
#define ATOMIC_INT_SIZE (4U)
#define ATOMIC_INT_SAME_SIZED_TYPE uint32_t
#define ATOMIC_UINT_SIZE (4U)
#define ATOMIC_UINT_SAME_SIZED_TYPE uint32_t
#define ATOMIC_LONG_SIZE (4U)
#define ATOMIC_LONG_SAME_SIZED_TYPE uint32_t
#define ATOMIC_ULONG_SIZE (4U)
#define ATOMIC_ULONG_SAME_SIZED_TYPE uint32_t
#define ATOMIC_LLONG_SIZE (8U)
#define ATOMIC_LLONG_SAME_SIZED_TYPE uint64_t
#define ATOMIC_ULLONG_SIZE (8U)
#define ATOMIC_ULLONG_SAME_SIZED_TYPE uint64_t
#define ATOMIC_INT_LEAST8_T_SIZE (1U)
#define ATOMIC_INT_LEAST8_T_SAME_SIZED_TYPE uint8_t
#define ATOMIC_UINT_LEAST8_T_SIZE (1U)
#define ATOMIC_UINT_LEAST8_T_SAME_SIZED_TYPE uint8_t
#define ATOMIC_INT_LEAST16_T_SIZE (2U)
#define ATOMIC_INT_LEAST16_T_SAME_SIZED_TYPE uint16_t
#define ATOMIC_UINT_LEAST16_T_SIZE (2U)
#define ATOMIC_UINT_LEAST16_T_SAME_SIZED_TYPE uint16_t
#define ATOMIC_INT_LEAST32_T_SIZE (4U)
#define ATOMIC_INT_LEAST32_T_SAME_SIZED_TYPE uint32_t
#define ATOMIC_UINT_LEAST32_T_SIZE (4U)
#define ATOMIC_UINT_LEAST32_T_SAME_SIZED_TYPE uint32_t
#define ATOMIC_INT_LEAST64_T_SIZE (8U)
#define ATOMIC_INT_LEAST64_T_SAME_SIZED_TYPE uint64_t
#define ATOMIC_UINT_LEAST64_T_SIZE (8U)
#define ATOMIC_UINT_LEAST64_T_SAME_SIZED_TYPE uint64_t
#define ATOMIC_INT_FAST8_T_SIZE (4U)
#define ATOMIC_INT_FAST8_T_SAME_SIZED_TYPE uint32_t
#define ATOMIC_UINT_FAST8_T_SIZE (4U)
#define ATOMIC_UINT_FAST8_T_SAME_SIZED_TYPE uint32_t
#define ATOMIC_INT_FAST16_T_SIZE (4U)
#define ATOMIC_INT_FAST16_T_SAME_SIZED_TYPE uint32_t
#define ATOMIC_UINT_FAST16_T_SIZE (4U)
#define ATOMIC_UINT_FAST16_T_SAME_SIZED_TYPE uint32_t
#define ATOMIC_INT_FAST32_T_SIZE (4U)
#define ATOMIC_INT_FAST32_T_SAME_SIZED_TYPE uint32_t
#define ATOMIC_UINT_FAST32_T_SIZE (4U)
#define ATOMIC_UINT_FAST32_T_SAME_SIZED_TYPE uint32_t
#define ATOMIC_INT_FAST64_T_SIZE (8U)
#define ATOMIC_INT_FAST64_T_SAME_SIZED_TYPE uint64_t
#define ATOMIC_UINT_FAST64_T_SIZE (8U)
#define ATOMIC_UINT_FAST64_T_SAME_SIZED_TYPE uint64_t
#define ATOMIC_INTPTR_T_SIZE (4U)
#define ATOMIC_INTPTR_T_SAME_SIZED_TYPE uint32_t
#define ATOMIC_UINTPTR_T_SIZE (4U)
#define ATOMIC_UINTPTR_T_SAME_SIZED_TYPE uint32_t
#define ATOMIC_SIZE_T_SIZE (4U)
#define ATOMIC_SIZE_T_SAME_SIZED_TYPE uint32_t
#define ATOMIC_PTRDIFF_T_SIZE (4U)
#define ATOMIC_PTRDIFF_T_SAME_SIZED_TYPE uint32_t
#define ATOMIC_INTMAX_T_SIZE (8U)
#define ATOMIC_INTMAX_T_SAME_SIZED_TYPE uint64_t
#define ATOMIC_UINTMAX_T_SIZE (8U)
#define ATOMIC_UINTMAX_T_SAME_SIZED_TYPE uint64_t

71
cpu/mips32r2_common/include/cpu.h
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@ -1,71 +0,0 @@
/*
* Copyright(C) 2017, 2016, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
/**
* @defgroup cpu_mips32r2_common Imagination Technologies MIPS32R2 Common
* @ingroup cpu
* @brief CPU definitions for MIPS32R2 devices.
* @{
*
* @file
* @brief CPU definitions for MIPS32R2 devices.
*
* @author Neil Jones <neil.jones@imgtec.com>
*/
#ifndef CPU_H
#define CPU_H
#include <stdint.h>
#include "cpu_conf.h"
#include "thread.h"
#include "irq.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Select fastest bitarithm_lsb implementation
* @{
*/
#define BITARITHM_LSB_BUILTIN
#define BITARITHM_HAS_CLZ
/** @} */
/**
* @brief Gets the last instruction's address
*
* @todo: Not supported
*/
static inline uintptr_t cpu_get_caller_pc(void)
{
/* This function must exist else RIOT won't compile */
return 0;
}
/**
* @brief Trigger a conditional context scheduler run / context switch
*
* This function is supposed to be called in the end of each ISR.
*/
static inline void mips32r2_isr_end(void)
{
if (sched_context_switch_request) {
thread_yield_higher();
}
}
#ifdef __cplusplus
}
#endif
#endif /* CPU_H */
/** @} */

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cpu/mips32r2_common/include/eic.h
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@ -1,72 +0,0 @@
/*
* Copyright 2016, Imagination Technologies Limited and/or its
* affiliated group companies.
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu
* @brief Imagination Technologies MIPS32R2 Common implementation
* @{
*
* @file
* @brief API for supporting External Interrupt Controllers (EIC mode)
*
* @author Neil Jones <neil.jones@imgtec.com>
*/
#ifndef EIC_H
#define EIC_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief External ISR callback
*/
typedef void (*external_isr_ptr_t)(void);
/**
* @brief Set External ISR callback
*/
void set_external_isr_cb(int vecNum, external_isr_ptr_t cbFunc);
/**
* @brief Configure interrupt priority
*
* @param[in] vecNum
* @param[in] priority
* @param[in] subpriority
*/
void eic_configure_priority(int vecNum, int priority, int subpriority);
/**
* @brief Enable interrupt
*
* @param[in] vecNum
*/
void eic_enable(int vecNum);
/**
* @brief Disable interrupt
*
* @param[in] vecNum
*/
void eic_disable(int vecNum);
/**
* @brief Clear interrupt flag
*
* @param[in] vecNum
*/
void eic_clear_flag(int vecNum);
#ifdef __cplusplus
}
#endif
#endif /* EIC_H */
/** @} */

49
cpu/mips32r2_common/include/thread_arch.h
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/*
* Copyright(C) 2017, 2016, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_mips32r2_common
* @{
*
* @file
* @brief Implementation of the kernels thread interface
*
* @author Neil Jones <neil.jones@imgtec.com>
*/
#ifndef THREAD_ARCH_H
#define THREAD_ARCH_H
#ifdef __cplusplus
extern "C" {
#endif
#define THREAD_API_INLINED
#ifndef DOXYGEN /* Doxygen is in core/include/thread.h */
static inline __attribute__((always_inline)) void thread_yield_higher(void)
{
/*
* throw a syscall exception to get into exception level
* we context switch at exception level.
*
* Note syscall 1 is reserved for UHI see:
* http://wiki.prplfoundation.org/w/images/4/42/UHI_Reference_Manual.pdf
*/
__asm volatile ("syscall 2");
}
#endif /* DOXYGEN */
#ifdef __cplusplus
}
#endif
#endif /* THREAD_ARCH_H */
/** @} */

46
cpu/mips32r2_common/irq_arch.c
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/*
* Copyright 2016, Imagination Technologies Limited and/or its
* affiliated group companies.
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
#include <mips/m32c0.h>
#include "irq.h"
unsigned int irq_enable(void)
{
unsigned int status;
__asm__ volatile ("ei %0" : "=r" (status));
return status;
}
unsigned int irq_disable(void)
{
unsigned int status;
__asm__ volatile ("di %0" : "=r" (status));
return status;
}
void irq_restore(unsigned int state)
{
if (state & SR_IE) {
mips32_bs_c0(C0_STATUS, SR_IE);
}
else {
mips32_bc_c0(C0_STATUS, SR_IE);
}
}
bool irq_is_in(void)
{
return mips32_get_c0(C0_STATUS) & SR_EXL;
}
bool irq_is_enabled(void)
{
return mips32_get_c0(C0_STATUS) & SR_IE;
}

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cpu/mips32r2_common/mips_dsp.S
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/*
* Copyright 2016, Imagination Technologies Limited and/or its
* affiliated group companies.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/* ************ PLEASE READ ME !!!! ****************
This file is missing from $MIPS_ELF_ROOT/share/mips/hal
Future toolchain versions will have this file included and this local copy will
be no longer needed.
Note the above copyright/license is 3 Clause BSD and as such is compatible with LGPLv2.1
as such we grant licensing this file under LGPLv2.1 (See the file LICENSE in the top level
directory for more details) as well.
Thanks for reading.
*/
.set nomips16
#include <mips/asm.h>
#include <mips/regdef.h>
#include <mips/m32c0.h>
#include <mips/hal.h>
#include <mips/endian.h>
#
# FUNCTION: _dsp_save
#
# DESCRIPTION: save the DSP context.
#
# RETURNS: int
#
# 0: No context saved
# CTX_*: Type of conext stored
#
LEAF(_dsp_save)
PTR_S zero, LINKCTX_NEXT(a0)
move v0, zero
# Test for DSP support
mfc0 t0, C0_CONFIG3
ext t0, t0, CFG3_DSPP_SHIFT, 1
beqz t0, 1f
# Test for DSP enabled
mfc0 t0, C0_STATUS
ext t0, t0, SR_MX_SHIFT, 1
beqz t0, 1f
lui v0, %hi(LINKCTX_TYPE_DSP)
addiu v0, v0, %lo(LINKCTX_TYPE_DSP)
.set push
.set dsp
rddsp t1
mfhi t2, $ac1
mflo t3, $ac1
mfhi t4, $ac2
mflo t5, $ac2
mfhi t6, $ac3
mflo t7, $ac3
.set pop
sw t1, DSPCTX_DSPC(a0)
sw t2, DSPCTX_HI1(a0)
sw t3, DSPCTX_LO1(a0)
sw t4, DSPCTX_HI2(a0)
sw t5, DSPCTX_LO2(a0)
sw t6, DSPCTX_HI3(a0)
sw t7, DSPCTX_LO3(a0)
REG_S v0, LINKCTX_ID(a0)
1:
jr ra
END(_dsp_save)
#
# FUNCTION: _dsp_load
#
# DESCRIPTION: load the DSP context.
#
# RETURNS: int
#
# 0: Unrecognised context
# CTX_*: Type of context restored
#
LEAF(_dsp_load)
REG_L v0, LINKCTX_ID(a0)
lui v1, %hi(LINKCTX_TYPE_DSP)
addiu v1, v1, %lo(LINKCTX_TYPE_DSP)
bne v0,v1,1f
# Test for DSP support
mfc0 t0, C0_CONFIG3
ext t0, t0, CFG3_DSPP_SHIFT, 1
beqz t0, 1f
# Force on DSP
di t3
ehb
or t3, t3, SR_MX
mtc0 t3, C0_STATUS
ehb
lw t1, DSPCTX_DSPC(a0)
lw t2, DSPCTX_HI1(a0)
lw t3, DSPCTX_LO1(a0)
lw t4, DSPCTX_HI2(a0)
lw t5, DSPCTX_LO2(a0)
lw t6, DSPCTX_HI3(a0)
lw t7, DSPCTX_LO3(a0)
.set push
.set dsp
wrdsp t1
mthi t2, $ac1
mtlo t3, $ac1
mthi t4, $ac2
mtlo t5, $ac2
mthi t6, $ac3
mtlo t7, $ac3
.set pop
jr ra
1:
# Don't recognise this context, fail
move v0, zero
jr ra
END(_dsp_load)

288
cpu/mips32r2_common/mips_excpt_entry.S
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@ -1,288 +0,0 @@
/*
* Copyright 2014-2015, Imagination Technologies Limited and/or its
* affiliated group companies.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/* ************ PLEASE READ ME !!!! ****************
This file is a copy of the mips_excpt_entry.S from $MIPS_ELF_ROOT/share/mips/hal
(from the 2016.05-03 version) with a single modification, we add a global flag
'__exception_restore' so we can jump to the restore code sequence from C.
Future toolchain versions will have this change included and this file will
be no longer needed.
Note the above copyright/license is 3 Clause BSD and as such is compatible with LGPLv2.1
as such we grant licensing this file under LGPLv2.1 (See the file LICENSE in the top level
directory for more details) as well.
Thanks for reading.
*/
# Keep each function in a separate named section
#define _FUNCTION_SECTIONS_
.set nomips16
#include <mips/asm.h>
#include <mips/regdef.h>
#include <mips/cpu.h>
#include <mips/hal.h>
# Context size, adjusted for ABI parameter area
#define ADJ (NARGSAVE * SZARG)
# Round up to 16-byte boundary (maximum stack alignment required for any
# supported ABI)
#define CTX_SIZEROUND ((CTX_SIZE + ALSZ) & ALMASK)
#define CTX_SIZEADJ (CTX_SIZEROUND + ADJ)
#define e_ISR s1
#define e_CR s3
#define e_BADV s4
#define e_SR s5
#define e_EPC s6
#define e_RA s7
# DESCRIPTION: Exception entry point. This is small because it must go at
# EBASE+0x180. It saves enough context to chain onwards to
# __exception_save.
#
LEAF(__exception_entry)
.set push
.set noat
.weak _mips_tlb_refill
_mips_tlb_refill = __exception_save
__tlb_refill_loop:
# Support an alternative entry point at the start of the exception
# vector. Since the exception vector is normally placed first
# in the link map this allows a user to start execution from the
# same address that an executable is loaded to.
LA k1, __first_boot
lw k1, 0(k1)
beqz k1, 1f
# The start code is responsible for clearing __first_boot prior
# to installing the exception handlers.
j _start
1:
LA k1, _mips_tlb_refill
beqz k1, __tlb_refill_loop
jr k1
.org 0x80
.weak _mips_xtlb_refill
_mips_xtlb_refill = __exception_save
__xtlb_refill_loop:
LA k1, _mips_xtlb_refill
beqz k1, __xtlb_refill_loop
jr k1
.org 0x100
.weak _mips_cache_error
__cache_error_loop:
LA k1, _mips_cache_error
beqz k1, __cache_error_loop
jr k1
.org 0x180
# Free up k1, defering sp adjustment until later
REG_S k1, (-CTX_SIZEROUND + CTX_K1)(sp)
# Use k1 to invoke __exception_save
LA k1, _mips_general_exception
jr k1
.set pop
END(__exception_entry)
#
# FUNCTION: __exception_save
#
# DESCRIPTION: Exception context save. Save the context, then fake up a call
# frame.
#
ANESTED(__exception_save, _mips_general_exception, CTX_SIZEADJ, zero)
.globl __exception_save;
.globl __exception_restore;
.set push
.set noat
# k1 is already saved, so use it to save the users sp
move k1, sp
# Finally adjust sp
PTR_ADDU sp, sp, -CTX_SIZEADJ # This should be picked up by the backtracer
# Save context
REG_S $1, CTX_REG(1) + ADJ(sp)
REG_S $2, CTX_REG(2) + ADJ(sp)
REG_S $3, CTX_REG(3) + ADJ(sp)
REG_S $4, CTX_REG(4) + ADJ(sp)
REG_S $5, CTX_REG(5) + ADJ(sp)
REG_S $6, CTX_REG(6) + ADJ(sp)
REG_S $7, CTX_REG(7) + ADJ(sp)
REG_S $8, CTX_REG(8) + ADJ(sp)
REG_S $9, CTX_REG(9) + ADJ(sp)
REG_S $10, CTX_REG(10) + ADJ(sp)
REG_S $11, CTX_REG(11) + ADJ(sp)
REG_S $12, CTX_REG(12) + ADJ(sp)
REG_S $13, CTX_REG(13) + ADJ(sp)
REG_S $14, CTX_REG(14) + ADJ(sp)
REG_S $15, CTX_REG(15) + ADJ(sp)
REG_S $16, CTX_REG(16) + ADJ(sp)
REG_S $17, CTX_REG(17) + ADJ(sp)
REG_S $18, CTX_REG(18) + ADJ(sp)
REG_S $19, CTX_REG(19) + ADJ(sp)
REG_S $20, CTX_REG(20) + ADJ(sp)
REG_S $21, CTX_REG(21) + ADJ(sp)
REG_S $22, CTX_REG(22) + ADJ(sp)
REG_S $23, CTX_REG(23) + ADJ(sp)
REG_S $24, CTX_REG(24) + ADJ(sp)
REG_S $25, CTX_REG(25) + ADJ(sp)
REG_S $26, CTX_REG(26) + ADJ(sp)
# k1/$27 has already been saved
REG_S $28, CTX_REG(28) + ADJ(sp)
REG_S k1, CTX_REG(29) + ADJ(sp) # Use saved sp from earlier
REG_S $30, CTX_REG(30) + ADJ(sp)
REG_S $31, CTX_REG(31) + ADJ(sp)
PTR_S $0, CTX_LINK + ADJ(sp) # Clear the link field
#if (__mips_isa_rev < 6)
mfhi $9
mflo $10
REG_S $9, CTX_HI0 + ADJ(sp)
REG_S $10, CTX_LO0 + ADJ(sp)
#endif
# Trick the backtracer into stepping back to the point where the exception
# occurred.
PTR_MFC0 ra, C0_EPC
mfc0 e_CR, C0_CR
REG_S ra, CTX_EPC + ADJ(sp)
# Finish storing the rest of the CP0 registers
PTR_MFC0 $9, C0_BADVADDR
REG_S $9, CTX_BADVADDR + ADJ(sp)
sw e_CR, CTX_CAUSE + ADJ(sp)
move $11, $0
move $12, $0
mfc0 $9, C0_CONFIG3
ext $10, $9, CFG3_BP_SHIFT, 1
beqz $10, 1f
mfc0 $11, C0_BADPINSTR
1:
ext $9, $9, CFG3_BI_SHIFT, 1
beqz $9, 1f
mfc0 $12, C0_BADINSTR
1:
sw $11, CTX_BADPINSTR + ADJ(sp)
sw $12, CTX_BADINSTR + ADJ(sp)
# Start computing the address of the context for a0
move a0, sp
# Clear EXL. Exceptions can now nest.
mfc0 e_SR, C0_SR
sw e_SR, CTX_STATUS + ADJ(sp)
lui $9, %hi(~SR_EXL)
addiu $9, $9, %lo(~SR_EXL)
and e_SR, e_SR, $9
mtc0 e_SR, C0_SR
# Manually set up the return address to restore the context below
LA ra, __exception_restore
# Extract the cause code
and a1, e_CR, CR_XMASK
# Finish computing the address of the context for a0
addiu a0, a0, ADJ
# Shift exception number down into expected range
srl a1, a1, 2
# Call the handler, indirect through t9 albeit not for any specific
# reason
LA t9, _mips_handle_exception
jr t9
# Return point from handler
# Load context
# now a function on its own, note save code just falls through.
__exception_restore:
#if (__mips_isa_rev < 6)
REG_L $9, CTX_HI0 + ADJ(sp)
REG_L $10, CTX_LO0 + ADJ(sp)
mthi $9
mtlo $10
#endif
REG_L $1, CTX_REG(1) + ADJ(sp)
REG_L $2, CTX_REG(2) + ADJ(sp)
REG_L $3, CTX_REG(3) + ADJ(sp)
REG_L $4, CTX_REG(4) + ADJ(sp)
REG_L $5, CTX_REG(5) + ADJ(sp)
REG_L $6, CTX_REG(6) + ADJ(sp)
REG_L $7, CTX_REG(7) + ADJ(sp)
REG_L $8, CTX_REG(8) + ADJ(sp)
REG_L $9, CTX_REG(9) + ADJ(sp)
REG_L $10, CTX_REG(10) + ADJ(sp)
REG_L $11, CTX_REG(11) + ADJ(sp)
REG_L $12, CTX_REG(12) + ADJ(sp)
REG_L $13, CTX_REG(13) + ADJ(sp)
REG_L $14, CTX_REG(14) + ADJ(sp)
REG_L $15, CTX_REG(15) + ADJ(sp)
REG_L $16, CTX_REG(16) + ADJ(sp)
REG_L $17, CTX_REG(17) + ADJ(sp)
REG_L $18, CTX_REG(18) + ADJ(sp)
REG_L $19, CTX_REG(19) + ADJ(sp)
REG_L $20, CTX_REG(20) + ADJ(sp)
REG_L $21, CTX_REG(21) + ADJ(sp)
REG_L $22, CTX_REG(22) + ADJ(sp)
REG_L $23, CTX_REG(23) + ADJ(sp)
REG_L $24, CTX_REG(24) + ADJ(sp)
REG_L $25, CTX_REG(25) + ADJ(sp)
# $26/K0 and $27/K1 are restored with interrupts disabled
REG_L $28, CTX_REG(28) + ADJ(sp)
# $29/SP is restored last
REG_L $30, CTX_REG(30) + ADJ(sp)
REG_L $31, CTX_REG(31) + ADJ(sp)
di
lw k0, CTX_STATUS + ADJ(sp)
REG_L k1, CTX_EPC + ADJ(sp)
mtc0 k0, C0_SR
PTR_MTC0 k1, C0_EPC
ehb
REG_L k0, CTX_K0 + ADJ(sp)
REG_L k1, CTX_K1 + ADJ(sp)
REG_L sp, CTX_SP + ADJ(sp)
# Return from exception
eret
.set pop
END(__exception_save)

100
cpu/mips32r2_common/mips_excpt_isr.S
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@ -1,100 +0,0 @@
/*
* Copyright 2014-2015, Imagination Technologies Limited and/or its
* affiliated group companies.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#
# Keep each function in a separate named section
#define _FUNCTION_SECTIONS_
.set nomips16
#include <mips/regdef.h>
#include <mips/asm.h>
#include <mips/cpu.h>
#define VEC_SPACE (SZPTR * 8)
LEAF(__isr_vec)
.set push
.set noat
AENT(__isr_vec_sw0)
.weak _mips_isr_sw0
LA k1, _mips_isr_sw0
beqz k1, 1f
jr k1
.org VEC_SPACE
AENT(__isr_vec_sw1)
.weak _mips_isr_sw1
LA k1, _mips_isr_sw1
beqz k1, 1f
jr k1
.org 2 * VEC_SPACE
AENT(__isr_vec_hw0)
.weak _mips_isr_hw0
LA k1, _mips_isr_hw0
beqz k1, 1f
jr k1
.org 3 * VEC_SPACE
AENT(__isr_vec_hw1)
.weak _mips_isr_hw1
LA k1, _mips_isr_hw1
beqz k1, 1f
jr k1
.org 4 * VEC_SPACE
AENT(__isr_vec_hw2)
.weak _mips_isr_hw2
LA k1, _mips_isr_hw2
beqz k1, 1f
jr k1
.org 5 * VEC_SPACE
AENT(__isr_vec_hw3)
.weak _mips_isr_hw3
LA k1, _mips_isr_hw3
beqz k1, 1f
jr k1
.org 6 * VEC_SPACE
AENT(__isr_vec_hw4)
.weak _mips_isr_hw4
LA k1, _mips_isr_hw4
beqz k1, 1f
jr k1
.org 7 * VEC_SPACE
AENT(__isr_vec_hw5)
.weak _mips_isr_hw5
LA k1, _mips_isr_hw5
beqz k1, 1f
jr k1
.org 8 * VEC_SPACE
AENT(__isr_vec_fallback)
.weak _mips_interrupt
1:
LA k1, _mips_interrupt
beqz k1, 1b
jr k1
.set pop
END(__isr_vec)

1
cpu/mips32r2_common/newlib_syscalls_mips_uhi/Makefile
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@ -1 +0,0 @@
include $(RIOTBASE)/Makefile.base

341
cpu/mips32r2_common/newlib_syscalls_mips_uhi/syscalls.c
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@ -1,341 +0,0 @@
/*
* Copyright (C) 2017 Imagination Technologies
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup sys_newlib
* @{
*
* @file
* @brief Newlib system call implementation for use with the mips-mti-elf
* toolchain newlib incorporating as semi-hosting interface called 'UHI'
*
* @author Neil Jones <neil.jones@imgtec.com>
*
* @}
*/
#include <unistd.h>
#include <reent.h>
#include <errno.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/stat.h>
#include <sys/unistd.h>
#include <stdint.h>
#include <fcntl.h>
#include <mips/hal.h>
#include "cpu.h"
#include "board.h"
#include "sched.h"
#include "thread.h"
#include "irq.h"
#include "log.h"
#include "periph/pm.h"
/**
* * @brief manage the heap
* */
extern char _sheap; /* start of the heap */
extern char _eheap; /* end of the heap */
char *heap_top = &_sheap + 4;
/* Only need to define these when MIPS newlib is not used */
#ifndef __mips__
/**
* @brief Free resources on NewLib de-initialization, not used for RIOT
*/
/* __attribute__((used)) fixes linker errors when building with LTO, but without nano.specs */
__attribute__((used)) void _fini(void)
{
/* nothing to do here */
}
/**
* @brief Exit a program without cleaning up files
*
* If your system doesn't provide this, it is best to avoid linking with subroutines that
* require it (exit, system).
*
* @param n the exit code, 0 for all OK, >0 for not OK
*/
void _exit(int n)
{
exit(n);
/* cppcheck-suppress unreachableCode
* (reason: pm_off spins indefinitely after pulling the plug) */
pm_off();
}
/**
* @brief Allocate memory from the heap.
*
* The current heap implementation is very rudimentary, it is only able to allocate
* memory. But it does not have any means to free memory again
*
* @return pointer to the newly allocated memory on success
* @return pointer set to address `-1` on failure
*/
void *_sbrk_r(struct _reent *r, ptrdiff_t incr)
{
unsigned int state = irq_disable();
void *res = heap_top;
if ((heap_top + incr > &_eheap) || (heap_top + incr < &_sheap)) {
r->_errno = ENOMEM;
res = (void *)-1;
} else {
heap_top += incr;
}
irq_restore(state);
return res;
}
#endif /*__mips__*/
/**
* @brief Get the process-ID of the current thread
*
* @return the process ID of the current thread
*/
pid_t _getpid(void)
{
return thread_getpid();
}
/**
* @brief Get the process-ID of the current thread
*
* @return the process ID of the current thread
*/
pid_t _getpid_r(struct _reent *ptr)
{
(void)ptr;
return thread_getpid();
}
/**
* @brief Send a signal to a given thread
*
* @param r pointer to reent structure
* @param pid process ID to kill
* @param sig signal number to pass to process
*
* @return -1 on error
* @return 0 on success
*/
__attribute__ ((weak))
int _kill_r(struct _reent *r, pid_t pid, int sig)
{
(void)pid;
(void)sig;
r->_errno = ESRCH; /* not implemented yet */
return -1;
}
/**
* @brief Open a file
*
* This is a wrapper around @c _open
*
* @param r pointer to reent structure
* @param name file name to open
* @param flags flags, see man 3p open
* @param mode mode, file creation mode if the file is created when opening
*
* @return fd number (>= 0) on success
* @return -1 on error
*/
int _open_r(struct _reent *r, const char *name, int flags, int mode)
{
(void)r;
return open(name, flags, mode);
}
/**
* @brief Read bytes from an open file
*
* This is a wrapper around @c _read
*
* @param[in] r pointer to reent structure
* @param[in] fd open file descriptor obtained from @c open()
* @param[out] dest destination buffer
* @param[in] count maximum number of bytes to read
*
* @return number of bytes read on success
* @return -1 on error,
*/
_ssize_t _read_r(struct _reent *r, int fd, void *dest, size_t count)
{
(void)r;
return read(fd,dest,count);
}
/**
* @brief Write bytes to an open file
*
* This is a wrapper around @c _write
*
* @param[in] r pointer to reent structure
* @param[in] fd open file descriptor obtained from @c open()
* @param[in] src source data buffer
* @param[in] count maximum number of bytes to write
*
* @return number of bytes written on success
* @return -1 on error
*/
_ssize_t _write_r(struct _reent *r, int fd, const void *src, size_t count)
{
(void)r;
int res = write(fd, src, count);
return res;
}
/**
* @brief Close an open file
*
* This is a wrapper around @c _close
*
* If this call returns an error, the fd should still be considered invalid and
* no further attempt to use it shall be made, not even to retry @c close()
*
* @param[in] r pointer to reent structure
* @param[in] fd open file descriptor obtained from @c open()
*
* @return 0 on success
* @return -1 on error
*/
int _close_r(struct _reent *r, int fd)
{
(void)r;
int res = close(fd);
return res;
}
/**
* @brief Query or set options on an open file
*
* This is a wrapper around @c _fcntl
*
* @param[in] r pointer to reent structure
* @param[in] fd open file descriptor obtained from @c open()
* @param[in] cmd fcntl command, see man 3p fcntl
* @param[in] arg argument to fcntl command, see man 3p fcntl
*
* @return 0 on success
* @return -1 on error
*/
int _fcntl_r (struct _reent *r, int fd, int cmd, int arg)
{
(void)r;
int res = fcntl(fd, cmd, arg);
return res;
}
/**
* @brief Seek to position in file
*
* This is a wrapper around @c _lseek
*
* @p whence determines the function of the seek and should be set to one of
* the following values:
*
* - @c SEEK_SET: Seek to absolute offset @p off
* - @c SEEK_CUR: Seek to current location + @p off
* - @c SEEK_END: Seek to end of file + @p off
*
* @param[in] r pointer to reent structure
* @param[in] fd open file descriptor obtained from @c open()
* @param[in] off seek offset
* @param[in] whence determines the seek method, see detailed description
*
* @return the new seek location in the file on success
* @return -1 on error
*/
_off_t _lseek_r(struct _reent *r, int fd, _off_t off, int whence)
{
(void)r;
int res = lseek(fd, off, whence);
return res;
}
/**
* @brief Get status of an open file
*
* This is a wrapper around @c _fstat
*
* @param[in] r pointer to reent structure
* @param[in] fd open file descriptor obtained from @c open()
* @param[out] buf pointer to stat struct to fill
*
* @return 0 on success
* @return -1 on error
*/
int _fstat_r(struct _reent *r, int fd, struct stat *buf)
{
(void)r;
int res = fstat(fd, buf);
return res;
}
/*
* @brief Unlink (delete) a file
*
* @param[in] r pointer to reent structure
* @param[in] path path to file to be deleted
*
* @return 0 on success
* @return -1 on error
*/
int _unlink_r(struct _reent *r, const char *path)
{
(void)r;
int res = unlink(path);
return res;
}
/**
* @brief Query whether output stream is a terminal
*
* @param r pointer to reent structure
* @param fd descriptor of stream to query
*
* @return 0 for none tty
* @return 1 for tty
*
*/
int _isatty_r(struct _reent *r, int fd)
{
r->_errno = 0;
if(fd == STDIN_FILENO || fd == STDOUT_FILENO || fd == STDERR_FILENO) {
return 1;
}
return 0;
}
/**
* @brief Send a signal to a thread
*
* @param[in] pid the pid to send to
* @param[in] sig the signal to send
*
* @return 0 on success
* @return -1 on error
*
*/
__attribute__ ((weak))
int _kill(pid_t pid, int sig)
{
(void)pid;
(void)sig;
errno = ESRCH; /* not implemented yet */
return -1;
}

3
cpu/mips32r2_common/periph/Makefile
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@ -1,3 +0,0 @@
MODULE = mips32r2_common_periph
include $(RIOTMAKE)/periph.mk

31
cpu/mips32r2_common/periph/pm.c
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@ -1,31 +0,0 @@
/*
* Copyright 2016, Imagination Technologies Limited and/or its
* affiliated group companies.
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_mips32r2_common
* @ingroup drivers_periph_pm
* @{
*
* @file
* @brief common periph/pm functions
*
* @author Neil Jones <neil.jones@imgtec.com>
*
* @}
*/
#include <mips/m32c0.h>
#include "periph/pm.h"
void pm_set_lowest(void)
{
/* Don't wait if interrupts are not enabled - we would never return!*/
if (mips32_get_c0(C0_STATUS) & SR_IE) {
__asm volatile ("wait");
}
}

387
cpu/mips32r2_common/thread_arch.c
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@ -1,387 +0,0 @@
/*
* Copyright 2016, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
#include <assert.h>
#include <mips/cpu.h>
#include <mips/hal.h>
#include <unistd.h>
#include <sys/stat.h>
#include <stdio.h>
#include <string.h>
#include "thread.h"
#include "cpu.h"
#include "irq.h"
#include "cpu_conf.h"
#include "malloc.h"
#include "stdio_uart.h"
#define STACK_END_PAINT (0xdeadc0de)
#define C0_STATUS_EXL (2)
#define PADDING (16)
#define MICROMIPS_ISA_MODE (1)
#define M32_SYSCALL (0xC)
#define M32_SYSCALL_MASK (0xfc00003f)
/*
* note the major 16bits of a 32bit MicroMIPS opcode appear first in the
* instruction stream
*/
#define MM_SYSCALL (0x8B7C0000)
#define MM_SYSCALL_MASK (0xfffffc00)
#ifdef MIPS_HARD_FLOAT
/* pointer to the current and old fpu context for lazy context switching */
static struct fp64ctx *currentfpctx; /* fpu context of current running task */
static struct fp64ctx *oldfpctx; /* fpu context of last task that executed fpu */
#endif
/*
* Stack Layout, note struct gpctx is defined in
* $MIPS_ELF_ROOT/mips-mti-elf/include/mips/hal.h
*
* Top Of Stack
* ---------------
* | |
* | User stack |
* | |
* --------------- <--- gpctx->sp
* | |
* | gpctx |
* | |
* ---------------
* | 16 byte pad |
* --------------- <--- thread_get_active()->sp
*/
char *thread_stack_init(thread_task_func_t task_func, void *arg,
void *stack_start, int stack_size)
{
/* make sure it is aligned to 8 bytes this is a requirement of the O32 ABI */
uintptr_t *p = (uintptr_t *)(((long)(stack_start) + stack_size) & ~7);
uintptr_t *fp;
/* paint */
p--;
*p-- = STACK_END_PAINT;
/* prepare stack for __exception_restore() */
fp = p;
p -= sizeof(struct gpctx) / sizeof(unsigned int);
struct gpctx *initial_ctx = (struct gpctx *)p;
initial_ctx->a[0] = (reg_t)arg;
initial_ctx->status = mips32_get_c0(C0_STATUS) | SR_IE; /* Enable interrupts */
__asm volatile ("sw $gp, 0(%0)" : : "r" (&initial_ctx->gp));
initial_ctx->epc = (reg_t)task_func;
initial_ctx->ra = (reg_t)sched_task_exit;
initial_ctx->sp = (reg_t)fp;
initial_ctx->link = (struct linkctx *)NULL;
#ifdef MIPS_MICROMIPS
initial_ctx->epc |= MICROMIPS_ISA_MODE;
initial_ctx->ra |= MICROMIPS_ISA_MODE;
#endif
#ifdef MIPS_HARD_FLOAT
/*
* Disable FPU so we get an exception on first use to allow
* Lazy FPU context save and restore
*/
initial_ctx->status &= ~SR_CU1;
initial_ctx->status |= SR_FR; /*use double width FPU */
#endif
/*
* note the -4 (-16 bytes) as the toolchain exception handling code
* adjusts the sp for alignment
*/
p -= PADDING/sizeof(unsigned int);
return (void *)p;
}
void thread_stack_print(void)
{
uintptr_t *sp = (void *)thread_get_active()->sp;
printf("Stack trace:\n");
while (*sp != STACK_END_PAINT) {
printf(" 0x%p: 0x%08lx\n", sp, *sp);
sp++;
}
}
extern void __exception_restore(void);
void cpu_switch_context_exit(void)
{
unsigned int status = mips32_get_c0(C0_STATUS);
/*
* Set Exception level if we are not already running at it
* the EXL mode depends on the bootloader.
*/
if ((status & C0_STATUS_EXL) == 0) {
mips32_set_c0(C0_STATUS, status | C0_STATUS_EXL);
}
sched_run();
__asm volatile ("lw $sp, 0(%0)" : : "r" (&thread_get_active()->sp));
__exception_restore();
UNREACHABLE();
}
struct linkctx* exctx_find(reg_t id, struct gpctx *gp)
{
struct linkctx **ctx = (struct linkctx **)&gp->link;
while (*ctx) {
if ((*ctx)->id == id) {
return *ctx;
}
ctx = &(*ctx)->next;
}
return NULL;
}
/* unaligned access helper */
static inline uint32_t
#ifndef __clang__
/* Clang does not support attribute optimize */
__attribute__((optimize("-O3")))
#endif
mem_rw(const void *vaddr)
{
uint32_t v;
memcpy(&v, vaddr, sizeof(v));
return v;
}
#ifdef MIPS_DSP
extern int _dsp_save(struct dspctx *ctx);
extern int _dsp_load(struct dspctx *ctx);
#endif
/*
* The official mips toolchain version 2016.05-03 needs this attribute.
* Newer versions (>=2017.10-05) don't. Those started being based on gcc 6,
* thus use that to guard the attribute.
*
* See https://github.com/RIOT-OS/RIOT/pull/11986.
*/
#if __GNUC__ <= 4
void __attribute__((nomips16))
#else
void
#endif
/* note return type from above #ifdef */
_mips_handle_exception(struct gpctx *ctx, int exception)
{
unsigned int syscall_num = 0;
#ifdef MIPS_DSP
struct dspctx dsp_ctx; /* intentionally allocated on current stack */
#endif
switch (exception) {
case EXC_SYS:
#ifdef MIPS_MICROMIPS
/* note major 16bits of opcode is first in instruction stream */
syscall_num =
mem_rw((const void *)(ctx->epc & ~MICROMIPS_ISA_MODE))
& 0x3FF;
#else
syscall_num = (mem_rw((const void *)ctx->epc) >> 6) & 0xFFFF;
#endif
#ifdef MODULE_STDIO_UART
#include <mips/uhi_syscalls.h>
/*
* intercept UHI write syscalls (printf) which would normally
* get routed to debug probe or bootloader handler and output
* via a UART
*/
if (syscall_num == __MIPS_UHI_SYSCALL_NUM) {
if (ctx->t2[1] == __MIPS_UHI_WRITE &&
(ctx->a[0] == STDOUT_FILENO || ctx->a[0] == STDERR_FILENO)) {
uint32_t status = irq_disable();
stdio_write((void *)ctx->a[1], ctx->a[2]);
ctx->v[0] = ctx->a[2];
ctx->epc += 4; /* move PC past the syscall */
irq_restore(status);
return;
}
else if (ctx->t2[1] == __MIPS_UHI_READ && ctx->a[0] == STDIN_FILENO) {
ctx->v[0] = stdio_read((void *)ctx->a[1], ctx->a[2]);
ctx->epc += 4; /* move PC past the syscall */
return;
}
else if (ctx->t2[1] == __MIPS_UHI_FSTAT &&
(ctx->a[0] == STDOUT_FILENO || ctx->a[0] == STDIN_FILENO || ctx->a[0] == STDERR_FILENO)) {
/*
* Printf fstat's the stdout/stdin/stderr file so
* fill out a minimal struct stat.
*/
struct stat *sbuf = (struct stat *)ctx->a[1];
memset(sbuf, 0, sizeof(struct stat));
sbuf->st_mode = S_IRUSR | S_IWUSR | S_IWGRP;
sbuf->st_blksize = BUFSIZ;
/* return 0 */
ctx->v[0] = 0;
ctx->epc += 4; /* move PC past the syscall */
return;
}
}
else
#endif
if (syscall_num == 2) {
unsigned int return_instruction = 0;
struct gpctx *new_ctx;
#ifdef MIPS_DSP
struct dspctx *new_dspctx;
#endif
/*
* Syscall 1 is reserved for UHI.
*/
/*
* save the stack pointer in the thread info
* note we want the saved value to include the
* saved off context and the 16 bytes padding.
* Note we cannot use the current sp value as
* the prologue of this function has adjusted it
*/
thread_t *t = thread_get_active();
t->sp = (char *)(ctx->sp - sizeof(struct gpctx) - PADDING);
#ifdef MIPS_DSP
_dsp_save(&dsp_ctx);
_linkctx_append(ctx,&(dsp_ctx.link));
#endif
#ifdef MIPS_HARD_FLOAT
if(currentfpctx) {
_linkctx_append(ctx,&(currentfpctx->fp.link));
}
#endif
sched_run();
t = thread_get_active();
new_ctx = (struct gpctx *)((unsigned int)t->sp + PADDING);
#ifdef MIPS_HARD_FLOAT
currentfpctx = (struct fp64ctx *)exctx_find(LINKCTX_TYPE_FP64, new_ctx);
if(!currentfpctx) {
/* check for half-width FPU ctx in-case hardware doesn't support double. */
currentfpctx = (struct fp64ctx *)exctx_find(LINKCTX_TYPE_FP32, new_ctx);
}
#endif
#ifdef MIPS_DSP
new_dspctx = (struct dspctx *)exctx_find(LINKCTX_TYPE_DSP, new_ctx);
if (new_dspctx)
_dsp_load(new_dspctx);
#endif
#ifdef MIPS_MICROMIPS
return_instruction =
mem_rw((const void *)(new_ctx->epc & ~MICROMIPS_ISA_MODE));
if ((return_instruction & MM_SYSCALL_MASK) == MM_SYSCALL) { /* syscall */
new_ctx->epc += 4; /* move PC past the syscall */
}
#else
return_instruction = mem_rw((const void *)new_ctx->epc);
if ((return_instruction & M32_SYSCALL_MASK) == M32_SYSCALL) { /* syscall */
new_ctx->epc += 4; /* move PC past the syscall */
}
#endif
/*
* The toolchain Exception restore code just wholesale copies the
* status register from the context back to the register losing
* any changes that may have occurred, 'status' is really global state
* You don't enable interrupts on one thread and not another...
* So we just copy the current status value into the saved value
* so nothing changes on the restore
*/
new_ctx->status = mips32_get_c0(C0_STATUS);
#ifdef MIPS_HARD_FLOAT
/*
* Disable FPU so we get an exception on first use to allow
* Lazy FPU context save and restore
*/
new_ctx->status &= ~SR_CU1;
#endif
__asm volatile ("lw $sp, 0(%0)" : : "r" (&thread_get_active()->sp));
/*
* Jump straight to the exception restore code
* if we return this functions prologue messes up
* the stack pointer
*/
__exception_restore();
UNREACHABLE();
}
break;
#ifdef MIPS_HARD_FLOAT
case EXC_CPU:
{
int newly_allocd = false;
mips_bissr(SR_CU1);
ctx->status |= SR_CU1;
if (!currentfpctx) {
currentfpctx = malloc(sizeof(struct fp64ctx));
assert(currentfpctx);
memset(currentfpctx,0,sizeof(struct fp64ctx));
currentfpctx->fp.link.id = LINKCTX_TYPE_FP64;
newly_allocd = true;
}
/* this means no one exec'd fpu since we last run */
if (oldfpctx == currentfpctx) {
return;
}
if (oldfpctx) {
_fpctx_save(&oldfpctx->fp);
}
if (!newly_allocd) {
_fpctx_load(&currentfpctx->fp);
}
/*
* next fpu exception must save our context as it's not necessarily
* the next context switch will cause fpu exception and it's very
* hard for any future task to determine which was the last one
* that performed fpu operations. so by saving this pointer now we
* give this knowledge to that future task
*/
oldfpctx = currentfpctx;
return;
}
#endif
/* default: */
}
/* Pass all other exceptions through to the toolchain handler */
__exception_handle(ctx, exception);
}

14
cpu/mips_pic32_common/Kconfig
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@ -1,14 +0,0 @@
# Copyright (c) 2020 HAW Hamburg
#
# This file is subject to the terms and conditions of the GNU Lesser
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.
#
config CPU_COMMON_MIPS_PIC32
bool
select HAS_PERIPH_CPUID
select HAS_PERIPH_GPIO
select HAS_PERIPH_GPIO_IRQ
source "$(RIOTCPU)/mips32r2_common/Kconfig"

2
cpu/mips_pic32_common/Makefile
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@ -1,2 +0,0 @@
DIRS += periph
include $(RIOTBASE)/Makefile.base

11
cpu/mips_pic32_common/Makefile.dep
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@ -1,11 +0,0 @@
USEMODULE += mips_pic32_common
USEMODULE += mips_pic32_common_periph
# mips32 needs periph_timer for its gettimeofday() implementation
USEMODULE += periph_timer
# add module defining cpu model specific symbols. This module is located in
# $(RIOTCPU)/$(CPU)/$(CPU_MODEL)
USEMODULE += $(CPU_MODEL)
include $(RIOTCPU)/mips32r2_common/Makefile.dep

4
cpu/mips_pic32_common/Makefile.features
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@ -1,4 +0,0 @@
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_gpio periph_gpio_irq
include $(RIOTCPU)/mips32r2_common/Makefile.features

11
cpu/mips_pic32_common/Makefile.include
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@ -1,11 +0,0 @@
include $(RIOTCPU)/mips32r2_common/Makefile.include
# The 2020.06-01 toolchain provides POSIX defines for pthread which conflicts
# with the one in RIOT. The following CFLAGS skip the inclusion of the types
# shipped by the toolchain.
CFLAGS += -D_SYS__PTHREADTYPES_H_
CFLAGS += -DCPU_FAM_$(call uppercase_and_underscore,$(CPU_FAM))
LINKFLAGS += -L$(RIOTCPU)/mips_pic32_common/ldscripts
INCLUDES += -I$(RIOTCPU)/mips_pic32_common/include
DIRS += $(RIOTCPU)/$(CPU)/$(CPU_MODEL)

10
cpu/mips_pic32_common/doc.txt
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@ -1,10 +0,0 @@
/**
* @defgroup cpu_mips_pic32_common Microchip MIPS common
* @ingroup cpu
* @brief Microchip MIPS common
* @deprecated Will not be available after the 2022.07 release. This includes
all MIPS based boards and cpus.
*
* This module contains all common code and definition to all Microchip MIPS
* cpu families supported by RIOT: @ref cpu_mips_pic32mx, @ref cpu_mips_pic32mz.
*/

95
cpu/mips_pic32_common/eic.c
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@ -1,95 +0,0 @@
/*
* Copyright (C) 2019 Francois Berder
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
#include "cpu_conf.h"
#include "eic.h"
#include <stdint.h>
#if defined(CPU_FAM_PIC32MX)
#define VEC_NUMOF (64)
#elif defined (CPU_FAM_PIC32MZ)
#define VEC_NUMOF (256)
#endif
#define IECSET(V) *(volatile uint32_t *)((uintptr_t)&IEC0SET + 0x10 * ((V) / 32))
#define IECCLR(V) *(volatile uint32_t *)((uintptr_t)&IEC0CLR + 0x10 * ((V) / 32))
#define IFSCLR(V) *(volatile uint32_t *)((uintptr_t)&IFS0CLR + 0x10 * ((V) / 32))
#define IPC(V) *(volatile uint32_t *)((uintptr_t)&IPC0 + 0x10 * ((V) / 4))
static external_isr_ptr_t vectors[VEC_NUMOF];
void set_external_isr_cb(int vecNum, external_isr_ptr_t cbFunc)
{
if (vecNum < VEC_NUMOF)
vectors[vecNum] = cbFunc;
}
/* note Compiler inserts GP context save + restore code (to current stack). */
/*
* This is a hack - currently the toolchain does not support correct placement
* of EIC mode vectors (it is coming though) But we can support non-vectored EIC
* mode and note the default PIC32 interrupt controller (which uses EIC +
* MCU-ASE) defaults to non vectored mode anyway with all interrupts coming via
* vector 0 which is equivalent to 'sw0' in 'VI' mode.
*
* Thus all EIC interrupts should be decoded here.
*
* When toolchain support is available we could move to full vector mode but
* this does take up significant space (MCU-ASE provides 256 vectors at 32B
* spacing (the default) that's 8KB of vector space!), So a single entry point
* may be better anyway.
*
*/
void __attribute__ ((interrupt("vector=sw0"), keep_interrupts_masked)) _mips_isr_sw0(void)
{
#if defined(CPU_FAM_PIC32MX)
int vecNum = INTSTAT & _INTSTAT_VEC_MASK;
#elif defined (CPU_FAM_PIC32MZ)
int vecNum = INTSTAT & _INTSTAT_SIRQ_MASK;
#endif
if (vectors[vecNum])
vectors[vecNum]();
}
void eic_configure_priority(int vecNum, int priority, int subpriority)
{
unsigned int offset;
if (vecNum >= VEC_NUMOF)
return;
offset = 8 * (vecNum & 0x3);
IPC(vecNum) &= ~(0x1F << offset);
IPC(vecNum) |= ((priority << 2) | (subpriority)) << offset;
}
void eic_enable(int vecNum)
{
if (vecNum >= VEC_NUMOF)
return;
IECSET(vecNum) = 1U << (vecNum & 0x1F);
}
void eic_disable(int vecNum)
{
if (vecNum >= VEC_NUMOF)
return;
IECCLR(vecNum) = 1U << (vecNum & 0x1F);
}
void eic_clear_flag(int vecNum)
{
if (vecNum >= VEC_NUMOF)
return;
IFSCLR(vecNum) = 1U << (vecNum & 0x1F);
}

126
cpu/mips_pic32_common/include/periph_cpu_common.h
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/*
* Copyright(C) 2017, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
/**
* @ingroup cpu_mips_pic32_common
* @brief Shared CPU specific definitions for the MIPS family.
* @{
*
* @file
* @brief Shared CPU specific definitions for the MIPS family.
*
* @author Francois Berder <francois.berder@imgtec.com>
*/
#ifndef PERIPH_CPU_COMMON_H
#define PERIPH_CPU_COMMON_H
#include "cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief We run from flash on PIC32
*/
#define FLASH_XIP (1)
/**
* @name Power management configuration
* @{
*/
#define PROVIDES_PM_SET_LOWEST
/** @} */
/**
* @brief Length of the CPU_ID in bytes
*/
#define CPUID_LEN (4U)
#ifndef DOXYGEN
/**
* @brief Overwrite the default gpio_t type definition
* @{
*/
#define HAVE_GPIO_T
typedef uint32_t gpio_t;
/** @} */
#endif
/**
* @brief Override GPIO pin selection macro
*/
#define GPIO_PIN(x, y) (((_PORTB_BASE_ADDRESS & 0xFFFFF000) + (x << 8)) | y)
/**
* @brief Available ports on the PIC32 family
*/
enum {
PORT_A = 0, /**< port A */
PORT_B = 1, /**< port B */
PORT_C = 2, /**< port C */
PORT_D = 3, /**< port D */
PORT_E = 4, /**< port E */
PORT_F = 5, /**< port F */
PORT_G = 6, /**< port G */
};
/**
* @brief Prevent shared timer functions from being used
*/
#define PERIPH_TIMER_PROVIDES_SET
/**
* @brief Available MUX values for configuring a pin's alternate function
*/
typedef enum {
GPIO_AF0 = 0, /**< use alternate function 0 */
GPIO_AF1, /**< use alternate function 1 */
GPIO_AF2, /**< use alternate function 2 */
GPIO_AF3, /**< use alternate function 3 */
GPIO_AF4, /**< use alternate function 4 */
GPIO_AF5, /**< use alternate function 5 */
GPIO_AF6, /**< use alternate function 6 */
GPIO_AF7, /**< use alternate function 7 */
GPIO_AF8, /**< use alternate function 8 */
GPIO_AF9, /**< use alternate function 9 */
GPIO_AF10, /**< use alternate function 10 */
GPIO_AF11, /**< use alternate function 11 */
GPIO_AF12, /**< use alternate function 12 */
GPIO_AF13, /**< use alternate function 13 */
GPIO_AF14, /**< use alternate function 14 */
GPIO_AF15 /**< use alternate function 15 */
} gpio_af_t;
/**
* @brief Structure for UART configuration data
*/
typedef struct {
volatile unsigned int * base; /**< UART device base register address */
uint32_t clock; /**< Peripheral clock frequency */
gpio_t rx_pin; /**< RX pin */
gpio_t tx_pin; /**< TX pin */
volatile unsigned int *rx_mux_reg; /**< Address of RX mux register*/
volatile unsigned int *tx_mux_reg; /**< Address of TX mux register */
gpio_af_t rx_af; /**< alternate function for RX pin */
gpio_af_t tx_af; /**< alternate function for TX pin */
uint32_t vector; /**< vector number */
#ifdef CPU_FAM_PIC32MX
uint32_t irq; /**< interrupt number */
#endif
} uart_conf_t;
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CPU_COMMON_H */
/** @} */

21
cpu/mips_pic32_common/ldscripts/xfa.ld
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@ -1,21 +0,0 @@
SECTIONS
{
.data :
{
KEEP (*(SORT(.xfa.*)))
}
_fdata = ADDR(.data);
_edata = (_fdata + SIZEOF(.data));
}
INSERT BEFORE .sbss;
SECTIONS
{
.rodata :
{
KEEP (*(SORT(.roxfa.*)))
}
}
INSERT AFTER .dtors;

3
cpu/mips_pic32_common/periph/Makefile
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@ -1,3 +0,0 @@
MODULE = mips_pic32_common_periph
include $(RIOTMAKE)/periph.mk

18
cpu/mips_pic32_common/periph/cpuid.c
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@ -1,18 +0,0 @@
/*
* Copyright(C) 2017 Francois Berder <fberder@outlook.fr>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
#include <stdint.h>
#include <string.h>
#include "board.h"
#include "periph/cpuid.h"
void cpuid_get(void *id)
{
memcpy(id, (uint32_t*)&DEVID, CPUID_LEN);
}

334
cpu/mips_pic32_common/periph/gpio.c
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/*
* Copyright(C) 2017 Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
/**
* @ingroup cpu_mips_pic32_common
* @ingroup drivers_periph_gpio
* @{
*
* @file
* @brief Low-level GPIO driver implementation
*
* @}
*/
#include "cpu.h"
#include "eic.h"
#include "bitarithm.h"
#include "periph/gpio.h"
#include "periph_conf.h"
#define LATx(P) ((P)[0x30/0x4])
#define LATxCLR(P) ((P)[0x34/0x4])
#define LATxSET(P) ((P)[0x38/0x4])
#define LATxINV(P) ((P)[0x3C/0x4])
#define PORTx(P) ((P)[0x20/0x4])
#define CNPUxCLR(P) ((P)[0x54/0x4])
#define CNPUxSET(P) ((P)[0x58/0x4])
#define CNPDxCLR(P) ((P)[0x64/0x4])
#define CNPDxSET(P) ((P)[0x68/0x4])
#define ODCxCLR(P) ((P)[0x44/0x4])
#define ODCxSET(P) ((P)[0x48/0x4])
#define ANSELxCLR(P) ((P)[0x04/0x4])
#define TRISxCLR(P) ((P)[0x14/0x4])
#define TRISxSET(P) ((P)[0x18/0x4])
#define CNENxCLR(P) ((P)[0x84/0x4])
#define CNENxSET(P) ((P)[0x88/0x4])
#define CNNExCLR(P) ((P)[0xA4/0x4])
#define CNNExSET(P) ((P)[0xA8/0x4])
#define CNSTATx(P) ((P)[0x90/0x4])
#define CNCONxCLR(P) ((P)[0x74/0x4])
#define CNCONxSET(P) ((P)[0x78/0x4])
#define CNFx(P) ((P)[0xB0/0x4])
/**
* @brief Extract the port base address from the given pin identifier
*/
static inline volatile unsigned int * _port(gpio_t pin)
{
return (volatile unsigned int *)(pin & ~(0xff));
}
/**
* @brief Extract the port number form the given identifier
*
* The port number is extracted by looking at bits 8, 9, 10, 11 of the base
* register addresses.
*/
static inline int _port_num(gpio_t pin)
{
return ((pin >> 8) & 0x0f);
}
/**
* @brief Extract the pin number from the last 4 bit of the pin identifier
*/
static inline int _pin_num(gpio_t pin)
{
return (pin & 0x0f);
}
#ifdef MODULE_PERIPH_GPIO_IRQ
/**
* @brief The PIC32 family has 7 I/O ports and 16 I/O per port
*/
#define PORT_NUMOF (7U)
#define GPIO_NUMOF (16U)
static gpio_flank_t isr_flank[PORT_NUMOF][GPIO_NUMOF];
static gpio_isr_ctx_t isr_ctx[PORT_NUMOF][GPIO_NUMOF];
#if defined(CPU_FAM_PIC32MX)
static void isr_handler(uint32_t port_addr)
{
uint32_t cnstat = CNSTATx(_port(port_addr));
uint32_t port = PORTx(_port(port_addr));
cnstat &= (1 << GPIO_NUMOF) - 1;
uint8_t pin = 0;
while (cnstat) {
cnstat = bitarithm_test_and_clear(cnstat, &pin);
if (isr_flank[_port_num(port_addr)][pin] == GPIO_BOTH
|| (isr_flank[_port_num(port_addr)][pin] == GPIO_RISING && (port & (1U << pin)))
|| (isr_flank[_port_num(port_addr)][pin] == GPIO_FALLING && !(port & (1U << pin))))
isr_ctx[_port_num(port_addr)][pin].cb(isr_ctx[_port_num(port_addr)][pin].arg);
}
}
static void cn_isr(void)
{
#ifdef _PORTA_BASE_ADDRESS
isr_handler(_PORTA_BASE_ADDRESS);
#endif
#ifdef _PORTB_BASE_ADDRESS
isr_handler(_PORTB_BASE_ADDRESS);
#endif
#ifdef _PORTC_BASE_ADDRESS
isr_handler(_PORTC_BASE_ADDRESS);
#endif
#ifdef _PORTD_BASE_ADDRESS
isr_handler(_PORTD_BASE_ADDRESS);
#endif
#ifdef _PORTE_BASE_ADDRESS
isr_handler(_PORTE_BASE_ADDRESS);
#endif
#ifdef _PORTF_BASE_ADDRESS
isr_handler(_PORTF_BASE_ADDRESS);
#endif
#ifdef _PORTG_BASE_ADDRESS
isr_handler(_PORTG_BASE_ADDRESS);
#endif
mips32r2_isr_end();
}
#elif defined(CPU_FAM_PIC32MZ)
static void isr_handler(uint32_t port_addr)
{
uint8_t pin = 0;
unsigned state = CNFx(_port(port_addr));
CNFx(_port(port_addr)) = 0;
while (state) {
state = bitarithm_test_and_clear(state, &pin);
isr_ctx[_port_num(port_addr)][pin].cb(isr_ctx[_port_num(port_addr)][pin].arg);
}
}
static void cn_porta_isr(void)
{
isr_handler(_PORTA_BASE_ADDRESS);
mips32r2_isr_end();
}
static void cn_portb_isr(void)
{
isr_handler(_PORTB_BASE_ADDRESS);
mips32r2_isr_end();
}
static void cn_portc_isr(void)
{
isr_handler(_PORTC_BASE_ADDRESS);
mips32r2_isr_end();
}
static void cn_portd_isr(void)
{
isr_handler(_PORTD_BASE_ADDRESS);
mips32r2_isr_end();
}
static void cn_porte_isr(void)
{
isr_handler(_PORTE_BASE_ADDRESS);
mips32r2_isr_end();
}
static void cn_portf_isr(void)
{
isr_handler(_PORTF_BASE_ADDRESS);
mips32r2_isr_end();
}
static void cn_portg_isr(void)
{
isr_handler(_PORTG_BASE_ADDRESS);
mips32r2_isr_end();
}
#endif
#endif /* MODULE_PERIPH_GPIO_IRQ */
int gpio_init(gpio_t pin, gpio_mode_t mode)
{
volatile unsigned int * port = _port(pin);
int pin_num = _pin_num(pin);
uint8_t output = 0, pu = 0, pd = 0, od = 0;
switch (mode) {
case GPIO_IN:
break;
case GPIO_IN_PD:
pd = 1;
break;
case GPIO_IN_PU:
pu = 1;
break;
case GPIO_OD_PU:
pu = 1; /* fall-through */
case GPIO_OD:
od = 1; /* fall-through */
case GPIO_OUT:
output = 1;
break;
}
ANSELxCLR(port) = 1U << pin_num; /* Configure GPIO as digital */
if (pu)
CNPUxSET(port) = 1U << pin_num;
else
CNPUxCLR(port) = 1U << pin_num;
if (pd)
CNPDxSET(port) = 1U << pin_num;
else
CNPDxCLR(port) = 1U << pin_num;
if (od)
ODCxSET(port) = 1U << pin_num;
else
ODCxCLR(port) = 1U << pin_num;
if (output)
TRISxCLR(port) = 1U << pin_num;
else
TRISxSET(port) = 1U << pin_num;
return 0;
}
int gpio_read(gpio_t pin)
{
return PORTx(_port(pin)) & (1U << _pin_num(pin));
}
void gpio_set(gpio_t pin)
{
LATxSET(_port(pin)) = 1U << _pin_num(pin);
}
void gpio_clear(gpio_t pin)
{
LATxCLR(_port(pin)) = 1U << _pin_num(pin);
}
void gpio_toggle(gpio_t pin)
{
LATxINV(_port(pin)) = 1U << _pin_num(pin);
}
void gpio_write(gpio_t pin, int value)
{
if (value)
gpio_set(pin);
else
gpio_clear(pin);
}
#ifdef MODULE_PERIPH_GPIO_IRQ
int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
gpio_cb_t cb, void *arg)
{
int pin_num = _pin_num(pin);
int port_num = _port_num(pin);
/* set callback */
isr_ctx[port_num][pin_num].cb = cb;
isr_ctx[port_num][pin_num].arg = arg;
isr_flank[port_num][pin_num] = flank;
/* initialize pin as input */
gpio_init(pin, mode);
#if defined(CPU_FAM_PIC32MX)
set_external_isr_cb(_CHANGE_NOTICE_VECTOR, cn_isr);
eic_configure_priority(_CHANGE_NOTICE_VECTOR, 1, 0);
eic_enable(_CHANGE_NOTICE_A_IRQ + port_num);
#elif defined(CPU_FAM_PIC32MZ)
switch (port_num) {
case PORT_A: set_external_isr_cb(_CHANGE_NOTICE_A_VECTOR, cn_porta_isr); break;
case PORT_B: set_external_isr_cb(_CHANGE_NOTICE_B_VECTOR, cn_portb_isr); break;
case PORT_C: set_external_isr_cb(_CHANGE_NOTICE_C_VECTOR, cn_portc_isr); break;
case PORT_D: set_external_isr_cb(_CHANGE_NOTICE_D_VECTOR, cn_portd_isr); break;
case PORT_E: set_external_isr_cb(_CHANGE_NOTICE_E_VECTOR, cn_porte_isr); break;
case PORT_F: set_external_isr_cb(_CHANGE_NOTICE_F_VECTOR, cn_portf_isr); break;
case PORT_G: set_external_isr_cb(_CHANGE_NOTICE_G_VECTOR, cn_portg_isr); break;
}
eic_configure_priority(_CHANGE_NOTICE_A_VECTOR + port_num, 1, 0);
eic_enable(_CHANGE_NOTICE_A_VECTOR + port_num);
CNCONxSET(_port(pin)) = _CNCONB_EDGEDETECT_MASK;
#endif
CNCONxSET(_port(pin)) = _CNCONB_ON_MASK;
gpio_irq_enable(pin);
return 0;
}
void gpio_irq_enable(gpio_t pin)
{
#if defined(CPU_FAM_PIC32MX)
CNENxSET(_port(pin)) = 1U << _pin_num(pin);
#elif defined(CPU_FAM_PIC32MZ)
switch (isr_flank[_port_num(pin)][_pin_num(pin)]) {
case GPIO_RISING:
CNENxSET(_port(pin)) = 1U << _pin_num(pin);
CNNExCLR(_port(pin)) = 1U << _pin_num(pin);
break;
case GPIO_FALLING:
CNENxCLR(_port(pin)) = 1U << _pin_num(pin);
CNNExSET(_port(pin)) = 1U << _pin_num(pin);
break;
case GPIO_BOTH:
CNENxSET(_port(pin)) = 1U << _pin_num(pin);
CNNExSET(_port(pin)) = 1U << _pin_num(pin);
break;
}
#endif
}
void gpio_irq_disable(gpio_t pin)
{
CNENxCLR(_port(pin)) = 1U << _pin_num(pin);
#if defined(CPU_FAM_PIC32Mz)
CNNExCLR(_port(pin)) = 1U << _pin_num(pin);
#endif
}
#endif /* MODULE_PERIPH_GPIO_IRQ */

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cpu/mips_pic32_common/periph/hwrng.c
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/*
* Copyright(C) 2017 Francois Berder <fberder@outlook.fr>
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
#include <string.h>
#include "board.h"
#include "periph/hwrng.h"
#ifdef _RNG
static void wait_plen_cycles(void)
{
unsigned int i;
for (i = 0; i < (RNGCON & _RNGCON_PLEN_MASK); ++i)
__asm volatile ("nop");
}
void hwrng_init(void)
{
RNGCON = _RNGCON_TRNGEN_MASK;
/*
* Wait to have at least 64 bits before setting the 64-bit seed
* of the pseudo random generator.
*/
while (RNGCNT < 64) {}
/* Load seed from the TRNG */
RNGCON |= _RNGCON_LOAD_MASK;
while (RNGCON & _RNGCON_LOAD_MASK) {}
RNGCON &= ~_RNGCON_TRNGEN_MASK;
RNGPOLY1 = 0x00C00003;
RNGPOLY2 = 0x00000000;
RNGCON |= 42; /* Set PLEN to 42 */
RNGCON |= _RNGCON_CONT_MASK;
}
void hwrng_read(void *buf, unsigned int num)
{
unsigned int i = 0;
uint8_t *buffer = (uint8_t *)buf;
RNGCON |= _RNGCON_PRNGEN_MASK;
for (i = 0; i < (num >> 3); ++i) {
uint32_t rng1, rng2;
wait_plen_cycles();
rng1 = RNGNUMGEN1;
rng2 = RNGNUMGEN2;
memcpy(buffer, &rng1, sizeof(rng1));
memcpy(buffer + 4, &rng2, sizeof(rng2));
buffer += 8;
}
num &= 0x7;
if (num) {
uint32_t rng1, n = num & 0x3;
wait_plen_cycles();
rng1 = RNGNUMGEN1;
memcpy(buffer, &rng1, n);
num -= n;
buffer += n;
if (num) {
uint32_t rng2 = RNGNUMGEN2;
memcpy(buffer, &rng2, num);
}
}
RNGCON &= ~_RNGCON_PRNGEN_MASK;
}
#endif /* _RNG */

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cpu/mips_pic32_common/periph/pm.c
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/*
* Copyright 2020 Francois Berder
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_mips_pic32_common
* @ingroup drivers_periph_pm
* @{
*
* @file
* @brief common periph/pm functions
*
* @author Francois Berder <fberder@outlook.fr >
*
* @}
*/
#include "periph/pm.h"
void pm_reboot(void)
{
/* Unlock OSCCON */
SYSKEY = 0x00000000;
SYSKEY = 0xAA996655;
SYSKEY = 0x556699AA;
/* Set SWRST bit to arm reset */
RSWRSTSET = 1;
/* Read RSWRST register to trigger reset */
RSWRST;
while(1);
}

218
cpu/mips_pic32_common/periph/timer.c
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@ -1,218 +0,0 @@
/*
* Copyright 2016, Imagination Technologies Limited and/or its
* affiliated group companies.
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_mips32r2_common
* @ingroup drivers_periph_timer
* @{
*
* @file
* @brief Implementation of the low-level timer driver
*
* @}
*/
#include <assert.h>
#include <mips/cpu.h>
#include <mips/m32c0.h>
#include <mips/regdef.h>
#include <mips/asm.h>
#include <string.h>
#include <periph/timer.h>
#include "cpu_conf.h"
#include <stdio.h>
#include "sched.h"
#include "thread.h"
#include "board.h"
#include "irq.h"
#include "timex.h"
#include "div.h"
#include <sys/time.h>
#include "eic.h"
/*
* setting TIMER_ACCURACY_SHIFT lower will improve accuracy
* at the cost of more regular interrupts (hence less power efficient).
* */
#define TIMER_ACCURACY_SHIFT (10)
#define TIMER_ACCURACY (1 << TIMER_ACCURACY_SHIFT)
#define CHANNELS (3)
/* TICKS_PER_US must be set in the board file */
#ifndef TICKS_PER_US
#error "Please set TICK_PER_US in your board file"
#endif
/*
* The base MIPS count / compare timer is fixed frequency at core clock / 2
* and is pretty basic This timer is currently only supported in Vectored
* Interrupt Mode (VI), EIC mode is partially supported in non-vectored mode
* only.
*
* RIOT's xtimer expects the timer to operate at 1MHZ or any 2^n multiple or
* factor of this, thus we maintain a software timer which counts at 1MHz.
* This is not particularly power efficient and may add latency too.
*
* If other SoC specific timers are available which are more flexible then
* it is advised to use them, this timer is a fallback version
* that should work on all MIPS implementations.
*
*/
static timer_isr_ctx_t timer_isr_ctx;
volatile unsigned int counter;
volatile unsigned int compares[CHANNELS];
static void timer_isr(void)
{
IFS0CLR =_IFS0_CTIF_MASK;
uint32_t status = irq_disable();
counter += TIMER_ACCURACY;
irq_restore(status);
if (counter == compares[0]) {
/*
* The Xtimer code expects the ISR to take some time
* but our counter is a fake software one, so bump it a
* bit to give the impression some time elapsed in the ISR.
* Without this the callback ( _shoot(timer) on xtimer_core.c )
* never fires.
*/
counter += TIMER_ACCURACY;
timer_isr_ctx.cb(timer_isr_ctx.arg, 0);
mips32r2_isr_end();
}
if (counter == compares[1]) {
timer_isr_ctx.cb(timer_isr_ctx.arg, 1);
mips32r2_isr_end();
}
if (counter == compares[2]) {
timer_isr_ctx.cb(timer_isr_ctx.arg, 2);
mips32r2_isr_end();
}
mips_setcompare(mips_getcount() + TICKS_PER_US * TIMER_ACCURACY);
}
/*
* The mips toolchain C library does not implement gettimeofday()
*
* implement it here using the timer.
*
*/
int gettimeofday(struct timeval *__restrict __p, void *__restrict __tz)
{
(void)__tz;
uint64_t now = counter * US_PER_MS;
__p->tv_sec = div_u64_by_1000000(now);
__p->tv_usec = now - (__p->tv_sec * US_PER_SEC);
return 0;
}
int timer_init(tim_t dev, uint32_t freq, timer_cb_t cb, void *arg)
{
assert(dev == 0);
(void)dev;
(void)freq; /* Cannot adjust Frequency */
timer_isr_ctx.cb = cb;
timer_isr_ctx.arg = arg;
/* Clear down soft counters */
memset((void *)compares, 0, sizeof(compares));
counter = (1 << TIMER_ACCURACY_SHIFT);
/* Set compare up */
mips_setcompare(mips_getcount() + TICKS_PER_US * TIMER_ACCURACY);
/* Start the timer if stopped */
mips32_bc_c0(C0_CAUSE, CR_DC);
/* Enable Timer Interrupts */
set_external_isr_cb(_CORE_TIMER_VECTOR, timer_isr);
eic_configure_priority(_CORE_TIMER_VECTOR, 1, 0);
eic_enable(_CORE_TIMER_VECTOR);
return 0;
}
int timer_set(tim_t dev, int channel, unsigned int timeout)
{
assert(dev == 0);
assert(channel < CHANNELS);
(void)dev;
timeout >>= TIMER_ACCURACY_SHIFT;
timeout <<= TIMER_ACCURACY_SHIFT;
uint32_t status = irq_disable();
compares[channel] = counter + timeout;
irq_restore(status);
return 0;
}
int timer_set_absolute(tim_t dev, int channel, unsigned int value)
{
assert(dev == 0);
assert(channel < CHANNELS);
(void)dev;
value >>= TIMER_ACCURACY_SHIFT;
value <<= TIMER_ACCURACY_SHIFT;
uint32_t status = irq_disable();
compares[channel] = value;
irq_restore(status);
return 0;
}
int timer_clear(tim_t dev, int channel)
{
assert(dev == 0);
assert(channel < CHANNELS);
(void)dev;
uint32_t status = irq_disable();
compares[channel] = 0;
irq_restore(status);
return 0;
}
unsigned int timer_read(tim_t dev)
{
assert(dev == 0);
(void)dev;
return counter;
}
void timer_start(tim_t dev)
{
(void)dev;
mips32_bc_c0(C0_CAUSE, CR_DC);
}
void timer_stop(tim_t dev)
{
(void)dev;
mips32_bs_c0(C0_CAUSE, CR_DC);
}

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cpu/mips_pic32_common/periph/uart.c
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/*
* Copyright(C) 2016,2017 Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
/**
* @ingroup cpu_mips_pic32_common
* @ingroup drivers_periph_uart
* @{
*
* @file
* @brief Peripheral UART driver implementation
*
* @}
*/
#include "cpu.h"
#include "eic.h"
#include "sched.h"
#include "thread.h"
#include "assert.h"
#include "periph/uart.h"
#include "periph/gpio.h"
#define UxMODE(U) ((U)[0x00/4])
#define UxMODECLR(U) ((U)[0x04/4])
#define UxMODESET(U) ((U)[0x08/4])
#define UxSTA(U) ((U)[0x10/4])
#define UxSTACLR(U) ((U)[0x14/4])
#define UxSTASET(U) ((U)[0x18/4])
#define UxTXREG(U) ((U)[0x20/4])
#define UxRXREG(U) ((U)[0x30/4])
#define UxBRG(U) ((U)[0x40/4])
/**
* @brief Allocate memory to store the callback functions.
*/
static uart_isr_ctx_t uart_ctx[UART_NUMOF];
static void irq_handler(uart_t uart)
{
uint32_t status = UxSTA(uart_config[uart].base);
if (status & _U1STA_URXDA_MASK) {
uart_ctx[uart].rx_cb(uart_ctx[uart].arg, UxRXREG(uart_config[uart].base));
}
if (status & _U1STA_OERR_MASK) {
UxSTA(uart_config[uart].base) &= ~_U1STA_OERR_MASK;
}
#ifdef CPU_FAM_PIC32MX
eic_clear_flag(uart_config[uart].irq);
#else
eic_clear_flag(uart_config[uart].vector);
#endif
mips32r2_isr_end();
}
#ifdef UART_0_ISR
void UART_0_ISR(void)
{
irq_handler(UART_DEV(0));
}
#endif
#ifdef UART_1_ISR
void UART_1_ISR(void)
{
irq_handler(UART_DEV(1));
}
#endif
#ifdef UART_2_ISR
void UART_2_ISR(void)
{
irq_handler(UART_DEV(2));
}
#endif
#ifdef UART_3_ISR
void UART_3_ISR(void)
{
irq_handler(UART_DEV(3));
}
#endif
#ifdef UART_4_ISR
void UART_4_ISR(void)
{
irq_handler(UART_DEV(4));
}
#endif
#ifdef UART_5_ISR
void UART_5_ISR(void)
{
irq_handler(UART_DEV(5));
}
#endif
static void uart_init_pins(uart_t uart, uart_rx_cb_t rx_cb)
{
/* configure TX pin */
gpio_init(uart_config[uart].tx_pin, GPIO_OUT);
/* set TX pin high to avoid garbage during further initialization */
gpio_set(uart_config[uart].tx_pin);
*(uart_config[uart].tx_mux_reg) = uart_config[uart].tx_af;
/* configure RX pin */
if (rx_cb) {
gpio_init(uart_config[uart].rx_pin, GPIO_IN_PU);
*(uart_config[uart].rx_mux_reg) = uart_config[uart].rx_af;
}
}
int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
{
assert(uart < UART_NUMOF);
uart_init_pins(uart, rx_cb);
UxBRG(uart_config[uart].base) = (uart_config[uart].clock / (16 * baudrate)) - 1;
UxSTA(uart_config[uart].base) = 0;
if (rx_cb) {
/* register callbacks */
uart_ctx[uart].rx_cb = rx_cb;
uart_ctx[uart].arg = arg;
UxSTASET(uart_config[uart].base) = _U1STA_URXEN_MASK;
switch (uart) {
#ifdef UART_0_ISR
case UART_DEV(0): set_external_isr_cb(uart_config[uart].vector, UART_0_ISR); break;
#endif
#ifdef UART_1_ISR
case UART_DEV(1): set_external_isr_cb(uart_config[uart].vector, UART_1_ISR); break;
#endif
#ifdef UART_2_ISR
case UART_DEV(2): set_external_isr_cb(uart_config[uart].vector, UART_2_ISR); break;
#endif
#ifdef UART_3_ISR
case UART_DEV(3): set_external_isr_cb(uart_config[uart].vector, UART_3_ISR); break;
#endif
#ifdef UART_4_ISR
case UART_DEV(4): set_external_isr_cb(uart_config[uart].vector, UART_4_ISR); break;
#endif
#ifdef UART_5_ISR
case UART_DEV(5): set_external_isr_cb(uart_config[uart].vector, UART_5_ISR); break;
#endif
}
eic_configure_priority(uart_config[uart].vector, 1, 0);
#ifdef CPU_FAM_PIC32MX
eic_enable(uart_config[uart].irq);
#else
eic_enable(uart_config[uart].vector);
#endif
}
UxSTASET(uart_config[uart].base) = _U1STA_UTXEN_MASK;
UxMODE(uart_config[uart].base) = _U1MODE_ON_MASK;
return 0;
}
void uart_write(uart_t uart, const uint8_t *data, size_t len)
{
assert(uart < UART_NUMOF);
while(len--) {
while(UxSTA(uart_config[uart].base)& _U1STA_UTXBF_MASK) {}
UxTXREG(uart_config[uart].base) = *data++;
}
}
void uart_poweron(uart_t uart)
{
assert(uart < UART_NUMOF);
UxMODESET(uart_config[uart].base)= _U1MODE_ON_MASK;
}
void uart_poweroff(uart_t uart)
{
assert(uart < UART_NUMOF);
UxMODECLR(uart_config[uart].base)= _U1MODE_ON_MASK;
}

244
cpu/mips_pic32_common/reset_mod.S
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/*
* Copyright 2014-2015, Imagination Technologies Limited and/or its
* affiliated group companies.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/* ************ PLEASE READ ME !!!! ****************
This file is a copy of the reset_mod.S from $MIPS_ELF_ROOT/share/mips/boot
(from the 2016.05-03 version) with a couple of modifications:
#define SKIP_COPY_TO_RAM - prevents the bootloader copying the whole contents
of flash to ram (as we want to XIP from flash), we copy initialized data from
flash to ram in 'software_init_hook'.
move .org's to before the labels to make the vector labels appear at the vector
addresses.
In boot_debug_exception vector drop out of debug mode before spining, this allows
attachment of an external debug program to investigate a hung system.
Future toolchain versions will have these changes included and this file will
be no longer needed.
Note the above copyright/license is 3 Clause BSD and as such is compatible with LGPLv2.1
as such we grant licensing this file under LGPLv2.1 (See the file LICENSE in the top level
directory for more details) as well.
Thanks for reading.
*/
#define _RESETCODE
.set nomips16
#include <mips/regdef.h>
#include <mips/cpu.h>
#include <mips/asm.h>
.set push
.set nomicromips
LEAF(__reset_vector)
lui a2, %hi(__cpu_init)
addiu a2, %lo(__cpu_init)
mtc0 $0, C0_COUNT # Clear cp0 Count (Used to measure boot time.)
jr a2
.space 32 # Just to cope with a quirk of MIPS malta boards
# this can be deleted for anything else.
END(__reset_vector)
.set pop
LEAF(__cpu_init)
# Verify the code is here due to a reset and not NMI. If this is an NMI then trigger
# a debugger breakpoint using a sdbp instruction.
mfc0 s1, C0_STATUS # Read CP0 Status
ext s1, s1, SR_NMI_SHIFT, 1 # extract NMI
beqz s1, init_resources # /* Branch if this is NOT an NMI exception. */
move k0, t9 # Preserve t9
move k1, a0 # Preserve a0
li $25, 15 # UHI exception operation
li $4, 0 # Use hard register context
sdbbp 1 # Invoke UHI operation
init_resources:
# Init CP0 Status, Count, Compare, Watch*, and Cause.
jal __init_cp0
# Initialise L2/L3 cache
# This could be done from cached code if there is a cca override or similar
# Determine L2/L3 cache config.
lui a2, %hi(__init_l23cache)
addiu a2, a2, %lo(__init_l23cache)
jal a2
init_ic:
# Initialize the L1 instruction cache.
jal __init_icache
# The changing of Kernel mode cacheability must be done from KSEG1
# Since the code is executing from KSEG0 It needs to do a jump to KSEG1 change K0
# and jump back to KSEG0
lui a2, %hi(__change_k0_cca)
addiu a2, a2, %lo(__change_k0_cca)
li a1, 0xf
ins a2, a1, 29, 1 # changed to KSEG1 address by setting bit 29
jalr a2
.weak __init_l23cache_cached
lui a2, %hi(__init_l23cache_cached)
addiu a2, a2, %lo(__init_l23cache_cached)
beqz a2, init_dc
jal a2
init_dc:
# Initialize the L1 data cache
jal __init_dcache
# Initialize the TLB.
jal __init_tlb
# Allow everything else to be initialized via a hook.
.weak __boot_init_hook
lui a2, %hi(__boot_init_hook)
addiu a2, a2, %lo(__boot_init_hook)
beqz a2, 1f
jalr a2
1:
#ifndef SKIP_COPY_TO_RAM
# Copy code and data to RAM
li s1, 0xffffffff
# Copy code and read-only/initialized data from FLASH to (uncached) RAM.
lui a1, %hi(__flash_app_start)
addiu a1, a1, %lo(__flash_app_start)
ins a1, s1, 29, 1 # Make it uncached (kseg1)
lui a2, %hi(__app_start)
addiu a2, a2, %lo(__app_start)
ins a2, s1, 29, 1 # Make it uncached (kseg1)
lui a3, %hi(_edata)
addiu a3, a3, %lo(_edata)
ins a3, s1, 29, 1 # Make it uncached (kseg1)
beq a2, a3, $Lcopy_to_ram_done
$Lnext_ram_word:
lw a0, 0(a1)
sw a0, 0(a2)
addiu a2, a2, 4
addiu a1, a1, 4
bne a3, a2, $Lnext_ram_word
$Lcopy_to_ram_done:
#endif
# Prepare for eret to _start
lui ra, %hi($Lall_done) # If main returns then go to all_done.
addiu ra, ra, %lo($Lall_done)
lui v0, %hi(_start) # Load the address of _start
addiu v0, v0, %lo(_start)
mtc0 v0, C0_ERRPC # Set ErrorEPC to _start
ehb # Clear hazards (makes sure write to ErrorPC has completed)
li a0, 0 # UHI compliant null argument setup
# Return from exception will now execute the application startup code
eret
$Lall_done:
# If _start returns it will return to this point.
# Just spin here reporting the exit.
li $25, 1 # UHI exit operation
move $4, v0 # /* Collect exit code for UHI exit */
sdbbp 1 # Invoke UHI operation
b $Lall_done
END(__cpu_init)
/**************************************************************************************
B O O T E X C E P T I O N H A N D L E R S (CP0 Status[BEV] = 1)
**************************************************************************************/
/* NOTE: the linker script must insure that this code starts at start + 0x200 so the exception */
/* vectors will be addressed properly. All .org assume this! */
/* TLB refill, 32 bit task. */
.org 0x200 # TLB refill, 32 bit task.
LEAF(__boot_tlb_refill)
move k0, t9 # Preserve t9
move k1, a0 # Preserve a0
li $25, 15 # UHI exception operation
li $4, 0 # Use hard register context
sdbbp 1 # Invoke UHI operation
END(__boot_tlb_refill)
.org 0x280 # XTLB refill, 64 bit task. BEV + 0x280
LEAF(__boot_xtlb_refill)
move k0, t9 # Preserve t9
move k1, a0 # Preserve a0
li $25, 15 # UHI exception operation
li $4, 0 # Use hard register context
sdbbp 1 # Invoke UHI operation
END(__boot_xtlb_refill)
.org 0x300 # Cache error exception. BEV + 0x300
LEAF(__boot_cache_error)
move k0, t9 # Preserve t9
move k1, a0 # Preserve a0
li $25, 15 # UHI exception operation
li $4, 0 # Use hard register context
sdbbp 1 # Invoke UHI operation
END(__boot_cache_error)
.org 0x380 # General exception. BEV + 0x380
LEAF(__boot_general_exception)
move k0, t9 # Preserve t9
move k1, a0 # Preserve a0
li $25, 15 # UHI exception operation
li $4, 0 # Use hard register context
sdbbp 1 # Invoke UHI operation
END(__boot_general_exception)
# If you want the above code to fit into 1k flash you will need to leave
# out the code below. This is the code that covers the debug exception
# which you normally will not get.
.org 0x480
LEAF(__boot_debug_exception)
# EJTAG Debug (with ProbEn = 0 in the EJTAG Control Register)
mfc0 k1, C0_DEPC # Save Debug exception point in DESAVE
mtc0 k1, C0_DESAVE
LA k1, 1f
# Drop out of debug mode before spinning (To allow a JTAG probe in).
mtc0 k1, C0_DEPC
ehb
deret
1:
b 1b #Spin indefinitely
END(__boot_debug_exception)

35
cpu/mips_pic32mx/Kconfig
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# Copyright (c) 2020 HAW Hamburg
#
# This file is subject to the terms and conditions of the GNU Lesser
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.
#
config CPU_FAM_PIC32MX
bool
select CPU_COMMON_MIPS_PIC32
select CPU_CORE_M4K
select HAS_CPU_MIPS_PIC32MX
## CPU Models
config CPU_MODEL_P32MX470F512H
bool
select CPU_FAM_PIC32MX
## Declaration of specific features
config HAS_CPU_MIPS_PIC32MX
bool
help
Indicates that a 'mips_pic32mx' cpu is being used.
## Common CPU symbols
config CPU_FAM
default "pic32mx" if CPU_FAM_PIC32MX
config CPU_MODEL
default "p32mx470f512h" if CPU_MODEL_P32MX470F512H
config CPU
default "mips_pic32mx" if CPU_FAM_PIC32MX
source "$(RIOTCPU)/mips_pic32_common/Kconfig"

6
cpu/mips_pic32mx/Makefile
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@ -1,6 +0,0 @@
MODULE = cpu
DIRS += $(RIOTCPU)/mips_pic32_common
DIRS += $(RIOTCPU)/mips32r2_common
include $(RIOTBASE)/Makefile.base

1
cpu/mips_pic32mx/Makefile.dep
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include $(RIOTCPU)/mips_pic32_common/Makefile.dep

4
cpu/mips_pic32mx/Makefile.features
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@ -1,4 +0,0 @@
CPU_CORE = m4k
CPU_FAM = pic32mx
include $(RIOTCPU)/mips_pic32_common/Makefile.features

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cpu/mips_pic32mx/Makefile.include
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export ROMABLE = 1
include $(RIOTCPU)/mips_pic32_common/Makefile.include
include $(RIOTMAKE)/arch/mips.inc.mk
# define build specific options
CFLAGS += -march=m4k -DSKIP_COPY_TO_RAM
LINKFLAGS += -Wl,--defsym,__use_excpt_boot=0 $(CFLAGS)
LINKFLAGS += -Tpic32mx512_12_128_uhi.ld
# the pickit programmer (MPLAB-IPE) wants physical addresses in the hex file!!
OBJCOPY = objcopy #use system objcopy as toolchain one is broken.
OFLAGS += \
--change-section-lma .bootflash-0xA0000000 \
--change-section-lma .exception_vector-0x80000000 \
--change-section-lma .text-0x80000000 \
--change-section-lma .init-0x80000000 \
--change-section-lma .fini-0x80000000 \
--change-section-lma .eh_frame-0x80000000 \
--change-section-lma .ctors-0x80000000 \
--change-section-lma .dtors-0x80000000 \
--change-section-lma .rodata-0x80000000 \
--change-section-lma .data-0x80000000 \
--change-section-lma .bss-0x80000000 \
--change-section-lma .startdata-0x80000000 \
ifneq (,$(filter cpp,$(FEATURES_USED)))
OFLAGS += --change-section-lma .gcc_except_table-0x80000000
endif
# system objcopy is not able to generate a binfile for MIPS
BINFILE =
# hence, use HEXFILE instead for hashing
HASHFILE = $(HEXFILE)

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cpu/mips_pic32mx/include/cpu_conf.h
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/*
* Copyright(C) 2016,2017, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
/**
* @defgroup cpu_mips_pic32mx PIC32MX
* @ingroup cpu
* @{
*
* @file
* @brief CPU definitions for Microchip PIC32MX devices.
*
* @author Neil Jones <neil.jones@imgtec.com>
*/
#ifndef CPU_CONF_H
#define CPU_CONF_H
#ifdef CPU_MODEL_P32MX470F512H
#include "vendor/p32mx470f512h.h"
#else
#error "No CPU headers for the defined CPU_MODEL found"
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Configuration of default stack sizes
*
* printf takes a pretty tortured route through the C lib
* then via UHI syscall exception to end up at the UART
* driver.
*
* When debugging timer code we get printfs on the idle threads
* stack which can easily blow its limits.
*
* Note code must be compiled at -Os with these values, using -O0
* you'll overflow these stacks.
*
* NO ISR stack is in use yet, interrupt use the current running stack
* hence the big-ish default stack size.
* @{
*/
#ifndef THREAD_EXTRA_STACKSIZE_PRINTF
#define THREAD_EXTRA_STACKSIZE_PRINTF (1024)
#endif
#ifndef THREAD_STACKSIZE_DEFAULT
#define THREAD_STACKSIZE_DEFAULT (2048)
#endif
#ifndef THREAD_STACKSIZE_IDLE
#ifdef NDEBUG
#define THREAD_STACKSIZE_IDLE (512)
#else
#define THREAD_STACKSIZE_IDLE (512 + THREAD_EXTRA_STACKSIZE_PRINTF)
#endif
#endif
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* CPU_CONF_H */
/** @} */

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cpu/mips_pic32mx/include/periph_cpu.h
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/*
* Copyright(C) 2016,2017, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
#ifndef PERIPH_CPU_H
#define PERIPH_CPU_H
#include "periph_cpu_common.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CPU_H */

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cpu/mips_pic32mx/include/vendor/p32mx470f512h.h vendored
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324
cpu/mips_pic32mx/ldscripts/pic32mx512_12_128_uhi.ld
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/*
* For all MX devices with 512K program flash / 12KB boot flash and 128KB Ram
*
* A platform and target independent link script to produce UHI
* compliant binaries with varying levels of system initialization
* support.
*/
__entry = DEFINED(__reset_vector) ? 0xbfc00000 : _start;
ENTRY(__entry)
OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradbigmips", "elf32-tradlittlemips")
GROUP(-lc -luhi -lgcc -lhal)
SEARCH_DIR(.)
__DYNAMIC = 0;
STARTUP(crt0.o)
/* Force the exception handler to be registered */
EXTERN(__register_excpt_handler)
/* Force the exception handler to be included in the link */
EXTERN(__exception_entry)
/*
* Require verbose exceptions. This can be changed to pull in
* __exception_handle_quiet to reduce code size but be less
* informative
*/
EXTERN(__exception_handle_verbose)
/* Force the interrupt handlers to tbe included in the link */
EXTERN(__isr_vec)
/* Require the UHI getargs support */
EXTERN(__getargs)
/*
* Set the location of the top of the stack. A value of 0 means
* that it will be automatically placed at the highest address
* available as described by the __memory_* setttings
*/
PROVIDE (__stack = 0);
/* Size of the memory returned by _get_ram_range */
PROVIDE (__memory_size = 128K);
/* Base of the memory returned by _get_ram_range */
PROVIDE (__memory_base = 0x80000000);
/* Stride length for tlb software invalidate for tlbinvf
* (mipsXXr3+). Some MIPS implementations may layout the sets/ways
* differently in the index register. Either sets LSB or ways LSB.
*
* By setting this to 1 we presume that sets come first. The default boot
* code will decrement this value from the Number of TLB entries.
*/
PROVIDE (__tlb_stride_length = 1);
/* By default, XPA is not used even if available. To enable XPA,
* __enable_xpa should be 1.
*/
PROVIDE (__enable_xpa = 0);
/*
* 0 = Do not use exception handler present in boot for UHI
* 1 = Use exception handler present in boot for UHI if BEV is 0 at
* startup
* 2 = Always use exception handler present in boot for UHI
*/
PROVIDE (__use_excpt_boot = 0);
/*
* Include the code to be able to return to boot context. This is
* necessary if __use_excpt_boot != 0.
*/
EXTERN (__register_excpt_boot);
ASSERT (DEFINED(__register_excpt_boot) || __use_excpt_boot == 0,
"Registration for boot context is required for UHI chaining")
/* Control if subnormal floating-point values are flushed to zero in
hardware. This applies to both FPU and MSA operations. */
PROVIDE (__flush_to_zero = 1);
/* Set up the public symbols depending on whether the user has chosen
quiet or verbose exception handling above */
EXTERN (__exception_handle);
PROVIDE(__exception_handle = (DEFINED(__exception_handle_quiet)
? __exception_handle_quiet
: __exception_handle_verbose));
PROVIDE(_mips_handle_exception = __exception_handle);
/*
* Initalize some symbols to be zero so we can reference them in the
* crt0 without core dumping. These functions are all optional, but
* we do this so we can have our crt0 always use them if they exist.
* This is so BSPs work better when using the crt0 installed with gcc.
* We have to initalize them twice, so we multiple object file
* formats, as some prepend an underscore.
*/
PROVIDE (hardware_exit_hook = 0);
PROVIDE (hardware_hazard_hook = 0);
PROVIDE (hardware_init_hook = 0);
PROVIDE (software_init_hook = 0);
/* The default base address for application flash code is 0x9D001000 */
PROVIDE (__app_start = 0x9D001000) ;
/* Set default vector spacing to 32 bytes. */
PROVIDE (__isr_vec_space = 32);
/* Leave space for 9 vector entries by default. 8 entry points and one
fallback handler. */
PROVIDE (__isr_vec_count = 9);
/*
* The start of boot flash must be set if including boot code. By default
* the use of boot code will mean that application code is copied
* from flash to RAM at runtime before being executed.
*/
PROVIDE (__boot_flash_start = DEFINED(__reset_vector) ? 0xbfc00000 : __app_start);
PROVIDE (__bev_override = 0x9fc00000);
PROVIDE (__flash_vector_start = 0x9D000000);
PROVIDE (__flash_app_start = 0x9D001000);
SECTIONS
{
/* Start of bootrom */
.bootflash __bev_override : /* Runs uncached (from 0xBfc00000) until I$ is
initialized. */
AT (__boot_flash_start)
{
__base = .;
*(.reset) /* Reset entry point. */
*(.boot) /* Boot code. */
. = ALIGN(8);
. = __base + 0x2ff0; /*Alternate Config bits (lower Alias)*/
KEEP(*(.devcfg3))
KEEP(*(.devcfg2))
KEEP(*(.devcfg1))
KEEP(*(.devcfg0))
} = 0xFFFFFFFF
/* Start of the application */
.exception_vector ALIGN(__flash_vector_start, 0x1000) :
AT (__flash_vector_start)
{
PROVIDE (__excpt_ebase = ABSOLUTE(.));
__base = .;
KEEP(* (.text.__exception_entry))
. = __base + 0x200;
KEEP(* (SORT(.text.__isr_vec*)))
/* Leave space for all the vector entries */
. = __base + 0x200 + (__isr_vec_space * __isr_vec_count);
ASSERT(__isr_vec_space == (DEFINED(__isr_vec_sw0)
? __isr_vec_sw1 - __isr_vec_sw0
: __isr_vec_space),
"Actual ISR vector spacing does not match __isr_vec_space");
ASSERT(__base + 0x200 == (DEFINED(__isr_vec_sw0)
? __isr_vec_sw0 & 0xfffffffe : __base + 0x200),
"__isr_vec_sw0 is not placed at EBASE + 0x200");
. = ALIGN(8);
} = 0
. = __flash_app_start;
.text : {
_ftext = . ;
PROVIDE (eprol = .);
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
*(.mips16.fn.*)
*(.mips16.call.*)
}
.init : {
KEEP (*(.init))
}
.fini : {
KEEP (*(.fini))
}
.rel.sdata : {
PROVIDE (__runtime_reloc_start = .);
*(.rel.sdata)
PROVIDE (__runtime_reloc_stop = .);
}
PROVIDE (etext = .);
_etext = .;
.eh_frame_hdr : { *(.eh_frame_hdr) }
.eh_frame : { KEEP (*(.eh_frame)) }
.gcc_except_table : { *(.gcc_except_table*) }
.jcr : { KEEP (*(.jcr)) }
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
}
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
}
. = .;
.MIPS.abiflags : {
__MIPS_abiflags_start = .;
*(.MIPS.abiflags)
__MIPS_abiflags_end = .;
}
.rodata : {
*(.rdata)
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
}
_rom_data_copy = .;
.data ALIGN(__memory_base + 0x1000, 16) :
AT (_rom_data_copy)
{
_fdata = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
_gp = . + 0x8000;
__global = _gp;
*(.lit8)
*(.lit4)
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
}
. = ALIGN(4);
PROVIDE (edata = .);
_edata = .;
_fbss = .;
.sbss : {
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
}
.bss : {
_bss_start = . ;
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
}
. = ALIGN(4);
PROVIDE (end = .);
_end = .;
/* Now place the data that is only needed within start.S and can be
overwritten by the heap. */
.startdata : {
*(.startdata)
}
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to
the beginning of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_ranges 0 : { *(.debug_ranges) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* Special sections generated by gcc */
/* Newer GNU linkers strip by default */
.mdebug.abi32 0 : { KEEP(*(.mdebug.abi32)) }
.mdebug.abiN32 0 : { KEEP(*(.mdebug.abiN32)) }
.mdebug.abi64 0 : { KEEP(*(.mdebug.abi64)) }
.mdebug.abiO64 0 : { KEEP(*(.mdebug.abiO64)) }
.mdebug.eabi32 0 : { KEEP(*(.mdebug.eabi32)) }
.mdebug.eabi64 0 : { KEEP(*(.mdebug.eabi64)) }
.gcc_compiled_long32 0 : { KEEP(*(.gcc_compiled_long32)) }
.gcc_compiled_long64 0 : { KEEP(*(.gcc_compiled_long64)) }
}

1
cpu/mips_pic32mx/p32mx470f512h/Makefile
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@ -1 +0,0 @@
include $(RIOTBASE)/Makefile.base

2732
cpu/mips_pic32mx/p32mx470f512h/p32mx470f512h.S
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36
cpu/mips_pic32mz/Kconfig
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@ -1,36 +0,0 @@
# Copyright (c) 2020 HAW Hamburg
#
# This file is subject to the terms and conditions of the GNU Lesser
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.
#
config CPU_FAM_PIC32MZ
bool
select CPU_COMMON_MIPS_PIC32
select CPU_CORE_M5101
select HAS_CPU_MIPS_PIC32MZ
select HAS_PERIPH_HWRNG
## CPU Models
config CPU_MODEL_P32MZ2048EFG100
bool
select CPU_FAM_PIC32MZ
## Declaration of specific features
config HAS_CPU_MIPS_PIC32MZ
bool
help
Indicates that a 'mips_pic32mz' cpu is being used.
## Common CPU symbols
config CPU_FAM
default "pic32mz" if CPU_FAM_PIC32MZ
config CPU_MODEL
default "p32mz2048efg100" if CPU_MODEL_P32MZ2048EFG100
config CPU
default "mips_pic32mz" if CPU_FAM_PIC32MZ
source "$(RIOTCPU)/mips_pic32_common/Kconfig"

6
cpu/mips_pic32mz/Makefile
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@ -1,6 +0,0 @@
MODULE = cpu
DIRS += $(RIOTCPU)/mips_pic32_common
DIRS += $(RIOTCPU)/mips32r2_common
include $(RIOTBASE)/Makefile.base

1
cpu/mips_pic32mz/Makefile.dep
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@ -1 +0,0 @@
include $(RIOTCPU)/mips_pic32_common/Makefile.dep

6
cpu/mips_pic32mz/Makefile.features
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@ -1,6 +0,0 @@
CPU_CORE = m5101
CPU_FAM = pic32mz
FEATURES_PROVIDED += periph_hwrng
include $(RIOTCPU)/mips_pic32_common/Makefile.features

39
cpu/mips_pic32mz/Makefile.include
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@ -1,39 +0,0 @@
export ROMABLE = 1
include $(RIOTCPU)/mips_pic32_common/Makefile.include
include $(RIOTMAKE)/arch/mips.inc.mk
# define build specific options
CFLAGS += -march=m5101 -mmicromips -DSKIP_COPY_TO_RAM
CFLAGS += -DMIPS_MICROMIPS
LINKFLAGS += -Wl,--defsym,__use_excpt_boot=0 $(CFLAGS)
LINKFLAGS += -Tpic32mz2048_uhi.ld
# the pickit programmer (MPLAB-IPE) wants physical addresses in the hex file!!
OBJCOPY = objcopy #use system objcopy as toolchain one is broken.
OFLAGS += \
--change-section-lma .lowerbootflashalias-0xA0000000 \
--change-section-lma .bootflash1-0xA0000000 \
--change-section-lma .bootflash2-0xA0000000 \
--change-section-lma .exception_vector-0x80000000 \
--change-section-lma .text-0x80000000 \
--change-section-lma .init-0x80000000 \
--change-section-lma .fini-0x80000000 \
--change-section-lma .eh_frame-0x80000000 \
--change-section-lma .ctors-0x80000000 \
--change-section-lma .dtors-0x80000000 \
--change-section-lma .rodata-0x80000000 \
--change-section-lma .data-0x80000000 \
--change-section-lma .bss-0x80000000 \
--change-section-lma .startdata-0x80000000
ifneq (,$(filter cpp,$(FEATURES_USED)))
OFLAGS += --change-section-lma .gcc_except_table-0x80000000
endif
# system objcopy is not able to generate a binfile for MIPS
BINFILE =
# hence, use HEXFILE instead for hashing
HASHFILE = $(HEXFILE)

75
cpu/mips_pic32mz/include/cpu_conf.h
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@ -1,75 +0,0 @@
/*
* Copyright(C) 2017, 2016, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
/**
* @defgroup cpu_mips_pic32mz PIC32MZ
* @ingroup cpu
* @{
*
* @file
* @brief CPU definitions for Microchip PIC32MZ devices.
*
* @author Neil Jones <neil.jones@imgtec.com>
*/
#ifndef CPU_CONF_H
#define CPU_CONF_H
#ifdef CPU_MODEL_P32MZ2048EFG100
#include "vendor/p32mz2048efg100.h"
#else
#error "No CPU headers for the defined CPU_MODEL found"
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Configuration of default stack sizes
*
* printf takes a pretty tortured route through the C lib
* then via UHI syscall exception to end up at the UART
* driver.
*
* When debugging timer code we get printfs on the idle threads
* stack which can easily blow its limits.
*
* Note code must be compiled at -Os with these values, using -O0
* you'll overflow these stacks.
*
* NO ISR stack is in use yet, interrupt use the current running stack
* hence the big-ish default stack size.
* @{
*/
#ifndef THREAD_EXTRA_STACKSIZE_PRINTF
#define THREAD_EXTRA_STACKSIZE_PRINTF (1024)
#endif
#ifndef THREAD_STACKSIZE_DEFAULT
#define THREAD_STACKSIZE_DEFAULT (2048)
#endif
#ifndef THREAD_STACKSIZE_IDLE
#ifdef NDEBUG
#define THREAD_STACKSIZE_IDLE (512)
#else
#define THREAD_STACKSIZE_IDLE (512 + THREAD_EXTRA_STACKSIZE_PRINTF)
#endif
#endif
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* CPU_CONF_H */
/** @} */

24
cpu/mips_pic32mz/include/periph_cpu.h
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@ -1,24 +0,0 @@
/*
* Copyright(C) 2016,2017, Imagination Technologies Limited and/or its
* affiliated group companies.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*
*/
#ifndef PERIPH_CPU_H
#define PERIPH_CPU_H
#include "periph_cpu_common.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CPU_H */

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cpu/mips_pic32mz/include/vendor/p32mz2048efg100.h vendored
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409
cpu/mips_pic32mz/ldscripts/pic32mz2048_uhi.ld
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@ -1,409 +0,0 @@
/*
* A platform and target independent link script to produce UHI
* compliant binaries with varying levels of system initialization
* support.
*/
__entry = DEFINED(__reset_vector) ? 0xbfc00000 : _start;
ENTRY(__entry)
OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradbigmips", "elf32-tradlittlemips")
GROUP(-lc -luhi -lgcc -lhal)
SEARCH_DIR(.)
__DYNAMIC = 0;
STARTUP(crt0.o)
/* Force the exception handler to be registered */
EXTERN(__register_excpt_handler)
/* Force the exception handler to be included in the link */
EXTERN(__exception_entry)
/*
* Require verbose exceptions. This can be changed to pull in
* __exception_handle_quiet to reduce code size but be less
* informative
*/
EXTERN(__exception_handle_verbose)
/* Force the interrupt handlers to tbe included in the link */
EXTERN(__isr_vec)
/* Require the UHI getargs support */
EXTERN(__getargs)
/*
* Set the location of the top of the stack. A value of 0 means
* that it will be automatically placed at the highest address
* available as described by the __memory_* setttings
*/
PROVIDE (__stack = 0);
/* Size of the memory returned by _get_ram_range */
PROVIDE (__memory_size = 512K);
/* Base of the memory returned by _get_ram_range */
PROVIDE (__memory_base = 0x80000000);
/* Stride length for tlb software invalidate for tlbinvf
* (mipsXXr3+). Some MIPS implementations may layout the sets/ways
* differently in the index register. Either sets LSB or ways LSB.
*
* By setting this to 1 we presume that sets come first. The default boot
* code will decrement this value from the Number of TLB entries.
*/
PROVIDE (__tlb_stride_length = 1);
/* By default, XPA is not used even if available. To enable XPA,
* __enable_xpa should be 1.
*/
PROVIDE (__enable_xpa = 0);
/*
* 0 = Do not use exception handler present in boot for UHI
* 1 = Use exception handler present in boot for UHI if BEV is 0 at
* startup
* 2 = Always use exception handler present in boot for UHI
*/
PROVIDE (__use_excpt_boot = 0);
/*
* Include the code to be able to return to boot context. This is
* necessary if __use_excpt_boot != 0.
*/
EXTERN (__register_excpt_boot);
ASSERT (DEFINED(__register_excpt_boot) || __use_excpt_boot == 0,
"Registration for boot context is required for UHI chaining")
/* Control if subnormal floating-point values are flushed to zero in
hardware. This applies to both FPU and MSA operations. */
PROVIDE (__flush_to_zero = 1);
/* Set up the public symbols depending on whether the user has chosen
quiet or verbose exception handling above */
EXTERN (__exception_handle);
PROVIDE(__exception_handle = (DEFINED(__exception_handle_quiet)
? __exception_handle_quiet
: __exception_handle_verbose));
PROVIDE(_mips_handle_exception = __exception_handle);
/*
* Initalize some symbols to be zero so we can reference them in the
* crt0 without core dumping. These functions are all optional, but
* we do this so we can have our crt0 always use them if they exist.
* This is so BSPs work better when using the crt0 installed with gcc.
* We have to initalize them twice, so we multiple object file
* formats, as some prepend an underscore.
*/
PROVIDE (hardware_exit_hook = 0);
PROVIDE (hardware_hazard_hook = 0);
PROVIDE (hardware_init_hook = 0);
PROVIDE (software_init_hook = 0);
/* The default base address for application flash code is 0x9D001000 */
PROVIDE (__app_start = 0x9D001000) ;
/* Set default vector spacing to 32 bytes. */
PROVIDE (__isr_vec_space = 32);
/* Leave space for 9 vector entries by default. 8 entry points and one
fallback handler. */
PROVIDE (__isr_vec_count = 9);
/*
* The start of boot flash must be set if including boot code. By default
* the use of boot code will mean that application code is copied
* from flash to RAM at runtime before being executed.
*/
PROVIDE (__lower_boot_flash_start = DEFINED(__reset_vector) ? 0xbfc00000 : __app_start);
PROVIDE (__boot_flash1_start = 0xbfc40000);
PROVIDE (__boot_flash2_start = 0xbfc60000);
PROVIDE (__bev_override = 0x9fc00000);
PROVIDE (__flash_vector_start = 0x9D000000);
PROVIDE (__flash_app_start = 0x9D001000);
SECTIONS
{
/* Start of bootrom */
.lowerbootflashalias __bev_override : /* Runs uncached (from 0xBfc00000) until I$ is
initialized. */
AT (__lower_boot_flash_start)
{
__base = .;
*(.reset) /* Reset entry point. */
*(.boot) /* Boot code. */
. = ALIGN(8);
. = __base + 0xff40; /*Alternate Config bits (lower Alias)*/
KEEP(*(.adevcfg3_la))
KEEP(*(.adevcfg2_la))
KEEP(*(.adevcfg1_la))
KEEP(*(.adevcfg0_la))
. = __base + 0xff5c;
KEEP(*(.adevcp0_la))
. = __base + 0xff6c;
KEEP(*(.adevsign_la))
. = __base + 0xffc0; /*Config bits (lower Alias)*/
KEEP(*(.devcfg3_la))
KEEP(*(.devcfg2_la))
KEEP(*(.devcfg1_la))
KEEP(*(.devcfg0_la))
. = __base + 0xffdc;
KEEP(*(.devcp0_la))
. = __base + 0xffec;
KEEP(*(.devsign_la))
. = __base + 0xfff0;
KEEP(*(.seq_la))
} = 0xFFFFFFFF
/*
* We only add this block to keep the MPLAB programmer happy
* It seems to want the config regs values in the non aliased locations
*/
. = __base + 0x40000 + 0xff40;
.bootflash1 :
AT(__boot_flash1_start + 0xff40)
{
__altbase = .;
. = __altbase; /* Alternate Config Bits (boot flash 1) */
KEEP(*(.adevcfg3_b1))
KEEP(*(.adevcfg2_b1))
KEEP(*(.adevcfg1_b1))
KEEP(*(.adevcfg0_b1))
. = __altbase + 0x1c;
KEEP(*(.adevcp0_b1))
. = __altbase + 0x2c;
KEEP(*(.adevsign_b1))
. = __altbase + 0x80;
KEEP(*(.devcfg3_b1))
KEEP(*(.devcfg2_b1))
KEEP(*(.devcfg1_b1))
KEEP(*(.devcfg0_b1))
. = __altbase + 0x9c;
KEEP(*(.devcp0_b1))
. = __altbase + 0xAc;
KEEP(*(.devsign_b1))
. = __altbase + 0xB0;
KEEP(*(.seq_b1))
} = 0xFFFFFFFF
/*
* We only add this block to keep the MPLAB programmer happy
* It seems to want the config regs values in the non aliased locations
*/
. = __base + 0x60000 + 0xff40;
.bootflash2 :
AT(__boot_flash2_start + 0xff40)
{
__altbase = .;
. = __altbase; /* Alternate Config Bits (boot flash 1) */
KEEP(*(.adevcfg3_b2))
KEEP(*(.adevcfg2_b2))
KEEP(*(.adevcfg1_b2))
KEEP(*(.adevcfg0_b2))
. = __altbase + 0x1c;
KEEP(*(.adevcp0_b2))
. = __altbase + 0x2c;
KEEP(*(.adevsign_b2))
. = __altbase + 0x80;
KEEP(*(.devcfg3_b2))
KEEP(*(.devcfg2_b2))
KEEP(*(.devcfg1_b2))
KEEP(*(.devcfg0_b2))
. = __altbase + 0x9c;
KEEP(*(.devcp0_b2))
. = __altbase + 0xAc;
KEEP(*(.devsign_b2))
. = __altbase + 0xB0;
KEEP(*(.seq_b2))
} = 0xFFFFFFFF
/* Start of the application */
.exception_vector ALIGN(__flash_vector_start, 0x1000) :
AT (__flash_vector_start)
{
PROVIDE (__excpt_ebase = ABSOLUTE(.));
__base = .;
KEEP(* (.text.__exception_entry))
. = __base + 0x200;
KEEP(* (SORT(.text.__isr_vec*)))
/* Leave space for all the vector entries */
. = __base + 0x200 + (__isr_vec_space * __isr_vec_count);
ASSERT(__isr_vec_space == (DEFINED(__isr_vec_sw0)
? __isr_vec_sw1 - __isr_vec_sw0
: __isr_vec_space),
"Actual ISR vector spacing does not match __isr_vec_space");
ASSERT(__base + 0x200 == (DEFINED(__isr_vec_sw0)
? __isr_vec_sw0 & 0xfffffffe : __base + 0x200),
"__isr_vec_sw0 is not placed at EBASE + 0x200");
. = ALIGN(8);
} = 0
. = __flash_app_start;
.text : {
_ftext = . ;
PROVIDE (eprol = .);
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
*(.mips16.fn.*)
*(.mips16.call.*)
}
.init : {
KEEP (*(.init))
}
.fini : {
KEEP (*(.fini))
}
.rel.sdata : {
PROVIDE (__runtime_reloc_start = .);
*(.rel.sdata)
PROVIDE (__runtime_reloc_stop = .);
}
PROVIDE (etext = .);
_etext = .;
.eh_frame_hdr : { *(.eh_frame_hdr) }
.eh_frame : { KEEP (*(.eh_frame)) }
.gcc_except_table : { *(.gcc_except_table*) }
.jcr : { KEEP (*(.jcr)) }
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
}
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
}
. = .;
.MIPS.abiflags : {
__MIPS_abiflags_start = .;
*(.MIPS.abiflags)
__MIPS_abiflags_end = .;
}
.rodata : {
*(.rdata)
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
}
_rom_data_copy = .;
.data ALIGN(__memory_base + 0x1000, 16) :
AT (_rom_data_copy)
{
_fdata = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
_gp = . + 0x8000;
__global = _gp;
*(.lit8)
*(.lit4)
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
}
. = ALIGN(4);
PROVIDE (edata = .);
_edata = .;
_fbss = .;
.sbss : {
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
}
.bss : {
_bss_start = . ;
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
}
. = ALIGN(4);
PROVIDE (end = .);
_end = .;
/* Now place the data that is only needed within start.S and can be
overwritten by the heap. */
.startdata : {
*(.startdata)
}
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to
the beginning of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_ranges 0 : { *(.debug_ranges) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* Special sections generated by gcc */
/* Newer GNU linkers strip by default */
.mdebug.abi32 0 : { KEEP(*(.mdebug.abi32)) }
.mdebug.abiN32 0 : { KEEP(*(.mdebug.abiN32)) }
.mdebug.abi64 0 : { KEEP(*(.mdebug.abi64)) }
.mdebug.abiO64 0 : { KEEP(*(.mdebug.abiO64)) }
.mdebug.eabi32 0 : { KEEP(*(.mdebug.eabi32)) }
.mdebug.eabi64 0 : { KEEP(*(.mdebug.eabi64)) }
.gcc_compiled_long32 0 : { KEEP(*(.gcc_compiled_long32)) }
.gcc_compiled_long64 0 : { KEEP(*(.gcc_compiled_long64)) }
}

1
cpu/mips_pic32mz/p32mz2048efg100/Makefile
View File

@ -1 +0,0 @@
include $(RIOTBASE)/Makefile.base

6288
cpu/mips_pic32mz/p32mz2048efg100/p32mz2048efg100.S
View File

File diff suppressed because it is too large Load Diff

3
dist/tools/ci/print_toolchain_versions.sh vendored
View File

@ -124,7 +124,7 @@ printf "%s\n" "-----------------------------"
printf "%25s: %s\n" "native gcc" "$(get_cmd_version gcc)"
for p in \
arm-none-eabi \
avr mips-mti-elf \
avr \
msp430-elf \
riscv-none-elf \
riscv64-unknown-elf \
@ -141,7 +141,6 @@ printf "%s\n" "-----------------------"
# platform specific newlib version
for p in \
arm-none-eabi \
mips-mti-elf \
msp430-elf \
riscv-none-elf \
riscv64-unknown-elf \

18
dist/tools/doccheck/exclude_patterns vendored
View File

@ -1,9 +1,3 @@
boards/6lowpan\-clicker/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_CORECLOCK \(macro definition\) of file periph_conf\.h is not documented\.
boards/6lowpan\-clicker/include/periph_conf\.h:[0-9]+: warning: Member TIMER_0_CHANNELS \(macro definition\) of file periph_conf\.h is not documented\.
boards/6lowpan\-clicker/include/periph_conf\.h:[0-9]+: warning: Member TIMER_NUMOF \(macro definition\) of file periph_conf\.h is not documented\.
boards/6lowpan\-clicker/include/periph_conf\.h:[0-9]+: warning: Member UART_0_ISR \(macro definition\) of file periph_conf\.h is not documented\.
boards/6lowpan\-clicker/include/periph_conf\.h:[0-9]+: warning: Member UART_NUMOF \(macro definition\) of file periph_conf\.h is not documented\.
boards/6lowpan\-clicker/include/periph_conf\.h:[0-9]+: warning: Member uart_config\[\] \(variable\) of file periph_conf\.h is not documented\.
boards/acd52832/include/board\.h:[0-9]+: warning: Member LED_PORT \(macro definition\) of file board\.h is not documented\.
boards/acd52832/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_CORECLOCK \(macro definition\) of file periph_conf\.h is not documented\.
boards/acd52832/include/periph_conf\.h:[0-9]+: warning: Member I2C_NUMOF \(macro definition\) of file periph_conf\.h is not documented\.
@ -3213,12 +3207,6 @@ boards/phynode\-kw41z/include/periph_conf\.h:[0-9]+: warning: Member ADC_REF_SET
boards/phynode\-kw41z/include/periph_conf\.h:[0-9]+: warning: Member SPI_NUMOF \(macro definition\) of file periph_conf\.h is not documented\.
boards/phynode\-kw41z/include/periph_conf\.h:[0-9]+: warning: Member adc_config\[\] \(variable\) of file periph_conf\.h is not documented\.
boards/phynode\-kw41z/include/periph_conf\.h:[0-9]+: warning: Member spi_config\[\] \(variable\) of file periph_conf\.h is not documented\.
boards/pic32\-wifire/include/periph_conf\.h:[0-9]+: warning: Member CLOCK_CORECLOCK \(macro definition\) of file periph_conf\.h is not documented\.
boards/pic32\-wifire/include/periph_conf\.h:[0-9]+: warning: Member TIMER_0_CHANNELS \(macro definition\) of file periph_conf\.h is not documented\.
boards/pic32\-wifire/include/periph_conf\.h:[0-9]+: warning: Member TIMER_NUMOF \(macro definition\) of file periph_conf\.h is not documented\.
boards/pic32\-wifire/include/periph_conf\.h:[0-9]+: warning: Member UART_0_ISR \(macro definition\) of file periph_conf\.h is not documented\.
boards/pic32\-wifire/include/periph_conf\.h:[0-9]+: warning: Member UART_NUMOF \(macro definition\) of file periph_conf\.h is not documented\.
boards/pic32\-wifire/include/periph_conf\.h:[0-9]+: warning: Member uart_config\[\] \(variable\) of file periph_conf\.h is not documented\.
boards/pinetime/include/board\.h:[0-9]+: warning: Member BACKLIGHT_MASK \(macro definition\) of file board\.h is not documented\.
boards/pinetime/include/board\.h:[0-9]+: warning: Member BACKLIGHT_OFF \(macro definition\) of file board\.h is not documented\.
boards/pinetime/include/board\.h:[0-9]+: warning: Member BACKLIGHT_ON \(macro definition\) of file board\.h is not documented\.
@ -6007,11 +5995,7 @@ cpu/lpc23xx/include/periph_cpu\.h:[0-9]+: warning: Member PERIPH_SPI_NEEDS_TRANS
cpu/lpc23xx/include/periph_cpu\.h:[0-9]+: warning: Member PERIPH_SPI_NEEDS_TRANSFER_REG \(macro definition\) of file periph_cpu\.h is not documented\.
cpu/lpc23xx/include/periph_cpu\.h:[0-9]+: warning: Member PERIPH_SPI_NEEDS_TRANSFER_REGS \(macro definition\) of file periph_cpu\.h is not documented\.
cpu/lpc23xx/include/periph_cpu\.h:[0-9]+: warning: Member PM_NUM_MODES \(macro definition\) of file periph_cpu\.h is not documented\.
cpu/mips32r2_common/include/cpu\.h:[0-9]+: warning: Member BITARITHM_HAS_CLZ \(macro definition\) of group cpu_mips32r2_common is not documented\.
cpu/mips_pic32mx/include/cpu_conf\.h:[0-9]+: warning: Member THREAD_STACKSIZE_DEFAULT \(macro definition\) of group cpu_mips_pic32mx is not documented\.
cpu/mips_pic32mx/include/cpu_conf\.h:[0-9]+: warning: Member THREAD_STACKSIZE_IDLE \(macro definition\) of group cpu_mips_pic32mx is not documented\.
cpu/mips_pic32mz/include/cpu_conf\.h:[0-9]+: warning: Member THREAD_STACKSIZE_DEFAULT \(macro definition\) of group cpu_mips_pic32mz is not documented\.
cpu/mips_pic32mz/include/cpu_conf\.h:[0-9]+: warning: Member THREAD_STACKSIZE_IDLE \(macro definition\) of group cpu_mips_pic32mz is not documented\.
cpu/lpc23xx/include/periph_cpu\.h:[0-9]+: warning: end of file with unbalanced grouping commands
cpu/msp430_common/include/cpu_conf\.h:[0-9]+: warning: Member CONFIG_GNRC_PKTBUF_SIZE \(macro definition\) of file cpu_conf\.h is not documented\.
cpu/msp430_common/include/cpu_conf\.h:[0-9]+: warning: Member FLASHPAGE_SIZE \(macro definition\) of file cpu_conf\.h is not documented\.
cpu/msp430_common/include/cpu_conf\.h:[0-9]+: warning: Member FLASHPAGE_WRITE_BLOCK_ALIGNMENT \(macro definition\) of file cpu_conf\.h is not documented\.

12
dist/tools/packer/scripts/toolchains.sh vendored
View File

@ -8,18 +8,6 @@ cd /opt && wget -nv -O - "${ARM_GCC_ARCHIVE_URL}" | tar -jxf -
echo "export PATH=/opt/gcc-arm-none-eabi-9-2019-q4-major/bin:\$PATH" >> /home/${SSH_USERNAME}/.bashrc
# Install MIPS toolchain
MIPS_VERSION=2018.09-03
curl -L "https://codescape.mips.com/components/toolchain/${MIPS_VERSION}/Codescape.GNU.Tools.Package.${MIPS_VERSION}.for.MIPS.MTI.Bare.Metal.CentOS-6.x86_64.tar.gz" -o - \
| tar -C /opt -zx
rm -rf /opt/mips-mti-elf/*/share/{doc,info,man,locale}
cd /opt/mips-mti-elf/*/mips-mti-elf/bin
for f in *; do test -f "../../bin/mips-mti-elf-$f" && ln -f "../../bin/mips-mti-elf-$f" "$f"; done
cd -
echo "export MIPS_ELF_ROOT=/opt/mips-mti-elf/${MIPS_VERSION}" >> /home/${SSH_USERNAME}/.bashrc
echo "export PATH=\$MIPS_ELF_ROOT/bin:\$PATH" >> /home/${SSH_USERNAME}/.bashrc
# Install MSP430 toolchain
MSP430_URL=https://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/latest/exports
MSP430_VERSION=8.3.0.16_linux64

2
dist/tools/pic32prog/.gitignore vendored
View File

@ -1,2 +0,0 @@
pic32prog
bin/

26
dist/tools/pic32prog/Makefile vendored
View File

@ -1,26 +0,0 @@
PKG_NAME = pic32prog
PKG_URL = https://github.com/sergev/pic32prog
PKG_VERSION = b9f8db3b352804392b02b42475fc42874ac8bf04
PKG_LICENSE = GPL-2
# manually set some RIOT env vars, so this Makefile can be called stand-alone
RIOTBASE ?= $(CURDIR)/../../..
RIOTTOOLS ?= $(CURDIR)/..
PKG_SOURCE_DIR = $(CURDIR)/bin
PKG_BUILD_OUT_OF_SOURCE = 0
include $(RIOTBASE)/pkg/pkg.mk
# Building it requires some dependencies, on ubuntu:
#
# sudo apt-get install libusb-dev libusb-1.0-0-dev libudev-dev
all: $(CURDIR)/pic32prog
$(CURDIR)/pic32prog:
@echo "[INFO] compiling pic32prog from source now"
@env -i PATH=$(PATH) TERM=$(TERM) $(MAKE) -C $(PKG_BUILD_DIR)
@mv $(PKG_BUILD_DIR)/pic32prog $(CURDIR)/pic32prog
clean::
rm -f $(CURDIR)/pic32prog

166
dist/tools/pic32prog/doc.md vendored
View File

@ -1,166 +0,0 @@
Flashing on Linux using pickit-3
================================
This document describes how to enable flashing a pic32-wifire from Linux with a
PICkit3 using [pic32prog](https://github.com/sergev/pic32prog).
It will require flashing a specific firmware on the PICkit3.
As this can only be done from a Windows computer, that not many Linux users
have, the following steps explain how to setup a Windows VirtualBox virtual
machine and flash the PICkit3 from it.
Information come from this comment
https://github.com/RIOT-OS/RIOT/pull/6092#issuecomment-261987955
Steps
-----
### Setup your computer
The steps were run on Ubuntu 16.04
* Install VirtualBox
* Add yourself to the 'vboxusers' group
```
sudo usermod -a -G vboxusers your_username
```
* Reboot
### Setup Windows VM
You can download a free 90 days valid windows VirtualBox image from:
https://developer.microsoft.com/en-us/microsoft-edge/tools/vms/
This document was tested on a Windows 10 VirtualBox image
* Create a machine in VirtualBox in File-Import Appliance.
* Start the virtual machine and wait until you are on the windows desktop
* Install VirtualBox Guest-additions for USB support
* Doc: https://www.virtualbox.org/manual/ch04.html#additions-windows
* Shutdown the virtual machine
* Plug the PICkit3 flasher USB to your computer
* In the virtual machine settings, go to USB:
* Select "Enable USB Controller" with "USB 1.1"
* Click the small '+' sign on the right and add the Microchip devices.
* Doc: https://www.virtualbox.org/manual/ch03.html#idm1640
* Start the virtual machine
### Downloads
Download and extract:
* PICkit3-Programmer http://ww1.microchip.com/downloads/en/DeviceDoc/PICkit3%20Programmer%20Application%20v3.10.zip
The steps were adapted from the archive's README:
* Extract `PICkit3 Programmer Application Setup v3.10.zip`
* Run `setup.exe`
* Run PICkit3
* Tools/Download PICkit Operating System
* Select `c://Program Files/Microchip/PICkit3/PK3OSV020005.hex`
* Device will be flashed with the new firmware
* The GUI status should now say that the board is found
* Close the program (it crashes when closing it but it is ok)
* Turn off your VM
pic32prog
---------
Download and compile `pic32prog` flasher
https://github.com/sergev/pic32prog
Run the following command with PICkit3 connected in usb but without the
chipKIT-Wi-Fire board connected
```
$ pic32prog
Programmer for Microchip PIC32 microcontrollers, Version 2.0.221
Copyright: (C) 2011-2015 Serge Vakulenko
Adapter: PICkit3 Version 2.0.5
No device attached.
No target found.
```
You should see the `Adapter: PICkit3 Version 2.0.5` line.
### Troubleshooting
If you do not get the `Adapter: PICkit3 Version 2.0.5` line,
try running it with `sudo pic32prog`. If it works with `sudo` it is a
permission issue.
Add yourself to the `plugdev` group, add the following `udev` rule to
`/etc/udev/rules.d/26-microchip.rules` and reboot.
```
# Adapted from http://en.microstickplus.com/mplabx-on-linux
ATTR{idVendor}=="04d8", MODE="664", GROUP="plugdev"
```
Flashing
--------
* Connect the chipKIT-Wi-Fire to USB
* Connect the PICkit3 to JP1 ICSP holes
* https://docs.creatordev.io/wifire/guides/wifire-programming/
* The triangle `▶` goes into the port number 1 (a hole with a square around it)
Opposite side of the JP1 ICSP text.
Run pic32prog again
```
$ pic32prog
Programmer for Microchip PIC32 microcontrollers, Version 2.0.221
Copyright: (C) 2011-2015 Serge Vakulenko
Adapter: PICkit3 Version 2.0.5
Processor: MZ2048EFG100 (id 1720E053)
Flash memory: 2048 kbytes
Boot memory: 80 kbytes
Configuration:
DEVCFG0 = fff6fff7
3 Debugger disabled
4 JTAG enabled
8 Use PGC2/PGD2
3 Flash ECC disabled, unlocked
DEVCFG1 = 03743cb9
1 System PLL
8 Internal-external switch over enabled
0 Primary oscillator: External
4 CLKO output disabled
DEVCFG2 = fff9b11a
2 PLL divider: 1/3
1 PLL input frequency range: 5-10 MHz
31 PLL feedback divider: x50
1 PLL postscaler: 1/2
4 USB PLL input clock: 24 MHz
8 Enable USB PLL
DEVCFG3 = 86ffffff
2 Default Ethernet pins
USBID pin: controlled by port
```
Now try flashing the chipKIT-Wi-Fire with RIOT default example compiled for
pic32-wifire with `pic32prog path/to/firmware.hex`
```
$ pic32prog bin/pic32-wifire/default.hex
Programmer for Microchip PIC32 microcontrollers, Version 2.0.221
Copyright: (C) 2011-2015 Serge Vakulenko
Adapter: PICkit3 Version 2.0.5
Processor: MZ2048EFG100
Flash memory: 2048 kbytes
Boot memory: 80 kbytes
Data: 117020 bytes
Erase: done
Program flash: ########################### done
Program boot: #### done
Verify flash: ########################## done
Verify boot: ### done
Program rate: 6159 bytes per second
```

4
doc/doxygen/src/flashing.md
View File

@ -102,10 +102,6 @@ support multiple platforms are given in section
- `lpc2k_pgm`
### MIPS32r2
- `pic32prog`
### MSP430
- `mspdebug`

6
doc/doxygen/src/getting-started.md
View File

@ -132,12 +132,6 @@ For example, in Ubuntu the above tools can be installed with the following comma
board support
* Optional: GDB multiarch for debugging
### Architecture: MIPS
* GCC, binutils, and newlib for MIPS
* Alternatively: Install docker and export `BUILD_IN_DOCKER=1`
* Check board documentation for flashing and debugging
### Architecture: native
* On 64 bit systems: multilib versions for your host compilers, standard C library, and development

68
makefiles/arch/mips.inc.mk
View File

@ -1,68 +0,0 @@
# Target triple for the build.
TARGET_ARCH_MIPS ?= mips-mti-elf
TARGET_ARCH ?= $(TARGET_ARCH_MIPS)
ABI = 32
# Default values for the linker script symbols listed below are
# defined in the linker script.
# These are linker script symbols that are prefixed with '__"
priv_symbols = MEMORY_BASE MEMORY_SIZE STACK
priv_symbols += ENABLE_XPA
priv_symbols += FLUSH_TO_ZERO
priv_symbols += FLASH_START APP_START FLASH_APP_START
priv_symbols += ISR_VEC_SPACE ISR_VECTOR_COUNT
# A bit of makefile magic:
# foreach symbol in overridable ld-symbols :
# If symbol has a value, produce a linker argument for that symbol.
MIPS_HAL_LDFLAGS = $(foreach a,$(priv_symbols),$(if $($a),-Wl$(comma)--defsym$(comma)__$(call lowercase,$(a))=$($a)))
ifeq ($(ROMABLE),1)
MIPS_HAL_LDFLAGS += -T bootcode.ld
endif
# Otherwise we get an error about a missing declaration of strnlen in some parts.
ifeq (, $(filter -std=%, $(CFLAGS)))
CFLAGS += -std=gnu11
endif
CFLAGS_CPU = -EL -mabi=$(ABI)
CFLAGS_LINK = -ffunction-sections -fno-builtin -fshort-enums -fdata-sections
CFLAGS_DBG ?= -g3
CFLAGS_OPT ?= -Os
CFLAGS += $(CFLAGS_CPU) $(CFLAGS_LINK) $(CFLAGS_OPT) $(CFLAGS_DBG)
CFLAGS += -DCPU_MODEL_$(call uppercase_and_underscore,$(CPU_MODEL))
ifeq ($(USE_HARD_FLOAT),1)
CFLAGS += -mhard-float -DMIPS_HARD_FLOAT
else
#hard-float is the default so we must set soft-float
CFLAGS += -msoft-float
LINKFLAGS += -msoft-float
endif
ifeq ($(USE_DSP),1)
CFLAGS += -mdsp -DMIPS_DSP
endif
ifeq ($(TOOLCHAIN),llvm)
# The MIPS toolchain headers in assembly mode are not compatible with Clang
CCAS = $(PREFIX)gcc
CCASUWFLAGS += -target $(TARGET_ARCH)
endif
ASFLAGS += $(CFLAGS_CPU) $(CFLAGS_OPT) $(CFLAGS_DBG)
LINKFLAGS += $(MIPS_HAL_LDFLAGS)
LINKFLAGS += -L$(RIOTCPU)/$(CPU)/ldscripts
LINKFLAGS += $(CFLAGS_CPU) $(CFLAGS_DBG) $(CFLAGS_OPT)
LINKFLAGS += -Wl,--gc-sections
# XFA support
LINKFLAGS += -T$(RIOTCPU)/mips_pic32_common/ldscripts/xfa.ld
OPTIONAL_CFLAGS_BLACKLIST += -Wformat-overflow
OPTIONAL_CFLAGS_BLACKLIST += -Wformat-truncation
OPTIONAL_CFLAGS_BLACKLIST += -gz

2
makefiles/deprecated_boards.inc.mk
View File

@ -1,8 +1,6 @@
# Add deprecated modules here
# Keep this list ALPHABETICALLY SORTED!!!!
ifeq ($(MAKELEVEL),0)
DEPRECATED_BOARDS += 6lowpan-clicker
DEPRECATED_BOARDS += pic32-wifire
ifneq (,$(filter $(DEPRECATED_BOARDS),$(BOARD)))
$(shell $(COLOR_ECHO) "$(COLOR_RED)Deprecated board: $(COLOR_RESET)"\

2
makefiles/deprecated_cpus.inc.mk
View File

@ -1,8 +1,6 @@
# Add deprecated modules here
# Keep this list ALPHABETICALLY SORTED!!!!
ifeq ($(MAKELEVEL),0)
DEPRECATED_CPUS += mips_pic32mx
DEPRECATED_CPUS += mips_pic32mz
ifneq (,$(filter $(DEPRECATED_CPUS),$(CPU)))
$(shell $(COLOR_ECHO) "$(COLOR_RED)Deprecated cpu: $(COLOR_RESET)"\
"$(CPU)" 1>&2)

46
makefiles/tools/pic32prog.inc.mk
View File

@ -1,46 +0,0 @@
# pic32prog flasher
# =================
#
# https://github.com/sergev/pic32prog
#
# Allow flashing pic32 boards using:
# * Microchip PICkit2
# * Microchip PICkit3 with script firmware
#
#
# PICkit-3
# --------
#
# This requires changing the firmware to 'scripting mode'
# Should be done from a Windows computer/virtual machine as described here
#
# https://github.com/RIOT-OS/RIOT/blob/master/dist/tools/pic32prog/doc.md
#
#
# Udev rule
# ---------
#
# Add yourself to the `plugdev` group, add the following `udev` rule to
# `/etc/udev/rules.d/26-microchip.rules` and reboot.
#
# ```
# # Adapted from http://en.microstickplus.com/mplabx-on-linux
# ATTR{idVendor}=="04d8", MODE="664", GROUP="plugdev"
# ```
RIOT_PIC32PROG = $(RIOTTOOLS)/pic32prog/pic32prog
PIC32PROG ?= $(RIOT_PIC32PROG)
FLASHFILE ?= $(HEXFILE)
FLASHER ?= $(PIC32PROG)
FFLAGS ?= $(FLASHFILE)
# No reset command, but the board resets on terminal open
RESET ?=
RESET_FLAGS ?=
# Compile pic32prog if using the one provided in RIOT
ifeq ($(PIC32PROG),$(RIOT_PIC32PROG))
FLASHDEPS += $(RIOT_PIC32PROG)
endif

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