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https://github.com/RIOT-OS/RIOT.git
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drivers: adcxx1c, ads101x, ad7746: Change I2C macro to DEV
Due to a name clash the helper macro I2C should be change. Helper macros in other drivers are called DEV. Changing to DEV fixes the naming conflict.
This commit is contained in:
parent
4c9890b269
commit
3ed9060527
@ -30,7 +30,7 @@
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#include "xtimer.h"
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#include "xtimer.h"
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#define I2C (dev->params.i2c)
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#define DEV (dev->params.i2c)
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#define ADDR (dev->params.addr)
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#define ADDR (dev->params.addr)
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#define CONF_TEST_VALUE (1 << AD7746_CONFIGURATION_VTF1_BIT)
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#define CONF_TEST_VALUE (1 << AD7746_CONFIGURATION_VTF1_BIT)
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@ -122,13 +122,13 @@ int ad7746_init(ad7746_t *dev, const ad7746_params_t *params)
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assert(dev && params);
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assert(dev && params);
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dev->params = *params;
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dev->params = *params;
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i2c_acquire(I2C);
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i2c_acquire(DEV);
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uint8_t reg = 0;
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uint8_t reg = 0;
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/* Test communication write and read configuration register */
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/* Test communication write and read configuration register */
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status = i2c_write_reg(I2C, ADDR, AD7746_REG_CONFIGURATION, CONF_TEST_VALUE,
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status = i2c_write_reg(DEV, ADDR, AD7746_REG_CONFIGURATION, CONF_TEST_VALUE,
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0);
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0);
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status += i2c_read_reg(I2C, ADDR, AD7746_REG_CONFIGURATION, ®, 0);
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status += i2c_read_reg(DEV, ADDR, AD7746_REG_CONFIGURATION, ®, 0);
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if (status < 0 || reg != CONF_TEST_VALUE) {
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if (status < 0 || reg != CONF_TEST_VALUE) {
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DEBUG("[ad7746] init - error: unable to communicate with the device "
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DEBUG("[ad7746] init - error: unable to communicate with the device "
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@ -140,7 +140,7 @@ int ad7746_init(ad7746_t *dev, const ad7746_params_t *params)
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/* Enable capacitive channel and select input */
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/* Enable capacitive channel and select input */
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reg = (1 << AD7746_CAP_SETUP_CAPEN_BIT) |
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reg = (1 << AD7746_CAP_SETUP_CAPEN_BIT) |
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(dev->params.cap_input << AD7746_CAP_SETUP_CIN2_BIT);
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(dev->params.cap_input << AD7746_CAP_SETUP_CIN2_BIT);
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if (i2c_write_reg(I2C, ADDR, AD7746_REG_CAP_SETUP, reg, 0)) {
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if (i2c_write_reg(DEV, ADDR, AD7746_REG_CAP_SETUP, reg, 0)) {
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DEBUG("[ad7746] init - error: unable to enable capacitive channel\n");
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DEBUG("[ad7746] init - error: unable to enable capacitive channel\n");
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goto release;
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goto release;
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}
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}
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@ -150,7 +150,7 @@ int ad7746_init(ad7746_t *dev, const ad7746_params_t *params)
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reg = (1 << AD7746_VT_SETUP_VTEN_BIT) |
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reg = (1 << AD7746_VT_SETUP_VTEN_BIT) |
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(dev->params.vt_mode << AD7746_VT_SETUP_VTMD0_BIT) |
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(dev->params.vt_mode << AD7746_VT_SETUP_VTMD0_BIT) |
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(1 << AD7746_VT_SETUP_VTCHOP_BIT);
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(1 << AD7746_VT_SETUP_VTCHOP_BIT);
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if (i2c_write_reg(I2C, ADDR, AD7746_REG_VT_SETUP, reg, 0)) {
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if (i2c_write_reg(DEV, ADDR, AD7746_REG_VT_SETUP, reg, 0)) {
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DEBUG("[ad7746] init - error: unable to enable the v/t channel\n");
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DEBUG("[ad7746] init - error: unable to enable the v/t channel\n");
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goto release;
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goto release;
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}
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}
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@ -158,7 +158,7 @@ int ad7746_init(ad7746_t *dev, const ad7746_params_t *params)
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/* Set EXC sources */
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/* Set EXC sources */
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reg = (dev->params.exc_config << AD7746_EXC_SETUP_INV_EXCA_BIT);
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reg = (dev->params.exc_config << AD7746_EXC_SETUP_INV_EXCA_BIT);
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if (i2c_write_reg(I2C, ADDR, AD7746_REG_EXC_SETUP, reg, 0)) {
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if (i2c_write_reg(DEV, ADDR, AD7746_REG_EXC_SETUP, reg, 0)) {
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DEBUG("[ad7746] init - error: unable to set EXC outputs\n");
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DEBUG("[ad7746] init - error: unable to set EXC outputs\n");
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goto release;
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goto release;
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}
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}
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@ -167,7 +167,7 @@ int ad7746_init(ad7746_t *dev, const ad7746_params_t *params)
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if (dev->params.dac_a_cap) {
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if (dev->params.dac_a_cap) {
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assert(dev->params.dac_a_cap <= AD7746_DAC_MAX);
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assert(dev->params.dac_a_cap <= AD7746_DAC_MAX);
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reg = (1 << AD7746_DACAEN_BIT) | dev->params.dac_a_cap;
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reg = (1 << AD7746_DACAEN_BIT) | dev->params.dac_a_cap;
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if (i2c_write_reg(I2C, ADDR, AD7746_REG_CAP_DAC_A, reg, 0)) {
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if (i2c_write_reg(DEV, ADDR, AD7746_REG_CAP_DAC_A, reg, 0)) {
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DEBUG("[ad7746] init - error: unable to set DAC A\n");
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DEBUG("[ad7746] init - error: unable to set DAC A\n");
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goto release;
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goto release;
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}
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}
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@ -177,7 +177,7 @@ int ad7746_init(ad7746_t *dev, const ad7746_params_t *params)
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if (dev->params.dac_b_cap) {
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if (dev->params.dac_b_cap) {
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assert(dev->params.dac_b_cap <= AD7746_DAC_MAX);
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assert(dev->params.dac_b_cap <= AD7746_DAC_MAX);
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reg = (1 << AD7746_DACBEN_BIT) | dev->params.dac_b_cap;
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reg = (1 << AD7746_DACBEN_BIT) | dev->params.dac_b_cap;
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if (i2c_write_reg(I2C, ADDR, AD7746_REG_CAP_DAC_B, reg, 0)) {
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if (i2c_write_reg(DEV, ADDR, AD7746_REG_CAP_DAC_B, reg, 0)) {
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DEBUG("[ad7746] init - error: unable to set DAC B\n");
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DEBUG("[ad7746] init - error: unable to set DAC B\n");
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goto release;
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goto release;
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}
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}
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@ -187,7 +187,7 @@ int ad7746_init(ad7746_t *dev, const ad7746_params_t *params)
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reg = (1 << AD7746_CONFIGURATION_MD0_BIT) |
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reg = (1 << AD7746_CONFIGURATION_MD0_BIT) |
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(dev->params.cap_sample_rate << AD7746_CONFIGURATION_CAPF0_BIT) |
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(dev->params.cap_sample_rate << AD7746_CONFIGURATION_CAPF0_BIT) |
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(dev->params.vt_sample_rate << AD7746_CONFIGURATION_VTF0_BIT);
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(dev->params.vt_sample_rate << AD7746_CONFIGURATION_VTF0_BIT);
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if (i2c_write_reg(I2C, ADDR, AD7746_REG_CONFIGURATION, reg, 0)) {
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if (i2c_write_reg(DEV, ADDR, AD7746_REG_CONFIGURATION, reg, 0)) {
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DEBUG("[ad7746] init - error: unable to set mode and SR\n");
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DEBUG("[ad7746] init - error: unable to set mode and SR\n");
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goto release;
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goto release;
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}
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}
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@ -195,7 +195,7 @@ int ad7746_init(ad7746_t *dev, const ad7746_params_t *params)
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res = AD7746_OK;
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res = AD7746_OK;
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release:
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release:
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i2c_release(I2C);
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i2c_release(DEV);
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return res;
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return res;
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}
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}
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@ -205,8 +205,8 @@ int ad7746_set_vt_ch_mode(ad7746_t *dev, ad7746_vt_mode_t mode)
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int res = AD7746_NOI2C;
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int res = AD7746_NOI2C;
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assert(dev);
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assert(dev);
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i2c_acquire(I2C);
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i2c_acquire(DEV);
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if (i2c_read_reg(I2C, ADDR, AD7746_REG_VT_SETUP, ®, 0)) {
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if (i2c_read_reg(DEV, ADDR, AD7746_REG_VT_SETUP, ®, 0)) {
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goto release;
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goto release;
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}
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}
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@ -221,7 +221,7 @@ int ad7746_set_vt_ch_mode(ad7746_t *dev, ad7746_vt_mode_t mode)
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(mode << AD7746_VT_SETUP_VTMD0_BIT);
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(mode << AD7746_VT_SETUP_VTMD0_BIT);
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}
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}
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if (i2c_write_reg(I2C, ADDR, AD7746_REG_VT_SETUP, reg, 0)) {
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if (i2c_write_reg(DEV, ADDR, AD7746_REG_VT_SETUP, reg, 0)) {
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DEBUG("[ad7746] set_vt_ch - error: unable to set v/t channel mode\n");
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DEBUG("[ad7746] set_vt_ch - error: unable to set v/t channel mode\n");
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goto release;
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goto release;
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}
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}
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@ -230,7 +230,7 @@ int ad7746_set_vt_ch_mode(ad7746_t *dev, ad7746_vt_mode_t mode)
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dev->params.vt_mode = mode;
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dev->params.vt_mode = mode;
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release:
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release:
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i2c_release(I2C);
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i2c_release(DEV);
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return res;
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return res;
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}
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}
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@ -270,9 +270,9 @@ int ad7746_set_cap_ch_input(const ad7746_t *dev, ad7746_cap_input_t input)
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int res = AD7746_NOI2C;
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int res = AD7746_NOI2C;
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assert(dev);
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assert(dev);
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i2c_acquire(I2C);
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i2c_acquire(DEV);
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if (i2c_read_reg(I2C, ADDR, AD7746_REG_CAP_SETUP, ®, 0)) {
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if (i2c_read_reg(DEV, ADDR, AD7746_REG_CAP_SETUP, ®, 0)) {
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goto release;
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goto release;
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}
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}
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@ -283,14 +283,14 @@ int ad7746_set_cap_ch_input(const ad7746_t *dev, ad7746_cap_input_t input)
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reg &= ~(1 << AD7746_CAP_SETUP_CIN2_BIT);
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reg &= ~(1 << AD7746_CAP_SETUP_CIN2_BIT);
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}
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}
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if (i2c_write_reg(I2C, ADDR, AD7746_REG_CAP_SETUP, reg, 0)) {
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if (i2c_write_reg(DEV, ADDR, AD7746_REG_CAP_SETUP, reg, 0)) {
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goto release;
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goto release;
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}
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}
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res = AD7746_OK;
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res = AD7746_OK;
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release:
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release:
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i2c_release(I2C);
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i2c_release(DEV);
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return res;
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return res;
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}
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}
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@ -300,23 +300,23 @@ int ad7746_set_cap_sr(const ad7746_t *dev, ad7746_cap_sample_rate_t sr)
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int res = AD7746_NOI2C;
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int res = AD7746_NOI2C;
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assert(dev);
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assert(dev);
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i2c_acquire(I2C);
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i2c_acquire(DEV);
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if (i2c_read_reg(I2C, ADDR, AD7746_REG_CONFIGURATION, ®, 0)) {
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if (i2c_read_reg(DEV, ADDR, AD7746_REG_CONFIGURATION, ®, 0)) {
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goto release;
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goto release;
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}
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}
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reg &= ~(7 << AD7746_CONFIGURATION_CAPF0_BIT);
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reg &= ~(7 << AD7746_CONFIGURATION_CAPF0_BIT);
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reg |= (sr << AD7746_CONFIGURATION_CAPF0_BIT);
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reg |= (sr << AD7746_CONFIGURATION_CAPF0_BIT);
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if (i2c_write_reg(I2C, ADDR, AD7746_REG_CONFIGURATION, reg, 0)) {
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if (i2c_write_reg(DEV, ADDR, AD7746_REG_CONFIGURATION, reg, 0)) {
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goto release;
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goto release;
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}
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}
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res = AD7746_OK;
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res = AD7746_OK;
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release:
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release:
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i2c_release(I2C);
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i2c_release(DEV);
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return res;
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return res;
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}
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}
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@ -326,23 +326,23 @@ int ad7746_set_vt_sr(const ad7746_t *dev, ad7746_vt_sample_rate_t sr)
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int res = AD7746_NOI2C;
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int res = AD7746_NOI2C;
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assert(dev);
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assert(dev);
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i2c_acquire(I2C);
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i2c_acquire(DEV);
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if (i2c_read_reg(I2C, ADDR, AD7746_REG_CONFIGURATION, ®, 0)) {
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if (i2c_read_reg(DEV, ADDR, AD7746_REG_CONFIGURATION, ®, 0)) {
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goto release;
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goto release;
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}
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}
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reg &= ~(3 << AD7746_CONFIGURATION_VTF0_BIT);
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reg &= ~(3 << AD7746_CONFIGURATION_VTF0_BIT);
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reg |= (sr << AD7746_CONFIGURATION_VTF0_BIT);
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reg |= (sr << AD7746_CONFIGURATION_VTF0_BIT);
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if (i2c_write_reg(I2C, ADDR, AD7746_REG_CONFIGURATION, reg, 0)) {
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if (i2c_write_reg(DEV, ADDR, AD7746_REG_CONFIGURATION, reg, 0)) {
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goto release;
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goto release;
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}
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}
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res = AD7746_OK;
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res = AD7746_OK;
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release:
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release:
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i2c_release(I2C);
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i2c_release(DEV);
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return res;
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return res;
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}
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}
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@ -406,9 +406,9 @@ static int _read_raw_ch(const ad7746_t *dev, uint8_t ch, uint32_t *raw)
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assert(dev);
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assert(dev);
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assert((ch == AD7746_READ_CAP_CH) || (ch == AD7746_READ_VT_CH));
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assert((ch == AD7746_READ_CAP_CH) || (ch == AD7746_READ_VT_CH));
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i2c_acquire(I2C);
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i2c_acquire(DEV);
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if (i2c_read_reg(I2C, ADDR, AD7746_REG_STATUS, buf, 0)) {
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if (i2c_read_reg(DEV, ADDR, AD7746_REG_STATUS, buf, 0)) {
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goto release;
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goto release;
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}
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}
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@ -418,7 +418,7 @@ static int _read_raw_ch(const ad7746_t *dev, uint8_t ch, uint32_t *raw)
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goto release;
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goto release;
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}
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}
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if (i2c_read_regs(I2C, ADDR, reg, buf, 3, 0)) {
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if (i2c_read_regs(DEV, ADDR, reg, buf, 3, 0)) {
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goto release;
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goto release;
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}
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}
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@ -427,7 +427,7 @@ static int _read_raw_ch(const ad7746_t *dev, uint8_t ch, uint32_t *raw)
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res = AD7746_OK;
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res = AD7746_OK;
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release:
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release:
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i2c_release(I2C);
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i2c_release(DEV);
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return res;
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return res;
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}
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}
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@ -27,7 +27,7 @@
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#define ENABLE_DEBUG (0)
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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#include "debug.h"
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#define I2C (dev->params.i2c)
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#define DEV (dev->params.i2c)
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#define ADDR (dev->params.addr)
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#define ADDR (dev->params.addr)
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/* Configuration register test value
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/* Configuration register test value
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@ -42,23 +42,23 @@ int adcxx1c_init(adcxx1c_t *dev, const adcxx1c_params_t *params)
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dev->params = *params;
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dev->params = *params;
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dev->cb = NULL;
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dev->cb = NULL;
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i2c_acquire(I2C);
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i2c_acquire(DEV);
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uint8_t reg = 0;
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uint8_t reg = 0;
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/* Test communication write and read configuration register */
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/* Test communication write and read configuration register */
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status = i2c_write_reg(I2C, ADDR, ADCXX1C_CONF_ADDR, CONF_TEST_VALUE, 0);
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status = i2c_write_reg(DEV, ADDR, ADCXX1C_CONF_ADDR, CONF_TEST_VALUE, 0);
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status += i2c_read_reg(I2C, ADDR, ADCXX1C_CONF_ADDR, ®, 0);
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status += i2c_read_reg(DEV, ADDR, ADCXX1C_CONF_ADDR, ®, 0);
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if (status < 0 || reg != CONF_TEST_VALUE) {
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if (status < 0 || reg != CONF_TEST_VALUE) {
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i2c_release(I2C);
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i2c_release(DEV);
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DEBUG("[adcxx1c] init - error: unable to communicate with the device "
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DEBUG("[adcxx1c] init - error: unable to communicate with the device "
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"(reg=%x)\n", reg);
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"(reg=%x)\n", reg);
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return ADCXX1C_NODEV;
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return ADCXX1C_NODEV;
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}
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}
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reg = dev->params.cycle << 5;
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reg = dev->params.cycle << 5;
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status = i2c_write_reg(I2C, ADDR, ADCXX1C_CONF_ADDR, reg, 0);
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status = i2c_write_reg(DEV, ADDR, ADCXX1C_CONF_ADDR, reg, 0);
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i2c_release(I2C);
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i2c_release(DEV);
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if (status < 0) {
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if (status < 0) {
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DEBUG("[adcxx1c] init - error: unable to communicate with the device "
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DEBUG("[adcxx1c] init - error: unable to communicate with the device "
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"(err=%x)\n", status);
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"(err=%x)\n", status);
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@ -75,9 +75,9 @@ int adcxx1c_read_raw(const adcxx1c_t *dev, int16_t *raw)
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uint8_t buf[2];
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uint8_t buf[2];
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int status;
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int status;
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|
||||||
i2c_acquire(I2C);
|
i2c_acquire(DEV);
|
||||||
status = i2c_read_regs(I2C, ADDR, ADCXX1C_CONV_RES_ADDR, buf, 2, 0);
|
status = i2c_read_regs(DEV, ADDR, ADCXX1C_CONV_RES_ADDR, buf, 2, 0);
|
||||||
i2c_release(I2C);
|
i2c_release(DEV);
|
||||||
if (status < 0) {
|
if (status < 0) {
|
||||||
return ADCXX1C_NOI2C;
|
return ADCXX1C_NOI2C;
|
||||||
}
|
}
|
||||||
@ -101,12 +101,12 @@ int adcxx1c_enable_alert(adcxx1c_t *dev, adcxx1c_cb_t cb, void *arg)
|
|||||||
uint8_t reg;
|
uint8_t reg;
|
||||||
int status;
|
int status;
|
||||||
|
|
||||||
i2c_acquire(I2C);
|
i2c_acquire(DEV);
|
||||||
i2c_read_reg(I2C, ADDR, ADCXX1C_CONF_ADDR, ®, 0);
|
i2c_read_reg(DEV, ADDR, ADCXX1C_CONF_ADDR, ®, 0);
|
||||||
reg |= (dev->params.alert_pin != GPIO_UNDEF ? ADCXX1C_CONF_ALERT_PIN_EN : 0)
|
reg |= (dev->params.alert_pin != GPIO_UNDEF ? ADCXX1C_CONF_ALERT_PIN_EN : 0)
|
||||||
| ADCXX1C_CONF_ALERT_FLAG_EN;
|
| ADCXX1C_CONF_ALERT_FLAG_EN;
|
||||||
status = i2c_write_reg(I2C, ADDR, ADCXX1C_CONF_ADDR, reg, 0);
|
status = i2c_write_reg(DEV, ADDR, ADCXX1C_CONF_ADDR, reg, 0);
|
||||||
i2c_release(I2C);
|
i2c_release(DEV);
|
||||||
if (status < 0) {
|
if (status < 0) {
|
||||||
DEBUG("[adcxx1c] enable_alert - error: unable to communicate with the "
|
DEBUG("[adcxx1c] enable_alert - error: unable to communicate with the "
|
||||||
"device (err=%d)\n", status);
|
"device (err=%d)\n", status);
|
||||||
@ -129,14 +129,14 @@ int adcxx1c_set_alert_parameters(const adcxx1c_t *dev, int16_t low_limit,
|
|||||||
uint8_t buf[2];
|
uint8_t buf[2];
|
||||||
int status;
|
int status;
|
||||||
|
|
||||||
i2c_acquire(I2C);
|
i2c_acquire(DEV);
|
||||||
|
|
||||||
low_limit <<= (12 - dev->params.bits);
|
low_limit <<= (12 - dev->params.bits);
|
||||||
buf[0] = low_limit >> 8;
|
buf[0] = low_limit >> 8;
|
||||||
buf[1] = low_limit & 0xFF;
|
buf[1] = low_limit & 0xFF;
|
||||||
status = i2c_write_regs(I2C, ADDR, ADCXX1C_LOW_LIMIT_ADDR, buf, 2, 0);
|
status = i2c_write_regs(DEV, ADDR, ADCXX1C_LOW_LIMIT_ADDR, buf, 2, 0);
|
||||||
if (status < 0) {
|
if (status < 0) {
|
||||||
i2c_release(I2C);
|
i2c_release(DEV);
|
||||||
DEBUG("[adcxx1c] set_alert (low limit) - error: unable to communicate "
|
DEBUG("[adcxx1c] set_alert (low limit) - error: unable to communicate "
|
||||||
"with the device (err=%d)\n", status);
|
"with the device (err=%d)\n", status);
|
||||||
return ADCXX1C_NOI2C;
|
return ADCXX1C_NOI2C;
|
||||||
@ -145,9 +145,9 @@ int adcxx1c_set_alert_parameters(const adcxx1c_t *dev, int16_t low_limit,
|
|||||||
high_limit <<= (12 - dev->params.bits);
|
high_limit <<= (12 - dev->params.bits);
|
||||||
buf[0] = high_limit >> 8;
|
buf[0] = high_limit >> 8;
|
||||||
buf[1] = high_limit & 0xFF;
|
buf[1] = high_limit & 0xFF;
|
||||||
status = i2c_write_regs(I2C, ADDR, ADCXX1C_HIGH_LIMIT_ADDR, buf, 2, 0);
|
status = i2c_write_regs(DEV, ADDR, ADCXX1C_HIGH_LIMIT_ADDR, buf, 2, 0);
|
||||||
if (status < 0) {
|
if (status < 0) {
|
||||||
i2c_release(I2C);
|
i2c_release(DEV);
|
||||||
DEBUG("[adcxx1c] set_alert (high limit) - error: unable to communicate "
|
DEBUG("[adcxx1c] set_alert (high limit) - error: unable to communicate "
|
||||||
"with the device (err=%d)\n", status);
|
"with the device (err=%d)\n", status);
|
||||||
return ADCXX1C_NOI2C;
|
return ADCXX1C_NOI2C;
|
||||||
@ -156,15 +156,15 @@ int adcxx1c_set_alert_parameters(const adcxx1c_t *dev, int16_t low_limit,
|
|||||||
hysteresis <<= (12 - dev->params.bits);
|
hysteresis <<= (12 - dev->params.bits);
|
||||||
buf[0] = hysteresis >> 8;
|
buf[0] = hysteresis >> 8;
|
||||||
buf[1] = hysteresis & 0xFF;
|
buf[1] = hysteresis & 0xFF;
|
||||||
status = i2c_write_regs(I2C, ADDR, ADCXX1C_HYSTERESIS_ADDR, buf, 2, 0);
|
status = i2c_write_regs(DEV, ADDR, ADCXX1C_HYSTERESIS_ADDR, buf, 2, 0);
|
||||||
if (status < 0) {
|
if (status < 0) {
|
||||||
i2c_release(I2C);
|
i2c_release(DEV);
|
||||||
DEBUG("[adcxx1c] set_alert (hysteresis) - error: unable to communicate "
|
DEBUG("[adcxx1c] set_alert (hysteresis) - error: unable to communicate "
|
||||||
"with the device (err=%d)\n", status);
|
"with the device (err=%d)\n", status);
|
||||||
return ADCXX1C_NOI2C;
|
return ADCXX1C_NOI2C;
|
||||||
}
|
}
|
||||||
|
|
||||||
i2c_release(I2C);
|
i2c_release(DEV);
|
||||||
|
|
||||||
return ADCXX1C_OK;
|
return ADCXX1C_OK;
|
||||||
}
|
}
|
||||||
|
@ -35,7 +35,7 @@
|
|||||||
#define ADS101X_READ_DELAY (8 * US_PER_MS) /* Compatible with 128SPS */
|
#define ADS101X_READ_DELAY (8 * US_PER_MS) /* Compatible with 128SPS */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define I2C (dev->params.i2c)
|
#define DEV (dev->params.i2c)
|
||||||
#define ADDR (dev->params.addr)
|
#define ADDR (dev->params.addr)
|
||||||
|
|
||||||
static int _ads101x_init_test(i2c_t i2c, uint8_t addr);
|
static int _ads101x_init_test(i2c_t i2c, uint8_t addr);
|
||||||
@ -46,7 +46,7 @@ int ads101x_init(ads101x_t *dev, const ads101x_params_t *params)
|
|||||||
|
|
||||||
dev->params = *params;
|
dev->params = *params;
|
||||||
|
|
||||||
return _ads101x_init_test(I2C, ADDR);
|
return _ads101x_init_test(DEV, ADDR);
|
||||||
}
|
}
|
||||||
|
|
||||||
int ads101x_alert_init(ads101x_alert_t *dev,
|
int ads101x_alert_init(ads101x_alert_t *dev,
|
||||||
@ -62,7 +62,7 @@ int ads101x_alert_init(ads101x_alert_t *dev,
|
|||||||
ads101x_set_alert_parameters(dev, dev->params.low_limit,
|
ads101x_set_alert_parameters(dev, dev->params.low_limit,
|
||||||
dev->params.high_limit);
|
dev->params.high_limit);
|
||||||
|
|
||||||
return _ads101x_init_test(I2C, ADDR);
|
return _ads101x_init_test(DEV, ADDR);
|
||||||
}
|
}
|
||||||
|
|
||||||
static int _ads101x_init_test(i2c_t i2c, uint8_t addr)
|
static int _ads101x_init_test(i2c_t i2c, uint8_t addr)
|
||||||
@ -106,9 +106,9 @@ int ads101x_set_mux_gain(const ads101x_t *dev, uint8_t mux_gain)
|
|||||||
{
|
{
|
||||||
uint8_t regs[2];
|
uint8_t regs[2];
|
||||||
|
|
||||||
i2c_acquire(I2C);
|
i2c_acquire(DEV);
|
||||||
|
|
||||||
i2c_read_regs(I2C, ADDR, ADS101X_CONF_ADDR, ®s, 2, 0x0);
|
i2c_read_regs(DEV, ADDR, ADS101X_CONF_ADDR, ®s, 2, 0x0);
|
||||||
|
|
||||||
/* Zero mux and gain */
|
/* Zero mux and gain */
|
||||||
regs[0] &= ~ADS101X_MUX_MASK;
|
regs[0] &= ~ADS101X_MUX_MASK;
|
||||||
@ -117,9 +117,9 @@ int ads101x_set_mux_gain(const ads101x_t *dev, uint8_t mux_gain)
|
|||||||
/* Write mux and gain */
|
/* Write mux and gain */
|
||||||
regs[0] |= mux_gain;
|
regs[0] |= mux_gain;
|
||||||
|
|
||||||
i2c_write_regs(I2C, ADDR, ADS101X_CONF_ADDR, ®s, 2, 0x0);
|
i2c_write_regs(DEV, ADDR, ADS101X_CONF_ADDR, ®s, 2, 0x0);
|
||||||
|
|
||||||
i2c_release(I2C);
|
i2c_release(DEV);
|
||||||
|
|
||||||
return ADS101X_OK;
|
return ADS101X_OK;
|
||||||
}
|
}
|
||||||
@ -128,25 +128,25 @@ int ads101x_read_raw(const ads101x_t *dev, int16_t *raw)
|
|||||||
{
|
{
|
||||||
uint8_t regs[2];
|
uint8_t regs[2];
|
||||||
|
|
||||||
i2c_acquire(I2C);
|
i2c_acquire(DEV);
|
||||||
|
|
||||||
/* Read control register */
|
/* Read control register */
|
||||||
i2c_read_regs(I2C, ADDR, ADS101X_CONF_ADDR, ®s, 2, 0x0);
|
i2c_read_regs(DEV, ADDR, ADS101X_CONF_ADDR, ®s, 2, 0x0);
|
||||||
|
|
||||||
/* Tell the ADC to aquire a single-shot sample */
|
/* Tell the ADC to aquire a single-shot sample */
|
||||||
regs[0] |= ADS101X_CONF_OS_CONV;
|
regs[0] |= ADS101X_CONF_OS_CONV;
|
||||||
i2c_write_regs(I2C, ADDR, ADS101X_CONF_ADDR, ®s, 2, 0x0);
|
i2c_write_regs(DEV, ADDR, ADS101X_CONF_ADDR, ®s, 2, 0x0);
|
||||||
|
|
||||||
/* Wait for the sample to be aquired */
|
/* Wait for the sample to be aquired */
|
||||||
xtimer_usleep(ADS101X_READ_DELAY);
|
xtimer_usleep(ADS101X_READ_DELAY);
|
||||||
|
|
||||||
/* Read the sample */
|
/* Read the sample */
|
||||||
if (i2c_read_regs(I2C, ADDR, ADS101X_CONV_RES_ADDR, ®s, 2, 0x0) < 0) {
|
if (i2c_read_regs(DEV, ADDR, ADS101X_CONV_RES_ADDR, ®s, 2, 0x0) < 0) {
|
||||||
i2c_release(I2C);
|
i2c_release(DEV);
|
||||||
return ADS101X_NODATA;
|
return ADS101X_NODATA;
|
||||||
}
|
}
|
||||||
|
|
||||||
i2c_release(I2C);
|
i2c_release(DEV);
|
||||||
|
|
||||||
/* If all okay, change raw value */
|
/* If all okay, change raw value */
|
||||||
*raw = (int16_t)(regs[0] << 8) | (int16_t)(regs[1]);
|
*raw = (int16_t)(regs[0] << 8) | (int16_t)(regs[1]);
|
||||||
@ -164,14 +164,14 @@ int ads101x_enable_alert(ads101x_alert_t *dev,
|
|||||||
}
|
}
|
||||||
|
|
||||||
/* Read control register */
|
/* Read control register */
|
||||||
i2c_acquire(I2C);
|
i2c_acquire(DEV);
|
||||||
i2c_read_regs(I2C, ADDR, ADS101X_CONF_ADDR, ®s, 2, 0x0);
|
i2c_read_regs(DEV, ADDR, ADS101X_CONF_ADDR, ®s, 2, 0x0);
|
||||||
|
|
||||||
/* Enable alert comparator */
|
/* Enable alert comparator */
|
||||||
regs[1] &= ~ADS101X_CONF_COMP_DIS;
|
regs[1] &= ~ADS101X_CONF_COMP_DIS;
|
||||||
i2c_write_regs(I2C, ADDR, ADS101X_CONF_ADDR, ®s, 2, 0x0);
|
i2c_write_regs(DEV, ADDR, ADS101X_CONF_ADDR, ®s, 2, 0x0);
|
||||||
|
|
||||||
i2c_release(I2C);
|
i2c_release(DEV);
|
||||||
|
|
||||||
/* Enable interrupt */
|
/* Enable interrupt */
|
||||||
dev->arg = arg;
|
dev->arg = arg;
|
||||||
@ -186,20 +186,20 @@ int ads101x_set_alert_parameters(const ads101x_alert_t *dev,
|
|||||||
{
|
{
|
||||||
uint8_t regs[2];
|
uint8_t regs[2];
|
||||||
|
|
||||||
i2c_acquire(I2C);
|
i2c_acquire(DEV);
|
||||||
|
|
||||||
/* Set up low_limit */
|
/* Set up low_limit */
|
||||||
regs[0] = (uint8_t)(low_limit >> 8);
|
regs[0] = (uint8_t)(low_limit >> 8);
|
||||||
regs[1] = (uint8_t)low_limit;
|
regs[1] = (uint8_t)low_limit;
|
||||||
i2c_write_regs(I2C, ADDR, ADS101X_LOW_LIMIT_ADDR, ®s, 2, 0x0);
|
i2c_write_regs(DEV, ADDR, ADS101X_LOW_LIMIT_ADDR, ®s, 2, 0x0);
|
||||||
|
|
||||||
/* Set up high_limit */
|
/* Set up high_limit */
|
||||||
regs[0] = (uint8_t)(high_limit >> 8);
|
regs[0] = (uint8_t)(high_limit >> 8);
|
||||||
regs[1] = (uint8_t)high_limit;
|
regs[1] = (uint8_t)high_limit;
|
||||||
i2c_write_regs(I2C, ADDR, ADS101X_HIGH_LIMIT_ADDR, ®s, 2, 0x0);
|
i2c_write_regs(DEV, ADDR, ADS101X_HIGH_LIMIT_ADDR, ®s, 2, 0x0);
|
||||||
|
|
||||||
/* Read control register */
|
/* Read control register */
|
||||||
i2c_read_regs(I2C, ADDR, ADS101X_CONF_ADDR, ®s, 2, 0x0);
|
i2c_read_regs(DEV, ADDR, ADS101X_CONF_ADDR, ®s, 2, 0x0);
|
||||||
|
|
||||||
/* Set up window mode */
|
/* Set up window mode */
|
||||||
if (low_limit != 0) {
|
if (low_limit != 0) {
|
||||||
@ -210,9 +210,9 @@ int ads101x_set_alert_parameters(const ads101x_alert_t *dev,
|
|||||||
/* Disable window mode */
|
/* Disable window mode */
|
||||||
regs[1] &= ~ADS101X_CONF_COMP_MODE_WIND;
|
regs[1] &= ~ADS101X_CONF_COMP_MODE_WIND;
|
||||||
}
|
}
|
||||||
i2c_write_regs(I2C, ADDR, ADS101X_CONF_ADDR, ®s, 2, 0x0);
|
i2c_write_regs(DEV, ADDR, ADS101X_CONF_ADDR, ®s, 2, 0x0);
|
||||||
|
|
||||||
i2c_release(I2C);
|
i2c_release(DEV);
|
||||||
|
|
||||||
return ADS101X_OK;
|
return ADS101X_OK;
|
||||||
}
|
}
|
||||||
|
Loading…
Reference in New Issue
Block a user