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drivers: adcxx1c, ads101x, ad7746: Change I2C macro to DEV

Due to a name clash the helper macro I2C should be change.
Helper macros in other drivers are called DEV.
Changing to DEV fixes the naming conflict.
This commit is contained in:
MrKevinWeiss 2019-04-08 13:30:48 +02:00
parent 4c9890b269
commit 3ed9060527
3 changed files with 76 additions and 76 deletions

View File

@ -30,7 +30,7 @@
#include "xtimer.h" #include "xtimer.h"
#define I2C (dev->params.i2c) #define DEV (dev->params.i2c)
#define ADDR (dev->params.addr) #define ADDR (dev->params.addr)
#define CONF_TEST_VALUE (1 << AD7746_CONFIGURATION_VTF1_BIT) #define CONF_TEST_VALUE (1 << AD7746_CONFIGURATION_VTF1_BIT)
@ -122,13 +122,13 @@ int ad7746_init(ad7746_t *dev, const ad7746_params_t *params)
assert(dev && params); assert(dev && params);
dev->params = *params; dev->params = *params;
i2c_acquire(I2C); i2c_acquire(DEV);
uint8_t reg = 0; uint8_t reg = 0;
/* Test communication write and read configuration register */ /* Test communication write and read configuration register */
status = i2c_write_reg(I2C, ADDR, AD7746_REG_CONFIGURATION, CONF_TEST_VALUE, status = i2c_write_reg(DEV, ADDR, AD7746_REG_CONFIGURATION, CONF_TEST_VALUE,
0); 0);
status += i2c_read_reg(I2C, ADDR, AD7746_REG_CONFIGURATION, &reg, 0); status += i2c_read_reg(DEV, ADDR, AD7746_REG_CONFIGURATION, &reg, 0);
if (status < 0 || reg != CONF_TEST_VALUE) { if (status < 0 || reg != CONF_TEST_VALUE) {
DEBUG("[ad7746] init - error: unable to communicate with the device " DEBUG("[ad7746] init - error: unable to communicate with the device "
@ -140,7 +140,7 @@ int ad7746_init(ad7746_t *dev, const ad7746_params_t *params)
/* Enable capacitive channel and select input */ /* Enable capacitive channel and select input */
reg = (1 << AD7746_CAP_SETUP_CAPEN_BIT) | reg = (1 << AD7746_CAP_SETUP_CAPEN_BIT) |
(dev->params.cap_input << AD7746_CAP_SETUP_CIN2_BIT); (dev->params.cap_input << AD7746_CAP_SETUP_CIN2_BIT);
if (i2c_write_reg(I2C, ADDR, AD7746_REG_CAP_SETUP, reg, 0)) { if (i2c_write_reg(DEV, ADDR, AD7746_REG_CAP_SETUP, reg, 0)) {
DEBUG("[ad7746] init - error: unable to enable capacitive channel\n"); DEBUG("[ad7746] init - error: unable to enable capacitive channel\n");
goto release; goto release;
} }
@ -150,7 +150,7 @@ int ad7746_init(ad7746_t *dev, const ad7746_params_t *params)
reg = (1 << AD7746_VT_SETUP_VTEN_BIT) | reg = (1 << AD7746_VT_SETUP_VTEN_BIT) |
(dev->params.vt_mode << AD7746_VT_SETUP_VTMD0_BIT) | (dev->params.vt_mode << AD7746_VT_SETUP_VTMD0_BIT) |
(1 << AD7746_VT_SETUP_VTCHOP_BIT); (1 << AD7746_VT_SETUP_VTCHOP_BIT);
if (i2c_write_reg(I2C, ADDR, AD7746_REG_VT_SETUP, reg, 0)) { if (i2c_write_reg(DEV, ADDR, AD7746_REG_VT_SETUP, reg, 0)) {
DEBUG("[ad7746] init - error: unable to enable the v/t channel\n"); DEBUG("[ad7746] init - error: unable to enable the v/t channel\n");
goto release; goto release;
} }
@ -158,7 +158,7 @@ int ad7746_init(ad7746_t *dev, const ad7746_params_t *params)
/* Set EXC sources */ /* Set EXC sources */
reg = (dev->params.exc_config << AD7746_EXC_SETUP_INV_EXCA_BIT); reg = (dev->params.exc_config << AD7746_EXC_SETUP_INV_EXCA_BIT);
if (i2c_write_reg(I2C, ADDR, AD7746_REG_EXC_SETUP, reg, 0)) { if (i2c_write_reg(DEV, ADDR, AD7746_REG_EXC_SETUP, reg, 0)) {
DEBUG("[ad7746] init - error: unable to set EXC outputs\n"); DEBUG("[ad7746] init - error: unable to set EXC outputs\n");
goto release; goto release;
} }
@ -167,7 +167,7 @@ int ad7746_init(ad7746_t *dev, const ad7746_params_t *params)
if (dev->params.dac_a_cap) { if (dev->params.dac_a_cap) {
assert(dev->params.dac_a_cap <= AD7746_DAC_MAX); assert(dev->params.dac_a_cap <= AD7746_DAC_MAX);
reg = (1 << AD7746_DACAEN_BIT) | dev->params.dac_a_cap; reg = (1 << AD7746_DACAEN_BIT) | dev->params.dac_a_cap;
if (i2c_write_reg(I2C, ADDR, AD7746_REG_CAP_DAC_A, reg, 0)) { if (i2c_write_reg(DEV, ADDR, AD7746_REG_CAP_DAC_A, reg, 0)) {
DEBUG("[ad7746] init - error: unable to set DAC A\n"); DEBUG("[ad7746] init - error: unable to set DAC A\n");
goto release; goto release;
} }
@ -177,7 +177,7 @@ int ad7746_init(ad7746_t *dev, const ad7746_params_t *params)
if (dev->params.dac_b_cap) { if (dev->params.dac_b_cap) {
assert(dev->params.dac_b_cap <= AD7746_DAC_MAX); assert(dev->params.dac_b_cap <= AD7746_DAC_MAX);
reg = (1 << AD7746_DACBEN_BIT) | dev->params.dac_b_cap; reg = (1 << AD7746_DACBEN_BIT) | dev->params.dac_b_cap;
if (i2c_write_reg(I2C, ADDR, AD7746_REG_CAP_DAC_B, reg, 0)) { if (i2c_write_reg(DEV, ADDR, AD7746_REG_CAP_DAC_B, reg, 0)) {
DEBUG("[ad7746] init - error: unable to set DAC B\n"); DEBUG("[ad7746] init - error: unable to set DAC B\n");
goto release; goto release;
} }
@ -187,7 +187,7 @@ int ad7746_init(ad7746_t *dev, const ad7746_params_t *params)
reg = (1 << AD7746_CONFIGURATION_MD0_BIT) | reg = (1 << AD7746_CONFIGURATION_MD0_BIT) |
(dev->params.cap_sample_rate << AD7746_CONFIGURATION_CAPF0_BIT) | (dev->params.cap_sample_rate << AD7746_CONFIGURATION_CAPF0_BIT) |
(dev->params.vt_sample_rate << AD7746_CONFIGURATION_VTF0_BIT); (dev->params.vt_sample_rate << AD7746_CONFIGURATION_VTF0_BIT);
if (i2c_write_reg(I2C, ADDR, AD7746_REG_CONFIGURATION, reg, 0)) { if (i2c_write_reg(DEV, ADDR, AD7746_REG_CONFIGURATION, reg, 0)) {
DEBUG("[ad7746] init - error: unable to set mode and SR\n"); DEBUG("[ad7746] init - error: unable to set mode and SR\n");
goto release; goto release;
} }
@ -195,7 +195,7 @@ int ad7746_init(ad7746_t *dev, const ad7746_params_t *params)
res = AD7746_OK; res = AD7746_OK;
release: release:
i2c_release(I2C); i2c_release(DEV);
return res; return res;
} }
@ -205,8 +205,8 @@ int ad7746_set_vt_ch_mode(ad7746_t *dev, ad7746_vt_mode_t mode)
int res = AD7746_NOI2C; int res = AD7746_NOI2C;
assert(dev); assert(dev);
i2c_acquire(I2C); i2c_acquire(DEV);
if (i2c_read_reg(I2C, ADDR, AD7746_REG_VT_SETUP, &reg, 0)) { if (i2c_read_reg(DEV, ADDR, AD7746_REG_VT_SETUP, &reg, 0)) {
goto release; goto release;
} }
@ -221,7 +221,7 @@ int ad7746_set_vt_ch_mode(ad7746_t *dev, ad7746_vt_mode_t mode)
(mode << AD7746_VT_SETUP_VTMD0_BIT); (mode << AD7746_VT_SETUP_VTMD0_BIT);
} }
if (i2c_write_reg(I2C, ADDR, AD7746_REG_VT_SETUP, reg, 0)) { if (i2c_write_reg(DEV, ADDR, AD7746_REG_VT_SETUP, reg, 0)) {
DEBUG("[ad7746] set_vt_ch - error: unable to set v/t channel mode\n"); DEBUG("[ad7746] set_vt_ch - error: unable to set v/t channel mode\n");
goto release; goto release;
} }
@ -230,7 +230,7 @@ int ad7746_set_vt_ch_mode(ad7746_t *dev, ad7746_vt_mode_t mode)
dev->params.vt_mode = mode; dev->params.vt_mode = mode;
release: release:
i2c_release(I2C); i2c_release(DEV);
return res; return res;
} }
@ -270,9 +270,9 @@ int ad7746_set_cap_ch_input(const ad7746_t *dev, ad7746_cap_input_t input)
int res = AD7746_NOI2C; int res = AD7746_NOI2C;
assert(dev); assert(dev);
i2c_acquire(I2C); i2c_acquire(DEV);
if (i2c_read_reg(I2C, ADDR, AD7746_REG_CAP_SETUP, &reg, 0)) { if (i2c_read_reg(DEV, ADDR, AD7746_REG_CAP_SETUP, &reg, 0)) {
goto release; goto release;
} }
@ -283,14 +283,14 @@ int ad7746_set_cap_ch_input(const ad7746_t *dev, ad7746_cap_input_t input)
reg &= ~(1 << AD7746_CAP_SETUP_CIN2_BIT); reg &= ~(1 << AD7746_CAP_SETUP_CIN2_BIT);
} }
if (i2c_write_reg(I2C, ADDR, AD7746_REG_CAP_SETUP, reg, 0)) { if (i2c_write_reg(DEV, ADDR, AD7746_REG_CAP_SETUP, reg, 0)) {
goto release; goto release;
} }
res = AD7746_OK; res = AD7746_OK;
release: release:
i2c_release(I2C); i2c_release(DEV);
return res; return res;
} }
@ -300,23 +300,23 @@ int ad7746_set_cap_sr(const ad7746_t *dev, ad7746_cap_sample_rate_t sr)
int res = AD7746_NOI2C; int res = AD7746_NOI2C;
assert(dev); assert(dev);
i2c_acquire(I2C); i2c_acquire(DEV);
if (i2c_read_reg(I2C, ADDR, AD7746_REG_CONFIGURATION, &reg, 0)) { if (i2c_read_reg(DEV, ADDR, AD7746_REG_CONFIGURATION, &reg, 0)) {
goto release; goto release;
} }
reg &= ~(7 << AD7746_CONFIGURATION_CAPF0_BIT); reg &= ~(7 << AD7746_CONFIGURATION_CAPF0_BIT);
reg |= (sr << AD7746_CONFIGURATION_CAPF0_BIT); reg |= (sr << AD7746_CONFIGURATION_CAPF0_BIT);
if (i2c_write_reg(I2C, ADDR, AD7746_REG_CONFIGURATION, reg, 0)) { if (i2c_write_reg(DEV, ADDR, AD7746_REG_CONFIGURATION, reg, 0)) {
goto release; goto release;
} }
res = AD7746_OK; res = AD7746_OK;
release: release:
i2c_release(I2C); i2c_release(DEV);
return res; return res;
} }
@ -326,23 +326,23 @@ int ad7746_set_vt_sr(const ad7746_t *dev, ad7746_vt_sample_rate_t sr)
int res = AD7746_NOI2C; int res = AD7746_NOI2C;
assert(dev); assert(dev);
i2c_acquire(I2C); i2c_acquire(DEV);
if (i2c_read_reg(I2C, ADDR, AD7746_REG_CONFIGURATION, &reg, 0)) { if (i2c_read_reg(DEV, ADDR, AD7746_REG_CONFIGURATION, &reg, 0)) {
goto release; goto release;
} }
reg &= ~(3 << AD7746_CONFIGURATION_VTF0_BIT); reg &= ~(3 << AD7746_CONFIGURATION_VTF0_BIT);
reg |= (sr << AD7746_CONFIGURATION_VTF0_BIT); reg |= (sr << AD7746_CONFIGURATION_VTF0_BIT);
if (i2c_write_reg(I2C, ADDR, AD7746_REG_CONFIGURATION, reg, 0)) { if (i2c_write_reg(DEV, ADDR, AD7746_REG_CONFIGURATION, reg, 0)) {
goto release; goto release;
} }
res = AD7746_OK; res = AD7746_OK;
release: release:
i2c_release(I2C); i2c_release(DEV);
return res; return res;
} }
@ -406,9 +406,9 @@ static int _read_raw_ch(const ad7746_t *dev, uint8_t ch, uint32_t *raw)
assert(dev); assert(dev);
assert((ch == AD7746_READ_CAP_CH) || (ch == AD7746_READ_VT_CH)); assert((ch == AD7746_READ_CAP_CH) || (ch == AD7746_READ_VT_CH));
i2c_acquire(I2C); i2c_acquire(DEV);
if (i2c_read_reg(I2C, ADDR, AD7746_REG_STATUS, buf, 0)) { if (i2c_read_reg(DEV, ADDR, AD7746_REG_STATUS, buf, 0)) {
goto release; goto release;
} }
@ -418,7 +418,7 @@ static int _read_raw_ch(const ad7746_t *dev, uint8_t ch, uint32_t *raw)
goto release; goto release;
} }
if (i2c_read_regs(I2C, ADDR, reg, buf, 3, 0)) { if (i2c_read_regs(DEV, ADDR, reg, buf, 3, 0)) {
goto release; goto release;
} }
@ -427,7 +427,7 @@ static int _read_raw_ch(const ad7746_t *dev, uint8_t ch, uint32_t *raw)
res = AD7746_OK; res = AD7746_OK;
release: release:
i2c_release(I2C); i2c_release(DEV);
return res; return res;
} }

View File

@ -27,7 +27,7 @@
#define ENABLE_DEBUG (0) #define ENABLE_DEBUG (0)
#include "debug.h" #include "debug.h"
#define I2C (dev->params.i2c) #define DEV (dev->params.i2c)
#define ADDR (dev->params.addr) #define ADDR (dev->params.addr)
/* Configuration register test value /* Configuration register test value
@ -42,23 +42,23 @@ int adcxx1c_init(adcxx1c_t *dev, const adcxx1c_params_t *params)
dev->params = *params; dev->params = *params;
dev->cb = NULL; dev->cb = NULL;
i2c_acquire(I2C); i2c_acquire(DEV);
uint8_t reg = 0; uint8_t reg = 0;
/* Test communication write and read configuration register */ /* Test communication write and read configuration register */
status = i2c_write_reg(I2C, ADDR, ADCXX1C_CONF_ADDR, CONF_TEST_VALUE, 0); status = i2c_write_reg(DEV, ADDR, ADCXX1C_CONF_ADDR, CONF_TEST_VALUE, 0);
status += i2c_read_reg(I2C, ADDR, ADCXX1C_CONF_ADDR, &reg, 0); status += i2c_read_reg(DEV, ADDR, ADCXX1C_CONF_ADDR, &reg, 0);
if (status < 0 || reg != CONF_TEST_VALUE) { if (status < 0 || reg != CONF_TEST_VALUE) {
i2c_release(I2C); i2c_release(DEV);
DEBUG("[adcxx1c] init - error: unable to communicate with the device " DEBUG("[adcxx1c] init - error: unable to communicate with the device "
"(reg=%x)\n", reg); "(reg=%x)\n", reg);
return ADCXX1C_NODEV; return ADCXX1C_NODEV;
} }
reg = dev->params.cycle << 5; reg = dev->params.cycle << 5;
status = i2c_write_reg(I2C, ADDR, ADCXX1C_CONF_ADDR, reg, 0); status = i2c_write_reg(DEV, ADDR, ADCXX1C_CONF_ADDR, reg, 0);
i2c_release(I2C); i2c_release(DEV);
if (status < 0) { if (status < 0) {
DEBUG("[adcxx1c] init - error: unable to communicate with the device " DEBUG("[adcxx1c] init - error: unable to communicate with the device "
"(err=%x)\n", status); "(err=%x)\n", status);
@ -75,9 +75,9 @@ int adcxx1c_read_raw(const adcxx1c_t *dev, int16_t *raw)
uint8_t buf[2]; uint8_t buf[2];
int status; int status;
i2c_acquire(I2C); i2c_acquire(DEV);
status = i2c_read_regs(I2C, ADDR, ADCXX1C_CONV_RES_ADDR, buf, 2, 0); status = i2c_read_regs(DEV, ADDR, ADCXX1C_CONV_RES_ADDR, buf, 2, 0);
i2c_release(I2C); i2c_release(DEV);
if (status < 0) { if (status < 0) {
return ADCXX1C_NOI2C; return ADCXX1C_NOI2C;
} }
@ -101,12 +101,12 @@ int adcxx1c_enable_alert(adcxx1c_t *dev, adcxx1c_cb_t cb, void *arg)
uint8_t reg; uint8_t reg;
int status; int status;
i2c_acquire(I2C); i2c_acquire(DEV);
i2c_read_reg(I2C, ADDR, ADCXX1C_CONF_ADDR, &reg, 0); i2c_read_reg(DEV, ADDR, ADCXX1C_CONF_ADDR, &reg, 0);
reg |= (dev->params.alert_pin != GPIO_UNDEF ? ADCXX1C_CONF_ALERT_PIN_EN : 0) reg |= (dev->params.alert_pin != GPIO_UNDEF ? ADCXX1C_CONF_ALERT_PIN_EN : 0)
| ADCXX1C_CONF_ALERT_FLAG_EN; | ADCXX1C_CONF_ALERT_FLAG_EN;
status = i2c_write_reg(I2C, ADDR, ADCXX1C_CONF_ADDR, reg, 0); status = i2c_write_reg(DEV, ADDR, ADCXX1C_CONF_ADDR, reg, 0);
i2c_release(I2C); i2c_release(DEV);
if (status < 0) { if (status < 0) {
DEBUG("[adcxx1c] enable_alert - error: unable to communicate with the " DEBUG("[adcxx1c] enable_alert - error: unable to communicate with the "
"device (err=%d)\n", status); "device (err=%d)\n", status);
@ -129,14 +129,14 @@ int adcxx1c_set_alert_parameters(const adcxx1c_t *dev, int16_t low_limit,
uint8_t buf[2]; uint8_t buf[2];
int status; int status;
i2c_acquire(I2C); i2c_acquire(DEV);
low_limit <<= (12 - dev->params.bits); low_limit <<= (12 - dev->params.bits);
buf[0] = low_limit >> 8; buf[0] = low_limit >> 8;
buf[1] = low_limit & 0xFF; buf[1] = low_limit & 0xFF;
status = i2c_write_regs(I2C, ADDR, ADCXX1C_LOW_LIMIT_ADDR, buf, 2, 0); status = i2c_write_regs(DEV, ADDR, ADCXX1C_LOW_LIMIT_ADDR, buf, 2, 0);
if (status < 0) { if (status < 0) {
i2c_release(I2C); i2c_release(DEV);
DEBUG("[adcxx1c] set_alert (low limit) - error: unable to communicate " DEBUG("[adcxx1c] set_alert (low limit) - error: unable to communicate "
"with the device (err=%d)\n", status); "with the device (err=%d)\n", status);
return ADCXX1C_NOI2C; return ADCXX1C_NOI2C;
@ -145,9 +145,9 @@ int adcxx1c_set_alert_parameters(const adcxx1c_t *dev, int16_t low_limit,
high_limit <<= (12 - dev->params.bits); high_limit <<= (12 - dev->params.bits);
buf[0] = high_limit >> 8; buf[0] = high_limit >> 8;
buf[1] = high_limit & 0xFF; buf[1] = high_limit & 0xFF;
status = i2c_write_regs(I2C, ADDR, ADCXX1C_HIGH_LIMIT_ADDR, buf, 2, 0); status = i2c_write_regs(DEV, ADDR, ADCXX1C_HIGH_LIMIT_ADDR, buf, 2, 0);
if (status < 0) { if (status < 0) {
i2c_release(I2C); i2c_release(DEV);
DEBUG("[adcxx1c] set_alert (high limit) - error: unable to communicate " DEBUG("[adcxx1c] set_alert (high limit) - error: unable to communicate "
"with the device (err=%d)\n", status); "with the device (err=%d)\n", status);
return ADCXX1C_NOI2C; return ADCXX1C_NOI2C;
@ -156,15 +156,15 @@ int adcxx1c_set_alert_parameters(const adcxx1c_t *dev, int16_t low_limit,
hysteresis <<= (12 - dev->params.bits); hysteresis <<= (12 - dev->params.bits);
buf[0] = hysteresis >> 8; buf[0] = hysteresis >> 8;
buf[1] = hysteresis & 0xFF; buf[1] = hysteresis & 0xFF;
status = i2c_write_regs(I2C, ADDR, ADCXX1C_HYSTERESIS_ADDR, buf, 2, 0); status = i2c_write_regs(DEV, ADDR, ADCXX1C_HYSTERESIS_ADDR, buf, 2, 0);
if (status < 0) { if (status < 0) {
i2c_release(I2C); i2c_release(DEV);
DEBUG("[adcxx1c] set_alert (hysteresis) - error: unable to communicate " DEBUG("[adcxx1c] set_alert (hysteresis) - error: unable to communicate "
"with the device (err=%d)\n", status); "with the device (err=%d)\n", status);
return ADCXX1C_NOI2C; return ADCXX1C_NOI2C;
} }
i2c_release(I2C); i2c_release(DEV);
return ADCXX1C_OK; return ADCXX1C_OK;
} }

View File

@ -35,7 +35,7 @@
#define ADS101X_READ_DELAY (8 * US_PER_MS) /* Compatible with 128SPS */ #define ADS101X_READ_DELAY (8 * US_PER_MS) /* Compatible with 128SPS */
#endif #endif
#define I2C (dev->params.i2c) #define DEV (dev->params.i2c)
#define ADDR (dev->params.addr) #define ADDR (dev->params.addr)
static int _ads101x_init_test(i2c_t i2c, uint8_t addr); static int _ads101x_init_test(i2c_t i2c, uint8_t addr);
@ -46,7 +46,7 @@ int ads101x_init(ads101x_t *dev, const ads101x_params_t *params)
dev->params = *params; dev->params = *params;
return _ads101x_init_test(I2C, ADDR); return _ads101x_init_test(DEV, ADDR);
} }
int ads101x_alert_init(ads101x_alert_t *dev, int ads101x_alert_init(ads101x_alert_t *dev,
@ -62,7 +62,7 @@ int ads101x_alert_init(ads101x_alert_t *dev,
ads101x_set_alert_parameters(dev, dev->params.low_limit, ads101x_set_alert_parameters(dev, dev->params.low_limit,
dev->params.high_limit); dev->params.high_limit);
return _ads101x_init_test(I2C, ADDR); return _ads101x_init_test(DEV, ADDR);
} }
static int _ads101x_init_test(i2c_t i2c, uint8_t addr) static int _ads101x_init_test(i2c_t i2c, uint8_t addr)
@ -106,9 +106,9 @@ int ads101x_set_mux_gain(const ads101x_t *dev, uint8_t mux_gain)
{ {
uint8_t regs[2]; uint8_t regs[2];
i2c_acquire(I2C); i2c_acquire(DEV);
i2c_read_regs(I2C, ADDR, ADS101X_CONF_ADDR, &regs, 2, 0x0); i2c_read_regs(DEV, ADDR, ADS101X_CONF_ADDR, &regs, 2, 0x0);
/* Zero mux and gain */ /* Zero mux and gain */
regs[0] &= ~ADS101X_MUX_MASK; regs[0] &= ~ADS101X_MUX_MASK;
@ -117,9 +117,9 @@ int ads101x_set_mux_gain(const ads101x_t *dev, uint8_t mux_gain)
/* Write mux and gain */ /* Write mux and gain */
regs[0] |= mux_gain; regs[0] |= mux_gain;
i2c_write_regs(I2C, ADDR, ADS101X_CONF_ADDR, &regs, 2, 0x0); i2c_write_regs(DEV, ADDR, ADS101X_CONF_ADDR, &regs, 2, 0x0);
i2c_release(I2C); i2c_release(DEV);
return ADS101X_OK; return ADS101X_OK;
} }
@ -128,25 +128,25 @@ int ads101x_read_raw(const ads101x_t *dev, int16_t *raw)
{ {
uint8_t regs[2]; uint8_t regs[2];
i2c_acquire(I2C); i2c_acquire(DEV);
/* Read control register */ /* Read control register */
i2c_read_regs(I2C, ADDR, ADS101X_CONF_ADDR, &regs, 2, 0x0); i2c_read_regs(DEV, ADDR, ADS101X_CONF_ADDR, &regs, 2, 0x0);
/* Tell the ADC to aquire a single-shot sample */ /* Tell the ADC to aquire a single-shot sample */
regs[0] |= ADS101X_CONF_OS_CONV; regs[0] |= ADS101X_CONF_OS_CONV;
i2c_write_regs(I2C, ADDR, ADS101X_CONF_ADDR, &regs, 2, 0x0); i2c_write_regs(DEV, ADDR, ADS101X_CONF_ADDR, &regs, 2, 0x0);
/* Wait for the sample to be aquired */ /* Wait for the sample to be aquired */
xtimer_usleep(ADS101X_READ_DELAY); xtimer_usleep(ADS101X_READ_DELAY);
/* Read the sample */ /* Read the sample */
if (i2c_read_regs(I2C, ADDR, ADS101X_CONV_RES_ADDR, &regs, 2, 0x0) < 0) { if (i2c_read_regs(DEV, ADDR, ADS101X_CONV_RES_ADDR, &regs, 2, 0x0) < 0) {
i2c_release(I2C); i2c_release(DEV);
return ADS101X_NODATA; return ADS101X_NODATA;
} }
i2c_release(I2C); i2c_release(DEV);
/* If all okay, change raw value */ /* If all okay, change raw value */
*raw = (int16_t)(regs[0] << 8) | (int16_t)(regs[1]); *raw = (int16_t)(regs[0] << 8) | (int16_t)(regs[1]);
@ -164,14 +164,14 @@ int ads101x_enable_alert(ads101x_alert_t *dev,
} }
/* Read control register */ /* Read control register */
i2c_acquire(I2C); i2c_acquire(DEV);
i2c_read_regs(I2C, ADDR, ADS101X_CONF_ADDR, &regs, 2, 0x0); i2c_read_regs(DEV, ADDR, ADS101X_CONF_ADDR, &regs, 2, 0x0);
/* Enable alert comparator */ /* Enable alert comparator */
regs[1] &= ~ADS101X_CONF_COMP_DIS; regs[1] &= ~ADS101X_CONF_COMP_DIS;
i2c_write_regs(I2C, ADDR, ADS101X_CONF_ADDR, &regs, 2, 0x0); i2c_write_regs(DEV, ADDR, ADS101X_CONF_ADDR, &regs, 2, 0x0);
i2c_release(I2C); i2c_release(DEV);
/* Enable interrupt */ /* Enable interrupt */
dev->arg = arg; dev->arg = arg;
@ -186,20 +186,20 @@ int ads101x_set_alert_parameters(const ads101x_alert_t *dev,
{ {
uint8_t regs[2]; uint8_t regs[2];
i2c_acquire(I2C); i2c_acquire(DEV);
/* Set up low_limit */ /* Set up low_limit */
regs[0] = (uint8_t)(low_limit >> 8); regs[0] = (uint8_t)(low_limit >> 8);
regs[1] = (uint8_t)low_limit; regs[1] = (uint8_t)low_limit;
i2c_write_regs(I2C, ADDR, ADS101X_LOW_LIMIT_ADDR, &regs, 2, 0x0); i2c_write_regs(DEV, ADDR, ADS101X_LOW_LIMIT_ADDR, &regs, 2, 0x0);
/* Set up high_limit */ /* Set up high_limit */
regs[0] = (uint8_t)(high_limit >> 8); regs[0] = (uint8_t)(high_limit >> 8);
regs[1] = (uint8_t)high_limit; regs[1] = (uint8_t)high_limit;
i2c_write_regs(I2C, ADDR, ADS101X_HIGH_LIMIT_ADDR, &regs, 2, 0x0); i2c_write_regs(DEV, ADDR, ADS101X_HIGH_LIMIT_ADDR, &regs, 2, 0x0);
/* Read control register */ /* Read control register */
i2c_read_regs(I2C, ADDR, ADS101X_CONF_ADDR, &regs, 2, 0x0); i2c_read_regs(DEV, ADDR, ADS101X_CONF_ADDR, &regs, 2, 0x0);
/* Set up window mode */ /* Set up window mode */
if (low_limit != 0) { if (low_limit != 0) {
@ -210,9 +210,9 @@ int ads101x_set_alert_parameters(const ads101x_alert_t *dev,
/* Disable window mode */ /* Disable window mode */
regs[1] &= ~ADS101X_CONF_COMP_MODE_WIND; regs[1] &= ~ADS101X_CONF_COMP_MODE_WIND;
} }
i2c_write_regs(I2C, ADDR, ADS101X_CONF_ADDR, &regs, 2, 0x0); i2c_write_regs(DEV, ADDR, ADS101X_CONF_ADDR, &regs, 2, 0x0);
i2c_release(I2C); i2c_release(DEV);
return ADS101X_OK; return ADS101X_OK;
} }