diff --git a/cpu/gd32v/Kconfig b/cpu/gd32v/Kconfig new file mode 100644 index 0000000000..0ca68c9ecc --- /dev/null +++ b/cpu/gd32v/Kconfig @@ -0,0 +1,38 @@ +# Copyright (c) 2020 Inria +# +# This file is subject to the terms and conditions of the GNU Lesser +# General Public License v2.1. See the file LICENSE in the top level +# directory for more details. +# + +config CPU_FAM_GD32V + bool + select CPU_CORE_RV32I + select HAS_CPU_GD32V + select HAS_PERIPH_CLIC + select HAS_PERIPH_GPIO + select HAS_PERIPH_FLASHPAGE + select HAS_PERIPH_FLASHPAGE_PAGEWISE + select HAS_PERIPH_PM + select HAS_PERIPH_WDT + +config CPU_MODEL_GD32VF103VBT6 + bool + select CPU_FAM_GD32V + +## Definition of specific features +config HAS_CPU_GD32V + bool + help + Indicates that a 'gd32v' cpu is being used. + +config CPU_FAM + default "gd32v" if CPU_FAM_GD32V + +config CPU_MODEL + default "gd32vf103vbt6" if CPU_MODEL_GD32VF103VBT6 + +config CPU + default "gd32v" if CPU_FAM_GD32V + +source "$(RIOTCPU)/riscv_common/Kconfig" diff --git a/cpu/gd32v/Makefile b/cpu/gd32v/Makefile new file mode 100644 index 0000000000..d10d9f2635 --- /dev/null +++ b/cpu/gd32v/Makefile @@ -0,0 +1,6 @@ +# define the module that is built +MODULE = cpu + +DIRS += periph $(RIOTCPU)/riscv_common + +include $(RIOTBASE)/Makefile.base diff --git a/cpu/gd32v/Makefile.dep b/cpu/gd32v/Makefile.dep new file mode 100644 index 0000000000..b5500510a4 --- /dev/null +++ b/cpu/gd32v/Makefile.dep @@ -0,0 +1,15 @@ +FEATURES_REQUIRED += periph_clic +FEATURES_REQUIRED_ANY += newlib|picolibc +ifneq (,$(filter newlib,$(USEMODULE))) + USEMODULE += newlib_nano + USEMODULE += newlib_syscalls_default +endif + +USEMODULE += periph +USEMODULE += riscv_common + +ifneq (,$(filter periph_pm,$(USEMODULE))) + FEATURES_REQUIRED += periph_wdt +endif + +include $(RIOTCPU)/riscv_common/Makefile.dep diff --git a/cpu/gd32v/Makefile.features b/cpu/gd32v/Makefile.features new file mode 100644 index 0000000000..489f9ca4b9 --- /dev/null +++ b/cpu/gd32v/Makefile.features @@ -0,0 +1,9 @@ +FEATURES_PROVIDED += periph_clic +FEATURES_PROVIDED += periph_gpio +FEATURES_PROVIDED += periph_timer +FEATURES_PROVIDED += periph_wdt +FEATURES_PROVIDED += periph_pm +FEATURES_PROVIDED += periph_flashpage +FEATURES_PROVIDED += periph_flashpage_pagewise + +include $(RIOTCPU)/riscv_common/Makefile.features diff --git a/cpu/gd32v/Makefile.include b/cpu/gd32v/Makefile.include new file mode 100644 index 0000000000..3b1ec4d9a3 --- /dev/null +++ b/cpu/gd32v/Makefile.include @@ -0,0 +1,9 @@ +RAM_START_ADDR ?= 0x20000000 +RAM_LEN ?= 32K + +ROM_START_ADDR ?= 0x08000000 +ROM_LEN ?= 128K + +LINKER_SCRIPT ?= riscv.ld + +include $(RIOTCPU)/riscv_common/Makefile.include diff --git a/cpu/gd32v/clock.c b/cpu/gd32v/clock.c new file mode 100644 index 0000000000..d9146d0353 --- /dev/null +++ b/cpu/gd32v/clock.c @@ -0,0 +1,149 @@ +/* + * Copyright (C) 2020 Koen Zandberg + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ +/** + * @ingroup cpu_gd32v + * @{ + * + * @file + * @brief GD32V Clock initialization + * + * @author Koen Zandberg + * + * Heavily based on the stm32f1 connectivity line clock initialization + */ +#include "kernel_defines.h" +#include "irq.h" +#include "cpu.h" +#include "periph_conf.h" + +#define CLOCK_AHB CLOCK_CORECLOCK /* Equal to the CPU clock */ +#define CLOCK_APB1 CLOCK_AHB/2 /* Half AHB clock */ +#define CLOCK_APB2 CLOCK_AHB /* Equal to the AHB clock */ + +#define CLOCK_AHB_DIV 0 /* Max speed at 108 MHz */ +#define CLOCK_APB1_DIV (0x04 | 0) /* Max speed at 54 MHz */ +#define CLOCK_APB2_DIV (0x0 | 0) /* Max speed at 108 MHz */ + +#define CLOCK_AHB_DIV_CONF (CLOCK_AHB_DIV << RCU_CFG0_AHBPSC_Pos) +#define CLOCK_APB1_DIV_CONF (CLOCK_APB1_DIV << RCU_CFG0_APB1PSC_Pos) +#define CLOCK_APB2_DIV_CONF (CLOCK_APB2_DIV << RCU_CFG0_APB2PSC_Pos) + +#define PREDV0_CONF 1 /* Divide by 2 */ +#define PLL_MULT_FACTOR (CLOCK_CORECLOCK / \ + (CLOCK_HXTAL / (PREDV0_CONF + 1)) - 1) + +#define RCU_CFG0_SCS_IRC8 (0 << RCU_CFG0_SCS_Pos) +#define RCU_CFG0_SCS_HXTAL (1 << RCU_CFG0_SCS_Pos) +#define RCU_CFG0_SCS_PLL (2 << RCU_CFG0_SCS_Pos) + +#define ENABLE_DEBUG 0 +#include "debug.h" + +void periph_clk_en(bus_t bus, uint32_t mask) +{ + switch (bus) { + case AHB: + cpu_reg_enable_bits(&RCU->AHBEN, mask); + break; + case APB1: + cpu_reg_enable_bits(&RCU->APB1EN, mask); + break; + case APB2: + cpu_reg_enable_bits(&RCU->APB2EN, mask); + break; + default: + DEBUG("unsupported bus %d\n", (int)bus); + break; + } +} + +void periph_clk_dis(bus_t bus, uint32_t mask) +{ + switch (bus) { + case AHB: + cpu_reg_disable_bits(&RCU->AHBEN, mask); + break; + case APB1: + cpu_reg_disable_bits(&RCU->APB1EN, mask); + break; + case APB2: + cpu_reg_disable_bits(&RCU->APB2EN, mask); + break; + default: + DEBUG("unsupported bus %d\n", (int)bus); + break; + } +} + +uint32_t periph_apb_clk(bus_t bus) +{ + switch (bus) { + case AHB: + return CLOCK_AHB; + case APB1: + return CLOCK_APB1; + case APB2: + return CLOCK_APB2; + } + return 0; +} + +void gd32v_enable_irc8(void) +{ + cpu_reg_enable_bits(&RCU->CTL, RCU_CTL_IRC8MEN_Msk); + while (!(RCU->CTL & RCU_CTL_IRC8MSTB_Msk)) {} +} + +void gd32v_disable_irc8(void) +{ + RCU->CTL &= ~(RCU_CTL_IRC8MEN_Msk); +} + +void gd32vf103_clock_init(void) +{ + unsigned is = irq_disable(); + + /* enable HSI clock for the duration of initialization */ + gd32v_enable_irc8(); + + /* use HSI as system clock while we do any further configuration and + * configure the AHB and APB clock dividers as configure by the board */ + RCU->CFG0 = (RCU_CFG0_SCS_IRC8 | CLOCK_AHB_DIV_CONF | + CLOCK_APB1_DIV_CONF | CLOCK_APB2_DIV_CONF); + while ((RCU->CFG0 & RCU_CFG0_SCSS_Msk) != + (RCU_CFG0_SCS_IRC8 << RCU_CFG0_SCSS_Pos)) {} + + /* disable all active clocks except IRC8 -> resets the clk configuration */ + RCU->CTL = (RCU_CTL_IRC8MEN_Msk); + + if (IS_ACTIVE(CONFIG_BOARD_HAS_HXTAL)) { + cpu_reg_enable_bits(&RCU->CTL, RCU_CTL_HXTALEN_Msk); + while (!(RCU->CTL & RCU_CTL_HXTALSTB_Msk)) {} + } + + RCU->CFG1 = (PREDV0_CONF); + + RCU->CFG0 |= (CLOCK_HXTAL << RCU_CFG0_PLLSEL_Pos) | + ((PLL_MULT_FACTOR & 0xf) << RCU_CFG0_PLLMF_3_0_Pos) | + ((PLL_MULT_FACTOR & 0x10) << (RCU_CFG0_PLLMF_4_Pos - 4)); + + RCU->CTL |= (RCU_CTL_PLLEN_Msk); + + /* Wait for PLL to stabilize */ + while ((RCU->CTL & RCU_CTL_PLLSTB_Msk) != RCU_CTL_PLLSTB_Msk) {} + + /* Switch clock input */ + RCU->CFG0 |= RCU_CFG0_SCS_PLL; + + RCU->AHBEN &= ~RCU_AHBEN_FMCSPEN_Msk; + + while ((RCU->CFG0 & RCU_CFG0_SCSS_Msk) != + (RCU_CFG0_SCS_PLL << RCU_CFG0_SCSS_Pos)) {} + gd32v_disable_irc8(); + irq_restore(is); +} diff --git a/cpu/gd32v/cpu.c b/cpu/gd32v/cpu.c new file mode 100644 index 0000000000..0f31dfba11 --- /dev/null +++ b/cpu/gd32v/cpu.c @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2020 Koen Zandberg + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ +/** + * @ingroup cpu_gd32v + * @{ + * + * @file + * @brief GD32V CPU initialization + * + * @author Koen Zandberg + */ +#include "stdio_uart.h" +#include "periph/init.h" +#include "irq_arch.h" +#include "periph_cpu.h" +#include "periph_conf.h" + +#define ENABLE_DEBUG 0 +#include "debug.h" + +extern void __libc_init_array(void); + +void cpu_init(void) +{ + gd32vf103_clock_init(); + /* Common RISC-V initialization */ + riscv_init(); + stdio_init(); + periph_init(); +} diff --git a/cpu/gd32v/doc.txt b/cpu/gd32v/doc.txt new file mode 100644 index 0000000000..05e7264454 --- /dev/null +++ b/cpu/gd32v/doc.txt @@ -0,0 +1,6 @@ +/** + * @defgroup cpu_gd32v GD32V + * @ingroup cpu + * @brief GigaDevice GD32 RISC-V Microcontrollers + * + */ diff --git a/cpu/gd32v/include/cpu_conf.h b/cpu/gd32v/include/cpu_conf.h new file mode 100644 index 0000000000..eab6b59b9f --- /dev/null +++ b/cpu/gd32v/include/cpu_conf.h @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2020 Koen Zandberg + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup cpu_gd32v + * @{ + * + * @file + * @brief CPU specific configuration options + * + * @author Koen Zandberg + */ + +#include "vendor/gd32vf103_core.h" +#include "cpu_conf_common.h" + +#ifndef CPU_CONF_H +#define CPU_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define CLIC_NUM_INTERRUPTS (ECLIC_NUM_INTERRUPTS) +#define CLIC_BASE_ADDR (ECLIC_CTRL_ADDR) +#define CPU_DEFAULT_IRQ_PRIO (0xFF) + +/** + * @brief The gd32v doesn't use the MIE CSR, but uses the CLIC instead + */ +#define HAVE_CSR_MIE (0) + +/** + * @name Flashpage settings + * @{ + */ +#define FLASHPAGE_SIZE (1024U) +#define FLASHPAGE_NUMOF (128U) +#define FLASHPAGE_WRITE_BLOCK_SIZE (2U) +#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U) +#define CPU_FLASH_BASE 0x08000000 +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* CPU_CONF_H */ +/** @} */ diff --git a/cpu/gd32v/include/periph_cpu.h b/cpu/gd32v/include/periph_cpu.h new file mode 100644 index 0000000000..df4bae1e71 --- /dev/null +++ b/cpu/gd32v/include/periph_cpu.h @@ -0,0 +1,289 @@ +/* + * Copyright (C) 2020 Koen Zandberg + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup cpu_gd32v + * @{ + * + * @file + * @brief CPU specific definitions for internal peripheral handling + * + * @author Koen Zandberg + */ + +#ifndef PERIPH_CPU_H +#define PERIPH_CPU_H + +#include + +#include "cpu.h" +#include "clic.h" +#include "kernel_defines.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Power management configuration + * @{ + */ +#define PROVIDES_PM_SET_LOWEST +/** @} */ + +/** + * @brief On-Chip buses + */ +typedef enum { + AHB, /**< Advanced High-performance Bus */ + APB1, /**< Advanced Peripheral Bus 1 */ + APB2, /**< Advanced Peripheral Bus 2 */ +} bus_t; + +/** + * @brief Available GPIO ports + */ +enum { +#ifdef GPIOA + PORT_A = 0, /**< port A */ +#endif +#ifdef GPIOB + PORT_B = 1, /**< port B */ +#endif +#ifdef GPIOC + PORT_C = 2, /**< port C */ +#endif +#ifdef GPIOD + PORT_D = 3, /**< port D */ +#endif +#ifdef GPIOE + PORT_E = 4, /**< port E */ +#endif +}; + +#ifndef DOXYGEN +/** + * @brief Overwrite the default gpio_t type definition + * @{ + */ +#define HAVE_GPIO_T +typedef uint32_t gpio_t; +/** @} */ + +/** + * @brief Definition of a fitting UNDEF value + */ +#define GPIO_UNDEF (0xffffffff) + +/** + * @brief Define a CPU specific GPIO pin generator macro + */ +#define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 10)) | y) + +/** + * @brief Generate GPIO mode bitfields + * + * We use 5 bit to encode the mode: + * - bit 0+1: pin mode (input / output) + * - bit 2+3: pull resistor configuration + * - bit 4: output type (0: push-pull, 1: open-drain) + */ +#define GPIO_MODE(io, pr, ot) ((io << 0) | (pr << 2) | (ot << 4)) +/** + * @brief Override GPIO mode options + * + * We use 4 bit to encode CNF and MODE. + * @{ + */ +#define HAVE_GPIO_MODE_T +typedef enum { + GPIO_IN = GPIO_MODE(0, 1, 0), /**< input w/o pull R */ + GPIO_IN_PD = GPIO_MODE(0, 2, 0), /**< input with pull-down */ + GPIO_IN_PU = GPIO_MODE(0, 2, 1), /**< input with pull-up */ + GPIO_OUT = GPIO_MODE(3, 0, 0), /**< push-pull output */ + GPIO_OD = GPIO_MODE(3, 1, 0), /**< open-drain w/o pull R */ + GPIO_OD_PU = (0xff) /**< not supported by HW */ +} gpio_mode_t; +/** @} */ +#endif /* ndef DOXYGEN */ + +/** + * @brief Override alternative GPIO mode options + */ +typedef enum { + GPIO_AF_OUT_PP = 0xb, /**< alternate function output - push-pull */ + GPIO_AF_OUT_OD = 0xf, /**< alternate function output - open-drain */ +} gpio_af_t; + +/** + * @brief Timer configuration + */ +typedef struct { + TIMER_Type *dev; /**< timer device */ + uint32_t max; /**< maximum value to count to (16/32 bit) */ + uint32_t rcu_mask; /**< corresponding bit in the RCC register */ + uint8_t bus; /**< APBx bus the timer is clock from */ + uint8_t irqn; /**< global IRQ channel */ +} timer_conf_t; + +/** + * @brief Structure for UART configuration data + */ +typedef struct { + USART_Type *dev; /**< UART device base register address */ + uint32_t rcu_mask; /**< bit in clock enable register */ + gpio_t rx_pin; /**< RX pin */ + gpio_t tx_pin; /**< TX pin */ + uint8_t bus; /**< APB bus */ + uint8_t irqn; /**< IRQ channel */ +} uart_conf_t; + +/** + * @brief UART interrupt priority + */ +#define UART_ISR_PRIO (2) + +/** + * @name This CPU makes use of the following shared SPI functions + * @{ + */ +#define PERIPH_SPI_NEEDS_TRANSFER_BYTE 1 +#define PERIPH_SPI_NEEDS_TRANSFER_REG 1 +#define PERIPH_SPI_NEEDS_TRANSFER_REGS 1 +/** @} */ + +/** + * @brief Structure for SPI configuration data + */ +typedef struct { + uint32_t addr; /**< SPI control register address */ + gpio_t mosi; /**< MOSI pin */ + gpio_t miso; /**< MISO pin */ + gpio_t sclk; /**< SCLK pin */ +} spi_conf_t; + +/** + * @name Use the shared I2C functions + * @{ + */ +/** Use read reg function from periph common */ +#define PERIPH_I2C_NEED_READ_REG +/** Use write reg function from periph common */ +#define PERIPH_I2C_NEED_WRITE_REG +/** Use read regs function from periph common */ +#define PERIPH_I2C_NEED_READ_REGS +/** Use write regs function from periph common */ +#define PERIPH_I2C_NEED_WRITE_REGS +/** @} */ + +#ifndef DOXYGEN +/** + * @brief Default mapping of I2C bus speed values + * @{ + */ +#define HAVE_I2C_SPEED_T +typedef enum { + I2C_SPEED_NORMAL, /**< normal mode: ~100kbit/s */ + I2C_SPEED_FAST, /**< fast mode: ~400kbit/s */ +} i2c_speed_t; +/** @} */ +#endif /* ndef DOXYGEN */ + +/** + * @brief I2C configuration options + */ +typedef struct { + uint32_t addr; /**< device base address */ + gpio_t scl; /**< SCL pin */ + gpio_t sda; /**< SDA pin */ + i2c_speed_t speed; /**< I2C speed */ +} i2c_conf_t; + +/** + * @name WDT upper and lower bound times in ms + * @{ + */ +#define NWDT_TIME_LOWER_LIMIT (1) +/* Ensure the internal "count" variable stays within the uint32 bounds. + This variable corresponds to max_time * RTC_FREQ / MS_PER_SEC. On fe310, + RTC_FREQ is 32768Hz. The 15 right shift is equivalent to a division by RTC_FREQ. + */ +#define NWDT_TIME_UPPER_LIMIT ((UINT32_MAX >> 15) * MS_PER_SEC + 1) +/** @} */ + +/** + * @brief WDT interrupt priority: use highest priority + */ +#define WDT_INTR_PRIORITY (PLIC_NUM_PRIORITIES) + +/** + * @brief No brakes on the WDT train + */ +#define WDT_HAS_STOP (0) + +/** + * @name RTT/RTC configuration + * + * @{ + */ +#define RTT_INTR_PRIORITY (2) + +#define RTT_MAX_VALUE (0xffffffff) +#define RTT_CLOCK_FREQUENCY (32768U) /* in Hz */ +#define RTT_MAX_FREQUENCY (RTT_CLOCK_FREQUENCY) /* in Hz */ +#define RTT_MIN_FREQUENCY (1U) /* in Hz */ + +#ifndef RTT_FREQUENCY +#define RTT_FREQUENCY (RTT_MAX_FREQUENCY) /* in Hz */ +#endif + +/** + * @brief Enable the given peripheral clock + * + * @param[in] bus bus the peripheral is connected to + * @param[in] mask bit in the RCU enable register + */ +void periph_clk_en(bus_t bus, uint32_t mask); + +/** + * @brief Disable the given peripheral clock + * + * @param[in] bus bus the peripheral is connected to + * @param[in] mask bit in the RCU enable register + */ +void periph_clk_dis(bus_t bus, uint32_t mask); + +/** + * @brief Get the actual bus clock frequency for the APB buses + * + * @param[in] bus target APBx bus + * + * @return bus clock frequency in Hz + */ +uint32_t periph_apb_clk(bus_t bus); + +/** + * @brief Configure the alternate function for the given pin + * + * @param[in] pin pin to configure + * @param[in] af alternate function to use + */ +void gpio_init_af(gpio_t pin, gpio_af_t af); + +void gd32vf103_clock_init(void); +void gd32v_enable_irc8(void); +void gd32v_disable_irc8(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* PERIPH_CPU_H */ +/** @} */ diff --git a/cpu/gd32v/include/vendor/gd32vf103.h b/cpu/gd32v/include/vendor/gd32vf103.h new file mode 100644 index 0000000000..feba8fd87e --- /dev/null +++ b/cpu/gd32v/include/vendor/gd32vf103.h @@ -0,0 +1,196 @@ +/*! + \file gd32vf103.h + \brief general definitions for GD32VF103 + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_H +#define GD32VF103_H + +#ifdef cplusplus + extern "C" { +#endif + + /* IO definitions (access restrictions to peripheral registers) */ + /** + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. + */ + #ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ + #else + #define __I volatile const /*!< Defines 'read only' permissions */ + #endif + #define __O volatile /*!< Defines 'write only' permissions */ + #define __IO volatile /*!< Defines 'read / write' permissions */ + +#include "vendor/gd32vf103_periph.h" + +/* define interrupt number */ +typedef enum IRQn +{ + + CLIC_INT_RESERVED = 0, /*!< RISC-V reserved */ + CLIC_INT_SFT = 3, /*!< Software interrupt */ + CLIC_INT_TMR = 7, /*!< CPU Timer interrupt */ + CLIC_INT_BWEI = 17, /*!< Bus Error interrupt */ + CLIC_INT_PMOVI = 18, /*!< Performance Monitor */ + + /* interruput numbers */ + WWDGT_IRQn = 19, /*!< window watchDog timer interrupt */ + LVD_IRQn = 20, /*!< LVD through EXTI line detect interrupt */ + TAMPER_IRQn = 21, /*!< tamper through EXTI line detect */ + RTC_IRQn = 22, /*!< RTC alarm interrupt */ + FMC_IRQn = 23, /*!< FMC interrupt */ + RCU_CTC_IRQn = 24, /*!< RCU and CTC interrupt */ + EXTI0_IRQn = 25, /*!< EXTI line 0 interrupts */ + EXTI1_IRQn = 26, /*!< EXTI line 1 interrupts */ + EXTI2_IRQn = 27, /*!< EXTI line 2 interrupts */ + EXTI3_IRQn = 28, /*!< EXTI line 3 interrupts */ + EXTI4_IRQn = 29, /*!< EXTI line 4 interrupts */ + DMA0_Channel0_IRQn = 30, /*!< DMA0 channel0 interrupt */ + DMA0_Channel1_IRQn = 31, /*!< DMA0 channel1 interrupt */ + DMA0_Channel2_IRQn = 32, /*!< DMA0 channel2 interrupt */ + DMA0_Channel3_IRQn = 33, /*!< DMA0 channel3 interrupt */ + DMA0_Channel4_IRQn = 34, /*!< DMA0 channel4 interrupt */ + DMA0_Channel5_IRQn = 35, /*!< DMA0 channel5 interrupt */ + DMA0_Channel6_IRQn = 36, /*!< DMA0 channel6 interrupt */ + ADC0_1_IRQn = 37, /*!< ADC0 and ADC1 interrupt */ + CAN0_TX_IRQn = 38, /*!< CAN0 TX interrupts */ + CAN0_RX0_IRQn = 39, /*!< CAN0 RX0 interrupts */ + CAN0_RX1_IRQn = 40, /*!< CAN0 RX1 interrupts */ + CAN0_EWMC_IRQn = 41, /*!< CAN0 EWMC interrupts */ + EXTI5_9_IRQn = 42, /*!< EXTI[9:5] interrupts */ + TIMER0_BRK_IRQn = 43, /*!< TIMER0 break interrupts */ + TIMER0_UP_IRQn = 44, /*!< TIMER0 update interrupts */ + TIMER0_TRG_CMT_IRQn = 45, /*!< TIMER0 trigger and commutation interrupts */ + TIMER0_Channel_IRQn = 46, /*!< TIMER0 channel capture compare interrupts */ + TIMER1_IRQn = 47, /*!< TIMER1 interrupt */ + TIMER2_IRQn = 48, /*!< TIMER2 interrupt */ + TIMER3_IRQn = 49, /*!< TIMER3 interrupts */ + I2C0_EV_IRQn = 50, /*!< I2C0 event interrupt */ + I2C0_ER_IRQn = 51, /*!< I2C0 error interrupt */ + I2C1_EV_IRQn = 52, /*!< I2C1 event interrupt */ + I2C1_ER_IRQn = 53, /*!< I2C1 error interrupt */ + SPI0_IRQn = 54, /*!< SPI0 interrupt */ + SPI1_IRQn = 55, /*!< SPI1 interrupt */ + USART0_IRQn = 56, /*!< USART0 interrupt */ + USART1_IRQn = 57, /*!< USART1 interrupt */ + USART2_IRQn = 58, /*!< USART2 interrupt */ + EXTI10_15_IRQn = 59, /*!< EXTI[15:10] interrupts */ + RTC_ALARM_IRQn = 60, /*!< RTC alarm interrupt EXTI */ + USBFS_WKUP_IRQn = 61, /*!< USBFS wakeup interrupt */ + + EXMC_IRQn = 67, /*!< EXMC global interrupt */ + + TIMER4_IRQn = 69, /*!< TIMER4 global interrupt */ + SPI2_IRQn = 70, /*!< SPI2 global interrupt */ + UART3_IRQn = 71, /*!< UART3 global interrupt */ + UART4_IRQn = 72, /*!< UART4 global interrupt */ + TIMER5_IRQn = 73, /*!< TIMER5 global interrupt */ + TIMER6_IRQn = 74, /*!< TIMER6 global interrupt */ + DMA1_Channel0_IRQn = 75, /*!< DMA1 channel0 global interrupt */ + DMA1_Channel1_IRQn = 76, /*!< DMA1 channel1 global interrupt */ + DMA1_Channel2_IRQn = 77, /*!< DMA1 channel2 global interrupt */ + DMA1_Channel3_IRQn = 78, /*!< DMA1 channel3 global interrupt */ + DMA1_Channel4_IRQn = 79, /*!< DMA1 channel3 global interrupt */ + + CAN1_TX_IRQn = 82, /*!< CAN1 TX interrupt */ + CAN1_RX0_IRQn = 83, /*!< CAN1 RX0 interrupt */ + CAN1_RX1_IRQn = 84, /*!< CAN1 RX1 interrupt */ + CAN1_EWMC_IRQn = 85, /*!< CAN1 EWMC interrupt */ + USBFS_IRQn = 86, /*!< USBFS global interrupt */ + + ECLIC_NUM_INTERRUPTS +} IRQn_Type; + +/* includes */ +#include + +/* bit operations */ +#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) +#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) +#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) +#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) +#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) +#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) +#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i))) + +/* main flash and SRAM memory map */ +#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ +#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */ +#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */ +#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */ +#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */ + +/* peripheral memory map */ +#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ +#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ +#define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */ +#define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */ + +/* advanced peripheral bus 1 memory map */ +#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ +#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ +#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ +#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ +#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ +#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ +#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ +#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */ +#define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */ +#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ +#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */ + +/* advanced peripheral bus 2 memory map */ +#define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */ +#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */ +#define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */ +#define GPIOA_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIOA base address */ +#define GPIOB_BASE (APB2_BUS_BASE + 0x00000C00U) /*!< GPIOA base address */ +#define GPIOC_BASE (APB2_BUS_BASE + 0x00001000U) /*!< GPIOA base address */ +#define GPIOD_BASE (APB2_BUS_BASE + 0x00001400U) /*!< GPIOA base address */ +#define GPIOE_BASE (APB2_BUS_BASE + 0x00001800U) /*!< GPIOA base address */ +#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */ + +/* advanced high performance bus 1 memory map */ +#define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */ +#define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */ +#define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */ +#define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */ +#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */ + +#ifdef cplusplus +} +#endif +#endif diff --git a/cpu/gd32v/include/vendor/gd32vf103_adc.h b/cpu/gd32v/include/vendor/gd32vf103_adc.h new file mode 100644 index 0000000000..f06da0a848 --- /dev/null +++ b/cpu/gd32v/include/vendor/gd32vf103_adc.h @@ -0,0 +1,396 @@ +/*! + \file gd32vf103_adc.h + \brief definitions for the ADC + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_ADC_H +#define GD32VF103_ADC_H + +#include "gd32vf103.h" + +/* ADC definitions */ +#define ADC0 ADC_BASE +#define ADC1 (ADC_BASE + 0x400U) + +/* registers definitions */ +#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */ +#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */ +#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */ +#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */ +#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */ +#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */ +#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */ +#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */ +#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */ +#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */ +#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */ +#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */ +#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */ +#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */ +#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */ +#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */ +#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */ +#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */ +#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */ +#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */ +#define ADC_OVSCR(adcx) REG32((adcx) + 0x80U) /*!< ADC oversample control register */ + +/* bits definitions */ +/* ADC_STAT */ +#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ +#define ADC_STAT_EOC BIT(1) /*!< end of conversion */ +#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */ +#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ +#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ + +/* ADC_CTL0 */ +#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ +#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ +#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ +#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ +#define ADC_CTL0_SM BIT(8) /*!< scan mode */ +#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ +#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ +#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ +#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ +#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ +#define ADC_CTL0_SYNCM BITS(16,19) /*!< sync mode selection */ +#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ +#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ + +/* ADC_CTL1 */ +#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ +#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ +#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ +#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ +#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ +#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ +#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */ +#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ +#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */ +#define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */ +#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ +#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ +#define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */ + +/* ADC_SAMPTx x=0..1 */ +#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n sample time selection */ + +/* ADC_IOFFx x=0..3 */ +#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ + +/* ADC_WDHT */ +#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ + +/* ADC_WDLT */ +#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ + +/* ADC_RSQx x=0..2 */ +#define ADC_RSQX_RSQN BITS(0,4) /*!< nth conversion in regular sequence */ +#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ + +/* ADC_ISQ */ +#define ADC_ISQ_ISQN BITS(0,4) /*!< nth conversion in inserted sequence */ +#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ + +/* ADC_IDATAx x=0..3*/ +#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data n */ + +/* ADC_RDATA */ +#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */ +#define ADC_RDATA_ADC1RDTR BITS(16,31) /*!< ADC1 regular channel data */ + +/* ADC_OVSCR */ +#define ADC_OVSCR_OVSEN BIT(0) /*!< oversampling enable */ +#define ADC_OVSCR_OVSR BITS(2,4) /*!< oversampling ratio */ +#define ADC_OVSCR_OVSS BITS(5,8) /*!< oversampling shift */ +#define ADC_OVSCR_TOVS BIT(9) /*!< triggered oversampling */ +#define ADC_OVSCR_DRES BITS(12,13) /*!< ADC data resolution */ + +/* constants definitions */ +/* adc_stat register value */ +#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ +#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ +#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */ +#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ +#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ + +/* adc_ctl0 register value */ +#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ + +/* scan mode */ +#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ + +/* inserted channel group convert automatically */ +#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ + +/* ADC sync mode */ +#define CTL0_SYNCM(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ +#define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */ +#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */ +#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */ +#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(3) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode */ +#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(4) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode */ +#define ADC_DAUL_INSERTED_PARALLEL CTL0_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode only */ +#define ADC_DAUL_REGULAL_PARALLEL CTL0_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode only */ +#define ADC_DAUL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up fast mode only */ +#define ADC_DAUL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(8) /*!< ADC0 and ADC1 work in follow-up slow mode only */ +#define ADC_DAUL_INSERTED_TRIGGER_ROTATION CTL0_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode only */ + +/* adc_ctl1 register value */ +#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ +#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ + +/* continuous mode */ +#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ + +/* external trigger select for regular channel */ +#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */ +/* for ADC0 and ADC1 regular channel */ +#define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */ +#define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */ +#define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */ +#define ADC0_1_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< TIMER1 CH1 event select */ +#define ADC0_1_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */ +#define ADC0_1_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(5) /*!< TIMER3 CH3 event select */ +#define ADC0_1_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */ +#define ADC0_1_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */ + +/* external trigger mode for inserted channel */ +#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ +/* for ADC0 and ADC1 inserted channel */ +#define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */ +#define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */ +#define ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< TIMER1 TRGO event select */ +#define ADC0_1_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< TIMER1 CH0 event select */ +#define ADC0_1_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */ +#define ADC0_1_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(5) /*!< TIMER3 TRGO event select */ +#define ADC0_1_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */ +#define ADC0_1_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */ + +/* adc_samptx register value */ +#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ +#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */ +#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ +#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ +#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */ +#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */ +#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */ +#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */ +#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ + +/* adc_ioffx register value */ +#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ + +/* adc_wdht register value */ +#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ + +/* adc_wdlt register value */ +#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ + +/* adc_rsqx register value */ +#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ + +/* adc_isq register value */ +#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ + +/* ADC channel group definitions */ +#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */ +#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */ +#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ + +#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ + +/* ADC inserted channel definitions */ +#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */ +#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */ +#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */ +#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */ + +/* ADC channel definitions */ +#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ +#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ +#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ +#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ +#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ +#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ +#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ +#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ +#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ +#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ +#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ +#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ +#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ +#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ +#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ +#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ +#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ +#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ + +/* ADC interrupt */ +#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ +#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ +#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ + +/* ADC interrupt flag */ +#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */ +#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */ +#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */ + +/* ADC resolution definitions */ +#define OVSCR_DRES(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) +#define ADC_RESOLUTION_12B OVSCR_DRES(0) /*!< 12-bit ADC resolution */ +#define ADC_RESOLUTION_10B OVSCR_DRES(1) /*!< 10-bit ADC resolution */ +#define ADC_RESOLUTION_8B OVSCR_DRES(2) /*!< 8-bit ADC resolution */ +#define ADC_RESOLUTION_6B OVSCR_DRES(3) /*!< 6-bit ADC resolution */ + +/* ADC oversampling mode */ +#define ADC_OVERSAMPLING_ALL_CONVERT 0 /*!< all oversampled conversions for a channel are done consecutively after a trigger */ +#define ADC_OVERSAMPLING_ONE_CONVERT 1 /*!< each oversampled conversion for a channel needs a trigger */ + +/* ADC oversampling shift */ +#define OVSCR_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) +#define ADC_OVERSAMPLING_SHIFT_NONE OVSCR_OVSS(0) /*!< no oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_1B OVSCR_OVSS(1) /*!< 1-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_2B OVSCR_OVSS(2) /*!< 2-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_3B OVSCR_OVSS(3) /*!< 3-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_4B OVSCR_OVSS(4) /*!< 4-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_5B OVSCR_OVSS(5) /*!< 5-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_6B OVSCR_OVSS(6) /*!< 6-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_7B OVSCR_OVSS(7) /*!< 7-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_8B OVSCR_OVSS(8) /*!< 8-bit oversampling shift */ + +/* ADC oversampling ratio */ +#define OVSCR_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) +#define ADC_OVERSAMPLING_RATIO_MUL2 OVSCR_OVSR(0) /*!< oversampling ratio X2 */ +#define ADC_OVERSAMPLING_RATIO_MUL4 OVSCR_OVSR(1) /*!< oversampling ratio X4 */ +#define ADC_OVERSAMPLING_RATIO_MUL8 OVSCR_OVSR(2) /*!< oversampling ratio X8 */ +#define ADC_OVERSAMPLING_RATIO_MUL16 OVSCR_OVSR(3) /*!< oversampling ratio X16 */ +#define ADC_OVERSAMPLING_RATIO_MUL32 OVSCR_OVSR(4) /*!< oversampling ratio X32 */ +#define ADC_OVERSAMPLING_RATIO_MUL64 OVSCR_OVSR(5) /*!< oversampling ratio X64 */ +#define ADC_OVERSAMPLING_RATIO_MUL128 OVSCR_OVSR(6) /*!< oversampling ratio X128 */ +#define ADC_OVERSAMPLING_RATIO_MUL256 OVSCR_OVSR(7) /*!< oversampling ratio X256 */ + +/* function declarations */ +/* initialization config */ +/* reset ADC */ +void adc_deinit(uint32_t adc_periph); +/* configure the ADC sync mode */ +void adc_mode_config(uint32_t mode); +/* enable or disable ADC special function */ +void adc_special_function_config(uint32_t adc_periph, uint32_t function, ControlStatus newvalue); +/* configure ADC data alignment */ +void adc_data_alignment_config(uint32_t adc_periph, uint32_t data_alignment); +/* enable ADC interface */ +void adc_enable(uint32_t adc_periph); +/* disable ADC interface */ +void adc_disable(uint32_t adc_periph); +/* ADC calibration and reset calibration */ +void adc_calibration_enable(uint32_t adc_periph); +/* enable the temperature sensor and Vrefint channel */ +void adc_tempsensor_vrefint_enable(void); +/* disable the temperature sensor and Vrefint channel */ +void adc_tempsensor_vrefint_disable(void); + +/* DMA config */ +/* enable DMA request */ +void adc_dma_mode_enable(uint32_t adc_periph); +/* disable DMA request */ +void adc_dma_mode_disable(uint32_t adc_periph); + +/* regular group and inserted group config */ +/* configure ADC discontinuous mode */ +void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length); + +/* configure the length of regular channel group or inserted channel group */ +void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length); +/* configure ADC regular channel */ +void adc_regular_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time); +/* configure ADC inserted channel */ +void adc_inserted_channel_config(uint32_t adc_periph, uint8_t rank, uint8_t adc_channel, uint32_t sample_time); +/* configure ADC inserted channel offset */ +void adc_inserted_channel_offset_config(uint32_t adc_periph, uint8_t inserted_channel, uint16_t offset); + +/* configure ADC external trigger source */ +void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source); +/* configure ADC external trigger */ +void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue); +/* enable ADC software trigger */ +void adc_software_trigger_enable(uint32_t adc_periph, uint8_t adc_channel_group); + +/* get channel data */ +/* read ADC regular group data register */ +uint16_t adc_regular_data_read(uint32_t adc_periph); +/* read ADC inserted group data register */ +uint16_t adc_inserted_data_read(uint32_t adc_periph, uint8_t inserted_channel); +/* read the last ADC0 and ADC1 conversion result data in sync mode */ +uint32_t adc_sync_mode_convert_value_read(void); + +/* watchdog config */ +/* configure ADC analog watchdog single channel */ +void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel); +/* configure ADC analog watchdog group channel */ +void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group); +/* disable ADC analog watchdog */ +void adc_watchdog_disable(uint32_t adc_periph); +/* configure ADC analog watchdog threshold */ +void adc_watchdog_threshold_config(uint32_t adc_periph, uint16_t low_threshold, uint16_t high_threshold); + +/* interrupt & flag functions */ +/* get the ADC flag bits */ +FlagStatus adc_flag_get(uint32_t adc_periph, uint32_t adc_flag); +/* clear the ADC flag bits */ +void adc_flag_clear(uint32_t adc_periph, uint32_t adc_flag); +/* get the bit state of ADCx software start conversion */ +FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph); +/* get the bit state of ADCx software inserted channel start conversion */ +FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph); +/* get the ADC interrupt bits */ +FlagStatus adc_interrupt_flag_get(uint32_t adc_periph, uint32_t adc_interrupt); +/* clear the ADC flag */ +void adc_interrupt_flag_clear(uint32_t adc_periph, uint32_t adc_interrupt); +/* enable ADC interrupt */ +void adc_interrupt_enable(uint32_t adc_periph, uint32_t adc_interrupt); +/* disable ADC interrupt */ +void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt); + +/* ADC resolution & oversample */ +/* ADC resolution config */ +void adc_resolution_config(uint32_t adc_periph, uint32_t resolution); +/* ADC oversample mode config */ +void adc_oversample_mode_config(uint32_t adc_periph, uint8_t mode, uint16_t shift, uint8_t ratio); +/* enable ADC oversample mode */ +void adc_oversample_mode_enable(uint32_t adc_periph); +/* disable ADC oversample mode */ +void adc_oversample_mode_disable(uint32_t adc_periph); + +#endif /* GD32VF103_ADC_H */ diff --git a/cpu/gd32v/include/vendor/gd32vf103_bkp.h b/cpu/gd32v/include/vendor/gd32vf103_bkp.h new file mode 100644 index 0000000000..733d701330 --- /dev/null +++ b/cpu/gd32v/include/vendor/gd32vf103_bkp.h @@ -0,0 +1,227 @@ +/*! + \file gd32vf103_bkp.h + \brief definitions for the BKP + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_BKP_H +#define GD32VF103_BKP_H + +#include "gd32vf103.h" + +/* BKP definitions */ +#define BKP BKP_BASE /*!< BKP base address */ + +/* registers definitions */ +#define BKP_DATA0 REG16((BKP) + 0x04U) /*!< BKP data register 0 */ +#define BKP_DATA1 REG16((BKP) + 0x08U) /*!< BKP data register 1 */ +#define BKP_DATA2 REG16((BKP) + 0x0CU) /*!< BKP data register 2 */ +#define BKP_DATA3 REG16((BKP) + 0x10U) /*!< BKP data register 3 */ +#define BKP_DATA4 REG16((BKP) + 0x14U) /*!< BKP data register 4 */ +#define BKP_DATA5 REG16((BKP) + 0x18U) /*!< BKP data register 5 */ +#define BKP_DATA6 REG16((BKP) + 0x1CU) /*!< BKP data register 6 */ +#define BKP_DATA7 REG16((BKP) + 0x20U) /*!< BKP data register 7 */ +#define BKP_DATA8 REG16((BKP) + 0x24U) /*!< BKP data register 8 */ +#define BKP_DATA9 REG16((BKP) + 0x28U) /*!< BKP data register 9 */ +#define BKP_DATA10 REG16((BKP) + 0x40U) /*!< BKP data register 10 */ +#define BKP_DATA11 REG16((BKP) + 0x44U) /*!< BKP data register 11 */ +#define BKP_DATA12 REG16((BKP) + 0x48U) /*!< BKP data register 12 */ +#define BKP_DATA13 REG16((BKP) + 0x4CU) /*!< BKP data register 13 */ +#define BKP_DATA14 REG16((BKP) + 0x50U) /*!< BKP data register 14 */ +#define BKP_DATA15 REG16((BKP) + 0x54U) /*!< BKP data register 15 */ +#define BKP_DATA16 REG16((BKP) + 0x58U) /*!< BKP data register 16 */ +#define BKP_DATA17 REG16((BKP) + 0x5CU) /*!< BKP data register 17 */ +#define BKP_DATA18 REG16((BKP) + 0x60U) /*!< BKP data register 18 */ +#define BKP_DATA19 REG16((BKP) + 0x64U) /*!< BKP data register 19 */ +#define BKP_DATA20 REG16((BKP) + 0x68U) /*!< BKP data register 20 */ +#define BKP_DATA21 REG16((BKP) + 0x6CU) /*!< BKP data register 21 */ +#define BKP_DATA22 REG16((BKP) + 0x70U) /*!< BKP data register 22 */ +#define BKP_DATA23 REG16((BKP) + 0x74U) /*!< BKP data register 23 */ +#define BKP_DATA24 REG16((BKP) + 0x78U) /*!< BKP data register 24 */ +#define BKP_DATA25 REG16((BKP) + 0x7CU) /*!< BKP data register 25 */ +#define BKP_DATA26 REG16((BKP) + 0x80U) /*!< BKP data register 26 */ +#define BKP_DATA27 REG16((BKP) + 0x84U) /*!< BKP data register 27 */ +#define BKP_DATA28 REG16((BKP) + 0x88U) /*!< BKP data register 28 */ +#define BKP_DATA29 REG16((BKP) + 0x8CU) /*!< BKP data register 29 */ +#define BKP_DATA30 REG16((BKP) + 0x90U) /*!< BKP data register 30 */ +#define BKP_DATA31 REG16((BKP) + 0x94U) /*!< BKP data register 31 */ +#define BKP_DATA32 REG16((BKP) + 0x98U) /*!< BKP data register 32 */ +#define BKP_DATA33 REG16((BKP) + 0x9CU) /*!< BKP data register 33 */ +#define BKP_DATA34 REG16((BKP) + 0xA0U) /*!< BKP data register 34 */ +#define BKP_DATA35 REG16((BKP) + 0xA4U) /*!< BKP data register 35 */ +#define BKP_DATA36 REG16((BKP) + 0xA8U) /*!< BKP data register 36 */ +#define BKP_DATA37 REG16((BKP) + 0xACU) /*!< BKP data register 37 */ +#define BKP_DATA38 REG16((BKP) + 0xB0U) /*!< BKP data register 38 */ +#define BKP_DATA39 REG16((BKP) + 0xB4U) /*!< BKP data register 39 */ +#define BKP_DATA40 REG16((BKP) + 0xB8U) /*!< BKP data register 40 */ +#define BKP_DATA41 REG16((BKP) + 0xBCU) /*!< BKP data register 41 */ +#define BKP_OCTL REG16((BKP) + 0x2CU) /*!< RTC signal output control register */ +#define BKP_TPCTL REG16((BKP) + 0x30U) /*!< tamper pin control register */ +#define BKP_TPCS REG16((BKP) + 0x34U) /*!< tamper control and status register */ + +/* bits definitions */ +/* BKP_DATA */ +#define BKP_DATA BITS(0,15) /*!< backup data */ + +/* BKP_OCTL */ +#define BKP_OCTL_RCCV BITS(0,6) /*!< RTC clock calibration value */ +#define BKP_OCTL_COEN BIT(7) /*!< RTC clock calibration output enable */ +#define BKP_OCTL_ASOEN BIT(8) /*!< RTC alarm or second signal output enable */ +#define BKP_OCTL_ROSEL BIT(9) /*!< RTC output selection */ + +/* BKP_TPCTL */ +#define BKP_TPCTL_TPEN BIT(0) /*!< tamper detection enable */ +#define BKP_TPCTL_TPAL BIT(1) /*!< tamper pin active level */ + +/* BKP_TPCS */ +#define BKP_TPCS_TER BIT(0) /*!< tamper event reset */ +#define BKP_TPCS_TIR BIT(1) /*!< tamper interrupt reset */ +#define BKP_TPCS_TPIE BIT(2) /*!< tamper interrupt enable */ +#define BKP_TPCS_TEF BIT(8) /*!< tamper event flag */ +#define BKP_TPCS_TIF BIT(9) /*!< tamper interrupt flag */ + +/* constants definitions */ +/* BKP data register number */ +typedef enum +{ + BKP_DATA_0 = 1, /*!< BKP data register 0 */ + BKP_DATA_1, /*!< BKP data register 1 */ + BKP_DATA_2, /*!< BKP data register 2 */ + BKP_DATA_3, /*!< BKP data register 3 */ + BKP_DATA_4, /*!< BKP data register 4 */ + BKP_DATA_5, /*!< BKP data register 5 */ + BKP_DATA_6, /*!< BKP data register 6 */ + BKP_DATA_7, /*!< BKP data register 7 */ + BKP_DATA_8, /*!< BKP data register 8 */ + BKP_DATA_9, /*!< BKP data register 9 */ + BKP_DATA_10, /*!< BKP data register 10 */ + BKP_DATA_11, /*!< BKP data register 11 */ + BKP_DATA_12, /*!< BKP data register 12 */ + BKP_DATA_13, /*!< BKP data register 13 */ + BKP_DATA_14, /*!< BKP data register 14 */ + BKP_DATA_15, /*!< BKP data register 15 */ + BKP_DATA_16, /*!< BKP data register 16 */ + BKP_DATA_17, /*!< BKP data register 17 */ + BKP_DATA_18, /*!< BKP data register 18 */ + BKP_DATA_19, /*!< BKP data register 19 */ + BKP_DATA_20, /*!< BKP data register 20 */ + BKP_DATA_21, /*!< BKP data register 21 */ + BKP_DATA_22, /*!< BKP data register 22 */ + BKP_DATA_23, /*!< BKP data register 23 */ + BKP_DATA_24, /*!< BKP data register 24 */ + BKP_DATA_25, /*!< BKP data register 25 */ + BKP_DATA_26, /*!< BKP data register 26 */ + BKP_DATA_27, /*!< BKP data register 27 */ + BKP_DATA_28, /*!< BKP data register 28 */ + BKP_DATA_29, /*!< BKP data register 29 */ + BKP_DATA_30, /*!< BKP data register 30 */ + BKP_DATA_31, /*!< BKP data register 31 */ + BKP_DATA_32, /*!< BKP data register 32 */ + BKP_DATA_33, /*!< BKP data register 33 */ + BKP_DATA_34, /*!< BKP data register 34 */ + BKP_DATA_35, /*!< BKP data register 35 */ + BKP_DATA_36, /*!< BKP data register 36 */ + BKP_DATA_37, /*!< BKP data register 37 */ + BKP_DATA_38, /*!< BKP data register 38 */ + BKP_DATA_39, /*!< BKP data register 39 */ + BKP_DATA_40, /*!< BKP data register 40 */ + BKP_DATA_41, /*!< BKP data register 41 */ +}bkp_data_register_enum; + +/* BKP register */ +#define BKP_DATA0_9(number) REG16((BKP) + 0x04U + (number) * 0x04U) +#define BKP_DATA10_41(number) REG16((BKP) + 0x40U + ((number)-10U) * 0x04U) + +/* get data of BKP data register */ +#define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15) + +/* RTC clock calibration value */ +#define OCTL_RCCV(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) + +/* RTC output selection */ +#define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U) /*!< RTC alarm pulse is selected as the RTC output */ +#define RTC_OUTPUT_SECOND_PULSE ((uint16_t)0x0200U) /*!< RTC second pulse is selected as the RTC output */ + +/* tamper pin active level */ +#define TAMPER_PIN_ACTIVE_HIGH ((uint16_t)0x0000U) /*!< the tamper pin is active high */ +#define TAMPER_PIN_ACTIVE_LOW ((uint16_t)0x0002U) /*!< the tamper pin is active low */ + +/* tamper flag */ +#define BKP_FLAG_TAMPER BKP_TPCS_TEF /*!< tamper event flag */ + +/* tamper interrupt flag */ +#define BKP_INT_FLAG_TAMPER BKP_TPCS_TIF /*!< tamper interrupt flag */ + +/* function declarations */ +/* reset BKP registers */ +void bkp_deinit(void); +/* write BKP data register */ +void bkp_data_write(bkp_data_register_enum register_number, uint16_t data); +/* read BKP data register */ +uint16_t bkp_data_read(bkp_data_register_enum register_number); + +/* RTC related functions */ +/* enable RTC clock calibration output */ +void bkp_rtc_calibration_output_enable(void); +/* disable RTC clock calibration output */ +void bkp_rtc_calibration_output_disable(void); +/* enable RTC alarm or second signal output */ +void bkp_rtc_signal_output_enable(void); +/* disable RTC alarm or second signal output */ +void bkp_rtc_signal_output_disable(void); +/* select RTC output */ +void bkp_rtc_output_select(uint16_t outputsel); +/* set RTC clock calibration value */ +void bkp_rtc_calibration_value_set(uint8_t value); + +/* tamper pin related functions */ +/* enable tamper pin detection */ +void bkp_tamper_detection_enable(void); +/* disable tamper pin detection */ +void bkp_tamper_detection_disable(void); +/* set tamper pin active level */ +void bkp_tamper_active_level_set(uint16_t level); + +/* interrupt & flag functions */ +/* enable tamper interrupt */ +void bkp_interrupt_enable(void); +/* disable tamper interrupt */ +void bkp_interrupt_disable(void); +/* get tamper flag state */ +FlagStatus bkp_flag_get(void); +/* clear tamper flag state */ +void bkp_flag_clear(void); +/* get tamper interrupt flag state */ +FlagStatus bkp_interrupt_flag_get(void); +/* clear tamper interrupt flag state */ +void bkp_interrupt_flag_clear(void); + +#endif /* GD32VF103_BKP_H */ diff --git a/cpu/gd32v/include/vendor/gd32vf103_can.h b/cpu/gd32v/include/vendor/gd32vf103_can.h new file mode 100644 index 0000000000..38d30683e4 --- /dev/null +++ b/cpu/gd32v/include/vendor/gd32vf103_can.h @@ -0,0 +1,751 @@ +/*! + \file gd32vf103_can.h + \brief definitions for the CAN + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + \version 2019-11-27, V1.0.1, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_CAN_H +#define GD32VF103_CAN_H + +#include "gd32vf103.h" + +/* CAN definitions */ +#define CAN0 CAN_BASE /*!< CAN0 base address */ +#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */ + +/* registers definitions */ +#define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register */ +#define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */ +#define CAN_TSTAT(canx) REG32((canx) + 0x08U) /*!< CAN transmit status register*/ +#define CAN_RFIFO0(canx) REG32((canx) + 0x0CU) /*!< CAN receive FIFO0 register */ +#define CAN_RFIFO1(canx) REG32((canx) + 0x10U) /*!< CAN receive FIFO1 register */ +#define CAN_INTEN(canx) REG32((canx) + 0x14U) /*!< CAN interrupt enable register */ +#define CAN_ERR(canx) REG32((canx) + 0x18U) /*!< CAN error register */ +#define CAN_BT(canx) REG32((canx) + 0x1CU) /*!< CAN bit timing register */ +#define CAN_TMI0(canx) REG32((canx) + 0x180U) /*!< CAN transmit mailbox0 identifier register */ +#define CAN_TMP0(canx) REG32((canx) + 0x184U) /*!< CAN transmit mailbox0 property register */ +#define CAN_TMDATA00(canx) REG32((canx) + 0x188U) /*!< CAN transmit mailbox0 data0 register */ +#define CAN_TMDATA10(canx) REG32((canx) + 0x18CU) /*!< CAN transmit mailbox0 data1 register */ +#define CAN_TMI1(canx) REG32((canx) + 0x190U) /*!< CAN transmit mailbox1 identifier register */ +#define CAN_TMP1(canx) REG32((canx) + 0x194U) /*!< CAN transmit mailbox1 property register */ +#define CAN_TMDATA01(canx) REG32((canx) + 0x198U) /*!< CAN transmit mailbox1 data0 register */ +#define CAN_TMDATA11(canx) REG32((canx) + 0x19CU) /*!< CAN transmit mailbox1 data1 register */ +#define CAN_TMI2(canx) REG32((canx) + 0x1A0U) /*!< CAN transmit mailbox2 identifier register */ +#define CAN_TMP2(canx) REG32((canx) + 0x1A4U) /*!< CAN transmit mailbox2 property register */ +#define CAN_TMDATA02(canx) REG32((canx) + 0x1A8U) /*!< CAN transmit mailbox2 data0 register */ +#define CAN_TMDATA12(canx) REG32((canx) + 0x1ACU) /*!< CAN transmit mailbox2 data1 register */ +#define CAN_RFIFOMI0(canx) REG32((canx) + 0x1B0U) /*!< CAN receive FIFO0 mailbox identifier register */ +#define CAN_RFIFOMP0(canx) REG32((canx) + 0x1B4U) /*!< CAN receive FIFO0 mailbox property register */ +#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x1B8U) /*!< CAN receive FIFO0 mailbox data0 register */ +#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1BCU) /*!< CAN receive FIFO0 mailbox data1 register */ +#define CAN_RFIFOMI1(canx) REG32((canx) + 0x1C0U) /*!< CAN receive FIFO1 mailbox identifier register */ +#define CAN_RFIFOMP1(canx) REG32((canx) + 0x1C4U) /*!< CAN receive FIFO1 mailbox property register */ +#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x1C8U) /*!< CAN receive FIFO1 mailbox data0 register */ +#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO1 mailbox data1 register */ +#define CAN_FCTL(canx) REG32((canx) + 0x200U) /*!< CAN filter control register */ +#define CAN_FMCFG(canx) REG32((canx) + 0x204U) /*!< CAN filter mode register */ +#define CAN_FSCFG(canx) REG32((canx) + 0x20CU) /*!< CAN filter scale register */ +#define CAN_FAFIFO(canx) REG32((canx) + 0x214U) /*!< CAN filter associated FIFO register */ +#define CAN_FW(canx) REG32((canx) + 0x21CU) /*!< CAN filter working register */ +#define CAN_F0DATA0(canx) REG32((canx) + 0x240U) /*!< CAN filter 0 data 0 register */ +#define CAN_F1DATA0(canx) REG32((canx) + 0x248U) /*!< CAN filter 1 data 0 register */ +#define CAN_F2DATA0(canx) REG32((canx) + 0x250U) /*!< CAN filter 2 data 0 register */ +#define CAN_F3DATA0(canx) REG32((canx) + 0x258U) /*!< CAN filter 3 data 0 register */ +#define CAN_F4DATA0(canx) REG32((canx) + 0x260U) /*!< CAN filter 4 data 0 register */ +#define CAN_F5DATA0(canx) REG32((canx) + 0x268U) /*!< CAN filter 5 data 0 register */ +#define CAN_F6DATA0(canx) REG32((canx) + 0x270U) /*!< CAN filter 6 data 0 register */ +#define CAN_F7DATA0(canx) REG32((canx) + 0x278U) /*!< CAN filter 7 data 0 register */ +#define CAN_F8DATA0(canx) REG32((canx) + 0x280U) /*!< CAN filter 8 data 0 register */ +#define CAN_F9DATA0(canx) REG32((canx) + 0x288U) /*!< CAN filter 9 data 0 register */ +#define CAN_F10DATA0(canx) REG32((canx) + 0x290U) /*!< CAN filter 10 data 0 register */ +#define CAN_F11DATA0(canx) REG32((canx) + 0x298U) /*!< CAN filter 11 data 0 register */ +#define CAN_F12DATA0(canx) REG32((canx) + 0x2A0U) /*!< CAN filter 12 data 0 register */ +#define CAN_F13DATA0(canx) REG32((canx) + 0x2A8U) /*!< CAN filter 13 data 0 register */ +#define CAN_F14DATA0(canx) REG32((canx) + 0x2B0U) /*!< CAN filter 14 data 0 register */ +#define CAN_F15DATA0(canx) REG32((canx) + 0x2B8U) /*!< CAN filter 15 data 0 register */ +#define CAN_F16DATA0(canx) REG32((canx) + 0x2C0U) /*!< CAN filter 16 data 0 register */ +#define CAN_F17DATA0(canx) REG32((canx) + 0x2C8U) /*!< CAN filter 17 data 0 register */ +#define CAN_F18DATA0(canx) REG32((canx) + 0x2D0U) /*!< CAN filter 18 data 0 register */ +#define CAN_F19DATA0(canx) REG32((canx) + 0x2D8U) /*!< CAN filter 19 data 0 register */ +#define CAN_F20DATA0(canx) REG32((canx) + 0x2E0U) /*!< CAN filter 20 data 0 register */ +#define CAN_F21DATA0(canx) REG32((canx) + 0x2E8U) /*!< CAN filter 21 data 0 register */ +#define CAN_F22DATA0(canx) REG32((canx) + 0x2F0U) /*!< CAN filter 22 data 0 register */ +#define CAN_F23DATA0(canx) REG32((canx) + 0x3F8U) /*!< CAN filter 23 data 0 register */ +#define CAN_F24DATA0(canx) REG32((canx) + 0x300U) /*!< CAN filter 24 data 0 register */ +#define CAN_F25DATA0(canx) REG32((canx) + 0x308U) /*!< CAN filter 25 data 0 register */ +#define CAN_F26DATA0(canx) REG32((canx) + 0x310U) /*!< CAN filter 26 data 0 register */ +#define CAN_F27DATA0(canx) REG32((canx) + 0x318U) /*!< CAN filter 27 data 0 register */ +#define CAN_F0DATA1(canx) REG32((canx) + 0x244U) /*!< CAN filter 0 data 1 register */ +#define CAN_F1DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 1 data 1 register */ +#define CAN_F2DATA1(canx) REG32((canx) + 0x254U) /*!< CAN filter 2 data 1 register */ +#define CAN_F3DATA1(canx) REG32((canx) + 0x25CU) /*!< CAN filter 3 data 1 register */ +#define CAN_F4DATA1(canx) REG32((canx) + 0x264U) /*!< CAN filter 4 data 1 register */ +#define CAN_F5DATA1(canx) REG32((canx) + 0x26CU) /*!< CAN filter 5 data 1 register */ +#define CAN_F6DATA1(canx) REG32((canx) + 0x274U) /*!< CAN filter 6 data 1 register */ +#define CAN_F7DATA1(canx) REG32((canx) + 0x27CU) /*!< CAN filter 7 data 1 register */ +#define CAN_F8DATA1(canx) REG32((canx) + 0x284U) /*!< CAN filter 8 data 1 register */ +#define CAN_F9DATA1(canx) REG32((canx) + 0x28CU) /*!< CAN filter 9 data 1 register */ +#define CAN_F10DATA1(canx) REG32((canx) + 0x294U) /*!< CAN filter 10 data 1 register */ +#define CAN_F11DATA1(canx) REG32((canx) + 0x29CU) /*!< CAN filter 11 data 1 register */ +#define CAN_F12DATA1(canx) REG32((canx) + 0x2A4U) /*!< CAN filter 12 data 1 register */ +#define CAN_F13DATA1(canx) REG32((canx) + 0x2ACU) /*!< CAN filter 13 data 1 register */ +#define CAN_F14DATA1(canx) REG32((canx) + 0x2B4U) /*!< CAN filter 14 data 1 register */ +#define CAN_F15DATA1(canx) REG32((canx) + 0x2BCU) /*!< CAN filter 15 data 1 register */ +#define CAN_F16DATA1(canx) REG32((canx) + 0x2C4U) /*!< CAN filter 16 data 1 register */ +#define CAN_F17DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 17 data 1 register */ +#define CAN_F18DATA1(canx) REG32((canx) + 0x2D4U) /*!< CAN filter 18 data 1 register */ +#define CAN_F19DATA1(canx) REG32((canx) + 0x2DCU) /*!< CAN filter 19 data 1 register */ +#define CAN_F20DATA1(canx) REG32((canx) + 0x2E4U) /*!< CAN filter 20 data 1 register */ +#define CAN_F21DATA1(canx) REG32((canx) + 0x2ECU) /*!< CAN filter 21 data 1 register */ +#define CAN_F22DATA1(canx) REG32((canx) + 0x2F4U) /*!< CAN filter 22 data 1 register */ +#define CAN_F23DATA1(canx) REG32((canx) + 0x2FCU) /*!< CAN filter 23 data 1 register */ +#define CAN_F24DATA1(canx) REG32((canx) + 0x304U) /*!< CAN filter 24 data 1 register */ +#define CAN_F25DATA1(canx) REG32((canx) + 0x30CU) /*!< CAN filter 25 data 1 register */ +#define CAN_F26DATA1(canx) REG32((canx) + 0x314U) /*!< CAN filter 26 data 1 register */ +#define CAN_F27DATA1(canx) REG32((canx) + 0x31CU) /*!< CAN filter 27 data 1 register */ + +/* CAN transmit mailbox bank */ +#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */ +#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */ +#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */ +#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */ + +/* CAN filter bank */ +#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */ +#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */ + +/* CAN receive fifo mailbox bank */ +#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */ +#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */ +#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */ +#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */ + +/* bits definitions */ +/* CAN_CTL */ +#define CAN_CTL_IWMOD BIT(0) /*!< initial working mode */ +#define CAN_CTL_SLPWMOD BIT(1) /*!< sleep working mode */ +#define CAN_CTL_TFO BIT(2) /*!< transmit FIFO order */ +#define CAN_CTL_RFOD BIT(3) /*!< receive FIFO overwrite disable */ +#define CAN_CTL_ARD BIT(4) /*!< automatic retransmission disable */ +#define CAN_CTL_AWU BIT(5) /*!< automatic wakeup */ +#define CAN_CTL_ABOR BIT(6) /*!< automatic bus-off recovery */ +#define CAN_CTL_TTC BIT(7) /*!< time triggered communication */ +#define CAN_CTL_SWRST BIT(15) /*!< CAN software reset */ +#define CAN_CTL_DFZ BIT(16) /*!< CAN debug freeze */ + +/* CAN_STAT */ +#define CAN_STAT_IWS BIT(0) /*!< initial working state */ +#define CAN_STAT_SLPWS BIT(1) /*!< sleep working state */ +#define CAN_STAT_ERRIF BIT(2) /*!< error interrupt flag*/ +#define CAN_STAT_WUIF BIT(3) /*!< status change interrupt flag of wakeup from sleep working mode */ +#define CAN_STAT_SLPIF BIT(4) /*!< status change interrupt flag of sleep working mode entering */ +#define CAN_STAT_TS BIT(8) /*!< transmitting state */ +#define CAN_STAT_RS BIT(9) /*!< receiving state */ +#define CAN_STAT_LASTRX BIT(10) /*!< last sample value of rx pin */ +#define CAN_STAT_RXL BIT(11) /*!< CAN rx signal */ + +/* CAN_TSTAT */ +#define CAN_TSTAT_MTF0 BIT(0) /*!< mailbox0 transmit finished */ +#define CAN_TSTAT_MTFNERR0 BIT(1) /*!< mailbox0 transmit finished and no error */ +#define CAN_TSTAT_MAL0 BIT(2) /*!< mailbox0 arbitration lost */ +#define CAN_TSTAT_MTE0 BIT(3) /*!< mailbox0 transmit error */ +#define CAN_TSTAT_MST0 BIT(7) /*!< mailbox0 stop transmitting */ +#define CAN_TSTAT_MTF1 BIT(8) /*!< mailbox1 transmit finished */ +#define CAN_TSTAT_MTFNERR1 BIT(9) /*!< mailbox1 transmit finished and no error */ +#define CAN_TSTAT_MAL1 BIT(10) /*!< mailbox1 arbitration lost */ +#define CAN_TSTAT_MTE1 BIT(11) /*!< mailbox1 transmit error */ +#define CAN_TSTAT_MST1 BIT(15) /*!< mailbox1 stop transmitting */ +#define CAN_TSTAT_MTF2 BIT(16) /*!< mailbox2 transmit finished */ +#define CAN_TSTAT_MTFNERR2 BIT(17) /*!< mailbox2 transmit finished and no error */ +#define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */ +#define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */ +#define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */ +#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */ +#define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */ +#define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */ +#define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */ +#define CAN_TSTAT_TMLS0 BIT(29) /*!< last sending priority flag for mailbox0 */ +#define CAN_TSTAT_TMLS1 BIT(30) /*!< last sending priority flag for mailbox1 */ +#define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */ + +/* CAN_RFIFO0 */ +#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */ +#define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */ +#define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */ +#define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */ + +/* CAN_RFIFO1 */ +#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */ +#define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */ +#define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */ +#define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */ + +/* CAN_INTEN */ +#define CAN_INTEN_TMEIE BIT(0) /*!< transmit mailbox empty interrupt enable */ +#define CAN_INTEN_RFNEIE0 BIT(1) /*!< receive FIFO0 not empty interrupt enable */ +#define CAN_INTEN_RFFIE0 BIT(2) /*!< receive FIFO0 full interrupt enable */ +#define CAN_INTEN_RFOIE0 BIT(3) /*!< receive FIFO0 overfull interrupt enable */ +#define CAN_INTEN_RFNEIE1 BIT(4) /*!< receive FIFO1 not empty interrupt enable */ +#define CAN_INTEN_RFFIE1 BIT(5) /*!< receive FIFO1 full interrupt enable */ +#define CAN_INTEN_RFOIE1 BIT(6) /*!< receive FIFO1 overfull interrupt enable */ +#define CAN_INTEN_WERRIE BIT(8) /*!< warning error interrupt enable */ +#define CAN_INTEN_PERRIE BIT(9) /*!< passive error interrupt enable */ +#define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */ +#define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */ +#define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */ +#define CAN_INTEN_WIE BIT(16) /*!< wakeup interrupt enable */ +#define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */ + +/* CAN_ERR */ +#define CAN_ERR_WERR BIT(0) /*!< warning error */ +#define CAN_ERR_PERR BIT(1) /*!< passive error */ +#define CAN_ERR_BOERR BIT(2) /*!< bus-off error */ +#define CAN_ERR_ERRN BITS(4,6) /*!< error number */ +#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */ +#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */ + +/* CAN_BT */ +#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */ +#define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */ +#define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */ +#define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */ +#define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */ +#define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */ + +/* CAN_TMIx */ +#define CAN_TMI_TEN BIT(0) /*!< transmit enable */ +#define CAN_TMI_FT BIT(1) /*!< frame type */ +#define CAN_TMI_FF BIT(2) /*!< frame format */ +#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */ +#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */ + +/* CAN_TMPx */ +#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */ +#define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */ +#define CAN_TMP_TS BITS(16,31) /*!< time stamp */ + +/* CAN_TMDATA0x */ +#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */ +#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */ +#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */ +#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */ + +/* CAN_TMDATA1x */ +#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */ +#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */ +#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */ +#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */ + +/* CAN_RFIFOMIx */ +#define CAN_RFIFOMI_FT BIT(1) /*!< frame type */ +#define CAN_RFIFOMI_FF BIT(2) /*!< frame format */ +#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */ +#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */ + +/* CAN_RFIFOMPx */ +#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */ +#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */ +#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */ + +/* CAN_RFIFOMDATA0x */ +#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */ +#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */ +#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */ +#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */ + +/* CAN_RFIFOMDATA1x */ +#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */ +#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */ +#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */ +#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */ + +/* CAN_FCTL */ +#define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */ +#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ + +/* CAN_FMCFG */ +#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/ + +/* CAN_FSCFG */ +#define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits*/ + +/* CAN_FAFIFO */ +#define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */ + +/* CAN_FW */ +#define CAN_FW_FW(regval) BIT(regval) /*!< filter working */ + +/* CAN_FxDATAy */ +#define CAN_FDATA_FD(regval) BIT(regval) /*!< filter data */ + +/* consts definitions */ +/* define the CAN bit position and its register index offset */ +#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6))) +#define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU) + +#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) +#define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12))) +#define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) +#define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) + +/* register offset */ +#define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */ +#define TSTAT_REG_OFFSET ((uint8_t)0x08U) /*!< TSTAT register offset */ +#define RFIFO0_REG_OFFSET ((uint8_t)0x0CU) /*!< RFIFO0 register offset */ +#define RFIFO1_REG_OFFSET ((uint8_t)0x10U) /*!< RFIFO1 register offset */ +#define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */ + +/* CAN flags */ +typedef enum +{ + /* flags in STAT register */ + CAN_FLAG_RXL = CAN_REGIDX_BIT(STAT_REG_OFFSET, 11U), /*!< RX level */ + CAN_FLAG_LASTRX = CAN_REGIDX_BIT(STAT_REG_OFFSET, 10U), /*!< last sample value of RX pin */ + CAN_FLAG_RS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 9U), /*!< receiving state */ + CAN_FLAG_TS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 8U), /*!< transmitting state */ + CAN_FLAG_SLPIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 4U), /*!< status change flag of entering sleep working mode */ + CAN_FLAG_WUIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 3U), /*!< status change flag of wakeup from sleep working mode */ + CAN_FLAG_ERRIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 2U), /*!< error flag */ + CAN_FLAG_SLPWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 1U), /*!< sleep working state */ + CAN_FLAG_IWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 0U), /*!< initial working state */ + /* flags in TSTAT register */ + CAN_FLAG_TMLS2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 31U), /*!< transmit mailbox 2 last sending in Tx FIFO */ + CAN_FLAG_TMLS1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 30U), /*!< transmit mailbox 1 last sending in Tx FIFO */ + CAN_FLAG_TMLS0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 29U), /*!< transmit mailbox 0 last sending in Tx FIFO */ + CAN_FLAG_TME2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 28U), /*!< transmit mailbox 2 empty */ + CAN_FLAG_TME1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 27U), /*!< transmit mailbox 1 empty */ + CAN_FLAG_TME0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 26U), /*!< transmit mailbox 0 empty */ + CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ + CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ + CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */ + CAN_FLAG_MAL2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 18U), /*!< mailbox 2 arbitration lost */ + CAN_FLAG_MAL1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 10U), /*!< mailbox 1 arbitration lost */ + CAN_FLAG_MAL0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 2U), /*!< mailbox 0 arbitration lost */ + CAN_FLAG_MTFNERR2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 17U), /*!< mailbox 2 transmit finished with no error */ + CAN_FLAG_MTFNERR1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 9U), /*!< mailbox 1 transmit finished with no error */ + CAN_FLAG_MTFNERR0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 1U), /*!< mailbox 0 transmit finished with no error */ + CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */ + CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */ + CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */ + /* flags in RFIFO0 register */ + CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */ + CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */ + /* flags in RFIFO1 register */ + CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */ + CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */ + /* flags in ERR register */ + CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ + CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ + CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ +}can_flag_enum; + +/* CAN interrupt flags */ +typedef enum +{ + /* interrupt flags in STAT register */ + CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ + CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ + CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */ + /* interrupt flags in TSTAT register */ + CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */ + CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */ + CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */ + /* interrupt flags in RFIFO0 register */ + CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */ + CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */ + CAN_INT_FLAG_RFL0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 2U, 1U), /*!< receive FIFO0 not empty interrupt flag */ + /* interrupt flags in RFIFO0 register */ + CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */ + CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */ + CAN_INT_FLAG_RFL1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 2U, 4U), /*!< receive FIFO0 not empty interrupt flag */ + /* interrupt flags in ERR register */ + CAN_INT_FLAG_ERRN = CAN_REGIDX_BITS(ERR_REG_OFFSET, 3U, 11U), /*!< error number interrupt flag */ + CAN_INT_FLAG_BOERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 2U, 10U), /*!< bus-off error interrupt flag */ + CAN_INT_FLAG_PERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 1U, 9U), /*!< passive error interrupt flag */ + CAN_INT_FLAG_WERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 0U, 8U), /*!< warning error interrupt flag */ +}can_interrupt_flag_enum; + +/* CAN initiliaze parameters struct */ +typedef struct +{ + uint8_t working_mode; /*!< CAN working mode */ + uint8_t resync_jump_width; /*!< CAN resynchronization jump width */ + uint8_t time_segment_1; /*!< time segment 1 */ + uint8_t time_segment_2; /*!< time segment 2 */ + ControlStatus time_triggered; /*!< time triggered communication mode */ + ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */ + ControlStatus auto_wake_up; /*!< automatic wake-up mode */ + ControlStatus no_auto_retrans; /*!< automatic retransmission mode disable */ + ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */ + ControlStatus trans_fifo_order; /*!< transmit FIFO order */ + uint16_t prescaler; /*!< baudrate prescaler */ +}can_parameter_struct; + +/* CAN transmit message struct */ +typedef struct +{ + uint32_t tx_sfid; /*!< standard format frame identifier */ + uint32_t tx_efid; /*!< extended format frame identifier */ + uint8_t tx_ff; /*!< format of frame, standard or extended format */ + uint8_t tx_ft; /*!< type of frame, data or remote */ + uint8_t tx_dlen; /*!< data length */ + uint8_t tx_data[8]; /*!< transmit data */ +}can_trasnmit_message_struct; + +/* CAN receive message struct */ +typedef struct +{ + uint32_t rx_sfid; /*!< standard format frame identifier */ + uint32_t rx_efid; /*!< extended format frame identifier */ + uint8_t rx_ff; /*!< format of frame, standard or extended format */ + uint8_t rx_ft; /*!< type of frame, data or remote */ + uint8_t rx_dlen; /*!< data length */ + uint8_t rx_data[8]; /*!< receive data */ + uint8_t rx_fi; /*!< filtering index */ +} can_receive_message_struct; + +/* CAN filter parameters struct */ +typedef struct +{ + uint16_t filter_list_high; /*!< filter list number high bits*/ + uint16_t filter_list_low; /*!< filter list number low bits */ + uint16_t filter_mask_high; /*!< filter mask number high bits */ + uint16_t filter_mask_low; /*!< filter mask number low bits */ + uint16_t filter_fifo_number; /*!< receive FIFO associated with the filter */ + uint16_t filter_number; /*!< filter number */ + uint16_t filter_mode; /*!< filter mode, list or mask */ + uint16_t filter_bits; /*!< filter scale */ + ControlStatus filter_enable; /*!< filter work or not */ +}can_filter_parameter_struct; + +/* CAN errors */ +typedef enum +{ + CAN_ERROR_NONE = 0, /*!< no error */ + CAN_ERROR_FILL, /*!< fill error */ + CAN_ERROR_FORMATE, /*!< format error */ + CAN_ERROR_ACK, /*!< ACK error */ + CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */ + CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */ + CAN_ERROR_CRC, /*!< CRC error */ + CAN_ERROR_SOFTWARECFG, /*!< software configure */ +}can_error_enum; + +/* transmit states */ +typedef enum +{ + CAN_TRANSMIT_FAILED = 0U, /*!< CAN transmitted failure */ + CAN_TRANSMIT_OK = 1U, /*!< CAN transmitted success */ + CAN_TRANSMIT_PENDING = 2U, /*!< CAN transmitted pending */ + CAN_TRANSMIT_NOMAILBOX = 4U, /*!< no empty mailbox to be used for CAN */ +}can_transmit_state_enum; + +typedef enum +{ + CAN_INIT_STRUCT = 0, /* CAN initiliaze parameters struct */ + CAN_FILTER_STRUCT, /* CAN filter parameters struct */ + CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */ + CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */ +}can_struct_type_enum; + +/* CAN baudrate prescaler*/ +#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) + +/* CAN bit segment 1*/ +#define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) + +/* CAN bit segment 2*/ +#define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) + +/* CAN resynchronization jump width*/ +#define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) + +/* CAN communication mode*/ +#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) + +/* CAN FDATA high 16 bits */ +#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) + +/* CAN FDATA low 16 bits */ +#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) + +/* CAN1 filter start bank_number*/ +#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) + +/* CAN transmit mailbox extended identifier*/ +#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) + +/* CAN transmit mailbox standard identifier*/ +#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) + +/* transmit data byte 0 */ +#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* transmit data byte 1 */ +#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) + +/* transmit data byte 2 */ +#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) + +/* transmit data byte 3 */ +#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) + +/* transmit data byte 4 */ +#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* transmit data byte 5 */ +#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) + +/* transmit data byte 6 */ +#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) + +/* transmit data byte 7 */ +#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) + +/* receive mailbox extended identifier*/ +#define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3U, 31U) + +/* receive mailbox standrad identifier*/ +#define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21U, 31U) + +/* receive data length */ +#define GET_RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0U, 3U) + +/* the index of the filter by which the frame is passed */ +#define GET_RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8U, 15U) + +/* receive data byte 0 */ +#define GET_RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0U, 7U) + +/* receive data byte 1 */ +#define GET_RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8U, 15U) + +/* receive data byte 2 */ +#define GET_RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16U, 23U) + +/* receive data byte 3 */ +#define GET_RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24U, 31U) + +/* receive data byte 4 */ +#define GET_RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0U, 7U) + +/* receive data byte 5 */ +#define GET_RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8U, 15U) + +/* receive data byte 6 */ +#define GET_RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16U, 23U) + +/* receive data byte 7 */ +#define GET_RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24U, 31U) + +/* error number */ +#define GET_ERR_ERRN(regval) GET_BITS((uint32_t)(regval), 4U, 6U) + +/* transmit error count */ +#define GET_ERR_TECNT(regval) GET_BITS((uint32_t)(regval), 16U, 23U) + +/* receive error count */ +#define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24U, 31U) + +/* CAN errors */ +#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) +#define CAN_ERRN_0 ERR_ERRN(0U) /* no error */ +#define CAN_ERRN_1 ERR_ERRN(1U) /*!< fill error */ +#define CAN_ERRN_2 ERR_ERRN(2U) /*!< format error */ +#define CAN_ERRN_3 ERR_ERRN(3U) /*!< ACK error */ +#define CAN_ERRN_4 ERR_ERRN(4U) /*!< bit recessive error */ +#define CAN_ERRN_5 ERR_ERRN(5U) /*!< bit dominant error */ +#define CAN_ERRN_6 ERR_ERRN(6U) /*!< CRC error */ +#define CAN_ERRN_7 ERR_ERRN(7U) /*!< software error */ + +#define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */ + +/* CAN communication mode */ +#define CAN_NORMAL_MODE ((uint8_t)0x00U) /*!< normal communication mode */ +#define CAN_LOOPBACK_MODE ((uint8_t)0x01U) /*!< loopback communication mode */ +#define CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */ +#define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */ + +/* CAN resynchronisation jump width */ +#define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ +#define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ +#define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ +#define CAN_BT_SJW_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ + +/* CAN time segment 1 */ +#define CAN_BT_BS1_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ +#define CAN_BT_BS1_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ +#define CAN_BT_BS1_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ +#define CAN_BT_BS1_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ +#define CAN_BT_BS1_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ +#define CAN_BT_BS1_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ +#define CAN_BT_BS1_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ +#define CAN_BT_BS1_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ +#define CAN_BT_BS1_9TQ ((uint8_t)0x08U) /*!< 9 time quanta */ +#define CAN_BT_BS1_10TQ ((uint8_t)0x09U) /*!< 10 time quanta */ +#define CAN_BT_BS1_11TQ ((uint8_t)0x0AU) /*!< 11 time quanta */ +#define CAN_BT_BS1_12TQ ((uint8_t)0x0BU) /*!< 12 time quanta */ +#define CAN_BT_BS1_13TQ ((uint8_t)0x0CU) /*!< 13 time quanta */ +#define CAN_BT_BS1_14TQ ((uint8_t)0x0DU) /*!< 14 time quanta */ +#define CAN_BT_BS1_15TQ ((uint8_t)0x0EU) /*!< 15 time quanta */ +#define CAN_BT_BS1_16TQ ((uint8_t)0x0FU) /*!< 16 time quanta */ + +/* CAN time segment 2 */ +#define CAN_BT_BS2_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ +#define CAN_BT_BS2_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ +#define CAN_BT_BS2_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ +#define CAN_BT_BS2_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ +#define CAN_BT_BS2_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ +#define CAN_BT_BS2_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ +#define CAN_BT_BS2_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ +#define CAN_BT_BS2_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ + +/* CAN mailbox number */ +#define CAN_MAILBOX0 ((uint8_t)0x00U) /*!< mailbox0 */ +#define CAN_MAILBOX1 ((uint8_t)0x01U) /*!< mailbox1 */ +#define CAN_MAILBOX2 ((uint8_t)0x02U) /*!< mailbox2 */ +#define CAN_NOMAILBOX ((uint8_t)0x03U) /*!< no mailbox empty */ + +/* CAN frame format */ +#define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */ +#define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */ + +/* CAN receive fifo */ +#define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */ +#define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */ + +/* frame number of receive fifo */ +#define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */ + +#define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */ +#define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */ + +/* CAN working mode */ +#define CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */ +#define CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */ +#define CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */ + +/* filter bits */ +#define CAN_FILTERBITS_16BIT ((uint8_t)0x00U) /*!< CAN filter 16 bits */ +#define CAN_FILTERBITS_32BIT ((uint8_t)0x01U) /*!< CAN filter 32 bits */ + +/* filter mode */ +#define CAN_FILTERMODE_MASK ((uint8_t)0x00U) /*!< mask mode */ +#define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */ + +/* filter 16 bits mask */ +#define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) /*!< can filter 16 bits mask */ + +/* frame type */ +#define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */ +#define CAN_FT_REMOTE ((uint32_t)0x00000002U) /*!< remote frame */ + +/* CAN timeout */ +#define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */ + +/* interrupt enable bits */ +#define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */ +#define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */ +#define CAN_INT_RFF0 CAN_INTEN_RFFIE0 /*!< receive FIFO0 full interrupt enable */ +#define CAN_INT_RFO0 CAN_INTEN_RFOIE0 /*!< receive FIFO0 overfull interrupt enable */ +#define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1 /*!< receive FIFO1 not empty interrupt enable */ +#define CAN_INT_RFF1 CAN_INTEN_RFFIE1 /*!< receive FIFO1 full interrupt enable */ +#define CAN_INT_RFO1 CAN_INTEN_RFOIE1 /*!< receive FIFO1 overfull interrupt enable */ +#define CAN_INT_WERR CAN_INTEN_WERRIE /*!< warning error interrupt enable */ +#define CAN_INT_PERR CAN_INTEN_PERRIE /*!< passive error interrupt enable */ +#define CAN_INT_BO CAN_INTEN_BOIE /*!< bus-off interrupt enable */ +#define CAN_INT_ERRN CAN_INTEN_ERRNIE /*!< error number interrupt enable */ +#define CAN_INT_ERR CAN_INTEN_ERRIE /*!< error interrupt enable */ +#define CAN_INT_WAKEUP CAN_INTEN_WIE /*!< wakeup interrupt enable */ +#define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */ + +/* function declarations */ +/* deinitialize CAN */ +void can_deinit(uint32_t can_periph); +/* initialize CAN struct */ +void can_struct_para_init(can_struct_type_enum type, void* p_struct); +/* initialize CAN */ +ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init); +/* CAN filter init */ +void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init); +/* set can1 fliter start bank number */ +void can1_filter_start_bank(uint8_t start_bank); +/* enable functions */ +/* CAN debug freeze enable */ +void can_debug_freeze_enable(uint32_t can_periph); +/* CAN debug freeze disable */ +void can_debug_freeze_disable(uint32_t can_periph); +/* CAN time trigger mode enable */ +void can_time_trigger_mode_enable(uint32_t can_periph); +/* CAN time trigger mode disable */ +void can_time_trigger_mode_disable(uint32_t can_periph); + +/* transmit functions */ +/* transmit CAN message */ +uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message); +/* get CAN transmit state */ +can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number); +/* stop CAN transmission */ +void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); +/* CAN receive message */ +void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message); +/* CAN release fifo */ +void can_fifo_release(uint32_t can_periph, uint8_t fifo_number); +/* CAN receive message length */ +uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number); +/* CAN working mode */ +ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode); +/* CAN wakeup from sleep mode */ +ErrStatus can_wakeup(uint32_t can_periph); + +/* CAN get error */ +can_error_enum can_error_get(uint32_t can_periph); +/* get CAN receive error number */ +uint8_t can_receive_error_number_get(uint32_t can_periph); +/* get CAN transmit error number */ +uint8_t can_transmit_error_number_get(uint32_t can_periph); + +/* CAN interrupt enable */ +void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); +/* CAN interrupt disable */ +void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); +/* CAN get flag state */ +FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag); +/* CAN clear flag state */ +void can_flag_clear(uint32_t can_periph, can_flag_enum flag); +/* CAN get interrupt flag state */ +FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag); +/* CAN clear interrupt flag state */ +void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag); + +#endif /* GD32VF103_CAN_H */ diff --git a/cpu/gd32v/include/vendor/gd32vf103_core.h b/cpu/gd32v/include/vendor/gd32vf103_core.h new file mode 100644 index 0000000000..8109f2130a --- /dev/null +++ b/cpu/gd32v/include/vendor/gd32vf103_core.h @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2020 Koen Zandberg + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ +/** + * @ingroup cpu_gd32v + * @{ + * + * @file + * @brief Extra definitions for the GD32VF103 core missing from the + * other vendor definitions + * + * @author Koen Zandberg + */ +#ifndef GD32VF103_CORE_H +#define GD32VF103_CORE_H + +#include "vendor/gd32vf103.h" + +#ifdef cplusplus + extern "C" { +#endif + +#define _REG32(p, i) (*(volatile uint32_t *) ((p) + (i))) +#define _REG32P(p, i) ((volatile uint32_t *) ((p) + (i))) + +/** + * @brief RISC-V ECLIC per interrupt configuration registers + */ +typedef struct __attribute((packed)) { + volatile uint8_t ip; /**< Interrupt pending */ + volatile uint8_t ie; /**< Interrupt enable */ + volatile uint8_t attr; /**< Interrupt attributes */ + volatile uint8_t ctl; /**< Interrupt control */ +} eclic_clicint_t; + +/** + * @name RISC-V ECLIC definitions + * @{ + */ +#define ECLIC_CTRL_ADDR 0xd2000000 +#define ECLIC_REG(offset) _REG32(ECLIC_CTRL_ADDR, offset) +#define ECLIC_REGP(offset) _REG32P(ECLIC_CTRL_ADDR, offset) + +#define ECLIC_CLICCFG *((volatile uint8_t*)ECLIC_REGP(0x0)) +#define ECLIC_CLICINFO *((volatile uint32_t*)ECLIC_REGP(0x4) +#define ECLIC_CLICMTH *((volatile uint8_t*)ECLIC_REGP(0xb) +#define ECLIC_CLICINT_ADDR ECLIC_REGP(0x1000) +#define ECLIC_CLICINT ((volatile eclic_clicint_t *)ECLIC_CLICINT_ADDR) +/** @} */ + + +/** + * @name RISC-V core timer definitions on the GD32V. No actual CLINT is present, + * but the core timer implements similar register definitions. + * @{ + */ +#define CLINT_CTRL_ADDR 0xd1000000 + +#define CLINT_MTIME (0x0000U) +#define CLINT_MTIMECMP (0x0008U) +#define CLINT_MSTOP (0x0FF8U) +#define CLINT_MSIP (0x0FFCU) + +#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset) +#define CLINT_FREQ_DIV (4U) + +/** @} */ + +#ifdef cplusplus +} +#endif + +#endif /* GD32VF103_CORE_H */ diff --git a/cpu/gd32v/include/vendor/gd32vf103_crc.h b/cpu/gd32v/include/vendor/gd32vf103_crc.h new file mode 100644 index 0000000000..78b94e72e0 --- /dev/null +++ b/cpu/gd32v/include/vendor/gd32vf103_crc.h @@ -0,0 +1,78 @@ +/*! + \file gd32vf103_crc.h + \brief definitions for the CRC + + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_CRC_H +#define GD32VF103_CRC_H + +#include "gd32vf103.h" + +/* CRC definitions */ +#define CRC CRC_BASE + +/* registers definitions */ +#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */ +#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */ +#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */ + +/* bits definitions */ +/* CRC_DATA */ +#define CRC_DATA_DATA BITS(0, 31) /*!< CRC calculation result bits */ + +/* CRC_FDATA */ +#define CRC_FDATA_FDATA BITS(0, 7) /*!< CRC free data bits */ + +/* CRC_CTL */ +#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */ + +/* function declarations */ +/* deinit CRC calculation unit */ +void crc_deinit(void); + +/* reset data register(CRC_DATA) to the value of 0xFFFFFFFF */ +void crc_data_register_reset(void); +/* read the value of the data register */ +uint32_t crc_data_register_read(void); + +/* read the value of the free data register */ +uint8_t crc_free_data_register_read(void); +/* write data to the free data register */ +void crc_free_data_register_write(uint8_t free_data); + +/* calculate the CRC value of a 32-bit data */ +uint32_t crc_single_data_calculate(uint32_t sdata); +/* calculate the CRC value of an array of 32-bit values */ +uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size); + +#endif /* GD32VF103_CRC_H */ diff --git a/cpu/gd32v/include/vendor/gd32vf103_dac.h b/cpu/gd32v/include/vendor/gd32vf103_dac.h new file mode 100644 index 0000000000..3ebc93042d --- /dev/null +++ b/cpu/gd32v/include/vendor/gd32vf103_dac.h @@ -0,0 +1,242 @@ +/*! + \file gd32vf103_dac.h + \brief definitions for the DAC + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_DAC_H +#define GD32VF103_DAC_H + +#include "gd32vf103.h" + +/* DACx(x=0,1) definitions */ +#define DAC DAC_BASE +#define DAC0 (0U) +#define DAC1 (1U) + +/* registers definitions */ +#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */ +#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */ +#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */ +#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */ +#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */ +#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */ +#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */ +#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */ +#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */ +#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */ +#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */ +#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */ +#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */ + +/* bits definitions */ +/* DAC_CTL */ +#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ +#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */ +#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ +#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ +#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ +#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ +#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ +#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ +#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ +#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ +#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ +#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ +#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ +#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ + +/* DAC_SWT */ +#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */ +#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ + +/* DAC0_R12DH */ +#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ + +/* DAC0_L12DH */ +#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ + +/* DAC0_R8DH */ +#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ + +/* DAC1_R12DH */ +#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ + +/* DAC1_L12DH */ +#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ + +/* DAC1_R8DH */ +#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ + +/* DACC_R12DH */ +#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ +#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ + +/* DACC_L12DH */ +#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ +#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ + +/* DACC_R8DH */ +#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ +#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ + +/* DAC0_DO */ +#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ + +/* DAC1_DO */ +#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ + +/* constants definitions */ +/* DAC trigger source */ +#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) +#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ +#define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */ +#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ +#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */ +#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */ +#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */ +#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */ +#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ + +/* DAC noise wave mode */ +#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) +#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ +#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ +#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ + +/* DAC noise wave bit width */ +#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) +#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ +#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ +#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ +#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ +#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ +#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ +#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ +#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ +#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ +#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ +#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ +#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ + +/* unmask LFSR bits in DAC LFSR noise mode */ +#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ +#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ +#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ +#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ +#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ +#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ +#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ +#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ +#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ +#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ +#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ +#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ + +/* DAC data alignment */ +#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12b alignment */ +#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12b alignment */ +#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8b alignment */ +/* triangle amplitude in DAC triangle noise mode */ +#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ +#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ +#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ +#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ +#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ +#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ +#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ +#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ +#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ +#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ +#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ +#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ + +/* function declarations */ +/* initialization functions */ +/* deinitialize DAC */ +void dac_deinit(void); +/* enable DAC */ +void dac_enable(uint32_t dac_periph); +/* disable DAC */ +void dac_disable(uint32_t dac_periph); +/* enable DAC DMA */ +void dac_dma_enable(uint32_t dac_periph); +/* disable DAC DMA */ +void dac_dma_disable(uint32_t dac_periph); +/* enable DAC output buffer */ +void dac_output_buffer_enable(uint32_t dac_periph); +/* disable DAC output buffer */ +void dac_output_buffer_disable(uint32_t dac_periph); +/* get the last data output value */ +uint16_t dac_output_value_get(uint32_t dac_periph); +/* set DAC data holding register value */ +void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data); + +/* DAC trigger configuration */ +/* enable DAC trigger */ +void dac_trigger_enable(uint32_t dac_periph); +/* disable DAC trigger */ +void dac_trigger_disable(uint32_t dac_periph); +/* configure DAC trigger source */ +void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource); +/* enable DAC software trigger */ +void dac_software_trigger_enable(uint32_t dac_periph); +/* disable DAC software trigger */ +void dac_software_trigger_disable(uint32_t dac_periph); + +/* DAC wave mode configuration */ +/* configure DAC wave mode */ +void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode); +/* configure DAC wave bit width */ +void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width); +/* configure DAC LFSR noise mode */ +void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits); +/* configure DAC triangle noise mode */ +void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude); + +/* DAC concurrent mode configuration */ +/* enable DAC concurrent mode */ +void dac_concurrent_enable(void); +/* disable DAC concurrent mode */ +void dac_concurrent_disable(void); +/* enable DAC concurrent software trigger */ +void dac_concurrent_software_trigger_enable(void); +/* disable DAC concurrent software trigger */ +void dac_concurrent_software_trigger_disable(void); +/* enable DAC concurrent buffer function */ +void dac_concurrent_output_buffer_enable(void); +/* disable DAC concurrent buffer function */ +void dac_concurrent_output_buffer_disable(void); +/* set DAC concurrent mode data holding register value */ +void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); + +#endif /* GD32VF103_DAC_H */ diff --git a/cpu/gd32v/include/vendor/gd32vf103_dbg.h b/cpu/gd32v/include/vendor/gd32vf103_dbg.h new file mode 100644 index 0000000000..262abc75d6 --- /dev/null +++ b/cpu/gd32v/include/vendor/gd32vf103_dbg.h @@ -0,0 +1,109 @@ +/*! + \file gd32vf103_dbg.h + \brief definitions for the DBG + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_DBG_H +#define GD32VF103_DBG_H + +#include "gd32vf103.h" + +/* DBG definitions */ +#define DBG DBG_BASE + +/* registers definitions */ +#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */ +#define DBG_CTL REG32(DBG + 0x04U) /*!< DBG control register */ + +/* bits definitions */ +/* DBG_ID */ +#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ + +/* DBG_CTL */ +#define DBG_CTL_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ +#define DBG_CTL_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ +#define DBG_CTL_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ +#define DBG_CTL_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */ +#define DBG_CTL_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */ +#define DBG_CTL_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */ +#define DBG_CTL_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */ +#define DBG_CTL_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */ +#define DBG_CTL_TIMER3_HOLD BIT(13) /*!< hold TIMER3 counter when core is halted */ +#define DBG_CTL_CAN0_HOLD BIT(14) /*!< debug CAN0 kept when core is halted */ +#define DBG_CTL_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */ +#define DBG_CTL_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */ +#define DBG_CTL_TIMER4_HOLD BIT(18) /*!< hold TIMER4 counter when core is halted */ +#define DBG_CTL_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */ +#define DBG_CTL_TIMER6_HOLD BIT(20) /*!< hold TIMER6 counter when core is halted */ +#define DBG_CTL_CAN1_HOLD BIT(21) /*!< debug CAN1 kept when core is halted */ + +/* constants definitions */ +/* debug hold when core is halted */ +typedef enum +{ + DBG_FWDGT_HOLD = BIT(8), /*!< debug FWDGT kept when core is halted */ + DBG_WWDGT_HOLD = BIT(9), /*!< debug WWDGT kept when core is halted */ + DBG_TIMER0_HOLD = BIT(10), /*!< hold TIMER0 counter when core is halted */ + DBG_TIMER1_HOLD = BIT(11), /*!< hold TIMER1 counter when core is halted */ + DBG_TIMER2_HOLD = BIT(12), /*!< hold TIMER2 counter when core is halted */ + DBG_TIMER3_HOLD = BIT(13), /*!< hold TIMER3 counter when core is halted */ + DBG_CAN0_HOLD = BIT(14), /*!< debug CAN0 kept when core is halted */ + DBG_I2C0_HOLD = BIT(15), /*!< hold I2C0 smbus when core is halted */ + DBG_I2C1_HOLD = BIT(16), /*!< hold I2C1 smbus when core is halted */ + DBG_TIMER4_HOLD = BIT(17), /*!< hold TIMER4 counter when core is halted */ + DBG_TIMER5_HOLD = BIT(18), /*!< hold TIMER5 counter when core is halted */ + DBG_TIMER6_HOLD = BIT(19), /*!< hold TIMER6 counter when core is halted */ + DBG_CAN1_HOLD = BIT(21), /*!< debug CAN1 kept when core is halted */ +}dbg_periph_enum; + +/* DBG low power mode configurations */ +#define DBG_LOW_POWER_SLEEP DBG_CTL_SLP_HOLD /*!< keep debugger connection during sleep mode */ +#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ +#define DBG_LOW_POWER_STANDBY DBG_CTL_STB_HOLD /*!< keep debugger connection during standby mode */ + +/* function declarations */ +/* read DBG_ID code register */ +uint32_t dbg_id_get(void); + +/* low power behavior configuration */ +/* enable low power behavior when the MCU is in debug mode */ +void dbg_low_power_enable(uint32_t dbg_low_power); +/* disable low power behavior when the MCU is in debug mode */ +void dbg_low_power_disable(uint32_t dbg_low_power); + +/* peripheral behavior configuration */ +/* enable peripheral behavior when the MCU is in debug mode */ +void dbg_periph_enable(dbg_periph_enum dbg_periph); +/* disable peripheral behavior when the MCU is in debug mode */ +void dbg_periph_disable(dbg_periph_enum dbg_periph); + +#endif /* GD32VF103_DBG_H */ diff --git a/cpu/gd32v/include/vendor/gd32vf103_dma.h b/cpu/gd32v/include/vendor/gd32vf103_dma.h new file mode 100644 index 0000000000..1dfd1d873e --- /dev/null +++ b/cpu/gd32v/include/vendor/gd32vf103_dma.h @@ -0,0 +1,283 @@ +/*! + \file gd32vf103_dma.h + \brief definitions for the DMA + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + \version 2019-10-30, V1.0.1, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_DMA_H +#define GD32VF103_DMA_H + +#include "gd32vf103.h" + +/* DMA definitions */ +#define DMA0 (DMA_BASE) /*!< DMA0 base address */ +#define DMA1 (DMA_BASE + 0x0400U) /*!< DMA1 base address */ + +/* registers definitions */ +#define DMA_INTF(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register */ +#define DMA_INTC(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag clear register */ + +#define DMA_CH0CTL(dmax) REG32((dmax) + 0x08U) /*!< DMA channel 0 control register */ +#define DMA_CH0CNT(dmax) REG32((dmax) + 0x0CU) /*!< DMA channel 0 counter register */ +#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 peripheral base address register */ +#define DMA_CH0MADDR(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 memory base address register */ + +#define DMA_CH1CTL(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 1 control register */ +#define DMA_CH1CNT(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 1 counter register */ +#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 1 peripheral base address register */ +#define DMA_CH1MADDR(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 memory base address register */ + +#define DMA_CH2CTL(dmax) REG32((dmax) + 0x30U) /*!< DMA channel 2 control register */ +#define DMA_CH2CNT(dmax) REG32((dmax) + 0x34U) /*!< DMA channel 2 counter register */ +#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x38U) /*!< DMA channel 2 peripheral base address register */ +#define DMA_CH2MADDR(dmax) REG32((dmax) + 0x3CU) /*!< DMA channel 2 memory base address register */ + +#define DMA_CH3CTL(dmax) REG32((dmax) + 0x44U) /*!< DMA channel 3 control register */ +#define DMA_CH3CNT(dmax) REG32((dmax) + 0x48U) /*!< DMA channel 3 counter register */ +#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x4CU) /*!< DMA channel 3 peripheral base address register */ +#define DMA_CH3MADDR(dmax) REG32((dmax) + 0x50U) /*!< DMA channel 3 memory base address register */ + +#define DMA_CH4CTL(dmax) REG32((dmax) + 0x58U) /*!< DMA channel 4 control register */ +#define DMA_CH4CNT(dmax) REG32((dmax) + 0x5CU) /*!< DMA channel 4 counter register */ +#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x60U) /*!< DMA channel 4 peripheral base address register */ +#define DMA_CH4MADDR(dmax) REG32((dmax) + 0x64U) /*!< DMA channel 4 memory base address register */ + +#define DMA_CH5CTL(dmax) REG32((dmax) + 0x6CU) /*!< DMA channel 5 control register */ +#define DMA_CH5CNT(dmax) REG32((dmax) + 0x70U) /*!< DMA channel 5 counter register */ +#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x74U) /*!< DMA channel 5 peripheral base address register */ +#define DMA_CH5MADDR(dmax) REG32((dmax) + 0x78U) /*!< DMA channel 5 memory base address register */ + +#define DMA_CH6CTL(dmax) REG32((dmax) + 0x80U) /*!< DMA channel 6 control register */ +#define DMA_CH6CNT(dmax) REG32((dmax) + 0x84U) /*!< DMA channel 6 counter register */ +#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x88U) /*!< DMA channel 6 peripheral base address register */ +#define DMA_CH6MADDR(dmax) REG32((dmax) + 0x8CU) /*!< DMA channel 6 memory base address register */ + +/* bits definitions */ +/* DMA_INTF */ +#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */ +#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */ +#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */ +#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */ + +/* DMA_INTC */ +#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */ +#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */ +#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */ +#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */ + +/* DMA_CHxCTL, x=0..6 */ +#define DMA_CHXCTL_CHEN BIT(0) /*!< channel enable */ +#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel full transfer finish interrupt */ +#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel half transfer finish interrupt */ +#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel error interrupt */ +#define DMA_CHXCTL_DIR BIT(4) /*!< transfer direction */ +#define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */ +#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ +#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ +#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data width of peripheral */ +#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data width of memory */ +#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level */ +#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ + +/* DMA_CHxCNT, x=0..6 */ +#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ + +/* DMA_CHxPADDR, x=0..6 */ +#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ + +/* DMA_CHxMADDR, x=0..6 */ +#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ + +/* constants definitions */ +/* DMA channel select */ +typedef enum +{ + DMA_CH0 = 0, /*!< DMA Channel0 */ + DMA_CH1, /*!< DMA Channel1 */ + DMA_CH2, /*!< DMA Channel2 */ + DMA_CH3, /*!< DMA Channel3 */ + DMA_CH4, /*!< DMA Channel4 */ + DMA_CH5, /*!< DMA Channel5 */ + DMA_CH6 /*!< DMA Channel6 */ +} dma_channel_enum; + +/* DMA initialize struct */ +typedef struct +{ + uint32_t periph_addr; /*!< peripheral base address */ + uint32_t periph_width; /*!< transfer data size of peripheral */ + uint32_t memory_addr; /*!< memory base address */ + uint32_t memory_width; /*!< transfer data size of memory */ + uint32_t number; /*!< channel transfer number */ + uint32_t priority; /*!< channel priority level */ + uint8_t periph_inc; /*!< peripheral increasing mode */ + uint8_t memory_inc; /*!< memory increasing mode */ + uint8_t direction; /*!< channel data transfer direction */ + +} dma_parameter_struct; + +#define DMA_FLAG_ADD(flag, shift) ((flag) << ((shift) * 4U)) /*!< DMA channel flag shift */ + +/* DMA_register address */ +#define DMA_CHCTL(dma, channel) REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */ +#define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */ +#define DMA_CHPADDR(dma, channel) REG32(((dma) + 0x10U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */ +#define DMA_CHMADDR(dma, channel) REG32(((dma) + 0x14U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */ + +/* DMA reset value */ +#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ +#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ +#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ +#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ +#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \ + DMA_INTF_HTFIF | DMA_INTF_ERRIF) /*!< clear DMA channel DMA_INTF register */ + +/* DMA_INTF register */ +/* interrupt flag bits */ +#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ +#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */ +#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */ +#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */ + +/* flag bits */ +#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ +#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */ +#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */ +#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */ + +/* DMA_CHxCTL register */ +/* interrupt enable bits */ +#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */ +#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */ +#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */ + +/* transfer direction */ +#define DMA_PERIPHERAL_TO_MEMORY ((uint8_t)0x00U) /*!< read from peripheral and write to memory */ +#define DMA_MEMORY_TO_PERIPHERAL ((uint8_t)0x01U) /*!< read from memory and write to peripheral */ + +/* peripheral increasing mode */ +#define DMA_PERIPH_INCREASE_DISABLE ((uint8_t)0x00U) /*!< next address of peripheral is fixed address mode */ +#define DMA_PERIPH_INCREASE_ENABLE ((uint8_t)0x01U) /*!< next address of peripheral is increasing address mode */ + +/* memory increasing mode */ +#define DMA_MEMORY_INCREASE_DISABLE ((uint8_t)0x00U) /*!< next address of memory is fixed address mode */ +#define DMA_MEMORY_INCREASE_ENABLE ((uint8_t)0x01U) /*!< next address of memory is increasing address mode */ + +/* transfer data size of peripheral */ +#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< transfer data size of peripheral */ +#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0U) /*!< transfer data size of peripheral is 8-bit */ +#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1U) /*!< transfer data size of peripheral is 16-bit */ +#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2U) /*!< transfer data size of peripheral is 32-bit */ + +/* transfer data size of memory */ +#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< transfer data size of memory */ +#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0U) /*!< transfer data size of memory is 8-bit */ +#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1U) /*!< transfer data size of memory is 16-bit */ +#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2U) /*!< transfer data size of memory is 32-bit */ + +/* channel priority level */ +#define CHCTL_PRIO(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */ +#define DMA_PRIORITY_LOW CHCTL_PRIO(0U) /*!< low priority */ +#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1U) /*!< medium priority */ +#define DMA_PRIORITY_HIGH CHCTL_PRIO(2U) /*!< high priority */ +#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3U) /*!< ultra high priority */ + +/* memory to memory mode */ +#define DMA_MEMORY_TO_MEMORY_DISABLE ((uint32_t)0x00000000U) /*!< disable memory to memory mode */ +#define DMA_MEMORY_TO_MEMORY_ENABLE ((uint32_t)0x00000001U) /*!< enable memory to memory mode */ + +/* DMA_CHxCNT register */ +/* transfer counter */ +#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT /*!< transfer counter mask */ + +/* function declarations */ +/* DMA deinitialization and initialization functions */ +/* deinitialize DMA a channel registers */ +void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx); +/* initialize the parameters of DMA struct with the default values */ +void dma_struct_para_init(dma_parameter_struct* init_struct); +/* initialize DMA channel */ +void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct *init_struct); +/* enable DMA circulation mode */ +void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable DMA circulation mode */ +void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* enable memory to memory mode */ +void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable memory to memory mode */ +void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* enable DMA channel */ +void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable DMA channel */ +void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx); + +/* DMA configuration functions */ +/* set DMA peripheral base address */ +void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); +/* set DMA memory base address */ +void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); +/* set the number of remaining data to be transferred by the DMA */ +void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number); +/* get the number of remaining data to be transferred by the DMA */ +uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx); +/* configure priority level of DMA channel */ +void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority); +/* configure transfer data size of memory */ +void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth); +/* configure transfer data size of peripheral */ +void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth); +/* enable next address increasement algorithm of memory */ +void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable next address increasement algorithm of memory */ +void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* enable next address increasement algorithm of peripheral */ +void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); +/* disable next address increasement algorithm of peripheral */ +void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); +/* configure the direction of data transfer on the channel */ +void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t direction); + +/* flag and interrupt functions */ +/* check DMA flag is set or not */ +FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* clear the flag of a DMA channel */ +void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* check DMA flag and interrupt enable bit is set or not */ +FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* clear the interrupt flag of a DMA channel */ +void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); +/* enable DMA interrupt */ +void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); +/* disable DMA interrupt */ +void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); + +#endif /* GD32VF103_DMA_H */ diff --git a/cpu/gd32v/include/vendor/gd32vf103_eclic.h b/cpu/gd32v/include/vendor/gd32vf103_eclic.h new file mode 100644 index 0000000000..b36f9a6ccf --- /dev/null +++ b/cpu/gd32v/include/vendor/gd32vf103_eclic.h @@ -0,0 +1,66 @@ +/*! + \file gd32vf103_eclic.h + \brief definitions for the ECLIC(Enhancement Core-Local Interrupt Controller) + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_ECLIC_H +#define GD32VF103_ECLIC_H + +#include "gd32vf103.h" + +/* constants definitions */ +#define ECLIC_PRIGROUP_LEVEL0_PRIO4 0 /*!< 0 bits for level 4 bits for priority */ +#define ECLIC_PRIGROUP_LEVEL1_PRIO3 1 /*!< 1 bits for level 3 bits for priority */ +#define ECLIC_PRIGROUP_LEVEL2_PRIO2 2 /*!< 2 bits for level 2 bits for priority */ +#define ECLIC_PRIGROUP_LEVEL3_PRIO1 3 /*!< 3 bits for level 1 bits for priority */ +#define ECLIC_PRIGROUP_LEVEL4_PRIO0 4 /*!< 4 bits for level 0 bits for priority */ + +#define __SEV eclic_send_event + +/* function declarations */ +/* enable the global interrupt */ +void eclic_global_interrupt_enable(void); +/* disable the global interrupt */ +void eclic_global_interrupt_disable(void); +/* set the priority group */ +void eclic_priority_group_set(uint32_t prigroup); +/* enable the interrupt request */ +void eclic_irq_enable(uint32_t source, uint8_t level, uint8_t priority); +/* disable the interrupt request */ +void eclic_irq_disable(uint32_t source); + +/* reset system */ +void eclic_system_reset(void); +/* send event(SEV) */ +void eclic_send_event(void); + +#endif /* GD32VF103_ECLIC_H */ diff --git a/cpu/gd32v/include/vendor/gd32vf103_exmc.h b/cpu/gd32v/include/vendor/gd32vf103_exmc.h new file mode 100644 index 0000000000..8022104b0c --- /dev/null +++ b/cpu/gd32v/include/vendor/gd32vf103_exmc.h @@ -0,0 +1,126 @@ +/*! + \file gd32vf103_exmc.h + \brief definitions for the EXMC + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_EXMC_H +#define GD32VF103_EXMC_H + +#include "gd32vf103.h" + +/* EXMC definitions */ +#define EXMC (EXMC_BASE) /*!< EXMC register base address */ + +/* registers definitions */ +/* NOR/PSRAM */ +#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register 0 */ +#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register 0 */ +#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register 0 */ + +/* bits definitions */ +/* NOR/PSRAM */ +/* EXMC_SNCTLx, x=0 */ +#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */ +#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing */ +#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */ +#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */ +#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ +#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ +#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */ +#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ +#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */ + +/* EXMC_SNTCFGx, x=0 */ +#define EXMC_SNTCFG_ASET BITS(0,3) /*!< address setup time */ +#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< address hold time */ +#define EXMC_SNTCFG_DSET BITS(8,15) /*!< data setup time */ +#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ + +/* constants definitions */ +/* EXMC NOR/SRAM timing initialize struct */ +typedef struct +{ + uint32_t bus_latency; /*!< configure the bus latency */ + uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ + uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */ + uint32_t asyn_address_setuptime; /*!< configure the data setup time,asynchronous access mode valid */ +}exmc_norsram_timing_parameter_struct; + +/* EXMC NOR/SRAM initialize struct */ +typedef struct +{ + uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */ + uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */ + uint32_t nwait_signal; /*!< enable or disable the NWAIT signal */ + uint32_t memory_write; /*!< enable or disable the write operation */ + uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */ + uint32_t databus_width; /*!< specifies the databus width of external memory */ + uint32_t memory_type; /*!< specifies the type of external memory */ + uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */ + exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write */ +}exmc_norsram_parameter_struct; + +/* EXMC register address */ +#define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC SRAM/NOR flash control register */ +#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash timing configuration register */ + +/* NOR bank memory data bus width */ +#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */ +#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */ + +/* NOR bank memory type */ +#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ +#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ +#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ + +/* EXMC NOR/SRAM bank region definition */ +#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */ + +/* EXMC NWAIT signal polarity configuration */ +#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */ +#define EXMC_NWAIT_POLARITY_HIGH ((uint32_t)0x00000200U) /*!< high level is active of NWAIT */ + +/* function declarations */ +/* deinitialize EXMC NOR/SRAM region */ +void exmc_norsram_deinit(uint32_t norsram_region); +/* exmc_norsram_parameter_struct parameter initialize */ +void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); +/* initialize EXMC NOR/SRAM region */ +void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); +/* EXMC NOR/SRAM bank enable */ +void exmc_norsram_enable(uint32_t norsram_region); +/* EXMC NOR/SRAM bank disable */ +void exmc_norsram_disable(uint32_t norsram_region); + +#endif /* GD32VF103_EXMC_H */ diff --git a/cpu/gd32v/include/vendor/gd32vf103_exti.h b/cpu/gd32v/include/vendor/gd32vf103_exti.h new file mode 100644 index 0000000000..8e8ca85e19 --- /dev/null +++ b/cpu/gd32v/include/vendor/gd32vf103_exti.h @@ -0,0 +1,245 @@ +/*! + \file gd32vf103_exti.h + \brief definitions for the EXTI + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_EXTI_H +#define GD32VF103_EXTI_H + +#include "gd32vf103.h" + +/* EXTI definitions */ +#define EXTI EXTI_BASE + +/* registers definitions */ +#define EXTI_INTEN REG32(EXTI + 0x00U) /*!< interrupt enable register */ +#define EXTI_EVEN REG32(EXTI + 0x04U) /*!< event enable register */ +#define EXTI_RTEN REG32(EXTI + 0x08U) /*!< rising edge trigger enable register */ +#define EXTI_FTEN REG32(EXTI + 0x0CU) /*!< falling trigger enable register */ +#define EXTI_SWIEV REG32(EXTI + 0x10U) /*!< software interrupt event register */ +#define EXTI_PD REG32(EXTI + 0x14U) /*!< pending register */ + +/* bits definitions */ +/* EXTI_INTEN */ +#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */ +#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */ +#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */ +#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */ +#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */ +#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */ +#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */ +#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */ +#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */ +#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */ +#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */ +#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */ +#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */ +#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */ +#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */ +#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */ +#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */ +#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */ +#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */ + +/* EXTI_EVEN */ +#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */ +#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */ +#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */ +#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */ +#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */ +#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */ +#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */ +#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */ +#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */ +#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */ +#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */ +#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */ +#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */ +#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */ +#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */ +#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */ +#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */ +#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */ +#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */ + +/* EXTI_RTEN */ +#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */ +#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */ +#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */ +#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */ +#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */ +#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */ +#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */ +#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */ +#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */ +#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */ +#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */ +#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */ +#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */ +#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */ +#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */ +#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */ +#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */ +#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */ +#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */ + +/* EXTI_FTEN */ +#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */ +#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */ +#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */ +#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */ +#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */ +#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */ +#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */ +#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */ +#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */ +#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */ +#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */ +#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */ +#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */ +#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */ +#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */ +#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */ +#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */ +#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */ +#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */ + +/* EXTI_SWIEV */ +#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */ +#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */ +#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */ +#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */ +#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */ +#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */ +#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */ +#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */ +#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */ +#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */ +#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */ +#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */ +#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */ +#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */ +#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */ +#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */ +#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */ +#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */ +#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */ + +/* EXTI_PD */ +#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */ +#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */ +#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */ +#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */ +#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */ +#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */ +#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */ +#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */ +#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */ +#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */ +#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */ +#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */ +#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */ +#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */ +#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */ +#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */ +#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */ +#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */ +#define EXTI_PD_PD18 BIT(18) /*!< interrupt/event pending status from line 18 */ + +/* constants definitions */ +/* EXTI line number */ +typedef enum { + EXTI_0 = BIT(0), /*!< EXTI line 0 */ + EXTI_1 = BIT(1), /*!< EXTI line 1 */ + EXTI_2 = BIT(2), /*!< EXTI line 2 */ + EXTI_3 = BIT(3), /*!< EXTI line 3 */ + EXTI_4 = BIT(4), /*!< EXTI line 4 */ + EXTI_5 = BIT(5), /*!< EXTI line 5 */ + EXTI_6 = BIT(6), /*!< EXTI line 6 */ + EXTI_7 = BIT(7), /*!< EXTI line 7 */ + EXTI_8 = BIT(8), /*!< EXTI line 8 */ + EXTI_9 = BIT(9), /*!< EXTI line 9 */ + EXTI_10 = BIT(10), /*!< EXTI line 10 */ + EXTI_11 = BIT(11), /*!< EXTI line 11 */ + EXTI_12 = BIT(12), /*!< EXTI line 12 */ + EXTI_13 = BIT(13), /*!< EXTI line 13 */ + EXTI_14 = BIT(14), /*!< EXTI line 14 */ + EXTI_15 = BIT(15), /*!< EXTI line 15 */ + EXTI_16 = BIT(16), /*!< EXTI line 16 */ + EXTI_17 = BIT(17), /*!< EXTI line 17 */ + EXTI_18 = BIT(18), /*!< EXTI line 18 */ +} exti_line_enum; + +/* external interrupt and event */ +typedef enum { + EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */ + EXTI_EVENT /*!< EXTI event mode */ +} exti_mode_enum; + +/* interrupt trigger mode */ +typedef enum { + EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ + EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ + EXTI_TRIG_BOTH, /*!< EXTI rising edge and falling edge trigger */ + EXTI_TRIG_NONE /*!< without rising edge or falling edge trigger */ +} exti_trig_type_enum; + +/* function declarations */ +/* initialization, EXTI lines configuration functions */ +/* deinitialize the EXTI */ +void exti_deinit(void); +/* enable the configuration of EXTI initialize */ +void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type); +/* enable the interrupts from EXTI line x */ +void exti_interrupt_enable(exti_line_enum linex); +/* enable the events from EXTI line x */ +void exti_event_enable(exti_line_enum linex); +/* disable the interrupts from EXTI line x */ +void exti_interrupt_disable(exti_line_enum linex); +/* disable the events from EXTI line x */ +void exti_event_disable(exti_line_enum linex); + +/* interrupt & flag functions */ +/* get EXTI lines pending flag */ +FlagStatus exti_flag_get(exti_line_enum linex); +/* clear EXTI lines pending flag */ +void exti_flag_clear(exti_line_enum linex); +/* get EXTI lines flag when the interrupt flag is set */ +FlagStatus exti_interrupt_flag_get(exti_line_enum linex); +/* clear EXTI lines pending flag */ +void exti_interrupt_flag_clear(exti_line_enum linex); +/* enable the EXTI software interrupt event */ +void exti_software_interrupt_enable(exti_line_enum linex); +/* disable the EXTI software interrupt event */ +void exti_software_interrupt_disable(exti_line_enum linex); + +#endif /* GD32VF103_EXTI_H */ diff --git a/cpu/gd32v/include/vendor/gd32vf103_fmc.h b/cpu/gd32v/include/vendor/gd32vf103_fmc.h new file mode 100644 index 0000000000..05ecbd6551 --- /dev/null +++ b/cpu/gd32v/include/vendor/gd32vf103_fmc.h @@ -0,0 +1,312 @@ +/*! + \file gd32vf103_fmc.h + \brief definitions for the FMC + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + \version 2019-09-18, V1.0.1, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_FMC_H +#define GD32VF103_FMC_H + +#include "gd32vf103.h" + +/* FMC and option byte definition */ +#define FMC FMC_BASE /*!< FMC register base address */ +#define OB OB_BASE /*!< option bytes base address */ + +/* registers definitions */ +#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */ +#define FMC_KEY REG32((FMC) + 0x04U) /*!< FMC unlock key register */ +#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */ +#define FMC_STAT REG32((FMC) + 0x0CU) /*!< FMC status register */ +#define FMC_CTL REG32((FMC) + 0x10U) /*!< FMC control register */ +#define FMC_ADDR REG32((FMC) + 0x14U) /*!< FMC address register */ +#define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */ +#define FMC_WP REG32((FMC) + 0x20U) /*!< FMC erase/program protection register */ +#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */ + +#define OB_SPC REG16((OB) + 0x00U) /*!< option byte security protection value */ +#define OB_USER REG16((OB) + 0x02U) /*!< option byte user value*/ +#define OB_WP0 REG16((OB) + 0x08U) /*!< option byte write protection 0 */ +#define OB_WP1 REG16((OB) + 0x0AU) /*!< option byte write protection 1 */ +#define OB_WP2 REG16((OB) + 0x0CU) /*!< option byte write protection 2 */ +#define OB_WP3 REG16((OB) + 0x0EU) /*!< option byte write protection 3 */ + +/* bits definitions */ +/* FMC_WS */ +#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */ + +/* FMC_KEY */ +#define FMC_KEY_KEY BITS(0,31) /*!< FMC_CTL unlock key bits */ + +/* FMC_OBKEY */ +#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */ + +/* FMC_STAT */ +#define FMC_STAT_BUSY BIT(0) /*!< flash busy flag bit */ +#define FMC_STAT_PGERR BIT(2) /*!< flash program error flag bit */ +#define FMC_STAT_WPERR BIT(4) /*!< erase/program protection error flag bit */ +#define FMC_STAT_ENDF BIT(5) /*!< end of operation flag bit */ + +/* FMC_CTL */ +#define FMC_CTL_PG BIT(0) /*!< main flash program command bit */ +#define FMC_CTL_PER BIT(1) /*!< main flash page erase command bit */ +#define FMC_CTL_MER BIT(2) /*!< main flash mass erase command bit */ +#define FMC_CTL_OBPG BIT(4) /*!< option bytes program command bit */ +#define FMC_CTL_OBER BIT(5) /*!< option bytes erase command bit */ +#define FMC_CTL_START BIT(6) /*!< send erase command to FMC bit */ +#define FMC_CTL_LK BIT(7) /*!< FMC_CTL lock bit */ +#define FMC_CTL_OBWEN BIT(9) /*!< option bytes erase/program enable bit */ +#define FMC_CTL_ERRIE BIT(10) /*!< error interrupt enable bit */ +#define FMC_CTL_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ + +/* FMC_ADDR */ +#define FMC_ADDR0_ADDR BITS(0,31) /*!< Flash erase/program command address bits */ + +/* FMC_OBSTAT */ +#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */ +#define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */ +#define FMC_OBSTAT_USER BITS(2,9) /*!< store USER of option bytes block after system reset */ +#define FMC_OBSTAT_DATA BITS(10,25) /*!< store DATA of option bytes block after system reset. */ + +/* FMC_WP */ +#define FMC_WP_WP BITS(0,31) /*!< store WP of option bytes block after system reset */ + +/* FMC_WSEN */ +#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */ + +/* FMC_PID */ +#define FMC_PID_PID BITS(0,31) /*!< product ID bits */ + +/* constants definitions */ +/* define the FMC bit position and its register index offset */ +#define FMC_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define FMC_REG_VAL(offset) (REG32(FMC + ((uint32_t)(offset) >> 6))) +#define FMC_BIT_POS(val) ((uint32_t)(val) & 0x1FU) +#define FMC_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) +#define FMC_REG_VALS(offset) (REG32(FMC + ((uint32_t)(offset) >> 12))) +#define FMC_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) +#define FMC_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) +#define FMC_REG_OFFSET_GET(flag) ((uint32_t)(flag) >> 12) + +/* configuration register */ +#define FMC_STAT_REG_OFFSET 0x0CU /*!< status register offset */ +#define FMC_CTL_REG_OFFSET 0x10U /*!< control register offset */ +#define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option byte status register offset */ + +/* fmc state */ +typedef enum +{ + FMC_READY, /*!< the operation has been completed */ + FMC_BUSY, /*!< the operation is in progress */ + FMC_PGERR, /*!< program error */ + FMC_WPERR, /*!< erase/program protection error */ + FMC_TOERR, /*!< timeout error */ +}fmc_state_enum; + +/* FMC interrupt enable */ +typedef enum +{ + FMC_INT_END = FMC_REGIDX_BIT(FMC_CTL_REG_OFFSET, 12U), /*!< enable FMC end of program interrupt */ + FMC_INT_ERR = FMC_REGIDX_BIT(FMC_CTL_REG_OFFSET, 10U), /*!< enable FMC error interrupt */ +}fmc_int_enum; + +/* FMC flags */ +typedef enum +{ + FMC_FLAG_BUSY = FMC_REGIDX_BIT(FMC_STAT_REG_OFFSET, 0U), /*!< FMC busy flag */ + FMC_FLAG_PGERR = FMC_REGIDX_BIT(FMC_STAT_REG_OFFSET, 2U), /*!< FMC operation error flag bit */ + FMC_FLAG_WPERR = FMC_REGIDX_BIT(FMC_STAT_REG_OFFSET, 4U), /*!< FMC erase/program protection error flag bit */ + FMC_FLAG_END = FMC_REGIDX_BIT(FMC_STAT_REG_OFFSET, 5U), /*!< FMC end of operation flag bit */ + FMC_FLAG_OBERR = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U), /*!< FMC option bytes read error flag */ +}fmc_flag_enum; + +/* FMC interrupt flags */ +typedef enum +{ + FMC_INT_FLAG_PGERR = FMC_REGIDX_BITS(FMC_STAT_REG_OFFSET, 2U, 10U), /*!< FMC operation error interrupt flag bit */ + FMC_INT_FLAG_WPERR = FMC_REGIDX_BITS(FMC_STAT_REG_OFFSET, 4U, 10U), /*!< FMC erase/program protection error interrupt flag bit */ + FMC_INT_FLAG_END = FMC_REGIDX_BITS(FMC_STAT_REG_OFFSET, 5U, 12U), /*!< FMC end of operation interrupt flag bit */ +}fmc_interrupt_flag_enum; + +/* unlock key */ +#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ +#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ + +/* FMC wait state counter */ +#define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval))) +#define WS_WSCNT_0 WS_WSCNT(0) /*!< FMC 0 wait */ +#define WS_WSCNT_1 WS_WSCNT(1) /*!< FMC 1 wait */ +#define WS_WSCNT_2 WS_WSCNT(2) /*!< FMC 2 wait */ + +/* option bytes software/hardware free watch dog timer */ +#define OB_FWDGT_SW ((uint8_t)0x01U) /*!< software free watchdog */ +#define OB_FWDGT_HW ((uint8_t)0x00U) /*!< hardware free watchdog */ + +/* option bytes reset or not entering deep sleep mode */ +#define OB_DEEPSLEEP_NRST ((uint8_t)0x02U) /*!< no reset when entering deepsleep mode */ +#define OB_DEEPSLEEP_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering deepsleep mode */ + +/* option bytes reset or not entering standby mode */ +#define OB_STDBY_NRST ((uint8_t)0x04U) /*!< no reset when entering deepsleep mode */ +#define OB_STDBY_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering standby mode */ + +/* option bytes boot bank value */ +#define OB_BOOT_B0 ((uint8_t)0x08U) /*!< boot from bank0 */ + +#define OB_USER_MASK ((uint8_t)0xF0U) /*!< MASK value */ + +/* read protect configure */ +#define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */ +#define FMC_USPC ((uint8_t)0xBBU) /*!< under security protection */ + +/* OB_SPC */ +#define OB_SPC_SPC ((uint32_t)0x000000FFU) /*!< option byte security protection value */ +#define OB_SPC_SPC_N ((uint32_t)0x0000FF00U) /*!< option byte security protection complement value */ + +/* OB_USER */ +#define OB_USER_USER ((uint32_t)0x00FF0000U) /*!< user option value */ +#define OB_USER_USER_N ((uint32_t)0xFF000000U) /*!< user option complement value */ + +/* OB_WP0 */ +#define OB_WP0_WP0 ((uint32_t)0x000000FFU) /*!< FMC write protection option value */ + +/* OB_WP1 */ +#define OB_WP1_WP1 ((uint32_t)0x0000FF00U) /*!< FMC write protection option complement value */ + +/* OB_WP2 */ +#define OB_WP2_WP2 ((uint32_t)0x00FF0000U) /*!< FMC write protection option value */ + +/* OB_WP3 */ +#define OB_WP3_WP3 ((uint32_t)0xFF000000U) /*!< FMC write protection option complement value */ + +/* option bytes write protection */ +#define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */ +#define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */ +#define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */ +#define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */ +#define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */ +#define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */ +#define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */ +#define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */ +#define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */ +#define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */ +#define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */ +#define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */ +#define OB_WP_12 ((uint32_t)0x00001000U) /*!< erase/program protection of sector 12 */ +#define OB_WP_13 ((uint32_t)0x00002000U) /*!< erase/program protection of sector 13 */ +#define OB_WP_14 ((uint32_t)0x00004000U) /*!< erase/program protection of sector 14 */ +#define OB_WP_15 ((uint32_t)0x00008000U) /*!< erase/program protection of sector 15 */ +#define OB_WP_16 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 16 */ +#define OB_WP_17 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 17 */ +#define OB_WP_18 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 18 */ +#define OB_WP_19 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 19 */ +#define OB_WP_20 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 20 */ +#define OB_WP_21 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 21 */ +#define OB_WP_22 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 22 */ +#define OB_WP_23 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 23 */ +#define OB_WP_24 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 24 */ +#define OB_WP_25 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 25 */ +#define OB_WP_26 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 26 */ +#define OB_WP_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 27 */ +#define OB_WP_28 ((uint32_t)0x10000000U) /*!< erase/program protection of sector 28 */ +#define OB_WP_29 ((uint32_t)0x20000000U) /*!< erase/program protection of sector 29 */ +#define OB_WP_30 ((uint32_t)0x40000000U) /*!< erase/program protection of sector 30 */ +#define OB_WP_31 ((uint32_t)0x80000000U) /*!< erase/program protection of sector 31 */ +#define OB_WP_ALL ((uint32_t)0xFFFFFFFFU) /*!< erase/program protection of all sectors */ + +/* FMC timeout */ +#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< FMC timeout count value */ + +/* FMC BANK address */ +#define FMC_SIZE (*(uint16_t *)0x1FFFF7E0U) /*!< FMC size */ +#define SRAM_SIZE (*(uint16_t *)0x1FFFF7E2U) /*!< SRAM size*/ + +/* function declarations */ +/* FMC main memory programming functions */ +/* set the FMC wait state counter */ +void fmc_wscnt_set(uint32_t wscnt); +/* unlock the main FMC operation */ +void fmc_unlock(void); +/* lock the main FMC operation */ +void fmc_lock(void); +/* FMC erase page */ +fmc_state_enum fmc_page_erase(uint32_t page_address); +/* FMC erase whole chip */ +fmc_state_enum fmc_mass_erase(void); +/* FMC program a word at the corresponding address */ +fmc_state_enum fmc_word_program(uint32_t address, uint32_t data); +/* FMC program a half word at the corresponding address */ +fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data); + +/* FMC option bytes programming functions */ +/* unlock the option byte operation */ +void ob_unlock(void); +/* lock the option byte operation */ +void ob_lock(void); +/* erase the FMC option byte */ +fmc_state_enum ob_erase(void); +/* enable write protection */ +fmc_state_enum ob_write_protection_enable(uint32_t ob_wp); +/* configure security protection */ +fmc_state_enum ob_security_protection_config(uint8_t ob_spc); +/* program the FMC user option byte */ +fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot); +/* program the FMC data option byte */ +fmc_state_enum ob_data_program(uint32_t address, uint8_t data); +/* get OB_USER in register FMC_OBSTAT */ +uint8_t ob_user_get(void); +/* get OB_DATA in register FMC_OBSTAT */ +uint16_t ob_data_get(void); +/* get the FMC option byte write protection */ +uint32_t ob_write_protection_get(void); +/* get FMC option byte security protection state */ +FlagStatus ob_spc_get(void); + +/* FMC interrupts and flags management functions */ +/* enable FMC interrupt */ +void fmc_interrupt_enable(uint32_t interrupt); +/* disable FMC interrupt */ +void fmc_interrupt_disable(uint32_t interrupt); +/* check flag is set or not */ +FlagStatus fmc_flag_get(uint32_t flag); +/* clear the FMC flag */ +void fmc_flag_clear(uint32_t flag); +/* get FMC interrupt flag state */ +FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag); +/* clear FMC interrupt flag state */ +void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag); +/* return the FMC state */ +fmc_state_enum fmc_state_get(void); +/* check FMC ready or not */ +fmc_state_enum fmc_ready_wait(uint32_t timeout); + +#endif /* GD32VF103_FMC_H */ diff --git a/cpu/gd32v/include/vendor/gd32vf103_fwdgt.h b/cpu/gd32v/include/vendor/gd32vf103_fwdgt.h new file mode 100644 index 0000000000..941cdc1057 --- /dev/null +++ b/cpu/gd32v/include/vendor/gd32vf103_fwdgt.h @@ -0,0 +1,104 @@ +/*! + \file gd32vf103_fwdgt.h + \brief definitions for the FWDGT + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_FWDGT_H +#define GD32VF103_FWDGT_H + +#include "gd32vf103.h" + +/* FWDGT definitions */ +#define FWDGT FWDGT_BASE /*!< FWDGT base address */ + +/* registers definitions */ +#define FWDGT_CTL REG32((FWDGT) + 0x00000000U) /*!< FWDGT control register */ +#define FWDGT_PSC REG32((FWDGT) + 0x00000004U) /*!< FWDGT prescaler register */ +#define FWDGT_RLD REG32((FWDGT) + 0x00000008U) /*!< FWDGT reload register */ +#define FWDGT_STAT REG32((FWDGT) + 0x0000000CU) /*!< FWDGT status register */ + +/* bits definitions */ +/* FWDGT_CTL */ +#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ + +/* FWDGT_PSC */ +#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ + +/* FWDGT_RLD */ +#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ + +/* FWDGT_STAT */ +#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ +#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */ + +/* constants definitions */ +/* psc register value */ +#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) +#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ +#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ +#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ +#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */ +#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */ +#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */ +#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */ + +/* control value */ +#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */ +#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */ +#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */ +#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */ + +/* FWDGT timeout value */ +#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */ +#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */ + +/* FWDGT flag definitions */ +#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */ +#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */ + +/* function declarations */ +/* enable write access to FWDGT_PSC and FWDGT_RLD */ +void fwdgt_write_enable(void); +/* disable write access to FWDGT_PSC and FWDGT_RLD */ +void fwdgt_write_disable(void); +/* start the free watchdog timer counter */ +void fwdgt_enable(void); + +/* reload the counter of FWDGT */ +void fwdgt_counter_reload(void); +/* configure counter reload value, and prescaler divider value */ +ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div); + +/* get flag state of FWDGT */ +FlagStatus fwdgt_flag_get(uint16_t flag); + +#endif /* GD32VF103_FWDGT_H */ diff --git a/cpu/gd32v/include/vendor/gd32vf103_gpio.h b/cpu/gd32v/include/vendor/gd32vf103_gpio.h new file mode 100644 index 0000000000..d547299d63 --- /dev/null +++ b/cpu/gd32v/include/vendor/gd32vf103_gpio.h @@ -0,0 +1,421 @@ +/*! + \file gd32vf103_gpio.h + \brief definitions for the GPIO + + \version 2019-06-5, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_GPIO_H +#define GD32VF103_GPIO_H + +#include "gd32vf103.h" + +/* GPIOx(x=A,B,C,D,E) definitions */ +#define GPIOA (GPIO_BASE + 0x00000000U) +#define GPIOB (GPIO_BASE + 0x00000400U) +#define GPIOC (GPIO_BASE + 0x00000800U) +#define GPIOD (GPIO_BASE + 0x00000C00U) +#define GPIOE (GPIO_BASE + 0x00001000U) + +/* AFIO definitions */ +#define AFIO AFIO_BASE + +/* registers definitions */ + +/* GPIO registers definitions */ +#define GPIO_CTL0(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register 0 */ +#define GPIO_CTL1(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port control register 1 */ +#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port input status register */ +#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port output control register */ +#define GPIO_BOP(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port bit operation register */ +#define GPIO_BC(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO bit clear register */ +#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port configuration lock register */ + +/* AFIO registers definitions */ +#define AFIO_EC REG32(AFIO + 0x00U) /*!< AFIO event control register */ +#define AFIO_PCF0 REG32(AFIO + 0x04U) /*!< AFIO port configuration register 0 */ +#define AFIO_EXTISS0 REG32(AFIO + 0x08U) /*!< AFIO port EXTI sources selection register 0 */ +#define AFIO_EXTISS1 REG32(AFIO + 0x0CU) /*!< AFIO port EXTI sources selection register 1 */ +#define AFIO_EXTISS2 REG32(AFIO + 0x10U) /*!< AFIO port EXTI sources selection register 2 */ +#define AFIO_EXTISS3 REG32(AFIO + 0x14U) /*!< AFIO port EXTI sources selection register 3 */ +#define AFIO_PCF1 REG32(AFIO + 0x1CU) /*!< AFIO port configuration register 1 */ + +/* bits definitions */ +/* GPIO_CTL0 */ +#define GPIO_CTL0_MD0 BITS(0, 1) /*!< port 0 mode bits */ +#define GPIO_CTL0_CTL0 BITS(2, 3) /*!< pin 0 configuration bits */ +#define GPIO_CTL0_MD1 BITS(4, 5) /*!< port 1 mode bits */ +#define GPIO_CTL0_CTL1 BITS(6, 7) /*!< pin 1 configuration bits */ +#define GPIO_CTL0_MD2 BITS(8, 9) /*!< port 2 mode bits */ +#define GPIO_CTL0_CTL2 BITS(10, 11) /*!< pin 2 configuration bits */ +#define GPIO_CTL0_MD3 BITS(12, 13) /*!< port 3 mode bits */ +#define GPIO_CTL0_CTL3 BITS(14, 15) /*!< pin 3 configuration bits */ +#define GPIO_CTL0_MD4 BITS(16, 17) /*!< port 4 mode bits */ +#define GPIO_CTL0_CTL4 BITS(18, 19) /*!< pin 4 configuration bits */ +#define GPIO_CTL0_MD5 BITS(20, 21) /*!< port 5 mode bits */ +#define GPIO_CTL0_CTL5 BITS(22, 23) /*!< pin 5 configuration bits */ +#define GPIO_CTL0_MD6 BITS(24, 25) /*!< port 6 mode bits */ +#define GPIO_CTL0_CTL6 BITS(26, 27) /*!< pin 6 configuration bits */ +#define GPIO_CTL0_MD7 BITS(28, 29) /*!< port 7 mode bits */ +#define GPIO_CTL0_CTL7 BITS(30, 31) /*!< pin 7 configuration bits */ + +/* GPIO_CTL1 */ +#define GPIO_CTL1_MD8 BITS(0, 1) /*!< port 8 mode bits */ +#define GPIO_CTL1_CTL8 BITS(2, 3) /*!< pin 8 configuration bits */ +#define GPIO_CTL1_MD9 BITS(4, 5) /*!< port 9 mode bits */ +#define GPIO_CTL1_CTL9 BITS(6, 7) /*!< pin 9 configuration bits */ +#define GPIO_CTL1_MD10 BITS(8, 9) /*!< port 10 mode bits */ +#define GPIO_CTL1_CTL10 BITS(10, 11) /*!< pin 10 configuration bits */ +#define GPIO_CTL1_MD11 BITS(12, 13) /*!< port 11 mode bits */ +#define GPIO_CTL1_CTL11 BITS(14, 15) /*!< pin 11 configuration bits */ +#define GPIO_CTL1_MD12 BITS(16, 17) /*!< port 12 mode bits */ +#define GPIO_CTL1_CTL12 BITS(18, 19) /*!< pin 12 configuration bits */ +#define GPIO_CTL1_MD13 BITS(20, 21) /*!< port 13 mode bits */ +#define GPIO_CTL1_CTL13 BITS(22, 23) /*!< pin 13 configuration bits */ +#define GPIO_CTL1_MD14 BITS(24, 25) /*!< port 14 mode bits */ +#define GPIO_CTL1_CTL14 BITS(26, 27) /*!< pin 14 configuration bits */ +#define GPIO_CTL1_MD15 BITS(28, 29) /*!< port 15 mode bits */ +#define GPIO_CTL1_CTL15 BITS(30, 31) /*!< pin 15 configuration bits */ + +/* GPIO_ISTAT */ +#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ +#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */ +#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */ +#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */ +#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */ +#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */ +#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */ +#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */ +#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */ +#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */ +#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */ +#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */ +#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */ +#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */ +#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */ +#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ + +/* GPIO_OCTL */ +#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */ +#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */ +#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */ +#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */ +#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */ +#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */ +#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */ +#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */ +#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */ +#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */ +#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */ +#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */ +#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */ +#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */ +#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */ +#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */ + +/* GPIO_BOP */ +#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ +#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */ +#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */ +#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */ +#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */ +#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */ +#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */ +#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */ +#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */ +#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */ +#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */ +#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */ +#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */ +#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */ +#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */ +#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */ +#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */ +#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */ +#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */ +#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */ +#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */ +#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */ +#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */ +#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */ +#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */ +#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */ +#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */ +#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */ +#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */ +#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */ +#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */ +#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */ + +/* GPIO_BC */ +#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */ +#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */ +#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */ +#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */ +#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */ +#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */ +#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */ +#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */ +#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */ +#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */ +#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */ +#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */ +#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */ +#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */ +#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */ +#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */ + +/* GPIO_LOCK */ +#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */ +#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */ +#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */ +#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */ +#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */ +#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */ +#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */ +#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */ +#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */ +#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */ +#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */ +#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */ +#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */ +#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ +#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ +#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ +#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ + +/* AFIO_EC */ +#define AFIO_EC_PIN BITS(0, 3) /*!< event output pin selection */ +#define AFIO_EC_PORT BITS(4, 6) /*!< event output port selection */ +#define AFIO_EC_EOE BIT(7) /*!< event output enable */ + +/* AFIO_PCF0 */ +#define AFIO_PCF0_SPI0_REMAP BIT(0) /*!< SPI0 remapping */ +#define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ +#define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ +#define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ +#define AFIO_PCF0_USART2_REMAP BITS(4, 5) /*!< USART2 remapping */ +#define AFIO_PCF0_TIMER0_REMAP BITS(6, 7) /*!< TIMER0 remapping */ +#define AFIO_PCF0_TIMER1_REMAP BITS(8, 9) /*!< TIMER1 remapping */ +#define AFIO_PCF0_TIMER2_REMAP BITS(10, 11) /*!< TIMER2 remapping */ +#define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ +#define AFIO_PCF0_CAN_REMAP BITS(13, 14) /*!< CAN remapping */ +#define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER3 channel3 internal remapping */ +#define AFIO_PCF0_SWJ_CFG BITS(24, 26) /*!< serial wire JTAG configuration */ +#define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */ +#define AFIO_PCF0_TIMER1_ITI1_REMAP BIT(29) /*!< TIMER1 internal trigger 1 remapping */ + +/* AFIO_EXTISS0 */ +#define AFIO_EXTI0_SS BITS(0, 3) /*!< EXTI 0 sources selection */ +#define AFIO_EXTI1_SS BITS(4, 7) /*!< EXTI 1 sources selection */ +#define AFIO_EXTI2_SS BITS(8, 11) /*!< EXTI 2 sources selection */ +#define AFIO_EXTI3_SS BITS(12, 15) /*!< EXTI 3 sources selection */ + +/* AFIO_EXTISS1 */ +#define AFIO_EXTI4_SS BITS(0, 3) /*!< EXTI 4 sources selection */ +#define AFIO_EXTI5_SS BITS(4, 7) /*!< EXTI 5 sources selection */ +#define AFIO_EXTI6_SS BITS(8, 11) /*!< EXTI 6 sources selection */ +#define AFIO_EXTI7_SS BITS(12, 15) /*!< EXTI 7 sources selection */ + +/* AFIO_EXTISS2 */ +#define AFIO_EXTI8_SS BITS(0, 3) /*!< EXTI 8 sources selection */ +#define AFIO_EXTI9_SS BITS(4, 7) /*!< EXTI 9 sources selection */ +#define AFIO_EXTI10_SS BITS(8, 11) /*!< EXTI 10 sources selection */ +#define AFIO_EXTI11_SS BITS(12, 15) /*!< EXTI 11 sources selection */ + +/* AFIO_EXTISS3 */ +#define AFIO_EXTI12_SS BITS(0, 3) /*!< EXTI 12 sources selection */ +#define AFIO_EXTI13_SS BITS(4, 7) /*!< EXTI 13 sources selection */ +#define AFIO_EXTI14_SS BITS(8, 11) /*!< EXTI 14 sources selection */ +#define AFIO_EXTI15_SS BITS(12, 15) /*!< EXTI 15 sources selection */ + +/* AFIO_PCF1 */ +#define AFIO_PCF1_EXMC_NADV BIT(10) /*!< EXMC_NADV connect/disconnect */ + +/* constants definitions */ +typedef FlagStatus bit_status; + +/* GPIO mode values set */ +#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (4U * (n)))) +#define GPIO_MODE_MASK(n) (0xFU << (4U * (n))) + +/* GPIO mode definitions */ +#define GPIO_MODE_AIN ((uint8_t)0x00U) /*!< analog input mode */ +#define GPIO_MODE_IN_FLOATING ((uint8_t)0x04U) /*!< floating input mode */ +#define GPIO_MODE_IPD ((uint8_t)0x28U) /*!< pull-down input mode */ +#define GPIO_MODE_IPU ((uint8_t)0x48U) /*!< pull-up input mode */ +#define GPIO_MODE_OUT_OD ((uint8_t)0x14U) /*!< GPIO output with open-drain */ +#define GPIO_MODE_OUT_PP ((uint8_t)0x10U) /*!< GPIO output with push-pull */ +#define GPIO_MODE_AF_OD ((uint8_t)0x1CU) /*!< AFIO output with open-drain */ +#define GPIO_MODE_AF_PP ((uint8_t)0x18U) /*!< AFIO output with push-pull */ + +/* GPIO output max speed value */ +#define GPIO_OSPEED_10MHZ ((uint8_t)0x01U) /*!< output max speed 10MHz */ +#define GPIO_OSPEED_2MHZ ((uint8_t)0x02U) /*!< output max speed 2MHz */ +#define GPIO_OSPEED_50MHZ ((uint8_t)0x03U) /*!< output max speed 50MHz */ + +/* GPIO event output port definitions */ +#define GPIO_EVENT_PORT_GPIOA ((uint8_t)0x00U) /*!< event output port A */ +#define GPIO_EVENT_PORT_GPIOB ((uint8_t)0x01U) /*!< event output port B */ +#define GPIO_EVENT_PORT_GPIOC ((uint8_t)0x02U) /*!< event output port C */ +#define GPIO_EVENT_PORT_GPIOD ((uint8_t)0x03U) /*!< event output port D */ +#define GPIO_EVENT_PORT_GPIOE ((uint8_t)0x04U) /*!< event output port E */ + +/* GPIO output port source definitions */ +#define GPIO_PORT_SOURCE_GPIOA ((uint8_t)0x00U) /*!< output port source A */ +#define GPIO_PORT_SOURCE_GPIOB ((uint8_t)0x01U) /*!< output port source B */ +#define GPIO_PORT_SOURCE_GPIOC ((uint8_t)0x02U) /*!< output port source C */ +#define GPIO_PORT_SOURCE_GPIOD ((uint8_t)0x03U) /*!< output port source D */ +#define GPIO_PORT_SOURCE_GPIOE ((uint8_t)0x04U) /*!< output port source E */ + +/* GPIO event output pin definitions */ +#define GPIO_EVENT_PIN_0 ((uint8_t)0x00U) /*!< GPIO event pin 0 */ +#define GPIO_EVENT_PIN_1 ((uint8_t)0x01U) /*!< GPIO event pin 1 */ +#define GPIO_EVENT_PIN_2 ((uint8_t)0x02U) /*!< GPIO event pin 2 */ +#define GPIO_EVENT_PIN_3 ((uint8_t)0x03U) /*!< GPIO event pin 3 */ +#define GPIO_EVENT_PIN_4 ((uint8_t)0x04U) /*!< GPIO event pin 4 */ +#define GPIO_EVENT_PIN_5 ((uint8_t)0x05U) /*!< GPIO event pin 5 */ +#define GPIO_EVENT_PIN_6 ((uint8_t)0x06U) /*!< GPIO event pin 6 */ +#define GPIO_EVENT_PIN_7 ((uint8_t)0x07U) /*!< GPIO event pin 7 */ +#define GPIO_EVENT_PIN_8 ((uint8_t)0x08U) /*!< GPIO event pin 8 */ +#define GPIO_EVENT_PIN_9 ((uint8_t)0x09U) /*!< GPIO event pin 9 */ +#define GPIO_EVENT_PIN_10 ((uint8_t)0x0AU) /*!< GPIO event pin 10 */ +#define GPIO_EVENT_PIN_11 ((uint8_t)0x0BU) /*!< GPIO event pin 11 */ +#define GPIO_EVENT_PIN_12 ((uint8_t)0x0CU) /*!< GPIO event pin 12 */ +#define GPIO_EVENT_PIN_13 ((uint8_t)0x0DU) /*!< GPIO event pin 13 */ +#define GPIO_EVENT_PIN_14 ((uint8_t)0x0EU) /*!< GPIO event pin 14 */ +#define GPIO_EVENT_PIN_15 ((uint8_t)0x0FU) /*!< GPIO event pin 15 */ + +/* GPIO output pin source definitions */ +#define GPIO_PIN_SOURCE_0 ((uint8_t)0x00U) /*!< GPIO pin source 0 */ +#define GPIO_PIN_SOURCE_1 ((uint8_t)0x01U) /*!< GPIO pin source 1 */ +#define GPIO_PIN_SOURCE_2 ((uint8_t)0x02U) /*!< GPIO pin source 2 */ +#define GPIO_PIN_SOURCE_3 ((uint8_t)0x03U) /*!< GPIO pin source 3 */ +#define GPIO_PIN_SOURCE_4 ((uint8_t)0x04U) /*!< GPIO pin source 4 */ +#define GPIO_PIN_SOURCE_5 ((uint8_t)0x05U) /*!< GPIO pin source 5 */ +#define GPIO_PIN_SOURCE_6 ((uint8_t)0x06U) /*!< GPIO pin source 6 */ +#define GPIO_PIN_SOURCE_7 ((uint8_t)0x07U) /*!< GPIO pin source 7 */ +#define GPIO_PIN_SOURCE_8 ((uint8_t)0x08U) /*!< GPIO pin source 8 */ +#define GPIO_PIN_SOURCE_9 ((uint8_t)0x09U) /*!< GPIO pin source 9 */ +#define GPIO_PIN_SOURCE_10 ((uint8_t)0x0AU) /*!< GPIO pin source 10 */ +#define GPIO_PIN_SOURCE_11 ((uint8_t)0x0BU) /*!< GPIO pin source 11 */ +#define GPIO_PIN_SOURCE_12 ((uint8_t)0x0CU) /*!< GPIO pin source 12 */ +#define GPIO_PIN_SOURCE_13 ((uint8_t)0x0DU) /*!< GPIO pin source 13 */ +#define GPIO_PIN_SOURCE_14 ((uint8_t)0x0EU) /*!< GPIO pin source 14 */ +#define GPIO_PIN_SOURCE_15 ((uint8_t)0x0FU) /*!< GPIO pin source 15 */ + +/* GPIO pin definitions */ +#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */ +#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */ +#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */ +#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */ +#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */ +#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */ +#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */ +#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */ +#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */ +#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */ +#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */ +#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */ +#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */ +#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ +#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ +#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ +#define GPIO_PIN_ALL BITS(0, 15) /*!< GPIO pin all */ + +/* GPIO remap definitions */ +#define GPIO_SPI0_REMAP ((uint32_t)0x00000001U) /*!< SPI0 remapping */ +#define GPIO_I2C0_REMAP ((uint32_t)0x00000002U) /*!< I2C0 remapping */ +#define GPIO_USART0_REMAP ((uint32_t)0x00000004U) /*!< USART0 remapping */ +#define GPIO_USART1_REMAP ((uint32_t)0x00000008U) /*!< USART1 remapping */ +#define GPIO_USART2_PARTIAL_REMAP ((uint32_t)0x00140010U) /*!< USART2 partial remapping */ +#define GPIO_USART2_FULL_REMAP ((uint32_t)0x00140030U) /*!< USART2 full remapping */ +#define GPIO_TIMER0_PARTIAL_REMAP ((uint32_t)0x00160040U) /*!< TIMER0 partial remapping */ +#define GPIO_TIMER0_FULL_REMAP ((uint32_t)0x001600C0U) /*!< TIMER0 full remapping */ +#define GPIO_TIMER1_PARTIAL_REMAP0 ((uint32_t)0x00180100U) /*!< TIMER1 partial remapping */ +#define GPIO_TIMER1_PARTIAL_REMAP1 ((uint32_t)0x00180200U) /*!< TIMER1 partial remapping */ +#define GPIO_TIMER1_FULL_REMAP ((uint32_t)0x00180300U) /*!< TIMER1 full remapping */ +#define GPIO_TIMER2_PARTIAL_REMAP ((uint32_t)0x001A0800U) /*!< TIMER2 partial remapping */ +#define GPIO_TIMER2_FULL_REMAP ((uint32_t)0x001A0C00U) /*!< TIMER2 full remapping */ +#define GPIO_TIMER3_REMAP ((uint32_t)0x00001000U) /*!< TIMER3 remapping */ +#define GPIO_CAN0_PARTIAL_REMAP ((uint32_t)0x001D4000U) /*!< CAN0 partial remapping */ +#define GPIO_CAN0_FULL_REMAP ((uint32_t)0x001D6000U) /*!< CAN0 full remapping */ +#define GPIO_PD01_REMAP ((uint32_t)0x00008000U) /*!< PD01 remapping */ +#define GPIO_TIMER4CH3_IREMAP ((uint32_t)0x00200001U) /*!< TIMER4 channel3 internal remapping */ +#define GPIO_CAN1_REMAP ((uint32_t)0x00200040U) /*!< CAN1 remapping */ +#define GPIO_SWJ_NONJTRST_REMAP ((uint32_t)0x00300100U) /*!< JTAG-DP,but without NJTRST */ +#define GPIO_SWJ_DISABLE_REMAP ((uint32_t)0x00300200U) /*!< JTAG-DP disabled */ +#define GPIO_SPI2_REMAP ((uint32_t)0x00201100U) /*!< SPI2 remapping */ +#define GPIO_TIMER1ITI1_REMAP ((uint32_t)0x00202000U) /*!< TIMER1 internal trigger 1 remapping */ +#define GPIO_EXMC_NADV_REMAP ((uint32_t)0x80000400U) /*!< EXMC_NADV connect/disconnect */ + +/* function declarations */ +/* reset GPIO port */ +void gpio_deinit(uint32_t gpio_periph); +/* reset alternate function I/O(AFIO) */ +void gpio_afio_deinit(void); +/* GPIO parameter initialization */ +void gpio_init(uint32_t gpio_periph,uint32_t mode,uint32_t speed,uint32_t pin); + +/* set GPIO pin bit */ +void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); +/* reset GPIO pin bit */ +void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); +/* write data to the specified GPIO pin */ +void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); +/* write data to the specified GPIO port */ +void gpio_port_write(uint32_t gpio_periph, uint16_t data); + +/* get GPIO pin input status */ +FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin); +/* get GPIO port input status */ +uint16_t gpio_input_port_get(uint32_t gpio_periph); +/* get GPIO pin output status */ +FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin); +/* get GPIO port output status */ +uint16_t gpio_output_port_get(uint32_t gpio_periph); + +/* configure GPIO pin remap */ +void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue); + +/* select GPIO pin exti sources */ +void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin); +/* configure GPIO pin event output */ +void gpio_event_output_config(uint8_t output_port, uint8_t output_pin); +/* enable GPIO pin event output */ +void gpio_event_output_enable(void); +/* disable GPIO pin event output */ +void gpio_event_output_disable(void); + +/* lock GPIO pin bit */ +void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin); + +#endif /* GD32VF103_GPIO_H */ diff --git a/cpu/gd32v/include/vendor/gd32vf103_i2c.h b/cpu/gd32v/include/vendor/gd32vf103_i2c.h new file mode 100644 index 0000000000..404063b351 --- /dev/null +++ b/cpu/gd32v/include/vendor/gd32vf103_i2c.h @@ -0,0 +1,276 @@ +/*! + \file gd32vf103_i2c.h + \brief definitions for the I2C + + \version 2019-06-05, V1.0.1, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_I2C_H +#define GD32VF103_I2C_H + +#include "gd32vf103.h" + +/* I2Cx(x=0,1) definitions */ +#define I2C0 I2C_BASE /*!< I2C0 base address */ +#define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */ + +/* registers definitions */ +#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */ +#define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */ +#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0*/ +#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register */ +#define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register */ +#define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register 0 */ +#define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register */ +#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU) /*!< I2C clock configure register */ +#define I2C_RT(i2cx) REG32((i2cx) + 0x20U) /*!< I2C rise time register */ +#define I2C_FMPCFG(i2cx) REG32((i2cx) + 0x90U) /*!< I2C fast-mode-plus configure register */ +/* bits definitions */ +/* I2Cx_CTL0 */ +#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ +#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ +#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ +#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ +#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ +#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ +#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */ +#define I2C_CTL0_START BIT(8) /*!< start generation */ +#define I2C_CTL0_STOP BIT(9) /*!< stop generation */ +#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ +#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ +#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ +#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ +#define I2C_CTL0_SRESET BIT(15) /*!< software reset */ + +/* I2Cx_CTL1 */ +#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ +#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ +#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ +#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ +#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ +#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ + +/* I2Cx_SADDR0 */ +#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ +#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ + +/* I2Cx_SADDR1 */ +#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ +#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ + +/* I2Cx_DATA */ +#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ + +/* I2Cx_STAT0 */ +#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ +#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ +#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ +#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ +#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ +#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ +#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ +#define I2C_STAT0_BERR BIT(8) /*!< bus error */ +#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ +#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ +#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ +#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ +#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ +#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ + +/* I2Cx_STAT1 */ +#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ +#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ +#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */ +#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ +#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ +#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ +#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ +#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ + +/* I2Cx_CKCFG */ +#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */ +#define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */ +#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ + +/* I2Cx_RT */ +#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */ + +/* I2Cx_FMPCFG */ +#define I2C_FMPCFG_FMPEN BIT(0) /*!< fast mode plus enable bit */ + +/* constants definitions */ +/* define the I2C bit position and its register index offset */ +#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) +#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x1FU) +#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) +#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) +#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) + +/* register offset */ +#define I2C_CTL1_REG_OFFSET 0x04U /*!< CTL1 register offset */ +#define I2C_STAT0_REG_OFFSET 0x14U /*!< STAT0 register offset */ +#define I2C_STAT1_REG_OFFSET 0x18U /*!< STAT1 register offset */ + +/* I2C flags */ +typedef enum { + /* flags in STAT0 register */ + I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ + I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ + I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ + I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ + I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ + I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving */ + I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ + I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ + I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ + I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ + I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ + I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ + I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ + I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ + /* flags in STAT1 register */ + I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ + I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ + I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ + I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ + I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ + I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ + I2C_FLAG_DUMODF = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ +} i2c_flag_enum; + +/* I2C interrupt flags */ +typedef enum { + /* interrupt flags in CTL1 register */ + I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */ + I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ + I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ + I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */ + I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */ + I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */ + I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ + I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ + I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */ + I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */ + I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */ + I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */ + I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */ + I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */ +} i2c_interrupt_flag_enum; + +/* I2C interrupt enable or disable */ +typedef enum { + /* interrupt in CTL1 register */ + I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */ + I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */ + I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */ +} i2c_interrupt_enum; + +/* SMBus/I2C mode switch and SMBus type selection */ +#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ +#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ + +/* SMBus/I2C mode switch and SMBus type selection */ +#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ +#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ + +/* I2C transfer direction */ +#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ +#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ + +/* whether or not to send an ACK */ +#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ +#define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */ + +/* I2C POAP position*/ +#define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */ +#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ + +/* I2C dual-address mode switch */ +#define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U) /*!< dual-address mode disabled */ +#define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U) /*!< dual-address mode enabled */ + +/* whether or not to stretch SCL low */ +#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is enabled */ +#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< SCL stretching is disabled */ + +/* whether or not to response to a general call */ +#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ +#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ + +/* software reset I2C */ +#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ +#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ + +/* I2C DMA mode configure */ +/* DMA mode switch */ +#define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */ +#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */ + +/* flag indicating DMA last transfer */ +#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ +#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ + +/* I2C PEC configure */ +/* PEC enable */ +#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ +#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ + +/* PEC transfer */ +#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */ +#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ + +/* I2C SMBus configure */ +/* issue or not alert through SMBA pin */ +#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ +#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ + +/* ARP protocol in SMBus switch */ +#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP enable */ +#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP disable */ + +/* transmit I2C data */ +#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* receive I2C data */ +#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) + +/* I2C duty cycle in fast mode */ +#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< I2C fast mode Tlow/Thigh = 2 */ +#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< I2C fast mode Tlow/Thigh = 16/9 */ + +/* address mode for the I2C slave */ +#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */ +#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */ + +#endif /* GD32VF103_I2C_H */ diff --git a/cpu/gd32v/include/vendor/gd32vf103_periph.h b/cpu/gd32v/include/vendor/gd32vf103_periph.h new file mode 100644 index 0000000000..2b7727bb98 --- /dev/null +++ b/cpu/gd32v/include/vendor/gd32vf103_periph.h @@ -0,0 +1,21813 @@ +/* + * @note Generated by SVDConv V3.3.35 on Tuesday, 01.09.2020 17:58:39 + * from File 'GD32VF103.svd', + */ + +#ifndef GD32VF103_PERIPH_H +#define GD32VF103_PERIPH_H + +#include "stdint.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* =========================================================================================================================== */ +/* ================ ADC0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Analog to digital converter (ADC0) + */ + +typedef struct { /*!< (@ 0x40012400) ADC0 Structure */ + + union { + __IO uint32_t STAT; /*!< (@ 0x00000000) status register */ + + struct { + __IO uint32_t WDE : 1; /*!< [0..0] Analog watchdog event flag */ + __IO uint32_t EOC : 1; /*!< [1..1] End of group conversion flag */ + __IO uint32_t EOIC : 1; /*!< [2..2] End of inserted group conversion flag */ + __IO uint32_t STIC : 1; /*!< [3..3] Start flag of inserted channel group */ + __IO uint32_t STRC : 1; /*!< [4..4] Start flag of regular channel group */ + uint32_t : 27; + } STAT_b; + } ; + + union { + __IO uint32_t CTL0; /*!< (@ 0x00000004) control register 0 */ + + struct { + __IO uint32_t WDCHSEL : 5; /*!< [4..0] Analog watchdog channel select */ + __IO uint32_t EOCIE : 1; /*!< [5..5] Interrupt enable for EOC */ + __IO uint32_t WDEIE : 1; /*!< [6..6] Interrupt enable for WDE */ + __IO uint32_t EOICIE : 1; /*!< [7..7] Interrupt enable for EOIC */ + __IO uint32_t SM : 1; /*!< [8..8] Scan mode */ + __IO uint32_t WDSC : 1; /*!< [9..9] When in scan mode, analog watchdog is effective on a + single channel */ + __IO uint32_t ICA : 1; /*!< [10..10] Inserted channel group convert automatically */ + __IO uint32_t DISRC : 1; /*!< [11..11] Discontinuous mode on regular channels */ + __IO uint32_t DISIC : 1; /*!< [12..12] Discontinuous mode on inserted channels */ + __IO uint32_t DISNUM : 3; /*!< [15..13] Number of conversions in discontinuous mode */ + __IO uint32_t SYNCM : 4; /*!< [19..16] sync mode selection */ + uint32_t : 2; + __IO uint32_t IWDEN : 1; /*!< [22..22] Inserted channel analog watchdog enable */ + __IO uint32_t RWDEN : 1; /*!< [23..23] Regular channel analog watchdog enable */ + uint32_t : 8; + } CTL0_b; + } ; + + union { + __IO uint32_t CTL1; /*!< (@ 0x00000008) control register 1 */ + + struct { + __IO uint32_t ADCON : 1; /*!< [0..0] ADC on */ + __IO uint32_t CTN : 1; /*!< [1..1] Continuous mode */ + __IO uint32_t CLB : 1; /*!< [2..2] ADC calibration */ + __IO uint32_t RSTCLB : 1; /*!< [3..3] Reset calibration */ + uint32_t : 4; + __IO uint32_t DMA : 1; /*!< [8..8] DMA request enable */ + uint32_t : 2; + __IO uint32_t DAL : 1; /*!< [11..11] Data alignment */ + __IO uint32_t ETSIC : 3; /*!< [14..12] External trigger select for inserted channel */ + __IO uint32_t ETEIC : 1; /*!< [15..15] External trigger select for inserted channel */ + uint32_t : 1; + __IO uint32_t ETSRC : 3; /*!< [19..17] External trigger select for regular channel */ + __IO uint32_t ETERC : 1; /*!< [20..20] External trigger enable for regular channel */ + __IO uint32_t SWICST : 1; /*!< [21..21] Start on inserted channel */ + __IO uint32_t SWRCST : 1; /*!< [22..22] Start on regular channel */ + __IO uint32_t TSVREN : 1; /*!< [23..23] Channel 16 and 17 enable of ADC0 */ + uint32_t : 8; + } CTL1_b; + } ; + + union { + __IO uint32_t SAMPT0; /*!< (@ 0x0000000C) Sample time register 0 */ + + struct { + __IO uint32_t SPT10 : 3; /*!< [2..0] Channel 10 sample time selection */ + __IO uint32_t SPT11 : 3; /*!< [5..3] Channel 11 sample time selection */ + __IO uint32_t SPT12 : 3; /*!< [8..6] Channel 12 sample time selection */ + __IO uint32_t SPT13 : 3; /*!< [11..9] Channel 13 sample time selection */ + __IO uint32_t SPT14 : 3; /*!< [14..12] Channel 14 sample time selection */ + __IO uint32_t SPT15 : 3; /*!< [17..15] Channel 15 sample time selection */ + __IO uint32_t SPT16 : 3; /*!< [20..18] Channel 16 sample time selection */ + __IO uint32_t SPT17 : 3; /*!< [23..21] Channel 17 sample time selection */ + uint32_t : 8; + } SAMPT0_b; + } ; + + union { + __IO uint32_t SAMPT1; /*!< (@ 0x00000010) Sample time register 1 */ + + struct { + __IO uint32_t SPT0 : 3; /*!< [2..0] Channel 0 sample time selection */ + __IO uint32_t SPT1 : 3; /*!< [5..3] Channel 1 sample time selection */ + __IO uint32_t SPT2 : 3; /*!< [8..6] Channel 2 sample time selection */ + __IO uint32_t SPT3 : 3; /*!< [11..9] Channel 3 sample time selection */ + __IO uint32_t SPT4 : 3; /*!< [14..12] Channel 4 sample time selection */ + __IO uint32_t SPT5 : 3; /*!< [17..15] Channel 5 sample time selection */ + __IO uint32_t SPT6 : 3; /*!< [20..18] Channel 6 sample time selection */ + __IO uint32_t SPT7 : 3; /*!< [23..21] Channel 7 sample time selection */ + __IO uint32_t SPT8 : 3; /*!< [26..24] Channel 8 sample time selection */ + __IO uint32_t SPT9 : 3; /*!< [29..27] Channel 9 sample time selection */ + uint32_t : 2; + } SAMPT1_b; + } ; + + union { + __IO uint32_t IOFF0; /*!< (@ 0x00000014) Inserted channel data offset register 0 */ + + struct { + __IO uint32_t IOFF : 12; /*!< [11..0] Data offset for inserted channel 0 */ + uint32_t : 20; + } IOFF0_b; + } ; + + union { + __IO uint32_t IOFF1; /*!< (@ 0x00000018) Inserted channel data offset register 1 */ + + struct { + __IO uint32_t IOFF : 12; /*!< [11..0] Data offset for inserted channel 1 */ + uint32_t : 20; + } IOFF1_b; + } ; + + union { + __IO uint32_t IOFF2; /*!< (@ 0x0000001C) Inserted channel data offset register 2 */ + + struct { + __IO uint32_t IOFF : 12; /*!< [11..0] Data offset for inserted channel 2 */ + uint32_t : 20; + } IOFF2_b; + } ; + + union { + __IO uint32_t IOFF3; /*!< (@ 0x00000020) Inserted channel data offset register 3 */ + + struct { + __IO uint32_t IOFF : 12; /*!< [11..0] Data offset for inserted channel 3 */ + uint32_t : 20; + } IOFF3_b; + } ; + + union { + __IO uint32_t WDHT; /*!< (@ 0x00000024) watchdog higher threshold register */ + + struct { + __IO uint32_t WDHT : 12; /*!< [11..0] Analog watchdog higher threshold */ + uint32_t : 20; + } WDHT_b; + } ; + + union { + __IO uint32_t WDLT; /*!< (@ 0x00000028) watchdog lower threshold register */ + + struct { + __IO uint32_t WDLT : 12; /*!< [11..0] Analog watchdog lower threshold */ + uint32_t : 20; + } WDLT_b; + } ; + + union { + __IO uint32_t RSQ0; /*!< (@ 0x0000002C) regular sequence register 0 */ + + struct { + __IO uint32_t RSQ12 : 5; /*!< [4..0] 13th conversion in regular sequence */ + __IO uint32_t RSQ13 : 5; /*!< [9..5] 14th conversion in regular sequence */ + __IO uint32_t RSQ14 : 5; /*!< [14..10] 15th conversion in regular sequence */ + __IO uint32_t RSQ15 : 5; /*!< [19..15] 16th conversion in regular sequence */ + __IO uint32_t RL : 4; /*!< [23..20] Regular channel group length */ + uint32_t : 8; + } RSQ0_b; + } ; + + union { + __IO uint32_t RSQ1; /*!< (@ 0x00000030) regular sequence register 1 */ + + struct { + __IO uint32_t RSQ6 : 5; /*!< [4..0] 7th conversion in regular sequence */ + __IO uint32_t RSQ7 : 5; /*!< [9..5] 8th conversion in regular sequence */ + __IO uint32_t RSQ8 : 5; /*!< [14..10] 9th conversion in regular sequence */ + __IO uint32_t RSQ9 : 5; /*!< [19..15] 10th conversion in regular sequence */ + __IO uint32_t RSQ10 : 5; /*!< [24..20] 11th conversion in regular sequence */ + __IO uint32_t RSQ11 : 5; /*!< [29..25] 12th conversion in regular sequence */ + uint32_t : 2; + } RSQ1_b; + } ; + + union { + __IO uint32_t RSQ2; /*!< (@ 0x00000034) regular sequence register 2 */ + + struct { + __IO uint32_t RSQ0 : 5; /*!< [4..0] 1st conversion in regular sequence */ + __IO uint32_t RSQ1 : 5; /*!< [9..5] 2nd conversion in regular sequence */ + __IO uint32_t RSQ2 : 5; /*!< [14..10] 3rd conversion in regular sequence */ + __IO uint32_t RSQ3 : 5; /*!< [19..15] 4th conversion in regular sequence */ + __IO uint32_t RSQ4 : 5; /*!< [24..20] 5th conversion in regular sequence */ + __IO uint32_t RSQ5 : 5; /*!< [29..25] 6th conversion in regular sequence */ + uint32_t : 2; + } RSQ2_b; + } ; + + union { + __IO uint32_t ISQ; /*!< (@ 0x00000038) Inserted sequence register */ + + struct { + __IO uint32_t ISQ0 : 5; /*!< [4..0] 1st conversion in inserted sequence */ + __IO uint32_t ISQ1 : 5; /*!< [9..5] 2nd conversion in inserted sequence */ + __IO uint32_t ISQ2 : 5; /*!< [14..10] 3rd conversion in inserted sequence */ + __IO uint32_t ISQ3 : 5; /*!< [19..15] 4th conversion in inserted sequence */ + __IO uint32_t IL : 2; /*!< [21..20] Inserted channel group length */ + uint32_t : 10; + } ISQ_b; + } ; + + union { + __I uint32_t IDATA0; /*!< (@ 0x0000003C) Inserted data register 0 */ + + struct { + __I uint32_t IDATAn : 16; /*!< [15..0] Inserted number n conversion data */ + uint32_t : 16; + } IDATA0_b; + } ; + + union { + __I uint32_t IDATA1; /*!< (@ 0x00000040) Inserted data register 1 */ + + struct { + __I uint32_t IDATAn : 16; /*!< [15..0] Inserted number n conversion data */ + uint32_t : 16; + } IDATA1_b; + } ; + + union { + __I uint32_t IDATA2; /*!< (@ 0x00000044) Inserted data register 2 */ + + struct { + __I uint32_t IDATAn : 16; /*!< [15..0] Inserted number n conversion data */ + uint32_t : 16; + } IDATA2_b; + } ; + + union { + __I uint32_t IDATA3; /*!< (@ 0x00000048) Inserted data register 3 */ + + struct { + __I uint32_t IDATAn : 16; /*!< [15..0] Inserted number n conversion data */ + uint32_t : 16; + } IDATA3_b; + } ; + + union { + __I uint32_t RDATA; /*!< (@ 0x0000004C) regular data register */ + + struct { + __I uint32_t RDATA : 16; /*!< [15..0] Regular channel data */ + __I uint32_t ADC1RDTR : 16; /*!< [31..16] ADC regular channel data */ + } RDATA_b; + } ; + __I uint32_t RESERVED[12]; + + union { + __IO uint32_t OVSAMPCTL; /*!< (@ 0x00000080) Oversample control register */ + + struct { + __IO uint32_t OVSEN : 1; /*!< [0..0] Oversampler Enable */ + uint32_t : 1; + __IO uint32_t OVSR : 3; /*!< [4..2] Oversampling ratio */ + __IO uint32_t OVSS : 4; /*!< [8..5] Oversampling shift */ + __IO uint32_t TOVS : 1; /*!< [9..9] Triggered Oversampling */ + uint32_t : 2; + __IO uint32_t DRES : 2; /*!< [13..12] ADC resolution */ + uint32_t : 18; + } OVSAMPCTL_b; + } ; +} ADC0_Type; /*!< Size = 132 (0x84) */ + + + +/* =========================================================================================================================== */ +/* ================ ADC1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Analog to digital converter (ADC1) + */ + +typedef struct { /*!< (@ 0x40012800) ADC1 Structure */ + + union { + __IO uint32_t STAT; /*!< (@ 0x00000000) status register */ + + struct { + __IO uint32_t WDE : 1; /*!< [0..0] Analog watchdog event flag */ + __IO uint32_t EOC : 1; /*!< [1..1] End of group conversion flag */ + __IO uint32_t EOIC : 1; /*!< [2..2] End of inserted group conversion flag */ + __IO uint32_t STIC : 1; /*!< [3..3] Start flag of inserted channel group */ + __IO uint32_t STRC : 1; /*!< [4..4] Start flag of regular channel group */ + uint32_t : 27; + } STAT_b; + } ; + + union { + __IO uint32_t CTL0; /*!< (@ 0x00000004) control register 0 */ + + struct { + __IO uint32_t WDCHSEL : 5; /*!< [4..0] Analog watchdog channel select */ + __IO uint32_t EOCIE : 1; /*!< [5..5] Interrupt enable for EOC */ + __IO uint32_t WDEIE : 1; /*!< [6..6] Interrupt enable for WDE */ + __IO uint32_t EOICIE : 1; /*!< [7..7] Interrupt enable for EOIC */ + __IO uint32_t SM : 1; /*!< [8..8] Scan mode */ + __IO uint32_t WDSC : 1; /*!< [9..9] When in scan mode, analog watchdog is effective on a + single channel */ + __IO uint32_t ICA : 1; /*!< [10..10] Inserted channel group convert automatically */ + __IO uint32_t DISRC : 1; /*!< [11..11] Discontinuous mode on regular channels */ + __IO uint32_t DISIC : 1; /*!< [12..12] Discontinuous mode on inserted channels */ + __IO uint32_t DISNUM : 3; /*!< [15..13] Number of conversions in discontinuous mode */ + uint32_t : 6; + __IO uint32_t IWDEN : 1; /*!< [22..22] Inserted channel analog watchdog enable */ + __IO uint32_t RWDEN : 1; /*!< [23..23] Regular channel analog watchdog enable */ + uint32_t : 8; + } CTL0_b; + } ; + + union { + __IO uint32_t CTL1; /*!< (@ 0x00000008) control register 1 */ + + struct { + __IO uint32_t ADCON : 1; /*!< [0..0] ADC on */ + __IO uint32_t CTN : 1; /*!< [1..1] Continuous mode */ + __IO uint32_t CLB : 1; /*!< [2..2] ADC calibration */ + __IO uint32_t RSTCLB : 1; /*!< [3..3] Reset calibration */ + uint32_t : 4; + __IO uint32_t DMA : 1; /*!< [8..8] DMA request enable */ + uint32_t : 2; + __IO uint32_t DAL : 1; /*!< [11..11] Data alignment */ + __IO uint32_t ETSIC : 3; /*!< [14..12] External trigger select for inserted channel */ + __IO uint32_t ETEIC : 1; /*!< [15..15] External trigger enable for inserted channel */ + uint32_t : 1; + __IO uint32_t ETSRC : 3; /*!< [19..17] External trigger select for regular channel */ + __IO uint32_t ETERC : 1; /*!< [20..20] External trigger enable for regular channel */ + __IO uint32_t SWICST : 1; /*!< [21..21] Start on inserted channel */ + __IO uint32_t SWRCST : 1; /*!< [22..22] Start on regular channel */ + uint32_t : 9; + } CTL1_b; + } ; + + union { + __IO uint32_t SAMPT0; /*!< (@ 0x0000000C) Sample time register 0 */ + + struct { + __IO uint32_t SPT10 : 3; /*!< [2..0] Channel 10 sample time selection */ + __IO uint32_t SPT11 : 3; /*!< [5..3] Channel 11 sample time selection */ + __IO uint32_t SPT12 : 3; /*!< [8..6] Channel 12 sample time selection */ + __IO uint32_t SPT13 : 3; /*!< [11..9] Channel 13 sample time selection */ + __IO uint32_t SPT14 : 3; /*!< [14..12] Channel 14 sample time selection */ + __IO uint32_t SPT15 : 3; /*!< [17..15] Channel 15 sample time selection */ + __IO uint32_t SPT16 : 3; /*!< [20..18] Channel 16 sample time selection */ + __IO uint32_t SPT17 : 3; /*!< [23..21] Channel 17 sample time selection */ + uint32_t : 8; + } SAMPT0_b; + } ; + + union { + __IO uint32_t SAMPT1; /*!< (@ 0x00000010) Sample time register 1 */ + + struct { + __IO uint32_t SPT0 : 3; /*!< [2..0] Channel 0 sample time selection */ + __IO uint32_t SPT1 : 3; /*!< [5..3] Channel 1 sample time selection */ + __IO uint32_t SPT2 : 3; /*!< [8..6] Channel 2 sample time selection */ + __IO uint32_t SPT3 : 3; /*!< [11..9] Channel 3 sample time selection */ + __IO uint32_t SPT4 : 3; /*!< [14..12] Channel 4 sample time selection */ + __IO uint32_t SPT5 : 3; /*!< [17..15] Channel 5 sample time selection */ + __IO uint32_t SPT6 : 3; /*!< [20..18] Channel 6 sample time selection */ + __IO uint32_t SPT7 : 3; /*!< [23..21] Channel 7 sample time selection */ + __IO uint32_t SPT8 : 3; /*!< [26..24] Channel 8 sample time selection */ + __IO uint32_t SPT9 : 3; /*!< [29..27] Channel 9 sample time selection */ + uint32_t : 2; + } SAMPT1_b; + } ; + + union { + __IO uint32_t IOFF0; /*!< (@ 0x00000014) Inserted channel data offset register 0 */ + + struct { + __IO uint32_t IOFF : 12; /*!< [11..0] Data offset for inserted channel 0 */ + uint32_t : 20; + } IOFF0_b; + } ; + + union { + __IO uint32_t IOFF1; /*!< (@ 0x00000018) Inserted channel data offset register 1 */ + + struct { + __IO uint32_t IOFF : 12; /*!< [11..0] Data offset for inserted channel 1 */ + uint32_t : 20; + } IOFF1_b; + } ; + + union { + __IO uint32_t IOFF2; /*!< (@ 0x0000001C) Inserted channel data offset register 2 */ + + struct { + __IO uint32_t IOFF : 12; /*!< [11..0] Data offset for inserted channel 2 */ + uint32_t : 20; + } IOFF2_b; + } ; + + union { + __IO uint32_t IOFF3; /*!< (@ 0x00000020) Inserted channel data offset register 3 */ + + struct { + __IO uint32_t IOFF : 12; /*!< [11..0] Data offset for inserted channel 3 */ + uint32_t : 20; + } IOFF3_b; + } ; + + union { + __IO uint32_t WDHT; /*!< (@ 0x00000024) watchdog higher threshold register */ + + struct { + __IO uint32_t WDHT : 12; /*!< [11..0] Analog watchdog higher threshold */ + uint32_t : 20; + } WDHT_b; + } ; + + union { + __IO uint32_t WDLT; /*!< (@ 0x00000028) watchdog lower threshold register */ + + struct { + __IO uint32_t WDLT : 12; /*!< [11..0] Analog watchdog lower threshold */ + uint32_t : 20; + } WDLT_b; + } ; + + union { + __IO uint32_t RSQ0; /*!< (@ 0x0000002C) regular sequence register 0 */ + + struct { + __IO uint32_t RSQ12 : 5; /*!< [4..0] 13th conversion in regular sequence */ + __IO uint32_t RSQ13 : 5; /*!< [9..5] 14th conversion in regular sequence */ + __IO uint32_t RSQ14 : 5; /*!< [14..10] 15th conversion in regular sequence */ + __IO uint32_t RSQ15 : 5; /*!< [19..15] 16th conversion in regular sequence */ + __IO uint32_t RL : 4; /*!< [23..20] Regular channel group length */ + uint32_t : 8; + } RSQ0_b; + } ; + + union { + __IO uint32_t RSQ1; /*!< (@ 0x00000030) regular sequence register 1 */ + + struct { + __IO uint32_t RSQ6 : 5; /*!< [4..0] 7th conversion in regular sequence */ + __IO uint32_t RSQ7 : 5; /*!< [9..5] 8th conversion in regular sequence */ + __IO uint32_t RSQ8 : 5; /*!< [14..10] 9th conversion in regular sequence */ + __IO uint32_t RSQ9 : 5; /*!< [19..15] 10th conversion in regular sequence */ + __IO uint32_t RSQ10 : 5; /*!< [24..20] 11th conversion in regular sequence */ + __IO uint32_t RSQ11 : 5; /*!< [29..25] 12th conversion in regular sequence */ + uint32_t : 2; + } RSQ1_b; + } ; + + union { + __IO uint32_t RSQ2; /*!< (@ 0x00000034) regular sequence register 2 */ + + struct { + __IO uint32_t RSQ0 : 5; /*!< [4..0] 1st conversion in regular sequence */ + __IO uint32_t RSQ1 : 5; /*!< [9..5] 2nd conversion in regular sequence */ + __IO uint32_t RSQ2 : 5; /*!< [14..10] 3rd conversion in regular sequence */ + __IO uint32_t RSQ3 : 5; /*!< [19..15] 4th conversion in regular sequence */ + __IO uint32_t RSQ4 : 5; /*!< [24..20] 5th conversion in regular sequence */ + __IO uint32_t RSQ5 : 5; /*!< [29..25] 6th conversion in regular sequence */ + uint32_t : 2; + } RSQ2_b; + } ; + + union { + __IO uint32_t ISQ; /*!< (@ 0x00000038) Inserted sequence register */ + + struct { + __IO uint32_t ISQ0 : 5; /*!< [4..0] 1st conversion in inserted sequence */ + __IO uint32_t ISQ1 : 5; /*!< [9..5] 2nd conversion in inserted sequence */ + __IO uint32_t ISQ2 : 5; /*!< [14..10] 3rd conversion in inserted sequence */ + __IO uint32_t ISQ3 : 5; /*!< [19..15] 4th conversion in inserted sequence */ + __IO uint32_t IL : 2; /*!< [21..20] Inserted channel group length */ + uint32_t : 10; + } ISQ_b; + } ; + + union { + __I uint32_t IDATA0; /*!< (@ 0x0000003C) Inserted data register 0 */ + + struct { + __I uint32_t IDATAn : 16; /*!< [15..0] Inserted number n conversion data */ + uint32_t : 16; + } IDATA0_b; + } ; + + union { + __I uint32_t IDATA1; /*!< (@ 0x00000040) Inserted data register 1 */ + + struct { + __I uint32_t IDATAn : 16; /*!< [15..0] Inserted number n conversion data */ + uint32_t : 16; + } IDATA1_b; + } ; + + union { + __I uint32_t IDATA2; /*!< (@ 0x00000044) Inserted data register 2 */ + + struct { + __I uint32_t IDATAn : 16; /*!< [15..0] Inserted number n conversion data */ + uint32_t : 16; + } IDATA2_b; + } ; + + union { + __I uint32_t IDATA3; /*!< (@ 0x00000048) Inserted data register 3 */ + + struct { + __I uint32_t IDATAn : 16; /*!< [15..0] Inserted number n conversion data */ + uint32_t : 16; + } IDATA3_b; + } ; + + union { + __I uint32_t RDATA; /*!< (@ 0x0000004C) regular data register */ + + struct { + __I uint32_t RDATA : 16; /*!< [15..0] Regular channel data */ + uint32_t : 16; + } RDATA_b; + } ; +} ADC1_Type; /*!< Size = 80 (0x50) */ + + + +/* =========================================================================================================================== */ +/* ================ AFIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Alternate-function I/Os (AFIO) + */ + +typedef struct { /*!< (@ 0x40010000) AFIO Structure */ + + union { + __IO uint32_t EC; /*!< (@ 0x00000000) Event control register */ + + struct { + __IO uint32_t PIN : 4; /*!< [3..0] Event output pin selection */ + __IO uint32_t PORT : 3; /*!< [6..4] Event output port selection */ + __IO uint32_t EOE : 1; /*!< [7..7] Event output enable */ + uint32_t : 24; + } EC_b; + } ; + + union { + __IO uint32_t PCF0; /*!< (@ 0x00000004) AFIO port configuration register 0 */ + + struct { + __IO uint32_t SPI0_REMAP : 1; /*!< [0..0] SPI0 remapping */ + __IO uint32_t I2C0_REMAP : 1; /*!< [1..1] I2C0 remapping */ + __IO uint32_t USART0_REMAP : 1; /*!< [2..2] USART0 remapping */ + __IO uint32_t USART1_REMAP : 1; /*!< [3..3] USART1 remapping */ + __IO uint32_t USART2_REMAP : 2; /*!< [5..4] USART2 remapping */ + __IO uint32_t TIMER0_REMAP : 2; /*!< [7..6] TIMER0 remapping */ + __IO uint32_t TIMER1_REMAP : 2; /*!< [9..8] TIMER1 remapping */ + __IO uint32_t TIMER2_REMAP : 2; /*!< [11..10] TIMER2 remapping */ + __IO uint32_t TIMER3_REMAP : 1; /*!< [12..12] TIMER3 remapping */ + __IO uint32_t CAN0_REMAP : 2; /*!< [14..13] CAN0 alternate interface remapping */ + __IO uint32_t PD01_REMAP : 1; /*!< [15..15] Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ + __IO uint32_t TIMER4CH3_IREMAP : 1; /*!< [16..16] TIMER4 channel3 internal remapping */ + uint32_t : 5; + __IO uint32_t CAN1_REMAP : 1; /*!< [22..22] CAN1 I/O remapping */ + uint32_t : 1; + __IO uint32_t SWJ_CFG : 3; /*!< [26..24] Serial wire JTAG configuration */ + uint32_t : 1; + __IO uint32_t SPI2_REMAP : 1; /*!< [28..28] SPI2/I2S2 remapping */ + __IO uint32_t TIMER1ITI1_REMAP : 1; /*!< [29..29] TIMER1 internal trigger 1 remapping */ + uint32_t : 2; + } PCF0_b; + } ; + + union { + __IO uint32_t EXTISS0; /*!< (@ 0x00000008) EXTI sources selection register 0 */ + + struct { + __IO uint32_t EXTI0_SS : 4; /*!< [3..0] EXTI 0 sources selection */ + __IO uint32_t EXTI1_SS : 4; /*!< [7..4] EXTI 1 sources selection */ + __IO uint32_t EXTI2_SS : 4; /*!< [11..8] EXTI 2 sources selection */ + __IO uint32_t EXTI3_SS : 4; /*!< [15..12] EXTI 3 sources selection */ + uint32_t : 16; + } EXTISS0_b; + } ; + + union { + __IO uint32_t EXTISS1; /*!< (@ 0x0000000C) EXTI sources selection register 1 */ + + struct { + __IO uint32_t EXTI4_SS : 4; /*!< [3..0] EXTI 4 sources selection */ + __IO uint32_t EXTI5_SS : 4; /*!< [7..4] EXTI 5 sources selection */ + __IO uint32_t EXTI6_SS : 4; /*!< [11..8] EXTI 6 sources selection */ + __IO uint32_t EXTI7_SS : 4; /*!< [15..12] EXTI 7 sources selection */ + uint32_t : 16; + } EXTISS1_b; + } ; + + union { + __IO uint32_t EXTISS2; /*!< (@ 0x00000010) EXTI sources selection register 2 */ + + struct { + __IO uint32_t EXTI8_SS : 4; /*!< [3..0] EXTI 8 sources selection */ + __IO uint32_t EXTI9_SS : 4; /*!< [7..4] EXTI 9 sources selection */ + __IO uint32_t EXTI10_SS : 4; /*!< [11..8] EXTI 10 sources selection */ + __IO uint32_t EXTI11_SS : 4; /*!< [15..12] EXTI 11 sources selection */ + uint32_t : 16; + } EXTISS2_b; + } ; + + union { + __IO uint32_t EXTISS3; /*!< (@ 0x00000014) EXTI sources selection register 3 */ + + struct { + __IO uint32_t EXTI12_SS : 4; /*!< [3..0] EXTI 12 sources selection */ + __IO uint32_t EXTI13_SS : 4; /*!< [7..4] EXTI 13 sources selection */ + __IO uint32_t EXTI14_SS : 4; /*!< [11..8] EXTI 14 sources selection */ + __IO uint32_t EXTI15_SS : 4; /*!< [15..12] EXTI 15 sources selection */ + uint32_t : 16; + } EXTISS3_b; + } ; + __I uint32_t RESERVED; + + union { + __IO uint32_t PCF1; /*!< (@ 0x0000001C) AFIO port configuration register 1 */ + + struct { + uint32_t : 10; + __IO uint32_t EXMC_NADV : 1; /*!< [10..10] EXMC_NADV connect/disconnect */ + uint32_t : 21; + } PCF1_b; + } ; +} AFIO_Type; /*!< Size = 32 (0x20) */ + + + +/* =========================================================================================================================== */ +/* ================ BKP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Backup registers (BKP) + */ + +typedef struct { /*!< (@ 0x40006C00) BKP Structure */ + __I uint16_t RESERVED[2]; + + union { + __IO uint16_t DATA0; /*!< (@ 0x00000004) Backup data register 0 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA0_b; + } ; + __I uint16_t RESERVED1; + + union { + __IO uint16_t DATA1; /*!< (@ 0x00000008) Backup data register 1 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA1_b; + } ; + __I uint16_t RESERVED2; + + union { + __IO uint16_t DATA2; /*!< (@ 0x0000000C) Backup data register 2 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA2_b; + } ; + __I uint16_t RESERVED3; + + union { + __IO uint16_t DATA3; /*!< (@ 0x00000010) Backup data register 3 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA3_b; + } ; + __I uint16_t RESERVED4; + + union { + __IO uint16_t DATA4; /*!< (@ 0x00000014) Backup data register 4 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA4_b; + } ; + __I uint16_t RESERVED5; + + union { + __IO uint16_t DATA5; /*!< (@ 0x00000018) Backup data register 5 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA5_b; + } ; + __I uint16_t RESERVED6; + + union { + __IO uint16_t DATA6; /*!< (@ 0x0000001C) Backup data register 6 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA6_b; + } ; + __I uint16_t RESERVED7; + + union { + __IO uint16_t DATA7; /*!< (@ 0x00000020) Backup data register 7 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA7_b; + } ; + __I uint16_t RESERVED8; + + union { + __IO uint16_t DATA8; /*!< (@ 0x00000024) Backup data register 8 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA8_b; + } ; + __I uint16_t RESERVED9; + + union { + __IO uint16_t DATA9; /*!< (@ 0x00000028) Backup data register 9 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA9_b; + } ; + __I uint16_t RESERVED10; + + union { + __IO uint16_t OCTL; /*!< (@ 0x0000002C) RTC signal output control register */ + + struct { + __IO uint16_t RCCV : 7; /*!< [6..0] RTC clock calibration value */ + __IO uint16_t COEN : 1; /*!< [7..7] RTC clock calibration output enable */ + __IO uint16_t ASOEN : 1; /*!< [8..8] RTC alarm or second signal output enable */ + __IO uint16_t ROSEL : 1; /*!< [9..9] RTC output selection */ + uint16_t : 6; + } OCTL_b; + } ; + __I uint16_t RESERVED11; + + union { + __IO uint16_t TPCTL; /*!< (@ 0x00000030) Tamper pin control register */ + + struct { + __IO uint16_t TPEN : 1; /*!< [0..0] TAMPER detection enable */ + __IO uint16_t TPAL : 1; /*!< [1..1] TAMPER pin active level */ + uint16_t : 14; + } TPCTL_b; + } ; + __I uint16_t RESERVED12; + + union { + __IO uint16_t TPCS; /*!< (@ 0x00000034) Tamper control and status register */ + + struct { + __IO uint16_t TER : 1; /*!< [0..0] Tamper event reset */ + __IO uint16_t TIR : 1; /*!< [1..1] Tamper interrupt reset */ + __IO uint16_t TPIE : 1; /*!< [2..2] Tamper interrupt enable */ + uint16_t : 5; + __IO uint16_t TEF : 1; /*!< [8..8] Tamper event flag */ + __IO uint16_t TIF : 1; /*!< [9..9] Tamper interrupt flag */ + uint16_t : 6; + } TPCS_b; + } ; + __I uint16_t RESERVED13[5]; + + union { + __IO uint16_t DATA10; /*!< (@ 0x00000040) Backup data register 10 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA10_b; + } ; + __I uint16_t RESERVED14; + + union { + __IO uint16_t DATA11; /*!< (@ 0x00000044) Backup data register 11 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA11_b; + } ; + __I uint16_t RESERVED15; + + union { + __IO uint16_t DATA12; /*!< (@ 0x00000048) Backup data register 12 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA12_b; + } ; + __I uint16_t RESERVED16; + + union { + __IO uint16_t DATA13; /*!< (@ 0x0000004C) Backup data register 13 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA13_b; + } ; + __I uint16_t RESERVED17; + + union { + __IO uint16_t DATA14; /*!< (@ 0x00000050) Backup data register 14 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA14_b; + } ; + __I uint16_t RESERVED18; + + union { + __IO uint16_t DATA15; /*!< (@ 0x00000054) Backup data register 15 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA15_b; + } ; + __I uint16_t RESERVED19; + + union { + __IO uint16_t DATA16; /*!< (@ 0x00000058) Backup data register 16 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA16_b; + } ; + __I uint16_t RESERVED20; + + union { + __IO uint16_t DATA17; /*!< (@ 0x0000005C) Backup data register 17 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA17_b; + } ; + __I uint16_t RESERVED21; + + union { + __IO uint16_t DATA18; /*!< (@ 0x00000060) Backup data register 18 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA18_b; + } ; + __I uint16_t RESERVED22; + + union { + __IO uint16_t DATA19; /*!< (@ 0x00000064) Backup data register 19 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA19_b; + } ; + __I uint16_t RESERVED23; + + union { + __IO uint16_t DATA20; /*!< (@ 0x00000068) Backup data register 20 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA20_b; + } ; + __I uint16_t RESERVED24; + + union { + __IO uint16_t DATA21; /*!< (@ 0x0000006C) Backup data register 21 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA21_b; + } ; + __I uint16_t RESERVED25; + + union { + __IO uint16_t DATA22; /*!< (@ 0x00000070) Backup data register 22 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA22_b; + } ; + __I uint16_t RESERVED26; + + union { + __IO uint16_t DATA23; /*!< (@ 0x00000074) Backup data register 23 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA23_b; + } ; + __I uint16_t RESERVED27; + + union { + __IO uint16_t DATA24; /*!< (@ 0x00000078) Backup data register 24 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA24_b; + } ; + __I uint16_t RESERVED28; + + union { + __IO uint16_t DATA25; /*!< (@ 0x0000007C) Backup data register 25 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA25_b; + } ; + __I uint16_t RESERVED29; + + union { + __IO uint16_t DATA26; /*!< (@ 0x00000080) Backup data register 26 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA26_b; + } ; + __I uint16_t RESERVED30; + + union { + __IO uint16_t DATA27; /*!< (@ 0x00000084) Backup data register 27 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA27_b; + } ; + __I uint16_t RESERVED31; + + union { + __IO uint16_t DATA28; /*!< (@ 0x00000088) Backup data register 28 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA28_b; + } ; + __I uint16_t RESERVED32; + + union { + __IO uint16_t DATA29; /*!< (@ 0x0000008C) Backup data register 29 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA29_b; + } ; + __I uint16_t RESERVED33; + + union { + __IO uint16_t DATA30; /*!< (@ 0x00000090) Backup data register 30 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA30_b; + } ; + __I uint16_t RESERVED34; + + union { + __IO uint16_t DATA31; /*!< (@ 0x00000094) Backup data register 31 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA31_b; + } ; + __I uint16_t RESERVED35; + + union { + __IO uint16_t DATA32; /*!< (@ 0x00000098) Backup data register 32 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA32_b; + } ; + __I uint16_t RESERVED36; + + union { + __IO uint16_t DATA33; /*!< (@ 0x0000009C) Backup data register 33 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA33_b; + } ; + __I uint16_t RESERVED37; + + union { + __IO uint16_t DATA34; /*!< (@ 0x000000A0) Backup data register 34 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA34_b; + } ; + __I uint16_t RESERVED38; + + union { + __IO uint16_t DATA35; /*!< (@ 0x000000A4) Backup data register 35 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA35_b; + } ; + __I uint16_t RESERVED39; + + union { + __IO uint16_t DATA36; /*!< (@ 0x000000A8) Backup data register 36 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA36_b; + } ; + __I uint16_t RESERVED40; + + union { + __IO uint16_t DATA37; /*!< (@ 0x000000AC) Backup data register 37 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA37_b; + } ; + __I uint16_t RESERVED41; + + union { + __IO uint16_t DATA38; /*!< (@ 0x000000B0) Backup data register 38 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA38_b; + } ; + __I uint16_t RESERVED42; + + union { + __IO uint16_t DATA39; /*!< (@ 0x000000B4) Backup data register 39 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA39_b; + } ; + __I uint16_t RESERVED43; + + union { + __IO uint16_t DATA40; /*!< (@ 0x000000B8) Backup data register 40 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA40_b; + } ; + __I uint16_t RESERVED44; + + union { + __IO uint16_t DATA41; /*!< (@ 0x000000BC) Backup data register 41 */ + + struct { + __IO uint16_t DATA : 16; /*!< [15..0] Backup data */ + } DATA41_b; + } ; +} BKP_Type; /*!< Size = 190 (0xbe) */ + + + +/* =========================================================================================================================== */ +/* ================ CAN0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Controller area network (CAN0) + */ + +typedef struct { /*!< (@ 0x40006400) CAN0 Structure */ + + union { + __IO uint32_t CTL; /*!< (@ 0x00000000) Control register */ + + struct { + __IO uint32_t IWMOD : 1; /*!< [0..0] Initial working mode */ + __IO uint32_t SLPWMOD : 1; /*!< [1..1] Sleep working mode */ + __IO uint32_t TFO : 1; /*!< [2..2] Transmit FIFO order */ + __IO uint32_t RFOD : 1; /*!< [3..3] Receive FIFO overwrite disable */ + __IO uint32_t ARD : 1; /*!< [4..4] Automatic retransmission disable */ + __IO uint32_t AWU : 1; /*!< [5..5] Automatic wakeup */ + __IO uint32_t ABOR : 1; /*!< [6..6] Automatic bus-off recovery */ + __IO uint32_t TTC : 1; /*!< [7..7] Time-triggered communication */ + uint32_t : 7; + __IO uint32_t SWRST : 1; /*!< [15..15] Software reset */ + __IO uint32_t DFZ : 1; /*!< [16..16] Debug freeze */ + uint32_t : 15; + } CTL_b; + } ; + + union { + __IO uint32_t STAT; /*!< (@ 0x00000004) Status register */ + + struct { + __I uint32_t IWS : 1; /*!< [0..0] Initial working state */ + __I uint32_t SLPWS : 1; /*!< [1..1] Sleep working state */ + __IO uint32_t ERRIF : 1; /*!< [2..2] Error interrupt flag */ + __IO uint32_t WUIF : 1; /*!< [3..3] Status change interrupt flag of wakeup from sleep working + mode */ + __IO uint32_t SLPIF : 1; /*!< [4..4] Status change interrupt flag of sleep working mode entering */ + uint32_t : 3; + __I uint32_t TS : 1; /*!< [8..8] Transmitting state */ + __I uint32_t RS : 1; /*!< [9..9] Receiving state */ + __I uint32_t LASTRX : 1; /*!< [10..10] Last sample value of RX pin */ + __I uint32_t RXL : 1; /*!< [11..11] RX level */ + uint32_t : 20; + } STAT_b; + } ; + + union { + __IO uint32_t TSTAT; /*!< (@ 0x00000008) Transmit status register */ + + struct { + __IO uint32_t MTF0 : 1; /*!< [0..0] Mailbox 0 transmit finished */ + __IO uint32_t MTFNERR0 : 1; /*!< [1..1] Mailbox 0 transmit finished and no error */ + __IO uint32_t MAL0 : 1; /*!< [2..2] Mailbox 0 arbitration lost */ + __IO uint32_t MTE0 : 1; /*!< [3..3] Mailbox 0 transmit error */ + uint32_t : 3; + __IO uint32_t MST0 : 1; /*!< [7..7] Mailbox 0 stop transmitting */ + __IO uint32_t MTF1 : 1; /*!< [8..8] Mailbox 1 transmit finished */ + __IO uint32_t MTFNERR1 : 1; /*!< [9..9] Mailbox 1 transmit finished and no error */ + __IO uint32_t MAL1 : 1; /*!< [10..10] Mailbox 1 arbitration lost */ + __IO uint32_t MTE1 : 1; /*!< [11..11] Mailbox 1 transmit error */ + uint32_t : 3; + __IO uint32_t MST1 : 1; /*!< [15..15] Mailbox 1 stop transmitting */ + __IO uint32_t MTF2 : 1; /*!< [16..16] Mailbox 2 transmit finished */ + __IO uint32_t MTFNERR2 : 1; /*!< [17..17] Mailbox 2 transmit finished and no error */ + __IO uint32_t MAL2 : 1; /*!< [18..18] Mailbox 2 arbitration lost */ + __IO uint32_t MTE2 : 1; /*!< [19..19] Mailbox 2 transmit error */ + uint32_t : 3; + __IO uint32_t MST2 : 1; /*!< [23..23] Mailbox 2 stop transmitting */ + __I uint32_t NUM : 2; /*!< [25..24] number of the transmit FIFO mailbox in which the frame + will be transmitted if at least one mailbox is empty */ + __I uint32_t TME0 : 1; /*!< [26..26] Transmit mailbox 0 empty */ + __I uint32_t TME1 : 1; /*!< [27..27] Transmit mailbox 1 empty */ + __I uint32_t TME2 : 1; /*!< [28..28] Transmit mailbox 2 empty */ + __I uint32_t TMLS0 : 1; /*!< [29..29] Transmit mailbox 0 last sending in transmit FIFO */ + __I uint32_t TMLS1 : 1; /*!< [30..30] Transmit mailbox 1 last sending in transmit FIFO */ + __I uint32_t TMLS2 : 1; /*!< [31..31] Transmit mailbox 2 last sending in transmit FIFO */ + } TSTAT_b; + } ; + + union { + __IO uint32_t RFIFO0; /*!< (@ 0x0000000C) Receive message FIFO0 register */ + + struct { + __I uint32_t RFL0 : 2; /*!< [1..0] Receive FIFO0 length */ + uint32_t : 1; + __IO uint32_t RFF0 : 1; /*!< [3..3] Receive FIFO0 full */ + __IO uint32_t RFO0 : 1; /*!< [4..4] Receive FIFO0 overfull */ + __IO uint32_t RFD0 : 1; /*!< [5..5] Receive FIFO0 dequeue */ + uint32_t : 26; + } RFIFO0_b; + } ; + + union { + __IO uint32_t RFIFO1; /*!< (@ 0x00000010) Receive message FIFO1 register */ + + struct { + __I uint32_t RFL1 : 2; /*!< [1..0] Receive FIFO1 length */ + uint32_t : 1; + __IO uint32_t RFF1 : 1; /*!< [3..3] Receive FIFO1 full */ + __IO uint32_t RFO1 : 1; /*!< [4..4] Receive FIFO1 overfull */ + __IO uint32_t RFD1 : 1; /*!< [5..5] Receive FIFO1 dequeue */ + uint32_t : 26; + } RFIFO1_b; + } ; + + union { + __IO uint32_t INTEN; /*!< (@ 0x00000014) Interrupt enable register */ + + struct { + __IO uint32_t TMEIE : 1; /*!< [0..0] Transmit mailbox empty interrupt enable */ + __IO uint32_t RFNEIE0 : 1; /*!< [1..1] Receive FIFO0 not empty interrupt enable */ + __IO uint32_t RFFIE0 : 1; /*!< [2..2] Receive FIFO0 full interrupt enable */ + __IO uint32_t RFOIE0 : 1; /*!< [3..3] Receive FIFO0 overfull interrupt enable */ + __IO uint32_t RFNEIE1 : 1; /*!< [4..4] Receive FIFO1 not empty interrupt enable */ + __IO uint32_t RFFIE1 : 1; /*!< [5..5] Receive FIFO1 full interrupt enable */ + __IO uint32_t RFOIE1 : 1; /*!< [6..6] Receive FIFO1 overfull interrupt enable */ + uint32_t : 1; + __IO uint32_t WERRIE : 1; /*!< [8..8] Warning error interrupt enable */ + __IO uint32_t PERRIE : 1; /*!< [9..9] Passive error interrupt enable */ + __IO uint32_t BOIE : 1; /*!< [10..10] Bus-off interrupt enable */ + __IO uint32_t ERRNIE : 1; /*!< [11..11] Error number interrupt enable */ + uint32_t : 3; + __IO uint32_t ERRIE : 1; /*!< [15..15] Error interrupt enable */ + __IO uint32_t WIE : 1; /*!< [16..16] Wakeup interrupt enable */ + __IO uint32_t SLPWIE : 1; /*!< [17..17] Sleep working interrupt enable */ + uint32_t : 14; + } INTEN_b; + } ; + + union { + __IO uint32_t ERR; /*!< (@ 0x00000018) Error register */ + + struct { + __I uint32_t WERR : 1; /*!< [0..0] Warning error */ + __I uint32_t PERR : 1; /*!< [1..1] Passive error */ + __I uint32_t BOERR : 1; /*!< [2..2] Bus-off error */ + uint32_t : 1; + __IO uint32_t ERRN : 3; /*!< [6..4] Error number */ + uint32_t : 9; + __I uint32_t TECNT : 8; /*!< [23..16] Transmit Error Count defined by the CAN standard */ + __I uint32_t RECNT : 8; /*!< [31..24] Receive Error Count defined by the CAN standard */ + } ERR_b; + } ; + + union { + __IO uint32_t BT; /*!< (@ 0x0000001C) Bit timing register */ + + struct { + __IO uint32_t BAUDPSC : 10; /*!< [9..0] Baud rate prescaler */ + uint32_t : 6; + __IO uint32_t BS1 : 4; /*!< [19..16] Bit segment 1 */ + __IO uint32_t BS2 : 3; /*!< [22..20] Bit segment 2 */ + uint32_t : 1; + __IO uint32_t SJW : 2; /*!< [25..24] Resynchronization jump width */ + uint32_t : 4; + __IO uint32_t LCMOD : 1; /*!< [30..30] Loopback communication mode */ + __IO uint32_t SCMOD : 1; /*!< [31..31] Silent communication mode */ + } BT_b; + } ; + __I uint32_t RESERVED[88]; + + union { + __IO uint32_t TMI0; /*!< (@ 0x00000180) Transmit mailbox identifier register 0 */ + + struct { + __IO uint32_t TEN : 1; /*!< [0..0] Transmit enable */ + __IO uint32_t FT : 1; /*!< [1..1] Frame type */ + __IO uint32_t FF : 1; /*!< [2..2] Frame format */ + __IO uint32_t EFID : 18; /*!< [20..3] The frame identifier */ + __IO uint32_t SFID_EFID : 11; /*!< [31..21] The frame identifier */ + } TMI0_b; + } ; + + union { + __IO uint32_t TMP0; /*!< (@ 0x00000184) Transmit mailbox property register 0 */ + + struct { + __IO uint32_t DLENC : 4; /*!< [3..0] Data length code */ + uint32_t : 4; + __IO uint32_t TSEN : 1; /*!< [8..8] Time stamp enable */ + uint32_t : 7; + __IO uint32_t TS : 16; /*!< [31..16] Time stamp */ + } TMP0_b; + } ; + + union { + __IO uint32_t TMDATA00; /*!< (@ 0x00000188) Transmit mailbox data0 register */ + + struct { + __IO uint32_t DB0 : 8; /*!< [7..0] Data byte 0 */ + __IO uint32_t DB1 : 8; /*!< [15..8] Data byte 1 */ + __IO uint32_t DB2 : 8; /*!< [23..16] Data byte 2 */ + __IO uint32_t DB3 : 8; /*!< [31..24] Data byte 3 */ + } TMDATA00_b; + } ; + + union { + __IO uint32_t TMDATA10; /*!< (@ 0x0000018C) Transmit mailbox data1 register */ + + struct { + __IO uint32_t DB4 : 8; /*!< [7..0] Data byte 4 */ + __IO uint32_t DB5 : 8; /*!< [15..8] Data byte 5 */ + __IO uint32_t DB6 : 8; /*!< [23..16] Data byte 6 */ + __IO uint32_t DB7 : 8; /*!< [31..24] Data byte 7 */ + } TMDATA10_b; + } ; + + union { + __IO uint32_t TMI1; /*!< (@ 0x00000190) Transmit mailbox identifier register 1 */ + + struct { + __IO uint32_t TEN : 1; /*!< [0..0] Transmit enable */ + __IO uint32_t FT : 1; /*!< [1..1] Frame type */ + __IO uint32_t FF : 1; /*!< [2..2] Frame format */ + __IO uint32_t EFID : 18; /*!< [20..3] The frame identifier */ + __IO uint32_t SFID_EFID : 11; /*!< [31..21] The frame identifier */ + } TMI1_b; + } ; + + union { + __IO uint32_t TMP1; /*!< (@ 0x00000194) Transmit mailbox property register 1 */ + + struct { + __IO uint32_t DLENC : 4; /*!< [3..0] Data length code */ + uint32_t : 4; + __IO uint32_t TSEN : 1; /*!< [8..8] Time stamp enable */ + uint32_t : 7; + __IO uint32_t TS : 16; /*!< [31..16] Time stamp */ + } TMP1_b; + } ; + + union { + __IO uint32_t TMDATA01; /*!< (@ 0x00000198) Transmit mailbox data0 register */ + + struct { + __IO uint32_t DB0 : 8; /*!< [7..0] Data byte 0 */ + __IO uint32_t DB1 : 8; /*!< [15..8] Data byte 1 */ + __IO uint32_t DB2 : 8; /*!< [23..16] Data byte 2 */ + __IO uint32_t DB3 : 8; /*!< [31..24] Data byte 3 */ + } TMDATA01_b; + } ; + + union { + __IO uint32_t TMDATA11; /*!< (@ 0x0000019C) Transmit mailbox data1 register */ + + struct { + __IO uint32_t DB4 : 8; /*!< [7..0] Data byte 4 */ + __IO uint32_t DB5 : 8; /*!< [15..8] Data byte 5 */ + __IO uint32_t DB6 : 8; /*!< [23..16] Data byte 6 */ + __IO uint32_t DB7 : 8; /*!< [31..24] Data byte 7 */ + } TMDATA11_b; + } ; + + union { + __IO uint32_t TMI2; /*!< (@ 0x000001A0) Transmit mailbox identifier register 2 */ + + struct { + __IO uint32_t TEN : 1; /*!< [0..0] Transmit enable */ + __IO uint32_t FT : 1; /*!< [1..1] Frame type */ + __IO uint32_t FF : 1; /*!< [2..2] Frame format */ + __IO uint32_t EFID : 18; /*!< [20..3] The frame identifier */ + __IO uint32_t SFID_EFID : 11; /*!< [31..21] The frame identifier */ + } TMI2_b; + } ; + + union { + __IO uint32_t TMP2; /*!< (@ 0x000001A4) Transmit mailbox property register 2 */ + + struct { + __IO uint32_t DLENC : 4; /*!< [3..0] Data length code */ + uint32_t : 4; + __IO uint32_t TSEN : 1; /*!< [8..8] Time stamp enable */ + uint32_t : 7; + __IO uint32_t TS : 16; /*!< [31..16] Time stamp */ + } TMP2_b; + } ; + + union { + __IO uint32_t TMDATA02; /*!< (@ 0x000001A8) Transmit mailbox data0 register */ + + struct { + __IO uint32_t DB0 : 8; /*!< [7..0] Data byte 0 */ + __IO uint32_t DB1 : 8; /*!< [15..8] Data byte 1 */ + __IO uint32_t DB2 : 8; /*!< [23..16] Data byte 2 */ + __IO uint32_t DB3 : 8; /*!< [31..24] Data byte 3 */ + } TMDATA02_b; + } ; + + union { + __IO uint32_t TMDATA12; /*!< (@ 0x000001AC) Transmit mailbox data1 register */ + + struct { + __IO uint32_t DB4 : 8; /*!< [7..0] Data byte 4 */ + __IO uint32_t DB5 : 8; /*!< [15..8] Data byte 5 */ + __IO uint32_t DB6 : 8; /*!< [23..16] Data byte 6 */ + __IO uint32_t DB7 : 8; /*!< [31..24] Data byte 7 */ + } TMDATA12_b; + } ; + + union { + __I uint32_t RFIFOMI0; /*!< (@ 0x000001B0) Receive FIFO mailbox identifier register */ + + struct { + uint32_t : 1; + __I uint32_t FT : 1; /*!< [1..1] Frame type */ + __I uint32_t FF : 1; /*!< [2..2] Frame format */ + __I uint32_t EFID : 18; /*!< [20..3] The frame identifier */ + __I uint32_t SFID_EFID : 11; /*!< [31..21] The frame identifier */ + } RFIFOMI0_b; + } ; + + union { + __I uint32_t RFIFOMP0; /*!< (@ 0x000001B4) Receive FIFO0 mailbox property register */ + + struct { + __I uint32_t DLENC : 4; /*!< [3..0] Data length code */ + uint32_t : 4; + __I uint32_t FI : 8; /*!< [15..8] Filtering index */ + __I uint32_t TS : 16; /*!< [31..16] Time stamp */ + } RFIFOMP0_b; + } ; + + union { + __I uint32_t RFIFOMDATA00; /*!< (@ 0x000001B8) Receive FIFO0 mailbox data0 register */ + + struct { + __I uint32_t DB0 : 8; /*!< [7..0] Data byte 0 */ + __I uint32_t DB1 : 8; /*!< [15..8] Data byte 1 */ + __I uint32_t DB2 : 8; /*!< [23..16] Data byte 2 */ + __I uint32_t DB3 : 8; /*!< [31..24] Data byte 3 */ + } RFIFOMDATA00_b; + } ; + + union { + __I uint32_t RFIFOMDATA10; /*!< (@ 0x000001BC) Receive FIFO0 mailbox data1 register */ + + struct { + __I uint32_t DB4 : 8; /*!< [7..0] Data byte 4 */ + __I uint32_t DB5 : 8; /*!< [15..8] Data byte 5 */ + __I uint32_t DB6 : 8; /*!< [23..16] Data byte 6 */ + __I uint32_t DB7 : 8; /*!< [31..24] Data byte 7 */ + } RFIFOMDATA10_b; + } ; + + union { + __I uint32_t RFIFOMI1; /*!< (@ 0x000001C0) Receive FIFO1 mailbox identifier register */ + + struct { + uint32_t : 1; + __I uint32_t FT : 1; /*!< [1..1] Frame type */ + __I uint32_t FF : 1; /*!< [2..2] Frame format */ + __I uint32_t EFID : 18; /*!< [20..3] The frame identifier */ + __I uint32_t SFID_EFID : 11; /*!< [31..21] The frame identifier */ + } RFIFOMI1_b; + } ; + + union { + __I uint32_t RFIFOMP1; /*!< (@ 0x000001C4) Receive FIFO1 mailbox property register */ + + struct { + __I uint32_t DLENC : 4; /*!< [3..0] Data length code */ + uint32_t : 4; + __I uint32_t FI : 8; /*!< [15..8] Filtering index */ + __I uint32_t TS : 16; /*!< [31..16] Time stamp */ + } RFIFOMP1_b; + } ; + + union { + __I uint32_t RFIFOMDATA01; /*!< (@ 0x000001C8) Receive FIFO1 mailbox data0 register */ + + struct { + __I uint32_t DB0 : 8; /*!< [7..0] Data byte 0 */ + __I uint32_t DB1 : 8; /*!< [15..8] Data byte 1 */ + __I uint32_t DB2 : 8; /*!< [23..16] Data byte 2 */ + __I uint32_t DB3 : 8; /*!< [31..24] Data byte 3 */ + } RFIFOMDATA01_b; + } ; + + union { + __I uint32_t RFIFOMDATA11; /*!< (@ 0x000001CC) Receive FIFO1 mailbox data1 register */ + + struct { + __I uint32_t DB4 : 8; /*!< [7..0] Data byte 4 */ + __I uint32_t DB5 : 8; /*!< [15..8] Data byte 5 */ + __I uint32_t DB6 : 8; /*!< [23..16] Data byte 6 */ + __I uint32_t DB7 : 8; /*!< [31..24] Data byte 7 */ + } RFIFOMDATA11_b; + } ; + __I uint32_t RESERVED1[12]; + + union { + __IO uint32_t FCTL; /*!< (@ 0x00000200) Filter control register */ + + struct { + __IO uint32_t FLD : 1; /*!< [0..0] Filter lock disable */ + uint32_t : 7; + __IO uint32_t HBC1F : 6; /*!< [13..8] Header bank of CAN1 filter */ + uint32_t : 18; + } FCTL_b; + } ; + + union { + __IO uint32_t FMCFG; /*!< (@ 0x00000204) Filter mode configuration register */ + + struct { + __IO uint32_t FMOD0 : 1; /*!< [0..0] Filter mode */ + __IO uint32_t FMOD1 : 1; /*!< [1..1] Filter mode */ + __IO uint32_t FMOD2 : 1; /*!< [2..2] Filter mode */ + __IO uint32_t FMOD3 : 1; /*!< [3..3] Filter mode */ + __IO uint32_t FMOD4 : 1; /*!< [4..4] Filter mode */ + __IO uint32_t FMOD5 : 1; /*!< [5..5] Filter mode */ + __IO uint32_t FMOD6 : 1; /*!< [6..6] Filter mode */ + __IO uint32_t FMOD7 : 1; /*!< [7..7] Filter mode */ + __IO uint32_t FMOD8 : 1; /*!< [8..8] Filter mode */ + __IO uint32_t FMOD9 : 1; /*!< [9..9] Filter mode */ + __IO uint32_t FMOD10 : 1; /*!< [10..10] Filter mode */ + __IO uint32_t FMOD11 : 1; /*!< [11..11] Filter mode */ + __IO uint32_t FMOD12 : 1; /*!< [12..12] Filter mode */ + __IO uint32_t FMOD13 : 1; /*!< [13..13] Filter mode */ + __IO uint32_t FMOD14 : 1; /*!< [14..14] Filter mode */ + __IO uint32_t FMOD15 : 1; /*!< [15..15] Filter mode */ + __IO uint32_t FMOD16 : 1; /*!< [16..16] Filter mode */ + __IO uint32_t FMOD17 : 1; /*!< [17..17] Filter mode */ + __IO uint32_t FMOD18 : 1; /*!< [18..18] Filter mode */ + __IO uint32_t FMOD19 : 1; /*!< [19..19] Filter mode */ + __IO uint32_t FMOD20 : 1; /*!< [20..20] Filter mode */ + __IO uint32_t FMOD21 : 1; /*!< [21..21] Filter mode */ + __IO uint32_t FMOD22 : 1; /*!< [22..22] Filter mode */ + __IO uint32_t FMOD23 : 1; /*!< [23..23] Filter mode */ + __IO uint32_t FMOD24 : 1; /*!< [24..24] Filter mode */ + __IO uint32_t FMOD25 : 1; /*!< [25..25] Filter mode */ + __IO uint32_t FMOD26 : 1; /*!< [26..26] Filter mode */ + __IO uint32_t FMOD27 : 1; /*!< [27..27] Filter mode */ + uint32_t : 4; + } FMCFG_b; + } ; + __I uint32_t RESERVED2; + + union { + __IO uint32_t FSCFG; /*!< (@ 0x0000020C) Filter scale configuration register */ + + struct { + __IO uint32_t FS0 : 1; /*!< [0..0] Filter scale configuration */ + __IO uint32_t FS1 : 1; /*!< [1..1] Filter scale configuration */ + __IO uint32_t FS2 : 1; /*!< [2..2] Filter scale configuration */ + __IO uint32_t FS3 : 1; /*!< [3..3] Filter scale configuration */ + __IO uint32_t FS4 : 1; /*!< [4..4] Filter scale configuration */ + __IO uint32_t FS5 : 1; /*!< [5..5] Filter scale configuration */ + __IO uint32_t FS6 : 1; /*!< [6..6] Filter scale configuration */ + __IO uint32_t FS7 : 1; /*!< [7..7] Filter scale configuration */ + __IO uint32_t FS8 : 1; /*!< [8..8] Filter scale configuration */ + __IO uint32_t FS9 : 1; /*!< [9..9] Filter scale configuration */ + __IO uint32_t FS10 : 1; /*!< [10..10] Filter scale configuration */ + __IO uint32_t FS11 : 1; /*!< [11..11] Filter scale configuration */ + __IO uint32_t FS12 : 1; /*!< [12..12] Filter scale configuration */ + __IO uint32_t FS13 : 1; /*!< [13..13] Filter scale configuration */ + __IO uint32_t FS14 : 1; /*!< [14..14] Filter scale configuration */ + __IO uint32_t FS15 : 1; /*!< [15..15] Filter scale configuration */ + __IO uint32_t FS16 : 1; /*!< [16..16] Filter scale configuration */ + __IO uint32_t FS17 : 1; /*!< [17..17] Filter scale configuration */ + __IO uint32_t FS18 : 1; /*!< [18..18] Filter scale configuration */ + __IO uint32_t FS19 : 1; /*!< [19..19] Filter scale configuration */ + __IO uint32_t FS20 : 1; /*!< [20..20] Filter scale configuration */ + __IO uint32_t FS21 : 1; /*!< [21..21] Filter scale configuration */ + __IO uint32_t FS22 : 1; /*!< [22..22] Filter scale configuration */ + __IO uint32_t FS23 : 1; /*!< [23..23] Filter scale configuration */ + __IO uint32_t FS24 : 1; /*!< [24..24] Filter scale configuration */ + __IO uint32_t FS25 : 1; /*!< [25..25] Filter scale configuration */ + __IO uint32_t FS26 : 1; /*!< [26..26] Filter scale configuration */ + __IO uint32_t FS27 : 1; /*!< [27..27] Filter scale configuration */ + uint32_t : 4; + } FSCFG_b; + } ; + __I uint32_t RESERVED3; + + union { + __IO uint32_t FAFIFO; /*!< (@ 0x00000214) Filter associated FIFO register */ + + struct { + __IO uint32_t FAF0 : 1; /*!< [0..0] Filter 0 associated with FIFO */ + __IO uint32_t FAF1 : 1; /*!< [1..1] Filter 1 associated with FIFO */ + __IO uint32_t FAF2 : 1; /*!< [2..2] Filter 2 associated with FIFO */ + __IO uint32_t FAF3 : 1; /*!< [3..3] Filter 3 associated with FIFO */ + __IO uint32_t FAF4 : 1; /*!< [4..4] Filter 4 associated with FIFO */ + __IO uint32_t FAF5 : 1; /*!< [5..5] Filter 5 associated with FIFO */ + __IO uint32_t FAF6 : 1; /*!< [6..6] Filter 6 associated with FIFO */ + __IO uint32_t FAF7 : 1; /*!< [7..7] Filter 7 associated with FIFO */ + __IO uint32_t FAF8 : 1; /*!< [8..8] Filter 8 associated with FIFO */ + __IO uint32_t FAF9 : 1; /*!< [9..9] Filter 9 associated with FIFO */ + __IO uint32_t FAF10 : 1; /*!< [10..10] Filter 10 associated with FIFO */ + __IO uint32_t FAF11 : 1; /*!< [11..11] Filter 11 associated with FIFO */ + __IO uint32_t FAF12 : 1; /*!< [12..12] Filter 12 associated with FIFO */ + __IO uint32_t FAF13 : 1; /*!< [13..13] Filter 13 associated with FIFO */ + __IO uint32_t FAF14 : 1; /*!< [14..14] Filter 14 associated with FIFO */ + __IO uint32_t FAF15 : 1; /*!< [15..15] Filter 15 associated with FIFO */ + __IO uint32_t FAF16 : 1; /*!< [16..16] Filter 16 associated with FIFO */ + __IO uint32_t FAF17 : 1; /*!< [17..17] Filter 17 associated with FIFO */ + __IO uint32_t FAF18 : 1; /*!< [18..18] Filter 18 associated with FIFO */ + __IO uint32_t FAF19 : 1; /*!< [19..19] Filter 19 associated with FIFO */ + __IO uint32_t FAF20 : 1; /*!< [20..20] Filter 20 associated with FIFO */ + __IO uint32_t FAF21 : 1; /*!< [21..21] Filter 21 associated with FIFO */ + __IO uint32_t FAF22 : 1; /*!< [22..22] Filter 22 associated with FIFO */ + __IO uint32_t FAF23 : 1; /*!< [23..23] Filter 23 associated with FIFO */ + __IO uint32_t FAF24 : 1; /*!< [24..24] Filter 24 associated with FIFO */ + __IO uint32_t FAF25 : 1; /*!< [25..25] Filter 25 associated with FIFO */ + __IO uint32_t FAF26 : 1; /*!< [26..26] Filter 26 associated with FIFO */ + __IO uint32_t FAF27 : 1; /*!< [27..27] Filter 27 associated with FIFO */ + uint32_t : 4; + } FAFIFO_b; + } ; + __I uint32_t RESERVED4; + + union { + __IO uint32_t FW; /*!< (@ 0x0000021C) Filter working register */ + + struct { + __IO uint32_t FW0 : 1; /*!< [0..0] Filter working */ + __IO uint32_t FW1 : 1; /*!< [1..1] Filter working */ + __IO uint32_t FW2 : 1; /*!< [2..2] Filter working */ + __IO uint32_t FW3 : 1; /*!< [3..3] Filter working */ + __IO uint32_t FW4 : 1; /*!< [4..4] Filter working */ + __IO uint32_t FW5 : 1; /*!< [5..5] Filter working */ + __IO uint32_t FW6 : 1; /*!< [6..6] Filter working */ + __IO uint32_t FW7 : 1; /*!< [7..7] Filter working */ + __IO uint32_t FW8 : 1; /*!< [8..8] Filter working */ + __IO uint32_t FW9 : 1; /*!< [9..9] Filter working */ + __IO uint32_t FW10 : 1; /*!< [10..10] Filter working */ + __IO uint32_t FW11 : 1; /*!< [11..11] Filter working */ + __IO uint32_t FW12 : 1; /*!< [12..12] Filter working */ + __IO uint32_t FW13 : 1; /*!< [13..13] Filter working */ + __IO uint32_t FW14 : 1; /*!< [14..14] Filter working */ + __IO uint32_t FW15 : 1; /*!< [15..15] Filter working */ + __IO uint32_t FW16 : 1; /*!< [16..16] Filter working */ + __IO uint32_t FW17 : 1; /*!< [17..17] Filter working */ + __IO uint32_t FW18 : 1; /*!< [18..18] Filter working */ + __IO uint32_t FW19 : 1; /*!< [19..19] Filter working */ + __IO uint32_t FW20 : 1; /*!< [20..20] Filter working */ + __IO uint32_t FW21 : 1; /*!< [21..21] Filter working */ + __IO uint32_t FW22 : 1; /*!< [22..22] Filter working */ + __IO uint32_t FW23 : 1; /*!< [23..23] Filter working */ + __IO uint32_t FW24 : 1; /*!< [24..24] Filter working */ + __IO uint32_t FW25 : 1; /*!< [25..25] Filter working */ + __IO uint32_t FW26 : 1; /*!< [26..26] Filter working */ + __IO uint32_t FW27 : 1; /*!< [27..27] Filter working */ + uint32_t : 4; + } FW_b; + } ; + __I uint32_t RESERVED5[8]; + + union { + __IO uint32_t F0DATA0; /*!< (@ 0x00000240) Filter 0 data 0 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F0DATA0_b; + } ; + + union { + __IO uint32_t F0DATA1; /*!< (@ 0x00000244) Filter 0 data 1 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F0DATA1_b; + } ; + + union { + __IO uint32_t F1DATA0; /*!< (@ 0x00000248) Filter 1 data 0 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F1DATA0_b; + } ; + + union { + __IO uint32_t F1DATA1; /*!< (@ 0x0000024C) Filter 1 data 1 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F1DATA1_b; + } ; + + union { + __IO uint32_t F2DATA0; /*!< (@ 0x00000250) Filter 2 data 0 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F2DATA0_b; + } ; + + union { + __IO uint32_t F2DATA1; /*!< (@ 0x00000254) Filter 2 data 1 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F2DATA1_b; + } ; + + union { + __IO uint32_t F3DATA0; /*!< (@ 0x00000258) Filter 3 data 0 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F3DATA0_b; + } ; + + union { + __IO uint32_t F3DATA1; /*!< (@ 0x0000025C) Filter 3 data 1 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F3DATA1_b; + } ; + + union { + __IO uint32_t F4DATA0; /*!< (@ 0x00000260) Filter 4 data 0 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F4DATA0_b; + } ; + + union { + __IO uint32_t F4DATA1; /*!< (@ 0x00000264) Filter 4 data 1 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F4DATA1_b; + } ; + + union { + __IO uint32_t F5DATA0; /*!< (@ 0x00000268) Filter 5 data 0 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F5DATA0_b; + } ; + + union { + __IO uint32_t F5DATA1; /*!< (@ 0x0000026C) Filter 5 data 1 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F5DATA1_b; + } ; + + union { + __IO uint32_t F6DATA0; /*!< (@ 0x00000270) Filter 6 data 0 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F6DATA0_b; + } ; + + union { + __IO uint32_t F6DATA1; /*!< (@ 0x00000274) Filter 6 data 1 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F6DATA1_b; + } ; + + union { + __IO uint32_t F7DATA0; /*!< (@ 0x00000278) Filter 7 data 0 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F7DATA0_b; + } ; + + union { + __IO uint32_t F7DATA1; /*!< (@ 0x0000027C) Filter 7 data 1 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F7DATA1_b; + } ; + + union { + __IO uint32_t F8DATA0; /*!< (@ 0x00000280) Filter 8 data 0 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F8DATA0_b; + } ; + + union { + __IO uint32_t F8DATA1; /*!< (@ 0x00000284) Filter 8 data 1 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F8DATA1_b; + } ; + + union { + __IO uint32_t F9DATA0; /*!< (@ 0x00000288) Filter 9 data 0 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F9DATA0_b; + } ; + + union { + __IO uint32_t F9DATA1; /*!< (@ 0x0000028C) Filter 9 data 1 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F9DATA1_b; + } ; + + union { + __IO uint32_t F10DATA0; /*!< (@ 0x00000290) Filter 10 data 0 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F10DATA0_b; + } ; + + union { + __IO uint32_t F10DATA1; /*!< (@ 0x00000294) Filter 10 data 1 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F10DATA1_b; + } ; + + union { + __IO uint32_t F11DATA0; /*!< (@ 0x00000298) Filter 11 data 0 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F11DATA0_b; + } ; + + union { + __IO uint32_t F11DATA1; /*!< (@ 0x0000029C) Filter 11 data 1 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F11DATA1_b; + } ; + + union { + __IO uint32_t F12DATA0; /*!< (@ 0x000002A0) Filter 12 data 0 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F12DATA0_b; + } ; + + union { + __IO uint32_t F12DATA1; /*!< (@ 0x000002A4) Filter 12 data 1 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F12DATA1_b; + } ; + + union { + __IO uint32_t F13DATA0; /*!< (@ 0x000002A8) Filter 13 data 0 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F13DATA0_b; + } ; + + union { + __IO uint32_t F13DATA1; /*!< (@ 0x000002AC) Filter 13 data 1 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F13DATA1_b; + } ; + + union { + __IO uint32_t F14DATA0; /*!< (@ 0x000002B0) Filter 14 data 0 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F14DATA0_b; + } ; + + union { + __IO uint32_t F14DATA1; /*!< (@ 0x000002B4) Filter 14 data 1 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F14DATA1_b; + } ; + + union { + __IO uint32_t F15DATA0; /*!< (@ 0x000002B8) Filter 15 data 0 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F15DATA0_b; + } ; + + union { + __IO uint32_t F15DATA1; /*!< (@ 0x000002BC) Filter 15 data 1 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F15DATA1_b; + } ; + + union { + __IO uint32_t F16DATA0; /*!< (@ 0x000002C0) Filter 16 data 0 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F16DATA0_b; + } ; + + union { + __IO uint32_t F16DATA1; /*!< (@ 0x000002C4) Filter 16 data 1 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F16DATA1_b; + } ; + + union { + __IO uint32_t F17DATA0; /*!< (@ 0x000002C8) Filter 17 data 0 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F17DATA0_b; + } ; + + union { + __IO uint32_t F17DATA1; /*!< (@ 0x000002CC) Filter 17 data 1 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F17DATA1_b; + } ; + + union { + __IO uint32_t F18DATA0; /*!< (@ 0x000002D0) Filter 18 data 0 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F18DATA0_b; + } ; + + union { + __IO uint32_t F18DATA1; /*!< (@ 0x000002D4) Filter 18 data 1 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F18DATA1_b; + } ; + + union { + __IO uint32_t F19DATA0; /*!< (@ 0x000002D8) Filter 19 data 0 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F19DATA0_b; + } ; + + union { + __IO uint32_t F19DATA1; /*!< (@ 0x000002DC) Filter 19 data 1 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F19DATA1_b; + } ; + + union { + __IO uint32_t F20DATA0; /*!< (@ 0x000002E0) Filter 20 data 0 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F20DATA0_b; + } ; + + union { + __IO uint32_t F20DATA1; /*!< (@ 0x000002E4) Filter 20 data 1 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F20DATA1_b; + } ; + + union { + __IO uint32_t F21DATA0; /*!< (@ 0x000002E8) Filter 21 data 0 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F21DATA0_b; + } ; + + union { + __IO uint32_t F21DATA1; /*!< (@ 0x000002EC) Filter 21 data 1 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F21DATA1_b; + } ; + + union { + __IO uint32_t F22DATA0; /*!< (@ 0x000002F0) Filter 22 data 0 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F22DATA0_b; + } ; + + union { + __IO uint32_t F22DATA1; /*!< (@ 0x000002F4) Filter 22 data 1 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F22DATA1_b; + } ; + + union { + __IO uint32_t F23DATA0; /*!< (@ 0x000002F8) Filter 23 data 0 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F23DATA0_b; + } ; + + union { + __IO uint32_t F23DATA1; /*!< (@ 0x000002FC) Filter 23 data 1 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F23DATA1_b; + } ; + + union { + __IO uint32_t F24DATA0; /*!< (@ 0x00000300) Filter 24 data 0 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F24DATA0_b; + } ; + + union { + __IO uint32_t F24DATA1; /*!< (@ 0x00000304) Filter 24 data 1 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F24DATA1_b; + } ; + + union { + __IO uint32_t F25DATA0; /*!< (@ 0x00000308) Filter 25 data 0 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F25DATA0_b; + } ; + + union { + __IO uint32_t F25DATA1; /*!< (@ 0x0000030C) Filter 25 data 1 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F25DATA1_b; + } ; + + union { + __IO uint32_t F26DATA0; /*!< (@ 0x00000310) Filter 26 data 0 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F26DATA0_b; + } ; + + union { + __IO uint32_t F26DATA1; /*!< (@ 0x00000314) Filter 26 data 1 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F26DATA1_b; + } ; + + union { + __IO uint32_t F27DATA0; /*!< (@ 0x00000318) Filter 27 data 0 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F27DATA0_b; + } ; + + union { + __IO uint32_t F27DATA1; /*!< (@ 0x0000031C) Filter 27 data 1 register */ + + struct { + __IO uint32_t FD0 : 1; /*!< [0..0] Filter bits */ + __IO uint32_t FD1 : 1; /*!< [1..1] Filter bits */ + __IO uint32_t FD2 : 1; /*!< [2..2] Filter bits */ + __IO uint32_t FD3 : 1; /*!< [3..3] Filter bits */ + __IO uint32_t FD4 : 1; /*!< [4..4] Filter bits */ + __IO uint32_t FD5 : 1; /*!< [5..5] Filter bits */ + __IO uint32_t FD6 : 1; /*!< [6..6] Filter bits */ + __IO uint32_t FD7 : 1; /*!< [7..7] Filter bits */ + __IO uint32_t FD8 : 1; /*!< [8..8] Filter bits */ + __IO uint32_t FD9 : 1; /*!< [9..9] Filter bits */ + __IO uint32_t FD10 : 1; /*!< [10..10] Filter bits */ + __IO uint32_t FD11 : 1; /*!< [11..11] Filter bits */ + __IO uint32_t FD12 : 1; /*!< [12..12] Filter bits */ + __IO uint32_t FD13 : 1; /*!< [13..13] Filter bits */ + __IO uint32_t FD14 : 1; /*!< [14..14] Filter bits */ + __IO uint32_t FD15 : 1; /*!< [15..15] Filter bits */ + __IO uint32_t FD16 : 1; /*!< [16..16] Filter bits */ + __IO uint32_t FD17 : 1; /*!< [17..17] Filter bits */ + __IO uint32_t FD18 : 1; /*!< [18..18] Filter bits */ + __IO uint32_t FD19 : 1; /*!< [19..19] Filter bits */ + __IO uint32_t FD20 : 1; /*!< [20..20] Filter bits */ + __IO uint32_t FD21 : 1; /*!< [21..21] Filter bits */ + __IO uint32_t FD22 : 1; /*!< [22..22] Filter bits */ + __IO uint32_t FD23 : 1; /*!< [23..23] Filter bits */ + __IO uint32_t FD24 : 1; /*!< [24..24] Filter bits */ + __IO uint32_t FD25 : 1; /*!< [25..25] Filter bits */ + __IO uint32_t FD26 : 1; /*!< [26..26] Filter bits */ + __IO uint32_t FD27 : 1; /*!< [27..27] Filter bits */ + __IO uint32_t FD28 : 1; /*!< [28..28] Filter bits */ + __IO uint32_t FD29 : 1; /*!< [29..29] Filter bits */ + __IO uint32_t FD30 : 1; /*!< [30..30] Filter bits */ + __IO uint32_t FD31 : 1; /*!< [31..31] Filter bits */ + } F27DATA1_b; + } ; +} CAN0_Type; /*!< Size = 800 (0x320) */ + + + +/* =========================================================================================================================== */ +/* ================ CRC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief cyclic redundancy check calculation unit (CRC) + */ + +typedef struct { /*!< (@ 0x40023000) CRC Structure */ + + union { + __IO uint32_t DATA; /*!< (@ 0x00000000) Data register */ + + struct { + __IO uint32_t DATA : 32; /*!< [31..0] CRC calculation result bits */ + } DATA_b; + } ; + + union { + __IO uint32_t FDATA; /*!< (@ 0x00000004) Free data register */ + + struct { + __IO uint32_t FDATA : 8; /*!< [7..0] Free Data Register bits */ + uint32_t : 24; + } FDATA_b; + } ; + + union { + __IO uint32_t CTL; /*!< (@ 0x00000008) Control register */ + + struct { + __IO uint32_t RST : 1; /*!< [0..0] reset bit */ + uint32_t : 31; + } CTL_b; + } ; +} CRC_Type; /*!< Size = 12 (0xc) */ + + + +/* =========================================================================================================================== */ +/* ================ DAC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Digital-to-analog converter (DAC) + */ + +typedef struct { /*!< (@ 0x40007400) DAC Structure */ + + union { + __IO uint32_t CTL; /*!< (@ 0x00000000) control register */ + + struct { + __IO uint32_t DEN0 : 1; /*!< [0..0] DAC0 enable */ + __IO uint32_t DBOFF0 : 1; /*!< [1..1] DAC0 output buffer turn off */ + __IO uint32_t DTEN0 : 1; /*!< [2..2] DAC0 trigger enable */ + __IO uint32_t DTSEL0 : 3; /*!< [5..3] DAC0 trigger selection */ + __IO uint32_t DWM0 : 2; /*!< [7..6] DAC0 noise wave mode */ + __IO uint32_t DWBW0 : 4; /*!< [11..8] DAC0 noise wave bit width */ + __IO uint32_t DDMAEN0 : 1; /*!< [12..12] DAC0 DMA enable */ + uint32_t : 3; + __IO uint32_t DEN1 : 1; /*!< [16..16] DAC1 enable */ + __IO uint32_t DBOFF1 : 1; /*!< [17..17] DAC1 output buffer turn off */ + __IO uint32_t DTEN1 : 1; /*!< [18..18] DAC1 trigger enable */ + __IO uint32_t DTSEL1 : 3; /*!< [21..19] DAC1 trigger selection */ + __IO uint32_t DWM1 : 2; /*!< [23..22] DAC1 noise wave mode */ + __IO uint32_t DWBW1 : 4; /*!< [27..24] DAC1 noise wave bit width */ + __IO uint32_t DDMAEN1 : 1; /*!< [28..28] DAC1 DMA enable */ + uint32_t : 3; + } CTL_b; + } ; + + union { + __O uint32_t SWT; /*!< (@ 0x00000004) software trigger register */ + + struct { + __O uint32_t SWTR0 : 1; /*!< [0..0] DAC0 software trigger */ + __O uint32_t SWTR1 : 1; /*!< [1..1] DAC1 software trigger */ + uint32_t : 30; + } SWT_b; + } ; + + union { + __IO uint32_t DAC0_R12DH; /*!< (@ 0x00000008) DAC0 12-bit right-aligned data holding register */ + + struct { + __IO uint32_t DAC0_DH : 12; /*!< [11..0] DAC0 12-bit right-aligned data */ + uint32_t : 20; + } DAC0_R12DH_b; + } ; + + union { + __IO uint32_t DAC0_L12DH; /*!< (@ 0x0000000C) DAC0 12-bit left-aligned data holding register */ + + struct { + uint32_t : 4; + __IO uint32_t DAC0_DH : 12; /*!< [15..4] DAC0 12-bit left-aligned data */ + uint32_t : 16; + } DAC0_L12DH_b; + } ; + + union { + __IO uint32_t DAC0_R8DH; /*!< (@ 0x00000010) DAC0 8-bit right aligned data holding register */ + + struct { + __IO uint32_t DAC0_DH : 8; /*!< [7..0] DAC0 8-bit right-aligned data */ + uint32_t : 24; + } DAC0_R8DH_b; + } ; + + union { + __IO uint32_t DAC1_R12DH; /*!< (@ 0x00000014) DAC1 12-bit right-aligned data holding register */ + + struct { + __IO uint32_t DAC1_DH : 12; /*!< [11..0] DAC1 12-bit right-aligned data */ + uint32_t : 20; + } DAC1_R12DH_b; + } ; + + union { + __IO uint32_t DAC1_L12DH; /*!< (@ 0x00000018) DAC1 12-bit left aligned data holding register */ + + struct { + uint32_t : 4; + __IO uint32_t DAC1_DH : 12; /*!< [15..4] DAC1 12-bit left-aligned data */ + uint32_t : 16; + } DAC1_L12DH_b; + } ; + + union { + __IO uint32_t DAC1_R8DH; /*!< (@ 0x0000001C) DAC1 8-bit right aligned data holding register */ + + struct { + __IO uint32_t DAC1_DH : 8; /*!< [7..0] DAC1 8-bit right-aligned data */ + uint32_t : 24; + } DAC1_R8DH_b; + } ; + + union { + __IO uint32_t DACC_R12DH; /*!< (@ 0x00000020) DAC concurrent mode 12-bit right-aligned data + holding register */ + + struct { + __IO uint32_t DAC0_DH : 12; /*!< [11..0] DAC0 12-bit right-aligned data */ + uint32_t : 4; + __IO uint32_t DAC1_DH : 12; /*!< [27..16] DAC1 12-bit right-aligned data */ + uint32_t : 4; + } DACC_R12DH_b; + } ; + + union { + __IO uint32_t DACC_L12DH; /*!< (@ 0x00000024) DAC concurrent mode 12-bit left aligned data + holding register */ + + struct { + uint32_t : 4; + __IO uint32_t DAC0_DH : 12; /*!< [15..4] DAC0 12-bit left-aligned data */ + uint32_t : 4; + __IO uint32_t DAC1_DH : 12; /*!< [31..20] DAC1 12-bit left-aligned data */ + } DACC_L12DH_b; + } ; + + union { + __IO uint32_t DACC_R8DH; /*!< (@ 0x00000028) DAC concurrent mode 8-bit right aligned data + holding register */ + + struct { + __IO uint32_t DAC0_DH : 8; /*!< [7..0] DAC0 8-bit right-aligned data */ + __IO uint32_t DAC1_DH : 8; /*!< [15..8] DAC1 8-bit right-aligned data */ + uint32_t : 16; + } DACC_R8DH_b; + } ; + + union { + __I uint32_t DAC0_DO; /*!< (@ 0x0000002C) DAC0 data output register */ + + struct { + __I uint32_t DAC0_DO : 12; /*!< [11..0] DAC0 data output */ + uint32_t : 20; + } DAC0_DO_b; + } ; + + union { + __I uint32_t DAC1_DO; /*!< (@ 0x00000030) DAC1 data output register */ + + struct { + __I uint32_t DAC1_DO : 12; /*!< [11..0] DAC1 data output */ + uint32_t : 20; + } DAC1_DO_b; + } ; +} DAC_Type; /*!< Size = 52 (0x34) */ + + + +/* =========================================================================================================================== */ +/* ================ DBG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Debug support (DBG) + */ + +typedef struct { /*!< (@ 0xE0042000) DBG Structure */ + + union { + __I uint32_t ID; /*!< (@ 0x00000000) ID code register */ + + struct { + __I uint32_t ID_CODE : 32; /*!< [31..0] DBG ID code register */ + } ID_b; + } ; + + union { + __IO uint32_t CTL; /*!< (@ 0x00000004) Control register 0 */ + + struct { + __IO uint32_t SLP_HOLD : 1; /*!< [0..0] Sleep mode hold register */ + __IO uint32_t DSLP_HOLD : 1; /*!< [1..1] Deep-sleep mode hold register */ + __IO uint32_t STB_HOLD : 1; /*!< [2..2] Standby mode hold register */ + uint32_t : 5; + __IO uint32_t FWDGT_HOLD : 1; /*!< [8..8] FWDGT hold bit */ + __IO uint32_t WWDGT_HOLD : 1; /*!< [9..9] WWDGT hold bit */ + __IO uint32_t TIMER0_HOLD : 1; /*!< [10..10] TIMER 0 hold bit */ + __IO uint32_t TIMER1_HOLD : 1; /*!< [11..11] TIMER 1 hold bit */ + __IO uint32_t TIMER2_HOLD : 1; /*!< [12..12] TIMER 2 hold bit */ + __IO uint32_t TIMER3_HOLD : 1; /*!< [13..13] TIMER 23 hold bit */ + __IO uint32_t CAN0_HOLD : 1; /*!< [14..14] CAN0 hold bit */ + __IO uint32_t I2C0_HOLD : 1; /*!< [15..15] I2C0 hold bit */ + __IO uint32_t I2C1_HOLD : 1; /*!< [16..16] I2C1 hold bit */ + uint32_t : 1; + __IO uint32_t TIMER4_HOLD : 1; /*!< [18..18] TIMER4_HOLD */ + __IO uint32_t TIMER5_HOLD : 1; /*!< [19..19] TIMER 5 hold bit */ + __IO uint32_t TIMER6_HOLD : 1; /*!< [20..20] TIMER 6 hold bit */ + __IO uint32_t CAN1_HOLD : 1; /*!< [21..21] CAN1 hold bit */ + uint32_t : 10; + } CTL_b; + } ; +} DBG_Type; /*!< Size = 8 (0x8) */ + + + +/* =========================================================================================================================== */ +/* ================ DMA0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief DMA controller (DMA0) + */ + +typedef struct { /*!< (@ 0x40020000) DMA0 Structure */ + + union { + __I uint32_t INTF; /*!< (@ 0x00000000) Interrupt flag register */ + + struct { + __I uint32_t GIF0 : 1; /*!< [0..0] Global interrupt flag of channel 0 */ + __I uint32_t FTFIF0 : 1; /*!< [1..1] Full Transfer finish flag of channe 0 */ + __I uint32_t HTFIF0 : 1; /*!< [2..2] Half transfer finish flag of channel 0 */ + __I uint32_t ERRIF0 : 1; /*!< [3..3] Error flag of channel 0 */ + __I uint32_t GIF1 : 1; /*!< [4..4] Global interrupt flag of channel 1 */ + __I uint32_t FTFIF1 : 1; /*!< [5..5] Full Transfer finish flag of channe 1 */ + __I uint32_t HTFIF1 : 1; /*!< [6..6] Half transfer finish flag of channel 1 */ + __I uint32_t ERRIF1 : 1; /*!< [7..7] Error flag of channel 1 */ + __I uint32_t GIF2 : 1; /*!< [8..8] Global interrupt flag of channel 2 */ + __I uint32_t FTFIF2 : 1; /*!< [9..9] Full Transfer finish flag of channe 2 */ + __I uint32_t HTFIF2 : 1; /*!< [10..10] Half transfer finish flag of channel 2 */ + __I uint32_t ERRIF2 : 1; /*!< [11..11] Error flag of channel 2 */ + __I uint32_t GIF3 : 1; /*!< [12..12] Global interrupt flag of channel 3 */ + __I uint32_t FTFIF3 : 1; /*!< [13..13] Full Transfer finish flag of channe 3 */ + __I uint32_t HTFIF3 : 1; /*!< [14..14] Half transfer finish flag of channel 3 */ + __I uint32_t ERRIF3 : 1; /*!< [15..15] Error flag of channel 3 */ + __I uint32_t GIF4 : 1; /*!< [16..16] Global interrupt flag of channel 4 */ + __I uint32_t FTFIF4 : 1; /*!< [17..17] Full Transfer finish flag of channe 4 */ + __I uint32_t HTFIF4 : 1; /*!< [18..18] Half transfer finish flag of channel 4 */ + __I uint32_t ERRIF4 : 1; /*!< [19..19] Error flag of channel 4 */ + __I uint32_t GIF5 : 1; /*!< [20..20] Global interrupt flag of channel 5 */ + __I uint32_t FTFIF5 : 1; /*!< [21..21] Full Transfer finish flag of channe 5 */ + __I uint32_t HTFIF5 : 1; /*!< [22..22] Half transfer finish flag of channel 5 */ + __I uint32_t ERRIF5 : 1; /*!< [23..23] Error flag of channel 5 */ + __I uint32_t GIF6 : 1; /*!< [24..24] Global interrupt flag of channel 6 */ + __I uint32_t FTFIF6 : 1; /*!< [25..25] Full Transfer finish flag of channe 6 */ + __I uint32_t HTFIF6 : 1; /*!< [26..26] Half transfer finish flag of channel 6 */ + __I uint32_t ERRIF6 : 1; /*!< [27..27] Error flag of channel 6 */ + uint32_t : 4; + } INTF_b; + } ; + + union { + __O uint32_t INTC; /*!< (@ 0x00000004) Interrupt flag clear register */ + + struct { + __O uint32_t GIFC0 : 1; /*!< [0..0] Clear global interrupt flag of channel 0 */ + __O uint32_t FTFIFC0 : 1; /*!< [1..1] Clear bit for full transfer finish flag of channel 0 */ + __O uint32_t HTFIFC0 : 1; /*!< [2..2] Clear bit for half transfer finish flag of channel 0 */ + __O uint32_t ERRIFC0 : 1; /*!< [3..3] Clear bit for error flag of channel 0 */ + __O uint32_t GIFC1 : 1; /*!< [4..4] Clear global interrupt flag of channel 1 */ + __O uint32_t FTFIFC1 : 1; /*!< [5..5] Clear bit for full transfer finish flag of channel 1 */ + __O uint32_t HTFIFC1 : 1; /*!< [6..6] Clear bit for half transfer finish flag of channel 1 */ + __O uint32_t ERRIFC1 : 1; /*!< [7..7] Clear bit for error flag of channel 1 */ + __O uint32_t GIFC2 : 1; /*!< [8..8] Clear global interrupt flag of channel 2 */ + __O uint32_t FTFIFC2 : 1; /*!< [9..9] Clear bit for full transfer finish flag of channel 2 */ + __O uint32_t HTFIFC2 : 1; /*!< [10..10] Clear bit for half transfer finish flag of channel + 2 */ + __O uint32_t ERRIFC2 : 1; /*!< [11..11] Clear bit for error flag of channel 2 */ + __O uint32_t GIFC3 : 1; /*!< [12..12] Clear global interrupt flag of channel 3 */ + __O uint32_t FTFIFC3 : 1; /*!< [13..13] Clear bit for full transfer finish flag of channel + 3 */ + __O uint32_t HTFIFC3 : 1; /*!< [14..14] Clear bit for half transfer finish flag of channel + 3 */ + __O uint32_t ERRIFC3 : 1; /*!< [15..15] Clear bit for error flag of channel 3 */ + __O uint32_t GIFC4 : 1; /*!< [16..16] Clear global interrupt flag of channel 4 */ + __O uint32_t FTFIFC4 : 1; /*!< [17..17] Clear bit for full transfer finish flag of channel + 4 */ + __O uint32_t HTFIFC4 : 1; /*!< [18..18] Clear bit for half transfer finish flag of channel + 4 */ + __O uint32_t ERRIFC4 : 1; /*!< [19..19] Clear bit for error flag of channel 4 */ + __O uint32_t GIFC5 : 1; /*!< [20..20] Clear global interrupt flag of channel 5 */ + __O uint32_t FTFIFC5 : 1; /*!< [21..21] Clear bit for full transfer finish flag of channel + 5 */ + __O uint32_t HTFIFC5 : 1; /*!< [22..22] Clear bit for half transfer finish flag of channel + 5 */ + __O uint32_t ERRIFC5 : 1; /*!< [23..23] Clear bit for error flag of channel 5 */ + __O uint32_t GIFC6 : 1; /*!< [24..24] Clear global interrupt flag of channel 6 */ + __O uint32_t FTFIFC6 : 1; /*!< [25..25] Clear bit for full transfer finish flag of channel + 6 */ + __O uint32_t HTFIFC6 : 1; /*!< [26..26] Clear bit for half transfer finish flag of channel + 6 */ + __O uint32_t ERRIFC6 : 1; /*!< [27..27] Clear bit for error flag of channel 6 */ + uint32_t : 4; + } INTC_b; + } ; + + union { + __IO uint32_t CH0CTL; /*!< (@ 0x00000008) Channel 0 control register */ + + struct { + __IO uint32_t CHEN : 1; /*!< [0..0] Channel enable */ + __IO uint32_t FTFIE : 1; /*!< [1..1] Enable bit for channel full transfer finish interrupt */ + __IO uint32_t HTFIE : 1; /*!< [2..2] Enable bit for channel half transfer finish interrupt */ + __IO uint32_t ERRIE : 1; /*!< [3..3] Enable bit for channel error interrupt */ + __IO uint32_t DIR : 1; /*!< [4..4] Transfer direction */ + __IO uint32_t CMEN : 1; /*!< [5..5] Circular mode enable */ + __IO uint32_t PNAGA : 1; /*!< [6..6] Next address generation algorithm of peripheral */ + __IO uint32_t MNAGA : 1; /*!< [7..7] Next address generation algorithm of memory */ + __IO uint32_t PWIDTH : 2; /*!< [9..8] Transfer data size of peripheral */ + __IO uint32_t MWIDTH : 2; /*!< [11..10] Transfer data size of memory */ + __IO uint32_t PRIO : 2; /*!< [13..12] Priority level */ + __IO uint32_t M2M : 1; /*!< [14..14] Memory to Memory Mode */ + uint32_t : 17; + } CH0CTL_b; + } ; + + union { + __IO uint32_t CH0CNT; /*!< (@ 0x0000000C) Channel 0 counter register */ + + struct { + __IO uint32_t CNT : 16; /*!< [15..0] Transfer counter */ + uint32_t : 16; + } CH0CNT_b; + } ; + + union { + __IO uint32_t CH0PADDR; /*!< (@ 0x00000010) Channel 0 peripheral base address register */ + + struct { + __IO uint32_t PADDR : 32; /*!< [31..0] Peripheral base address */ + } CH0PADDR_b; + } ; + + union { + __IO uint32_t CH0MADDR; /*!< (@ 0x00000014) Channel 0 memory base address register */ + + struct { + __IO uint32_t MADDR : 32; /*!< [31..0] Memory base address */ + } CH0MADDR_b; + } ; + __I uint32_t RESERVED; + + union { + __IO uint32_t CH1CTL; /*!< (@ 0x0000001C) Channel 1 control register */ + + struct { + __IO uint32_t CHEN : 1; /*!< [0..0] Channel enable */ + __IO uint32_t FTFIE : 1; /*!< [1..1] Enable bit for channel full transfer finish interrupt */ + __IO uint32_t HTFIE : 1; /*!< [2..2] Enable bit for channel half transfer finish interrupt */ + __IO uint32_t ERRIE : 1; /*!< [3..3] Enable bit for channel error interrupt */ + __IO uint32_t DIR : 1; /*!< [4..4] Transfer direction */ + __IO uint32_t CMEN : 1; /*!< [5..5] Circular mode enable */ + __IO uint32_t PNAGA : 1; /*!< [6..6] Next address generation algorithm of peripheral */ + __IO uint32_t MNAGA : 1; /*!< [7..7] Next address generation algorithm of memory */ + __IO uint32_t PWIDTH : 2; /*!< [9..8] Transfer data size of peripheral */ + __IO uint32_t MWIDTH : 2; /*!< [11..10] Transfer data size of memory */ + __IO uint32_t PRIO : 2; /*!< [13..12] Priority level */ + __IO uint32_t M2M : 1; /*!< [14..14] Memory to Memory Mode */ + uint32_t : 17; + } CH1CTL_b; + } ; + + union { + __IO uint32_t CH1CNT; /*!< (@ 0x00000020) Channel 1 counter register */ + + struct { + __IO uint32_t CNT : 16; /*!< [15..0] Transfer counter */ + uint32_t : 16; + } CH1CNT_b; + } ; + + union { + __IO uint32_t CH1PADDR; /*!< (@ 0x00000024) Channel 1 peripheral base address register */ + + struct { + __IO uint32_t PADDR : 32; /*!< [31..0] Peripheral base address */ + } CH1PADDR_b; + } ; + + union { + __IO uint32_t CH1MADDR; /*!< (@ 0x00000028) Channel 1 memory base address register */ + + struct { + __IO uint32_t MADDR : 32; /*!< [31..0] Memory base address */ + } CH1MADDR_b; + } ; + __I uint32_t RESERVED1; + + union { + __IO uint32_t CH2CTL; /*!< (@ 0x00000030) Channel 2 control register */ + + struct { + __IO uint32_t CHEN : 1; /*!< [0..0] Channel enable */ + __IO uint32_t FTFIE : 1; /*!< [1..1] Enable bit for channel full transfer finish interrupt */ + __IO uint32_t HTFIE : 1; /*!< [2..2] Enable bit for channel half transfer finish interrupt */ + __IO uint32_t ERRIE : 1; /*!< [3..3] Enable bit for channel error interrupt */ + __IO uint32_t DIR : 1; /*!< [4..4] Transfer direction */ + __IO uint32_t CMEN : 1; /*!< [5..5] Circular mode enable */ + __IO uint32_t PNAGA : 1; /*!< [6..6] Next address generation algorithm of peripheral */ + __IO uint32_t MNAGA : 1; /*!< [7..7] Next address generation algorithm of memory */ + __IO uint32_t PWIDTH : 2; /*!< [9..8] Transfer data size of peripheral */ + __IO uint32_t MWIDTH : 2; /*!< [11..10] Transfer data size of memory */ + __IO uint32_t PRIO : 2; /*!< [13..12] Priority level */ + __IO uint32_t M2M : 1; /*!< [14..14] Memory to Memory Mode */ + uint32_t : 17; + } CH2CTL_b; + } ; + + union { + __IO uint32_t CH2CNT; /*!< (@ 0x00000034) Channel 2 counter register */ + + struct { + __IO uint32_t CNT : 16; /*!< [15..0] Transfer counter */ + uint32_t : 16; + } CH2CNT_b; + } ; + + union { + __IO uint32_t CH2PADDR; /*!< (@ 0x00000038) Channel 2 peripheral base address register */ + + struct { + __IO uint32_t PADDR : 32; /*!< [31..0] Peripheral base address */ + } CH2PADDR_b; + } ; + + union { + __IO uint32_t CH2MADDR; /*!< (@ 0x0000003C) Channel 2 memory base address register */ + + struct { + __IO uint32_t MADDR : 32; /*!< [31..0] Memory base address */ + } CH2MADDR_b; + } ; + __I uint32_t RESERVED2; + + union { + __IO uint32_t CH3CTL; /*!< (@ 0x00000044) Channel 3 control register */ + + struct { + __IO uint32_t CHEN : 1; /*!< [0..0] Channel enable */ + __IO uint32_t FTFIE : 1; /*!< [1..1] Enable bit for channel full transfer finish interrupt */ + __IO uint32_t HTFIE : 1; /*!< [2..2] Enable bit for channel half transfer finish interrupt */ + __IO uint32_t ERRIE : 1; /*!< [3..3] Enable bit for channel error interrupt */ + __IO uint32_t DIR : 1; /*!< [4..4] Transfer direction */ + __IO uint32_t CMEN : 1; /*!< [5..5] Circular mode enable */ + __IO uint32_t PNAGA : 1; /*!< [6..6] Next address generation algorithm of peripheral */ + __IO uint32_t MNAGA : 1; /*!< [7..7] Next address generation algorithm of memory */ + __IO uint32_t PWIDTH : 2; /*!< [9..8] Transfer data size of peripheral */ + __IO uint32_t MWIDTH : 2; /*!< [11..10] Transfer data size of memory */ + __IO uint32_t PRIO : 2; /*!< [13..12] Priority level */ + __IO uint32_t M2M : 1; /*!< [14..14] Memory to Memory Mode */ + uint32_t : 17; + } CH3CTL_b; + } ; + + union { + __IO uint32_t CH3CNT; /*!< (@ 0x00000048) Channel 3 counter register */ + + struct { + __IO uint32_t CNT : 16; /*!< [15..0] Transfer counter */ + uint32_t : 16; + } CH3CNT_b; + } ; + + union { + __IO uint32_t CH3PADDR; /*!< (@ 0x0000004C) Channel 3 peripheral base address register */ + + struct { + __IO uint32_t PADDR : 32; /*!< [31..0] Peripheral base address */ + } CH3PADDR_b; + } ; + + union { + __IO uint32_t CH3MADDR; /*!< (@ 0x00000050) Channel 3 memory base address register */ + + struct { + __IO uint32_t MADDR : 32; /*!< [31..0] Memory base address */ + } CH3MADDR_b; + } ; + __I uint32_t RESERVED3; + + union { + __IO uint32_t CH4CTL; /*!< (@ 0x00000058) Channel 4 control register */ + + struct { + __IO uint32_t CHEN : 1; /*!< [0..0] Channel enable */ + __IO uint32_t FTFIE : 1; /*!< [1..1] Enable bit for channel full transfer finish interrupt */ + __IO uint32_t HTFIE : 1; /*!< [2..2] Enable bit for channel half transfer finish interrupt */ + __IO uint32_t ERRIE : 1; /*!< [3..3] Enable bit for channel error interrupt */ + __IO uint32_t DIR : 1; /*!< [4..4] Transfer direction */ + __IO uint32_t CMEN : 1; /*!< [5..5] Circular mode enable */ + __IO uint32_t PNAGA : 1; /*!< [6..6] Next address generation algorithm of peripheral */ + __IO uint32_t MNAGA : 1; /*!< [7..7] Next address generation algorithm of memory */ + __IO uint32_t PWIDTH : 2; /*!< [9..8] Transfer data size of peripheral */ + __IO uint32_t MWIDTH : 2; /*!< [11..10] Transfer data size of memory */ + __IO uint32_t PRIO : 2; /*!< [13..12] Priority level */ + __IO uint32_t M2M : 1; /*!< [14..14] Memory to Memory Mode */ + uint32_t : 17; + } CH4CTL_b; + } ; + + union { + __IO uint32_t CH4CNT; /*!< (@ 0x0000005C) Channel 4 counter register */ + + struct { + __IO uint32_t CNT : 16; /*!< [15..0] Transfer counter */ + uint32_t : 16; + } CH4CNT_b; + } ; + + union { + __IO uint32_t CH4PADDR; /*!< (@ 0x00000060) Channel 4 peripheral base address register */ + + struct { + __IO uint32_t PADDR : 32; /*!< [31..0] Peripheral base address */ + } CH4PADDR_b; + } ; + + union { + __IO uint32_t CH4MADDR; /*!< (@ 0x00000064) Channel 4 memory base address register */ + + struct { + __IO uint32_t MADDR : 32; /*!< [31..0] Memory base address */ + } CH4MADDR_b; + } ; + __I uint32_t RESERVED4; + + union { + __IO uint32_t CH5CTL; /*!< (@ 0x0000006C) Channel 5 control register */ + + struct { + __IO uint32_t CHEN : 1; /*!< [0..0] Channel enable */ + __IO uint32_t FTFIE : 1; /*!< [1..1] Enable bit for channel full transfer finish interrupt */ + __IO uint32_t HTFIE : 1; /*!< [2..2] Enable bit for channel half transfer finish interrupt */ + __IO uint32_t ERRIE : 1; /*!< [3..3] Enable bit for channel error interrupt */ + __IO uint32_t DIR : 1; /*!< [4..4] Transfer direction */ + __IO uint32_t CMEN : 1; /*!< [5..5] Circular mode enable */ + __IO uint32_t PNAGA : 1; /*!< [6..6] Next address generation algorithm of peripheral */ + __IO uint32_t MNAGA : 1; /*!< [7..7] Next address generation algorithm of memory */ + __IO uint32_t PWIDTH : 2; /*!< [9..8] Transfer data size of peripheral */ + __IO uint32_t MWIDTH : 2; /*!< [11..10] Transfer data size of memory */ + __IO uint32_t PRIO : 2; /*!< [13..12] Priority level */ + __IO uint32_t M2M : 1; /*!< [14..14] Memory to Memory Mode */ + uint32_t : 17; + } CH5CTL_b; + } ; + + union { + __IO uint32_t CH5CNT; /*!< (@ 0x00000070) Channel 5 counter register */ + + struct { + __IO uint32_t CNT : 16; /*!< [15..0] Transfer counter */ + uint32_t : 16; + } CH5CNT_b; + } ; + + union { + __IO uint32_t CH5PADDR; /*!< (@ 0x00000074) Channel 5 peripheral base address register */ + + struct { + __IO uint32_t PADDR : 32; /*!< [31..0] Peripheral base address */ + } CH5PADDR_b; + } ; + + union { + __IO uint32_t CH5MADDR; /*!< (@ 0x00000078) Channel 5 memory base address register */ + + struct { + __IO uint32_t MADDR : 32; /*!< [31..0] Memory base address */ + } CH5MADDR_b; + } ; + __I uint32_t RESERVED5; + + union { + __IO uint32_t CH6CTL; /*!< (@ 0x00000080) Channel 6 control register */ + + struct { + __IO uint32_t CHEN : 1; /*!< [0..0] Channel enable */ + __IO uint32_t FTFIE : 1; /*!< [1..1] Enable bit for channel full transfer finish interrupt */ + __IO uint32_t HTFIE : 1; /*!< [2..2] Enable bit for channel half transfer finish interrupt */ + __IO uint32_t ERRIE : 1; /*!< [3..3] Enable bit for channel error interrupt */ + __IO uint32_t DIR : 1; /*!< [4..4] Transfer direction */ + __IO uint32_t CMEN : 1; /*!< [5..5] Circular mode enable */ + __IO uint32_t PNAGA : 1; /*!< [6..6] Next address generation algorithm of peripheral */ + __IO uint32_t MNAGA : 1; /*!< [7..7] Next address generation algorithm of memory */ + __IO uint32_t PWIDTH : 2; /*!< [9..8] Transfer data size of peripheral */ + __IO uint32_t MWIDTH : 2; /*!< [11..10] Transfer data size of memory */ + __IO uint32_t PRIO : 2; /*!< [13..12] Priority level */ + __IO uint32_t M2M : 1; /*!< [14..14] Memory to Memory Mode */ + uint32_t : 17; + } CH6CTL_b; + } ; + + union { + __IO uint32_t CH6CNT; /*!< (@ 0x00000084) Channel 6 counter register */ + + struct { + __IO uint32_t CNT : 16; /*!< [15..0] Transfer counter */ + uint32_t : 16; + } CH6CNT_b; + } ; + + union { + __IO uint32_t CH6PADDR; /*!< (@ 0x00000088) Channel 6 peripheral base address register */ + + struct { + __IO uint32_t PADDR : 32; /*!< [31..0] Peripheral base address */ + } CH6PADDR_b; + } ; + + union { + __IO uint32_t CH6MADDR; /*!< (@ 0x0000008C) Channel 6 memory base address register */ + + struct { + __IO uint32_t MADDR : 32; /*!< [31..0] Memory base address */ + } CH6MADDR_b; + } ; +} DMA0_Type; /*!< Size = 144 (0x90) */ + + + +/* =========================================================================================================================== */ +/* ================ DMA1 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Direct memory access controller (DMA1) + */ + +typedef struct { /*!< (@ 0x40020400) DMA1 Structure */ + + union { + __I uint32_t INTF; /*!< (@ 0x00000000) Interrupt flag register */ + + struct { + __I uint32_t GIF0 : 1; /*!< [0..0] Global interrupt flag of channel 0 */ + __I uint32_t FTFIF0 : 1; /*!< [1..1] Full Transfer finish flag of channe 0 */ + __I uint32_t HTFIF0 : 1; /*!< [2..2] Half transfer finish flag of channel 0 */ + __I uint32_t ERRIF0 : 1; /*!< [3..3] Error flag of channel 0 */ + __I uint32_t GIF1 : 1; /*!< [4..4] Global interrupt flag of channel 1 */ + __I uint32_t FTFIF1 : 1; /*!< [5..5] Full Transfer finish flag of channe 1 */ + __I uint32_t HTFIF1 : 1; /*!< [6..6] Half transfer finish flag of channel 1 */ + __I uint32_t ERRIF1 : 1; /*!< [7..7] Error flag of channel 1 */ + __I uint32_t GIF2 : 1; /*!< [8..8] Global interrupt flag of channel 2 */ + __I uint32_t FTFIF2 : 1; /*!< [9..9] Full Transfer finish flag of channe 2 */ + __I uint32_t HTFIF2 : 1; /*!< [10..10] Half transfer finish flag of channel 2 */ + __I uint32_t ERRIF2 : 1; /*!< [11..11] Error flag of channel 2 */ + __I uint32_t GIF3 : 1; /*!< [12..12] Global interrupt flag of channel 3 */ + __I uint32_t FTFIF3 : 1; /*!< [13..13] Full Transfer finish flag of channe 3 */ + __I uint32_t HTFIF3 : 1; /*!< [14..14] Half transfer finish flag of channel 3 */ + __I uint32_t ERRIF3 : 1; /*!< [15..15] Error flag of channel 3 */ + __I uint32_t GIF4 : 1; /*!< [16..16] Global interrupt flag of channel 4 */ + __I uint32_t FTFIF4 : 1; /*!< [17..17] Full Transfer finish flag of channe 4 */ + __I uint32_t HTFIF4 : 1; /*!< [18..18] Half transfer finish flag of channel 4 */ + __I uint32_t ERRIF4 : 1; /*!< [19..19] Error flag of channel 4 */ + uint32_t : 12; + } INTF_b; + } ; + + union { + __O uint32_t INTC; /*!< (@ 0x00000004) Interrupt flag clear register */ + + struct { + __O uint32_t GIFC0 : 1; /*!< [0..0] Clear global interrupt flag of channel 0 */ + __O uint32_t FTFIFC0 : 1; /*!< [1..1] Clear bit for full transfer finish flag of channel 0 */ + __O uint32_t HTFIFC0 : 1; /*!< [2..2] Clear bit for half transfer finish flag of channel 0 */ + __O uint32_t ERRIFC0 : 1; /*!< [3..3] Clear bit for error flag of channel 0 */ + __O uint32_t GIFC1 : 1; /*!< [4..4] Clear global interrupt flag of channel 1 */ + __O uint32_t FTFIFC1 : 1; /*!< [5..5] Clear bit for full transfer finish flag of channel 1 */ + __O uint32_t HTFIFC1 : 1; /*!< [6..6] Clear bit for half transfer finish flag of channel 1 */ + __O uint32_t ERRIFC1 : 1; /*!< [7..7] Clear bit for error flag of channel 1 */ + __O uint32_t GIFC2 : 1; /*!< [8..8] Clear global interrupt flag of channel 2 */ + __O uint32_t FTFIFC2 : 1; /*!< [9..9] Clear bit for full transfer finish flag of channel 2 */ + __O uint32_t HTFIFC2 : 1; /*!< [10..10] Clear bit for half transfer finish flag of channel + 2 */ + __O uint32_t ERRIFC2 : 1; /*!< [11..11] Clear bit for error flag of channel 2 */ + __O uint32_t GIFC3 : 1; /*!< [12..12] Clear global interrupt flag of channel 3 */ + __O uint32_t FTFIFC3 : 1; /*!< [13..13] Clear bit for full transfer finish flag of channel + 3 */ + __O uint32_t HTFIFC3 : 1; /*!< [14..14] Clear bit for half transfer finish flag of channel + 3 */ + __O uint32_t ERRIFC3 : 1; /*!< [15..15] Clear bit for error flag of channel 3 */ + __O uint32_t GIFC4 : 1; /*!< [16..16] Clear global interrupt flag of channel 4 */ + __O uint32_t FTFIFC4 : 1; /*!< [17..17] Clear bit for full transfer finish flag of channel + 4 */ + __O uint32_t HTFIFC4 : 1; /*!< [18..18] Clear bit for half transfer finish flag of channel + 4 */ + __O uint32_t ERRIFC4 : 1; /*!< [19..19] Clear bit for error flag of channel 4 */ + uint32_t : 12; + } INTC_b; + } ; + + union { + __IO uint32_t CH0CTL; /*!< (@ 0x00000008) Channel 0 control register */ + + struct { + __IO uint32_t CHEN : 1; /*!< [0..0] Channel enable */ + __IO uint32_t FTFIE : 1; /*!< [1..1] Enable bit for channel full transfer finish interrupt */ + __IO uint32_t HTFIE : 1; /*!< [2..2] Enable bit for channel half transfer finish interrupt */ + __IO uint32_t ERRIE : 1; /*!< [3..3] Enable bit for channel error interrupt */ + __IO uint32_t DIR : 1; /*!< [4..4] Transfer direction */ + __IO uint32_t CMEN : 1; /*!< [5..5] Circular mode enable */ + __IO uint32_t PNAGA : 1; /*!< [6..6] Next address generation algorithm of peripheral */ + __IO uint32_t MNAGA : 1; /*!< [7..7] Next address generation algorithm of memory */ + __IO uint32_t PWIDTH : 2; /*!< [9..8] Transfer data size of peripheral */ + __IO uint32_t MWIDTH : 2; /*!< [11..10] Transfer data size of memory */ + __IO uint32_t PRIO : 2; /*!< [13..12] Priority level */ + __IO uint32_t M2M : 1; /*!< [14..14] Memory to Memory Mode */ + uint32_t : 17; + } CH0CTL_b; + } ; + + union { + __IO uint32_t CH0CNT; /*!< (@ 0x0000000C) Channel 0 counter register */ + + struct { + __IO uint32_t CNT : 16; /*!< [15..0] Transfer counter */ + uint32_t : 16; + } CH0CNT_b; + } ; + + union { + __IO uint32_t CH0PADDR; /*!< (@ 0x00000010) Channel 0 peripheral base address register */ + + struct { + __IO uint32_t PADDR : 32; /*!< [31..0] Peripheral base address */ + } CH0PADDR_b; + } ; + + union { + __IO uint32_t CH0MADDR; /*!< (@ 0x00000014) Channel 0 memory base address register */ + + struct { + __IO uint32_t MADDR : 32; /*!< [31..0] Memory base address */ + } CH0MADDR_b; + } ; + __I uint32_t RESERVED; + + union { + __IO uint32_t CH1CTL; /*!< (@ 0x0000001C) Channel 1 control register */ + + struct { + __IO uint32_t CHEN : 1; /*!< [0..0] Channel enable */ + __IO uint32_t FTFIE : 1; /*!< [1..1] Enable bit for channel full transfer finish interrupt */ + __IO uint32_t HTFIE : 1; /*!< [2..2] Enable bit for channel half transfer finish interrupt */ + __IO uint32_t ERRIE : 1; /*!< [3..3] Enable bit for channel error interrupt */ + __IO uint32_t DIR : 1; /*!< [4..4] Transfer direction */ + __IO uint32_t CMEN : 1; /*!< [5..5] Circular mode enable */ + __IO uint32_t PNAGA : 1; /*!< [6..6] Next address generation algorithm of peripheral */ + __IO uint32_t MNAGA : 1; /*!< [7..7] Next address generation algorithm of memory */ + __IO uint32_t PWIDTH : 2; /*!< [9..8] Transfer data size of peripheral */ + __IO uint32_t MWIDTH : 2; /*!< [11..10] Transfer data size of memory */ + __IO uint32_t PRIO : 2; /*!< [13..12] Priority level */ + __IO uint32_t M2M : 1; /*!< [14..14] Memory to Memory Mode */ + uint32_t : 17; + } CH1CTL_b; + } ; + + union { + __IO uint32_t CH1CNT; /*!< (@ 0x00000020) Channel 1 counter register */ + + struct { + __IO uint32_t CNT : 16; /*!< [15..0] Transfer counter */ + uint32_t : 16; + } CH1CNT_b; + } ; + + union { + __IO uint32_t CH1PADDR; /*!< (@ 0x00000024) Channel 1 peripheral base address register */ + + struct { + __IO uint32_t PADDR : 32; /*!< [31..0] Peripheral base address */ + } CH1PADDR_b; + } ; + + union { + __IO uint32_t CH1MADDR; /*!< (@ 0x00000028) Channel 1 memory base address register */ + + struct { + __IO uint32_t MADDR : 32; /*!< [31..0] Memory base address */ + } CH1MADDR_b; + } ; + __I uint32_t RESERVED1; + + union { + __IO uint32_t CH2CTL; /*!< (@ 0x00000030) Channel 2 control register */ + + struct { + __IO uint32_t CHEN : 1; /*!< [0..0] Channel enable */ + __IO uint32_t FTFIE : 1; /*!< [1..1] Enable bit for channel full transfer finish interrupt */ + __IO uint32_t HTFIE : 1; /*!< [2..2] Enable bit for channel half transfer finish interrupt */ + __IO uint32_t ERRIE : 1; /*!< [3..3] Enable bit for channel error interrupt */ + __IO uint32_t DIR : 1; /*!< [4..4] Transfer direction */ + __IO uint32_t CMEN : 1; /*!< [5..5] Circular mode enable */ + __IO uint32_t PNAGA : 1; /*!< [6..6] Next address generation algorithm of peripheral */ + __IO uint32_t MNAGA : 1; /*!< [7..7] Next address generation algorithm of memory */ + __IO uint32_t PWIDTH : 2; /*!< [9..8] Transfer data size of peripheral */ + __IO uint32_t MWIDTH : 2; /*!< [11..10] Transfer data size of memory */ + __IO uint32_t PRIO : 2; /*!< [13..12] Priority level */ + __IO uint32_t M2M : 1; /*!< [14..14] Memory to Memory Mode */ + uint32_t : 17; + } CH2CTL_b; + } ; + + union { + __IO uint32_t CH2CNT; /*!< (@ 0x00000034) Channel 2 counter register */ + + struct { + __IO uint32_t CNT : 16; /*!< [15..0] Transfer counter */ + uint32_t : 16; + } CH2CNT_b; + } ; + + union { + __IO uint32_t CH2PADDR; /*!< (@ 0x00000038) Channel 2 peripheral base address register */ + + struct { + __IO uint32_t PADDR : 32; /*!< [31..0] Peripheral base address */ + } CH2PADDR_b; + } ; + + union { + __IO uint32_t CH2MADDR; /*!< (@ 0x0000003C) Channel 2 memory base address register */ + + struct { + __IO uint32_t MADDR : 32; /*!< [31..0] Memory base address */ + } CH2MADDR_b; + } ; + __I uint32_t RESERVED2; + + union { + __IO uint32_t CH3CTL; /*!< (@ 0x00000044) Channel 3 control register */ + + struct { + __IO uint32_t CHEN : 1; /*!< [0..0] Channel enable */ + __IO uint32_t FTFIE : 1; /*!< [1..1] Enable bit for channel full transfer finish interrupt */ + __IO uint32_t HTFIE : 1; /*!< [2..2] Enable bit for channel half transfer finish interrupt */ + __IO uint32_t ERRIE : 1; /*!< [3..3] Enable bit for channel error interrupt */ + __IO uint32_t DIR : 1; /*!< [4..4] Transfer direction */ + __IO uint32_t CMEN : 1; /*!< [5..5] Circular mode enable */ + __IO uint32_t PNAGA : 1; /*!< [6..6] Next address generation algorithm of peripheral */ + __IO uint32_t MNAGA : 1; /*!< [7..7] Next address generation algorithm of memory */ + __IO uint32_t PWIDTH : 2; /*!< [9..8] Transfer data size of peripheral */ + __IO uint32_t MWIDTH : 2; /*!< [11..10] Transfer data size of memory */ + __IO uint32_t PRIO : 2; /*!< [13..12] Priority level */ + __IO uint32_t M2M : 1; /*!< [14..14] Memory to Memory Mode */ + uint32_t : 17; + } CH3CTL_b; + } ; + + union { + __IO uint32_t CH3CNT; /*!< (@ 0x00000048) Channel 3 counter register */ + + struct { + __IO uint32_t CNT : 16; /*!< [15..0] Transfer counter */ + uint32_t : 16; + } CH3CNT_b; + } ; + + union { + __IO uint32_t CH3PADDR; /*!< (@ 0x0000004C) Channel 3 peripheral base address register */ + + struct { + __IO uint32_t PADDR : 32; /*!< [31..0] Peripheral base address */ + } CH3PADDR_b; + } ; + + union { + __IO uint32_t CH3MADDR; /*!< (@ 0x00000050) Channel 3 memory base address register */ + + struct { + __IO uint32_t MADDR : 32; /*!< [31..0] Memory base address */ + } CH3MADDR_b; + } ; + __I uint32_t RESERVED3; + + union { + __IO uint32_t CH4CTL; /*!< (@ 0x00000058) Channel 4 control register */ + + struct { + __IO uint32_t CHEN : 1; /*!< [0..0] Channel enable */ + __IO uint32_t FTFIE : 1; /*!< [1..1] Enable bit for channel full transfer finish interrupt */ + __IO uint32_t HTFIE : 1; /*!< [2..2] Enable bit for channel half transfer finish interrupt */ + __IO uint32_t ERRIE : 1; /*!< [3..3] Enable bit for channel error interrupt */ + __IO uint32_t DIR : 1; /*!< [4..4] Transfer direction */ + __IO uint32_t CMEN : 1; /*!< [5..5] Circular mode enable */ + __IO uint32_t PNAGA : 1; /*!< [6..6] Next address generation algorithm of peripheral */ + __IO uint32_t MNAGA : 1; /*!< [7..7] Next address generation algorithm of memory */ + __IO uint32_t PWIDTH : 2; /*!< [9..8] Transfer data size of peripheral */ + __IO uint32_t MWIDTH : 2; /*!< [11..10] Transfer data size of memory */ + __IO uint32_t PRIO : 2; /*!< [13..12] Priority level */ + __IO uint32_t M2M : 1; /*!< [14..14] Memory to Memory Mode */ + uint32_t : 17; + } CH4CTL_b; + } ; + + union { + __IO uint32_t CH4CNT; /*!< (@ 0x0000005C) Channel 4 counter register */ + + struct { + __IO uint32_t CNT : 16; /*!< [15..0] Transfer counter */ + uint32_t : 16; + } CH4CNT_b; + } ; + + union { + __IO uint32_t CH4PADDR; /*!< (@ 0x00000060) Channel 4 peripheral base address register */ + + struct { + __IO uint32_t PADDR : 32; /*!< [31..0] Peripheral base address */ + } CH4PADDR_b; + } ; + + union { + __IO uint32_t CH4MADDR; /*!< (@ 0x00000064) Channel 4 memory base address register */ + + struct { + __IO uint32_t MADDR : 32; /*!< [31..0] Memory base address */ + } CH4MADDR_b; + } ; +} DMA1_Type; /*!< Size = 104 (0x68) */ + + + +/* =========================================================================================================================== */ +/* ================ EXMC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief External memory controller (EXMC) + */ + +typedef struct { /*!< (@ 0xA0000000) EXMC Structure */ + + union { + __IO uint32_t SNCTL0; /*!< (@ 0x00000000) SRAM/NOR flash control register 0 */ + + struct { + __IO uint32_t NRBKEN : 1; /*!< [0..0] NOR bank enable */ + __IO uint32_t NRMUX : 1; /*!< [1..1] NOR bank memory address/data multiplexing */ + __IO uint32_t NRTP : 2; /*!< [3..2] NOR bank memory type */ + __IO uint32_t NRW : 2; /*!< [5..4] NOR bank memory data bus width */ + __IO uint32_t NREN : 1; /*!< [6..6] NOR Flash access enable */ + uint32_t : 2; + __IO uint32_t NRWTPOL : 1; /*!< [9..9] NWAIT signal polarity */ + uint32_t : 2; + __IO uint32_t WREN : 1; /*!< [12..12] Write enable */ + __IO uint32_t NRWTEN : 1; /*!< [13..13] NWAIT signal enable */ + uint32_t : 1; + __IO uint32_t ASYNCWAIT : 1; /*!< [15..15] Asynchronous wait */ + uint32_t : 16; + } SNCTL0_b; + } ; + + union { + __IO uint32_t SNTCFG0; /*!< (@ 0x00000004) SRAM/NOR flash timing configuration register + 0 */ + + struct { + __IO uint32_t ASET : 4; /*!< [3..0] Address setup time */ + __IO uint32_t AHLD : 4; /*!< [7..4] Address hold time */ + __IO uint32_t DSET : 8; /*!< [15..8] Data setup time */ + __IO uint32_t BUSLAT : 4; /*!< [19..16] Bus latency */ + uint32_t : 12; + } SNTCFG0_b; + } ; + + union { + __IO uint32_t SNCTL1; /*!< (@ 0x00000008) SRAM/NOR flash control register 1 */ + + struct { + __IO uint32_t NRBKEN : 1; /*!< [0..0] NOR bank enable */ + __IO uint32_t NRMUX : 1; /*!< [1..1] NOR bank memory address/data multiplexing */ + __IO uint32_t NRTP : 2; /*!< [3..2] NOR bank memory type */ + __IO uint32_t NRW : 2; /*!< [5..4] NOR bank memory data bus width */ + __IO uint32_t NREN : 1; /*!< [6..6] NOR Flash access enable */ + uint32_t : 2; + __IO uint32_t NRWTPOL : 1; /*!< [9..9] NWAIT signal polarity */ + uint32_t : 2; + __IO uint32_t WREN : 1; /*!< [12..12] Write enable */ + __IO uint32_t NRWTEN : 1; /*!< [13..13] NWAIT signal enable */ + uint32_t : 1; + __IO uint32_t ASYNCWAIT : 1; /*!< [15..15] Asynchronous wait */ + uint32_t : 16; + } SNCTL1_b; + } ; +} EXMC_Type; /*!< Size = 12 (0xc) */ + + + +/* =========================================================================================================================== */ +/* ================ EXTI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief External interrupt/event + controller (EXTI) + */ + +typedef struct { /*!< (@ 0x40010400) EXTI Structure */ + + union { + __IO uint32_t INTEN; /*!< (@ 0x00000000) Interrupt enable register (EXTI_INTEN) */ + + struct { + __IO uint32_t INTEN0 : 1; /*!< [0..0] Enable Interrupt on line 0 */ + __IO uint32_t INTEN1 : 1; /*!< [1..1] Enable Interrupt on line 1 */ + __IO uint32_t INTEN2 : 1; /*!< [2..2] Enable Interrupt on line 2 */ + __IO uint32_t INTEN3 : 1; /*!< [3..3] Enable Interrupt on line 3 */ + __IO uint32_t INTEN4 : 1; /*!< [4..4] Enable Interrupt on line 4 */ + __IO uint32_t INTEN5 : 1; /*!< [5..5] Enable Interrupt on line 5 */ + __IO uint32_t INTEN6 : 1; /*!< [6..6] Enable Interrupt on line 6 */ + __IO uint32_t INTEN7 : 1; /*!< [7..7] Enable Interrupt on line 7 */ + __IO uint32_t INTEN8 : 1; /*!< [8..8] Enable Interrupt on line 8 */ + __IO uint32_t INTEN9 : 1; /*!< [9..9] Enable Interrupt on line 9 */ + __IO uint32_t INTEN10 : 1; /*!< [10..10] Enable Interrupt on line 10 */ + __IO uint32_t INTEN11 : 1; /*!< [11..11] Enable Interrupt on line 11 */ + __IO uint32_t INTEN12 : 1; /*!< [12..12] Enable Interrupt on line 12 */ + __IO uint32_t INTEN13 : 1; /*!< [13..13] Enable Interrupt on line 13 */ + __IO uint32_t INTEN14 : 1; /*!< [14..14] Enable Interrupt on line 14 */ + __IO uint32_t INTEN15 : 1; /*!< [15..15] Enable Interrupt on line 15 */ + __IO uint32_t INTEN16 : 1; /*!< [16..16] Enable Interrupt on line 16 */ + __IO uint32_t INTEN17 : 1; /*!< [17..17] Enable Interrupt on line 17 */ + __IO uint32_t INTEN18 : 1; /*!< [18..18] Enable Interrupt on line 18 */ + uint32_t : 13; + } INTEN_b; + } ; + + union { + __IO uint32_t EVEN; /*!< (@ 0x00000004) Event enable register (EXTI_EVEN) */ + + struct { + __IO uint32_t EVEN0 : 1; /*!< [0..0] Enable Event on line 0 */ + __IO uint32_t EVEN1 : 1; /*!< [1..1] Enable Event on line 1 */ + __IO uint32_t EVEN2 : 1; /*!< [2..2] Enable Event on line 2 */ + __IO uint32_t EVEN3 : 1; /*!< [3..3] Enable Event on line 3 */ + __IO uint32_t EVEN4 : 1; /*!< [4..4] Enable Event on line 4 */ + __IO uint32_t EVEN5 : 1; /*!< [5..5] Enable Event on line 5 */ + __IO uint32_t EVEN6 : 1; /*!< [6..6] Enable Event on line 6 */ + __IO uint32_t EVEN7 : 1; /*!< [7..7] Enable Event on line 7 */ + __IO uint32_t EVEN8 : 1; /*!< [8..8] Enable Event on line 8 */ + __IO uint32_t EVEN9 : 1; /*!< [9..9] Enable Event on line 9 */ + __IO uint32_t EVEN10 : 1; /*!< [10..10] Enable Event on line 10 */ + __IO uint32_t EVEN11 : 1; /*!< [11..11] Enable Event on line 11 */ + __IO uint32_t EVEN12 : 1; /*!< [12..12] Enable Event on line 12 */ + __IO uint32_t EVEN13 : 1; /*!< [13..13] Enable Event on line 13 */ + __IO uint32_t EVEN14 : 1; /*!< [14..14] Enable Event on line 14 */ + __IO uint32_t EVEN15 : 1; /*!< [15..15] Enable Event on line 15 */ + __IO uint32_t EVEN16 : 1; /*!< [16..16] Enable Event on line 16 */ + __IO uint32_t EVEN17 : 1; /*!< [17..17] Enable Event on line 17 */ + __IO uint32_t EVEN18 : 1; /*!< [18..18] Enable Event on line 18 */ + uint32_t : 13; + } EVEN_b; + } ; + + union { + __IO uint32_t RTEN; /*!< (@ 0x00000008) Rising Edge Trigger Enable register (EXTI_RTEN) */ + + struct { + __IO uint32_t RTEN0 : 1; /*!< [0..0] Rising edge trigger enable of line 0 */ + __IO uint32_t RTEN1 : 1; /*!< [1..1] Rising edge trigger enable of line 1 */ + __IO uint32_t RTEN2 : 1; /*!< [2..2] Rising edge trigger enable of line 2 */ + __IO uint32_t RTEN3 : 1; /*!< [3..3] Rising edge trigger enable of line 3 */ + __IO uint32_t RTEN4 : 1; /*!< [4..4] Rising edge trigger enable of line 4 */ + __IO uint32_t RTEN5 : 1; /*!< [5..5] Rising edge trigger enable of line 5 */ + __IO uint32_t RTEN6 : 1; /*!< [6..6] Rising edge trigger enable of line 6 */ + __IO uint32_t RTEN7 : 1; /*!< [7..7] Rising edge trigger enable of line 7 */ + __IO uint32_t RTEN8 : 1; /*!< [8..8] Rising edge trigger enable of line 8 */ + __IO uint32_t RTEN9 : 1; /*!< [9..9] Rising edge trigger enable of line 9 */ + __IO uint32_t RTEN10 : 1; /*!< [10..10] Rising edge trigger enable of line 10 */ + __IO uint32_t RTEN11 : 1; /*!< [11..11] Rising edge trigger enable of line 11 */ + __IO uint32_t RTEN12 : 1; /*!< [12..12] Rising edge trigger enable of line 12 */ + __IO uint32_t RTEN13 : 1; /*!< [13..13] Rising edge trigger enable of line 13 */ + __IO uint32_t RTEN14 : 1; /*!< [14..14] Rising edge trigger enable of line 14 */ + __IO uint32_t RTEN15 : 1; /*!< [15..15] Rising edge trigger enable of line 15 */ + __IO uint32_t RTEN16 : 1; /*!< [16..16] Rising edge trigger enable of line 16 */ + __IO uint32_t RTEN17 : 1; /*!< [17..17] Rising edge trigger enable of line 17 */ + __IO uint32_t RTEN18 : 1; /*!< [18..18] Rising edge trigger enable of line 18 */ + uint32_t : 13; + } RTEN_b; + } ; + + union { + __IO uint32_t FTEN; /*!< (@ 0x0000000C) Falling Egde Trigger Enable register (EXTI_FTEN) */ + + struct { + __IO uint32_t FTEN0 : 1; /*!< [0..0] Falling edge trigger enable of line 0 */ + __IO uint32_t FTEN1 : 1; /*!< [1..1] Falling edge trigger enable of line 1 */ + __IO uint32_t FTEN2 : 1; /*!< [2..2] Falling edge trigger enable of line 2 */ + __IO uint32_t FTEN3 : 1; /*!< [3..3] Falling edge trigger enable of line 3 */ + __IO uint32_t FTEN4 : 1; /*!< [4..4] Falling edge trigger enable of line 4 */ + __IO uint32_t FTEN5 : 1; /*!< [5..5] Falling edge trigger enable of line 5 */ + __IO uint32_t FTEN6 : 1; /*!< [6..6] Falling edge trigger enable of line 6 */ + __IO uint32_t FTEN7 : 1; /*!< [7..7] Falling edge trigger enable of line 7 */ + __IO uint32_t FTEN8 : 1; /*!< [8..8] Falling edge trigger enable of line 8 */ + __IO uint32_t FTEN9 : 1; /*!< [9..9] Falling edge trigger enable of line 9 */ + __IO uint32_t FTEN10 : 1; /*!< [10..10] Falling edge trigger enable of line 10 */ + __IO uint32_t FTEN11 : 1; /*!< [11..11] Falling edge trigger enable of line 11 */ + __IO uint32_t FTEN12 : 1; /*!< [12..12] Falling edge trigger enable of line 12 */ + __IO uint32_t FTEN13 : 1; /*!< [13..13] Falling edge trigger enable of line 13 */ + __IO uint32_t FTEN14 : 1; /*!< [14..14] Falling edge trigger enable of line 14 */ + __IO uint32_t FTEN15 : 1; /*!< [15..15] Falling edge trigger enable of line 15 */ + __IO uint32_t FTEN16 : 1; /*!< [16..16] Falling edge trigger enable of line 16 */ + __IO uint32_t FTEN17 : 1; /*!< [17..17] Falling edge trigger enable of line 17 */ + __IO uint32_t FTEN18 : 1; /*!< [18..18] Falling edge trigger enable of line 18 */ + uint32_t : 13; + } FTEN_b; + } ; + + union { + __IO uint32_t SWIEV; /*!< (@ 0x00000010) Software interrupt event register (EXTI_SWIEV) */ + + struct { + __IO uint32_t SWIEV0 : 1; /*!< [0..0] Interrupt/Event software trigger on line 0 */ + __IO uint32_t SWIEV1 : 1; /*!< [1..1] Interrupt/Event software trigger on line 1 */ + __IO uint32_t SWIEV2 : 1; /*!< [2..2] Interrupt/Event software trigger on line 2 */ + __IO uint32_t SWIEV3 : 1; /*!< [3..3] Interrupt/Event software trigger on line 3 */ + __IO uint32_t SWIEV4 : 1; /*!< [4..4] Interrupt/Event software trigger on line 4 */ + __IO uint32_t SWIEV5 : 1; /*!< [5..5] Interrupt/Event software trigger on line 5 */ + __IO uint32_t SWIEV6 : 1; /*!< [6..6] Interrupt/Event software trigger on line 6 */ + __IO uint32_t SWIEV7 : 1; /*!< [7..7] Interrupt/Event software trigger on line 7 */ + __IO uint32_t SWIEV8 : 1; /*!< [8..8] Interrupt/Event software trigger on line 8 */ + __IO uint32_t SWIEV9 : 1; /*!< [9..9] Interrupt/Event software trigger on line 9 */ + __IO uint32_t SWIEV10 : 1; /*!< [10..10] Interrupt/Event software trigger on line 10 */ + __IO uint32_t SWIEV11 : 1; /*!< [11..11] Interrupt/Event software trigger on line 11 */ + __IO uint32_t SWIEV12 : 1; /*!< [12..12] Interrupt/Event software trigger on line 12 */ + __IO uint32_t SWIEV13 : 1; /*!< [13..13] Interrupt/Event software trigger on line 13 */ + __IO uint32_t SWIEV14 : 1; /*!< [14..14] Interrupt/Event software trigger on line 14 */ + __IO uint32_t SWIEV15 : 1; /*!< [15..15] Interrupt/Event software trigger on line 15 */ + __IO uint32_t SWIEV16 : 1; /*!< [16..16] Interrupt/Event software trigger on line 16 */ + __IO uint32_t SWIEV17 : 1; /*!< [17..17] Interrupt/Event software trigger on line 17 */ + __IO uint32_t SWIEV18 : 1; /*!< [18..18] Interrupt/Event software trigger on line 18 */ + uint32_t : 13; + } SWIEV_b; + } ; + + union { + __IO uint32_t PD; /*!< (@ 0x00000014) Pending register (EXTI_PD) */ + + struct { + __IO uint32_t PD0 : 1; /*!< [0..0] Interrupt pending status of line 0 */ + __IO uint32_t PD1 : 1; /*!< [1..1] Interrupt pending status of line 1 */ + __IO uint32_t PD2 : 1; /*!< [2..2] Interrupt pending status of line 2 */ + __IO uint32_t PD3 : 1; /*!< [3..3] Interrupt pending status of line 3 */ + __IO uint32_t PD4 : 1; /*!< [4..4] Interrupt pending status of line 4 */ + __IO uint32_t PD5 : 1; /*!< [5..5] Interrupt pending status of line 5 */ + __IO uint32_t PD6 : 1; /*!< [6..6] Interrupt pending status of line 6 */ + __IO uint32_t PD7 : 1; /*!< [7..7] Interrupt pending status of line 7 */ + __IO uint32_t PD8 : 1; /*!< [8..8] Interrupt pending status of line 8 */ + __IO uint32_t PD9 : 1; /*!< [9..9] Interrupt pending status of line 9 */ + __IO uint32_t PD10 : 1; /*!< [10..10] Interrupt pending status of line 10 */ + __IO uint32_t PD11 : 1; /*!< [11..11] Interrupt pending status of line 11 */ + __IO uint32_t PD12 : 1; /*!< [12..12] Interrupt pending status of line 12 */ + __IO uint32_t PD13 : 1; /*!< [13..13] Interrupt pending status of line 13 */ + __IO uint32_t PD14 : 1; /*!< [14..14] Interrupt pending status of line 14 */ + __IO uint32_t PD15 : 1; /*!< [15..15] Interrupt pending status of line 15 */ + __IO uint32_t PD16 : 1; /*!< [16..16] Interrupt pending status of line 16 */ + __IO uint32_t PD17 : 1; /*!< [17..17] Interrupt pending status of line 17 */ + __IO uint32_t PD18 : 1; /*!< [18..18] Interrupt pending status of line 18 */ + uint32_t : 13; + } PD_b; + } ; +} EXTI_Type; /*!< Size = 24 (0x18) */ + + + +/* =========================================================================================================================== */ +/* ================ FMC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief FMC (FMC) + */ + +typedef struct { /*!< (@ 0x40022000) FMC Structure */ + + union { + __IO uint32_t WS; /*!< (@ 0x00000000) wait state counter register */ + + struct { + __IO uint32_t WSCNT : 3; /*!< [2..0] wait state counter register */ + uint32_t : 29; + } WS_b; + } ; + + union { + __O uint32_t KEY0; /*!< (@ 0x00000004) Unlock key register 0 */ + + struct { + __O uint32_t KEY : 32; /*!< [31..0] FMC_CTL0 unlock key */ + } KEY0_b; + } ; + + union { + __O uint32_t OBKEY; /*!< (@ 0x00000008) Option byte unlock key register */ + + struct { + __O uint32_t OBKEY : 32; /*!< [31..0] FMC_ CTL0 option byte operation unlock register */ + } OBKEY_b; + } ; + + union { + __IO uint32_t STAT0; /*!< (@ 0x0000000C) Status register 0 */ + + struct { + __I uint32_t BUSY : 1; /*!< [0..0] The flash is busy bit */ + uint32_t : 1; + __IO uint32_t PGERR : 1; /*!< [2..2] Program error flag bit */ + uint32_t : 1; + __IO uint32_t WPERR : 1; /*!< [4..4] Erase/Program protection error flag bit */ + __IO uint32_t ENDF : 1; /*!< [5..5] End of operation flag bit */ + uint32_t : 26; + } STAT0_b; + } ; + + union { + __IO uint32_t CTL0; /*!< (@ 0x00000010) Control register 0 */ + + struct { + __IO uint32_t PG : 1; /*!< [0..0] Main flash program for bank0 command bit */ + __IO uint32_t PER : 1; /*!< [1..1] Main flash page erase for bank0 command bit */ + __IO uint32_t MER : 1; /*!< [2..2] Main flash mass erase for bank0 command bit */ + uint32_t : 1; + __IO uint32_t OBPG : 1; /*!< [4..4] Option bytes program command bit */ + __IO uint32_t OBER : 1; /*!< [5..5] Option bytes erase command bit */ + __IO uint32_t START : 1; /*!< [6..6] Send erase command to FMC bit */ + __IO uint32_t LK : 1; /*!< [7..7] FMC_CTL0 lock bit */ + uint32_t : 1; + __IO uint32_t OBWEN : 1; /*!< [9..9] Option byte erase/program enable bit */ + __IO uint32_t ERRIE : 1; /*!< [10..10] Error interrupt enable bit */ + uint32_t : 1; + __IO uint32_t ENDIE : 1; /*!< [12..12] End of operation interrupt enable bit */ + uint32_t : 19; + } CTL0_b; + } ; + + union { + __O uint32_t ADDR0; /*!< (@ 0x00000014) Address register 0 */ + + struct { + __O uint32_t ADDR : 32; /*!< [31..0] Flash erase/program command address bits */ + } ADDR0_b; + } ; + __I uint32_t RESERVED; + + union { + __I uint32_t OBSTAT; /*!< (@ 0x0000001C) Option byte status register */ + + struct { + __I uint32_t OBERR : 1; /*!< [0..0] Option bytes read error bit */ + __I uint32_t SPC : 1; /*!< [1..1] Option bytes security protection code */ + __I uint32_t USER : 8; /*!< [9..2] Store USER of option bytes block after system reset */ + __I uint32_t DATA : 16; /*!< [25..10] Store DATA[15:0] of option bytes block after system + reset */ + uint32_t : 6; + } OBSTAT_b; + } ; + + union { + __I uint32_t WP; /*!< (@ 0x00000020) Erase/Program Protection register */ + + struct { + __I uint32_t WP : 32; /*!< [31..0] Store WP[31:0] of option bytes block after system reset */ + } WP_b; + } ; + __I uint32_t RESERVED1[55]; + + union { + __I uint32_t PID; /*!< (@ 0x00000100) Product ID register */ + + struct { + __I uint32_t PID : 32; /*!< [31..0] Product reserved ID code register */ + } PID_b; + } ; +} FMC_Type; /*!< Size = 260 (0x104) */ + + + +/* =========================================================================================================================== */ +/* ================ FWDGT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief free watchdog timer (FWDGT) + */ + +typedef struct { /*!< (@ 0x40003000) FWDGT Structure */ + + union { + __O uint32_t CTL; /*!< (@ 0x00000000) Control register */ + + struct { + __O uint32_t CMD : 16; /*!< [15..0] Key value */ + uint32_t : 16; + } CTL_b; + } ; + + union { + __IO uint32_t PSC; /*!< (@ 0x00000004) Prescaler register */ + + struct { + __IO uint32_t PSC : 3; /*!< [2..0] Free watchdog timer prescaler selection */ + uint32_t : 29; + } PSC_b; + } ; + + union { + __IO uint32_t RLD; /*!< (@ 0x00000008) Reload register */ + + struct { + __IO uint32_t RLD : 12; /*!< [11..0] Free watchdog timer counter reload value */ + uint32_t : 20; + } RLD_b; + } ; + + union { + __I uint32_t STAT; /*!< (@ 0x0000000C) Status register */ + + struct { + __I uint32_t PUD : 1; /*!< [0..0] Free watchdog timer prescaler value update */ + __I uint32_t RUD : 1; /*!< [1..1] Free watchdog timer counter reload value update */ + uint32_t : 30; + } STAT_b; + } ; +} FWDGT_Type; /*!< Size = 16 (0x10) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief General-purpose I/Os (GPIO) + */ + +typedef struct { /*!< (@ 0x40010800) GPIO Structure */ + + union { + __IO uint32_t CTL0; /*!< (@ 0x00000000) port control register 0 */ + + struct { + __IO uint32_t MD0 : 2; /*!< [1..0] Port x mode bits (x = 0) */ + __IO uint32_t CTL0 : 2; /*!< [3..2] Port x configuration bits (x = 0) */ + __IO uint32_t MD1 : 2; /*!< [5..4] Port x mode bits (x = 1) */ + __IO uint32_t CTL1 : 2; /*!< [7..6] Port x configuration bits (x = 1) */ + __IO uint32_t MD2 : 2; /*!< [9..8] Port x mode bits (x = 2 ) */ + __IO uint32_t CTL2 : 2; /*!< [11..10] Port x configuration bits (x = 2) */ + __IO uint32_t MD3 : 2; /*!< [13..12] Port x mode bits (x = 3 ) */ + __IO uint32_t CTL3 : 2; /*!< [15..14] Port x configuration bits (x = 3) */ + __IO uint32_t MD4 : 2; /*!< [17..16] Port x mode bits (x = 4) */ + __IO uint32_t CTL4 : 2; /*!< [19..18] Port x configuration bits (x = 4) */ + __IO uint32_t MD5 : 2; /*!< [21..20] Port x mode bits (x = 5) */ + __IO uint32_t CTL5 : 2; /*!< [23..22] Port x configuration bits (x = 5) */ + __IO uint32_t MD6 : 2; /*!< [25..24] Port x mode bits (x = 6) */ + __IO uint32_t CTL6 : 2; /*!< [27..26] Port x configuration bits (x = 6) */ + __IO uint32_t MD7 : 2; /*!< [29..28] Port x mode bits (x = 7) */ + __IO uint32_t CTL7 : 2; /*!< [31..30] Port x configuration bits (x = 7) */ + } CTL0_b; + } ; + + union { + __IO uint32_t CTL1; /*!< (@ 0x00000004) port control register 1 */ + + struct { + __IO uint32_t MD8 : 2; /*!< [1..0] Port x mode bits (x = 8) */ + __IO uint32_t CTL8 : 2; /*!< [3..2] Port x configuration bits (x = 8) */ + __IO uint32_t MD9 : 2; /*!< [5..4] Port x mode bits (x = 9) */ + __IO uint32_t CTL9 : 2; /*!< [7..6] Port x configuration bits (x = 9) */ + __IO uint32_t MD10 : 2; /*!< [9..8] Port x mode bits (x = 10 ) */ + __IO uint32_t CTL10 : 2; /*!< [11..10] Port x configuration bits (x = 10) */ + __IO uint32_t MD11 : 2; /*!< [13..12] Port x mode bits (x = 11 ) */ + __IO uint32_t CTL11 : 2; /*!< [15..14] Port x configuration bits (x = 11) */ + __IO uint32_t MD12 : 2; /*!< [17..16] Port x mode bits (x = 12) */ + __IO uint32_t CTL12 : 2; /*!< [19..18] Port x configuration bits (x = 12) */ + __IO uint32_t MD13 : 2; /*!< [21..20] Port x mode bits (x = 13) */ + __IO uint32_t CTL13 : 2; /*!< [23..22] Port x configuration bits (x = 13) */ + __IO uint32_t MD14 : 2; /*!< [25..24] Port x mode bits (x = 14) */ + __IO uint32_t CTL14 : 2; /*!< [27..26] Port x configuration bits (x = 14) */ + __IO uint32_t MD15 : 2; /*!< [29..28] Port x mode bits (x = 15) */ + __IO uint32_t CTL15 : 2; /*!< [31..30] Port x configuration bits (x = 15) */ + } CTL1_b; + } ; + + union { + __I uint32_t ISTAT; /*!< (@ 0x00000008) Port input status register */ + + struct { + __I uint32_t ISTAT0 : 1; /*!< [0..0] Port input status */ + __I uint32_t ISTAT1 : 1; /*!< [1..1] Port input status */ + __I uint32_t ISTAT2 : 1; /*!< [2..2] Port input status */ + __I uint32_t ISTAT3 : 1; /*!< [3..3] Port input status */ + __I uint32_t ISTAT4 : 1; /*!< [4..4] Port input status */ + __I uint32_t ISTAT5 : 1; /*!< [5..5] Port input status */ + __I uint32_t ISTAT6 : 1; /*!< [6..6] Port input status */ + __I uint32_t ISTAT7 : 1; /*!< [7..7] Port input status */ + __I uint32_t ISTAT8 : 1; /*!< [8..8] Port input status */ + __I uint32_t ISTAT9 : 1; /*!< [9..9] Port input status */ + __I uint32_t ISTAT10 : 1; /*!< [10..10] Port input status */ + __I uint32_t ISTAT11 : 1; /*!< [11..11] Port input status */ + __I uint32_t ISTAT12 : 1; /*!< [12..12] Port input status */ + __I uint32_t ISTAT13 : 1; /*!< [13..13] Port input status */ + __I uint32_t ISTAT14 : 1; /*!< [14..14] Port input status */ + __I uint32_t ISTAT15 : 1; /*!< [15..15] Port input status */ + uint32_t : 16; + } ISTAT_b; + } ; + + union { + __IO uint32_t OCTL; /*!< (@ 0x0000000C) Port output control register */ + + struct { + __IO uint32_t OCTL0 : 1; /*!< [0..0] Port output control */ + __IO uint32_t OCTL1 : 1; /*!< [1..1] Port output control */ + __IO uint32_t OCTL2 : 1; /*!< [2..2] Port output control */ + __IO uint32_t OCTL3 : 1; /*!< [3..3] Port output control */ + __IO uint32_t OCTL4 : 1; /*!< [4..4] Port output control */ + __IO uint32_t OCTL5 : 1; /*!< [5..5] Port output control */ + __IO uint32_t OCTL6 : 1; /*!< [6..6] Port output control */ + __IO uint32_t OCTL7 : 1; /*!< [7..7] Port output control */ + __IO uint32_t OCTL8 : 1; /*!< [8..8] Port output control */ + __IO uint32_t OCTL9 : 1; /*!< [9..9] Port output control */ + __IO uint32_t OCTL10 : 1; /*!< [10..10] Port output control */ + __IO uint32_t OCTL11 : 1; /*!< [11..11] Port output control */ + __IO uint32_t OCTL12 : 1; /*!< [12..12] Port output control */ + __IO uint32_t OCTL13 : 1; /*!< [13..13] Port output control */ + __IO uint32_t OCTL14 : 1; /*!< [14..14] Port output control */ + __IO uint32_t OCTL15 : 1; /*!< [15..15] Port output control */ + uint32_t : 16; + } OCTL_b; + } ; + + union { + __O uint32_t BOP; /*!< (@ 0x00000010) Port bit operate register */ + + struct { + __O uint32_t BOP0 : 1; /*!< [0..0] Port 0 Set bit */ + __O uint32_t BOP1 : 1; /*!< [1..1] Port 1 Set bit */ + __O uint32_t BOP2 : 1; /*!< [2..2] Port 2 Set bit */ + __O uint32_t BOP3 : 1; /*!< [3..3] Port 3 Set bit */ + __O uint32_t BOP4 : 1; /*!< [4..4] Port 4 Set bit */ + __O uint32_t BOP5 : 1; /*!< [5..5] Port 5 Set bit */ + __O uint32_t BOP6 : 1; /*!< [6..6] Port 6 Set bit */ + __O uint32_t BOP7 : 1; /*!< [7..7] Port 7 Set bit */ + __O uint32_t BOP8 : 1; /*!< [8..8] Port 8 Set bit */ + __O uint32_t BOP9 : 1; /*!< [9..9] Port 9 Set bit */ + __O uint32_t BOP10 : 1; /*!< [10..10] Port 10 Set bit */ + __O uint32_t BOP11 : 1; /*!< [11..11] Port 11 Set bit */ + __O uint32_t BOP12 : 1; /*!< [12..12] Port 12 Set bit */ + __O uint32_t BOP13 : 1; /*!< [13..13] Port 13 Set bit */ + __O uint32_t BOP14 : 1; /*!< [14..14] Port 14 Set bit */ + __O uint32_t BOP15 : 1; /*!< [15..15] Port 15 Set bit */ + __O uint32_t CR0 : 1; /*!< [16..16] Port 0 Clear bit */ + __O uint32_t CR1 : 1; /*!< [17..17] Port 1 Clear bit */ + __O uint32_t CR2 : 1; /*!< [18..18] Port 2 Clear bit */ + __O uint32_t CR3 : 1; /*!< [19..19] Port 3 Clear bit */ + __O uint32_t CR4 : 1; /*!< [20..20] Port 4 Clear bit */ + __O uint32_t CR5 : 1; /*!< [21..21] Port 5 Clear bit */ + __O uint32_t CR6 : 1; /*!< [22..22] Port 6 Clear bit */ + __O uint32_t CR7 : 1; /*!< [23..23] Port 7 Clear bit */ + __O uint32_t CR8 : 1; /*!< [24..24] Port 8 Clear bit */ + __O uint32_t CR9 : 1; /*!< [25..25] Port 9 Clear bit */ + __O uint32_t CR10 : 1; /*!< [26..26] Port 10 Clear bit */ + __O uint32_t CR11 : 1; /*!< [27..27] Port 11 Clear bit */ + __O uint32_t CR12 : 1; /*!< [28..28] Port 12 Clear bit */ + __O uint32_t CR13 : 1; /*!< [29..29] Port 13 Clear bit */ + __O uint32_t CR14 : 1; /*!< [30..30] Port 14 Clear bit */ + __O uint32_t CR15 : 1; /*!< [31..31] Port 15 Clear bit */ + } BOP_b; + } ; + + union { + __O uint32_t BC; /*!< (@ 0x00000014) Port bit clear register */ + + struct { + __O uint32_t CR0 : 1; /*!< [0..0] Port 0 Clear bit */ + __O uint32_t CR1 : 1; /*!< [1..1] Port 1 Clear bit */ + __O uint32_t CR2 : 1; /*!< [2..2] Port 2 Clear bit */ + __O uint32_t CR3 : 1; /*!< [3..3] Port 3 Clear bit */ + __O uint32_t CR4 : 1; /*!< [4..4] Port 4 Clear bit */ + __O uint32_t CR5 : 1; /*!< [5..5] Port 5 Clear bit */ + __O uint32_t CR6 : 1; /*!< [6..6] Port 6 Clear bit */ + __O uint32_t CR7 : 1; /*!< [7..7] Port 7 Clear bit */ + __O uint32_t CR8 : 1; /*!< [8..8] Port 8 Clear bit */ + __O uint32_t CR9 : 1; /*!< [9..9] Port 9 Clear bit */ + __O uint32_t CR10 : 1; /*!< [10..10] Port 10 Clear bit */ + __O uint32_t CR11 : 1; /*!< [11..11] Port 11 Clear bit */ + __O uint32_t CR12 : 1; /*!< [12..12] Port 12 Clear bit */ + __O uint32_t CR13 : 1; /*!< [13..13] Port 13 Clear bit */ + __O uint32_t CR14 : 1; /*!< [14..14] Port 14 Clear bit */ + __O uint32_t CR15 : 1; /*!< [15..15] Port 15 Clear bit */ + uint32_t : 16; + } BC_b; + } ; + + union { + __IO uint32_t LOCK; /*!< (@ 0x00000018) GPIO port configuration lock register */ + + struct { + __IO uint32_t LK0 : 1; /*!< [0..0] Port Lock bit 0 */ + __IO uint32_t LK1 : 1; /*!< [1..1] Port Lock bit 1 */ + __IO uint32_t LK2 : 1; /*!< [2..2] Port Lock bit 2 */ + __IO uint32_t LK3 : 1; /*!< [3..3] Port Lock bit 3 */ + __IO uint32_t LK4 : 1; /*!< [4..4] Port Lock bit 4 */ + __IO uint32_t LK5 : 1; /*!< [5..5] Port Lock bit 5 */ + __IO uint32_t LK6 : 1; /*!< [6..6] Port Lock bit 6 */ + __IO uint32_t LK7 : 1; /*!< [7..7] Port Lock bit 7 */ + __IO uint32_t LK8 : 1; /*!< [8..8] Port Lock bit 8 */ + __IO uint32_t LK9 : 1; /*!< [9..9] Port Lock bit 9 */ + __IO uint32_t LK10 : 1; /*!< [10..10] Port Lock bit 10 */ + __IO uint32_t LK11 : 1; /*!< [11..11] Port Lock bit 11 */ + __IO uint32_t LK12 : 1; /*!< [12..12] Port Lock bit 12 */ + __IO uint32_t LK13 : 1; /*!< [13..13] Port Lock bit 13 */ + __IO uint32_t LK14 : 1; /*!< [14..14] Port Lock bit 14 */ + __IO uint32_t LK15 : 1; /*!< [15..15] Port Lock bit 15 */ + __IO uint32_t LKK : 1; /*!< [16..16] Lock sequence key */ + uint32_t : 15; + } LOCK_b; + } ; +} GPIO_Type; /*!< Size = 28 (0x1c) */ + + + +/* =========================================================================================================================== */ +/* ================ I2C0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Inter integrated circuit (I2C0) + */ + +typedef struct { /*!< (@ 0x40005400) I2C0 Structure */ + + union { + __IO uint16_t CTL0; /*!< (@ 0x00000000) Control register 0 */ + + struct { + __IO uint16_t I2CEN : 1; /*!< [0..0] I2C peripheral enable */ + __IO uint16_t SMBEN : 1; /*!< [1..1] SMBus/I2C mode switch */ + uint16_t : 1; + __IO uint16_t SMBSEL : 1; /*!< [3..3] SMBusType Selection */ + __IO uint16_t ARPEN : 1; /*!< [4..4] ARP protocol in SMBus switch */ + __IO uint16_t PECEN : 1; /*!< [5..5] PEC Calculation Switch */ + __IO uint16_t GCEN : 1; /*!< [6..6] Whether or not to response to a General Call (0x00) */ + __IO uint16_t SS : 1; /*!< [7..7] Whether to stretch SCL low when data is not ready in + slave mode */ + __IO uint16_t START : 1; /*!< [8..8] Generate a START condition on I2C bus */ + __IO uint16_t STOP : 1; /*!< [9..9] Generate a STOP condition on I2C bus */ + __IO uint16_t ACKEN : 1; /*!< [10..10] Whether or not to send an ACK */ + __IO uint16_t POAP : 1; /*!< [11..11] Position of ACK and PEC when receiving */ + __IO uint16_t PECTRANS : 1; /*!< [12..12] PEC Transfer */ + __IO uint16_t SALT : 1; /*!< [13..13] SMBus alert */ + uint16_t : 1; + __IO uint16_t SRESET : 1; /*!< [15..15] Software reset */ + } CTL0_b; + } ; + __I uint16_t RESERVED; + + union { + __IO uint16_t CTL1; /*!< (@ 0x00000004) Control register 1 */ + + struct { + __IO uint16_t I2CCLK : 6; /*!< [5..0] I2C Peripheral clock frequency */ + uint16_t : 2; + __IO uint16_t ERRIE : 1; /*!< [8..8] Error interrupt enable */ + __IO uint16_t EVIE : 1; /*!< [9..9] Event interrupt enable */ + __IO uint16_t BUFIE : 1; /*!< [10..10] Buffer interrupt enable */ + __IO uint16_t DMAON : 1; /*!< [11..11] DMA mode switch */ + __IO uint16_t DMALST : 1; /*!< [12..12] Flag indicating DMA last transfer */ + uint16_t : 3; + } CTL1_b; + } ; + __I uint16_t RESERVED1; + + union { + __IO uint16_t SADDR0; /*!< (@ 0x00000008) Slave address register 0 */ + + struct { + __IO uint16_t ADDRESS0 : 1; /*!< [0..0] Bit 0 of a 10-bit address */ + __IO uint16_t ADDRESS7_1 : 7; /*!< [7..1] 7-bit address or bits 7:1 of a 10-bit address */ + __IO uint16_t ADDRESS9_8 : 2; /*!< [9..8] Highest two bits of a 10-bit address */ + uint16_t : 5; + __IO uint16_t ADDFORMAT : 1; /*!< [15..15] Address mode for the I2C slave */ + } SADDR0_b; + } ; + __I uint16_t RESERVED2; + + union { + __IO uint16_t SADDR1; /*!< (@ 0x0000000C) Slave address register 1 */ + + struct { + __IO uint16_t DUADEN : 1; /*!< [0..0] Dual-Address mode switch */ + __IO uint16_t ADDRESS2 : 7; /*!< [7..1] Second I2C address for the slave in Dual-Address mode */ + uint16_t : 8; + } SADDR1_b; + } ; + __I uint16_t RESERVED3; + + union { + __IO uint16_t DATA; /*!< (@ 0x00000010) Transfer buffer register */ + + struct { + __IO uint16_t TRB : 8; /*!< [7..0] Transmission or reception data buffer register */ + uint16_t : 8; + } DATA_b; + } ; + __I uint16_t RESERVED4; + + union { + __IO uint16_t STAT0; /*!< (@ 0x00000014) Transfer status register 0 */ + + struct { + __I uint16_t SBSEND : 1; /*!< [0..0] START condition sent out in master mode */ + __I uint16_t ADDSEND : 1; /*!< [1..1] Address is sent in master mode or received and matches + in slave mode */ + __I uint16_t BTC : 1; /*!< [2..2] Byte transmission completed */ + __I uint16_t ADD10SEND : 1; /*!< [3..3] Header of 10-bit address is sent in master mode */ + __I uint16_t STPDET : 1; /*!< [4..4] STOP condition detected in slave mode */ + uint16_t : 1; + __I uint16_t RBNE : 1; /*!< [6..6] I2C_DATA is not Empty during receiving */ + __I uint16_t TBE : 1; /*!< [7..7] I2C_DATA is Empty during transmitting */ + __IO uint16_t BERR : 1; /*!< [8..8] A bus error occurs indication a unexpected START or STOP + condition on I2C bus */ + __IO uint16_t LOSTARB : 1; /*!< [9..9] Arbitration Lost in master mode */ + __IO uint16_t AERR : 1; /*!< [10..10] Acknowledge error */ + __IO uint16_t OUERR : 1; /*!< [11..11] Over-run or under-run situation occurs in slave mode */ + __IO uint16_t PECERR : 1; /*!< [12..12] PEC error when receiving data */ + uint16_t : 1; + __IO uint16_t SMBTO : 1; /*!< [14..14] Timeout signal in SMBus mode */ + __IO uint16_t SMBALT : 1; /*!< [15..15] SMBus Alert status */ + } STAT0_b; + } ; + __I uint16_t RESERVED5; + + union { + __I uint16_t STAT1; /*!< (@ 0x00000018) Transfer status register 1 */ + + struct { + __I uint16_t MASTER : 1; /*!< [0..0] A flag indicating whether I2C block is in master or slave + mode */ + __I uint16_t I2CBSY : 1; /*!< [1..1] Busy flag */ + __I uint16_t TR : 1; /*!< [2..2] Whether the I2C is a transmitter or a receiver */ + uint16_t : 1; + __I uint16_t RXGC : 1; /*!< [4..4] General call address (00h) received */ + __I uint16_t DEFSMB : 1; /*!< [5..5] Default address of SMBusDevice */ + __I uint16_t HSTSMB : 1; /*!< [6..6] SMBus Host Header detected in slave mode */ + __I uint16_t DUMODF : 1; /*!< [7..7] Dual Flag in slave mode */ + __I uint16_t PECV : 8; /*!< [15..8] Packet Error Checking Value that calculated by hardware + when PEC is enabled */ + } STAT1_b; + } ; + __I uint16_t RESERVED6; + + union { + __IO uint16_t CKCFG; /*!< (@ 0x0000001C) Clock configure register */ + + struct { + __IO uint16_t CLKC : 12; /*!< [11..0] I2C Clock control in master mode */ + uint16_t : 2; + __IO uint16_t DTCY : 1; /*!< [14..14] Duty cycle in fast mode */ + __IO uint16_t FAST : 1; /*!< [15..15] I2C speed selection in master mode */ + } CKCFG_b; + } ; + __I uint16_t RESERVED7; + + union { + __IO uint16_t RT; /*!< (@ 0x00000020) Rise time register */ + + struct { + __IO uint16_t RISETIME : 6; /*!< [5..0] Maximum rise time in master mode */ + uint16_t : 10; + } RT_b; + } ; +} I2C_Type; /*!< Size = 34 (0x22) */ + + + +/* =========================================================================================================================== */ +/* ================ ECLIC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Enhanced Core Local Interrupt Controller (ECLIC) + */ + +typedef struct { /*!< (@ 0xD2000000) ECLIC Structure */ + + union { + __IO uint8_t CLICCFG; /*!< (@ 0x00000000) cliccfg Register */ + + struct { + uint8_t : 1; + __IO uint8_t NLBITS : 4; /*!< [4..1] NLBITS */ + uint8_t : 3; + } CLICCFG_b; + } ; + __I uint8_t RESERVED; + __I uint16_t RESERVED1; + + union { + __I uint32_t CLICINFO; /*!< (@ 0x00000004) clicinfo Register */ + + struct { + __I uint32_t NUM_INTERRUPT : 13; /*!< [12..0] NUM_INTERRUPT */ + __I uint32_t VERSION : 8; /*!< [20..13] VERSION */ + __I uint32_t CLICINTCTLBITS : 4; /*!< [24..21] CLICINTCTLBITS */ + uint32_t : 7; + } CLICINFO_b; + } ; + __I uint16_t RESERVED2; + __I uint8_t RESERVED3; + + union { + __IO uint8_t MTH; /*!< (@ 0x0000000B) MTH Register */ + + struct { + __IO uint8_t MTH : 8; /*!< [7..0] MTH */ + } MTH_b; + } ; + __I uint32_t RESERVED4[1021]; + + union { + __IO uint8_t CLICINTIP_0; /*!< (@ 0x00001000) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_0_b; + } ; + + union { + __IO uint8_t CLICINTIE_0; /*!< (@ 0x00001001) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_0_b; + } ; + + union { + __IO uint8_t CLICINTATTR_0; /*!< (@ 0x00001002) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_0_b; + } ; + + union { + __IO uint8_t CLICINTCTL_0; /*!< (@ 0x00001003) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_0_b; + } ; + + union { + __IO uint8_t CLICINTIP_1; /*!< (@ 0x00001004) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_1_b; + } ; + + union { + __IO uint8_t CLICINTIE_1; /*!< (@ 0x00001005) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_1_b; + } ; + + union { + __IO uint8_t CLICINTATTR_1; /*!< (@ 0x00001006) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_1_b; + } ; + + union { + __IO uint8_t CLICINTCTL_1; /*!< (@ 0x00001007) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_1_b; + } ; + + union { + __IO uint8_t CLICINTIP_2; /*!< (@ 0x00001008) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_2_b; + } ; + + union { + __IO uint8_t CLICINTIE_2; /*!< (@ 0x00001009) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_2_b; + } ; + + union { + __IO uint8_t CLICINTATTR_2; /*!< (@ 0x0000100A) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_2_b; + } ; + + union { + __IO uint8_t CLICINTCTL_2; /*!< (@ 0x0000100B) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_2_b; + } ; + + union { + __IO uint8_t CLICINTIP_3; /*!< (@ 0x0000100C) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_3_b; + } ; + + union { + __IO uint8_t CLICINTIE_3; /*!< (@ 0x0000100D) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_3_b; + } ; + + union { + __IO uint8_t CLICINTATTR_3; /*!< (@ 0x0000100E) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_3_b; + } ; + + union { + __IO uint8_t CLICINTCTL_3; /*!< (@ 0x0000100F) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_3_b; + } ; + + union { + __IO uint8_t CLICINTIP_4; /*!< (@ 0x00001010) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_4_b; + } ; + + union { + __IO uint8_t CLICINTIE_4; /*!< (@ 0x00001011) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_4_b; + } ; + + union { + __IO uint8_t CLICINTATTR_4; /*!< (@ 0x00001012) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_4_b; + } ; + + union { + __IO uint8_t CLICINTCTL_4; /*!< (@ 0x00001013) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_4_b; + } ; + + union { + __IO uint8_t CLICINTIP_5; /*!< (@ 0x00001014) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_5_b; + } ; + + union { + __IO uint8_t CLICINTIE_5; /*!< (@ 0x00001015) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_5_b; + } ; + + union { + __IO uint8_t CLICINTATTR_5; /*!< (@ 0x00001016) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_5_b; + } ; + + union { + __IO uint8_t CLICINTCTL_5; /*!< (@ 0x00001017) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_5_b; + } ; + + union { + __IO uint8_t CLICINTIP_6; /*!< (@ 0x00001018) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_6_b; + } ; + + union { + __IO uint8_t CLICINTIE_6; /*!< (@ 0x00001019) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_6_b; + } ; + + union { + __IO uint8_t CLICINTATTR_6; /*!< (@ 0x0000101A) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_6_b; + } ; + + union { + __IO uint8_t CLICINTCTL_6; /*!< (@ 0x0000101B) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_6_b; + } ; + + union { + __IO uint8_t CLICINTIP_7; /*!< (@ 0x0000101C) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_7_b; + } ; + + union { + __IO uint8_t CLICINTIE_7; /*!< (@ 0x0000101D) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_7_b; + } ; + + union { + __IO uint8_t CLICINTATTR_7; /*!< (@ 0x0000101E) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_7_b; + } ; + + union { + __IO uint8_t CLICINTCTL_7; /*!< (@ 0x0000101F) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_7_b; + } ; + + union { + __IO uint8_t CLICINTIP_8; /*!< (@ 0x00001020) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_8_b; + } ; + + union { + __IO uint8_t CLICINTIE_8; /*!< (@ 0x00001021) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_8_b; + } ; + + union { + __IO uint8_t CLICINTATTR_8; /*!< (@ 0x00001022) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_8_b; + } ; + + union { + __IO uint8_t CLICINTCTL_8; /*!< (@ 0x00001023) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_8_b; + } ; + + union { + __IO uint8_t CLICINTIP_9; /*!< (@ 0x00001024) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_9_b; + } ; + + union { + __IO uint8_t CLICINTIE_9; /*!< (@ 0x00001025) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_9_b; + } ; + + union { + __IO uint8_t CLICINTATTR_9; /*!< (@ 0x00001026) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_9_b; + } ; + + union { + __IO uint8_t CLICINTCTL_9; /*!< (@ 0x00001027) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_9_b; + } ; + + union { + __IO uint8_t CLICINTIP_10; /*!< (@ 0x00001028) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_10_b; + } ; + + union { + __IO uint8_t CLICINTIE_10; /*!< (@ 0x00001029) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_10_b; + } ; + + union { + __IO uint8_t CLICINTATTR_10; /*!< (@ 0x0000102A) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_10_b; + } ; + + union { + __IO uint8_t CLICINTCTL_10; /*!< (@ 0x0000102B) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_10_b; + } ; + + union { + __IO uint8_t CLICINTIP_11; /*!< (@ 0x0000102C) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_11_b; + } ; + + union { + __IO uint8_t CLICINTIE_11; /*!< (@ 0x0000102D) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_11_b; + } ; + + union { + __IO uint8_t CLICINTATTR_11; /*!< (@ 0x0000102E) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_11_b; + } ; + + union { + __IO uint8_t CLICINTCTL_11; /*!< (@ 0x0000102F) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_11_b; + } ; + + union { + __IO uint8_t CLICINTIP_12; /*!< (@ 0x00001030) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_12_b; + } ; + + union { + __IO uint8_t CLICINTIE_12; /*!< (@ 0x00001031) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_12_b; + } ; + + union { + __IO uint8_t CLICINTATTR_12; /*!< (@ 0x00001032) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_12_b; + } ; + + union { + __IO uint8_t CLICINTCTL_12; /*!< (@ 0x00001033) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_12_b; + } ; + + union { + __IO uint8_t CLICINTIP_13; /*!< (@ 0x00001034) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_13_b; + } ; + + union { + __IO uint8_t CLICINTIE_13; /*!< (@ 0x00001035) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_13_b; + } ; + + union { + __IO uint8_t CLICINTATTR_13; /*!< (@ 0x00001036) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_13_b; + } ; + + union { + __IO uint8_t CLICINTCTL_13; /*!< (@ 0x00001037) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_13_b; + } ; + + union { + __IO uint8_t CLICINTIP_14; /*!< (@ 0x00001038) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_14_b; + } ; + + union { + __IO uint8_t CLICINTIE_14; /*!< (@ 0x00001039) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_14_b; + } ; + + union { + __IO uint8_t CLICINTATTR_14; /*!< (@ 0x0000103A) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_14_b; + } ; + + union { + __IO uint8_t CLICINTCTL_14; /*!< (@ 0x0000103B) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_14_b; + } ; + + union { + __IO uint8_t CLICINTIP_15; /*!< (@ 0x0000103C) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_15_b; + } ; + + union { + __IO uint8_t CLICINTIE_15; /*!< (@ 0x0000103D) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_15_b; + } ; + + union { + __IO uint8_t CLICINTATTR_15; /*!< (@ 0x0000103E) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_15_b; + } ; + + union { + __IO uint8_t CLICINTCTL_15; /*!< (@ 0x0000103F) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_15_b; + } ; + + union { + __IO uint8_t CLICINTIP_16; /*!< (@ 0x00001040) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_16_b; + } ; + + union { + __IO uint8_t CLICINTIE_16; /*!< (@ 0x00001041) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_16_b; + } ; + + union { + __IO uint8_t CLICINTATTR_16; /*!< (@ 0x00001042) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_16_b; + } ; + + union { + __IO uint8_t CLICINTCTL_16; /*!< (@ 0x00001043) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_16_b; + } ; + + union { + __IO uint8_t CLICINTIP_17; /*!< (@ 0x00001044) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_17_b; + } ; + + union { + __IO uint8_t CLICINTIE_17; /*!< (@ 0x00001045) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_17_b; + } ; + + union { + __IO uint8_t CLICINTATTR_17; /*!< (@ 0x00001046) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_17_b; + } ; + + union { + __IO uint8_t CLICINTCTL_17; /*!< (@ 0x00001047) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_17_b; + } ; + + union { + __IO uint8_t CLICINTIP_18; /*!< (@ 0x00001048) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_18_b; + } ; + + union { + __IO uint8_t CLICINTIE_18; /*!< (@ 0x00001049) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_18_b; + } ; + + union { + __IO uint8_t CLICINTATTR_18; /*!< (@ 0x0000104A) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_18_b; + } ; + + union { + __IO uint8_t CLICINTCTL_18; /*!< (@ 0x0000104B) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_18_b; + } ; + + union { + __IO uint8_t CLICINTIP_19; /*!< (@ 0x0000104C) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_19_b; + } ; + + union { + __IO uint8_t CLICINTIE_19; /*!< (@ 0x0000104D) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_19_b; + } ; + + union { + __IO uint8_t CLICINTATTR_19; /*!< (@ 0x0000104E) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_19_b; + } ; + + union { + __IO uint8_t CLICINTCTL_19; /*!< (@ 0x0000104F) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_19_b; + } ; + + union { + __IO uint8_t CLICINTIP_20; /*!< (@ 0x00001050) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_20_b; + } ; + + union { + __IO uint8_t CLICINTIE_20; /*!< (@ 0x00001051) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_20_b; + } ; + + union { + __IO uint8_t CLICINTATTR_20; /*!< (@ 0x00001052) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_20_b; + } ; + + union { + __IO uint8_t CLICINTCTL_20; /*!< (@ 0x00001053) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_20_b; + } ; + + union { + __IO uint8_t CLICINTIP_21; /*!< (@ 0x00001054) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_21_b; + } ; + + union { + __IO uint8_t CLICINTIE_21; /*!< (@ 0x00001055) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_21_b; + } ; + + union { + __IO uint8_t CLICINTATTR_21; /*!< (@ 0x00001056) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_21_b; + } ; + + union { + __IO uint8_t CLICINTCTL_21; /*!< (@ 0x00001057) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_21_b; + } ; + + union { + __IO uint8_t CLICINTIP_22; /*!< (@ 0x00001058) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_22_b; + } ; + + union { + __IO uint8_t CLICINTIE_22; /*!< (@ 0x00001059) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_22_b; + } ; + + union { + __IO uint8_t CLICINTATTR_22; /*!< (@ 0x0000105A) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_22_b; + } ; + + union { + __IO uint8_t CLICINTCTL_22; /*!< (@ 0x0000105B) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_22_b; + } ; + + union { + __IO uint8_t CLICINTIP_23; /*!< (@ 0x0000105C) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_23_b; + } ; + + union { + __IO uint8_t CLICINTIE_23; /*!< (@ 0x0000105D) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_23_b; + } ; + + union { + __IO uint8_t CLICINTATTR_23; /*!< (@ 0x0000105E) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_23_b; + } ; + + union { + __IO uint8_t CLICINTCTL_23; /*!< (@ 0x0000105F) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_23_b; + } ; + + union { + __IO uint8_t CLICINTIP_24; /*!< (@ 0x00001060) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_24_b; + } ; + + union { + __IO uint8_t CLICINTIE_24; /*!< (@ 0x00001061) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_24_b; + } ; + + union { + __IO uint8_t CLICINTATTR_24; /*!< (@ 0x00001062) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_24_b; + } ; + + union { + __IO uint8_t CLICINTCTL_24; /*!< (@ 0x00001063) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_24_b; + } ; + + union { + __IO uint8_t CLICINTIP_25; /*!< (@ 0x00001064) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_25_b; + } ; + + union { + __IO uint8_t CLICINTIE_25; /*!< (@ 0x00001065) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_25_b; + } ; + + union { + __IO uint8_t CLICINTATTR_25; /*!< (@ 0x00001066) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_25_b; + } ; + + union { + __IO uint8_t CLICINTCTL_25; /*!< (@ 0x00001067) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_25_b; + } ; + + union { + __IO uint8_t CLICINTIP_26; /*!< (@ 0x00001068) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_26_b; + } ; + + union { + __IO uint8_t CLICINTIE_26; /*!< (@ 0x00001069) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_26_b; + } ; + + union { + __IO uint8_t CLICINTATTR_26; /*!< (@ 0x0000106A) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_26_b; + } ; + + union { + __IO uint8_t CLICINTCTL_26; /*!< (@ 0x0000106B) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_26_b; + } ; + + union { + __IO uint8_t CLICINTIP_27; /*!< (@ 0x0000106C) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_27_b; + } ; + + union { + __IO uint8_t CLICINTIE_27; /*!< (@ 0x0000106D) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_27_b; + } ; + + union { + __IO uint8_t CLICINTATTR_27; /*!< (@ 0x0000106E) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_27_b; + } ; + + union { + __IO uint8_t CLICINTCTL_27; /*!< (@ 0x0000106F) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_27_b; + } ; + + union { + __IO uint8_t CLICINTIP_28; /*!< (@ 0x00001070) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_28_b; + } ; + + union { + __IO uint8_t CLICINTIE_28; /*!< (@ 0x00001071) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_28_b; + } ; + + union { + __IO uint8_t CLICINTATTR_28; /*!< (@ 0x00001072) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_28_b; + } ; + + union { + __IO uint8_t CLICINTCTL_28; /*!< (@ 0x00001073) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_28_b; + } ; + + union { + __IO uint8_t CLICINTIP_29; /*!< (@ 0x00001074) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_29_b; + } ; + + union { + __IO uint8_t CLICINTIE_29; /*!< (@ 0x00001075) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_29_b; + } ; + + union { + __IO uint8_t CLICINTATTR_29; /*!< (@ 0x00001076) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_29_b; + } ; + + union { + __IO uint8_t CLICINTCTL_29; /*!< (@ 0x00001077) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_29_b; + } ; + + union { + __IO uint8_t CLICINTIP_30; /*!< (@ 0x00001078) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_30_b; + } ; + + union { + __IO uint8_t CLICINTIE_30; /*!< (@ 0x00001079) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_30_b; + } ; + + union { + __IO uint8_t CLICINTATTR_30; /*!< (@ 0x0000107A) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_30_b; + } ; + + union { + __IO uint8_t CLICINTCTL_30; /*!< (@ 0x0000107B) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_30_b; + } ; + + union { + __IO uint8_t CLICINTIP_31; /*!< (@ 0x0000107C) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_31_b; + } ; + + union { + __IO uint8_t CLICINTIE_31; /*!< (@ 0x0000107D) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_31_b; + } ; + + union { + __IO uint8_t CLICINTATTR_31; /*!< (@ 0x0000107E) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_31_b; + } ; + + union { + __IO uint8_t CLICINTCTL_31; /*!< (@ 0x0000107F) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_31_b; + } ; + + union { + __IO uint8_t CLICINTIP_32; /*!< (@ 0x00001080) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_32_b; + } ; + + union { + __IO uint8_t CLICINTIE_32; /*!< (@ 0x00001081) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_32_b; + } ; + + union { + __IO uint8_t CLICINTATTR_32; /*!< (@ 0x00001082) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_32_b; + } ; + + union { + __IO uint8_t CLICINTCTL_32; /*!< (@ 0x00001083) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_32_b; + } ; + + union { + __IO uint8_t CLICINTIP_33; /*!< (@ 0x00001084) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_33_b; + } ; + + union { + __IO uint8_t CLICINTIE_33; /*!< (@ 0x00001085) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_33_b; + } ; + + union { + __IO uint8_t CLICINTATTR_33; /*!< (@ 0x00001086) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_33_b; + } ; + + union { + __IO uint8_t CLICINTCTL_33; /*!< (@ 0x00001087) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_33_b; + } ; + + union { + __IO uint8_t CLICINTIP_34; /*!< (@ 0x00001088) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_34_b; + } ; + + union { + __IO uint8_t CLICINTIE_34; /*!< (@ 0x00001089) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_34_b; + } ; + + union { + __IO uint8_t CLICINTATTR_34; /*!< (@ 0x0000108A) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_34_b; + } ; + + union { + __IO uint8_t CLICINTCTL_34; /*!< (@ 0x0000108B) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_34_b; + } ; + + union { + __IO uint8_t CLICINTIP_35; /*!< (@ 0x0000108C) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_35_b; + } ; + + union { + __IO uint8_t CLICINTIE_35; /*!< (@ 0x0000108D) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_35_b; + } ; + + union { + __IO uint8_t CLICINTATTR_35; /*!< (@ 0x0000108E) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_35_b; + } ; + + union { + __IO uint8_t CLICINTCTL_35; /*!< (@ 0x0000108F) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_35_b; + } ; + + union { + __IO uint8_t CLICINTIP_36; /*!< (@ 0x00001090) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_36_b; + } ; + + union { + __IO uint8_t CLICINTIE_36; /*!< (@ 0x00001091) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_36_b; + } ; + + union { + __IO uint8_t CLICINTATTR_36; /*!< (@ 0x00001092) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_36_b; + } ; + + union { + __IO uint8_t CLICINTCTL_36; /*!< (@ 0x00001093) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_36_b; + } ; + + union { + __IO uint8_t CLICINTIP_37; /*!< (@ 0x00001094) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_37_b; + } ; + + union { + __IO uint8_t CLICINTIE_37; /*!< (@ 0x00001095) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_37_b; + } ; + + union { + __IO uint8_t CLICINTATTR_37; /*!< (@ 0x00001096) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_37_b; + } ; + + union { + __IO uint8_t CLICINTCTL_37; /*!< (@ 0x00001097) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_37_b; + } ; + + union { + __IO uint8_t CLICINTIP_38; /*!< (@ 0x00001098) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_38_b; + } ; + + union { + __IO uint8_t CLICINTIE_38; /*!< (@ 0x00001099) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_38_b; + } ; + + union { + __IO uint8_t CLICINTATTR_38; /*!< (@ 0x0000109A) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_38_b; + } ; + + union { + __IO uint8_t CLICINTCTL_38; /*!< (@ 0x0000109B) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_38_b; + } ; + + union { + __IO uint8_t CLICINTIP_39; /*!< (@ 0x0000109C) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_39_b; + } ; + + union { + __IO uint8_t CLICINTIE_39; /*!< (@ 0x0000109D) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_39_b; + } ; + + union { + __IO uint8_t CLICINTATTR_39; /*!< (@ 0x0000109E) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_39_b; + } ; + + union { + __IO uint8_t CLICINTCTL_39; /*!< (@ 0x0000109F) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_39_b; + } ; + + union { + __IO uint8_t CLICINTIP_40; /*!< (@ 0x000010A0) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_40_b; + } ; + + union { + __IO uint8_t CLICINTIE_40; /*!< (@ 0x000010A1) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_40_b; + } ; + + union { + __IO uint8_t CLICINTATTR_40; /*!< (@ 0x000010A2) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_40_b; + } ; + + union { + __IO uint8_t CLICINTCTL_40; /*!< (@ 0x000010A3) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_40_b; + } ; + + union { + __IO uint8_t CLICINTIP_41; /*!< (@ 0x000010A4) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_41_b; + } ; + + union { + __IO uint8_t CLICINTIE_41; /*!< (@ 0x000010A5) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_41_b; + } ; + + union { + __IO uint8_t CLICINTATTR_41; /*!< (@ 0x000010A6) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_41_b; + } ; + + union { + __IO uint8_t CLICINTCTL_41; /*!< (@ 0x000010A7) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_41_b; + } ; + + union { + __IO uint8_t CLICINTIP_42; /*!< (@ 0x000010A8) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_42_b; + } ; + + union { + __IO uint8_t CLICINTIE_42; /*!< (@ 0x000010A9) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_42_b; + } ; + + union { + __IO uint8_t CLICINTATTR_42; /*!< (@ 0x000010AA) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_42_b; + } ; + + union { + __IO uint8_t CLICINTCTL_42; /*!< (@ 0x000010AB) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_42_b; + } ; + + union { + __IO uint8_t CLICINTIP_43; /*!< (@ 0x000010AC) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_43_b; + } ; + + union { + __IO uint8_t CLICINTIE_43; /*!< (@ 0x000010AD) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_43_b; + } ; + + union { + __IO uint8_t CLICINTATTR_43; /*!< (@ 0x000010AE) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_43_b; + } ; + + union { + __IO uint8_t CLICINTCTL_43; /*!< (@ 0x000010AF) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_43_b; + } ; + + union { + __IO uint8_t CLICINTIP_44; /*!< (@ 0x000010B0) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_44_b; + } ; + + union { + __IO uint8_t CLICINTIE_44; /*!< (@ 0x000010B1) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_44_b; + } ; + + union { + __IO uint8_t CLICINTATTR_44; /*!< (@ 0x000010B2) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_44_b; + } ; + + union { + __IO uint8_t CLICINTCTL_44; /*!< (@ 0x000010B3) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_44_b; + } ; + + union { + __IO uint8_t CLICINTIP_45; /*!< (@ 0x000010B4) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_45_b; + } ; + + union { + __IO uint8_t CLICINTIE_45; /*!< (@ 0x000010B5) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_45_b; + } ; + + union { + __IO uint8_t CLICINTATTR_45; /*!< (@ 0x000010B6) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_45_b; + } ; + + union { + __IO uint8_t CLICINTCTL_45; /*!< (@ 0x000010B7) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_45_b; + } ; + + union { + __IO uint8_t CLICINTIP_46; /*!< (@ 0x000010B8) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_46_b; + } ; + + union { + __IO uint8_t CLICINTIE_46; /*!< (@ 0x000010B9) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_46_b; + } ; + + union { + __IO uint8_t CLICINTATTR_46; /*!< (@ 0x000010BA) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_46_b; + } ; + + union { + __IO uint8_t CLICINTCTL_46; /*!< (@ 0x000010BB) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_46_b; + } ; + + union { + __IO uint8_t CLICINTIP_47; /*!< (@ 0x000010BC) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_47_b; + } ; + + union { + __IO uint8_t CLICINTIE_47; /*!< (@ 0x000010BD) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_47_b; + } ; + + union { + __IO uint8_t CLICINTATTR_47; /*!< (@ 0x000010BE) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_47_b; + } ; + + union { + __IO uint8_t CLICINTCTL_47; /*!< (@ 0x000010BF) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_47_b; + } ; + + union { + __IO uint8_t CLICINTIP_48; /*!< (@ 0x000010C0) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_48_b; + } ; + + union { + __IO uint8_t CLICINTIE_48; /*!< (@ 0x000010C1) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_48_b; + } ; + + union { + __IO uint8_t CLICINTATTR_48; /*!< (@ 0x000010C2) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_48_b; + } ; + + union { + __IO uint8_t CLICINTCTL_48; /*!< (@ 0x000010C3) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_48_b; + } ; + + union { + __IO uint8_t CLICINTIP_49; /*!< (@ 0x000010C4) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_49_b; + } ; + + union { + __IO uint8_t CLICINTIE_49; /*!< (@ 0x000010C5) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_49_b; + } ; + + union { + __IO uint8_t CLICINTATTR_49; /*!< (@ 0x000010C6) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_49_b; + } ; + + union { + __IO uint8_t CLICINTCTL_49; /*!< (@ 0x000010C7) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_49_b; + } ; + + union { + __IO uint8_t CLICINTIP_50; /*!< (@ 0x000010C8) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_50_b; + } ; + + union { + __IO uint8_t CLICINTIE_50; /*!< (@ 0x000010C9) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_50_b; + } ; + + union { + __IO uint8_t CLICINTATTR_50; /*!< (@ 0x000010CA) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_50_b; + } ; + + union { + __IO uint8_t CLICINTCTL_50; /*!< (@ 0x000010CB) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_50_b; + } ; + + union { + __IO uint8_t CLICINTIP_51; /*!< (@ 0x000010CC) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_51_b; + } ; + + union { + __IO uint8_t CLICINTIE_51; /*!< (@ 0x000010CD) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_51_b; + } ; + + union { + __IO uint8_t CLICINTATTR_51; /*!< (@ 0x000010CE) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_51_b; + } ; + + union { + __IO uint8_t CLICINTCTL_51; /*!< (@ 0x000010CF) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_51_b; + } ; + + union { + __IO uint8_t CLICINTIP_52; /*!< (@ 0x000010D0) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_52_b; + } ; + + union { + __IO uint8_t CLICINTIE_52; /*!< (@ 0x000010D1) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_52_b; + } ; + + union { + __IO uint8_t CLICINTATTR_52; /*!< (@ 0x000010D2) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_52_b; + } ; + + union { + __IO uint8_t CLICINTCTL_52; /*!< (@ 0x000010D3) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_52_b; + } ; + + union { + __IO uint8_t CLICINTIP_53; /*!< (@ 0x000010D4) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_53_b; + } ; + + union { + __IO uint8_t CLICINTIE_53; /*!< (@ 0x000010D5) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_53_b; + } ; + + union { + __IO uint8_t CLICINTATTR_53; /*!< (@ 0x000010D6) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_53_b; + } ; + + union { + __IO uint8_t CLICINTCTL_53; /*!< (@ 0x000010D7) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_53_b; + } ; + + union { + __IO uint8_t CLICINTIP_54; /*!< (@ 0x000010D8) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_54_b; + } ; + + union { + __IO uint8_t CLICINTIE_54; /*!< (@ 0x000010D9) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_54_b; + } ; + + union { + __IO uint8_t CLICINTATTR_54; /*!< (@ 0x000010DA) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_54_b; + } ; + + union { + __IO uint8_t CLICINTCTL_54; /*!< (@ 0x000010DB) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_54_b; + } ; + + union { + __IO uint8_t CLICINTIP_55; /*!< (@ 0x000010DC) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_55_b; + } ; + + union { + __IO uint8_t CLICINTIE_55; /*!< (@ 0x000010DD) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_55_b; + } ; + + union { + __IO uint8_t CLICINTATTR_55; /*!< (@ 0x000010DE) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_55_b; + } ; + + union { + __IO uint8_t CLICINTCTL_55; /*!< (@ 0x000010DF) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_55_b; + } ; + + union { + __IO uint8_t CLICINTIP_56; /*!< (@ 0x000010E0) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_56_b; + } ; + + union { + __IO uint8_t CLICINTIE_56; /*!< (@ 0x000010E1) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_56_b; + } ; + + union { + __IO uint8_t CLICINTATTR_56; /*!< (@ 0x000010E2) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_56_b; + } ; + + union { + __IO uint8_t CLICINTCTL_56; /*!< (@ 0x000010E3) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_56_b; + } ; + + union { + __IO uint8_t CLICINTIP_57; /*!< (@ 0x000010E4) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_57_b; + } ; + + union { + __IO uint8_t CLICINTIE_57; /*!< (@ 0x000010E5) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_57_b; + } ; + + union { + __IO uint8_t CLICINTATTR_57; /*!< (@ 0x000010E6) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_57_b; + } ; + + union { + __IO uint8_t CLICINTCTL_57; /*!< (@ 0x000010E7) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_57_b; + } ; + + union { + __IO uint8_t CLICINTIP_58; /*!< (@ 0x000010E8) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_58_b; + } ; + + union { + __IO uint8_t CLICINTIE_58; /*!< (@ 0x000010E9) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_58_b; + } ; + + union { + __IO uint8_t CLICINTATTR_58; /*!< (@ 0x000010EA) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_58_b; + } ; + + union { + __IO uint8_t CLICINTCTL_58; /*!< (@ 0x000010EB) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_58_b; + } ; + + union { + __IO uint8_t CLICINTIP_59; /*!< (@ 0x000010EC) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_59_b; + } ; + + union { + __IO uint8_t CLICINTIE_59; /*!< (@ 0x000010ED) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_59_b; + } ; + + union { + __IO uint8_t CLICINTATTR_59; /*!< (@ 0x000010EE) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_59_b; + } ; + + union { + __IO uint8_t CLICINTCTL_59; /*!< (@ 0x000010EF) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_59_b; + } ; + + union { + __IO uint8_t CLICINTIP_60; /*!< (@ 0x000010F0) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_60_b; + } ; + + union { + __IO uint8_t CLICINTIE_60; /*!< (@ 0x000010F1) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_60_b; + } ; + + union { + __IO uint8_t CLICINTATTR_60; /*!< (@ 0x000010F2) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_60_b; + } ; + + union { + __IO uint8_t CLICINTCTL_60; /*!< (@ 0x000010F3) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_60_b; + } ; + + union { + __IO uint8_t CLICINTIP_61; /*!< (@ 0x000010F4) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_61_b; + } ; + + union { + __IO uint8_t CLICINTIE_61; /*!< (@ 0x000010F5) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_61_b; + } ; + + union { + __IO uint8_t CLICINTATTR_61; /*!< (@ 0x000010F6) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_61_b; + } ; + + union { + __IO uint8_t CLICINTCTL_61; /*!< (@ 0x000010F7) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_61_b; + } ; + + union { + __IO uint8_t CLICINTIP_62; /*!< (@ 0x000010F8) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_62_b; + } ; + + union { + __IO uint8_t CLICINTIE_62; /*!< (@ 0x000010F9) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_62_b; + } ; + + union { + __IO uint8_t CLICINTATTR_62; /*!< (@ 0x000010FA) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_62_b; + } ; + + union { + __IO uint8_t CLICINTCTL_62; /*!< (@ 0x000010FB) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_62_b; + } ; + + union { + __IO uint8_t CLICINTIP_63; /*!< (@ 0x000010FC) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_63_b; + } ; + + union { + __IO uint8_t CLICINTIE_63; /*!< (@ 0x000010FD) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_63_b; + } ; + + union { + __IO uint8_t CLICINTATTR_63; /*!< (@ 0x000010FE) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_63_b; + } ; + + union { + __IO uint8_t CLICINTCTL_63; /*!< (@ 0x000010FF) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_63_b; + } ; + + union { + __IO uint8_t CLICINTIP_64; /*!< (@ 0x00001100) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_64_b; + } ; + + union { + __IO uint8_t CLICINTIE_64; /*!< (@ 0x00001101) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_64_b; + } ; + + union { + __IO uint8_t CLICINTATTR_64; /*!< (@ 0x00001102) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_64_b; + } ; + + union { + __IO uint8_t CLICINTCTL_64; /*!< (@ 0x00001103) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_64_b; + } ; + + union { + __IO uint8_t CLICINTIP_65; /*!< (@ 0x00001104) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_65_b; + } ; + + union { + __IO uint8_t CLICINTIE_65; /*!< (@ 0x00001105) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_65_b; + } ; + + union { + __IO uint8_t CLICINTATTR_65; /*!< (@ 0x00001106) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_65_b; + } ; + + union { + __IO uint8_t CLICINTCTL_65; /*!< (@ 0x00001107) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_65_b; + } ; + + union { + __IO uint8_t CLICINTIP_66; /*!< (@ 0x00001108) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_66_b; + } ; + + union { + __IO uint8_t CLICINTIE_66; /*!< (@ 0x00001109) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_66_b; + } ; + + union { + __IO uint8_t CLICINTATTR_66; /*!< (@ 0x0000110A) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_66_b; + } ; + + union { + __IO uint8_t CLICINTCTL_66; /*!< (@ 0x0000110B) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_66_b; + } ; + + union { + __IO uint8_t CLICINTIP_67; /*!< (@ 0x0000110C) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_67_b; + } ; + + union { + __IO uint8_t CLICINTIE_67; /*!< (@ 0x0000110D) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_67_b; + } ; + + union { + __IO uint8_t CLICINTATTR_67; /*!< (@ 0x0000110E) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_67_b; + } ; + + union { + __IO uint8_t CLICINTCTL_67; /*!< (@ 0x0000110F) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_67_b; + } ; + + union { + __IO uint8_t CLICINTIP_68; /*!< (@ 0x00001110) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_68_b; + } ; + + union { + __IO uint8_t CLICINTIE_68; /*!< (@ 0x00001111) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_68_b; + } ; + + union { + __IO uint8_t CLICINTATTR_68; /*!< (@ 0x00001112) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_68_b; + } ; + + union { + __IO uint8_t CLICINTCTL_68; /*!< (@ 0x00001113) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_68_b; + } ; + + union { + __IO uint8_t CLICINTIP_69; /*!< (@ 0x00001114) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_69_b; + } ; + + union { + __IO uint8_t CLICINTIE_69; /*!< (@ 0x00001115) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_69_b; + } ; + + union { + __IO uint8_t CLICINTATTR_69; /*!< (@ 0x00001116) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_69_b; + } ; + + union { + __IO uint8_t CLICINTCTL_69; /*!< (@ 0x00001117) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_69_b; + } ; + + union { + __IO uint8_t CLICINTIP_70; /*!< (@ 0x00001118) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_70_b; + } ; + + union { + __IO uint8_t CLICINTIE_70; /*!< (@ 0x00001119) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_70_b; + } ; + + union { + __IO uint8_t CLICINTATTR_70; /*!< (@ 0x0000111A) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_70_b; + } ; + + union { + __IO uint8_t CLICINTCTL_70; /*!< (@ 0x0000111B) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_70_b; + } ; + + union { + __IO uint8_t CLICINTIP_71; /*!< (@ 0x0000111C) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_71_b; + } ; + + union { + __IO uint8_t CLICINTIE_71; /*!< (@ 0x0000111D) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_71_b; + } ; + + union { + __IO uint8_t CLICINTATTR_71; /*!< (@ 0x0000111E) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_71_b; + } ; + + union { + __IO uint8_t CLICINTCTL_71; /*!< (@ 0x0000111F) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_71_b; + } ; + + union { + __IO uint8_t CLICINTIP_72; /*!< (@ 0x00001120) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_72_b; + } ; + + union { + __IO uint8_t CLICINTIE_72; /*!< (@ 0x00001121) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_72_b; + } ; + + union { + __IO uint8_t CLICINTATTR_72; /*!< (@ 0x00001122) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_72_b; + } ; + + union { + __IO uint8_t CLICINTCTL_72; /*!< (@ 0x00001123) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_72_b; + } ; + + union { + __IO uint8_t CLICINTIP_73; /*!< (@ 0x00001124) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_73_b; + } ; + + union { + __IO uint8_t CLICINTIE_73; /*!< (@ 0x00001125) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_73_b; + } ; + + union { + __IO uint8_t CLICINTATTR_73; /*!< (@ 0x00001126) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_73_b; + } ; + + union { + __IO uint8_t CLICINTCTL_73; /*!< (@ 0x00001127) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_73_b; + } ; + + union { + __IO uint8_t CLICINTIP_74; /*!< (@ 0x00001128) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_74_b; + } ; + + union { + __IO uint8_t CLICINTIE_74; /*!< (@ 0x00001129) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_74_b; + } ; + + union { + __IO uint8_t CLICINTATTR_74; /*!< (@ 0x0000112A) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_74_b; + } ; + + union { + __IO uint8_t CLICINTCTL_74; /*!< (@ 0x0000112B) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_74_b; + } ; + + union { + __IO uint8_t CLICINTIP_75; /*!< (@ 0x0000112C) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_75_b; + } ; + + union { + __IO uint8_t CLICINTIE_75; /*!< (@ 0x0000112D) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_75_b; + } ; + + union { + __IO uint8_t CLICINTATTR_75; /*!< (@ 0x0000112E) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_75_b; + } ; + + union { + __IO uint8_t CLICINTCTL_75; /*!< (@ 0x0000112F) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_75_b; + } ; + + union { + __IO uint8_t CLICINTIP_76; /*!< (@ 0x00001130) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_76_b; + } ; + + union { + __IO uint8_t CLICINTIE_76; /*!< (@ 0x00001131) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_76_b; + } ; + + union { + __IO uint8_t CLICINTATTR_76; /*!< (@ 0x00001132) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_76_b; + } ; + + union { + __IO uint8_t CLICINTCTL_76; /*!< (@ 0x00001133) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_76_b; + } ; + + union { + __IO uint8_t CLICINTIP_77; /*!< (@ 0x00001134) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_77_b; + } ; + + union { + __IO uint8_t CLICINTIE_77; /*!< (@ 0x00001135) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_77_b; + } ; + + union { + __IO uint8_t CLICINTATTR_77; /*!< (@ 0x00001136) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_77_b; + } ; + + union { + __IO uint8_t CLICINTCTL_77; /*!< (@ 0x00001137) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_77_b; + } ; + + union { + __IO uint8_t CLICINTIP_78; /*!< (@ 0x00001138) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_78_b; + } ; + + union { + __IO uint8_t CLICINTIE_78; /*!< (@ 0x00001139) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_78_b; + } ; + + union { + __IO uint8_t CLICINTATTR_78; /*!< (@ 0x0000113A) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_78_b; + } ; + + union { + __IO uint8_t CLICINTCTL_78; /*!< (@ 0x0000113B) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_78_b; + } ; + + union { + __IO uint8_t CLICINTIP_79; /*!< (@ 0x0000113C) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_79_b; + } ; + + union { + __IO uint8_t CLICINTIE_79; /*!< (@ 0x0000113D) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_79_b; + } ; + + union { + __IO uint8_t CLICINTATTR_79; /*!< (@ 0x0000113E) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_79_b; + } ; + + union { + __IO uint8_t CLICINTCTL_79; /*!< (@ 0x0000113F) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_79_b; + } ; + + union { + __IO uint8_t CLICINTIP_80; /*!< (@ 0x00001140) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_80_b; + } ; + + union { + __IO uint8_t CLICINTIE_80; /*!< (@ 0x00001141) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_80_b; + } ; + + union { + __IO uint8_t CLICINTATTR_80; /*!< (@ 0x00001142) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_80_b; + } ; + + union { + __IO uint8_t CLICINTCTL_80; /*!< (@ 0x00001143) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_80_b; + } ; + + union { + __IO uint8_t CLICINTIP_81; /*!< (@ 0x00001144) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_81_b; + } ; + + union { + __IO uint8_t CLICINTIE_81; /*!< (@ 0x00001145) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_81_b; + } ; + + union { + __IO uint8_t CLICINTATTR_81; /*!< (@ 0x00001146) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_81_b; + } ; + + union { + __IO uint8_t CLICINTCTL_81; /*!< (@ 0x00001147) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_81_b; + } ; + + union { + __IO uint8_t CLICINTIP_82; /*!< (@ 0x00001148) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_82_b; + } ; + + union { + __IO uint8_t CLICINTIE_82; /*!< (@ 0x00001149) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_82_b; + } ; + + union { + __IO uint8_t CLICINTATTR_82; /*!< (@ 0x0000114A) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_82_b; + } ; + + union { + __IO uint8_t CLICINTCTL_82; /*!< (@ 0x0000114B) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_82_b; + } ; + + union { + __IO uint8_t CLICINTIP_83; /*!< (@ 0x0000114C) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_83_b; + } ; + + union { + __IO uint8_t CLICINTIE_83; /*!< (@ 0x0000114D) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_83_b; + } ; + + union { + __IO uint8_t CLICINTATTR_83; /*!< (@ 0x0000114E) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_83_b; + } ; + + union { + __IO uint8_t CLICINTCTL_83; /*!< (@ 0x0000114F) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_83_b; + } ; + + union { + __IO uint8_t CLICINTIP_84; /*!< (@ 0x00001150) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_84_b; + } ; + + union { + __IO uint8_t CLICINTIE_84; /*!< (@ 0x00001151) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_84_b; + } ; + + union { + __IO uint8_t CLICINTATTR_84; /*!< (@ 0x00001152) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_84_b; + } ; + + union { + __IO uint8_t CLICINTCTL_84; /*!< (@ 0x00001153) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_84_b; + } ; + __I uint8_t RESERVED5; + + union { + __IO uint8_t CLICINTIE_85; /*!< (@ 0x00001155) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_85_b; + } ; + + union { + __IO uint8_t CLICINTATTR_85; /*!< (@ 0x00001156) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_85_b; + } ; + + union { + __IO uint8_t CLICINTCTL_85; /*!< (@ 0x00001157) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_85_b; + } ; + + union { + __IO uint8_t CLICINTIP_85; /*!< (@ 0x00001158) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_85_b; + } ; + + union { + __IO uint8_t CLICINTIE_86; /*!< (@ 0x00001159) clicintie Register */ + + struct { + __IO uint8_t IE : 1; /*!< [0..0] IE */ + uint8_t : 7; + } CLICINTIE_86_b; + } ; + + union { + __IO uint8_t CLICINTATTR_86; /*!< (@ 0x0000115A) clicintattr Register */ + + struct { + __IO uint8_t SHV : 1; /*!< [0..0] SHV */ + __IO uint8_t TRIG : 2; /*!< [2..1] TRIG */ + uint8_t : 5; + } CLICINTATTR_86_b; + } ; + + union { + __IO uint8_t CLICINTCTL_86; /*!< (@ 0x0000115B) clicintctl Register */ + + struct { + __IO uint8_t LEVEL_PRIORITY : 8; /*!< [7..0] LEVEL_PRIORITY */ + } CLICINTCTL_86_b; + } ; + + union { + __IO uint8_t CLICINTIP_86; /*!< (@ 0x0000115C) clicintip Register */ + + struct { + __IO uint8_t IP : 1; /*!< [0..0] IP */ + uint8_t : 7; + } CLICINTIP_86_b; + } ; + __I uint8_t RESERVED6; + __I uint16_t RESERVED7; +} ECLIC_Type; /*!< Size = 4448 (0x1160) */ + + + +/* =========================================================================================================================== */ +/* ================ PMU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Power management unit (PMU) + */ + +typedef struct { /*!< (@ 0x40007000) PMU Structure */ + + union { + __IO uint32_t CTL; /*!< (@ 0x00000000) power control register */ + + struct { + __IO uint32_t LDOLP : 1; /*!< [0..0] LDO Low Power Mode */ + __IO uint32_t STBMOD : 1; /*!< [1..1] Standby Mode */ + __IO uint32_t WURST : 1; /*!< [2..2] Wakeup Flag Reset */ + __IO uint32_t STBRST : 1; /*!< [3..3] Standby Flag Reset */ + __IO uint32_t LVDEN : 1; /*!< [4..4] Low Voltage Detector Enable */ + __IO uint32_t LVDT : 3; /*!< [7..5] Low Voltage Detector Threshold */ + __IO uint32_t BKPWEN : 1; /*!< [8..8] Backup Domain Write Enable */ + uint32_t : 23; + } CTL_b; + } ; + + union { + __IO uint32_t CS; /*!< (@ 0x00000004) power control/status register */ + + struct { + __I uint32_t WUF : 1; /*!< [0..0] Wakeup flag */ + __I uint32_t STBF : 1; /*!< [1..1] Standby flag */ + __I uint32_t LVDF : 1; /*!< [2..2] Low Voltage Detector Status Flag */ + uint32_t : 5; + __IO uint32_t WUPEN : 1; /*!< [8..8] Enable WKUP pin */ + uint32_t : 23; + } CS_b; + } ; +} PMU_Type; /*!< Size = 8 (0x8) */ + + + +/* =========================================================================================================================== */ +/* ================ RCU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Reset and clock unit (RCU) + */ + +typedef struct { /*!< (@ 0x40021000) RCU Structure */ + + union { + __IO uint32_t CTL; /*!< (@ 0x00000000) Control register */ + + struct { + __IO uint32_t IRC8MEN : 1; /*!< [0..0] Internal 8MHz RC oscillator Enable */ + __I uint32_t IRC8MSTB : 1; /*!< [1..1] IRC8M Internal 8MHz RC Oscillator stabilization Flag */ + uint32_t : 1; + __IO uint32_t IRC8MADJ : 5; /*!< [7..3] Internal 8MHz RC Oscillator clock trim adjust value */ + __I uint32_t IRC8MCALIB : 8; /*!< [15..8] Internal 8MHz RC Oscillator calibration value register */ + __IO uint32_t HXTALEN : 1; /*!< [16..16] External High Speed oscillator Enable */ + __I uint32_t HXTALSTB : 1; /*!< [17..17] External crystal oscillator (HXTAL) clock stabilization + flag */ + __IO uint32_t HXTALBPS : 1; /*!< [18..18] External crystal oscillator (HXTAL) clock bypass mode + enable */ + __IO uint32_t CKMEN : 1; /*!< [19..19] HXTAL Clock Monitor Enable */ + uint32_t : 4; + __IO uint32_t PLLEN : 1; /*!< [24..24] PLL enable */ + __I uint32_t PLLSTB : 1; /*!< [25..25] PLL Clock Stabilization Flag */ + __IO uint32_t PLL1EN : 1; /*!< [26..26] PLL1 enable */ + __I uint32_t PLL1STB : 1; /*!< [27..27] PLL1 Clock Stabilization Flag */ + __IO uint32_t PLL2EN : 1; /*!< [28..28] PLL2 enable */ + __I uint32_t PLL2STB : 1; /*!< [29..29] PLL2 Clock Stabilization Flag */ + uint32_t : 2; + } CTL_b; + } ; + + union { + __IO uint32_t CFG0; /*!< (@ 0x00000004) Clock configuration register 0 (RCU_CFG0) */ + + struct { + __IO uint32_t SCS : 2; /*!< [1..0] System clock switch */ + __I uint32_t SCSS : 2; /*!< [3..2] System clock switch status */ + __IO uint32_t AHBPSC : 4; /*!< [7..4] AHB prescaler selection */ + __IO uint32_t APB1PSC : 3; /*!< [10..8] APB1 prescaler selection */ + __IO uint32_t APB2PSC : 3; /*!< [13..11] APB2 prescaler selection */ + __IO uint32_t ADCPSC_1_0 : 2; /*!< [15..14] ADC clock prescaler selection */ + __IO uint32_t PLLSEL : 1; /*!< [16..16] PLL Clock Source Selection */ + __IO uint32_t PREDV0_LSB : 1; /*!< [17..17] The LSB of PREDV0 division factor */ + __IO uint32_t PLLMF_3_0 : 4; /*!< [21..18] The PLL clock multiplication factor */ + __IO uint32_t USBFSPSC : 2; /*!< [23..22] USBFS clock prescaler selection */ + __IO uint32_t CKOUT0SEL : 4; /*!< [27..24] CKOUT0 Clock Source Selection */ + __IO uint32_t ADCPSC_2 : 1; /*!< [28..28] Bit 2 of ADCPSC */ + __IO uint32_t PLLMF_4 : 1; /*!< [29..29] Bit 4 of PLLMF */ + uint32_t : 2; + } CFG0_b; + } ; + + union { + __IO uint32_t INT; /*!< (@ 0x00000008) Clock interrupt register (RCU_INT) */ + + struct { + __I uint32_t IRC40KSTBIF : 1; /*!< [0..0] IRC40K stabilization interrupt flag */ + __I uint32_t LXTALSTBIF : 1; /*!< [1..1] LXTAL stabilization interrupt flag */ + __I uint32_t IRC8MSTBIF : 1; /*!< [2..2] IRC8M stabilization interrupt flag */ + __I uint32_t HXTALSTBIF : 1; /*!< [3..3] HXTAL stabilization interrupt flag */ + __I uint32_t PLLSTBIF : 1; /*!< [4..4] PLL stabilization interrupt flag */ + __I uint32_t PLL1STBIF : 1; /*!< [5..5] PLL1 stabilization interrupt flag */ + __I uint32_t PLL2STBIF : 1; /*!< [6..6] PLL2 stabilization interrupt flag */ + __I uint32_t CKMIF : 1; /*!< [7..7] HXTAL Clock Stuck Interrupt Flag */ + __IO uint32_t IRC40KSTBIE : 1; /*!< [8..8] IRC40K Stabilization interrupt enable */ + __IO uint32_t LXTALSTBIE : 1; /*!< [9..9] LXTAL Stabilization Interrupt Enable */ + __IO uint32_t IRC8MSTBIE : 1; /*!< [10..10] IRC8M Stabilization Interrupt Enable */ + __IO uint32_t HXTALSTBIE : 1; /*!< [11..11] HXTAL Stabilization Interrupt Enable */ + __IO uint32_t PLLSTBIE : 1; /*!< [12..12] PLL Stabilization Interrupt Enable */ + __IO uint32_t PLL1STBIE : 1; /*!< [13..13] PLL1 Stabilization Interrupt Enable */ + __IO uint32_t PLL2STBIE : 1; /*!< [14..14] PLL2 Stabilization Interrupt Enable */ + uint32_t : 1; + __O uint32_t IRC40KSTBIC : 1; /*!< [16..16] IRC40K Stabilization Interrupt Clear */ + __O uint32_t LXTALSTBIC : 1; /*!< [17..17] LXTAL Stabilization Interrupt Clear */ + __O uint32_t IRC8MSTBIC : 1; /*!< [18..18] IRC8M Stabilization Interrupt Clear */ + __O uint32_t HXTALSTBIC : 1; /*!< [19..19] HXTAL Stabilization Interrupt Clear */ + __O uint32_t PLLSTBIC : 1; /*!< [20..20] PLL stabilization Interrupt Clear */ + __O uint32_t PLL1STBIC : 1; /*!< [21..21] PLL1 stabilization Interrupt Clear */ + __O uint32_t PLL2STBIC : 1; /*!< [22..22] PLL2 stabilization Interrupt Clear */ + __O uint32_t CKMIC : 1; /*!< [23..23] HXTAL Clock Stuck Interrupt Clear */ + uint32_t : 8; + } INT_b; + } ; + + union { + __IO uint32_t APB2RST; /*!< (@ 0x0000000C) APB2 reset register (RCU_APB2RST) */ + + struct { + __IO uint32_t AFRST : 1; /*!< [0..0] Alternate function I/O reset */ + uint32_t : 1; + __IO uint32_t PARST : 1; /*!< [2..2] GPIO port A reset */ + __IO uint32_t PBRST : 1; /*!< [3..3] GPIO port B reset */ + __IO uint32_t PCRST : 1; /*!< [4..4] GPIO port C reset */ + __IO uint32_t PDRST : 1; /*!< [5..5] GPIO port D reset */ + __IO uint32_t PERST : 1; /*!< [6..6] GPIO port E reset */ + uint32_t : 2; + __IO uint32_t ADC0RST : 1; /*!< [9..9] ADC0 reset */ + __IO uint32_t ADC1RST : 1; /*!< [10..10] ADC1 reset */ + __IO uint32_t TIMER0RST : 1; /*!< [11..11] Timer 0 reset */ + __IO uint32_t SPI0RST : 1; /*!< [12..12] SPI0 reset */ + uint32_t : 1; + __IO uint32_t USART0RST : 1; /*!< [14..14] USART0 Reset */ + uint32_t : 17; + } APB2RST_b; + } ; + + union { + __IO uint32_t APB1RST; /*!< (@ 0x00000010) APB1 reset register (RCU_APB1RST) */ + + struct { + __IO uint32_t TIMER1RST : 1; /*!< [0..0] TIMER1 timer reset */ + __IO uint32_t TIMER2RST : 1; /*!< [1..1] TIMER2 timer reset */ + __IO uint32_t TIMER3RST : 1; /*!< [2..2] TIMER3 timer reset */ + __IO uint32_t TIMER4RST : 1; /*!< [3..3] TIMER4 timer reset */ + __IO uint32_t TIMER5RST : 1; /*!< [4..4] TIMER5 timer reset */ + __IO uint32_t TIMER6RST : 1; /*!< [5..5] TIMER6 timer reset */ + uint32_t : 5; + __IO uint32_t WWDGTRST : 1; /*!< [11..11] Window watchdog timer reset */ + uint32_t : 2; + __IO uint32_t SPI1RST : 1; /*!< [14..14] SPI1 reset */ + __IO uint32_t SPI2RST : 1; /*!< [15..15] SPI2 reset */ + uint32_t : 1; + __IO uint32_t USART1RST : 1; /*!< [17..17] USART1 reset */ + __IO uint32_t USART2RST : 1; /*!< [18..18] USART2 reset */ + __IO uint32_t UART3RST : 1; /*!< [19..19] UART3 reset */ + __IO uint32_t UART4RST : 1; /*!< [20..20] UART4 reset */ + __IO uint32_t I2C0RST : 1; /*!< [21..21] I2C0 reset */ + __IO uint32_t I2C1RST : 1; /*!< [22..22] I2C1 reset */ + uint32_t : 2; + __IO uint32_t CAN0RST : 1; /*!< [25..25] CAN0 reset */ + __IO uint32_t CAN1RST : 1; /*!< [26..26] CAN1 reset */ + __IO uint32_t BKPIRST : 1; /*!< [27..27] Backup interface reset */ + __IO uint32_t PMURST : 1; /*!< [28..28] Power control reset */ + __IO uint32_t DACRST : 1; /*!< [29..29] DAC reset */ + uint32_t : 2; + } APB1RST_b; + } ; + + union { + __IO uint32_t AHBEN; /*!< (@ 0x00000014) AHB enable register */ + + struct { + __IO uint32_t DMA0EN : 1; /*!< [0..0] DMA0 clock enable */ + __IO uint32_t DMA1EN : 1; /*!< [1..1] DMA1 clock enable */ + __IO uint32_t SRAMSPEN : 1; /*!< [2..2] SRAM interface clock enable when sleep mode */ + uint32_t : 1; + __IO uint32_t FMCSPEN : 1; /*!< [4..4] FMC clock enable when sleep mode */ + uint32_t : 1; + __IO uint32_t CRCEN : 1; /*!< [6..6] CRC clock enable */ + uint32_t : 1; + __IO uint32_t EXMCEN : 1; /*!< [8..8] EXMC clock enable */ + uint32_t : 3; + __IO uint32_t USBFSEN : 1; /*!< [12..12] USBFS clock enable */ + uint32_t : 19; + } AHBEN_b; + } ; + + union { + __IO uint32_t APB2EN; /*!< (@ 0x00000018) APB2 clock enable register (RCU_APB2EN) */ + + struct { + __IO uint32_t AFEN : 1; /*!< [0..0] Alternate function IO clock enable */ + uint32_t : 1; + __IO uint32_t PAEN : 1; /*!< [2..2] GPIO port A clock enable */ + __IO uint32_t PBEN : 1; /*!< [3..3] GPIO port B clock enable */ + __IO uint32_t PCEN : 1; /*!< [4..4] GPIO port C clock enable */ + __IO uint32_t PDEN : 1; /*!< [5..5] GPIO port D clock enable */ + __IO uint32_t PEEN : 1; /*!< [6..6] GPIO port E clock enable */ + uint32_t : 2; + __IO uint32_t ADC0EN : 1; /*!< [9..9] ADC0 clock enable */ + __IO uint32_t ADC1EN : 1; /*!< [10..10] ADC1 clock enable */ + __IO uint32_t TIMER0EN : 1; /*!< [11..11] TIMER0 clock enable */ + __IO uint32_t SPI0EN : 1; /*!< [12..12] SPI0 clock enable */ + uint32_t : 1; + __IO uint32_t USART0EN : 1; /*!< [14..14] USART0 clock enable */ + uint32_t : 17; + } APB2EN_b; + } ; + + union { + __IO uint32_t APB1EN; /*!< (@ 0x0000001C) APB1 clock enable register (RCU_APB1EN) */ + + struct { + __IO uint32_t TIMER1EN : 1; /*!< [0..0] TIMER1 timer clock enable */ + __IO uint32_t TIMER2EN : 1; /*!< [1..1] TIMER2 timer clock enable */ + __IO uint32_t TIMER3EN : 1; /*!< [2..2] TIMER3 timer clock enable */ + __IO uint32_t TIMER4EN : 1; /*!< [3..3] TIMER4 timer clock enable */ + __IO uint32_t TIMER5EN : 1; /*!< [4..4] TIMER5 timer clock enable */ + __IO uint32_t TIMER6EN : 1; /*!< [5..5] TIMER6 timer clock enable */ + uint32_t : 5; + __IO uint32_t WWDGTEN : 1; /*!< [11..11] Window watchdog timer clock enable */ + uint32_t : 2; + __IO uint32_t SPI1EN : 1; /*!< [14..14] SPI1 clock enable */ + __IO uint32_t SPI2EN : 1; /*!< [15..15] SPI2 clock enable */ + uint32_t : 1; + __IO uint32_t USART1EN : 1; /*!< [17..17] USART1 clock enable */ + __IO uint32_t USART2EN : 1; /*!< [18..18] USART2 clock enable */ + __IO uint32_t UART3EN : 1; /*!< [19..19] UART3 clock enable */ + __IO uint32_t UART4EN : 1; /*!< [20..20] UART4 clock enable */ + __IO uint32_t I2C0EN : 1; /*!< [21..21] I2C0 clock enable */ + __IO uint32_t I2C1EN : 1; /*!< [22..22] I2C1 clock enable */ + uint32_t : 2; + __IO uint32_t CAN0EN : 1; /*!< [25..25] CAN0 clock enable */ + __IO uint32_t CAN1EN : 1; /*!< [26..26] CAN1 clock enable */ + __IO uint32_t BKPIEN : 1; /*!< [27..27] Backup interface clock enable */ + __IO uint32_t PMUEN : 1; /*!< [28..28] Power control clock enable */ + __IO uint32_t DACEN : 1; /*!< [29..29] DAC clock enable */ + uint32_t : 2; + } APB1EN_b; + } ; + + union { + __IO uint32_t BDCTL; /*!< (@ 0x00000020) Backup domain control register (RCU_BDCTL) */ + + struct { + __IO uint32_t LXTALEN : 1; /*!< [0..0] LXTAL enable */ + __I uint32_t LXTALSTB : 1; /*!< [1..1] External low-speed oscillator stabilization */ + __IO uint32_t LXTALBPS : 1; /*!< [2..2] LXTAL bypass mode enable */ + uint32_t : 5; + __IO uint32_t RTCSRC : 2; /*!< [9..8] RTC clock entry selection */ + uint32_t : 5; + __IO uint32_t RTCEN : 1; /*!< [15..15] RTC clock enable */ + __IO uint32_t BKPRST : 1; /*!< [16..16] Backup domain reset */ + uint32_t : 15; + } BDCTL_b; + } ; + + union { + __IO uint32_t RSTSCK; /*!< (@ 0x00000024) Reset source /clock register (RCU_RSTSCK) */ + + struct { + __IO uint32_t IRC40KEN : 1; /*!< [0..0] IRC40K enable */ + __I uint32_t IRC40KSTB : 1; /*!< [1..1] IRC40K stabilization */ + uint32_t : 22; + __IO uint32_t RSTFC : 1; /*!< [24..24] Reset flag clear */ + uint32_t : 1; + __I uint32_t EPRSTF : 1; /*!< [26..26] External PIN reset flag */ + __I uint32_t PORRSTF : 1; /*!< [27..27] Power reset flag */ + __I uint32_t SWRSTF : 1; /*!< [28..28] Software reset flag */ + __I uint32_t FWDGTRSTF : 1; /*!< [29..29] Free Watchdog timer reset flag */ + __I uint32_t WWDGTRSTF : 1; /*!< [30..30] Window watchdog timer reset flag */ + __I uint32_t LPRSTF : 1; /*!< [31..31] Low-power reset flag */ + } RSTSCK_b; + } ; + + union { + __IO uint32_t AHBRST; /*!< (@ 0x00000028) AHB reset register */ + + struct { + uint32_t : 12; + __IO uint32_t USBFSRST : 1; /*!< [12..12] USBFS reset */ + uint32_t : 19; + } AHBRST_b; + } ; + + union { + __IO uint32_t CFG1; /*!< (@ 0x0000002C) Clock Configuration register 1 */ + + struct { + __IO uint32_t PREDV0 : 4; /*!< [3..0] PREDV0 division factor */ + __IO uint32_t PREDV1 : 4; /*!< [7..4] PREDV1 division factor */ + __IO uint32_t PLL1MF : 4; /*!< [11..8] The PLL1 clock multiplication factor */ + __IO uint32_t PLL2MF : 4; /*!< [15..12] The PLL2 clock multiplication factor */ + __IO uint32_t PREDV0SEL : 1; /*!< [16..16] PREDV0 input Clock Source Selection */ + __IO uint32_t I2S1SEL : 1; /*!< [17..17] I2S1 Clock Source Selection */ + __IO uint32_t I2S2SEL : 1; /*!< [18..18] I2S2 Clock Source Selection */ + uint32_t : 13; + } CFG1_b; + } ; + __I uint32_t RESERVED; + + union { + __IO uint32_t DSV; /*!< (@ 0x00000034) Deep sleep mode Voltage register */ + + struct { + __IO uint32_t DSLPVS : 2; /*!< [1..0] Deep-sleep mode voltage select */ + uint32_t : 30; + } DSV_b; + } ; +} RCU_Type; /*!< Size = 56 (0x38) */ + + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Real-time clock (RTC) + */ + +typedef struct { /*!< (@ 0x40002800) RTC Structure */ + + union { + __IO uint32_t INTEN; /*!< (@ 0x00000000) RTC interrupt enable register */ + + struct { + __IO uint32_t SCIE : 1; /*!< [0..0] Second interrupt */ + __IO uint32_t ALRMIE : 1; /*!< [1..1] Alarm interrupt enable */ + __IO uint32_t OVIE : 1; /*!< [2..2] Overflow interrupt enable */ + uint32_t : 29; + } INTEN_b; + } ; + + union { + __IO uint32_t CTL; /*!< (@ 0x00000004) control register */ + + struct { + __IO uint32_t SCIF : 1; /*!< [0..0] Sencond interrupt flag */ + __IO uint32_t ALRMIF : 1; /*!< [1..1] Alarm interrupt flag */ + __IO uint32_t OVIF : 1; /*!< [2..2] Overflow interrupt flag */ + __IO uint32_t RSYNF : 1; /*!< [3..3] Registers synchronized flag */ + __IO uint32_t CMF : 1; /*!< [4..4] Configuration mode flag */ + __IO uint32_t LWOFF : 1; /*!< [5..5] Last write operation finished flag */ + uint32_t : 26; + } CTL_b; + } ; + + union { + __IO uint32_t PSCH; /*!< (@ 0x00000008) RTC prescaler high register */ + + struct { + __O uint32_t PSC : 4; /*!< [3..0] RTC prescaler value high */ + uint32_t : 28; + } PSCH_b; + } ; + + union { + __IO uint32_t PSCL; /*!< (@ 0x0000000C) RTC prescaler low register */ + + struct { + __O uint32_t PSC : 16; /*!< [15..0] RTC prescaler value low */ + uint32_t : 16; + } PSCL_b; + } ; + + union { + __I uint32_t DIVH; /*!< (@ 0x00000010) RTC divider high register */ + + struct { + __I uint32_t DIV : 4; /*!< [3..0] RTC divider value high */ + uint32_t : 28; + } DIVH_b; + } ; + + union { + __I uint32_t DIVL; /*!< (@ 0x00000014) RTC divider low register */ + + struct { + __I uint32_t DIV : 16; /*!< [15..0] RTC divider value low */ + uint32_t : 16; + } DIVL_b; + } ; + + union { + __IO uint32_t CNTH; /*!< (@ 0x00000018) RTC counter high register */ + + struct { + __IO uint32_t CNT : 16; /*!< [15..0] RTC counter value high */ + uint32_t : 16; + } CNTH_b; + } ; + + union { + __IO uint32_t CNTL; /*!< (@ 0x0000001C) RTC counter low register */ + + struct { + __IO uint32_t CNT : 16; /*!< [15..0] RTC counter value low */ + uint32_t : 16; + } CNTL_b; + } ; + + union { + __O uint32_t ALRMH; /*!< (@ 0x00000020) Alarm high register */ + + struct { + __O uint32_t ALRM : 16; /*!< [15..0] Alarm value high */ + uint32_t : 16; + } ALRMH_b; + } ; + + union { + __O uint32_t ALRML; /*!< (@ 0x00000024) RTC alarm low register */ + + struct { + __O uint32_t ALRM : 16; /*!< [15..0] alarm value low */ + uint32_t : 16; + } ALRML_b; + } ; +} RTC_Type; /*!< Size = 40 (0x28) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial peripheral interface (SPI0) + */ + +typedef struct { /*!< (@ 0x40013000) SPI0 Structure */ + + union { + __IO uint16_t CTL0; /*!< (@ 0x00000000) control register 0 */ + + struct { + __IO uint16_t CKPH : 1; /*!< [0..0] Clock Phase Selection */ + __IO uint16_t CKPL : 1; /*!< [1..1] Clock polarity Selection */ + __IO uint16_t MSTMOD : 1; /*!< [2..2] Master Mode Enable */ + __IO uint16_t PSC : 3; /*!< [5..3] Master Clock Prescaler Selection */ + __IO uint16_t SPIEN : 1; /*!< [6..6] SPI enable */ + __IO uint16_t LF : 1; /*!< [7..7] LSB First Mode */ + __IO uint16_t SWNSS : 1; /*!< [8..8] NSS Pin Selection In NSS Software Mode */ + __IO uint16_t SWNSSEN : 1; /*!< [9..9] NSS Software Mode Selection */ + __IO uint16_t RO : 1; /*!< [10..10] Receive only */ + __IO uint16_t FF16 : 1; /*!< [11..11] Data frame format */ + __IO uint16_t CRCNT : 1; /*!< [12..12] CRC Next Transfer */ + __IO uint16_t CRCEN : 1; /*!< [13..13] CRC Calculation Enable */ + __IO uint16_t BDOEN : 1; /*!< [14..14] Bidirectional Transmit output enable */ + __IO uint16_t BDEN : 1; /*!< [15..15] Bidirectional enable */ + } CTL0_b; + } ; + __I uint16_t RESERVED; + + union { + __IO uint16_t CTL1; /*!< (@ 0x00000004) control register 1 */ + + struct { + __IO uint16_t DMAREN : 1; /*!< [0..0] Rx buffer DMA enable */ + __IO uint16_t DMATEN : 1; /*!< [1..1] Transmit Buffer DMA Enable */ + __IO uint16_t NSSDRV : 1; /*!< [2..2] Drive NSS Output */ + __IO uint16_t NSSP : 1; /*!< [3..3] SPI NSS pulse mode enable */ + __IO uint16_t TMOD : 1; /*!< [4..4] SPI TI mode enable */ + __IO uint16_t ERRIE : 1; /*!< [5..5] Error interrupt enable */ + __IO uint16_t RBNEIE : 1; /*!< [6..6] RX buffer not empty interrupt enable */ + __IO uint16_t TBEIE : 1; /*!< [7..7] Tx buffer empty interrupt enable */ + uint16_t : 8; + } CTL1_b; + } ; + __I uint16_t RESERVED1; + + union { + __IO uint16_t STAT; /*!< (@ 0x00000008) status register */ + + struct { + __I uint16_t RBNE : 1; /*!< [0..0] Receive Buffer Not Empty */ + __I uint16_t TBE : 1; /*!< [1..1] Transmit Buffer Empty */ + __I uint16_t I2SCH : 1; /*!< [2..2] I2S channel side */ + __I uint16_t TXURERR : 1; /*!< [3..3] Transmission underrun error bit */ + __IO uint16_t CRCERR : 1; /*!< [4..4] SPI CRC Error Bit */ + __I uint16_t CONFERR : 1; /*!< [5..5] SPI Configuration error */ + __I uint16_t RXORERR : 1; /*!< [6..6] Reception Overrun Error Bit */ + __I uint16_t TRANS : 1; /*!< [7..7] Transmitting On-going Bit */ + __I uint16_t FERR : 1; /*!< [8..8] Format error */ + uint16_t : 7; + } STAT_b; + } ; + __I uint16_t RESERVED2; + + union { + __IO uint16_t DATA; /*!< (@ 0x0000000C) data register */ + + struct { + __IO uint16_t SPI_DATA : 16; /*!< [15..0] Data transfer register */ + } DATA_b; + } ; + __I uint16_t RESERVED3; + + union { + __IO uint16_t CRCPOLY; /*!< (@ 0x00000010) CRC polynomial register */ + + struct { + __IO uint16_t CRCPOLY : 16; /*!< [15..0] CRC polynomial value */ + } CRCPOLY_b; + } ; + __I uint16_t RESERVED4; + + union { + __I uint16_t RCRC; /*!< (@ 0x00000014) RX CRC register */ + + struct { + __I uint16_t RCRC : 16; /*!< [15..0] RX CRC value */ + } RCRC_b; + } ; + __I uint16_t RESERVED5; + + union { + __I uint16_t TCRC; /*!< (@ 0x00000018) TX CRC register */ + + struct { + __I uint16_t TCRC : 16; /*!< [15..0] Tx CRC value */ + } TCRC_b; + } ; + __I uint16_t RESERVED6; + + union { + __IO uint16_t I2SCTL; /*!< (@ 0x0000001C) I2S control register */ + + struct { + __IO uint16_t CHLEN : 1; /*!< [0..0] Channel length (number of bits per audio channel) */ + __IO uint16_t DTLEN : 2; /*!< [2..1] Data length */ + __IO uint16_t CKPL : 1; /*!< [3..3] Idle state clock polarity */ + __IO uint16_t I2SSTD : 2; /*!< [5..4] I2S standard selection */ + uint16_t : 1; + __IO uint16_t PCMSMOD : 1; /*!< [7..7] PCM frame synchronization mode */ + __IO uint16_t I2SOPMOD : 2; /*!< [9..8] I2S operation mode */ + __IO uint16_t I2SEN : 1; /*!< [10..10] I2S Enable */ + __IO uint16_t I2SSEL : 1; /*!< [11..11] I2S mode selection */ + uint16_t : 4; + } I2SCTL_b; + } ; + __I uint16_t RESERVED7; + + union { + __IO uint16_t I2SPSC; /*!< (@ 0x00000020) I2S prescaler register */ + + struct { + __IO uint16_t DIV : 8; /*!< [7..0] Dividing factor for the prescaler */ + __IO uint16_t OF : 1; /*!< [8..8] Odd factor for the prescaler */ + __IO uint16_t MCKOEN : 1; /*!< [9..9] I2S_MCK output enable */ + uint16_t : 6; + } I2SPSC_b; + } ; +} SPI_Type; /*!< Size = 34 (0x22) */ + + + +/* =========================================================================================================================== */ +/* ================ TIMER ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief timers (TIMER) + */ + +typedef struct { /*!< (@ 0x40012C00) TIMER0 Structure */ + + union { + __IO uint16_t CTL0; /*!< (@ 0x00000000) control register 0 */ + + struct { + __IO uint16_t CEN : 1; /*!< [0..0] Counter enable */ + __IO uint16_t UPDIS : 1; /*!< [1..1] Update disable */ + __IO uint16_t UPS : 1; /*!< [2..2] Update source */ + __IO uint16_t SPM : 1; /*!< [3..3] Single pulse mode */ + __IO uint16_t DIR : 1; /*!< [4..4] Direction */ + __IO uint16_t CAM : 2; /*!< [6..5] Counter aligns mode selection */ + __IO uint16_t ARSE : 1; /*!< [7..7] Auto-reload shadow enable */ + __IO uint16_t CKDIV : 2; /*!< [9..8] Clock division */ + uint16_t : 6; + } CTL0_b; + } ; + __I uint16_t RESERVED; + + union { + __IO uint16_t CTL1; /*!< (@ 0x00000004) control register 1 */ + + struct { + __IO uint16_t CCSE : 1; /*!< [0..0] Commutation control shadow enable */ + uint16_t : 1; + __IO uint16_t CCUC : 1; /*!< [2..2] Commutation control shadow register update control */ + __IO uint16_t DMAS : 1; /*!< [3..3] DMA request source selection */ + __IO uint16_t MMC : 3; /*!< [6..4] Master mode control */ + __IO uint16_t TI0S : 1; /*!< [7..7] Channel 0 trigger input selection */ + __IO uint16_t ISO0 : 1; /*!< [8..8] Idle state of channel 0 output */ + __IO uint16_t ISO0N : 1; /*!< [9..9] Idle state of channel 0 complementary output */ + __IO uint16_t ISO1 : 1; /*!< [10..10] Idle state of channel 1 output */ + __IO uint16_t ISO1N : 1; /*!< [11..11] Idle state of channel 1 complementary output */ + __IO uint16_t ISO2 : 1; /*!< [12..12] Idle state of channel 2 output */ + __IO uint16_t ISO2N : 1; /*!< [13..13] Idle state of channel 2 complementary output */ + __IO uint16_t ISO3 : 1; /*!< [14..14] Idle state of channel 3 output */ + uint16_t : 1; + } CTL1_b; + } ; + __I uint16_t RESERVED1; + + union { + __IO uint16_t SMCFG; /*!< (@ 0x00000008) slave mode configuration register */ + + struct { + __IO uint16_t SMC : 3; /*!< [2..0] Slave mode selection */ + uint16_t : 1; + __IO uint16_t TRGS : 3; /*!< [6..4] Trigger selection */ + __IO uint16_t MSM : 1; /*!< [7..7] Master/Slave mode */ + __IO uint16_t ETFC : 4; /*!< [11..8] External trigger filter control */ + __IO uint16_t ETPSC : 2; /*!< [13..12] External trigger prescaler */ + __IO uint16_t SMC1 : 1; /*!< [14..14] Part of SMC for enable External clock mode1 */ + __IO uint16_t ETP : 1; /*!< [15..15] External trigger polarity */ + } SMCFG_b; + } ; + __I uint16_t RESERVED2; + + union { + __IO uint16_t DMAINTEN; /*!< (@ 0x0000000C) DMA/Interrupt enable register */ + + struct { + __IO uint16_t UPIE : 1; /*!< [0..0] Update interrupt enable */ + __IO uint16_t CH0IE : 1; /*!< [1..1] Channel 0 capture/compare interrupt enable */ + __IO uint16_t CH1IE : 1; /*!< [2..2] Channel 1 capture/compare interrupt enable */ + __IO uint16_t CH2IE : 1; /*!< [3..3] Channel 2 capture/compare interrupt enable */ + __IO uint16_t CH3IE : 1; /*!< [4..4] Channel 3 capture/compare interrupt enable */ + __IO uint16_t CMTIE : 1; /*!< [5..5] commutation interrupt enable */ + __IO uint16_t TRGIE : 1; /*!< [6..6] Trigger interrupt enable */ + __IO uint16_t BRKIE : 1; /*!< [7..7] Break interrupt enable */ + __IO uint16_t UPDEN : 1; /*!< [8..8] Update DMA request enable */ + __IO uint16_t CH0DEN : 1; /*!< [9..9] Channel 0 capture/compare DMA request enable */ + __IO uint16_t CH1DEN : 1; /*!< [10..10] Channel 1 capture/compare DMA request enable */ + __IO uint16_t CH2DEN : 1; /*!< [11..11] Channel 2 capture/compare DMA request enable */ + __IO uint16_t CH3DEN : 1; /*!< [12..12] Channel 3 capture/compare DMA request enable */ + __IO uint16_t CMTDEN : 1; /*!< [13..13] Commutation DMA request enable */ + __IO uint16_t TRGDEN : 1; /*!< [14..14] Trigger DMA request enable */ + uint16_t : 1; + } DMAINTEN_b; + } ; + __I uint16_t RESERVED3; + + union { + __IO uint16_t INTF; /*!< (@ 0x00000010) Interrupt flag register */ + + struct { + __IO uint16_t UPIF : 1; /*!< [0..0] Update interrupt flag */ + __IO uint16_t CH0IF : 1; /*!< [1..1] Channel 0 capture/compare interrupt flag */ + __IO uint16_t CH1IF : 1; /*!< [2..2] Channel 1 capture/compare interrupt flag */ + __IO uint16_t CH2IF : 1; /*!< [3..3] Channel 2 capture/compare interrupt flag */ + __IO uint16_t CH3IF : 1; /*!< [4..4] Channel 3 capture/compare interrupt flag */ + __IO uint16_t CMTIF : 1; /*!< [5..5] Channel commutation interrupt flag */ + __IO uint16_t TRGIF : 1; /*!< [6..6] Trigger interrupt flag */ + __IO uint16_t BRKIF : 1; /*!< [7..7] Break interrupt flag */ + uint16_t : 1; + __IO uint16_t CH0OF : 1; /*!< [9..9] Channel 0 over capture flag */ + __IO uint16_t CH1OF : 1; /*!< [10..10] Channel 1 over capture flag */ + __IO uint16_t CH2OF : 1; /*!< [11..11] Channel 2 over capture flag */ + __IO uint16_t CH3OF : 1; /*!< [12..12] Channel 3 over capture flag */ + uint16_t : 3; + } INTF_b; + } ; + __I uint16_t RESERVED4; + + union { + __O uint16_t SWEVG; /*!< (@ 0x00000014) Software event generation register */ + + struct { + __O uint16_t UPG : 1; /*!< [0..0] Update event generation */ + __O uint16_t CH0G : 1; /*!< [1..1] Channel 0 capture or compare event generation */ + __O uint16_t CH1G : 1; /*!< [2..2] Channel 1 capture or compare event generation */ + __O uint16_t CH2G : 1; /*!< [3..3] Channel 2 capture or compare event generation */ + __O uint16_t CH3G : 1; /*!< [4..4] Channel 3 capture or compare event generation */ + __O uint16_t CMTG : 1; /*!< [5..5] Channel commutation event generation */ + __O uint16_t TRGG : 1; /*!< [6..6] Trigger event generation */ + __O uint16_t BRKG : 1; /*!< [7..7] Break event generation */ + uint16_t : 8; + } SWEVG_b; + } ; + __I uint16_t RESERVED5; + + union { + union { + __IO uint16_t CHCTL0_Output; /*!< (@ 0x00000018) Channel control register 0 (output mode) */ + + struct { + __IO uint16_t CH0MS : 2; /*!< [1..0] Channel 0 I/O mode selection */ + __IO uint16_t CH0COMFEN : 1; /*!< [2..2] Channel 0 output compare fast enable */ + __IO uint16_t CH0COMSEN : 1; /*!< [3..3] Channel 0 compare output shadow enable */ + __IO uint16_t CH0COMCTL : 3; /*!< [6..4] Channel 0 compare output control */ + __IO uint16_t CH0COMCEN : 1; /*!< [7..7] Channel 0 output compare clear enable */ + __IO uint16_t CH1MS : 2; /*!< [9..8] Channel 1 mode selection */ + __IO uint16_t CH1COMFEN : 1; /*!< [10..10] Channel 1 output compare fast enable */ + __IO uint16_t CH1COMSEN : 1; /*!< [11..11] Channel 1 output compare shadow enable */ + __IO uint16_t CH1COMCTL : 3; /*!< [14..12] Channel 1 compare output control */ + __IO uint16_t CH1COMCEN : 1; /*!< [15..15] Channel 1 output compare clear enable */ + } CHCTL0_Output_b; + } ; + + union { + __IO uint16_t CHCTL0_Input; /*!< (@ 0x00000018) Channel control register 0 (input mode) */ + + struct { + __IO uint16_t CH0MS : 2; /*!< [1..0] Channel 0 mode selection */ + __IO uint16_t CH0CAPPSC : 2; /*!< [3..2] Channel 0 input capture prescaler */ + __IO uint16_t CH0CAPFLT : 4; /*!< [7..4] Channel 0 input capture filter control */ + __IO uint16_t CH1MS : 2; /*!< [9..8] Channel 1 mode selection */ + __IO uint16_t CH1CAPPSC : 2; /*!< [11..10] Channel 1 input capture prescaler */ + __IO uint16_t CH1CAPFLT : 4; /*!< [15..12] Channel 1 input capture filter control */ + } CHCTL0_Input_b; + } ; + }; + __I uint16_t RESERVED6; + + union { + union { + __IO uint16_t CHCTL1_Output; /*!< (@ 0x0000001C) Channel control register 1 (output mode) */ + + struct { + __IO uint16_t CH2MS : 2; /*!< [1..0] Channel 2 I/O mode selection */ + __IO uint16_t CH2COMFEN : 1; /*!< [2..2] Channel 2 output compare fast enable */ + __IO uint16_t CH2COMSEN : 1; /*!< [3..3] Channel 2 compare output shadow enable */ + __IO uint16_t CH2COMCTL : 3; /*!< [6..4] Channel 2 compare output control */ + __IO uint16_t CH2COMCEN : 1; /*!< [7..7] Channel 2 output compare clear enable */ + __IO uint16_t CH3MS : 2; /*!< [9..8] Channel 3 mode selection */ + __IO uint16_t CH3COMFEN : 1; /*!< [10..10] Channel 3 output compare fast enable */ + __IO uint16_t CH3COMSEN : 1; /*!< [11..11] Channel 3 output compare shadow enable */ + __IO uint16_t CH3COMCTL : 3; /*!< [14..12] Channel 3 compare output control */ + __IO uint16_t CH3COMCEN : 1; /*!< [15..15] Channel 3 output compare clear enable */ + } CHCTL1_Output_b; + } ; + + union { + __IO uint16_t CHCTL1_Input; /*!< (@ 0x0000001C) Channel control register 1 (input mode) */ + + struct { + __IO uint16_t CH2MS : 2; /*!< [1..0] Channel 2 mode selection */ + __IO uint16_t CH2CAPPSC : 2; /*!< [3..2] Channel 2 input capture prescaler */ + __IO uint16_t CH2CAPFLT : 4; /*!< [7..4] Channel 2 input capture filter control */ + __IO uint16_t CH3MS : 2; /*!< [9..8] Channel 3 mode selection */ + __IO uint16_t CH3CAPPSC : 2; /*!< [11..10] Channel 3 input capture prescaler */ + __IO uint16_t CH3CAPFLT : 4; /*!< [15..12] Channel 3 input capture filter control */ + } CHCTL1_Input_b; + } ; + }; + __I uint16_t RESERVED7; + + union { + __IO uint16_t CHCTL2; /*!< (@ 0x00000020) Channel control register 2 */ + + struct { + __IO uint16_t CH0EN : 1; /*!< [0..0] Channel 0 capture/compare function enable */ + __IO uint16_t CH0P : 1; /*!< [1..1] Channel 0 capture/compare function polarity */ + __IO uint16_t CH0NEN : 1; /*!< [2..2] Channel 0 complementary output enable */ + __IO uint16_t CH0NP : 1; /*!< [3..3] Channel 0 complementary output polarity */ + __IO uint16_t CH1EN : 1; /*!< [4..4] Channel 1 capture/compare function enable */ + __IO uint16_t CH1P : 1; /*!< [5..5] Channel 1 capture/compare function polarity */ + __IO uint16_t CH1NEN : 1; /*!< [6..6] Channel 1 complementary output enable */ + __IO uint16_t CH1NP : 1; /*!< [7..7] Channel 1 complementary output polarity */ + __IO uint16_t CH2EN : 1; /*!< [8..8] Channel 2 capture/compare function enable */ + __IO uint16_t CH2P : 1; /*!< [9..9] Channel 2 capture/compare function polarity */ + __IO uint16_t CH2NEN : 1; /*!< [10..10] Channel 2 complementary output enable */ + __IO uint16_t CH2NP : 1; /*!< [11..11] Channel 2 complementary output polarity */ + __IO uint16_t CH3EN : 1; /*!< [12..12] Channel 3 capture/compare function enable */ + __IO uint16_t CH3P : 1; /*!< [13..13] Channel 3 capture/compare function polarity */ + uint16_t : 2; + } CHCTL2_b; + } ; + __I uint16_t RESERVED8; + + union { + __IO uint16_t CNT; /*!< (@ 0x00000024) counter */ + + struct { + __IO uint16_t CNT : 16; /*!< [15..0] current counter value */ + } CNT_b; + } ; + __I uint16_t RESERVED9; + + union { + __IO uint16_t PSC; /*!< (@ 0x00000028) prescaler */ + + struct { + __IO uint16_t PSC : 16; /*!< [15..0] Prescaler value of the counter clock */ + } PSC_b; + } ; + __I uint16_t RESERVED10; + + union { + __IO uint16_t CAR; /*!< (@ 0x0000002C) Counter auto reload register */ + + struct { + __IO uint16_t CARL : 16; /*!< [15..0] Counter auto reload value */ + } CAR_b; + } ; + __I uint16_t RESERVED11; + + union { + __IO uint16_t CREP; /*!< (@ 0x00000030) Counter repetition register */ + + struct { + __IO uint16_t CREP : 8; /*!< [7..0] Counter repetition value */ + uint16_t : 8; + } CREP_b; + } ; + __I uint16_t RESERVED12; + + union { + __IO uint16_t CH0CV; /*!< (@ 0x00000034) Channel 0 capture/compare value register */ + + struct { + __IO uint16_t CH0VAL : 16; /*!< [15..0] Capture or compare value of channel0 */ + } CH0CV_b; + } ; + __I uint16_t RESERVED13; + + union { + __IO uint16_t CH1CV; /*!< (@ 0x00000038) Channel 1 capture/compare value register */ + + struct { + __IO uint16_t CH1VAL : 16; /*!< [15..0] Capture or compare value of channel1 */ + } CH1CV_b; + } ; + __I uint16_t RESERVED14; + + union { + __IO uint16_t CH2CV; /*!< (@ 0x0000003C) Channel 2 capture/compare value register */ + + struct { + __IO uint16_t CH2VAL : 16; /*!< [15..0] Capture or compare value of channel 2 */ + } CH2CV_b; + } ; + __I uint16_t RESERVED15; + + union { + __IO uint16_t CH3CV; /*!< (@ 0x00000040) Channel 3 capture/compare value register */ + + struct { + __IO uint16_t CH3VAL : 16; /*!< [15..0] Capture or compare value of channel 3 */ + } CH3CV_b; + } ; + __I uint16_t RESERVED16; + + union { + __IO uint16_t CCHP; /*!< (@ 0x00000044) channel complementary protection register */ + + struct { + __IO uint16_t DTCFG : 8; /*!< [7..0] Dead time configure */ + __IO uint16_t PROT : 2; /*!< [9..8] Complementary register protect control */ + __IO uint16_t IOS : 1; /*!< [10..10] Idle mode off-state configure */ + __IO uint16_t ROS : 1; /*!< [11..11] Run mode off-state configure */ + __IO uint16_t BRKEN : 1; /*!< [12..12] Break enable */ + __IO uint16_t BRKP : 1; /*!< [13..13] Break polarity */ + __IO uint16_t OAEN : 1; /*!< [14..14] Output automatic enable */ + __IO uint16_t POEN : 1; /*!< [15..15] Primary output enable */ + } CCHP_b; + } ; + __I uint16_t RESERVED17; + + union { + __IO uint16_t DMACFG; /*!< (@ 0x00000048) DMA configuration register */ + + struct { + __IO uint16_t DMATA : 5; /*!< [4..0] DMA transfer access start address */ + uint16_t : 3; + __IO uint16_t DMATC : 5; /*!< [12..8] DMA transfer count */ + uint16_t : 3; + } DMACFG_b; + } ; + __I uint16_t RESERVED18; + + union { + __IO uint16_t DMATB; /*!< (@ 0x0000004C) DMA transfer buffer register */ + + struct { + __IO uint16_t DMATB : 16; /*!< [15..0] DMA transfer buffer */ + } DMATB_b; + } ; +} TIMER_Type; /*!< Size = 78 (0x4e) */ + + + +/* =========================================================================================================================== */ +/* ================ USART0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Universal synchronous asynchronous receiver + transmitter (USART0) + */ + +typedef struct { /*!< (@ 0x40013800) USART0 Structure */ + + union { + __IO uint32_t STAT; /*!< (@ 0x00000000) Status register */ + + struct { + __I uint32_t PERR : 1; /*!< [0..0] Parity error flag */ + __I uint32_t FERR : 1; /*!< [1..1] Frame error flag */ + __I uint32_t NERR : 1; /*!< [2..2] Noise error flag */ + __I uint32_t ORERR : 1; /*!< [3..3] Overrun error */ + __I uint32_t IDLEF : 1; /*!< [4..4] IDLE frame detected flag */ + __IO uint32_t RBNE : 1; /*!< [5..5] Read data buffer not empty */ + __IO uint32_t TC : 1; /*!< [6..6] Transmission complete */ + __I uint32_t TBE : 1; /*!< [7..7] Transmit data buffer empty */ + __IO uint32_t LBDF : 1; /*!< [8..8] LIN break detection flag */ + __IO uint32_t CTSF : 1; /*!< [9..9] CTS change flag */ + uint32_t : 22; + } STAT_b; + } ; + + union { + __IO uint32_t DATA; /*!< (@ 0x00000004) Data register */ + + struct { + __IO uint32_t DATA : 9; /*!< [8..0] Transmit or read data value */ + uint32_t : 23; + } DATA_b; + } ; + + union { + __IO uint32_t BAUD; /*!< (@ 0x00000008) Baud rate register */ + + struct { + __IO uint32_t FRADIV : 4; /*!< [3..0] Fraction part of baud-rate divider */ + __IO uint32_t INTDIV : 12; /*!< [15..4] Integer part of baud-rate divider */ + uint32_t : 16; + } BAUD_b; + } ; + + union { + __IO uint32_t CTL0; /*!< (@ 0x0000000C) Control register 0 */ + + struct { + __IO uint32_t SBKCMD : 1; /*!< [0..0] Send break command */ + __IO uint32_t RWU : 1; /*!< [1..1] Receiver wakeup from mute mode */ + __IO uint32_t REN : 1; /*!< [2..2] Receiver enable */ + __IO uint32_t TEN : 1; /*!< [3..3] Transmitter enable */ + __IO uint32_t IDLEIE : 1; /*!< [4..4] IDLE line detected interrupt enable */ + __IO uint32_t RBNEIE : 1; /*!< [5..5] Read data buffer not empty interrupt and overrun error + interrupt enable */ + __IO uint32_t TCIE : 1; /*!< [6..6] Transmission complete interrupt enable */ + __IO uint32_t TBEIE : 1; /*!< [7..7] Transmitter buffer empty interrupt enable */ + __IO uint32_t PERRIE : 1; /*!< [8..8] Parity error interrupt enable */ + __IO uint32_t PM : 1; /*!< [9..9] Parity mode */ + __IO uint32_t PCEN : 1; /*!< [10..10] Parity check function enable */ + __IO uint32_t WM : 1; /*!< [11..11] Wakeup method in mute mode */ + __IO uint32_t WL : 1; /*!< [12..12] Word length */ + __IO uint32_t UEN : 1; /*!< [13..13] USART enable */ + uint32_t : 18; + } CTL0_b; + } ; + + union { + __IO uint32_t CTL1; /*!< (@ 0x00000010) Control register 1 */ + + struct { + __IO uint32_t ADDR : 4; /*!< [3..0] Address of the USART */ + uint32_t : 1; + __IO uint32_t LBLEN : 1; /*!< [5..5] LIN break frame length */ + __IO uint32_t LBDIE : 1; /*!< [6..6] LIN break detection interrupt enable */ + uint32_t : 1; + __IO uint32_t CLEN : 1; /*!< [8..8] CK Length */ + __IO uint32_t CPH : 1; /*!< [9..9] Clock phase */ + __IO uint32_t CPL : 1; /*!< [10..10] Clock polarity */ + __IO uint32_t CKEN : 1; /*!< [11..11] CK pin enable */ + __IO uint32_t STB : 2; /*!< [13..12] STOP bits length */ + __IO uint32_t LMEN : 1; /*!< [14..14] LIN mode enable */ + uint32_t : 17; + } CTL1_b; + } ; + + union { + __IO uint32_t CTL2; /*!< (@ 0x00000014) Control register 2 */ + + struct { + __IO uint32_t ERRIE : 1; /*!< [0..0] Error interrupt enable */ + __IO uint32_t IREN : 1; /*!< [1..1] IrDA mode enable */ + __IO uint32_t IRLP : 1; /*!< [2..2] IrDA low-power */ + __IO uint32_t HDEN : 1; /*!< [3..3] Half-duplex selection */ + __IO uint32_t NKEN : 1; /*!< [4..4] Smartcard NACK enable */ + __IO uint32_t SCEN : 1; /*!< [5..5] Smartcard mode enable */ + __IO uint32_t DENR : 1; /*!< [6..6] DMA request enable for reception */ + __IO uint32_t DENT : 1; /*!< [7..7] DMA request enable for transmission */ + __IO uint32_t RTSEN : 1; /*!< [8..8] RTS enable */ + __IO uint32_t CTSEN : 1; /*!< [9..9] CTS enable */ + __IO uint32_t CTSIE : 1; /*!< [10..10] CTS interrupt enable */ + uint32_t : 21; + } CTL2_b; + } ; + + union { + __IO uint32_t GP; /*!< (@ 0x00000018) Guard time and prescaler register */ + + struct { + __IO uint32_t PSC : 8; /*!< [7..0] Prescaler value */ + __IO uint32_t GUAT : 8; /*!< [15..8] Guard time value in Smartcard mode */ + uint32_t : 16; + } GP_b; + } ; +} USART_Type; /*!< Size = 28 (0x1c) */ + + + +/* =========================================================================================================================== */ +/* ================ UART3 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Universal asynchronous receiver + transmitter (UART3) + */ + +typedef struct { /*!< (@ 0x40004C00) UART3 Structure */ + + union { + __IO uint32_t STAT; /*!< (@ 0x00000000) Status register */ + + struct { + __I uint32_t PERR : 1; /*!< [0..0] Parity error flag */ + __I uint32_t FERR : 1; /*!< [1..1] Frame error flag */ + __I uint32_t NERR : 1; /*!< [2..2] Noise error flag */ + __I uint32_t ORERR : 1; /*!< [3..3] Overrun error */ + __I uint32_t IDLEF : 1; /*!< [4..4] IDLE frame detected flag */ + __IO uint32_t RBNE : 1; /*!< [5..5] Read data buffer not empty */ + __IO uint32_t TC : 1; /*!< [6..6] Transmission complete */ + __I uint32_t TBE : 1; /*!< [7..7] Transmit data buffer empty */ + __IO uint32_t LBDF : 1; /*!< [8..8] LIN break detection flag */ + uint32_t : 23; + } STAT_b; + } ; + + union { + __IO uint32_t DATA; /*!< (@ 0x00000004) Data register */ + + struct { + __IO uint32_t DATA : 9; /*!< [8..0] Transmit or read data value */ + uint32_t : 23; + } DATA_b; + } ; + + union { + __IO uint32_t BAUD; /*!< (@ 0x00000008) Baud rate register */ + + struct { + __IO uint32_t FRADIV : 4; /*!< [3..0] Fraction part of baud-rate divider */ + __IO uint32_t INTDIV : 12; /*!< [15..4] Integer part of baud-rate divider */ + uint32_t : 16; + } BAUD_b; + } ; + + union { + __IO uint32_t CTL0; /*!< (@ 0x0000000C) Control register 0 */ + + struct { + __IO uint32_t SBKCMD : 1; /*!< [0..0] Send break command */ + __IO uint32_t RWU : 1; /*!< [1..1] Receiver wakeup from mute mode */ + __IO uint32_t REN : 1; /*!< [2..2] Receiver enable */ + __IO uint32_t TEN : 1; /*!< [3..3] Transmitter enable */ + __IO uint32_t IDLEIE : 1; /*!< [4..4] IDLE line detected interrupt enable */ + __IO uint32_t RBNEIE : 1; /*!< [5..5] Read data buffer not empty interrupt and overrun error + interrupt enable */ + __IO uint32_t TCIE : 1; /*!< [6..6] Transmission complete interrupt enable */ + __IO uint32_t TBEIE : 1; /*!< [7..7] Transmitter buffer empty interrupt enable */ + __IO uint32_t PERRIE : 1; /*!< [8..8] Parity error interrupt enable */ + __IO uint32_t PM : 1; /*!< [9..9] Parity mode */ + __IO uint32_t PCEN : 1; /*!< [10..10] Parity check function enable */ + __IO uint32_t WM : 1; /*!< [11..11] Wakeup method in mute mode */ + __IO uint32_t WL : 1; /*!< [12..12] Word length */ + __IO uint32_t UEN : 1; /*!< [13..13] USART enable */ + uint32_t : 18; + } CTL0_b; + } ; + + union { + __IO uint32_t CTL1; /*!< (@ 0x00000010) Control register 1 */ + + struct { + __IO uint32_t ADDR : 4; /*!< [3..0] Address of the USART */ + uint32_t : 1; + __IO uint32_t LBLEN : 1; /*!< [5..5] LIN break frame length */ + __IO uint32_t LBDIE : 1; /*!< [6..6] LIN break detection interrupt enable */ + uint32_t : 5; + __IO uint32_t STB : 2; /*!< [13..12] STOP bits length */ + __IO uint32_t LMEN : 1; /*!< [14..14] LIN mode enable */ + uint32_t : 17; + } CTL1_b; + } ; + + union { + __IO uint32_t CTL2; /*!< (@ 0x00000014) Control register 2 */ + + struct { + __IO uint32_t ERRIE : 1; /*!< [0..0] Error interrupt enable */ + __IO uint32_t IREN : 1; /*!< [1..1] IrDA mode enable */ + __IO uint32_t IRLP : 1; /*!< [2..2] IrDA low-power */ + __IO uint32_t HDEN : 1; /*!< [3..3] Half-duplex selection */ + uint32_t : 2; + __IO uint32_t DENR : 1; /*!< [6..6] DMA request enable for reception */ + __IO uint32_t DENT : 1; /*!< [7..7] DMA request enable for transmission */ + uint32_t : 24; + } CTL2_b; + } ; + + union { + __IO uint32_t GP; /*!< (@ 0x00000018) Guard time and prescaler register */ + + struct { + __IO uint32_t PSC : 8; /*!< [7..0] Prescaler value */ + uint32_t : 24; + } GP_b; + } ; +} UART_Type; /*!< Size = 28 (0x1c) */ + + + +/* =========================================================================================================================== */ +/* ================ USBFS_GLOBAL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief USB full speed global registers (USBFS_GLOBAL) + */ + +typedef struct { /*!< (@ 0x50000000) USBFS_GLOBAL Structure */ + + union { + __IO uint32_t GOTGCS; /*!< (@ 0x00000000) Global OTG control and status register (USBFS_GOTGCS) */ + + struct { + __I uint32_t SRPS : 1; /*!< [0..0] SRP success */ + __IO uint32_t SRPREQ : 1; /*!< [1..1] SRP request */ + uint32_t : 6; + __I uint32_t HNPS : 1; /*!< [8..8] Host success */ + __IO uint32_t HNPREQ : 1; /*!< [9..9] HNP request */ + __IO uint32_t HHNPEN : 1; /*!< [10..10] Host HNP enable */ + __IO uint32_t DHNPEN : 1; /*!< [11..11] Device HNP enabled */ + uint32_t : 4; + __I uint32_t IDPS : 1; /*!< [16..16] ID pin status */ + __I uint32_t DI : 1; /*!< [17..17] Debounce interval */ + __I uint32_t ASV : 1; /*!< [18..18] A-session valid */ + __I uint32_t BSV : 1; /*!< [19..19] B-session valid */ + uint32_t : 12; + } GOTGCS_b; + } ; + + union { + __IO uint32_t GOTGINTF; /*!< (@ 0x00000004) Global OTG interrupt flag register (USBFS_GOTGINTF) */ + + struct { + uint32_t : 2; + __IO uint32_t SESEND : 1; /*!< [2..2] Session end */ + uint32_t : 5; + __IO uint32_t SRPEND : 1; /*!< [8..8] Session request success status change */ + __IO uint32_t HNPEND : 1; /*!< [9..9] HNP end */ + uint32_t : 7; + __IO uint32_t HNPDET : 1; /*!< [17..17] Host negotiation request detected */ + __IO uint32_t ADTO : 1; /*!< [18..18] A-device timeout */ + __IO uint32_t DF : 1; /*!< [19..19] Debounce finish */ + uint32_t : 12; + } GOTGINTF_b; + } ; + + union { + __IO uint32_t GAHBCS; /*!< (@ 0x00000008) Global AHB control and status register (USBFS_GAHBCS) */ + + struct { + __IO uint32_t GINTEN : 1; /*!< [0..0] Global interrupt enable */ + uint32_t : 6; + __IO uint32_t TXFTH : 1; /*!< [7..7] Tx FIFO threshold */ + __IO uint32_t PTXFTH : 1; /*!< [8..8] Periodic Tx FIFO threshold */ + uint32_t : 23; + } GAHBCS_b; + } ; + + union { + __IO uint32_t GUSBCS; /*!< (@ 0x0000000C) Global USB control and status register (USBFS_GUSBCSR) */ + + struct { + __IO uint32_t TOC : 3; /*!< [2..0] Timeout calibration */ + uint32_t : 5; + __IO uint32_t SRPCEN : 1; /*!< [8..8] SRP capability enable */ + __IO uint32_t HNPCEN : 1; /*!< [9..9] HNP capability enable */ + __IO uint32_t UTT : 4; /*!< [13..10] USB turnaround time */ + uint32_t : 15; + __IO uint32_t FHM : 1; /*!< [29..29] Force host mode */ + __IO uint32_t FDM : 1; /*!< [30..30] Force device mode */ + uint32_t : 1; + } GUSBCS_b; + } ; + + union { + __IO uint32_t GRSTCTL; /*!< (@ 0x00000010) Global reset control register (USBFS_GRSTCTL) */ + + struct { + __IO uint32_t CSRST : 1; /*!< [0..0] Core soft reset */ + __IO uint32_t HCSRST : 1; /*!< [1..1] HCLK soft reset */ + __IO uint32_t HFCRST : 1; /*!< [2..2] Host frame counter reset */ + uint32_t : 1; + __IO uint32_t RXFF : 1; /*!< [4..4] RxFIFO flush */ + __IO uint32_t TXFF : 1; /*!< [5..5] TxFIFO flush */ + __IO uint32_t TXFNUM : 5; /*!< [10..6] TxFIFO number */ + uint32_t : 21; + } GRSTCTL_b; + } ; + + union { + __IO uint32_t GINTF; /*!< (@ 0x00000014) Global interrupt flag register (USBFS_GINTF) */ + + struct { + __I uint32_t COPM : 1; /*!< [0..0] Current operation mode */ + __IO uint32_t MFIF : 1; /*!< [1..1] Mode fault interrupt flag */ + __I uint32_t OTGIF : 1; /*!< [2..2] OTG interrupt flag */ + __IO uint32_t SOF : 1; /*!< [3..3] Start of frame */ + __I uint32_t RXFNEIF : 1; /*!< [4..4] RxFIFO non-empty interrupt flag */ + __I uint32_t NPTXFEIF : 1; /*!< [5..5] Non-periodic TxFIFO empty interrupt flag */ + __I uint32_t GNPINAK : 1; /*!< [6..6] Global Non-Periodic IN NAK effective */ + __I uint32_t GONAK : 1; /*!< [7..7] Global OUT NAK effective */ + uint32_t : 2; + __IO uint32_t ESP : 1; /*!< [10..10] Early suspend */ + __IO uint32_t SP : 1; /*!< [11..11] USB suspend */ + __IO uint32_t RST : 1; /*!< [12..12] USB reset */ + __IO uint32_t ENUMF : 1; /*!< [13..13] Enumeration finished */ + __IO uint32_t ISOOPDIF : 1; /*!< [14..14] Isochronous OUT packet dropped interrupt */ + __IO uint32_t EOPFIF : 1; /*!< [15..15] End of periodic frame interrupt flag */ + uint32_t : 2; + __I uint32_t IEPIF : 1; /*!< [18..18] IN endpoint interrupt flag */ + __I uint32_t OEPIF : 1; /*!< [19..19] OUT endpoint interrupt flag */ + __IO uint32_t ISOINCIF : 1; /*!< [20..20] Isochronous IN transfer Not Complete Interrupt Flag */ + __IO uint32_t PXNCIF_ISOONCIF : 1; /*!< [21..21] periodic transfer not complete interrupt flag(Host + mode)/isochronous OUT transfer not complete interrupt flag(Device + mode) */ + uint32_t : 2; + __I uint32_t HPIF : 1; /*!< [24..24] Host port interrupt flag */ + __I uint32_t HCIF : 1; /*!< [25..25] Host channels interrupt flag */ + __I uint32_t PTXFEIF : 1; /*!< [26..26] Periodic TxFIFO empty interrupt flag */ + uint32_t : 1; + __IO uint32_t IDPSC : 1; /*!< [28..28] ID pin status change */ + __IO uint32_t DISCIF : 1; /*!< [29..29] Disconnect interrupt flag */ + __IO uint32_t SESIF : 1; /*!< [30..30] Session interrupt flag */ + __IO uint32_t WKUPIF : 1; /*!< [31..31] Wakeup interrupt flag */ + } GINTF_b; + } ; + + union { + __IO uint32_t GINTEN; /*!< (@ 0x00000018) Global interrupt enable register (USBFS_GINTEN) */ + + struct { + uint32_t : 1; + __IO uint32_t MFIE : 1; /*!< [1..1] Mode fault interrupt enable */ + __IO uint32_t OTGIE : 1; /*!< [2..2] OTG interrupt enable */ + __IO uint32_t SOFIE : 1; /*!< [3..3] Start of frame interrupt enable */ + __IO uint32_t RXFNEIE : 1; /*!< [4..4] Receive FIFO non-empty interrupt enable */ + __IO uint32_t NPTXFEIE : 1; /*!< [5..5] Non-periodic TxFIFO empty interrupt enable */ + __IO uint32_t GNPINAKIE : 1; /*!< [6..6] Global non-periodic IN NAK effective interrupt enable */ + __IO uint32_t GONAKIE : 1; /*!< [7..7] Global OUT NAK effective interrupt enable */ + uint32_t : 2; + __IO uint32_t ESPIE : 1; /*!< [10..10] Early suspend interrupt enable */ + __IO uint32_t SPIE : 1; /*!< [11..11] USB suspend interrupt enable */ + __IO uint32_t RSTIE : 1; /*!< [12..12] USB reset interrupt enable */ + __IO uint32_t ENUMFIE : 1; /*!< [13..13] Enumeration finish interrupt enable */ + __IO uint32_t ISOOPDIE : 1; /*!< [14..14] Isochronous OUT packet dropped interrupt enable */ + __IO uint32_t EOPFIE : 1; /*!< [15..15] End of periodic frame interrupt enable */ + uint32_t : 2; + __IO uint32_t IEPIE : 1; /*!< [18..18] IN endpoints interrupt enable */ + __IO uint32_t OEPIE : 1; /*!< [19..19] OUT endpoints interrupt enable */ + __IO uint32_t ISOINCIE : 1; /*!< [20..20] isochronous IN transfer not complete interrupt enable */ + __IO uint32_t PXNCIE_ISOONCIE : 1; /*!< [21..21] periodic transfer not compelete Interrupt enable(Host + mode)/isochronous OUT transfer not complete interrupt enable(Device + mode) */ + uint32_t : 2; + __I uint32_t HPIE : 1; /*!< [24..24] Host port interrupt enable */ + __IO uint32_t HCIE : 1; /*!< [25..25] Host channels interrupt enable */ + __IO uint32_t PTXFEIE : 1; /*!< [26..26] Periodic TxFIFO empty interrupt enable */ + uint32_t : 1; + __IO uint32_t IDPSCIE : 1; /*!< [28..28] ID pin status change interrupt enable */ + __IO uint32_t DISCIE : 1; /*!< [29..29] Disconnect interrupt enable */ + __IO uint32_t SESIE : 1; /*!< [30..30] Session interrupt enable */ + __IO uint32_t WKUPIE : 1; /*!< [31..31] Wakeup interrupt enable */ + } GINTEN_b; + } ; + + union { + union { + __I uint32_t GRSTATR_Device; /*!< (@ 0x0000001C) Global Receive status read(Device mode) */ + + struct { + __I uint32_t EPNUM : 4; /*!< [3..0] Endpoint number */ + __I uint32_t BCOUNT : 11; /*!< [14..4] Byte count */ + __I uint32_t DPID : 2; /*!< [16..15] Data PID */ + __I uint32_t RPCKST : 4; /*!< [20..17] Recieve packet status */ + uint32_t : 11; + } GRSTATR_Device_b; + } ; + + union { + __I uint32_t GRSTATR_Host; /*!< (@ 0x0000001C) Global Receive status read(Host mode) */ + + struct { + __I uint32_t CNUM : 4; /*!< [3..0] Channel number */ + __I uint32_t BCOUNT : 11; /*!< [14..4] Byte count */ + __I uint32_t DPID : 2; /*!< [16..15] Data PID */ + __I uint32_t RPCKST : 4; /*!< [20..17] Reivece packet status */ + uint32_t : 11; + } GRSTATR_Host_b; + } ; + }; + + union { + union { + __I uint32_t GRSTATP_Device; /*!< (@ 0x00000020) Global Receive status pop(Device mode) */ + + struct { + __I uint32_t EPNUM : 4; /*!< [3..0] Endpoint number */ + __I uint32_t BCOUNT : 11; /*!< [14..4] Byte count */ + __I uint32_t DPID : 2; /*!< [16..15] Data PID */ + __I uint32_t RPCKST : 4; /*!< [20..17] Recieve packet status */ + uint32_t : 11; + } GRSTATP_Device_b; + } ; + + union { + __I uint32_t GRSTATP_Host; /*!< (@ 0x00000020) Global Receive status pop(Host mode) */ + + struct { + __I uint32_t CNUM : 4; /*!< [3..0] Channel number */ + __I uint32_t BCOUNT : 11; /*!< [14..4] Byte count */ + __I uint32_t DPID : 2; /*!< [16..15] Data PID */ + __I uint32_t RPCKST : 4; /*!< [20..17] Reivece packet status */ + uint32_t : 11; + } GRSTATP_Host_b; + } ; + }; + + union { + __IO uint32_t GRFLEN; /*!< (@ 0x00000024) Global Receive FIFO size register (USBFS_GRFLEN) */ + + struct { + __IO uint32_t RXFD : 16; /*!< [15..0] Rx FIFO depth */ + uint32_t : 16; + } GRFLEN_b; + } ; + + union { + union { + __IO uint32_t HNPTFLEN; /*!< (@ 0x00000028) Host non-periodic transmit FIFO length register + (Host mode) */ + + struct { + __IO uint32_t HNPTXRSAR : 16; /*!< [15..0] host non-periodic transmit Tx RAM start address */ + __IO uint32_t HNPTXFD : 16; /*!< [31..16] host non-periodic TxFIFO depth */ + } HNPTFLEN_b; + } ; + + union { + __IO uint32_t DIEP0TFLEN; /*!< (@ 0x00000028) Device IN endpoint 0 transmit FIFO length (Device + mode) */ + + struct { + __IO uint32_t IEP0TXRSAR : 16; /*!< [15..0] in endpoint 0 Tx RAM start address */ + __IO uint32_t IEP0TXFD : 16; /*!< [31..16] in endpoint 0 Tx FIFO depth */ + } DIEP0TFLEN_b; + } ; + }; + + union { + __I uint32_t HNPTFQSTAT; /*!< (@ 0x0000002C) Host non-periodic transmit FIFO/queue status + register (HNPTFQSTAT) */ + + struct { + __I uint32_t NPTXFS : 16; /*!< [15..0] Non-periodic TxFIFO space */ + __I uint32_t NPTXRQS : 8; /*!< [23..16] Non-periodic transmit request queue space */ + __I uint32_t NPTXRQTOP : 7; /*!< [30..24] Top of the non-periodic transmit request queue */ + uint32_t : 1; + } HNPTFQSTAT_b; + } ; + __I uint32_t RESERVED[2]; + + union { + __IO uint32_t GCCFG; /*!< (@ 0x00000038) Global core configuration register (USBFS_GCCFG) */ + + struct { + uint32_t : 16; + __IO uint32_t PWRON : 1; /*!< [16..16] Power on */ + uint32_t : 1; + __IO uint32_t VBUSACEN : 1; /*!< [18..18] The VBUS A-device Comparer enable */ + __IO uint32_t VBUSBCEN : 1; /*!< [19..19] The VBUS B-device Comparer enable */ + __IO uint32_t SOFOEN : 1; /*!< [20..20] SOF output enable */ + __IO uint32_t VBUSIG : 1; /*!< [21..21] VBUS ignored */ + uint32_t : 10; + } GCCFG_b; + } ; + + union { + __IO uint32_t CID; /*!< (@ 0x0000003C) core ID register */ + + struct { + __IO uint32_t CID : 32; /*!< [31..0] Core ID */ + } CID_b; + } ; + __I uint32_t RESERVED1[48]; + + union { + __IO uint32_t HPTFLEN; /*!< (@ 0x00000100) Host periodic transmit FIFO length register (HPTFLEN) */ + + struct { + __IO uint32_t HPTXFSAR : 16; /*!< [15..0] Host periodic TxFIFO start address */ + __IO uint32_t HPTXFD : 16; /*!< [31..16] Host periodic TxFIFO depth */ + } HPTFLEN_b; + } ; + + union { + __IO uint32_t DIEP1TFLEN; /*!< (@ 0x00000104) device IN endpoint transmit FIFO size register + (DIEP1TFLEN) */ + + struct { + __IO uint32_t IEPTXRSAR : 16; /*!< [15..0] IN endpoint FIFO transmit RAM start address */ + __IO uint32_t IEPTXFD : 16; /*!< [31..16] IN endpoint TxFIFO depth */ + } DIEP1TFLEN_b; + } ; + + union { + __IO uint32_t DIEP2TFLEN; /*!< (@ 0x00000108) device IN endpoint transmit FIFO size register + (DIEP2TFLEN) */ + + struct { + __IO uint32_t IEPTXRSAR : 16; /*!< [15..0] IN endpoint FIFO transmit RAM start address */ + __IO uint32_t IEPTXFD : 16; /*!< [31..16] IN endpoint TxFIFO depth */ + } DIEP2TFLEN_b; + } ; + + union { + __IO uint32_t DIEP3TFLEN; /*!< (@ 0x0000010C) device IN endpoint transmit FIFO size register + (FS_DIEP3TXFLEN) */ + + struct { + __IO uint32_t IEPTXRSAR : 16; /*!< [15..0] IN endpoint FIFO4 transmit RAM start address */ + __IO uint32_t IEPTXFD : 16; /*!< [31..16] IN endpoint TxFIFO depth */ + } DIEP3TFLEN_b; + } ; +} USBFS_GLOBAL_Type; /*!< Size = 272 (0x110) */ + + + +/* =========================================================================================================================== */ +/* ================ USBFS_HOST ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief USB on the go full speed host (USBFS_HOST) + */ + +typedef struct { /*!< (@ 0x50000400) USBFS_HOST Structure */ + + union { + __IO uint32_t HCTL; /*!< (@ 0x00000000) host configuration register (HCTL) */ + + struct { + __IO uint32_t CLKSEL : 2; /*!< [1..0] clock select for USB clock */ + uint32_t : 30; + } HCTL_b; + } ; + + union { + __IO uint32_t HFT; /*!< (@ 0x00000004) Host frame interval register */ + + struct { + __IO uint32_t FRI : 16; /*!< [15..0] Frame interval */ + uint32_t : 16; + } HFT_b; + } ; + + union { + __I uint32_t HFINFR; /*!< (@ 0x00000008) FS host frame number/frame time remaining register + (HFINFR) */ + + struct { + __I uint32_t FRNUM : 16; /*!< [15..0] Frame number */ + __I uint32_t FRT : 16; /*!< [31..16] Frame remaining time */ + } HFINFR_b; + } ; + __I uint32_t RESERVED; + + union { + __IO uint32_t HPTFQSTAT; /*!< (@ 0x00000010) Host periodic transmit FIFO/queue status register + (HPTFQSTAT) */ + + struct { + __I uint32_t PTXFS : 16; /*!< [15..0] Periodic transmit data FIFO space available */ + __I uint32_t PTXREQS : 8; /*!< [23..16] Periodic transmit request queue space available */ + __I uint32_t PTXREQT : 8; /*!< [31..24] Top of the periodic transmit request queue */ + } HPTFQSTAT_b; + } ; + + union { + __I uint32_t HACHINT; /*!< (@ 0x00000014) Host all channels interrupt register */ + + struct { + __I uint32_t HACHINT : 8; /*!< [7..0] Host all channel interrupts */ + uint32_t : 24; + } HACHINT_b; + } ; + + union { + __IO uint32_t HACHINTEN; /*!< (@ 0x00000018) host all channels interrupt mask register */ + + struct { + __IO uint32_t CINTEN : 8; /*!< [7..0] Channel interrupt enable */ + uint32_t : 24; + } HACHINTEN_b; + } ; + __I uint32_t RESERVED1[9]; + + union { + __IO uint32_t HPCS; /*!< (@ 0x00000040) Host port control and status register (USBFS_HPCS) */ + + struct { + __I uint32_t PCST : 1; /*!< [0..0] Port connect status */ + __IO uint32_t PCD : 1; /*!< [1..1] Port connect detected */ + __IO uint32_t PE : 1; /*!< [2..2] Port enable */ + __IO uint32_t PEDC : 1; /*!< [3..3] Port enable/disable change */ + uint32_t : 2; + __IO uint32_t PREM : 1; /*!< [6..6] Port resume */ + __IO uint32_t PSP : 1; /*!< [7..7] Port suspend */ + __IO uint32_t PRST : 1; /*!< [8..8] Port reset */ + uint32_t : 1; + __I uint32_t PLST : 2; /*!< [11..10] Port line status */ + __IO uint32_t PP : 1; /*!< [12..12] Port power */ + uint32_t : 4; + __I uint32_t PS : 2; /*!< [18..17] Port speed */ + uint32_t : 13; + } HPCS_b; + } ; + __I uint32_t RESERVED2[47]; + + union { + __IO uint32_t HCH0CTL; /*!< (@ 0x00000100) host channel-0 characteristics register (HCH0CTL) */ + + struct { + __IO uint32_t MPL : 11; /*!< [10..0] Maximum packet size */ + __IO uint32_t EPNUM : 4; /*!< [14..11] Endpoint number */ + __IO uint32_t EPDIR : 1; /*!< [15..15] Endpoint direction */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< [17..17] Low-speed device */ + __IO uint32_t EPTYPE : 2; /*!< [19..18] Endpoint type */ + uint32_t : 2; + __IO uint32_t DAR : 7; /*!< [28..22] Device address */ + __IO uint32_t ODDFRM : 1; /*!< [29..29] Odd frame */ + __IO uint32_t CDIS : 1; /*!< [30..30] Channel disable */ + __IO uint32_t CEN : 1; /*!< [31..31] Channel enable */ + } HCH0CTL_b; + } ; + __I uint32_t RESERVED3; + + union { + __IO uint32_t HCH0INTF; /*!< (@ 0x00000108) host channel-0 interrupt register (USBFS_HCHxINTF) */ + + struct { + __IO uint32_t TF : 1; /*!< [0..0] Transfer finished */ + __IO uint32_t CH : 1; /*!< [1..1] Channel halted */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< [3..3] STALL response received interrupt */ + __IO uint32_t NAK : 1; /*!< [4..4] NAK response received interrupt */ + __IO uint32_t ACK : 1; /*!< [5..5] ACK response received/transmitted interrupt */ + uint32_t : 1; + __IO uint32_t USBER : 1; /*!< [7..7] USB bus error */ + __IO uint32_t BBER : 1; /*!< [8..8] Babble error */ + __IO uint32_t REQOVR : 1; /*!< [9..9] Request queue overrun */ + __IO uint32_t DTER : 1; /*!< [10..10] Data toggle error */ + uint32_t : 21; + } HCH0INTF_b; + } ; + + union { + __IO uint32_t HCH0INTEN; /*!< (@ 0x0000010C) host channel-0 interrupt enable register (HCH0INTEN) */ + + struct { + __IO uint32_t TFIE : 1; /*!< [0..0] Transfer completed interrupt enable */ + __IO uint32_t CHIE : 1; /*!< [1..1] Channel halted interrupt enable */ + uint32_t : 1; + __IO uint32_t STALLIE : 1; /*!< [3..3] STALL interrupt enable */ + __IO uint32_t NAKIE : 1; /*!< [4..4] NAK interrupt enable */ + __IO uint32_t ACKIE : 1; /*!< [5..5] ACK interrupt enable */ + uint32_t : 1; + __IO uint32_t USBERIE : 1; /*!< [7..7] USB bus error interrupt enable */ + __IO uint32_t BBERIE : 1; /*!< [8..8] Babble error interrupt enable */ + __IO uint32_t REQOVRIE : 1; /*!< [9..9] request queue overrun interrupt enable */ + __IO uint32_t DTERIE : 1; /*!< [10..10] Data toggle error interrupt enable */ + uint32_t : 21; + } HCH0INTEN_b; + } ; + + union { + __IO uint32_t HCH0LEN; /*!< (@ 0x00000110) host channel-0 transfer length register */ + + struct { + __IO uint32_t TLEN : 19; /*!< [18..0] Transfer length */ + __IO uint32_t PCNT : 10; /*!< [28..19] Packet count */ + __IO uint32_t DPID : 2; /*!< [30..29] Data PID */ + uint32_t : 1; + } HCH0LEN_b; + } ; + __I uint32_t RESERVED4[3]; + + union { + __IO uint32_t HCH1CTL; /*!< (@ 0x00000120) host channel-1 characteristics register (HCH1CTL) */ + + struct { + __IO uint32_t MPL : 11; /*!< [10..0] Maximum packet size */ + __IO uint32_t EPNUM : 4; /*!< [14..11] Endpoint number */ + __IO uint32_t EPDIR : 1; /*!< [15..15] Endpoint direction */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< [17..17] Low-speed device */ + __IO uint32_t EPTYPE : 2; /*!< [19..18] Endpoint type */ + uint32_t : 2; + __IO uint32_t DAR : 7; /*!< [28..22] Device address */ + __IO uint32_t ODDFRM : 1; /*!< [29..29] Odd frame */ + __IO uint32_t CDIS : 1; /*!< [30..30] Channel disable */ + __IO uint32_t CEN : 1; /*!< [31..31] Channel enable */ + } HCH1CTL_b; + } ; + __I uint32_t RESERVED5; + + union { + __IO uint32_t HCH1INTF; /*!< (@ 0x00000128) host channel-1 interrupt register (HCH1INTF) */ + + struct { + __IO uint32_t TF : 1; /*!< [0..0] Transfer finished */ + __IO uint32_t CH : 1; /*!< [1..1] Channel halted */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< [3..3] STALL response received interrupt */ + __IO uint32_t NAK : 1; /*!< [4..4] NAK response received interrupt */ + __IO uint32_t ACK : 1; /*!< [5..5] ACK response received/transmitted interrupt */ + uint32_t : 1; + __IO uint32_t USBER : 1; /*!< [7..7] USB bus error */ + __IO uint32_t BBER : 1; /*!< [8..8] Babble error */ + __IO uint32_t REQOVR : 1; /*!< [9..9] Request queue overrun */ + __IO uint32_t DTER : 1; /*!< [10..10] Data toggle error */ + uint32_t : 21; + } HCH1INTF_b; + } ; + + union { + __IO uint32_t HCH1INTEN; /*!< (@ 0x0000012C) host channel-1 interrupt enable register (HCH1INTEN) */ + + struct { + __IO uint32_t TFIE : 1; /*!< [0..0] Transfer completed interrupt enable */ + __IO uint32_t CHIE : 1; /*!< [1..1] Channel halted interrupt enable */ + uint32_t : 1; + __IO uint32_t STALLIE : 1; /*!< [3..3] STALL interrupt enable */ + __IO uint32_t NAKIE : 1; /*!< [4..4] NAK interrupt enable */ + __IO uint32_t ACKIE : 1; /*!< [5..5] ACK interrupt enable */ + uint32_t : 1; + __IO uint32_t USBERIE : 1; /*!< [7..7] USB bus error interrupt enable */ + __IO uint32_t BBERIE : 1; /*!< [8..8] Babble error interrupt enable */ + __IO uint32_t REQOVRIE : 1; /*!< [9..9] request queue overrun interrupt enable */ + __IO uint32_t DTERIE : 1; /*!< [10..10] Data toggle error interrupt enable */ + uint32_t : 21; + } HCH1INTEN_b; + } ; + + union { + __IO uint32_t HCH1LEN; /*!< (@ 0x00000130) host channel-1 transfer length register */ + + struct { + __IO uint32_t TLEN : 19; /*!< [18..0] Transfer length */ + __IO uint32_t PCNT : 10; /*!< [28..19] Packet count */ + __IO uint32_t DPID : 2; /*!< [30..29] Data PID */ + uint32_t : 1; + } HCH1LEN_b; + } ; + __I uint32_t RESERVED6[3]; + + union { + __IO uint32_t HCH2CTL; /*!< (@ 0x00000140) host channel-2 characteristics register (HCH2CTL) */ + + struct { + __IO uint32_t MPL : 11; /*!< [10..0] Maximum packet size */ + __IO uint32_t EPNUM : 4; /*!< [14..11] Endpoint number */ + __IO uint32_t EPDIR : 1; /*!< [15..15] Endpoint direction */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< [17..17] Low-speed device */ + __IO uint32_t EPTYPE : 2; /*!< [19..18] Endpoint type */ + uint32_t : 2; + __IO uint32_t DAR : 7; /*!< [28..22] Device address */ + __IO uint32_t ODDFRM : 1; /*!< [29..29] Odd frame */ + __IO uint32_t CDIS : 1; /*!< [30..30] Channel disable */ + __IO uint32_t CEN : 1; /*!< [31..31] Channel enable */ + } HCH2CTL_b; + } ; + __I uint32_t RESERVED7; + + union { + __IO uint32_t HCH2INTF; /*!< (@ 0x00000148) host channel-2 interrupt register (HCH2INTF) */ + + struct { + __IO uint32_t TF : 1; /*!< [0..0] Transfer finished */ + __IO uint32_t CH : 1; /*!< [1..1] Channel halted */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< [3..3] STALL response received interrupt */ + __IO uint32_t NAK : 1; /*!< [4..4] NAK response received interrupt */ + __IO uint32_t ACK : 1; /*!< [5..5] ACK response received/transmitted interrupt */ + uint32_t : 1; + __IO uint32_t USBER : 1; /*!< [7..7] USB bus error */ + __IO uint32_t BBER : 1; /*!< [8..8] Babble error */ + __IO uint32_t REQOVR : 1; /*!< [9..9] Request queue overrun */ + __IO uint32_t DTER : 1; /*!< [10..10] Data toggle error */ + uint32_t : 21; + } HCH2INTF_b; + } ; + + union { + __IO uint32_t HCH2INTEN; /*!< (@ 0x0000014C) host channel-2 interrupt enable register (HCH2INTEN) */ + + struct { + __IO uint32_t TFIE : 1; /*!< [0..0] Transfer completed interrupt enable */ + __IO uint32_t CHIE : 1; /*!< [1..1] Channel halted interrupt enable */ + uint32_t : 1; + __IO uint32_t STALLIE : 1; /*!< [3..3] STALL interrupt enable */ + __IO uint32_t NAKIE : 1; /*!< [4..4] NAK interrupt enable */ + __IO uint32_t ACKIE : 1; /*!< [5..5] ACK interrupt enable */ + uint32_t : 1; + __IO uint32_t USBERIE : 1; /*!< [7..7] USB bus error interrupt enable */ + __IO uint32_t BBERIE : 1; /*!< [8..8] Babble error interrupt enable */ + __IO uint32_t REQOVRIE : 1; /*!< [9..9] request queue overrun interrupt enable */ + __IO uint32_t DTERIE : 1; /*!< [10..10] Data toggle error interrupt enable */ + uint32_t : 21; + } HCH2INTEN_b; + } ; + + union { + __IO uint32_t HCH2LEN; /*!< (@ 0x00000150) host channel-2 transfer length register */ + + struct { + __IO uint32_t TLEN : 19; /*!< [18..0] Transfer length */ + __IO uint32_t PCNT : 10; /*!< [28..19] Packet count */ + __IO uint32_t DPID : 2; /*!< [30..29] Data PID */ + uint32_t : 1; + } HCH2LEN_b; + } ; + __I uint32_t RESERVED8[3]; + + union { + __IO uint32_t HCH3CTL; /*!< (@ 0x00000160) host channel-3 characteristics register (HCH3CTL) */ + + struct { + __IO uint32_t MPL : 11; /*!< [10..0] Maximum packet size */ + __IO uint32_t EPNUM : 4; /*!< [14..11] Endpoint number */ + __IO uint32_t EPDIR : 1; /*!< [15..15] Endpoint direction */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< [17..17] Low-speed device */ + __IO uint32_t EPTYPE : 2; /*!< [19..18] Endpoint type */ + uint32_t : 2; + __IO uint32_t DAR : 7; /*!< [28..22] Device address */ + __IO uint32_t ODDFRM : 1; /*!< [29..29] Odd frame */ + __IO uint32_t CDIS : 1; /*!< [30..30] Channel disable */ + __IO uint32_t CEN : 1; /*!< [31..31] Channel enable */ + } HCH3CTL_b; + } ; + __I uint32_t RESERVED9; + + union { + __IO uint32_t HCH3INTF; /*!< (@ 0x00000168) host channel-3 interrupt register (HCH3INTF) */ + + struct { + __IO uint32_t TF : 1; /*!< [0..0] Transfer finished */ + __IO uint32_t CH : 1; /*!< [1..1] Channel halted */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< [3..3] STALL response received interrupt */ + __IO uint32_t NAK : 1; /*!< [4..4] NAK response received interrupt */ + __IO uint32_t ACK : 1; /*!< [5..5] ACK response received/transmitted interrupt */ + uint32_t : 1; + __IO uint32_t USBER : 1; /*!< [7..7] USB bus error */ + __IO uint32_t BBER : 1; /*!< [8..8] Babble error */ + __IO uint32_t REQOVR : 1; /*!< [9..9] Request queue overrun */ + __IO uint32_t DTER : 1; /*!< [10..10] Data toggle error */ + uint32_t : 21; + } HCH3INTF_b; + } ; + + union { + __IO uint32_t HCH3INTEN; /*!< (@ 0x0000016C) host channel-3 interrupt enable register (HCH3INTEN) */ + + struct { + __IO uint32_t TFIE : 1; /*!< [0..0] Transfer completed interrupt enable */ + __IO uint32_t CHIE : 1; /*!< [1..1] Channel halted interrupt enable */ + uint32_t : 1; + __IO uint32_t STALLIE : 1; /*!< [3..3] STALL interrupt enable */ + __IO uint32_t NAKIE : 1; /*!< [4..4] NAK interrupt enable */ + __IO uint32_t ACKIE : 1; /*!< [5..5] ACK interrupt enable */ + uint32_t : 1; + __IO uint32_t USBERIE : 1; /*!< [7..7] USB bus error interrupt enable */ + __IO uint32_t BBERIE : 1; /*!< [8..8] Babble error interrupt enable */ + __IO uint32_t REQOVRIE : 1; /*!< [9..9] request queue overrun interrupt enable */ + __IO uint32_t DTERIE : 1; /*!< [10..10] Data toggle error interrupt enable */ + uint32_t : 21; + } HCH3INTEN_b; + } ; + + union { + __IO uint32_t HCH3LEN; /*!< (@ 0x00000170) host channel-3 transfer length register */ + + struct { + __IO uint32_t TLEN : 19; /*!< [18..0] Transfer length */ + __IO uint32_t PCNT : 10; /*!< [28..19] Packet count */ + __IO uint32_t DPID : 2; /*!< [30..29] Data PID */ + uint32_t : 1; + } HCH3LEN_b; + } ; + __I uint32_t RESERVED10[3]; + + union { + __IO uint32_t HCH4CTL; /*!< (@ 0x00000180) host channel-4 characteristics register (HCH4CTL) */ + + struct { + __IO uint32_t MPL : 11; /*!< [10..0] Maximum packet size */ + __IO uint32_t EPNUM : 4; /*!< [14..11] Endpoint number */ + __IO uint32_t EPDIR : 1; /*!< [15..15] Endpoint direction */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< [17..17] Low-speed device */ + __IO uint32_t EPTYPE : 2; /*!< [19..18] Endpoint type */ + uint32_t : 2; + __IO uint32_t DAR : 7; /*!< [28..22] Device address */ + __IO uint32_t ODDFRM : 1; /*!< [29..29] Odd frame */ + __IO uint32_t CDIS : 1; /*!< [30..30] Channel disable */ + __IO uint32_t CEN : 1; /*!< [31..31] Channel enable */ + } HCH4CTL_b; + } ; + __I uint32_t RESERVED11; + + union { + __IO uint32_t HCH4INTF; /*!< (@ 0x00000188) host channel-4 interrupt register (HCH4INTF) */ + + struct { + __IO uint32_t TF : 1; /*!< [0..0] Transfer finished */ + __IO uint32_t CH : 1; /*!< [1..1] Channel halted */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< [3..3] STALL response received interrupt */ + __IO uint32_t NAK : 1; /*!< [4..4] NAK response received interrupt */ + __IO uint32_t ACK : 1; /*!< [5..5] ACK response received/transmitted interrupt */ + uint32_t : 1; + __IO uint32_t USBER : 1; /*!< [7..7] USB bus error */ + __IO uint32_t BBER : 1; /*!< [8..8] Babble error */ + __IO uint32_t REQOVR : 1; /*!< [9..9] Request queue overrun */ + __IO uint32_t DTER : 1; /*!< [10..10] Data toggle error */ + uint32_t : 21; + } HCH4INTF_b; + } ; + + union { + __IO uint32_t HCH4INTEN; /*!< (@ 0x0000018C) host channel-4 interrupt enable register (HCH4INTEN) */ + + struct { + __IO uint32_t TFIE : 1; /*!< [0..0] Transfer completed interrupt enable */ + __IO uint32_t CHIE : 1; /*!< [1..1] Channel halted interrupt enable */ + uint32_t : 1; + __IO uint32_t STALLIE : 1; /*!< [3..3] STALL interrupt enable */ + __IO uint32_t NAKIE : 1; /*!< [4..4] NAK interrupt enable */ + __IO uint32_t ACKIE : 1; /*!< [5..5] ACK interrupt enable */ + uint32_t : 1; + __IO uint32_t USBERIE : 1; /*!< [7..7] USB bus error interrupt enable */ + __IO uint32_t BBERIE : 1; /*!< [8..8] Babble error interrupt enable */ + __IO uint32_t REQOVRIE : 1; /*!< [9..9] request queue overrun interrupt enable */ + __IO uint32_t DTERIE : 1; /*!< [10..10] Data toggle error interrupt enable */ + uint32_t : 21; + } HCH4INTEN_b; + } ; + + union { + __IO uint32_t HCH4LEN; /*!< (@ 0x00000190) host channel-4 transfer length register */ + + struct { + __IO uint32_t TLEN : 19; /*!< [18..0] Transfer length */ + __IO uint32_t PCNT : 10; /*!< [28..19] Packet count */ + __IO uint32_t DPID : 2; /*!< [30..29] Data PID */ + uint32_t : 1; + } HCH4LEN_b; + } ; + __I uint32_t RESERVED12[3]; + + union { + __IO uint32_t HCH5CTL; /*!< (@ 0x000001A0) host channel-5 characteristics register (HCH5CTL) */ + + struct { + __IO uint32_t MPL : 11; /*!< [10..0] Maximum packet size */ + __IO uint32_t EPNUM : 4; /*!< [14..11] Endpoint number */ + __IO uint32_t EPDIR : 1; /*!< [15..15] Endpoint direction */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< [17..17] Low-speed device */ + __IO uint32_t EPTYPE : 2; /*!< [19..18] Endpoint type */ + uint32_t : 2; + __IO uint32_t DAR : 7; /*!< [28..22] Device address */ + __IO uint32_t ODDFRM : 1; /*!< [29..29] Odd frame */ + __IO uint32_t CDIS : 1; /*!< [30..30] Channel disable */ + __IO uint32_t CEN : 1; /*!< [31..31] Channel enable */ + } HCH5CTL_b; + } ; + __I uint32_t RESERVED13; + + union { + __IO uint32_t HCH5INTF; /*!< (@ 0x000001A8) host channel-5 interrupt register (HCH5INTF) */ + + struct { + __IO uint32_t TF : 1; /*!< [0..0] Transfer finished */ + __IO uint32_t CH : 1; /*!< [1..1] Channel halted */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< [3..3] STALL response received interrupt */ + __IO uint32_t NAK : 1; /*!< [4..4] NAK response received interrupt */ + __IO uint32_t ACK : 1; /*!< [5..5] ACK response received/transmitted interrupt */ + uint32_t : 1; + __IO uint32_t USBER : 1; /*!< [7..7] USB bus error */ + __IO uint32_t BBER : 1; /*!< [8..8] Babble error */ + __IO uint32_t REQOVR : 1; /*!< [9..9] Request queue overrun */ + __IO uint32_t DTER : 1; /*!< [10..10] Data toggle error */ + uint32_t : 21; + } HCH5INTF_b; + } ; + + union { + __IO uint32_t HCH5INTEN; /*!< (@ 0x000001AC) host channel-5 interrupt enable register (HCH5INTEN) */ + + struct { + __IO uint32_t TFIE : 1; /*!< [0..0] Transfer completed interrupt enable */ + __IO uint32_t CHIE : 1; /*!< [1..1] Channel halted interrupt enable */ + uint32_t : 1; + __IO uint32_t STALLIE : 1; /*!< [3..3] STALL interrupt enable */ + __IO uint32_t NAKIE : 1; /*!< [4..4] NAK interrupt enable */ + __IO uint32_t ACKIE : 1; /*!< [5..5] ACK interrupt enable */ + uint32_t : 1; + __IO uint32_t USBERIE : 1; /*!< [7..7] USB bus error interrupt enable */ + __IO uint32_t BBERIE : 1; /*!< [8..8] Babble error interrupt enable */ + __IO uint32_t REQOVRIE : 1; /*!< [9..9] request queue overrun interrupt enable */ + __IO uint32_t DTERIE : 1; /*!< [10..10] Data toggle error interrupt enable */ + uint32_t : 21; + } HCH5INTEN_b; + } ; + + union { + __IO uint32_t HCH5LEN; /*!< (@ 0x000001B0) host channel-5 transfer length register */ + + struct { + __IO uint32_t TLEN : 19; /*!< [18..0] Transfer length */ + __IO uint32_t PCNT : 10; /*!< [28..19] Packet count */ + __IO uint32_t DPID : 2; /*!< [30..29] Data PID */ + uint32_t : 1; + } HCH5LEN_b; + } ; + __I uint32_t RESERVED14[3]; + + union { + __IO uint32_t HCH6CTL; /*!< (@ 0x000001C0) host channel-6 characteristics register (HCH6CTL) */ + + struct { + __IO uint32_t MPL : 11; /*!< [10..0] Maximum packet size */ + __IO uint32_t EPNUM : 4; /*!< [14..11] Endpoint number */ + __IO uint32_t EPDIR : 1; /*!< [15..15] Endpoint direction */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< [17..17] Low-speed device */ + __IO uint32_t EPTYPE : 2; /*!< [19..18] Endpoint type */ + uint32_t : 2; + __IO uint32_t DAR : 7; /*!< [28..22] Device address */ + __IO uint32_t ODDFRM : 1; /*!< [29..29] Odd frame */ + __IO uint32_t CDIS : 1; /*!< [30..30] Channel disable */ + __IO uint32_t CEN : 1; /*!< [31..31] Channel enable */ + } HCH6CTL_b; + } ; + __I uint32_t RESERVED15; + + union { + __IO uint32_t HCH6INTF; /*!< (@ 0x000001C8) host channel-6 interrupt register (HCH6INTF) */ + + struct { + __IO uint32_t TF : 1; /*!< [0..0] Transfer finished */ + __IO uint32_t CH : 1; /*!< [1..1] Channel halted */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< [3..3] STALL response received interrupt */ + __IO uint32_t NAK : 1; /*!< [4..4] NAK response received interrupt */ + __IO uint32_t ACK : 1; /*!< [5..5] ACK response received/transmitted interrupt */ + uint32_t : 1; + __IO uint32_t USBER : 1; /*!< [7..7] USB bus error */ + __IO uint32_t BBER : 1; /*!< [8..8] Babble error */ + __IO uint32_t REQOVR : 1; /*!< [9..9] Request queue overrun */ + __IO uint32_t DTER : 1; /*!< [10..10] Data toggle error */ + uint32_t : 21; + } HCH6INTF_b; + } ; + + union { + __IO uint32_t HCH6INTEN; /*!< (@ 0x000001CC) host channel-6 interrupt enable register (HCH6INTEN) */ + + struct { + __IO uint32_t TFIE : 1; /*!< [0..0] Transfer completed interrupt enable */ + __IO uint32_t CHIE : 1; /*!< [1..1] Channel halted interrupt enable */ + uint32_t : 1; + __IO uint32_t STALLIE : 1; /*!< [3..3] STALL interrupt enable */ + __IO uint32_t NAKIE : 1; /*!< [4..4] NAK interrupt enable */ + __IO uint32_t ACKIE : 1; /*!< [5..5] ACK interrupt enable */ + uint32_t : 1; + __IO uint32_t USBERIE : 1; /*!< [7..7] USB bus error interrupt enable */ + __IO uint32_t BBERIE : 1; /*!< [8..8] Babble error interrupt enable */ + __IO uint32_t REQOVRIE : 1; /*!< [9..9] request queue overrun interrupt enable */ + __IO uint32_t DTERIE : 1; /*!< [10..10] Data toggle error interrupt enable */ + uint32_t : 21; + } HCH6INTEN_b; + } ; + + union { + __IO uint32_t HCH6LEN; /*!< (@ 0x000001D0) host channel-6 transfer length register */ + + struct { + __IO uint32_t TLEN : 19; /*!< [18..0] Transfer length */ + __IO uint32_t PCNT : 10; /*!< [28..19] Packet count */ + __IO uint32_t DPID : 2; /*!< [30..29] Data PID */ + uint32_t : 1; + } HCH6LEN_b; + } ; + __I uint32_t RESERVED16[3]; + + union { + __IO uint32_t HCH7CTL; /*!< (@ 0x000001E0) host channel-7 characteristics register (HCH7CTL) */ + + struct { + __IO uint32_t MPL : 11; /*!< [10..0] Maximum packet size */ + __IO uint32_t EPNUM : 4; /*!< [14..11] Endpoint number */ + __IO uint32_t EPDIR : 1; /*!< [15..15] Endpoint direction */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< [17..17] Low-speed device */ + __IO uint32_t EPTYPE : 2; /*!< [19..18] Endpoint type */ + uint32_t : 2; + __IO uint32_t DAR : 7; /*!< [28..22] Device address */ + __IO uint32_t ODDFRM : 1; /*!< [29..29] Odd frame */ + __IO uint32_t CDIS : 1; /*!< [30..30] Channel disable */ + __IO uint32_t CEN : 1; /*!< [31..31] Channel enable */ + } HCH7CTL_b; + } ; + __I uint32_t RESERVED17; + + union { + __IO uint32_t HCH7INTF; /*!< (@ 0x000001E8) host channel-7 interrupt register (HCH7INTF) */ + + struct { + __IO uint32_t TF : 1; /*!< [0..0] Transfer finished */ + __IO uint32_t CH : 1; /*!< [1..1] Channel halted */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< [3..3] STALL response received interrupt */ + __IO uint32_t NAK : 1; /*!< [4..4] NAK response received interrupt */ + __IO uint32_t ACK : 1; /*!< [5..5] ACK response received/transmitted interrupt */ + uint32_t : 1; + __IO uint32_t USBER : 1; /*!< [7..7] USB bus error */ + __IO uint32_t BBER : 1; /*!< [8..8] Babble error */ + __IO uint32_t REQOVR : 1; /*!< [9..9] Request queue overrun */ + __IO uint32_t DTER : 1; /*!< [10..10] Data toggle error */ + uint32_t : 21; + } HCH7INTF_b; + } ; + + union { + __IO uint32_t HCH7INTEN; /*!< (@ 0x000001EC) host channel-7 interrupt enable register (HCH7INTEN) */ + + struct { + __IO uint32_t TFIE : 1; /*!< [0..0] Transfer completed interrupt enable */ + __IO uint32_t CHIE : 1; /*!< [1..1] Channel halted interrupt enable */ + uint32_t : 1; + __IO uint32_t STALLIE : 1; /*!< [3..3] STALL interrupt enable */ + __IO uint32_t NAKIE : 1; /*!< [4..4] NAK interrupt enable */ + __IO uint32_t ACKIE : 1; /*!< [5..5] ACK interrupt enable */ + uint32_t : 1; + __IO uint32_t USBERIE : 1; /*!< [7..7] USB bus error interrupt enable */ + __IO uint32_t BBERIE : 1; /*!< [8..8] Babble error interrupt enable */ + __IO uint32_t REQOVRIE : 1; /*!< [9..9] request queue overrun interrupt enable */ + __IO uint32_t DTERIE : 1; /*!< [10..10] Data toggle error interrupt enable */ + uint32_t : 21; + } HCH7INTEN_b; + } ; + + union { + __IO uint32_t HCH7LEN; /*!< (@ 0x000001F0) host channel-7 transfer length register */ + + struct { + __IO uint32_t TLEN : 19; /*!< [18..0] Transfer length */ + __IO uint32_t PCNT : 10; /*!< [28..19] Packet count */ + __IO uint32_t DPID : 2; /*!< [30..29] Data PID */ + uint32_t : 1; + } HCH7LEN_b; + } ; +} USBFS_HOST_Type; /*!< Size = 500 (0x1f4) */ + + + +/* =========================================================================================================================== */ +/* ================ USBFS_DEVICE ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief USB on the go full speed device (USBFS_DEVICE) + */ + +typedef struct { /*!< (@ 0x50000800) USBFS_DEVICE Structure */ + + union { + __IO uint32_t DCFG; /*!< (@ 0x00000000) device configuration register (DCFG) */ + + struct { + __IO uint32_t DS : 2; /*!< [1..0] Device speed */ + __IO uint32_t NZLSOH : 1; /*!< [2..2] Non-zero-length status OUT handshake */ + uint32_t : 1; + __IO uint32_t DAR : 7; /*!< [10..4] Device address */ + __IO uint32_t EOPFT : 2; /*!< [12..11] end of periodic frame time */ + uint32_t : 19; + } DCFG_b; + } ; + + union { + __IO uint32_t DCTL; /*!< (@ 0x00000004) device control register (DCTL) */ + + struct { + __IO uint32_t RWKUP : 1; /*!< [0..0] Remote wakeup */ + __IO uint32_t SD : 1; /*!< [1..1] Soft disconnect */ + __I uint32_t GINS : 1; /*!< [2..2] Global IN NAK status */ + __I uint32_t GONS : 1; /*!< [3..3] Global OUT NAK status */ + uint32_t : 3; + __O uint32_t SGINAK : 1; /*!< [7..7] Set global IN NAK */ + __O uint32_t CGINAK : 1; /*!< [8..8] Clear global IN NAK */ + __O uint32_t SGONAK : 1; /*!< [9..9] Set global OUT NAK */ + __O uint32_t CGONAK : 1; /*!< [10..10] Clear global OUT NAK */ + __IO uint32_t POIF : 1; /*!< [11..11] Power-on initialization flag */ + uint32_t : 20; + } DCTL_b; + } ; + + union { + __I uint32_t DSTAT; /*!< (@ 0x00000008) device status register (DSTAT) */ + + struct { + __I uint32_t SPST : 1; /*!< [0..0] Suspend status */ + __I uint32_t ES : 2; /*!< [2..1] Enumerated speed */ + uint32_t : 5; + __I uint32_t FNRSOF : 14; /*!< [21..8] Frame number of the received SOF */ + uint32_t : 10; + } DSTAT_b; + } ; + __I uint32_t RESERVED; + + union { + __IO uint32_t DIEPINTEN; /*!< (@ 0x00000010) device IN endpoint common interrupt mask register + (DIEPINTEN) */ + + struct { + __IO uint32_t TFEN : 1; /*!< [0..0] Transfer finished interrupt enable */ + __IO uint32_t EPDISEN : 1; /*!< [1..1] Endpoint disabled interrupt enable */ + uint32_t : 1; + __IO uint32_t CITOEN : 1; /*!< [3..3] Control IN timeout condition interrupt enable (Non-isochronous + endpoints) */ + __IO uint32_t EPTXFUDEN : 1; /*!< [4..4] Endpoint Tx FIFO underrun interrupt enable bit */ + uint32_t : 1; + __IO uint32_t IEPNEEN : 1; /*!< [6..6] IN endpoint NAK effective interrupt enable */ + uint32_t : 25; + } DIEPINTEN_b; + } ; + + union { + __IO uint32_t DOEPINTEN; /*!< (@ 0x00000014) device OUT endpoint common interrupt enable register + (DOEPINTEN) */ + + struct { + __IO uint32_t TFEN : 1; /*!< [0..0] Transfer finished interrupt enable */ + __IO uint32_t EPDISEN : 1; /*!< [1..1] Endpoint disabled interrupt enable */ + uint32_t : 1; + __IO uint32_t STPFEN : 1; /*!< [3..3] SETUP phase finished interrupt enable */ + __IO uint32_t EPRXFOVREN : 1; /*!< [4..4] Endpoint Rx FIFO overrun interrupt enable */ + uint32_t : 1; + __IO uint32_t BTBSTPEN : 1; /*!< [6..6] Back-to-back SETUP packets interrupt enable */ + uint32_t : 25; + } DOEPINTEN_b; + } ; + + union { + __I uint32_t DAEPINT; /*!< (@ 0x00000018) device all endpoints interrupt register (DAEPINT) */ + + struct { + __I uint32_t IEPITB : 4; /*!< [3..0] Device all IN endpoint interrupt bits */ + uint32_t : 12; + __I uint32_t OEPITB : 4; /*!< [19..16] Device all OUT endpoint interrupt bits */ + uint32_t : 12; + } DAEPINT_b; + } ; + + union { + __IO uint32_t DAEPINTEN; /*!< (@ 0x0000001C) Device all endpoints interrupt enable register + (DAEPINTEN) */ + + struct { + __IO uint32_t IEPIE : 4; /*!< [3..0] IN EP interrupt interrupt enable bits */ + uint32_t : 12; + __IO uint32_t OEPIE : 4; /*!< [19..16] OUT endpoint interrupt enable bits */ + uint32_t : 12; + } DAEPINTEN_b; + } ; + __I uint32_t RESERVED1[2]; + + union { + __IO uint32_t DVBUSDT; /*!< (@ 0x00000028) device VBUS discharge time register */ + + struct { + __IO uint32_t DVBUSDT : 16; /*!< [15..0] Device VBUS discharge time */ + uint32_t : 16; + } DVBUSDT_b; + } ; + + union { + __IO uint32_t DVBUSPT; /*!< (@ 0x0000002C) device VBUS pulsing time register */ + + struct { + __IO uint32_t DVBUSPT : 12; /*!< [11..0] Device VBUS pulsing time */ + uint32_t : 20; + } DVBUSPT_b; + } ; + __I uint32_t RESERVED2; + + union { + __IO uint32_t DIEPFEINTEN; /*!< (@ 0x00000034) device IN endpoint FIFO empty interrupt enable + register */ + + struct { + __IO uint32_t IEPTXFEIE : 4; /*!< [3..0] IN EP Tx FIFO empty interrupt enable bits */ + uint32_t : 28; + } DIEPFEINTEN_b; + } ; + __I uint32_t RESERVED3[50]; + + union { + __IO uint32_t DIEP0CTL; /*!< (@ 0x00000100) device IN endpoint 0 control register (DIEP0CTL) */ + + struct { + __IO uint32_t MPL : 2; /*!< [1..0] Maximum packet length */ + uint32_t : 13; + __I uint32_t EPACT : 1; /*!< [15..15] endpoint active */ + uint32_t : 1; + __I uint32_t NAKS : 1; /*!< [17..17] NAK status */ + __I uint32_t EPTYPE : 2; /*!< [19..18] Endpoint type */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< [21..21] STALL handshake */ + __IO uint32_t TXFNUM : 4; /*!< [25..22] TxFIFO number */ + __O uint32_t CNAK : 1; /*!< [26..26] Clear NAK */ + __O uint32_t SNAK : 1; /*!< [27..27] Set NAK */ + uint32_t : 2; + __IO uint32_t EPD : 1; /*!< [30..30] Endpoint disable */ + __IO uint32_t EPEN : 1; /*!< [31..31] Endpoint enable */ + } DIEP0CTL_b; + } ; + __I uint32_t RESERVED4; + + union { + __IO uint32_t DIEP0INTF; /*!< (@ 0x00000108) device endpoint-0 interrupt register */ + + struct { + __IO uint32_t TF : 1; /*!< [0..0] Transfer finished */ + __IO uint32_t EPDIS : 1; /*!< [1..1] Endpoint finished */ + uint32_t : 1; + __IO uint32_t CITO : 1; /*!< [3..3] Control in timeout interrupt */ + __IO uint32_t EPTXFUD : 1; /*!< [4..4] Endpoint Tx FIFO underrun */ + uint32_t : 1; + __IO uint32_t IEPNE : 1; /*!< [6..6] IN endpoint NAK effective */ + __I uint32_t TXFE : 1; /*!< [7..7] Transmit FIFO empty */ + uint32_t : 24; + } DIEP0INTF_b; + } ; + __I uint32_t RESERVED5; + + union { + __IO uint32_t DIEP0LEN; /*!< (@ 0x00000110) device IN endpoint-0 transfer length register */ + + struct { + __IO uint32_t TLEN : 7; /*!< [6..0] Transfer length */ + uint32_t : 12; + __IO uint32_t PCNT : 2; /*!< [20..19] Packet count */ + uint32_t : 11; + } DIEP0LEN_b; + } ; + __I uint32_t RESERVED6; + + union { + __I uint32_t DIEP0TFSTAT; /*!< (@ 0x00000118) device IN endpoint 0 transmit FIFO status register */ + + struct { + __I uint32_t IEPTFS : 16; /*!< [15..0] IN endpoint TxFIFO space remaining */ + uint32_t : 16; + } DIEP0TFSTAT_b; + } ; + __I uint32_t RESERVED7; + + union { + __IO uint32_t DIEP1CTL; /*!< (@ 0x00000120) device in endpoint-1 control register */ + + struct { + __IO uint32_t MPL : 11; /*!< [10..0] maximum packet length */ + uint32_t : 4; + __IO uint32_t EPACT : 1; /*!< [15..15] Endpoint active */ + __I uint32_t EOFRM_DPID : 1; /*!< [16..16] EOFRM/DPID */ + __I uint32_t NAKS : 1; /*!< [17..17] NAK status */ + __IO uint32_t EPTYPE : 2; /*!< [19..18] Endpoint type */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< [21..21] STALL handshake */ + __IO uint32_t TXFNUM : 4; /*!< [25..22] Tx FIFO number */ + __O uint32_t CNAK : 1; /*!< [26..26] Clear NAK */ + __O uint32_t SNAK : 1; /*!< [27..27] Set NAK */ + __O uint32_t SD0PID_SEVENFRM : 1; /*!< [28..28] SD0PID/SEVNFRM */ + __O uint32_t SD1PID_SODDFRM : 1; /*!< [29..29] Set DATA1 PID/Set odd frame */ + __IO uint32_t EPD : 1; /*!< [30..30] Endpoint disable */ + __IO uint32_t EPEN : 1; /*!< [31..31] Endpoint enable */ + } DIEP1CTL_b; + } ; + __I uint32_t RESERVED8; + + union { + __IO uint32_t DIEP1INTF; /*!< (@ 0x00000128) device endpoint-1 interrupt register */ + + struct { + __IO uint32_t TF : 1; /*!< [0..0] Transfer finished */ + __IO uint32_t EPDIS : 1; /*!< [1..1] Endpoint finished */ + uint32_t : 1; + __IO uint32_t CITO : 1; /*!< [3..3] Control in timeout interrupt */ + __IO uint32_t EPTXFUD : 1; /*!< [4..4] Endpoint Tx FIFO underrun */ + uint32_t : 1; + __IO uint32_t IEPNE : 1; /*!< [6..6] IN endpoint NAK effective */ + __I uint32_t TXFE : 1; /*!< [7..7] Transmit FIFO empty */ + uint32_t : 24; + } DIEP1INTF_b; + } ; + __I uint32_t RESERVED9; + + union { + __IO uint32_t DIEP1LEN; /*!< (@ 0x00000130) device IN endpoint-1 transfer length register */ + + struct { + __IO uint32_t TLEN : 19; /*!< [18..0] Transfer length */ + __IO uint32_t PCNT : 10; /*!< [28..19] Packet count */ + __IO uint32_t MCPF : 2; /*!< [30..29] Multi packet count per frame */ + uint32_t : 1; + } DIEP1LEN_b; + } ; + __I uint32_t RESERVED10; + + union { + __I uint32_t DIEP1TFSTAT; /*!< (@ 0x00000138) device IN endpoint 1 transmit FIFO status register */ + + struct { + __I uint32_t IEPTFS : 16; /*!< [15..0] IN endpoint TxFIFO space remaining */ + uint32_t : 16; + } DIEP1TFSTAT_b; + } ; + __I uint32_t RESERVED11; + + union { + __IO uint32_t DIEP2CTL; /*!< (@ 0x00000140) device endpoint-2 control register */ + + struct { + __IO uint32_t MPL : 11; /*!< [10..0] maximum packet length */ + uint32_t : 4; + __IO uint32_t EPACT : 1; /*!< [15..15] Endpoint active */ + __I uint32_t EOFRM_DPID : 1; /*!< [16..16] EOFRM/DPID */ + __I uint32_t NAKS : 1; /*!< [17..17] NAK status */ + __IO uint32_t EPTYPE : 2; /*!< [19..18] Endpoint type */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< [21..21] STALL handshake */ + __IO uint32_t TXFNUM : 4; /*!< [25..22] Tx FIFO number */ + __O uint32_t CNAK : 1; /*!< [26..26] Clear NAK */ + __O uint32_t SNAK : 1; /*!< [27..27] Set NAK */ + __O uint32_t SD0PID_SEVENFRM : 1; /*!< [28..28] SD0PID/SEVNFRM */ + __O uint32_t SD1PID_SODDFRM : 1; /*!< [29..29] Set DATA1 PID/Set odd frame */ + __IO uint32_t EPD : 1; /*!< [30..30] Endpoint disable */ + __IO uint32_t EPEN : 1; /*!< [31..31] Endpoint enable */ + } DIEP2CTL_b; + } ; + __I uint32_t RESERVED12; + + union { + __IO uint32_t DIEP2INTF; /*!< (@ 0x00000148) device endpoint-2 interrupt register */ + + struct { + __IO uint32_t TF : 1; /*!< [0..0] Transfer finished */ + __IO uint32_t EPDIS : 1; /*!< [1..1] Endpoint finished */ + uint32_t : 1; + __IO uint32_t CITO : 1; /*!< [3..3] Control in timeout interrupt */ + __IO uint32_t EPTXFUD : 1; /*!< [4..4] Endpoint Tx FIFO underrun */ + uint32_t : 1; + __IO uint32_t IEPNE : 1; /*!< [6..6] IN endpoint NAK effective */ + __I uint32_t TXFE : 1; /*!< [7..7] Transmit FIFO empty */ + uint32_t : 24; + } DIEP2INTF_b; + } ; + __I uint32_t RESERVED13; + + union { + __IO uint32_t DIEP2LEN; /*!< (@ 0x00000150) device IN endpoint-2 transfer length register */ + + struct { + __IO uint32_t TLEN : 19; /*!< [18..0] Transfer length */ + __IO uint32_t PCNT : 10; /*!< [28..19] Packet count */ + __IO uint32_t MCPF : 2; /*!< [30..29] Multi packet count per frame */ + uint32_t : 1; + } DIEP2LEN_b; + } ; + __I uint32_t RESERVED14; + + union { + __I uint32_t DIEP2TFSTAT; /*!< (@ 0x00000158) device IN endpoint 2 transmit FIFO status register */ + + struct { + __I uint32_t IEPTFS : 16; /*!< [15..0] IN endpoint TxFIFO space remaining */ + uint32_t : 16; + } DIEP2TFSTAT_b; + } ; + __I uint32_t RESERVED15; + + union { + __IO uint32_t DIEP3CTL; /*!< (@ 0x00000160) device endpoint-3 control register */ + + struct { + __IO uint32_t MPL : 11; /*!< [10..0] maximum packet length */ + uint32_t : 4; + __IO uint32_t EPACT : 1; /*!< [15..15] Endpoint active */ + __I uint32_t EOFRM_DPID : 1; /*!< [16..16] EOFRM/DPID */ + __I uint32_t NAKS : 1; /*!< [17..17] NAK status */ + __IO uint32_t EPTYPE : 2; /*!< [19..18] Endpoint type */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< [21..21] STALL handshake */ + __IO uint32_t TXFNUM : 4; /*!< [25..22] Tx FIFO number */ + __O uint32_t CNAK : 1; /*!< [26..26] Clear NAK */ + __O uint32_t SNAK : 1; /*!< [27..27] Set NAK */ + __O uint32_t SD0PID_SEVENFRM : 1; /*!< [28..28] SD0PID/SEVNFRM */ + __O uint32_t SD1PID_SODDFRM : 1; /*!< [29..29] Set DATA1 PID/Set odd frame */ + __IO uint32_t EPD : 1; /*!< [30..30] Endpoint disable */ + __IO uint32_t EPEN : 1; /*!< [31..31] Endpoint enable */ + } DIEP3CTL_b; + } ; + __I uint32_t RESERVED16; + + union { + __IO uint32_t DIEP3INTF; /*!< (@ 0x00000168) device endpoint-3 interrupt register */ + + struct { + __IO uint32_t TF : 1; /*!< [0..0] Transfer finished */ + __IO uint32_t EPDIS : 1; /*!< [1..1] Endpoint finished */ + uint32_t : 1; + __IO uint32_t CITO : 1; /*!< [3..3] Control in timeout interrupt */ + __IO uint32_t EPTXFUD : 1; /*!< [4..4] Endpoint Tx FIFO underrun */ + uint32_t : 1; + __IO uint32_t IEPNE : 1; /*!< [6..6] IN endpoint NAK effective */ + __I uint32_t TXFE : 1; /*!< [7..7] Transmit FIFO empty */ + uint32_t : 24; + } DIEP3INTF_b; + } ; + __I uint32_t RESERVED17; + + union { + __IO uint32_t DIEP3LEN; /*!< (@ 0x00000170) device IN endpoint-3 transfer length register */ + + struct { + __IO uint32_t TLEN : 19; /*!< [18..0] Transfer length */ + __IO uint32_t PCNT : 10; /*!< [28..19] Packet count */ + __IO uint32_t MCPF : 2; /*!< [30..29] Multi packet count per frame */ + uint32_t : 1; + } DIEP3LEN_b; + } ; + __I uint32_t RESERVED18; + + union { + __I uint32_t DIEP3TFSTAT; /*!< (@ 0x00000178) device IN endpoint 3 transmit FIFO status register */ + + struct { + __I uint32_t IEPTFS : 16; /*!< [15..0] IN endpoint TxFIFO space remaining */ + uint32_t : 16; + } DIEP3TFSTAT_b; + } ; + __I uint32_t RESERVED19[97]; + + union { + __IO uint32_t DOEP0CTL; /*!< (@ 0x00000300) device endpoint-0 control register */ + + struct { + __I uint32_t MPL : 2; /*!< [1..0] Maximum packet length */ + uint32_t : 13; + __I uint32_t EPACT : 1; /*!< [15..15] Endpoint active */ + uint32_t : 1; + __I uint32_t NAKS : 1; /*!< [17..17] NAK status */ + __I uint32_t EPTYPE : 2; /*!< [19..18] Endpoint type */ + __IO uint32_t SNOOP : 1; /*!< [20..20] Snoop mode */ + __IO uint32_t STALL : 1; /*!< [21..21] STALL handshake */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< [26..26] Clear NAK */ + __O uint32_t SNAK : 1; /*!< [27..27] Set NAK */ + uint32_t : 2; + __I uint32_t EPD : 1; /*!< [30..30] Endpoint disable */ + __IO uint32_t EPEN : 1; /*!< [31..31] Endpoint enable */ + } DOEP0CTL_b; + } ; + __I uint32_t RESERVED20; + + union { + __IO uint32_t DOEP0INTF; /*!< (@ 0x00000308) device out endpoint-0 interrupt flag register */ + + struct { + __IO uint32_t TF : 1; /*!< [0..0] Transfer finished */ + __IO uint32_t EPDIS : 1; /*!< [1..1] Endpoint disabled */ + uint32_t : 1; + __IO uint32_t STPF : 1; /*!< [3..3] Setup phase finished */ + __IO uint32_t EPRXFOVR : 1; /*!< [4..4] Endpoint Rx FIFO overrun */ + uint32_t : 1; + __IO uint32_t BTBSTP : 1; /*!< [6..6] Back-to-back SETUP packets */ + uint32_t : 25; + } DOEP0INTF_b; + } ; + __I uint32_t RESERVED21; + + union { + __IO uint32_t DOEP0LEN; /*!< (@ 0x00000310) device OUT endpoint-0 transfer length register */ + + struct { + __IO uint32_t TLEN : 7; /*!< [6..0] Transfer length */ + uint32_t : 12; + __IO uint32_t PCNT : 1; /*!< [19..19] Packet count */ + uint32_t : 9; + __IO uint32_t STPCNT : 2; /*!< [30..29] SETUP packet count */ + uint32_t : 1; + } DOEP0LEN_b; + } ; + __I uint32_t RESERVED22[3]; + + union { + __IO uint32_t DOEP1CTL; /*!< (@ 0x00000320) device endpoint-1 control register */ + + struct { + __IO uint32_t MPL : 11; /*!< [10..0] maximum packet length */ + uint32_t : 4; + __IO uint32_t EPACT : 1; /*!< [15..15] Endpoint active */ + __I uint32_t EOFRM_DPID : 1; /*!< [16..16] EOFRM/DPID */ + __I uint32_t NAKS : 1; /*!< [17..17] NAK status */ + __IO uint32_t EPTYPE : 2; /*!< [19..18] Endpoint type */ + __IO uint32_t SNOOP : 1; /*!< [20..20] Snoop mode */ + __IO uint32_t STALL : 1; /*!< [21..21] STALL handshake */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< [26..26] Clear NAK */ + __O uint32_t SNAK : 1; /*!< [27..27] Set NAK */ + __O uint32_t SD0PID_SEVENFRM : 1; /*!< [28..28] SD0PID/SEVENFRM */ + __O uint32_t SD1PID_SODDFRM : 1; /*!< [29..29] SD1PID/SODDFRM */ + __IO uint32_t EPD : 1; /*!< [30..30] Endpoint disable */ + __IO uint32_t EPEN : 1; /*!< [31..31] Endpoint enable */ + } DOEP1CTL_b; + } ; + __I uint32_t RESERVED23; + + union { + __IO uint32_t DOEP1INTF; /*!< (@ 0x00000328) device out endpoint-1 interrupt flag register */ + + struct { + __IO uint32_t TF : 1; /*!< [0..0] Transfer finished */ + __IO uint32_t EPDIS : 1; /*!< [1..1] Endpoint disabled */ + uint32_t : 1; + __IO uint32_t STPF : 1; /*!< [3..3] Setup phase finished */ + __IO uint32_t EPRXFOVR : 1; /*!< [4..4] Endpoint Rx FIFO overrun */ + uint32_t : 1; + __IO uint32_t BTBSTP : 1; /*!< [6..6] Back-to-back SETUP packets */ + uint32_t : 25; + } DOEP1INTF_b; + } ; + __I uint32_t RESERVED24; + + union { + __IO uint32_t DOEP1LEN; /*!< (@ 0x00000330) device OUT endpoint-1 transfer length register */ + + struct { + __IO uint32_t TLEN : 19; /*!< [18..0] Transfer length */ + __IO uint32_t PCNT : 10; /*!< [28..19] Packet count */ + __IO uint32_t STPCNT_RXDPID : 2; /*!< [30..29] SETUP packet count/Received data PID */ + uint32_t : 1; + } DOEP1LEN_b; + } ; + __I uint32_t RESERVED25[3]; + + union { + __IO uint32_t DOEP2CTL; /*!< (@ 0x00000340) device endpoint-2 control register */ + + struct { + __IO uint32_t MPL : 11; /*!< [10..0] maximum packet length */ + uint32_t : 4; + __IO uint32_t EPACT : 1; /*!< [15..15] Endpoint active */ + __I uint32_t EOFRM_DPID : 1; /*!< [16..16] EOFRM/DPID */ + __I uint32_t NAKS : 1; /*!< [17..17] NAK status */ + __IO uint32_t EPTYPE : 2; /*!< [19..18] Endpoint type */ + __IO uint32_t SNOOP : 1; /*!< [20..20] Snoop mode */ + __IO uint32_t STALL : 1; /*!< [21..21] STALL handshake */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< [26..26] Clear NAK */ + __O uint32_t SNAK : 1; /*!< [27..27] Set NAK */ + __O uint32_t SD0PID_SEVENFRM : 1; /*!< [28..28] SD0PID/SEVENFRM */ + __O uint32_t SD1PID_SODDFRM : 1; /*!< [29..29] SD1PID/SODDFRM */ + __IO uint32_t EPD : 1; /*!< [30..30] Endpoint disable */ + __IO uint32_t EPEN : 1; /*!< [31..31] Endpoint enable */ + } DOEP2CTL_b; + } ; + __I uint32_t RESERVED26; + + union { + __IO uint32_t DOEP2INTF; /*!< (@ 0x00000348) device out endpoint-2 interrupt flag register */ + + struct { + __IO uint32_t TF : 1; /*!< [0..0] Transfer finished */ + __IO uint32_t EPDIS : 1; /*!< [1..1] Endpoint disabled */ + uint32_t : 1; + __IO uint32_t STPF : 1; /*!< [3..3] Setup phase finished */ + __IO uint32_t EPRXFOVR : 1; /*!< [4..4] Endpoint Rx FIFO overrun */ + uint32_t : 1; + __IO uint32_t BTBSTP : 1; /*!< [6..6] Back-to-back SETUP packets */ + uint32_t : 25; + } DOEP2INTF_b; + } ; + __I uint32_t RESERVED27; + + union { + __IO uint32_t DOEP2LEN; /*!< (@ 0x00000350) device OUT endpoint-2 transfer length register */ + + struct { + __IO uint32_t TLEN : 19; /*!< [18..0] Transfer length */ + __IO uint32_t PCNT : 10; /*!< [28..19] Packet count */ + __IO uint32_t STPCNT_RXDPID : 2; /*!< [30..29] SETUP packet count/Received data PID */ + uint32_t : 1; + } DOEP2LEN_b; + } ; + __I uint32_t RESERVED28[3]; + + union { + __IO uint32_t DOEP3CTL; /*!< (@ 0x00000360) device endpoint-3 control register */ + + struct { + __IO uint32_t MPL : 11; /*!< [10..0] maximum packet length */ + uint32_t : 4; + __IO uint32_t EPACT : 1; /*!< [15..15] Endpoint active */ + __I uint32_t EOFRM_DPID : 1; /*!< [16..16] EOFRM/DPID */ + __I uint32_t NAKS : 1; /*!< [17..17] NAK status */ + __IO uint32_t EPTYPE : 2; /*!< [19..18] Endpoint type */ + __IO uint32_t SNOOP : 1; /*!< [20..20] Snoop mode */ + __IO uint32_t STALL : 1; /*!< [21..21] STALL handshake */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< [26..26] Clear NAK */ + __O uint32_t SNAK : 1; /*!< [27..27] Set NAK */ + __O uint32_t SD0PID_SEVENFRM : 1; /*!< [28..28] SD0PID/SEVENFRM */ + __O uint32_t SD1PID_SODDFRM : 1; /*!< [29..29] SD1PID/SODDFRM */ + __IO uint32_t EPD : 1; /*!< [30..30] Endpoint disable */ + __IO uint32_t EPEN : 1; /*!< [31..31] Endpoint enable */ + } DOEP3CTL_b; + } ; + __I uint32_t RESERVED29; + + union { + __IO uint32_t DOEP3INTF; /*!< (@ 0x00000368) device out endpoint-3 interrupt flag register */ + + struct { + __IO uint32_t TF : 1; /*!< [0..0] Transfer finished */ + __IO uint32_t EPDIS : 1; /*!< [1..1] Endpoint disabled */ + uint32_t : 1; + __IO uint32_t STPF : 1; /*!< [3..3] Setup phase finished */ + __IO uint32_t EPRXFOVR : 1; /*!< [4..4] Endpoint Rx FIFO overrun */ + uint32_t : 1; + __IO uint32_t BTBSTP : 1; /*!< [6..6] Back-to-back SETUP packets */ + uint32_t : 25; + } DOEP3INTF_b; + } ; + __I uint32_t RESERVED30; + + union { + __IO uint32_t DOEP3LEN; /*!< (@ 0x00000370) device OUT endpoint-3 transfer length register */ + + struct { + __IO uint32_t TLEN : 19; /*!< [18..0] Transfer length */ + __IO uint32_t PCNT : 10; /*!< [28..19] Packet count */ + __IO uint32_t STPCNT_RXDPID : 2; /*!< [30..29] SETUP packet count/Received data PID */ + uint32_t : 1; + } DOEP3LEN_b; + } ; +} USBFS_DEVICE_Type; /*!< Size = 884 (0x374) */ + + + +/* =========================================================================================================================== */ +/* ================ USBFS_PWRCLK ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief USB on the go full speed (USBFS_PWRCLK) + */ + +typedef struct { /*!< (@ 0x50000E00) USBFS_PWRCLK Structure */ + + union { + __IO uint32_t PWRCLKCTL; /*!< (@ 0x00000000) power and clock gating control register (PWRCLKCTL) */ + + struct { + __IO uint32_t SUCLK : 1; /*!< [0..0] Stop the USB clock */ + __IO uint32_t SHCLK : 1; /*!< [1..1] Stop HCLK */ + uint32_t : 30; + } PWRCLKCTL_b; + } ; +} USBFS_PWRCLK_Type; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ WWDGT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Window watchdog timer (WWDGT) + */ + +typedef struct { /*!< (@ 0x40002C00) WWDGT Structure */ + + union { + __IO uint32_t CTL; /*!< (@ 0x00000000) Control register */ + + struct { + __IO uint32_t CNT : 7; /*!< [6..0] 7-bit counter */ + __IO uint32_t WDGTEN : 1; /*!< [7..7] Activation bit */ + uint32_t : 24; + } CTL_b; + } ; + + union { + __IO uint32_t CFG; /*!< (@ 0x00000004) Configuration register */ + + struct { + __IO uint32_t WIN : 7; /*!< [6..0] 7-bit window value */ + __IO uint32_t PSC : 2; /*!< [8..7] Prescaler */ + __IO uint32_t EWIE : 1; /*!< [9..9] Early wakeup interrupt */ + uint32_t : 22; + } CFG_b; + } ; + + union { + __IO uint32_t STAT; /*!< (@ 0x00000008) Status register */ + + struct { + __IO uint32_t EWIF : 1; /*!< [0..0] Early wakeup interrupt flag */ + uint32_t : 31; + } STAT_b; + } ; +} WWDGT_Type; /*!< Size = 12 (0xc) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +//#define ADC0_BASE 0x40012400UL +//#define ADC1_BASE 0x40012800UL +//#define AFIO_BASE 0x40010000UL +//#define BKP_BASE 0x40006C00UL +//#define CAN0_BASE 0x40006400UL +//#define CAN1_BASE 0x40006800UL +//#define CRC_BASE 0x40023000UL +//#define DAC_BASE 0x40007400UL +//#define DBG_BASE 0xE0042000UL +//#define DMA0_BASE 0x40020000UL +//#define DMA1_BASE 0x40020400UL +//#define EXMC_BASE 0xA0000000UL +//#define EXTI_BASE 0x40010400UL +//#define FMC_BASE 0x40022000UL +//#define FWDGT_BASE 0x40003000UL +//#define GPIOA_BASE 0x40010800UL +//#define GPIOB_BASE 0x40010C00UL +//#define GPIOC_BASE 0x40011000UL +//#define GPIOD_BASE 0x40011400UL +//#define GPIOE_BASE 0x40011800UL +//#define I2C0_BASE 0x40005400UL +//#define I2C1_BASE 0x40005800UL +//#define ECLIC_BASE 0xD2000000UL +//#define PMU_BASE 0x40007000UL +//#define RCU_BASE 0x40021000UL +//#define RTC_BASE 0x40002800UL +//#define SPI0_BASE 0x40013000UL +//#define SPI1_BASE 0x40003800UL +//#define SPI2_BASE 0x40003C00UL +#define TIMER0_BASE 0x40012C00UL +#define TIMER1_BASE 0x40000000UL +#define TIMER2_BASE 0x40000400UL +#define TIMER3_BASE 0x40000800UL +#define TIMER4_BASE 0x40000C00UL +#define TIMER5_BASE 0x40001000UL +#define TIMER6_BASE 0x40001400UL +#define USART0_BASE 0x40013800UL +#define USART1_BASE 0x40004400UL +#define USART2_BASE 0x40004800UL +//#define UART3_BASE 0x40004C00UL +//#define UART4_BASE 0x40005000UL +//#define USBFS_GLOBAL_BASE 0x50000000UL +//#define USBFS_HOST_BASE 0x50000400UL +//#define USBFS_DEVICE_BASE 0x50000800UL +//#define USBFS_PWRCLK_BASE 0x50000E00UL +//#define WWDGT_BASE 0x40002C00UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define ADC0 ((ADC0_Type*) ADC0_BASE) +#define ADC1 ((ADC1_Type*) ADC1_BASE) +#define AFIO ((AFIO_Type*) AFIO_BASE) +#define BKP ((BKP_Type*) BKP_BASE) +#define CAN0 ((CAN0_Type*) CAN0_BASE) +#define CAN1 ((CAN0_Type*) CAN1_BASE) +#define CRC ((CRC_Type*) CRC_BASE) +#define DAC ((DAC_Type*) DAC_BASE) +#define DBG ((DBG_Type*) DBG_BASE) +#define DMA0 ((DMA0_Type*) DMA0_BASE) +#define DMA1 ((DMA1_Type*) DMA1_BASE) +#define EXMC ((EXMC_Type*) EXMC_BASE) +#define EXTI ((EXTI_Type*) EXTI_BASE) +#define FMC ((FMC_Type*) FMC_BASE) +#define FWDGT ((FWDGT_Type*) FWDGT_BASE) +#define GPIOA ((GPIO_Type*) GPIOA_BASE) +#define GPIOB ((GPIO_Type*) GPIOB_BASE) +#define GPIOC ((GPIO_Type*) GPIOC_BASE) +#define GPIOD ((GPIO_Type*) GPIOD_BASE) +#define GPIOE ((GPIO_Type*) GPIOE_BASE) +#define I2C0 ((I2C_Type*) I2C0_BASE) +#define I2C1 ((I2C_Type*) I2C1_BASE) +#define ECLIC ((ECLIC_Type*) ECLIC_BASE) +#define PMU ((PMU_Type*) PMU_BASE) +#define RCU ((RCU_Type*) RCU_BASE) +#define RTC ((RTC_Type*) RTC_BASE) +#define SPI0 ((SPI_Type*) SPI0_BASE) +#define SPI1 ((SPI_Type*) SPI1_BASE) +#define SPI2 ((SPI_Type*) SPI2_BASE) +#define TIMER0 ((TIMER_Type*) TIMER0_BASE) +#define TIMER1 ((TIMER_Type*) TIMER1_BASE) +#define TIMER2 ((TIMER_Type*) TIMER2_BASE) +#define TIMER3 ((TIMER_Type*) TIMER3_BASE) +#define TIMER4 ((TIMER_Type*) TIMER4_BASE) +#define TIMER5 ((TIMER_Type*) TIMER5_BASE) +#define TIMER6 ((TIMER_Type*) TIMER6_BASE) +#define USART0 ((USART_Type*) USART0_BASE) +#define USART1 ((USART_Type*) USART1_BASE) +#define USART2 ((USART_Type*) USART2_BASE) +#define UART3 ((UART_Type*) UART3_BASE) +#define UART4 ((UART_Type*) UART4_BASE) +#define USBFS_GLOBAL ((USBFS_GLOBAL_Type*) USBFS_GLOBAL_BASE) +#define USBFS_HOST ((USBFS_HOST_Type*) USBFS_HOST_BASE) +#define USBFS_DEVICE ((USBFS_DEVICE_Type*) USBFS_DEVICE_BASE) +#define USBFS_PWRCLK ((USBFS_PWRCLK_Type*) USBFS_PWRCLK_BASE) +#define WWDGT ((WWDGT_Type*) WWDGT_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup PosMask_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ ADC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ +#define ADC0_STAT_STRC_Pos (4UL) /*!< STRC (Bit 4) */ +#define ADC0_STAT_STRC_Msk (0x10UL) /*!< STRC (Bitfield-Mask: 0x01) */ +#define ADC0_STAT_STIC_Pos (3UL) /*!< STIC (Bit 3) */ +#define ADC0_STAT_STIC_Msk (0x8UL) /*!< STIC (Bitfield-Mask: 0x01) */ +#define ADC0_STAT_EOIC_Pos (2UL) /*!< EOIC (Bit 2) */ +#define ADC0_STAT_EOIC_Msk (0x4UL) /*!< EOIC (Bitfield-Mask: 0x01) */ +#define ADC0_STAT_EOC_Pos (1UL) /*!< EOC (Bit 1) */ +#define ADC0_STAT_EOC_Msk (0x2UL) /*!< EOC (Bitfield-Mask: 0x01) */ +#define ADC0_STAT_WDE_Pos (0UL) /*!< WDE (Bit 0) */ +#define ADC0_STAT_WDE_Msk (0x1UL) /*!< WDE (Bitfield-Mask: 0x01) */ +/* ========================================================= CTL0 ========================================================== */ +#define ADC0_CTL0_RWDEN_Pos (23UL) /*!< RWDEN (Bit 23) */ +#define ADC0_CTL0_RWDEN_Msk (0x800000UL) /*!< RWDEN (Bitfield-Mask: 0x01) */ +#define ADC0_CTL0_IWDEN_Pos (22UL) /*!< IWDEN (Bit 22) */ +#define ADC0_CTL0_IWDEN_Msk (0x400000UL) /*!< IWDEN (Bitfield-Mask: 0x01) */ +#define ADC0_CTL0_SYNCM_Pos (16UL) /*!< SYNCM (Bit 16) */ +#define ADC0_CTL0_SYNCM_Msk (0xf0000UL) /*!< SYNCM (Bitfield-Mask: 0x0f) */ +#define ADC0_CTL0_DISNUM_Pos (13UL) /*!< DISNUM (Bit 13) */ +#define ADC0_CTL0_DISNUM_Msk (0xe000UL) /*!< DISNUM (Bitfield-Mask: 0x07) */ +#define ADC0_CTL0_DISIC_Pos (12UL) /*!< DISIC (Bit 12) */ +#define ADC0_CTL0_DISIC_Msk (0x1000UL) /*!< DISIC (Bitfield-Mask: 0x01) */ +#define ADC0_CTL0_DISRC_Pos (11UL) /*!< DISRC (Bit 11) */ +#define ADC0_CTL0_DISRC_Msk (0x800UL) /*!< DISRC (Bitfield-Mask: 0x01) */ +#define ADC0_CTL0_ICA_Pos (10UL) /*!< ICA (Bit 10) */ +#define ADC0_CTL0_ICA_Msk (0x400UL) /*!< ICA (Bitfield-Mask: 0x01) */ +#define ADC0_CTL0_WDSC_Pos (9UL) /*!< WDSC (Bit 9) */ +#define ADC0_CTL0_WDSC_Msk (0x200UL) /*!< WDSC (Bitfield-Mask: 0x01) */ +#define ADC0_CTL0_SM_Pos (8UL) /*!< SM (Bit 8) */ +#define ADC0_CTL0_SM_Msk (0x100UL) /*!< SM (Bitfield-Mask: 0x01) */ +#define ADC0_CTL0_EOICIE_Pos (7UL) /*!< EOICIE (Bit 7) */ +#define ADC0_CTL0_EOICIE_Msk (0x80UL) /*!< EOICIE (Bitfield-Mask: 0x01) */ +#define ADC0_CTL0_WDEIE_Pos (6UL) /*!< WDEIE (Bit 6) */ +#define ADC0_CTL0_WDEIE_Msk (0x40UL) /*!< WDEIE (Bitfield-Mask: 0x01) */ +#define ADC0_CTL0_EOCIE_Pos (5UL) /*!< EOCIE (Bit 5) */ +#define ADC0_CTL0_EOCIE_Msk (0x20UL) /*!< EOCIE (Bitfield-Mask: 0x01) */ +#define ADC0_CTL0_WDCHSEL_Pos (0UL) /*!< WDCHSEL (Bit 0) */ +#define ADC0_CTL0_WDCHSEL_Msk (0x1fUL) /*!< WDCHSEL (Bitfield-Mask: 0x1f) */ +/* ========================================================= CTL1 ========================================================== */ +#define ADC0_CTL1_TSVREN_Pos (23UL) /*!< TSVREN (Bit 23) */ +#define ADC0_CTL1_TSVREN_Msk (0x800000UL) /*!< TSVREN (Bitfield-Mask: 0x01) */ +#define ADC0_CTL1_SWRCST_Pos (22UL) /*!< SWRCST (Bit 22) */ +#define ADC0_CTL1_SWRCST_Msk (0x400000UL) /*!< SWRCST (Bitfield-Mask: 0x01) */ +#define ADC0_CTL1_SWICST_Pos (21UL) /*!< SWICST (Bit 21) */ +#define ADC0_CTL1_SWICST_Msk (0x200000UL) /*!< SWICST (Bitfield-Mask: 0x01) */ +#define ADC0_CTL1_ETERC_Pos (20UL) /*!< ETERC (Bit 20) */ +#define ADC0_CTL1_ETERC_Msk (0x100000UL) /*!< ETERC (Bitfield-Mask: 0x01) */ +#define ADC0_CTL1_ETSRC_Pos (17UL) /*!< ETSRC (Bit 17) */ +#define ADC0_CTL1_ETSRC_Msk (0xe0000UL) /*!< ETSRC (Bitfield-Mask: 0x07) */ +#define ADC0_CTL1_ETEIC_Pos (15UL) /*!< ETEIC (Bit 15) */ +#define ADC0_CTL1_ETEIC_Msk (0x8000UL) /*!< ETEIC (Bitfield-Mask: 0x01) */ +#define ADC0_CTL1_ETSIC_Pos (12UL) /*!< ETSIC (Bit 12) */ +#define ADC0_CTL1_ETSIC_Msk (0x7000UL) /*!< ETSIC (Bitfield-Mask: 0x07) */ +#define ADC0_CTL1_DAL_Pos (11UL) /*!< DAL (Bit 11) */ +#define ADC0_CTL1_DAL_Msk (0x800UL) /*!< DAL (Bitfield-Mask: 0x01) */ +#define ADC0_CTL1_DMA_Pos (8UL) /*!< DMA (Bit 8) */ +#define ADC0_CTL1_DMA_Msk (0x100UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ADC0_CTL1_RSTCLB_Pos (3UL) /*!< RSTCLB (Bit 3) */ +#define ADC0_CTL1_RSTCLB_Msk (0x8UL) /*!< RSTCLB (Bitfield-Mask: 0x01) */ +#define ADC0_CTL1_CLB_Pos (2UL) /*!< CLB (Bit 2) */ +#define ADC0_CTL1_CLB_Msk (0x4UL) /*!< CLB (Bitfield-Mask: 0x01) */ +#define ADC0_CTL1_CTN_Pos (1UL) /*!< CTN (Bit 1) */ +#define ADC0_CTL1_CTN_Msk (0x2UL) /*!< CTN (Bitfield-Mask: 0x01) */ +#define ADC0_CTL1_ADCON_Pos (0UL) /*!< ADCON (Bit 0) */ +#define ADC0_CTL1_ADCON_Msk (0x1UL) /*!< ADCON (Bitfield-Mask: 0x01) */ +/* ======================================================== SAMPT0 ========================================================= */ +#define ADC0_SAMPT0_SPT10_Pos (0UL) /*!< SPT10 (Bit 0) */ +#define ADC0_SAMPT0_SPT10_Msk (0x7UL) /*!< SPT10 (Bitfield-Mask: 0x07) */ +#define ADC0_SAMPT0_SPT11_Pos (3UL) /*!< SPT11 (Bit 3) */ +#define ADC0_SAMPT0_SPT11_Msk (0x38UL) /*!< SPT11 (Bitfield-Mask: 0x07) */ +#define ADC0_SAMPT0_SPT12_Pos (6UL) /*!< SPT12 (Bit 6) */ +#define ADC0_SAMPT0_SPT12_Msk (0x1c0UL) /*!< SPT12 (Bitfield-Mask: 0x07) */ +#define ADC0_SAMPT0_SPT13_Pos (9UL) /*!< SPT13 (Bit 9) */ +#define ADC0_SAMPT0_SPT13_Msk (0xe00UL) /*!< SPT13 (Bitfield-Mask: 0x07) */ +#define ADC0_SAMPT0_SPT14_Pos (12UL) /*!< SPT14 (Bit 12) */ +#define ADC0_SAMPT0_SPT14_Msk (0x7000UL) /*!< SPT14 (Bitfield-Mask: 0x07) */ +#define ADC0_SAMPT0_SPT15_Pos (15UL) /*!< SPT15 (Bit 15) */ +#define ADC0_SAMPT0_SPT15_Msk (0x38000UL) /*!< SPT15 (Bitfield-Mask: 0x07) */ +#define ADC0_SAMPT0_SPT16_Pos (18UL) /*!< SPT16 (Bit 18) */ +#define ADC0_SAMPT0_SPT16_Msk (0x1c0000UL) /*!< SPT16 (Bitfield-Mask: 0x07) */ +#define ADC0_SAMPT0_SPT17_Pos (21UL) /*!< SPT17 (Bit 21) */ +#define ADC0_SAMPT0_SPT17_Msk (0xe00000UL) /*!< SPT17 (Bitfield-Mask: 0x07) */ +/* ======================================================== SAMPT1 ========================================================= */ +#define ADC0_SAMPT1_SPT0_Pos (0UL) /*!< SPT0 (Bit 0) */ +#define ADC0_SAMPT1_SPT0_Msk (0x7UL) /*!< SPT0 (Bitfield-Mask: 0x07) */ +#define ADC0_SAMPT1_SPT1_Pos (3UL) /*!< SPT1 (Bit 3) */ +#define ADC0_SAMPT1_SPT1_Msk (0x38UL) /*!< SPT1 (Bitfield-Mask: 0x07) */ +#define ADC0_SAMPT1_SPT2_Pos (6UL) /*!< SPT2 (Bit 6) */ +#define ADC0_SAMPT1_SPT2_Msk (0x1c0UL) /*!< SPT2 (Bitfield-Mask: 0x07) */ +#define ADC0_SAMPT1_SPT3_Pos (9UL) /*!< SPT3 (Bit 9) */ +#define ADC0_SAMPT1_SPT3_Msk (0xe00UL) /*!< SPT3 (Bitfield-Mask: 0x07) */ +#define ADC0_SAMPT1_SPT4_Pos (12UL) /*!< SPT4 (Bit 12) */ +#define ADC0_SAMPT1_SPT4_Msk (0x7000UL) /*!< SPT4 (Bitfield-Mask: 0x07) */ +#define ADC0_SAMPT1_SPT5_Pos (15UL) /*!< SPT5 (Bit 15) */ +#define ADC0_SAMPT1_SPT5_Msk (0x38000UL) /*!< SPT5 (Bitfield-Mask: 0x07) */ +#define ADC0_SAMPT1_SPT6_Pos (18UL) /*!< SPT6 (Bit 18) */ +#define ADC0_SAMPT1_SPT6_Msk (0x1c0000UL) /*!< SPT6 (Bitfield-Mask: 0x07) */ +#define ADC0_SAMPT1_SPT7_Pos (21UL) /*!< SPT7 (Bit 21) */ +#define ADC0_SAMPT1_SPT7_Msk (0xe00000UL) /*!< SPT7 (Bitfield-Mask: 0x07) */ +#define ADC0_SAMPT1_SPT8_Pos (24UL) /*!< SPT8 (Bit 24) */ +#define ADC0_SAMPT1_SPT8_Msk (0x7000000UL) /*!< SPT8 (Bitfield-Mask: 0x07) */ +#define ADC0_SAMPT1_SPT9_Pos (27UL) /*!< SPT9 (Bit 27) */ +#define ADC0_SAMPT1_SPT9_Msk (0x38000000UL) /*!< SPT9 (Bitfield-Mask: 0x07) */ +/* ========================================================= IOFF0 ========================================================= */ +#define ADC0_IOFF0_IOFF_Pos (0UL) /*!< IOFF (Bit 0) */ +#define ADC0_IOFF0_IOFF_Msk (0xfffUL) /*!< IOFF (Bitfield-Mask: 0xfff) */ +/* ========================================================= IOFF1 ========================================================= */ +#define ADC0_IOFF1_IOFF_Pos (0UL) /*!< IOFF (Bit 0) */ +#define ADC0_IOFF1_IOFF_Msk (0xfffUL) /*!< IOFF (Bitfield-Mask: 0xfff) */ +/* ========================================================= IOFF2 ========================================================= */ +#define ADC0_IOFF2_IOFF_Pos (0UL) /*!< IOFF (Bit 0) */ +#define ADC0_IOFF2_IOFF_Msk (0xfffUL) /*!< IOFF (Bitfield-Mask: 0xfff) */ +/* ========================================================= IOFF3 ========================================================= */ +#define ADC0_IOFF3_IOFF_Pos (0UL) /*!< IOFF (Bit 0) */ +#define ADC0_IOFF3_IOFF_Msk (0xfffUL) /*!< IOFF (Bitfield-Mask: 0xfff) */ +/* ========================================================= WDHT ========================================================== */ +#define ADC0_WDHT_WDHT_Pos (0UL) /*!< WDHT (Bit 0) */ +#define ADC0_WDHT_WDHT_Msk (0xfffUL) /*!< WDHT (Bitfield-Mask: 0xfff) */ +/* ========================================================= WDLT ========================================================== */ +#define ADC0_WDLT_WDLT_Pos (0UL) /*!< WDLT (Bit 0) */ +#define ADC0_WDLT_WDLT_Msk (0xfffUL) /*!< WDLT (Bitfield-Mask: 0xfff) */ +/* ========================================================= RSQ0 ========================================================== */ +#define ADC0_RSQ0_RL_Pos (20UL) /*!< RL (Bit 20) */ +#define ADC0_RSQ0_RL_Msk (0xf00000UL) /*!< RL (Bitfield-Mask: 0x0f) */ +#define ADC0_RSQ0_RSQ15_Pos (15UL) /*!< RSQ15 (Bit 15) */ +#define ADC0_RSQ0_RSQ15_Msk (0xf8000UL) /*!< RSQ15 (Bitfield-Mask: 0x1f) */ +#define ADC0_RSQ0_RSQ14_Pos (10UL) /*!< RSQ14 (Bit 10) */ +#define ADC0_RSQ0_RSQ14_Msk (0x7c00UL) /*!< RSQ14 (Bitfield-Mask: 0x1f) */ +#define ADC0_RSQ0_RSQ13_Pos (5UL) /*!< RSQ13 (Bit 5) */ +#define ADC0_RSQ0_RSQ13_Msk (0x3e0UL) /*!< RSQ13 (Bitfield-Mask: 0x1f) */ +#define ADC0_RSQ0_RSQ12_Pos (0UL) /*!< RSQ12 (Bit 0) */ +#define ADC0_RSQ0_RSQ12_Msk (0x1fUL) /*!< RSQ12 (Bitfield-Mask: 0x1f) */ +/* ========================================================= RSQ1 ========================================================== */ +#define ADC0_RSQ1_RSQ11_Pos (25UL) /*!< RSQ11 (Bit 25) */ +#define ADC0_RSQ1_RSQ11_Msk (0x3e000000UL) /*!< RSQ11 (Bitfield-Mask: 0x1f) */ +#define ADC0_RSQ1_RSQ10_Pos (20UL) /*!< RSQ10 (Bit 20) */ +#define ADC0_RSQ1_RSQ10_Msk (0x1f00000UL) /*!< RSQ10 (Bitfield-Mask: 0x1f) */ +#define ADC0_RSQ1_RSQ9_Pos (15UL) /*!< RSQ9 (Bit 15) */ +#define ADC0_RSQ1_RSQ9_Msk (0xf8000UL) /*!< RSQ9 (Bitfield-Mask: 0x1f) */ +#define ADC0_RSQ1_RSQ8_Pos (10UL) /*!< RSQ8 (Bit 10) */ +#define ADC0_RSQ1_RSQ8_Msk (0x7c00UL) /*!< RSQ8 (Bitfield-Mask: 0x1f) */ +#define ADC0_RSQ1_RSQ7_Pos (5UL) /*!< RSQ7 (Bit 5) */ +#define ADC0_RSQ1_RSQ7_Msk (0x3e0UL) /*!< RSQ7 (Bitfield-Mask: 0x1f) */ +#define ADC0_RSQ1_RSQ6_Pos (0UL) /*!< RSQ6 (Bit 0) */ +#define ADC0_RSQ1_RSQ6_Msk (0x1fUL) /*!< RSQ6 (Bitfield-Mask: 0x1f) */ +/* ========================================================= RSQ2 ========================================================== */ +#define ADC0_RSQ2_RSQ5_Pos (25UL) /*!< RSQ5 (Bit 25) */ +#define ADC0_RSQ2_RSQ5_Msk (0x3e000000UL) /*!< RSQ5 (Bitfield-Mask: 0x1f) */ +#define ADC0_RSQ2_RSQ4_Pos (20UL) /*!< RSQ4 (Bit 20) */ +#define ADC0_RSQ2_RSQ4_Msk (0x1f00000UL) /*!< RSQ4 (Bitfield-Mask: 0x1f) */ +#define ADC0_RSQ2_RSQ3_Pos (15UL) /*!< RSQ3 (Bit 15) */ +#define ADC0_RSQ2_RSQ3_Msk (0xf8000UL) /*!< RSQ3 (Bitfield-Mask: 0x1f) */ +#define ADC0_RSQ2_RSQ2_Pos (10UL) /*!< RSQ2 (Bit 10) */ +#define ADC0_RSQ2_RSQ2_Msk (0x7c00UL) /*!< RSQ2 (Bitfield-Mask: 0x1f) */ +#define ADC0_RSQ2_RSQ1_Pos (5UL) /*!< RSQ1 (Bit 5) */ +#define ADC0_RSQ2_RSQ1_Msk (0x3e0UL) /*!< RSQ1 (Bitfield-Mask: 0x1f) */ +#define ADC0_RSQ2_RSQ0_Pos (0UL) /*!< RSQ0 (Bit 0) */ +#define ADC0_RSQ2_RSQ0_Msk (0x1fUL) /*!< RSQ0 (Bitfield-Mask: 0x1f) */ +/* ========================================================== ISQ ========================================================== */ +#define ADC0_ISQ_IL_Pos (20UL) /*!< IL (Bit 20) */ +#define ADC0_ISQ_IL_Msk (0x300000UL) /*!< IL (Bitfield-Mask: 0x03) */ +#define ADC0_ISQ_ISQ3_Pos (15UL) /*!< ISQ3 (Bit 15) */ +#define ADC0_ISQ_ISQ3_Msk (0xf8000UL) /*!< ISQ3 (Bitfield-Mask: 0x1f) */ +#define ADC0_ISQ_ISQ2_Pos (10UL) /*!< ISQ2 (Bit 10) */ +#define ADC0_ISQ_ISQ2_Msk (0x7c00UL) /*!< ISQ2 (Bitfield-Mask: 0x1f) */ +#define ADC0_ISQ_ISQ1_Pos (5UL) /*!< ISQ1 (Bit 5) */ +#define ADC0_ISQ_ISQ1_Msk (0x3e0UL) /*!< ISQ1 (Bitfield-Mask: 0x1f) */ +#define ADC0_ISQ_ISQ0_Pos (0UL) /*!< ISQ0 (Bit 0) */ +#define ADC0_ISQ_ISQ0_Msk (0x1fUL) /*!< ISQ0 (Bitfield-Mask: 0x1f) */ +/* ======================================================== IDATA0 ========================================================= */ +#define ADC0_IDATA0_IDATAn_Pos (0UL) /*!< IDATAn (Bit 0) */ +#define ADC0_IDATA0_IDATAn_Msk (0xffffUL) /*!< IDATAn (Bitfield-Mask: 0xffff) */ +/* ======================================================== IDATA1 ========================================================= */ +#define ADC0_IDATA1_IDATAn_Pos (0UL) /*!< IDATAn (Bit 0) */ +#define ADC0_IDATA1_IDATAn_Msk (0xffffUL) /*!< IDATAn (Bitfield-Mask: 0xffff) */ +/* ======================================================== IDATA2 ========================================================= */ +#define ADC0_IDATA2_IDATAn_Pos (0UL) /*!< IDATAn (Bit 0) */ +#define ADC0_IDATA2_IDATAn_Msk (0xffffUL) /*!< IDATAn (Bitfield-Mask: 0xffff) */ +/* ======================================================== IDATA3 ========================================================= */ +#define ADC0_IDATA3_IDATAn_Pos (0UL) /*!< IDATAn (Bit 0) */ +#define ADC0_IDATA3_IDATAn_Msk (0xffffUL) /*!< IDATAn (Bitfield-Mask: 0xffff) */ +/* ========================================================= RDATA ========================================================= */ +#define ADC0_RDATA_ADC1RDTR_Pos (16UL) /*!< ADC1RDTR (Bit 16) */ +#define ADC0_RDATA_ADC1RDTR_Msk (0xffff0000UL) /*!< ADC1RDTR (Bitfield-Mask: 0xffff) */ +#define ADC0_RDATA_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */ +#define ADC0_RDATA_RDATA_Msk (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff) */ +/* ======================================================= OVSAMPCTL ======================================================= */ +#define ADC0_OVSAMPCTL_DRES_Pos (12UL) /*!< DRES (Bit 12) */ +#define ADC0_OVSAMPCTL_DRES_Msk (0x3000UL) /*!< DRES (Bitfield-Mask: 0x03) */ +#define ADC0_OVSAMPCTL_TOVS_Pos (9UL) /*!< TOVS (Bit 9) */ +#define ADC0_OVSAMPCTL_TOVS_Msk (0x200UL) /*!< TOVS (Bitfield-Mask: 0x01) */ +#define ADC0_OVSAMPCTL_OVSS_Pos (5UL) /*!< OVSS (Bit 5) */ +#define ADC0_OVSAMPCTL_OVSS_Msk (0x1e0UL) /*!< OVSS (Bitfield-Mask: 0x0f) */ +#define ADC0_OVSAMPCTL_OVSR_Pos (2UL) /*!< OVSR (Bit 2) */ +#define ADC0_OVSAMPCTL_OVSR_Msk (0x1cUL) /*!< OVSR (Bitfield-Mask: 0x07) */ +#define ADC0_OVSAMPCTL_OVSEN_Pos (0UL) /*!< OVSEN (Bit 0) */ +#define ADC0_OVSAMPCTL_OVSEN_Msk (0x1UL) /*!< OVSEN (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ ADC1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ +#define ADC1_STAT_STRC_Pos (4UL) /*!< STRC (Bit 4) */ +#define ADC1_STAT_STRC_Msk (0x10UL) /*!< STRC (Bitfield-Mask: 0x01) */ +#define ADC1_STAT_STIC_Pos (3UL) /*!< STIC (Bit 3) */ +#define ADC1_STAT_STIC_Msk (0x8UL) /*!< STIC (Bitfield-Mask: 0x01) */ +#define ADC1_STAT_EOIC_Pos (2UL) /*!< EOIC (Bit 2) */ +#define ADC1_STAT_EOIC_Msk (0x4UL) /*!< EOIC (Bitfield-Mask: 0x01) */ +#define ADC1_STAT_EOC_Pos (1UL) /*!< EOC (Bit 1) */ +#define ADC1_STAT_EOC_Msk (0x2UL) /*!< EOC (Bitfield-Mask: 0x01) */ +#define ADC1_STAT_WDE_Pos (0UL) /*!< WDE (Bit 0) */ +#define ADC1_STAT_WDE_Msk (0x1UL) /*!< WDE (Bitfield-Mask: 0x01) */ +/* ========================================================= CTL0 ========================================================== */ +#define ADC1_CTL0_RWDEN_Pos (23UL) /*!< RWDEN (Bit 23) */ +#define ADC1_CTL0_RWDEN_Msk (0x800000UL) /*!< RWDEN (Bitfield-Mask: 0x01) */ +#define ADC1_CTL0_IWDEN_Pos (22UL) /*!< IWDEN (Bit 22) */ +#define ADC1_CTL0_IWDEN_Msk (0x400000UL) /*!< IWDEN (Bitfield-Mask: 0x01) */ +#define ADC1_CTL0_DISNUM_Pos (13UL) /*!< DISNUM (Bit 13) */ +#define ADC1_CTL0_DISNUM_Msk (0xe000UL) /*!< DISNUM (Bitfield-Mask: 0x07) */ +#define ADC1_CTL0_DISIC_Pos (12UL) /*!< DISIC (Bit 12) */ +#define ADC1_CTL0_DISIC_Msk (0x1000UL) /*!< DISIC (Bitfield-Mask: 0x01) */ +#define ADC1_CTL0_DISRC_Pos (11UL) /*!< DISRC (Bit 11) */ +#define ADC1_CTL0_DISRC_Msk (0x800UL) /*!< DISRC (Bitfield-Mask: 0x01) */ +#define ADC1_CTL0_ICA_Pos (10UL) /*!< ICA (Bit 10) */ +#define ADC1_CTL0_ICA_Msk (0x400UL) /*!< ICA (Bitfield-Mask: 0x01) */ +#define ADC1_CTL0_WDSC_Pos (9UL) /*!< WDSC (Bit 9) */ +#define ADC1_CTL0_WDSC_Msk (0x200UL) /*!< WDSC (Bitfield-Mask: 0x01) */ +#define ADC1_CTL0_SM_Pos (8UL) /*!< SM (Bit 8) */ +#define ADC1_CTL0_SM_Msk (0x100UL) /*!< SM (Bitfield-Mask: 0x01) */ +#define ADC1_CTL0_EOICIE_Pos (7UL) /*!< EOICIE (Bit 7) */ +#define ADC1_CTL0_EOICIE_Msk (0x80UL) /*!< EOICIE (Bitfield-Mask: 0x01) */ +#define ADC1_CTL0_WDEIE_Pos (6UL) /*!< WDEIE (Bit 6) */ +#define ADC1_CTL0_WDEIE_Msk (0x40UL) /*!< WDEIE (Bitfield-Mask: 0x01) */ +#define ADC1_CTL0_EOCIE_Pos (5UL) /*!< EOCIE (Bit 5) */ +#define ADC1_CTL0_EOCIE_Msk (0x20UL) /*!< EOCIE (Bitfield-Mask: 0x01) */ +#define ADC1_CTL0_WDCHSEL_Pos (0UL) /*!< WDCHSEL (Bit 0) */ +#define ADC1_CTL0_WDCHSEL_Msk (0x1fUL) /*!< WDCHSEL (Bitfield-Mask: 0x1f) */ +/* ========================================================= CTL1 ========================================================== */ +#define ADC1_CTL1_SWRCST_Pos (22UL) /*!< SWRCST (Bit 22) */ +#define ADC1_CTL1_SWRCST_Msk (0x400000UL) /*!< SWRCST (Bitfield-Mask: 0x01) */ +#define ADC1_CTL1_SWICST_Pos (21UL) /*!< SWICST (Bit 21) */ +#define ADC1_CTL1_SWICST_Msk (0x200000UL) /*!< SWICST (Bitfield-Mask: 0x01) */ +#define ADC1_CTL1_ETERC_Pos (20UL) /*!< ETERC (Bit 20) */ +#define ADC1_CTL1_ETERC_Msk (0x100000UL) /*!< ETERC (Bitfield-Mask: 0x01) */ +#define ADC1_CTL1_ETSRC_Pos (17UL) /*!< ETSRC (Bit 17) */ +#define ADC1_CTL1_ETSRC_Msk (0xe0000UL) /*!< ETSRC (Bitfield-Mask: 0x07) */ +#define ADC1_CTL1_ETEIC_Pos (15UL) /*!< ETEIC (Bit 15) */ +#define ADC1_CTL1_ETEIC_Msk (0x8000UL) /*!< ETEIC (Bitfield-Mask: 0x01) */ +#define ADC1_CTL1_ETSIC_Pos (12UL) /*!< ETSIC (Bit 12) */ +#define ADC1_CTL1_ETSIC_Msk (0x7000UL) /*!< ETSIC (Bitfield-Mask: 0x07) */ +#define ADC1_CTL1_DAL_Pos (11UL) /*!< DAL (Bit 11) */ +#define ADC1_CTL1_DAL_Msk (0x800UL) /*!< DAL (Bitfield-Mask: 0x01) */ +#define ADC1_CTL1_DMA_Pos (8UL) /*!< DMA (Bit 8) */ +#define ADC1_CTL1_DMA_Msk (0x100UL) /*!< DMA (Bitfield-Mask: 0x01) */ +#define ADC1_CTL1_RSTCLB_Pos (3UL) /*!< RSTCLB (Bit 3) */ +#define ADC1_CTL1_RSTCLB_Msk (0x8UL) /*!< RSTCLB (Bitfield-Mask: 0x01) */ +#define ADC1_CTL1_CLB_Pos (2UL) /*!< CLB (Bit 2) */ +#define ADC1_CTL1_CLB_Msk (0x4UL) /*!< CLB (Bitfield-Mask: 0x01) */ +#define ADC1_CTL1_CTN_Pos (1UL) /*!< CTN (Bit 1) */ +#define ADC1_CTL1_CTN_Msk (0x2UL) /*!< CTN (Bitfield-Mask: 0x01) */ +#define ADC1_CTL1_ADCON_Pos (0UL) /*!< ADCON (Bit 0) */ +#define ADC1_CTL1_ADCON_Msk (0x1UL) /*!< ADCON (Bitfield-Mask: 0x01) */ +/* ======================================================== SAMPT0 ========================================================= */ +#define ADC1_SAMPT0_SPT10_Pos (0UL) /*!< SPT10 (Bit 0) */ +#define ADC1_SAMPT0_SPT10_Msk (0x7UL) /*!< SPT10 (Bitfield-Mask: 0x07) */ +#define ADC1_SAMPT0_SPT11_Pos (3UL) /*!< SPT11 (Bit 3) */ +#define ADC1_SAMPT0_SPT11_Msk (0x38UL) /*!< SPT11 (Bitfield-Mask: 0x07) */ +#define ADC1_SAMPT0_SPT12_Pos (6UL) /*!< SPT12 (Bit 6) */ +#define ADC1_SAMPT0_SPT12_Msk (0x1c0UL) /*!< SPT12 (Bitfield-Mask: 0x07) */ +#define ADC1_SAMPT0_SPT13_Pos (9UL) /*!< SPT13 (Bit 9) */ +#define ADC1_SAMPT0_SPT13_Msk (0xe00UL) /*!< SPT13 (Bitfield-Mask: 0x07) */ +#define ADC1_SAMPT0_SPT14_Pos (12UL) /*!< SPT14 (Bit 12) */ +#define ADC1_SAMPT0_SPT14_Msk (0x7000UL) /*!< SPT14 (Bitfield-Mask: 0x07) */ +#define ADC1_SAMPT0_SPT15_Pos (15UL) /*!< SPT15 (Bit 15) */ +#define ADC1_SAMPT0_SPT15_Msk (0x38000UL) /*!< SPT15 (Bitfield-Mask: 0x07) */ +#define ADC1_SAMPT0_SPT16_Pos (18UL) /*!< SPT16 (Bit 18) */ +#define ADC1_SAMPT0_SPT16_Msk (0x1c0000UL) /*!< SPT16 (Bitfield-Mask: 0x07) */ +#define ADC1_SAMPT0_SPT17_Pos (21UL) /*!< SPT17 (Bit 21) */ +#define ADC1_SAMPT0_SPT17_Msk (0xe00000UL) /*!< SPT17 (Bitfield-Mask: 0x07) */ +/* ======================================================== SAMPT1 ========================================================= */ +#define ADC1_SAMPT1_SPT0_Pos (0UL) /*!< SPT0 (Bit 0) */ +#define ADC1_SAMPT1_SPT0_Msk (0x7UL) /*!< SPT0 (Bitfield-Mask: 0x07) */ +#define ADC1_SAMPT1_SPT1_Pos (3UL) /*!< SPT1 (Bit 3) */ +#define ADC1_SAMPT1_SPT1_Msk (0x38UL) /*!< SPT1 (Bitfield-Mask: 0x07) */ +#define ADC1_SAMPT1_SPT2_Pos (6UL) /*!< SPT2 (Bit 6) */ +#define ADC1_SAMPT1_SPT2_Msk (0x1c0UL) /*!< SPT2 (Bitfield-Mask: 0x07) */ +#define ADC1_SAMPT1_SPT3_Pos (9UL) /*!< SPT3 (Bit 9) */ +#define ADC1_SAMPT1_SPT3_Msk (0xe00UL) /*!< SPT3 (Bitfield-Mask: 0x07) */ +#define ADC1_SAMPT1_SPT4_Pos (12UL) /*!< SPT4 (Bit 12) */ +#define ADC1_SAMPT1_SPT4_Msk (0x7000UL) /*!< SPT4 (Bitfield-Mask: 0x07) */ +#define ADC1_SAMPT1_SPT5_Pos (15UL) /*!< SPT5 (Bit 15) */ +#define ADC1_SAMPT1_SPT5_Msk (0x38000UL) /*!< SPT5 (Bitfield-Mask: 0x07) */ +#define ADC1_SAMPT1_SPT6_Pos (18UL) /*!< SPT6 (Bit 18) */ +#define ADC1_SAMPT1_SPT6_Msk (0x1c0000UL) /*!< SPT6 (Bitfield-Mask: 0x07) */ +#define ADC1_SAMPT1_SPT7_Pos (21UL) /*!< SPT7 (Bit 21) */ +#define ADC1_SAMPT1_SPT7_Msk (0xe00000UL) /*!< SPT7 (Bitfield-Mask: 0x07) */ +#define ADC1_SAMPT1_SPT8_Pos (24UL) /*!< SPT8 (Bit 24) */ +#define ADC1_SAMPT1_SPT8_Msk (0x7000000UL) /*!< SPT8 (Bitfield-Mask: 0x07) */ +#define ADC1_SAMPT1_SPT9_Pos (27UL) /*!< SPT9 (Bit 27) */ +#define ADC1_SAMPT1_SPT9_Msk (0x38000000UL) /*!< SPT9 (Bitfield-Mask: 0x07) */ +/* ========================================================= IOFF0 ========================================================= */ +#define ADC1_IOFF0_IOFF_Pos (0UL) /*!< IOFF (Bit 0) */ +#define ADC1_IOFF0_IOFF_Msk (0xfffUL) /*!< IOFF (Bitfield-Mask: 0xfff) */ +/* ========================================================= IOFF1 ========================================================= */ +#define ADC1_IOFF1_IOFF_Pos (0UL) /*!< IOFF (Bit 0) */ +#define ADC1_IOFF1_IOFF_Msk (0xfffUL) /*!< IOFF (Bitfield-Mask: 0xfff) */ +/* ========================================================= IOFF2 ========================================================= */ +#define ADC1_IOFF2_IOFF_Pos (0UL) /*!< IOFF (Bit 0) */ +#define ADC1_IOFF2_IOFF_Msk (0xfffUL) /*!< IOFF (Bitfield-Mask: 0xfff) */ +/* ========================================================= IOFF3 ========================================================= */ +#define ADC1_IOFF3_IOFF_Pos (0UL) /*!< IOFF (Bit 0) */ +#define ADC1_IOFF3_IOFF_Msk (0xfffUL) /*!< IOFF (Bitfield-Mask: 0xfff) */ +/* ========================================================= WDHT ========================================================== */ +#define ADC1_WDHT_WDHT_Pos (0UL) /*!< WDHT (Bit 0) */ +#define ADC1_WDHT_WDHT_Msk (0xfffUL) /*!< WDHT (Bitfield-Mask: 0xfff) */ +/* ========================================================= WDLT ========================================================== */ +#define ADC1_WDLT_WDLT_Pos (0UL) /*!< WDLT (Bit 0) */ +#define ADC1_WDLT_WDLT_Msk (0xfffUL) /*!< WDLT (Bitfield-Mask: 0xfff) */ +/* ========================================================= RSQ0 ========================================================== */ +#define ADC1_RSQ0_RL_Pos (20UL) /*!< RL (Bit 20) */ +#define ADC1_RSQ0_RL_Msk (0xf00000UL) /*!< RL (Bitfield-Mask: 0x0f) */ +#define ADC1_RSQ0_RSQ15_Pos (15UL) /*!< RSQ15 (Bit 15) */ +#define ADC1_RSQ0_RSQ15_Msk (0xf8000UL) /*!< RSQ15 (Bitfield-Mask: 0x1f) */ +#define ADC1_RSQ0_RSQ14_Pos (10UL) /*!< RSQ14 (Bit 10) */ +#define ADC1_RSQ0_RSQ14_Msk (0x7c00UL) /*!< RSQ14 (Bitfield-Mask: 0x1f) */ +#define ADC1_RSQ0_RSQ13_Pos (5UL) /*!< RSQ13 (Bit 5) */ +#define ADC1_RSQ0_RSQ13_Msk (0x3e0UL) /*!< RSQ13 (Bitfield-Mask: 0x1f) */ +#define ADC1_RSQ0_RSQ12_Pos (0UL) /*!< RSQ12 (Bit 0) */ +#define ADC1_RSQ0_RSQ12_Msk (0x1fUL) /*!< RSQ12 (Bitfield-Mask: 0x1f) */ +/* ========================================================= RSQ1 ========================================================== */ +#define ADC1_RSQ1_RSQ11_Pos (25UL) /*!< RSQ11 (Bit 25) */ +#define ADC1_RSQ1_RSQ11_Msk (0x3e000000UL) /*!< RSQ11 (Bitfield-Mask: 0x1f) */ +#define ADC1_RSQ1_RSQ10_Pos (20UL) /*!< RSQ10 (Bit 20) */ +#define ADC1_RSQ1_RSQ10_Msk (0x1f00000UL) /*!< RSQ10 (Bitfield-Mask: 0x1f) */ +#define ADC1_RSQ1_RSQ9_Pos (15UL) /*!< RSQ9 (Bit 15) */ +#define ADC1_RSQ1_RSQ9_Msk (0xf8000UL) /*!< RSQ9 (Bitfield-Mask: 0x1f) */ +#define ADC1_RSQ1_RSQ8_Pos (10UL) /*!< RSQ8 (Bit 10) */ +#define ADC1_RSQ1_RSQ8_Msk (0x7c00UL) /*!< RSQ8 (Bitfield-Mask: 0x1f) */ +#define ADC1_RSQ1_RSQ7_Pos (5UL) /*!< RSQ7 (Bit 5) */ +#define ADC1_RSQ1_RSQ7_Msk (0x3e0UL) /*!< RSQ7 (Bitfield-Mask: 0x1f) */ +#define ADC1_RSQ1_RSQ6_Pos (0UL) /*!< RSQ6 (Bit 0) */ +#define ADC1_RSQ1_RSQ6_Msk (0x1fUL) /*!< RSQ6 (Bitfield-Mask: 0x1f) */ +/* ========================================================= RSQ2 ========================================================== */ +#define ADC1_RSQ2_RSQ5_Pos (25UL) /*!< RSQ5 (Bit 25) */ +#define ADC1_RSQ2_RSQ5_Msk (0x3e000000UL) /*!< RSQ5 (Bitfield-Mask: 0x1f) */ +#define ADC1_RSQ2_RSQ4_Pos (20UL) /*!< RSQ4 (Bit 20) */ +#define ADC1_RSQ2_RSQ4_Msk (0x1f00000UL) /*!< RSQ4 (Bitfield-Mask: 0x1f) */ +#define ADC1_RSQ2_RSQ3_Pos (15UL) /*!< RSQ3 (Bit 15) */ +#define ADC1_RSQ2_RSQ3_Msk (0xf8000UL) /*!< RSQ3 (Bitfield-Mask: 0x1f) */ +#define ADC1_RSQ2_RSQ2_Pos (10UL) /*!< RSQ2 (Bit 10) */ +#define ADC1_RSQ2_RSQ2_Msk (0x7c00UL) /*!< RSQ2 (Bitfield-Mask: 0x1f) */ +#define ADC1_RSQ2_RSQ1_Pos (5UL) /*!< RSQ1 (Bit 5) */ +#define ADC1_RSQ2_RSQ1_Msk (0x3e0UL) /*!< RSQ1 (Bitfield-Mask: 0x1f) */ +#define ADC1_RSQ2_RSQ0_Pos (0UL) /*!< RSQ0 (Bit 0) */ +#define ADC1_RSQ2_RSQ0_Msk (0x1fUL) /*!< RSQ0 (Bitfield-Mask: 0x1f) */ +/* ========================================================== ISQ ========================================================== */ +#define ADC1_ISQ_IL_Pos (20UL) /*!< IL (Bit 20) */ +#define ADC1_ISQ_IL_Msk (0x300000UL) /*!< IL (Bitfield-Mask: 0x03) */ +#define ADC1_ISQ_ISQ3_Pos (15UL) /*!< ISQ3 (Bit 15) */ +#define ADC1_ISQ_ISQ3_Msk (0xf8000UL) /*!< ISQ3 (Bitfield-Mask: 0x1f) */ +#define ADC1_ISQ_ISQ2_Pos (10UL) /*!< ISQ2 (Bit 10) */ +#define ADC1_ISQ_ISQ2_Msk (0x7c00UL) /*!< ISQ2 (Bitfield-Mask: 0x1f) */ +#define ADC1_ISQ_ISQ1_Pos (5UL) /*!< ISQ1 (Bit 5) */ +#define ADC1_ISQ_ISQ1_Msk (0x3e0UL) /*!< ISQ1 (Bitfield-Mask: 0x1f) */ +#define ADC1_ISQ_ISQ0_Pos (0UL) /*!< ISQ0 (Bit 0) */ +#define ADC1_ISQ_ISQ0_Msk (0x1fUL) /*!< ISQ0 (Bitfield-Mask: 0x1f) */ +/* ======================================================== IDATA0 ========================================================= */ +#define ADC1_IDATA0_IDATAn_Pos (0UL) /*!< IDATAn (Bit 0) */ +#define ADC1_IDATA0_IDATAn_Msk (0xffffUL) /*!< IDATAn (Bitfield-Mask: 0xffff) */ +/* ======================================================== IDATA1 ========================================================= */ +#define ADC1_IDATA1_IDATAn_Pos (0UL) /*!< IDATAn (Bit 0) */ +#define ADC1_IDATA1_IDATAn_Msk (0xffffUL) /*!< IDATAn (Bitfield-Mask: 0xffff) */ +/* ======================================================== IDATA2 ========================================================= */ +#define ADC1_IDATA2_IDATAn_Pos (0UL) /*!< IDATAn (Bit 0) */ +#define ADC1_IDATA2_IDATAn_Msk (0xffffUL) /*!< IDATAn (Bitfield-Mask: 0xffff) */ +/* ======================================================== IDATA3 ========================================================= */ +#define ADC1_IDATA3_IDATAn_Pos (0UL) /*!< IDATAn (Bit 0) */ +#define ADC1_IDATA3_IDATAn_Msk (0xffffUL) /*!< IDATAn (Bitfield-Mask: 0xffff) */ +/* ========================================================= RDATA ========================================================= */ +#define ADC1_RDATA_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */ +#define ADC1_RDATA_RDATA_Msk (0xffffUL) /*!< RDATA (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ AFIO ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EC =========================================================== */ +#define AFIO_EC_EOE_Pos (7UL) /*!< EOE (Bit 7) */ +#define AFIO_EC_EOE_Msk (0x80UL) /*!< EOE (Bitfield-Mask: 0x01) */ +#define AFIO_EC_PORT_Pos (4UL) /*!< PORT (Bit 4) */ +#define AFIO_EC_PORT_Msk (0x70UL) /*!< PORT (Bitfield-Mask: 0x07) */ +#define AFIO_EC_PIN_Pos (0UL) /*!< PIN (Bit 0) */ +#define AFIO_EC_PIN_Msk (0xfUL) /*!< PIN (Bitfield-Mask: 0x0f) */ +/* ========================================================= PCF0 ========================================================== */ +#define AFIO_PCF0_TIMER1ITI1_REMAP_Pos (29UL) /*!< TIMER1ITI1_REMAP (Bit 29) */ +#define AFIO_PCF0_TIMER1ITI1_REMAP_Msk (0x20000000UL) /*!< TIMER1ITI1_REMAP (Bitfield-Mask: 0x01) */ +#define AFIO_PCF0_SPI2_REMAP_Pos (28UL) /*!< SPI2_REMAP (Bit 28) */ +#define AFIO_PCF0_SPI2_REMAP_Msk (0x10000000UL) /*!< SPI2_REMAP (Bitfield-Mask: 0x01) */ +#define AFIO_PCF0_SWJ_CFG_Pos (24UL) /*!< SWJ_CFG (Bit 24) */ +#define AFIO_PCF0_SWJ_CFG_Msk (0x7000000UL) /*!< SWJ_CFG (Bitfield-Mask: 0x07) */ +#define AFIO_PCF0_CAN1_REMAP_Pos (22UL) /*!< CAN1_REMAP (Bit 22) */ +#define AFIO_PCF0_CAN1_REMAP_Msk (0x400000UL) /*!< CAN1_REMAP (Bitfield-Mask: 0x01) */ +#define AFIO_PCF0_TIMER4CH3_IREMAP_Pos (16UL) /*!< TIMER4CH3_IREMAP (Bit 16) */ +#define AFIO_PCF0_TIMER4CH3_IREMAP_Msk (0x10000UL) /*!< TIMER4CH3_IREMAP (Bitfield-Mask: 0x01) */ +#define AFIO_PCF0_PD01_REMAP_Pos (15UL) /*!< PD01_REMAP (Bit 15) */ +#define AFIO_PCF0_PD01_REMAP_Msk (0x8000UL) /*!< PD01_REMAP (Bitfield-Mask: 0x01) */ +#define AFIO_PCF0_CAN0_REMAP_Pos (13UL) /*!< CAN0_REMAP (Bit 13) */ +#define AFIO_PCF0_CAN0_REMAP_Msk (0x6000UL) /*!< CAN0_REMAP (Bitfield-Mask: 0x03) */ +#define AFIO_PCF0_TIMER3_REMAP_Pos (12UL) /*!< TIMER3_REMAP (Bit 12) */ +#define AFIO_PCF0_TIMER3_REMAP_Msk (0x1000UL) /*!< TIMER3_REMAP (Bitfield-Mask: 0x01) */ +#define AFIO_PCF0_TIMER2_REMAP_Pos (10UL) /*!< TIMER2_REMAP (Bit 10) */ +#define AFIO_PCF0_TIMER2_REMAP_Msk (0xc00UL) /*!< TIMER2_REMAP (Bitfield-Mask: 0x03) */ +#define AFIO_PCF0_TIMER1_REMAP_Pos (8UL) /*!< TIMER1_REMAP (Bit 8) */ +#define AFIO_PCF0_TIMER1_REMAP_Msk (0x300UL) /*!< TIMER1_REMAP (Bitfield-Mask: 0x03) */ +#define AFIO_PCF0_TIMER0_REMAP_Pos (6UL) /*!< TIMER0_REMAP (Bit 6) */ +#define AFIO_PCF0_TIMER0_REMAP_Msk (0xc0UL) /*!< TIMER0_REMAP (Bitfield-Mask: 0x03) */ +#define AFIO_PCF0_USART2_REMAP_Pos (4UL) /*!< USART2_REMAP (Bit 4) */ +#define AFIO_PCF0_USART2_REMAP_Msk (0x30UL) /*!< USART2_REMAP (Bitfield-Mask: 0x03) */ +#define AFIO_PCF0_USART1_REMAP_Pos (3UL) /*!< USART1_REMAP (Bit 3) */ +#define AFIO_PCF0_USART1_REMAP_Msk (0x8UL) /*!< USART1_REMAP (Bitfield-Mask: 0x01) */ +#define AFIO_PCF0_USART0_REMAP_Pos (2UL) /*!< USART0_REMAP (Bit 2) */ +#define AFIO_PCF0_USART0_REMAP_Msk (0x4UL) /*!< USART0_REMAP (Bitfield-Mask: 0x01) */ +#define AFIO_PCF0_I2C0_REMAP_Pos (1UL) /*!< I2C0_REMAP (Bit 1) */ +#define AFIO_PCF0_I2C0_REMAP_Msk (0x2UL) /*!< I2C0_REMAP (Bitfield-Mask: 0x01) */ +#define AFIO_PCF0_SPI0_REMAP_Pos (0UL) /*!< SPI0_REMAP (Bit 0) */ +#define AFIO_PCF0_SPI0_REMAP_Msk (0x1UL) /*!< SPI0_REMAP (Bitfield-Mask: 0x01) */ +/* ======================================================== EXTISS0 ======================================================== */ +#define AFIO_EXTISS0_EXTI3_SS_Pos (12UL) /*!< EXTI3_SS (Bit 12) */ +#define AFIO_EXTISS0_EXTI3_SS_Msk (0xf000UL) /*!< EXTI3_SS (Bitfield-Mask: 0x0f) */ +#define AFIO_EXTISS0_EXTI2_SS_Pos (8UL) /*!< EXTI2_SS (Bit 8) */ +#define AFIO_EXTISS0_EXTI2_SS_Msk (0xf00UL) /*!< EXTI2_SS (Bitfield-Mask: 0x0f) */ +#define AFIO_EXTISS0_EXTI1_SS_Pos (4UL) /*!< EXTI1_SS (Bit 4) */ +#define AFIO_EXTISS0_EXTI1_SS_Msk (0xf0UL) /*!< EXTI1_SS (Bitfield-Mask: 0x0f) */ +#define AFIO_EXTISS0_EXTI0_SS_Pos (0UL) /*!< EXTI0_SS (Bit 0) */ +#define AFIO_EXTISS0_EXTI0_SS_Msk (0xfUL) /*!< EXTI0_SS (Bitfield-Mask: 0x0f) */ +/* ======================================================== EXTISS1 ======================================================== */ +#define AFIO_EXTISS1_EXTI7_SS_Pos (12UL) /*!< EXTI7_SS (Bit 12) */ +#define AFIO_EXTISS1_EXTI7_SS_Msk (0xf000UL) /*!< EXTI7_SS (Bitfield-Mask: 0x0f) */ +#define AFIO_EXTISS1_EXTI6_SS_Pos (8UL) /*!< EXTI6_SS (Bit 8) */ +#define AFIO_EXTISS1_EXTI6_SS_Msk (0xf00UL) /*!< EXTI6_SS (Bitfield-Mask: 0x0f) */ +#define AFIO_EXTISS1_EXTI5_SS_Pos (4UL) /*!< EXTI5_SS (Bit 4) */ +#define AFIO_EXTISS1_EXTI5_SS_Msk (0xf0UL) /*!< EXTI5_SS (Bitfield-Mask: 0x0f) */ +#define AFIO_EXTISS1_EXTI4_SS_Pos (0UL) /*!< EXTI4_SS (Bit 0) */ +#define AFIO_EXTISS1_EXTI4_SS_Msk (0xfUL) /*!< EXTI4_SS (Bitfield-Mask: 0x0f) */ +/* ======================================================== EXTISS2 ======================================================== */ +#define AFIO_EXTISS2_EXTI11_SS_Pos (12UL) /*!< EXTI11_SS (Bit 12) */ +#define AFIO_EXTISS2_EXTI11_SS_Msk (0xf000UL) /*!< EXTI11_SS (Bitfield-Mask: 0x0f) */ +#define AFIO_EXTISS2_EXTI10_SS_Pos (8UL) /*!< EXTI10_SS (Bit 8) */ +#define AFIO_EXTISS2_EXTI10_SS_Msk (0xf00UL) /*!< EXTI10_SS (Bitfield-Mask: 0x0f) */ +#define AFIO_EXTISS2_EXTI9_SS_Pos (4UL) /*!< EXTI9_SS (Bit 4) */ +#define AFIO_EXTISS2_EXTI9_SS_Msk (0xf0UL) /*!< EXTI9_SS (Bitfield-Mask: 0x0f) */ +#define AFIO_EXTISS2_EXTI8_SS_Pos (0UL) /*!< EXTI8_SS (Bit 0) */ +#define AFIO_EXTISS2_EXTI8_SS_Msk (0xfUL) /*!< EXTI8_SS (Bitfield-Mask: 0x0f) */ +/* ======================================================== EXTISS3 ======================================================== */ +#define AFIO_EXTISS3_EXTI15_SS_Pos (12UL) /*!< EXTI15_SS (Bit 12) */ +#define AFIO_EXTISS3_EXTI15_SS_Msk (0xf000UL) /*!< EXTI15_SS (Bitfield-Mask: 0x0f) */ +#define AFIO_EXTISS3_EXTI14_SS_Pos (8UL) /*!< EXTI14_SS (Bit 8) */ +#define AFIO_EXTISS3_EXTI14_SS_Msk (0xf00UL) /*!< EXTI14_SS (Bitfield-Mask: 0x0f) */ +#define AFIO_EXTISS3_EXTI13_SS_Pos (4UL) /*!< EXTI13_SS (Bit 4) */ +#define AFIO_EXTISS3_EXTI13_SS_Msk (0xf0UL) /*!< EXTI13_SS (Bitfield-Mask: 0x0f) */ +#define AFIO_EXTISS3_EXTI12_SS_Pos (0UL) /*!< EXTI12_SS (Bit 0) */ +#define AFIO_EXTISS3_EXTI12_SS_Msk (0xfUL) /*!< EXTI12_SS (Bitfield-Mask: 0x0f) */ +/* ========================================================= PCF1 ========================================================== */ +#define AFIO_PCF1_EXMC_NADV_Pos (10UL) /*!< EXMC_NADV (Bit 10) */ +#define AFIO_PCF1_EXMC_NADV_Msk (0x400UL) /*!< EXMC_NADV (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ BKP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DATA0 ========================================================= */ +#define BKP_DATA0_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA0_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= DATA1 ========================================================= */ +#define BKP_DATA1_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA1_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= DATA2 ========================================================= */ +#define BKP_DATA2_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA2_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= DATA3 ========================================================= */ +#define BKP_DATA3_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA3_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= DATA4 ========================================================= */ +#define BKP_DATA4_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA4_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= DATA5 ========================================================= */ +#define BKP_DATA5_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA5_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= DATA6 ========================================================= */ +#define BKP_DATA6_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA6_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= DATA7 ========================================================= */ +#define BKP_DATA7_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA7_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= DATA8 ========================================================= */ +#define BKP_DATA8_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA8_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= DATA9 ========================================================= */ +#define BKP_DATA9_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA9_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA10 ========================================================= */ +#define BKP_DATA10_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA10_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA11 ========================================================= */ +#define BKP_DATA11_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA11_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA12 ========================================================= */ +#define BKP_DATA12_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA12_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA13 ========================================================= */ +#define BKP_DATA13_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA13_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA14 ========================================================= */ +#define BKP_DATA14_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA14_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA15 ========================================================= */ +#define BKP_DATA15_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA15_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA16 ========================================================= */ +#define BKP_DATA16_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA16_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA17 ========================================================= */ +#define BKP_DATA17_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA17_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA18 ========================================================= */ +#define BKP_DATA18_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA18_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA19 ========================================================= */ +#define BKP_DATA19_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA19_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA20 ========================================================= */ +#define BKP_DATA20_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA20_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA21 ========================================================= */ +#define BKP_DATA21_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA21_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA22 ========================================================= */ +#define BKP_DATA22_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA22_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA23 ========================================================= */ +#define BKP_DATA23_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA23_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA24 ========================================================= */ +#define BKP_DATA24_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA24_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA25 ========================================================= */ +#define BKP_DATA25_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA25_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA26 ========================================================= */ +#define BKP_DATA26_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA26_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA27 ========================================================= */ +#define BKP_DATA27_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA27_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA28 ========================================================= */ +#define BKP_DATA28_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA28_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA29 ========================================================= */ +#define BKP_DATA29_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA29_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA30 ========================================================= */ +#define BKP_DATA30_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA30_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA31 ========================================================= */ +#define BKP_DATA31_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA31_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA32 ========================================================= */ +#define BKP_DATA32_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA32_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA33 ========================================================= */ +#define BKP_DATA33_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA33_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA34 ========================================================= */ +#define BKP_DATA34_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA34_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA35 ========================================================= */ +#define BKP_DATA35_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA35_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA36 ========================================================= */ +#define BKP_DATA36_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA36_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA37 ========================================================= */ +#define BKP_DATA37_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA37_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA38 ========================================================= */ +#define BKP_DATA38_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA38_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA39 ========================================================= */ +#define BKP_DATA39_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA39_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA40 ========================================================= */ +#define BKP_DATA40_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA40_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DATA41 ========================================================= */ +#define BKP_DATA41_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define BKP_DATA41_DATA_Msk (0xffffUL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ========================================================= OCTL ========================================================== */ +#define BKP_OCTL_ROSEL_Pos (9UL) /*!< ROSEL (Bit 9) */ +#define BKP_OCTL_ROSEL_Msk (0x200UL) /*!< ROSEL (Bitfield-Mask: 0x01) */ +#define BKP_OCTL_ASOEN_Pos (8UL) /*!< ASOEN (Bit 8) */ +#define BKP_OCTL_ASOEN_Msk (0x100UL) /*!< ASOEN (Bitfield-Mask: 0x01) */ +#define BKP_OCTL_COEN_Pos (7UL) /*!< COEN (Bit 7) */ +#define BKP_OCTL_COEN_Msk (0x80UL) /*!< COEN (Bitfield-Mask: 0x01) */ +#define BKP_OCTL_RCCV_Pos (0UL) /*!< RCCV (Bit 0) */ +#define BKP_OCTL_RCCV_Msk (0x7fUL) /*!< RCCV (Bitfield-Mask: 0x7f) */ +/* ========================================================= TPCTL ========================================================= */ +#define BKP_TPCTL_TPAL_Pos (1UL) /*!< TPAL (Bit 1) */ +#define BKP_TPCTL_TPAL_Msk (0x2UL) /*!< TPAL (Bitfield-Mask: 0x01) */ +#define BKP_TPCTL_TPEN_Pos (0UL) /*!< TPEN (Bit 0) */ +#define BKP_TPCTL_TPEN_Msk (0x1UL) /*!< TPEN (Bitfield-Mask: 0x01) */ +/* ========================================================= TPCS ========================================================== */ +#define BKP_TPCS_TIF_Pos (9UL) /*!< TIF (Bit 9) */ +#define BKP_TPCS_TIF_Msk (0x200UL) /*!< TIF (Bitfield-Mask: 0x01) */ +#define BKP_TPCS_TEF_Pos (8UL) /*!< TEF (Bit 8) */ +#define BKP_TPCS_TEF_Msk (0x100UL) /*!< TEF (Bitfield-Mask: 0x01) */ +#define BKP_TPCS_TPIE_Pos (2UL) /*!< TPIE (Bit 2) */ +#define BKP_TPCS_TPIE_Msk (0x4UL) /*!< TPIE (Bitfield-Mask: 0x01) */ +#define BKP_TPCS_TIR_Pos (1UL) /*!< TIR (Bit 1) */ +#define BKP_TPCS_TIR_Msk (0x2UL) /*!< TIR (Bitfield-Mask: 0x01) */ +#define BKP_TPCS_TER_Pos (0UL) /*!< TER (Bit 0) */ +#define BKP_TPCS_TER_Msk (0x1UL) /*!< TER (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ CAN0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CTL ========================================================== */ +#define CAN0_CTL_DFZ_Pos (16UL) /*!< DFZ (Bit 16) */ +#define CAN0_CTL_DFZ_Msk (0x10000UL) /*!< DFZ (Bitfield-Mask: 0x01) */ +#define CAN0_CTL_SWRST_Pos (15UL) /*!< SWRST (Bit 15) */ +#define CAN0_CTL_SWRST_Msk (0x8000UL) /*!< SWRST (Bitfield-Mask: 0x01) */ +#define CAN0_CTL_TTC_Pos (7UL) /*!< TTC (Bit 7) */ +#define CAN0_CTL_TTC_Msk (0x80UL) /*!< TTC (Bitfield-Mask: 0x01) */ +#define CAN0_CTL_ABOR_Pos (6UL) /*!< ABOR (Bit 6) */ +#define CAN0_CTL_ABOR_Msk (0x40UL) /*!< ABOR (Bitfield-Mask: 0x01) */ +#define CAN0_CTL_AWU_Pos (5UL) /*!< AWU (Bit 5) */ +#define CAN0_CTL_AWU_Msk (0x20UL) /*!< AWU (Bitfield-Mask: 0x01) */ +#define CAN0_CTL_ARD_Pos (4UL) /*!< ARD (Bit 4) */ +#define CAN0_CTL_ARD_Msk (0x10UL) /*!< ARD (Bitfield-Mask: 0x01) */ +#define CAN0_CTL_RFOD_Pos (3UL) /*!< RFOD (Bit 3) */ +#define CAN0_CTL_RFOD_Msk (0x8UL) /*!< RFOD (Bitfield-Mask: 0x01) */ +#define CAN0_CTL_TFO_Pos (2UL) /*!< TFO (Bit 2) */ +#define CAN0_CTL_TFO_Msk (0x4UL) /*!< TFO (Bitfield-Mask: 0x01) */ +#define CAN0_CTL_SLPWMOD_Pos (1UL) /*!< SLPWMOD (Bit 1) */ +#define CAN0_CTL_SLPWMOD_Msk (0x2UL) /*!< SLPWMOD (Bitfield-Mask: 0x01) */ +#define CAN0_CTL_IWMOD_Pos (0UL) /*!< IWMOD (Bit 0) */ +#define CAN0_CTL_IWMOD_Msk (0x1UL) /*!< IWMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= STAT ========================================================== */ +#define CAN0_STAT_RXL_Pos (11UL) /*!< RXL (Bit 11) */ +#define CAN0_STAT_RXL_Msk (0x800UL) /*!< RXL (Bitfield-Mask: 0x01) */ +#define CAN0_STAT_LASTRX_Pos (10UL) /*!< LASTRX (Bit 10) */ +#define CAN0_STAT_LASTRX_Msk (0x400UL) /*!< LASTRX (Bitfield-Mask: 0x01) */ +#define CAN0_STAT_RS_Pos (9UL) /*!< RS (Bit 9) */ +#define CAN0_STAT_RS_Msk (0x200UL) /*!< RS (Bitfield-Mask: 0x01) */ +#define CAN0_STAT_TS_Pos (8UL) /*!< TS (Bit 8) */ +#define CAN0_STAT_TS_Msk (0x100UL) /*!< TS (Bitfield-Mask: 0x01) */ +#define CAN0_STAT_SLPIF_Pos (4UL) /*!< SLPIF (Bit 4) */ +#define CAN0_STAT_SLPIF_Msk (0x10UL) /*!< SLPIF (Bitfield-Mask: 0x01) */ +#define CAN0_STAT_WUIF_Pos (3UL) /*!< WUIF (Bit 3) */ +#define CAN0_STAT_WUIF_Msk (0x8UL) /*!< WUIF (Bitfield-Mask: 0x01) */ +#define CAN0_STAT_ERRIF_Pos (2UL) /*!< ERRIF (Bit 2) */ +#define CAN0_STAT_ERRIF_Msk (0x4UL) /*!< ERRIF (Bitfield-Mask: 0x01) */ +#define CAN0_STAT_SLPWS_Pos (1UL) /*!< SLPWS (Bit 1) */ +#define CAN0_STAT_SLPWS_Msk (0x2UL) /*!< SLPWS (Bitfield-Mask: 0x01) */ +#define CAN0_STAT_IWS_Pos (0UL) /*!< IWS (Bit 0) */ +#define CAN0_STAT_IWS_Msk (0x1UL) /*!< IWS (Bitfield-Mask: 0x01) */ +/* ========================================================= TSTAT ========================================================= */ +#define CAN0_TSTAT_TMLS2_Pos (31UL) /*!< TMLS2 (Bit 31) */ +#define CAN0_TSTAT_TMLS2_Msk (0x80000000UL) /*!< TMLS2 (Bitfield-Mask: 0x01) */ +#define CAN0_TSTAT_TMLS1_Pos (30UL) /*!< TMLS1 (Bit 30) */ +#define CAN0_TSTAT_TMLS1_Msk (0x40000000UL) /*!< TMLS1 (Bitfield-Mask: 0x01) */ +#define CAN0_TSTAT_TMLS0_Pos (29UL) /*!< TMLS0 (Bit 29) */ +#define CAN0_TSTAT_TMLS0_Msk (0x20000000UL) /*!< TMLS0 (Bitfield-Mask: 0x01) */ +#define CAN0_TSTAT_TME2_Pos (28UL) /*!< TME2 (Bit 28) */ +#define CAN0_TSTAT_TME2_Msk (0x10000000UL) /*!< TME2 (Bitfield-Mask: 0x01) */ +#define CAN0_TSTAT_TME1_Pos (27UL) /*!< TME1 (Bit 27) */ +#define CAN0_TSTAT_TME1_Msk (0x8000000UL) /*!< TME1 (Bitfield-Mask: 0x01) */ +#define CAN0_TSTAT_TME0_Pos (26UL) /*!< TME0 (Bit 26) */ +#define CAN0_TSTAT_TME0_Msk (0x4000000UL) /*!< TME0 (Bitfield-Mask: 0x01) */ +#define CAN0_TSTAT_NUM_Pos (24UL) /*!< NUM (Bit 24) */ +#define CAN0_TSTAT_NUM_Msk (0x3000000UL) /*!< NUM (Bitfield-Mask: 0x03) */ +#define CAN0_TSTAT_MST2_Pos (23UL) /*!< MST2 (Bit 23) */ +#define CAN0_TSTAT_MST2_Msk (0x800000UL) /*!< MST2 (Bitfield-Mask: 0x01) */ +#define CAN0_TSTAT_MTE2_Pos (19UL) /*!< MTE2 (Bit 19) */ +#define CAN0_TSTAT_MTE2_Msk (0x80000UL) /*!< MTE2 (Bitfield-Mask: 0x01) */ +#define CAN0_TSTAT_MAL2_Pos (18UL) /*!< MAL2 (Bit 18) */ +#define CAN0_TSTAT_MAL2_Msk (0x40000UL) /*!< MAL2 (Bitfield-Mask: 0x01) */ +#define CAN0_TSTAT_MTFNERR2_Pos (17UL) /*!< MTFNERR2 (Bit 17) */ +#define CAN0_TSTAT_MTFNERR2_Msk (0x20000UL) /*!< MTFNERR2 (Bitfield-Mask: 0x01) */ +#define CAN0_TSTAT_MTF2_Pos (16UL) /*!< MTF2 (Bit 16) */ +#define CAN0_TSTAT_MTF2_Msk (0x10000UL) /*!< MTF2 (Bitfield-Mask: 0x01) */ +#define CAN0_TSTAT_MST1_Pos (15UL) /*!< MST1 (Bit 15) */ +#define CAN0_TSTAT_MST1_Msk (0x8000UL) /*!< MST1 (Bitfield-Mask: 0x01) */ +#define CAN0_TSTAT_MTE1_Pos (11UL) /*!< MTE1 (Bit 11) */ +#define CAN0_TSTAT_MTE1_Msk (0x800UL) /*!< MTE1 (Bitfield-Mask: 0x01) */ +#define CAN0_TSTAT_MAL1_Pos (10UL) /*!< MAL1 (Bit 10) */ +#define CAN0_TSTAT_MAL1_Msk (0x400UL) /*!< MAL1 (Bitfield-Mask: 0x01) */ +#define CAN0_TSTAT_MTFNERR1_Pos (9UL) /*!< MTFNERR1 (Bit 9) */ +#define CAN0_TSTAT_MTFNERR1_Msk (0x200UL) /*!< MTFNERR1 (Bitfield-Mask: 0x01) */ +#define CAN0_TSTAT_MTF1_Pos (8UL) /*!< MTF1 (Bit 8) */ +#define CAN0_TSTAT_MTF1_Msk (0x100UL) /*!< MTF1 (Bitfield-Mask: 0x01) */ +#define CAN0_TSTAT_MST0_Pos (7UL) /*!< MST0 (Bit 7) */ +#define CAN0_TSTAT_MST0_Msk (0x80UL) /*!< MST0 (Bitfield-Mask: 0x01) */ +#define CAN0_TSTAT_MTE0_Pos (3UL) /*!< MTE0 (Bit 3) */ +#define CAN0_TSTAT_MTE0_Msk (0x8UL) /*!< MTE0 (Bitfield-Mask: 0x01) */ +#define CAN0_TSTAT_MAL0_Pos (2UL) /*!< MAL0 (Bit 2) */ +#define CAN0_TSTAT_MAL0_Msk (0x4UL) /*!< MAL0 (Bitfield-Mask: 0x01) */ +#define CAN0_TSTAT_MTFNERR0_Pos (1UL) /*!< MTFNERR0 (Bit 1) */ +#define CAN0_TSTAT_MTFNERR0_Msk (0x2UL) /*!< MTFNERR0 (Bitfield-Mask: 0x01) */ +#define CAN0_TSTAT_MTF0_Pos (0UL) /*!< MTF0 (Bit 0) */ +#define CAN0_TSTAT_MTF0_Msk (0x1UL) /*!< MTF0 (Bitfield-Mask: 0x01) */ +/* ======================================================== RFIFO0 ========================================================= */ +#define CAN0_RFIFO0_RFD0_Pos (5UL) /*!< RFD0 (Bit 5) */ +#define CAN0_RFIFO0_RFD0_Msk (0x20UL) /*!< RFD0 (Bitfield-Mask: 0x01) */ +#define CAN0_RFIFO0_RFO0_Pos (4UL) /*!< RFO0 (Bit 4) */ +#define CAN0_RFIFO0_RFO0_Msk (0x10UL) /*!< RFO0 (Bitfield-Mask: 0x01) */ +#define CAN0_RFIFO0_RFF0_Pos (3UL) /*!< RFF0 (Bit 3) */ +#define CAN0_RFIFO0_RFF0_Msk (0x8UL) /*!< RFF0 (Bitfield-Mask: 0x01) */ +#define CAN0_RFIFO0_RFL0_Pos (0UL) /*!< RFL0 (Bit 0) */ +#define CAN0_RFIFO0_RFL0_Msk (0x3UL) /*!< RFL0 (Bitfield-Mask: 0x03) */ +/* ======================================================== RFIFO1 ========================================================= */ +#define CAN0_RFIFO1_RFD1_Pos (5UL) /*!< RFD1 (Bit 5) */ +#define CAN0_RFIFO1_RFD1_Msk (0x20UL) /*!< RFD1 (Bitfield-Mask: 0x01) */ +#define CAN0_RFIFO1_RFO1_Pos (4UL) /*!< RFO1 (Bit 4) */ +#define CAN0_RFIFO1_RFO1_Msk (0x10UL) /*!< RFO1 (Bitfield-Mask: 0x01) */ +#define CAN0_RFIFO1_RFF1_Pos (3UL) /*!< RFF1 (Bit 3) */ +#define CAN0_RFIFO1_RFF1_Msk (0x8UL) /*!< RFF1 (Bitfield-Mask: 0x01) */ +#define CAN0_RFIFO1_RFL1_Pos (0UL) /*!< RFL1 (Bit 0) */ +#define CAN0_RFIFO1_RFL1_Msk (0x3UL) /*!< RFL1 (Bitfield-Mask: 0x03) */ +/* ========================================================= INTEN ========================================================= */ +#define CAN0_INTEN_SLPWIE_Pos (17UL) /*!< SLPWIE (Bit 17) */ +#define CAN0_INTEN_SLPWIE_Msk (0x20000UL) /*!< SLPWIE (Bitfield-Mask: 0x01) */ +#define CAN0_INTEN_WIE_Pos (16UL) /*!< WIE (Bit 16) */ +#define CAN0_INTEN_WIE_Msk (0x10000UL) /*!< WIE (Bitfield-Mask: 0x01) */ +#define CAN0_INTEN_ERRIE_Pos (15UL) /*!< ERRIE (Bit 15) */ +#define CAN0_INTEN_ERRIE_Msk (0x8000UL) /*!< ERRIE (Bitfield-Mask: 0x01) */ +#define CAN0_INTEN_ERRNIE_Pos (11UL) /*!< ERRNIE (Bit 11) */ +#define CAN0_INTEN_ERRNIE_Msk (0x800UL) /*!< ERRNIE (Bitfield-Mask: 0x01) */ +#define CAN0_INTEN_BOIE_Pos (10UL) /*!< BOIE (Bit 10) */ +#define CAN0_INTEN_BOIE_Msk (0x400UL) /*!< BOIE (Bitfield-Mask: 0x01) */ +#define CAN0_INTEN_PERRIE_Pos (9UL) /*!< PERRIE (Bit 9) */ +#define CAN0_INTEN_PERRIE_Msk (0x200UL) /*!< PERRIE (Bitfield-Mask: 0x01) */ +#define CAN0_INTEN_WERRIE_Pos (8UL) /*!< WERRIE (Bit 8) */ +#define CAN0_INTEN_WERRIE_Msk (0x100UL) /*!< WERRIE (Bitfield-Mask: 0x01) */ +#define CAN0_INTEN_RFOIE1_Pos (6UL) /*!< RFOIE1 (Bit 6) */ +#define CAN0_INTEN_RFOIE1_Msk (0x40UL) /*!< RFOIE1 (Bitfield-Mask: 0x01) */ +#define CAN0_INTEN_RFFIE1_Pos (5UL) /*!< RFFIE1 (Bit 5) */ +#define CAN0_INTEN_RFFIE1_Msk (0x20UL) /*!< RFFIE1 (Bitfield-Mask: 0x01) */ +#define CAN0_INTEN_RFNEIE1_Pos (4UL) /*!< RFNEIE1 (Bit 4) */ +#define CAN0_INTEN_RFNEIE1_Msk (0x10UL) /*!< RFNEIE1 (Bitfield-Mask: 0x01) */ +#define CAN0_INTEN_RFOIE0_Pos (3UL) /*!< RFOIE0 (Bit 3) */ +#define CAN0_INTEN_RFOIE0_Msk (0x8UL) /*!< RFOIE0 (Bitfield-Mask: 0x01) */ +#define CAN0_INTEN_RFFIE0_Pos (2UL) /*!< RFFIE0 (Bit 2) */ +#define CAN0_INTEN_RFFIE0_Msk (0x4UL) /*!< RFFIE0 (Bitfield-Mask: 0x01) */ +#define CAN0_INTEN_RFNEIE0_Pos (1UL) /*!< RFNEIE0 (Bit 1) */ +#define CAN0_INTEN_RFNEIE0_Msk (0x2UL) /*!< RFNEIE0 (Bitfield-Mask: 0x01) */ +#define CAN0_INTEN_TMEIE_Pos (0UL) /*!< TMEIE (Bit 0) */ +#define CAN0_INTEN_TMEIE_Msk (0x1UL) /*!< TMEIE (Bitfield-Mask: 0x01) */ +/* ========================================================== ERR ========================================================== */ +#define CAN0_ERR_RECNT_Pos (24UL) /*!< RECNT (Bit 24) */ +#define CAN0_ERR_RECNT_Msk (0xff000000UL) /*!< RECNT (Bitfield-Mask: 0xff) */ +#define CAN0_ERR_TECNT_Pos (16UL) /*!< TECNT (Bit 16) */ +#define CAN0_ERR_TECNT_Msk (0xff0000UL) /*!< TECNT (Bitfield-Mask: 0xff) */ +#define CAN0_ERR_ERRN_Pos (4UL) /*!< ERRN (Bit 4) */ +#define CAN0_ERR_ERRN_Msk (0x70UL) /*!< ERRN (Bitfield-Mask: 0x07) */ +#define CAN0_ERR_BOERR_Pos (2UL) /*!< BOERR (Bit 2) */ +#define CAN0_ERR_BOERR_Msk (0x4UL) /*!< BOERR (Bitfield-Mask: 0x01) */ +#define CAN0_ERR_PERR_Pos (1UL) /*!< PERR (Bit 1) */ +#define CAN0_ERR_PERR_Msk (0x2UL) /*!< PERR (Bitfield-Mask: 0x01) */ +#define CAN0_ERR_WERR_Pos (0UL) /*!< WERR (Bit 0) */ +#define CAN0_ERR_WERR_Msk (0x1UL) /*!< WERR (Bitfield-Mask: 0x01) */ +/* ========================================================== BT =========================================================== */ +#define CAN0_BT_SCMOD_Pos (31UL) /*!< SCMOD (Bit 31) */ +#define CAN0_BT_SCMOD_Msk (0x80000000UL) /*!< SCMOD (Bitfield-Mask: 0x01) */ +#define CAN0_BT_LCMOD_Pos (30UL) /*!< LCMOD (Bit 30) */ +#define CAN0_BT_LCMOD_Msk (0x40000000UL) /*!< LCMOD (Bitfield-Mask: 0x01) */ +#define CAN0_BT_SJW_Pos (24UL) /*!< SJW (Bit 24) */ +#define CAN0_BT_SJW_Msk (0x3000000UL) /*!< SJW (Bitfield-Mask: 0x03) */ +#define CAN0_BT_BS2_Pos (20UL) /*!< BS2 (Bit 20) */ +#define CAN0_BT_BS2_Msk (0x700000UL) /*!< BS2 (Bitfield-Mask: 0x07) */ +#define CAN0_BT_BS1_Pos (16UL) /*!< BS1 (Bit 16) */ +#define CAN0_BT_BS1_Msk (0xf0000UL) /*!< BS1 (Bitfield-Mask: 0x0f) */ +#define CAN0_BT_BAUDPSC_Pos (0UL) /*!< BAUDPSC (Bit 0) */ +#define CAN0_BT_BAUDPSC_Msk (0x3ffUL) /*!< BAUDPSC (Bitfield-Mask: 0x3ff) */ +/* ========================================================= TMI0 ========================================================== */ +#define CAN0_TMI0_SFID_EFID_Pos (21UL) /*!< SFID_EFID (Bit 21) */ +#define CAN0_TMI0_SFID_EFID_Msk (0xffe00000UL) /*!< SFID_EFID (Bitfield-Mask: 0x7ff) */ +#define CAN0_TMI0_EFID_Pos (3UL) /*!< EFID (Bit 3) */ +#define CAN0_TMI0_EFID_Msk (0x1ffff8UL) /*!< EFID (Bitfield-Mask: 0x3ffff) */ +#define CAN0_TMI0_FF_Pos (2UL) /*!< FF (Bit 2) */ +#define CAN0_TMI0_FF_Msk (0x4UL) /*!< FF (Bitfield-Mask: 0x01) */ +#define CAN0_TMI0_FT_Pos (1UL) /*!< FT (Bit 1) */ +#define CAN0_TMI0_FT_Msk (0x2UL) /*!< FT (Bitfield-Mask: 0x01) */ +#define CAN0_TMI0_TEN_Pos (0UL) /*!< TEN (Bit 0) */ +#define CAN0_TMI0_TEN_Msk (0x1UL) /*!< TEN (Bitfield-Mask: 0x01) */ +/* ========================================================= TMP0 ========================================================== */ +#define CAN0_TMP0_TS_Pos (16UL) /*!< TS (Bit 16) */ +#define CAN0_TMP0_TS_Msk (0xffff0000UL) /*!< TS (Bitfield-Mask: 0xffff) */ +#define CAN0_TMP0_TSEN_Pos (8UL) /*!< TSEN (Bit 8) */ +#define CAN0_TMP0_TSEN_Msk (0x100UL) /*!< TSEN (Bitfield-Mask: 0x01) */ +#define CAN0_TMP0_DLENC_Pos (0UL) /*!< DLENC (Bit 0) */ +#define CAN0_TMP0_DLENC_Msk (0xfUL) /*!< DLENC (Bitfield-Mask: 0x0f) */ +/* ======================================================= TMDATA00 ======================================================== */ +#define CAN0_TMDATA00_DB3_Pos (24UL) /*!< DB3 (Bit 24) */ +#define CAN0_TMDATA00_DB3_Msk (0xff000000UL) /*!< DB3 (Bitfield-Mask: 0xff) */ +#define CAN0_TMDATA00_DB2_Pos (16UL) /*!< DB2 (Bit 16) */ +#define CAN0_TMDATA00_DB2_Msk (0xff0000UL) /*!< DB2 (Bitfield-Mask: 0xff) */ +#define CAN0_TMDATA00_DB1_Pos (8UL) /*!< DB1 (Bit 8) */ +#define CAN0_TMDATA00_DB1_Msk (0xff00UL) /*!< DB1 (Bitfield-Mask: 0xff) */ +#define CAN0_TMDATA00_DB0_Pos (0UL) /*!< DB0 (Bit 0) */ +#define CAN0_TMDATA00_DB0_Msk (0xffUL) /*!< DB0 (Bitfield-Mask: 0xff) */ +/* ======================================================= TMDATA10 ======================================================== */ +#define CAN0_TMDATA10_DB7_Pos (24UL) /*!< DB7 (Bit 24) */ +#define CAN0_TMDATA10_DB7_Msk (0xff000000UL) /*!< DB7 (Bitfield-Mask: 0xff) */ +#define CAN0_TMDATA10_DB6_Pos (16UL) /*!< DB6 (Bit 16) */ +#define CAN0_TMDATA10_DB6_Msk (0xff0000UL) /*!< DB6 (Bitfield-Mask: 0xff) */ +#define CAN0_TMDATA10_DB5_Pos (8UL) /*!< DB5 (Bit 8) */ +#define CAN0_TMDATA10_DB5_Msk (0xff00UL) /*!< DB5 (Bitfield-Mask: 0xff) */ +#define CAN0_TMDATA10_DB4_Pos (0UL) /*!< DB4 (Bit 0) */ +#define CAN0_TMDATA10_DB4_Msk (0xffUL) /*!< DB4 (Bitfield-Mask: 0xff) */ +/* ========================================================= TMI1 ========================================================== */ +#define CAN0_TMI1_SFID_EFID_Pos (21UL) /*!< SFID_EFID (Bit 21) */ +#define CAN0_TMI1_SFID_EFID_Msk (0xffe00000UL) /*!< SFID_EFID (Bitfield-Mask: 0x7ff) */ +#define CAN0_TMI1_EFID_Pos (3UL) /*!< EFID (Bit 3) */ +#define CAN0_TMI1_EFID_Msk (0x1ffff8UL) /*!< EFID (Bitfield-Mask: 0x3ffff) */ +#define CAN0_TMI1_FF_Pos (2UL) /*!< FF (Bit 2) */ +#define CAN0_TMI1_FF_Msk (0x4UL) /*!< FF (Bitfield-Mask: 0x01) */ +#define CAN0_TMI1_FT_Pos (1UL) /*!< FT (Bit 1) */ +#define CAN0_TMI1_FT_Msk (0x2UL) /*!< FT (Bitfield-Mask: 0x01) */ +#define CAN0_TMI1_TEN_Pos (0UL) /*!< TEN (Bit 0) */ +#define CAN0_TMI1_TEN_Msk (0x1UL) /*!< TEN (Bitfield-Mask: 0x01) */ +/* ========================================================= TMP1 ========================================================== */ +#define CAN0_TMP1_TS_Pos (16UL) /*!< TS (Bit 16) */ +#define CAN0_TMP1_TS_Msk (0xffff0000UL) /*!< TS (Bitfield-Mask: 0xffff) */ +#define CAN0_TMP1_TSEN_Pos (8UL) /*!< TSEN (Bit 8) */ +#define CAN0_TMP1_TSEN_Msk (0x100UL) /*!< TSEN (Bitfield-Mask: 0x01) */ +#define CAN0_TMP1_DLENC_Pos (0UL) /*!< DLENC (Bit 0) */ +#define CAN0_TMP1_DLENC_Msk (0xfUL) /*!< DLENC (Bitfield-Mask: 0x0f) */ +/* ======================================================= TMDATA01 ======================================================== */ +#define CAN0_TMDATA01_DB3_Pos (24UL) /*!< DB3 (Bit 24) */ +#define CAN0_TMDATA01_DB3_Msk (0xff000000UL) /*!< DB3 (Bitfield-Mask: 0xff) */ +#define CAN0_TMDATA01_DB2_Pos (16UL) /*!< DB2 (Bit 16) */ +#define CAN0_TMDATA01_DB2_Msk (0xff0000UL) /*!< DB2 (Bitfield-Mask: 0xff) */ +#define CAN0_TMDATA01_DB1_Pos (8UL) /*!< DB1 (Bit 8) */ +#define CAN0_TMDATA01_DB1_Msk (0xff00UL) /*!< DB1 (Bitfield-Mask: 0xff) */ +#define CAN0_TMDATA01_DB0_Pos (0UL) /*!< DB0 (Bit 0) */ +#define CAN0_TMDATA01_DB0_Msk (0xffUL) /*!< DB0 (Bitfield-Mask: 0xff) */ +/* ======================================================= TMDATA11 ======================================================== */ +#define CAN0_TMDATA11_DB7_Pos (24UL) /*!< DB7 (Bit 24) */ +#define CAN0_TMDATA11_DB7_Msk (0xff000000UL) /*!< DB7 (Bitfield-Mask: 0xff) */ +#define CAN0_TMDATA11_DB6_Pos (16UL) /*!< DB6 (Bit 16) */ +#define CAN0_TMDATA11_DB6_Msk (0xff0000UL) /*!< DB6 (Bitfield-Mask: 0xff) */ +#define CAN0_TMDATA11_DB5_Pos (8UL) /*!< DB5 (Bit 8) */ +#define CAN0_TMDATA11_DB5_Msk (0xff00UL) /*!< DB5 (Bitfield-Mask: 0xff) */ +#define CAN0_TMDATA11_DB4_Pos (0UL) /*!< DB4 (Bit 0) */ +#define CAN0_TMDATA11_DB4_Msk (0xffUL) /*!< DB4 (Bitfield-Mask: 0xff) */ +/* ========================================================= TMI2 ========================================================== */ +#define CAN0_TMI2_SFID_EFID_Pos (21UL) /*!< SFID_EFID (Bit 21) */ +#define CAN0_TMI2_SFID_EFID_Msk (0xffe00000UL) /*!< SFID_EFID (Bitfield-Mask: 0x7ff) */ +#define CAN0_TMI2_EFID_Pos (3UL) /*!< EFID (Bit 3) */ +#define CAN0_TMI2_EFID_Msk (0x1ffff8UL) /*!< EFID (Bitfield-Mask: 0x3ffff) */ +#define CAN0_TMI2_FF_Pos (2UL) /*!< FF (Bit 2) */ +#define CAN0_TMI2_FF_Msk (0x4UL) /*!< FF (Bitfield-Mask: 0x01) */ +#define CAN0_TMI2_FT_Pos (1UL) /*!< FT (Bit 1) */ +#define CAN0_TMI2_FT_Msk (0x2UL) /*!< FT (Bitfield-Mask: 0x01) */ +#define CAN0_TMI2_TEN_Pos (0UL) /*!< TEN (Bit 0) */ +#define CAN0_TMI2_TEN_Msk (0x1UL) /*!< TEN (Bitfield-Mask: 0x01) */ +/* ========================================================= TMP2 ========================================================== */ +#define CAN0_TMP2_TS_Pos (16UL) /*!< TS (Bit 16) */ +#define CAN0_TMP2_TS_Msk (0xffff0000UL) /*!< TS (Bitfield-Mask: 0xffff) */ +#define CAN0_TMP2_TSEN_Pos (8UL) /*!< TSEN (Bit 8) */ +#define CAN0_TMP2_TSEN_Msk (0x100UL) /*!< TSEN (Bitfield-Mask: 0x01) */ +#define CAN0_TMP2_DLENC_Pos (0UL) /*!< DLENC (Bit 0) */ +#define CAN0_TMP2_DLENC_Msk (0xfUL) /*!< DLENC (Bitfield-Mask: 0x0f) */ +/* ======================================================= TMDATA02 ======================================================== */ +#define CAN0_TMDATA02_DB3_Pos (24UL) /*!< DB3 (Bit 24) */ +#define CAN0_TMDATA02_DB3_Msk (0xff000000UL) /*!< DB3 (Bitfield-Mask: 0xff) */ +#define CAN0_TMDATA02_DB2_Pos (16UL) /*!< DB2 (Bit 16) */ +#define CAN0_TMDATA02_DB2_Msk (0xff0000UL) /*!< DB2 (Bitfield-Mask: 0xff) */ +#define CAN0_TMDATA02_DB1_Pos (8UL) /*!< DB1 (Bit 8) */ +#define CAN0_TMDATA02_DB1_Msk (0xff00UL) /*!< DB1 (Bitfield-Mask: 0xff) */ +#define CAN0_TMDATA02_DB0_Pos (0UL) /*!< DB0 (Bit 0) */ +#define CAN0_TMDATA02_DB0_Msk (0xffUL) /*!< DB0 (Bitfield-Mask: 0xff) */ +/* ======================================================= TMDATA12 ======================================================== */ +#define CAN0_TMDATA12_DB7_Pos (24UL) /*!< DB7 (Bit 24) */ +#define CAN0_TMDATA12_DB7_Msk (0xff000000UL) /*!< DB7 (Bitfield-Mask: 0xff) */ +#define CAN0_TMDATA12_DB6_Pos (16UL) /*!< DB6 (Bit 16) */ +#define CAN0_TMDATA12_DB6_Msk (0xff0000UL) /*!< DB6 (Bitfield-Mask: 0xff) */ +#define CAN0_TMDATA12_DB5_Pos (8UL) /*!< DB5 (Bit 8) */ +#define CAN0_TMDATA12_DB5_Msk (0xff00UL) /*!< DB5 (Bitfield-Mask: 0xff) */ +#define CAN0_TMDATA12_DB4_Pos (0UL) /*!< DB4 (Bit 0) */ +#define CAN0_TMDATA12_DB4_Msk (0xffUL) /*!< DB4 (Bitfield-Mask: 0xff) */ +/* ======================================================= RFIFOMI0 ======================================================== */ +#define CAN0_RFIFOMI0_SFID_EFID_Pos (21UL) /*!< SFID_EFID (Bit 21) */ +#define CAN0_RFIFOMI0_SFID_EFID_Msk (0xffe00000UL) /*!< SFID_EFID (Bitfield-Mask: 0x7ff) */ +#define CAN0_RFIFOMI0_EFID_Pos (3UL) /*!< EFID (Bit 3) */ +#define CAN0_RFIFOMI0_EFID_Msk (0x1ffff8UL) /*!< EFID (Bitfield-Mask: 0x3ffff) */ +#define CAN0_RFIFOMI0_FF_Pos (2UL) /*!< FF (Bit 2) */ +#define CAN0_RFIFOMI0_FF_Msk (0x4UL) /*!< FF (Bitfield-Mask: 0x01) */ +#define CAN0_RFIFOMI0_FT_Pos (1UL) /*!< FT (Bit 1) */ +#define CAN0_RFIFOMI0_FT_Msk (0x2UL) /*!< FT (Bitfield-Mask: 0x01) */ +/* ======================================================= RFIFOMP0 ======================================================== */ +#define CAN0_RFIFOMP0_TS_Pos (16UL) /*!< TS (Bit 16) */ +#define CAN0_RFIFOMP0_TS_Msk (0xffff0000UL) /*!< TS (Bitfield-Mask: 0xffff) */ +#define CAN0_RFIFOMP0_FI_Pos (8UL) /*!< FI (Bit 8) */ +#define CAN0_RFIFOMP0_FI_Msk (0xff00UL) /*!< FI (Bitfield-Mask: 0xff) */ +#define CAN0_RFIFOMP0_DLENC_Pos (0UL) /*!< DLENC (Bit 0) */ +#define CAN0_RFIFOMP0_DLENC_Msk (0xfUL) /*!< DLENC (Bitfield-Mask: 0x0f) */ +/* ===================================================== RFIFOMDATA00 ====================================================== */ +#define CAN0_RFIFOMDATA00_DB3_Pos (24UL) /*!< DB3 (Bit 24) */ +#define CAN0_RFIFOMDATA00_DB3_Msk (0xff000000UL) /*!< DB3 (Bitfield-Mask: 0xff) */ +#define CAN0_RFIFOMDATA00_DB2_Pos (16UL) /*!< DB2 (Bit 16) */ +#define CAN0_RFIFOMDATA00_DB2_Msk (0xff0000UL) /*!< DB2 (Bitfield-Mask: 0xff) */ +#define CAN0_RFIFOMDATA00_DB1_Pos (8UL) /*!< DB1 (Bit 8) */ +#define CAN0_RFIFOMDATA00_DB1_Msk (0xff00UL) /*!< DB1 (Bitfield-Mask: 0xff) */ +#define CAN0_RFIFOMDATA00_DB0_Pos (0UL) /*!< DB0 (Bit 0) */ +#define CAN0_RFIFOMDATA00_DB0_Msk (0xffUL) /*!< DB0 (Bitfield-Mask: 0xff) */ +/* ===================================================== RFIFOMDATA10 ====================================================== */ +#define CAN0_RFIFOMDATA10_DB7_Pos (24UL) /*!< DB7 (Bit 24) */ +#define CAN0_RFIFOMDATA10_DB7_Msk (0xff000000UL) /*!< DB7 (Bitfield-Mask: 0xff) */ +#define CAN0_RFIFOMDATA10_DB6_Pos (16UL) /*!< DB6 (Bit 16) */ +#define CAN0_RFIFOMDATA10_DB6_Msk (0xff0000UL) /*!< DB6 (Bitfield-Mask: 0xff) */ +#define CAN0_RFIFOMDATA10_DB5_Pos (8UL) /*!< DB5 (Bit 8) */ +#define CAN0_RFIFOMDATA10_DB5_Msk (0xff00UL) /*!< DB5 (Bitfield-Mask: 0xff) */ +#define CAN0_RFIFOMDATA10_DB4_Pos (0UL) /*!< DB4 (Bit 0) */ +#define CAN0_RFIFOMDATA10_DB4_Msk (0xffUL) /*!< DB4 (Bitfield-Mask: 0xff) */ +/* ======================================================= RFIFOMI1 ======================================================== */ +#define CAN0_RFIFOMI1_SFID_EFID_Pos (21UL) /*!< SFID_EFID (Bit 21) */ +#define CAN0_RFIFOMI1_SFID_EFID_Msk (0xffe00000UL) /*!< SFID_EFID (Bitfield-Mask: 0x7ff) */ +#define CAN0_RFIFOMI1_EFID_Pos (3UL) /*!< EFID (Bit 3) */ +#define CAN0_RFIFOMI1_EFID_Msk (0x1ffff8UL) /*!< EFID (Bitfield-Mask: 0x3ffff) */ +#define CAN0_RFIFOMI1_FF_Pos (2UL) /*!< FF (Bit 2) */ +#define CAN0_RFIFOMI1_FF_Msk (0x4UL) /*!< FF (Bitfield-Mask: 0x01) */ +#define CAN0_RFIFOMI1_FT_Pos (1UL) /*!< FT (Bit 1) */ +#define CAN0_RFIFOMI1_FT_Msk (0x2UL) /*!< FT (Bitfield-Mask: 0x01) */ +/* ======================================================= RFIFOMP1 ======================================================== */ +#define CAN0_RFIFOMP1_TS_Pos (16UL) /*!< TS (Bit 16) */ +#define CAN0_RFIFOMP1_TS_Msk (0xffff0000UL) /*!< TS (Bitfield-Mask: 0xffff) */ +#define CAN0_RFIFOMP1_FI_Pos (8UL) /*!< FI (Bit 8) */ +#define CAN0_RFIFOMP1_FI_Msk (0xff00UL) /*!< FI (Bitfield-Mask: 0xff) */ +#define CAN0_RFIFOMP1_DLENC_Pos (0UL) /*!< DLENC (Bit 0) */ +#define CAN0_RFIFOMP1_DLENC_Msk (0xfUL) /*!< DLENC (Bitfield-Mask: 0x0f) */ +/* ===================================================== RFIFOMDATA01 ====================================================== */ +#define CAN0_RFIFOMDATA01_DB3_Pos (24UL) /*!< DB3 (Bit 24) */ +#define CAN0_RFIFOMDATA01_DB3_Msk (0xff000000UL) /*!< DB3 (Bitfield-Mask: 0xff) */ +#define CAN0_RFIFOMDATA01_DB2_Pos (16UL) /*!< DB2 (Bit 16) */ +#define CAN0_RFIFOMDATA01_DB2_Msk (0xff0000UL) /*!< DB2 (Bitfield-Mask: 0xff) */ +#define CAN0_RFIFOMDATA01_DB1_Pos (8UL) /*!< DB1 (Bit 8) */ +#define CAN0_RFIFOMDATA01_DB1_Msk (0xff00UL) /*!< DB1 (Bitfield-Mask: 0xff) */ +#define CAN0_RFIFOMDATA01_DB0_Pos (0UL) /*!< DB0 (Bit 0) */ +#define CAN0_RFIFOMDATA01_DB0_Msk (0xffUL) /*!< DB0 (Bitfield-Mask: 0xff) */ +/* ===================================================== RFIFOMDATA11 ====================================================== */ +#define CAN0_RFIFOMDATA11_DB7_Pos (24UL) /*!< DB7 (Bit 24) */ +#define CAN0_RFIFOMDATA11_DB7_Msk (0xff000000UL) /*!< DB7 (Bitfield-Mask: 0xff) */ +#define CAN0_RFIFOMDATA11_DB6_Pos (16UL) /*!< DB6 (Bit 16) */ +#define CAN0_RFIFOMDATA11_DB6_Msk (0xff0000UL) /*!< DB6 (Bitfield-Mask: 0xff) */ +#define CAN0_RFIFOMDATA11_DB5_Pos (8UL) /*!< DB5 (Bit 8) */ +#define CAN0_RFIFOMDATA11_DB5_Msk (0xff00UL) /*!< DB5 (Bitfield-Mask: 0xff) */ +#define CAN0_RFIFOMDATA11_DB4_Pos (0UL) /*!< DB4 (Bit 0) */ +#define CAN0_RFIFOMDATA11_DB4_Msk (0xffUL) /*!< DB4 (Bitfield-Mask: 0xff) */ +/* ========================================================= FCTL ========================================================== */ +#define CAN0_FCTL_HBC1F_Pos (8UL) /*!< HBC1F (Bit 8) */ +#define CAN0_FCTL_HBC1F_Msk (0x3f00UL) /*!< HBC1F (Bitfield-Mask: 0x3f) */ +#define CAN0_FCTL_FLD_Pos (0UL) /*!< FLD (Bit 0) */ +#define CAN0_FCTL_FLD_Msk (0x1UL) /*!< FLD (Bitfield-Mask: 0x01) */ +/* ========================================================= FMCFG ========================================================= */ +#define CAN0_FMCFG_FMOD27_Pos (27UL) /*!< FMOD27 (Bit 27) */ +#define CAN0_FMCFG_FMOD27_Msk (0x8000000UL) /*!< FMOD27 (Bitfield-Mask: 0x01) */ +#define CAN0_FMCFG_FMOD26_Pos (26UL) /*!< FMOD26 (Bit 26) */ +#define CAN0_FMCFG_FMOD26_Msk (0x4000000UL) /*!< FMOD26 (Bitfield-Mask: 0x01) */ +#define CAN0_FMCFG_FMOD25_Pos (25UL) /*!< FMOD25 (Bit 25) */ +#define CAN0_FMCFG_FMOD25_Msk (0x2000000UL) /*!< FMOD25 (Bitfield-Mask: 0x01) */ +#define CAN0_FMCFG_FMOD24_Pos (24UL) /*!< FMOD24 (Bit 24) */ +#define CAN0_FMCFG_FMOD24_Msk (0x1000000UL) /*!< FMOD24 (Bitfield-Mask: 0x01) */ +#define CAN0_FMCFG_FMOD23_Pos (23UL) /*!< FMOD23 (Bit 23) */ +#define CAN0_FMCFG_FMOD23_Msk (0x800000UL) /*!< FMOD23 (Bitfield-Mask: 0x01) */ +#define CAN0_FMCFG_FMOD22_Pos (22UL) /*!< FMOD22 (Bit 22) */ +#define CAN0_FMCFG_FMOD22_Msk (0x400000UL) /*!< FMOD22 (Bitfield-Mask: 0x01) */ +#define CAN0_FMCFG_FMOD21_Pos (21UL) /*!< FMOD21 (Bit 21) */ +#define CAN0_FMCFG_FMOD21_Msk (0x200000UL) /*!< FMOD21 (Bitfield-Mask: 0x01) */ +#define CAN0_FMCFG_FMOD20_Pos (20UL) /*!< FMOD20 (Bit 20) */ +#define CAN0_FMCFG_FMOD20_Msk (0x100000UL) /*!< FMOD20 (Bitfield-Mask: 0x01) */ +#define CAN0_FMCFG_FMOD19_Pos (19UL) /*!< FMOD19 (Bit 19) */ +#define CAN0_FMCFG_FMOD19_Msk (0x80000UL) /*!< FMOD19 (Bitfield-Mask: 0x01) */ +#define CAN0_FMCFG_FMOD18_Pos (18UL) /*!< FMOD18 (Bit 18) */ +#define CAN0_FMCFG_FMOD18_Msk (0x40000UL) /*!< FMOD18 (Bitfield-Mask: 0x01) */ +#define CAN0_FMCFG_FMOD17_Pos (17UL) /*!< FMOD17 (Bit 17) */ +#define CAN0_FMCFG_FMOD17_Msk (0x20000UL) /*!< FMOD17 (Bitfield-Mask: 0x01) */ +#define CAN0_FMCFG_FMOD16_Pos (16UL) /*!< FMOD16 (Bit 16) */ +#define CAN0_FMCFG_FMOD16_Msk (0x10000UL) /*!< FMOD16 (Bitfield-Mask: 0x01) */ +#define CAN0_FMCFG_FMOD15_Pos (15UL) /*!< FMOD15 (Bit 15) */ +#define CAN0_FMCFG_FMOD15_Msk (0x8000UL) /*!< FMOD15 (Bitfield-Mask: 0x01) */ +#define CAN0_FMCFG_FMOD14_Pos (14UL) /*!< FMOD14 (Bit 14) */ +#define CAN0_FMCFG_FMOD14_Msk (0x4000UL) /*!< FMOD14 (Bitfield-Mask: 0x01) */ +#define CAN0_FMCFG_FMOD13_Pos (13UL) /*!< FMOD13 (Bit 13) */ +#define CAN0_FMCFG_FMOD13_Msk (0x2000UL) /*!< FMOD13 (Bitfield-Mask: 0x01) */ +#define CAN0_FMCFG_FMOD12_Pos (12UL) /*!< FMOD12 (Bit 12) */ +#define CAN0_FMCFG_FMOD12_Msk (0x1000UL) /*!< FMOD12 (Bitfield-Mask: 0x01) */ +#define CAN0_FMCFG_FMOD11_Pos (11UL) /*!< FMOD11 (Bit 11) */ +#define CAN0_FMCFG_FMOD11_Msk (0x800UL) /*!< FMOD11 (Bitfield-Mask: 0x01) */ +#define CAN0_FMCFG_FMOD10_Pos (10UL) /*!< FMOD10 (Bit 10) */ +#define CAN0_FMCFG_FMOD10_Msk (0x400UL) /*!< FMOD10 (Bitfield-Mask: 0x01) */ +#define CAN0_FMCFG_FMOD9_Pos (9UL) /*!< FMOD9 (Bit 9) */ +#define CAN0_FMCFG_FMOD9_Msk (0x200UL) /*!< FMOD9 (Bitfield-Mask: 0x01) */ +#define CAN0_FMCFG_FMOD8_Pos (8UL) /*!< FMOD8 (Bit 8) */ +#define CAN0_FMCFG_FMOD8_Msk (0x100UL) /*!< FMOD8 (Bitfield-Mask: 0x01) */ +#define CAN0_FMCFG_FMOD7_Pos (7UL) /*!< FMOD7 (Bit 7) */ +#define CAN0_FMCFG_FMOD7_Msk (0x80UL) /*!< FMOD7 (Bitfield-Mask: 0x01) */ +#define CAN0_FMCFG_FMOD6_Pos (6UL) /*!< FMOD6 (Bit 6) */ +#define CAN0_FMCFG_FMOD6_Msk (0x40UL) /*!< FMOD6 (Bitfield-Mask: 0x01) */ +#define CAN0_FMCFG_FMOD5_Pos (5UL) /*!< FMOD5 (Bit 5) */ +#define CAN0_FMCFG_FMOD5_Msk (0x20UL) /*!< FMOD5 (Bitfield-Mask: 0x01) */ +#define CAN0_FMCFG_FMOD4_Pos (4UL) /*!< FMOD4 (Bit 4) */ +#define CAN0_FMCFG_FMOD4_Msk (0x10UL) /*!< FMOD4 (Bitfield-Mask: 0x01) */ +#define CAN0_FMCFG_FMOD3_Pos (3UL) /*!< FMOD3 (Bit 3) */ +#define CAN0_FMCFG_FMOD3_Msk (0x8UL) /*!< FMOD3 (Bitfield-Mask: 0x01) */ +#define CAN0_FMCFG_FMOD2_Pos (2UL) /*!< FMOD2 (Bit 2) */ +#define CAN0_FMCFG_FMOD2_Msk (0x4UL) /*!< FMOD2 (Bitfield-Mask: 0x01) */ +#define CAN0_FMCFG_FMOD1_Pos (1UL) /*!< FMOD1 (Bit 1) */ +#define CAN0_FMCFG_FMOD1_Msk (0x2UL) /*!< FMOD1 (Bitfield-Mask: 0x01) */ +#define CAN0_FMCFG_FMOD0_Pos (0UL) /*!< FMOD0 (Bit 0) */ +#define CAN0_FMCFG_FMOD0_Msk (0x1UL) /*!< FMOD0 (Bitfield-Mask: 0x01) */ +/* ========================================================= FSCFG ========================================================= */ +#define CAN0_FSCFG_FS0_Pos (0UL) /*!< FS0 (Bit 0) */ +#define CAN0_FSCFG_FS0_Msk (0x1UL) /*!< FS0 (Bitfield-Mask: 0x01) */ +#define CAN0_FSCFG_FS1_Pos (1UL) /*!< FS1 (Bit 1) */ +#define CAN0_FSCFG_FS1_Msk (0x2UL) /*!< FS1 (Bitfield-Mask: 0x01) */ +#define CAN0_FSCFG_FS2_Pos (2UL) /*!< FS2 (Bit 2) */ +#define CAN0_FSCFG_FS2_Msk (0x4UL) /*!< FS2 (Bitfield-Mask: 0x01) */ +#define CAN0_FSCFG_FS3_Pos (3UL) /*!< FS3 (Bit 3) */ +#define CAN0_FSCFG_FS3_Msk (0x8UL) /*!< FS3 (Bitfield-Mask: 0x01) */ +#define CAN0_FSCFG_FS4_Pos (4UL) /*!< FS4 (Bit 4) */ +#define CAN0_FSCFG_FS4_Msk (0x10UL) /*!< FS4 (Bitfield-Mask: 0x01) */ +#define CAN0_FSCFG_FS5_Pos (5UL) /*!< FS5 (Bit 5) */ +#define CAN0_FSCFG_FS5_Msk (0x20UL) /*!< FS5 (Bitfield-Mask: 0x01) */ +#define CAN0_FSCFG_FS6_Pos (6UL) /*!< FS6 (Bit 6) */ +#define CAN0_FSCFG_FS6_Msk (0x40UL) /*!< FS6 (Bitfield-Mask: 0x01) */ +#define CAN0_FSCFG_FS7_Pos (7UL) /*!< FS7 (Bit 7) */ +#define CAN0_FSCFG_FS7_Msk (0x80UL) /*!< FS7 (Bitfield-Mask: 0x01) */ +#define CAN0_FSCFG_FS8_Pos (8UL) /*!< FS8 (Bit 8) */ +#define CAN0_FSCFG_FS8_Msk (0x100UL) /*!< FS8 (Bitfield-Mask: 0x01) */ +#define CAN0_FSCFG_FS9_Pos (9UL) /*!< FS9 (Bit 9) */ +#define CAN0_FSCFG_FS9_Msk (0x200UL) /*!< FS9 (Bitfield-Mask: 0x01) */ +#define CAN0_FSCFG_FS10_Pos (10UL) /*!< FS10 (Bit 10) */ +#define CAN0_FSCFG_FS10_Msk (0x400UL) /*!< FS10 (Bitfield-Mask: 0x01) */ +#define CAN0_FSCFG_FS11_Pos (11UL) /*!< FS11 (Bit 11) */ +#define CAN0_FSCFG_FS11_Msk (0x800UL) /*!< FS11 (Bitfield-Mask: 0x01) */ +#define CAN0_FSCFG_FS12_Pos (12UL) /*!< FS12 (Bit 12) */ +#define CAN0_FSCFG_FS12_Msk (0x1000UL) /*!< FS12 (Bitfield-Mask: 0x01) */ +#define CAN0_FSCFG_FS13_Pos (13UL) /*!< FS13 (Bit 13) */ +#define CAN0_FSCFG_FS13_Msk (0x2000UL) /*!< FS13 (Bitfield-Mask: 0x01) */ +#define CAN0_FSCFG_FS14_Pos (14UL) /*!< FS14 (Bit 14) */ +#define CAN0_FSCFG_FS14_Msk (0x4000UL) /*!< FS14 (Bitfield-Mask: 0x01) */ +#define CAN0_FSCFG_FS15_Pos (15UL) /*!< FS15 (Bit 15) */ +#define CAN0_FSCFG_FS15_Msk (0x8000UL) /*!< FS15 (Bitfield-Mask: 0x01) */ +#define CAN0_FSCFG_FS16_Pos (16UL) /*!< FS16 (Bit 16) */ +#define CAN0_FSCFG_FS16_Msk (0x10000UL) /*!< FS16 (Bitfield-Mask: 0x01) */ +#define CAN0_FSCFG_FS17_Pos (17UL) /*!< FS17 (Bit 17) */ +#define CAN0_FSCFG_FS17_Msk (0x20000UL) /*!< FS17 (Bitfield-Mask: 0x01) */ +#define CAN0_FSCFG_FS18_Pos (18UL) /*!< FS18 (Bit 18) */ +#define CAN0_FSCFG_FS18_Msk (0x40000UL) /*!< FS18 (Bitfield-Mask: 0x01) */ +#define CAN0_FSCFG_FS19_Pos (19UL) /*!< FS19 (Bit 19) */ +#define CAN0_FSCFG_FS19_Msk (0x80000UL) /*!< FS19 (Bitfield-Mask: 0x01) */ +#define CAN0_FSCFG_FS20_Pos (20UL) /*!< FS20 (Bit 20) */ +#define CAN0_FSCFG_FS20_Msk (0x100000UL) /*!< FS20 (Bitfield-Mask: 0x01) */ +#define CAN0_FSCFG_FS21_Pos (21UL) /*!< FS21 (Bit 21) */ +#define CAN0_FSCFG_FS21_Msk (0x200000UL) /*!< FS21 (Bitfield-Mask: 0x01) */ +#define CAN0_FSCFG_FS22_Pos (22UL) /*!< FS22 (Bit 22) */ +#define CAN0_FSCFG_FS22_Msk (0x400000UL) /*!< FS22 (Bitfield-Mask: 0x01) */ +#define CAN0_FSCFG_FS23_Pos (23UL) /*!< FS23 (Bit 23) */ +#define CAN0_FSCFG_FS23_Msk (0x800000UL) /*!< FS23 (Bitfield-Mask: 0x01) */ +#define CAN0_FSCFG_FS24_Pos (24UL) /*!< FS24 (Bit 24) */ +#define CAN0_FSCFG_FS24_Msk (0x1000000UL) /*!< FS24 (Bitfield-Mask: 0x01) */ +#define CAN0_FSCFG_FS25_Pos (25UL) /*!< FS25 (Bit 25) */ +#define CAN0_FSCFG_FS25_Msk (0x2000000UL) /*!< FS25 (Bitfield-Mask: 0x01) */ +#define CAN0_FSCFG_FS26_Pos (26UL) /*!< FS26 (Bit 26) */ +#define CAN0_FSCFG_FS26_Msk (0x4000000UL) /*!< FS26 (Bitfield-Mask: 0x01) */ +#define CAN0_FSCFG_FS27_Pos (27UL) /*!< FS27 (Bit 27) */ +#define CAN0_FSCFG_FS27_Msk (0x8000000UL) /*!< FS27 (Bitfield-Mask: 0x01) */ +/* ======================================================== FAFIFO ========================================================= */ +#define CAN0_FAFIFO_FAF0_Pos (0UL) /*!< FAF0 (Bit 0) */ +#define CAN0_FAFIFO_FAF0_Msk (0x1UL) /*!< FAF0 (Bitfield-Mask: 0x01) */ +#define CAN0_FAFIFO_FAF1_Pos (1UL) /*!< FAF1 (Bit 1) */ +#define CAN0_FAFIFO_FAF1_Msk (0x2UL) /*!< FAF1 (Bitfield-Mask: 0x01) */ +#define CAN0_FAFIFO_FAF2_Pos (2UL) /*!< FAF2 (Bit 2) */ +#define CAN0_FAFIFO_FAF2_Msk (0x4UL) /*!< FAF2 (Bitfield-Mask: 0x01) */ +#define CAN0_FAFIFO_FAF3_Pos (3UL) /*!< FAF3 (Bit 3) */ +#define CAN0_FAFIFO_FAF3_Msk (0x8UL) /*!< FAF3 (Bitfield-Mask: 0x01) */ +#define CAN0_FAFIFO_FAF4_Pos (4UL) /*!< FAF4 (Bit 4) */ +#define CAN0_FAFIFO_FAF4_Msk (0x10UL) /*!< FAF4 (Bitfield-Mask: 0x01) */ +#define CAN0_FAFIFO_FAF5_Pos (5UL) /*!< FAF5 (Bit 5) */ +#define CAN0_FAFIFO_FAF5_Msk (0x20UL) /*!< FAF5 (Bitfield-Mask: 0x01) */ +#define CAN0_FAFIFO_FAF6_Pos (6UL) /*!< FAF6 (Bit 6) */ +#define CAN0_FAFIFO_FAF6_Msk (0x40UL) /*!< FAF6 (Bitfield-Mask: 0x01) */ +#define CAN0_FAFIFO_FAF7_Pos (7UL) /*!< FAF7 (Bit 7) */ +#define CAN0_FAFIFO_FAF7_Msk (0x80UL) /*!< FAF7 (Bitfield-Mask: 0x01) */ +#define CAN0_FAFIFO_FAF8_Pos (8UL) /*!< FAF8 (Bit 8) */ +#define CAN0_FAFIFO_FAF8_Msk (0x100UL) /*!< FAF8 (Bitfield-Mask: 0x01) */ +#define CAN0_FAFIFO_FAF9_Pos (9UL) /*!< FAF9 (Bit 9) */ +#define CAN0_FAFIFO_FAF9_Msk (0x200UL) /*!< FAF9 (Bitfield-Mask: 0x01) */ +#define CAN0_FAFIFO_FAF10_Pos (10UL) /*!< FAF10 (Bit 10) */ +#define CAN0_FAFIFO_FAF10_Msk (0x400UL) /*!< FAF10 (Bitfield-Mask: 0x01) */ +#define CAN0_FAFIFO_FAF11_Pos (11UL) /*!< FAF11 (Bit 11) */ +#define CAN0_FAFIFO_FAF11_Msk (0x800UL) /*!< FAF11 (Bitfield-Mask: 0x01) */ +#define CAN0_FAFIFO_FAF12_Pos (12UL) /*!< FAF12 (Bit 12) */ +#define CAN0_FAFIFO_FAF12_Msk (0x1000UL) /*!< FAF12 (Bitfield-Mask: 0x01) */ +#define CAN0_FAFIFO_FAF13_Pos (13UL) /*!< FAF13 (Bit 13) */ +#define CAN0_FAFIFO_FAF13_Msk (0x2000UL) /*!< FAF13 (Bitfield-Mask: 0x01) */ +#define CAN0_FAFIFO_FAF14_Pos (14UL) /*!< FAF14 (Bit 14) */ +#define CAN0_FAFIFO_FAF14_Msk (0x4000UL) /*!< FAF14 (Bitfield-Mask: 0x01) */ +#define CAN0_FAFIFO_FAF15_Pos (15UL) /*!< FAF15 (Bit 15) */ +#define CAN0_FAFIFO_FAF15_Msk (0x8000UL) /*!< FAF15 (Bitfield-Mask: 0x01) */ +#define CAN0_FAFIFO_FAF16_Pos (16UL) /*!< FAF16 (Bit 16) */ +#define CAN0_FAFIFO_FAF16_Msk (0x10000UL) /*!< FAF16 (Bitfield-Mask: 0x01) */ +#define CAN0_FAFIFO_FAF17_Pos (17UL) /*!< FAF17 (Bit 17) */ +#define CAN0_FAFIFO_FAF17_Msk (0x20000UL) /*!< FAF17 (Bitfield-Mask: 0x01) */ +#define CAN0_FAFIFO_FAF18_Pos (18UL) /*!< FAF18 (Bit 18) */ +#define CAN0_FAFIFO_FAF18_Msk (0x40000UL) /*!< FAF18 (Bitfield-Mask: 0x01) */ +#define CAN0_FAFIFO_FAF19_Pos (19UL) /*!< FAF19 (Bit 19) */ +#define CAN0_FAFIFO_FAF19_Msk (0x80000UL) /*!< FAF19 (Bitfield-Mask: 0x01) */ +#define CAN0_FAFIFO_FAF20_Pos (20UL) /*!< FAF20 (Bit 20) */ +#define CAN0_FAFIFO_FAF20_Msk (0x100000UL) /*!< FAF20 (Bitfield-Mask: 0x01) */ +#define CAN0_FAFIFO_FAF21_Pos (21UL) /*!< FAF21 (Bit 21) */ +#define CAN0_FAFIFO_FAF21_Msk (0x200000UL) /*!< FAF21 (Bitfield-Mask: 0x01) */ +#define CAN0_FAFIFO_FAF22_Pos (22UL) /*!< FAF22 (Bit 22) */ +#define CAN0_FAFIFO_FAF22_Msk (0x400000UL) /*!< FAF22 (Bitfield-Mask: 0x01) */ +#define CAN0_FAFIFO_FAF23_Pos (23UL) /*!< FAF23 (Bit 23) */ +#define CAN0_FAFIFO_FAF23_Msk (0x800000UL) /*!< FAF23 (Bitfield-Mask: 0x01) */ +#define CAN0_FAFIFO_FAF24_Pos (24UL) /*!< FAF24 (Bit 24) */ +#define CAN0_FAFIFO_FAF24_Msk (0x1000000UL) /*!< FAF24 (Bitfield-Mask: 0x01) */ +#define CAN0_FAFIFO_FAF25_Pos (25UL) /*!< FAF25 (Bit 25) */ +#define CAN0_FAFIFO_FAF25_Msk (0x2000000UL) /*!< FAF25 (Bitfield-Mask: 0x01) */ +#define CAN0_FAFIFO_FAF26_Pos (26UL) /*!< FAF26 (Bit 26) */ +#define CAN0_FAFIFO_FAF26_Msk (0x4000000UL) /*!< FAF26 (Bitfield-Mask: 0x01) */ +#define CAN0_FAFIFO_FAF27_Pos (27UL) /*!< FAF27 (Bit 27) */ +#define CAN0_FAFIFO_FAF27_Msk (0x8000000UL) /*!< FAF27 (Bitfield-Mask: 0x01) */ +/* ========================================================== FW =========================================================== */ +#define CAN0_FW_FW0_Pos (0UL) /*!< FW0 (Bit 0) */ +#define CAN0_FW_FW0_Msk (0x1UL) /*!< FW0 (Bitfield-Mask: 0x01) */ +#define CAN0_FW_FW1_Pos (1UL) /*!< FW1 (Bit 1) */ +#define CAN0_FW_FW1_Msk (0x2UL) /*!< FW1 (Bitfield-Mask: 0x01) */ +#define CAN0_FW_FW2_Pos (2UL) /*!< FW2 (Bit 2) */ +#define CAN0_FW_FW2_Msk (0x4UL) /*!< FW2 (Bitfield-Mask: 0x01) */ +#define CAN0_FW_FW3_Pos (3UL) /*!< FW3 (Bit 3) */ +#define CAN0_FW_FW3_Msk (0x8UL) /*!< FW3 (Bitfield-Mask: 0x01) */ +#define CAN0_FW_FW4_Pos (4UL) /*!< FW4 (Bit 4) */ +#define CAN0_FW_FW4_Msk (0x10UL) /*!< FW4 (Bitfield-Mask: 0x01) */ +#define CAN0_FW_FW5_Pos (5UL) /*!< FW5 (Bit 5) */ +#define CAN0_FW_FW5_Msk (0x20UL) /*!< FW5 (Bitfield-Mask: 0x01) */ +#define CAN0_FW_FW6_Pos (6UL) /*!< FW6 (Bit 6) */ +#define CAN0_FW_FW6_Msk (0x40UL) /*!< FW6 (Bitfield-Mask: 0x01) */ +#define CAN0_FW_FW7_Pos (7UL) /*!< FW7 (Bit 7) */ +#define CAN0_FW_FW7_Msk (0x80UL) /*!< FW7 (Bitfield-Mask: 0x01) */ +#define CAN0_FW_FW8_Pos (8UL) /*!< FW8 (Bit 8) */ +#define CAN0_FW_FW8_Msk (0x100UL) /*!< FW8 (Bitfield-Mask: 0x01) */ +#define CAN0_FW_FW9_Pos (9UL) /*!< FW9 (Bit 9) */ +#define CAN0_FW_FW9_Msk (0x200UL) /*!< FW9 (Bitfield-Mask: 0x01) */ +#define CAN0_FW_FW10_Pos (10UL) /*!< FW10 (Bit 10) */ +#define CAN0_FW_FW10_Msk (0x400UL) /*!< FW10 (Bitfield-Mask: 0x01) */ +#define CAN0_FW_FW11_Pos (11UL) /*!< FW11 (Bit 11) */ +#define CAN0_FW_FW11_Msk (0x800UL) /*!< FW11 (Bitfield-Mask: 0x01) */ +#define CAN0_FW_FW12_Pos (12UL) /*!< FW12 (Bit 12) */ +#define CAN0_FW_FW12_Msk (0x1000UL) /*!< FW12 (Bitfield-Mask: 0x01) */ +#define CAN0_FW_FW13_Pos (13UL) /*!< FW13 (Bit 13) */ +#define CAN0_FW_FW13_Msk (0x2000UL) /*!< FW13 (Bitfield-Mask: 0x01) */ +#define CAN0_FW_FW14_Pos (14UL) /*!< FW14 (Bit 14) */ +#define CAN0_FW_FW14_Msk (0x4000UL) /*!< FW14 (Bitfield-Mask: 0x01) */ +#define CAN0_FW_FW15_Pos (15UL) /*!< FW15 (Bit 15) */ +#define CAN0_FW_FW15_Msk (0x8000UL) /*!< FW15 (Bitfield-Mask: 0x01) */ +#define CAN0_FW_FW16_Pos (16UL) /*!< FW16 (Bit 16) */ +#define CAN0_FW_FW16_Msk (0x10000UL) /*!< FW16 (Bitfield-Mask: 0x01) */ +#define CAN0_FW_FW17_Pos (17UL) /*!< FW17 (Bit 17) */ +#define CAN0_FW_FW17_Msk (0x20000UL) /*!< FW17 (Bitfield-Mask: 0x01) */ +#define CAN0_FW_FW18_Pos (18UL) /*!< FW18 (Bit 18) */ +#define CAN0_FW_FW18_Msk (0x40000UL) /*!< FW18 (Bitfield-Mask: 0x01) */ +#define CAN0_FW_FW19_Pos (19UL) /*!< FW19 (Bit 19) */ +#define CAN0_FW_FW19_Msk (0x80000UL) /*!< FW19 (Bitfield-Mask: 0x01) */ +#define CAN0_FW_FW20_Pos (20UL) /*!< FW20 (Bit 20) */ +#define CAN0_FW_FW20_Msk (0x100000UL) /*!< FW20 (Bitfield-Mask: 0x01) */ +#define CAN0_FW_FW21_Pos (21UL) /*!< FW21 (Bit 21) */ +#define CAN0_FW_FW21_Msk (0x200000UL) /*!< FW21 (Bitfield-Mask: 0x01) */ +#define CAN0_FW_FW22_Pos (22UL) /*!< FW22 (Bit 22) */ +#define CAN0_FW_FW22_Msk (0x400000UL) /*!< FW22 (Bitfield-Mask: 0x01) */ +#define CAN0_FW_FW23_Pos (23UL) /*!< FW23 (Bit 23) */ +#define CAN0_FW_FW23_Msk (0x800000UL) /*!< FW23 (Bitfield-Mask: 0x01) */ +#define CAN0_FW_FW24_Pos (24UL) /*!< FW24 (Bit 24) */ +#define CAN0_FW_FW24_Msk (0x1000000UL) /*!< FW24 (Bitfield-Mask: 0x01) */ +#define CAN0_FW_FW25_Pos (25UL) /*!< FW25 (Bit 25) */ +#define CAN0_FW_FW25_Msk (0x2000000UL) /*!< FW25 (Bitfield-Mask: 0x01) */ +#define CAN0_FW_FW26_Pos (26UL) /*!< FW26 (Bit 26) */ +#define CAN0_FW_FW26_Msk (0x4000000UL) /*!< FW26 (Bitfield-Mask: 0x01) */ +#define CAN0_FW_FW27_Pos (27UL) /*!< FW27 (Bit 27) */ +#define CAN0_FW_FW27_Msk (0x8000000UL) /*!< FW27 (Bitfield-Mask: 0x01) */ +/* ======================================================== F0DATA0 ======================================================== */ +#define CAN0_F0DATA0_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F0DATA0_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F0DATA0_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F0DATA0_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F0DATA0_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F0DATA0_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F0DATA0_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F0DATA0_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F0DATA0_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F0DATA0_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F0DATA0_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F0DATA0_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F0DATA0_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F0DATA0_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F0DATA0_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F0DATA0_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F0DATA0_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F0DATA0_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F0DATA0_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F0DATA0_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F0DATA0_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F0DATA0_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F0DATA0_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F0DATA0_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F0DATA0_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F0DATA0_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F0DATA0_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F0DATA0_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F0DATA0_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F0DATA0_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F0DATA0_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F0DATA0_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA0_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F0DATA0_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================== F0DATA1 ======================================================== */ +#define CAN0_F0DATA1_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F0DATA1_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F0DATA1_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F0DATA1_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F0DATA1_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F0DATA1_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F0DATA1_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F0DATA1_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F0DATA1_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F0DATA1_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F0DATA1_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F0DATA1_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F0DATA1_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F0DATA1_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F0DATA1_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F0DATA1_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F0DATA1_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F0DATA1_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F0DATA1_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F0DATA1_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F0DATA1_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F0DATA1_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F0DATA1_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F0DATA1_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F0DATA1_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F0DATA1_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F0DATA1_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F0DATA1_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F0DATA1_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F0DATA1_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F0DATA1_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F0DATA1_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F0DATA1_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F0DATA1_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================== F1DATA0 ======================================================== */ +#define CAN0_F1DATA0_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F1DATA0_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F1DATA0_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F1DATA0_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F1DATA0_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F1DATA0_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F1DATA0_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F1DATA0_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F1DATA0_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F1DATA0_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F1DATA0_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F1DATA0_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F1DATA0_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F1DATA0_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F1DATA0_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F1DATA0_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F1DATA0_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F1DATA0_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F1DATA0_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F1DATA0_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F1DATA0_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F1DATA0_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F1DATA0_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F1DATA0_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F1DATA0_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F1DATA0_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F1DATA0_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F1DATA0_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F1DATA0_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F1DATA0_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F1DATA0_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F1DATA0_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA0_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F1DATA0_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================== F1DATA1 ======================================================== */ +#define CAN0_F1DATA1_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F1DATA1_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F1DATA1_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F1DATA1_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F1DATA1_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F1DATA1_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F1DATA1_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F1DATA1_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F1DATA1_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F1DATA1_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F1DATA1_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F1DATA1_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F1DATA1_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F1DATA1_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F1DATA1_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F1DATA1_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F1DATA1_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F1DATA1_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F1DATA1_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F1DATA1_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F1DATA1_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F1DATA1_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F1DATA1_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F1DATA1_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F1DATA1_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F1DATA1_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F1DATA1_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F1DATA1_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F1DATA1_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F1DATA1_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F1DATA1_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F1DATA1_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F1DATA1_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F1DATA1_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================== F2DATA0 ======================================================== */ +#define CAN0_F2DATA0_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F2DATA0_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F2DATA0_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F2DATA0_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F2DATA0_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F2DATA0_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F2DATA0_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F2DATA0_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F2DATA0_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F2DATA0_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F2DATA0_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F2DATA0_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F2DATA0_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F2DATA0_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F2DATA0_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F2DATA0_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F2DATA0_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F2DATA0_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F2DATA0_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F2DATA0_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F2DATA0_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F2DATA0_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F2DATA0_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F2DATA0_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F2DATA0_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F2DATA0_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F2DATA0_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F2DATA0_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F2DATA0_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F2DATA0_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F2DATA0_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F2DATA0_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA0_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F2DATA0_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================== F2DATA1 ======================================================== */ +#define CAN0_F2DATA1_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F2DATA1_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F2DATA1_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F2DATA1_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F2DATA1_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F2DATA1_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F2DATA1_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F2DATA1_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F2DATA1_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F2DATA1_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F2DATA1_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F2DATA1_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F2DATA1_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F2DATA1_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F2DATA1_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F2DATA1_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F2DATA1_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F2DATA1_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F2DATA1_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F2DATA1_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F2DATA1_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F2DATA1_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F2DATA1_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F2DATA1_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F2DATA1_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F2DATA1_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F2DATA1_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F2DATA1_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F2DATA1_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F2DATA1_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F2DATA1_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F2DATA1_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F2DATA1_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F2DATA1_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================== F3DATA0 ======================================================== */ +#define CAN0_F3DATA0_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F3DATA0_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F3DATA0_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F3DATA0_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F3DATA0_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F3DATA0_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F3DATA0_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F3DATA0_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F3DATA0_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F3DATA0_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F3DATA0_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F3DATA0_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F3DATA0_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F3DATA0_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F3DATA0_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F3DATA0_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F3DATA0_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F3DATA0_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F3DATA0_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F3DATA0_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F3DATA0_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F3DATA0_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F3DATA0_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F3DATA0_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F3DATA0_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F3DATA0_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F3DATA0_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F3DATA0_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F3DATA0_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F3DATA0_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F3DATA0_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F3DATA0_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA0_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F3DATA0_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================== F3DATA1 ======================================================== */ +#define CAN0_F3DATA1_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F3DATA1_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F3DATA1_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F3DATA1_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F3DATA1_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F3DATA1_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F3DATA1_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F3DATA1_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F3DATA1_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F3DATA1_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F3DATA1_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F3DATA1_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F3DATA1_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F3DATA1_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F3DATA1_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F3DATA1_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F3DATA1_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F3DATA1_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F3DATA1_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F3DATA1_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F3DATA1_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F3DATA1_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F3DATA1_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F3DATA1_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F3DATA1_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F3DATA1_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F3DATA1_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F3DATA1_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F3DATA1_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F3DATA1_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F3DATA1_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F3DATA1_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F3DATA1_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F3DATA1_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================== F4DATA0 ======================================================== */ +#define CAN0_F4DATA0_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F4DATA0_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F4DATA0_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F4DATA0_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F4DATA0_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F4DATA0_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F4DATA0_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F4DATA0_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F4DATA0_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F4DATA0_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F4DATA0_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F4DATA0_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F4DATA0_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F4DATA0_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F4DATA0_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F4DATA0_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F4DATA0_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F4DATA0_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F4DATA0_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F4DATA0_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F4DATA0_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F4DATA0_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F4DATA0_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F4DATA0_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F4DATA0_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F4DATA0_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F4DATA0_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F4DATA0_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F4DATA0_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F4DATA0_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F4DATA0_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F4DATA0_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA0_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F4DATA0_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================== F4DATA1 ======================================================== */ +#define CAN0_F4DATA1_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F4DATA1_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F4DATA1_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F4DATA1_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F4DATA1_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F4DATA1_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F4DATA1_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F4DATA1_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F4DATA1_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F4DATA1_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F4DATA1_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F4DATA1_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F4DATA1_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F4DATA1_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F4DATA1_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F4DATA1_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F4DATA1_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F4DATA1_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F4DATA1_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F4DATA1_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F4DATA1_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F4DATA1_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F4DATA1_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F4DATA1_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F4DATA1_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F4DATA1_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F4DATA1_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F4DATA1_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F4DATA1_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F4DATA1_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F4DATA1_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F4DATA1_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F4DATA1_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F4DATA1_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================== F5DATA0 ======================================================== */ +#define CAN0_F5DATA0_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F5DATA0_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F5DATA0_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F5DATA0_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F5DATA0_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F5DATA0_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F5DATA0_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F5DATA0_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F5DATA0_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F5DATA0_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F5DATA0_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F5DATA0_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F5DATA0_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F5DATA0_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F5DATA0_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F5DATA0_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F5DATA0_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F5DATA0_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F5DATA0_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F5DATA0_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F5DATA0_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F5DATA0_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F5DATA0_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F5DATA0_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F5DATA0_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F5DATA0_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F5DATA0_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F5DATA0_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F5DATA0_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F5DATA0_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F5DATA0_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F5DATA0_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA0_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F5DATA0_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================== F5DATA1 ======================================================== */ +#define CAN0_F5DATA1_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F5DATA1_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F5DATA1_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F5DATA1_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F5DATA1_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F5DATA1_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F5DATA1_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F5DATA1_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F5DATA1_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F5DATA1_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F5DATA1_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F5DATA1_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F5DATA1_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F5DATA1_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F5DATA1_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F5DATA1_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F5DATA1_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F5DATA1_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F5DATA1_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F5DATA1_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F5DATA1_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F5DATA1_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F5DATA1_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F5DATA1_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F5DATA1_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F5DATA1_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F5DATA1_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F5DATA1_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F5DATA1_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F5DATA1_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F5DATA1_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F5DATA1_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F5DATA1_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F5DATA1_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================== F6DATA0 ======================================================== */ +#define CAN0_F6DATA0_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F6DATA0_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F6DATA0_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F6DATA0_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F6DATA0_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F6DATA0_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F6DATA0_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F6DATA0_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F6DATA0_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F6DATA0_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F6DATA0_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F6DATA0_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F6DATA0_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F6DATA0_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F6DATA0_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F6DATA0_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F6DATA0_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F6DATA0_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F6DATA0_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F6DATA0_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F6DATA0_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F6DATA0_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F6DATA0_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F6DATA0_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F6DATA0_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F6DATA0_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F6DATA0_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F6DATA0_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F6DATA0_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F6DATA0_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F6DATA0_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F6DATA0_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA0_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F6DATA0_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================== F6DATA1 ======================================================== */ +#define CAN0_F6DATA1_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F6DATA1_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F6DATA1_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F6DATA1_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F6DATA1_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F6DATA1_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F6DATA1_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F6DATA1_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F6DATA1_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F6DATA1_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F6DATA1_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F6DATA1_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F6DATA1_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F6DATA1_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F6DATA1_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F6DATA1_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F6DATA1_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F6DATA1_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F6DATA1_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F6DATA1_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F6DATA1_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F6DATA1_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F6DATA1_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F6DATA1_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F6DATA1_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F6DATA1_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F6DATA1_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F6DATA1_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F6DATA1_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F6DATA1_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F6DATA1_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F6DATA1_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F6DATA1_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F6DATA1_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================== F7DATA0 ======================================================== */ +#define CAN0_F7DATA0_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F7DATA0_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F7DATA0_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F7DATA0_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F7DATA0_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F7DATA0_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F7DATA0_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F7DATA0_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F7DATA0_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F7DATA0_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F7DATA0_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F7DATA0_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F7DATA0_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F7DATA0_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F7DATA0_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F7DATA0_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F7DATA0_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F7DATA0_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F7DATA0_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F7DATA0_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F7DATA0_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F7DATA0_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F7DATA0_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F7DATA0_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F7DATA0_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F7DATA0_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F7DATA0_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F7DATA0_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F7DATA0_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F7DATA0_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F7DATA0_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F7DATA0_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA0_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F7DATA0_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================== F7DATA1 ======================================================== */ +#define CAN0_F7DATA1_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F7DATA1_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F7DATA1_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F7DATA1_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F7DATA1_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F7DATA1_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F7DATA1_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F7DATA1_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F7DATA1_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F7DATA1_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F7DATA1_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F7DATA1_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F7DATA1_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F7DATA1_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F7DATA1_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F7DATA1_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F7DATA1_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F7DATA1_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F7DATA1_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F7DATA1_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F7DATA1_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F7DATA1_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F7DATA1_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F7DATA1_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F7DATA1_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F7DATA1_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F7DATA1_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F7DATA1_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F7DATA1_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F7DATA1_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F7DATA1_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F7DATA1_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F7DATA1_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F7DATA1_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================== F8DATA0 ======================================================== */ +#define CAN0_F8DATA0_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F8DATA0_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F8DATA0_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F8DATA0_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F8DATA0_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F8DATA0_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F8DATA0_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F8DATA0_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F8DATA0_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F8DATA0_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F8DATA0_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F8DATA0_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F8DATA0_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F8DATA0_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F8DATA0_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F8DATA0_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F8DATA0_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F8DATA0_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F8DATA0_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F8DATA0_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F8DATA0_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F8DATA0_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F8DATA0_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F8DATA0_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F8DATA0_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F8DATA0_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F8DATA0_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F8DATA0_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F8DATA0_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F8DATA0_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F8DATA0_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F8DATA0_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA0_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F8DATA0_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================== F8DATA1 ======================================================== */ +#define CAN0_F8DATA1_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F8DATA1_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F8DATA1_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F8DATA1_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F8DATA1_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F8DATA1_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F8DATA1_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F8DATA1_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F8DATA1_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F8DATA1_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F8DATA1_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F8DATA1_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F8DATA1_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F8DATA1_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F8DATA1_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F8DATA1_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F8DATA1_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F8DATA1_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F8DATA1_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F8DATA1_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F8DATA1_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F8DATA1_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F8DATA1_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F8DATA1_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F8DATA1_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F8DATA1_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F8DATA1_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F8DATA1_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F8DATA1_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F8DATA1_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F8DATA1_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F8DATA1_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F8DATA1_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F8DATA1_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================== F9DATA0 ======================================================== */ +#define CAN0_F9DATA0_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F9DATA0_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F9DATA0_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F9DATA0_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F9DATA0_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F9DATA0_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F9DATA0_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F9DATA0_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F9DATA0_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F9DATA0_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F9DATA0_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F9DATA0_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F9DATA0_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F9DATA0_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F9DATA0_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F9DATA0_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F9DATA0_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F9DATA0_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F9DATA0_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F9DATA0_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F9DATA0_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F9DATA0_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F9DATA0_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F9DATA0_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F9DATA0_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F9DATA0_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F9DATA0_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F9DATA0_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F9DATA0_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F9DATA0_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F9DATA0_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F9DATA0_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA0_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F9DATA0_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================== F9DATA1 ======================================================== */ +#define CAN0_F9DATA1_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F9DATA1_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F9DATA1_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F9DATA1_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F9DATA1_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F9DATA1_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F9DATA1_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F9DATA1_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F9DATA1_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F9DATA1_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F9DATA1_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F9DATA1_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F9DATA1_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F9DATA1_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F9DATA1_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F9DATA1_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F9DATA1_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F9DATA1_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F9DATA1_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F9DATA1_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F9DATA1_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F9DATA1_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F9DATA1_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F9DATA1_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F9DATA1_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F9DATA1_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F9DATA1_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F9DATA1_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F9DATA1_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F9DATA1_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F9DATA1_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F9DATA1_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F9DATA1_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F9DATA1_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F10DATA0 ======================================================== */ +#define CAN0_F10DATA0_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F10DATA0_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F10DATA0_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F10DATA0_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F10DATA0_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F10DATA0_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F10DATA0_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F10DATA0_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F10DATA0_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F10DATA0_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F10DATA0_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F10DATA0_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F10DATA0_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F10DATA0_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F10DATA0_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F10DATA0_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F10DATA0_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F10DATA0_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F10DATA0_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F10DATA0_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F10DATA0_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F10DATA0_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F10DATA0_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F10DATA0_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F10DATA0_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F10DATA0_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F10DATA0_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F10DATA0_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F10DATA0_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F10DATA0_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F10DATA0_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F10DATA0_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA0_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F10DATA0_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F10DATA1 ======================================================== */ +#define CAN0_F10DATA1_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F10DATA1_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F10DATA1_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F10DATA1_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F10DATA1_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F10DATA1_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F10DATA1_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F10DATA1_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F10DATA1_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F10DATA1_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F10DATA1_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F10DATA1_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F10DATA1_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F10DATA1_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F10DATA1_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F10DATA1_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F10DATA1_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F10DATA1_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F10DATA1_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F10DATA1_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F10DATA1_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F10DATA1_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F10DATA1_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F10DATA1_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F10DATA1_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F10DATA1_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F10DATA1_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F10DATA1_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F10DATA1_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F10DATA1_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F10DATA1_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F10DATA1_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F10DATA1_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F10DATA1_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F11DATA0 ======================================================== */ +#define CAN0_F11DATA0_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F11DATA0_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F11DATA0_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F11DATA0_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F11DATA0_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F11DATA0_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F11DATA0_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F11DATA0_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F11DATA0_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F11DATA0_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F11DATA0_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F11DATA0_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F11DATA0_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F11DATA0_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F11DATA0_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F11DATA0_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F11DATA0_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F11DATA0_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F11DATA0_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F11DATA0_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F11DATA0_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F11DATA0_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F11DATA0_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F11DATA0_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F11DATA0_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F11DATA0_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F11DATA0_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F11DATA0_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F11DATA0_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F11DATA0_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F11DATA0_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F11DATA0_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA0_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F11DATA0_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F11DATA1 ======================================================== */ +#define CAN0_F11DATA1_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F11DATA1_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F11DATA1_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F11DATA1_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F11DATA1_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F11DATA1_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F11DATA1_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F11DATA1_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F11DATA1_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F11DATA1_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F11DATA1_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F11DATA1_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F11DATA1_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F11DATA1_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F11DATA1_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F11DATA1_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F11DATA1_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F11DATA1_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F11DATA1_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F11DATA1_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F11DATA1_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F11DATA1_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F11DATA1_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F11DATA1_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F11DATA1_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F11DATA1_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F11DATA1_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F11DATA1_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F11DATA1_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F11DATA1_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F11DATA1_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F11DATA1_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F11DATA1_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F11DATA1_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F12DATA0 ======================================================== */ +#define CAN0_F12DATA0_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F12DATA0_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F12DATA0_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F12DATA0_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F12DATA0_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F12DATA0_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F12DATA0_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F12DATA0_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F12DATA0_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F12DATA0_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F12DATA0_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F12DATA0_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F12DATA0_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F12DATA0_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F12DATA0_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F12DATA0_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F12DATA0_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F12DATA0_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F12DATA0_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F12DATA0_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F12DATA0_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F12DATA0_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F12DATA0_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F12DATA0_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F12DATA0_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F12DATA0_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F12DATA0_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F12DATA0_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F12DATA0_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F12DATA0_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F12DATA0_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F12DATA0_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA0_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F12DATA0_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F12DATA1 ======================================================== */ +#define CAN0_F12DATA1_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F12DATA1_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F12DATA1_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F12DATA1_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F12DATA1_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F12DATA1_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F12DATA1_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F12DATA1_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F12DATA1_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F12DATA1_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F12DATA1_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F12DATA1_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F12DATA1_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F12DATA1_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F12DATA1_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F12DATA1_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F12DATA1_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F12DATA1_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F12DATA1_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F12DATA1_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F12DATA1_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F12DATA1_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F12DATA1_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F12DATA1_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F12DATA1_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F12DATA1_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F12DATA1_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F12DATA1_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F12DATA1_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F12DATA1_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F12DATA1_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F12DATA1_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F12DATA1_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F12DATA1_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F13DATA0 ======================================================== */ +#define CAN0_F13DATA0_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F13DATA0_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F13DATA0_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F13DATA0_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F13DATA0_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F13DATA0_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F13DATA0_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F13DATA0_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F13DATA0_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F13DATA0_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F13DATA0_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F13DATA0_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F13DATA0_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F13DATA0_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F13DATA0_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F13DATA0_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F13DATA0_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F13DATA0_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F13DATA0_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F13DATA0_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F13DATA0_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F13DATA0_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F13DATA0_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F13DATA0_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F13DATA0_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F13DATA0_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F13DATA0_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F13DATA0_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F13DATA0_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F13DATA0_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F13DATA0_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F13DATA0_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA0_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F13DATA0_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F13DATA1 ======================================================== */ +#define CAN0_F13DATA1_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F13DATA1_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F13DATA1_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F13DATA1_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F13DATA1_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F13DATA1_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F13DATA1_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F13DATA1_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F13DATA1_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F13DATA1_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F13DATA1_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F13DATA1_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F13DATA1_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F13DATA1_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F13DATA1_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F13DATA1_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F13DATA1_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F13DATA1_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F13DATA1_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F13DATA1_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F13DATA1_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F13DATA1_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F13DATA1_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F13DATA1_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F13DATA1_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F13DATA1_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F13DATA1_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F13DATA1_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F13DATA1_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F13DATA1_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F13DATA1_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F13DATA1_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F13DATA1_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F13DATA1_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F14DATA0 ======================================================== */ +#define CAN0_F14DATA0_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F14DATA0_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F14DATA0_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F14DATA0_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F14DATA0_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F14DATA0_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F14DATA0_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F14DATA0_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F14DATA0_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F14DATA0_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F14DATA0_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F14DATA0_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F14DATA0_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F14DATA0_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F14DATA0_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F14DATA0_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F14DATA0_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F14DATA0_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F14DATA0_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F14DATA0_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F14DATA0_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F14DATA0_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F14DATA0_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F14DATA0_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F14DATA0_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F14DATA0_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F14DATA0_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F14DATA0_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F14DATA0_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F14DATA0_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F14DATA0_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F14DATA0_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA0_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F14DATA0_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F14DATA1 ======================================================== */ +#define CAN0_F14DATA1_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F14DATA1_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F14DATA1_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F14DATA1_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F14DATA1_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F14DATA1_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F14DATA1_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F14DATA1_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F14DATA1_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F14DATA1_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F14DATA1_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F14DATA1_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F14DATA1_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F14DATA1_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F14DATA1_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F14DATA1_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F14DATA1_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F14DATA1_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F14DATA1_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F14DATA1_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F14DATA1_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F14DATA1_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F14DATA1_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F14DATA1_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F14DATA1_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F14DATA1_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F14DATA1_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F14DATA1_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F14DATA1_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F14DATA1_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F14DATA1_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F14DATA1_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F14DATA1_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F14DATA1_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F15DATA0 ======================================================== */ +#define CAN0_F15DATA0_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F15DATA0_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F15DATA0_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F15DATA0_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F15DATA0_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F15DATA0_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F15DATA0_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F15DATA0_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F15DATA0_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F15DATA0_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F15DATA0_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F15DATA0_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F15DATA0_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F15DATA0_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F15DATA0_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F15DATA0_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F15DATA0_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F15DATA0_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F15DATA0_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F15DATA0_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F15DATA0_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F15DATA0_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F15DATA0_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F15DATA0_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F15DATA0_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F15DATA0_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F15DATA0_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F15DATA0_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F15DATA0_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F15DATA0_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F15DATA0_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F15DATA0_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA0_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F15DATA0_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F15DATA1 ======================================================== */ +#define CAN0_F15DATA1_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F15DATA1_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F15DATA1_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F15DATA1_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F15DATA1_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F15DATA1_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F15DATA1_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F15DATA1_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F15DATA1_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F15DATA1_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F15DATA1_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F15DATA1_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F15DATA1_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F15DATA1_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F15DATA1_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F15DATA1_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F15DATA1_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F15DATA1_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F15DATA1_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F15DATA1_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F15DATA1_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F15DATA1_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F15DATA1_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F15DATA1_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F15DATA1_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F15DATA1_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F15DATA1_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F15DATA1_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F15DATA1_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F15DATA1_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F15DATA1_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F15DATA1_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F15DATA1_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F15DATA1_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F16DATA0 ======================================================== */ +#define CAN0_F16DATA0_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F16DATA0_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F16DATA0_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F16DATA0_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F16DATA0_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F16DATA0_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F16DATA0_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F16DATA0_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F16DATA0_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F16DATA0_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F16DATA0_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F16DATA0_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F16DATA0_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F16DATA0_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F16DATA0_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F16DATA0_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F16DATA0_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F16DATA0_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F16DATA0_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F16DATA0_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F16DATA0_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F16DATA0_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F16DATA0_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F16DATA0_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F16DATA0_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F16DATA0_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F16DATA0_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F16DATA0_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F16DATA0_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F16DATA0_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F16DATA0_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F16DATA0_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA0_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F16DATA0_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F16DATA1 ======================================================== */ +#define CAN0_F16DATA1_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F16DATA1_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F16DATA1_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F16DATA1_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F16DATA1_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F16DATA1_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F16DATA1_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F16DATA1_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F16DATA1_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F16DATA1_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F16DATA1_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F16DATA1_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F16DATA1_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F16DATA1_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F16DATA1_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F16DATA1_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F16DATA1_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F16DATA1_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F16DATA1_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F16DATA1_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F16DATA1_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F16DATA1_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F16DATA1_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F16DATA1_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F16DATA1_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F16DATA1_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F16DATA1_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F16DATA1_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F16DATA1_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F16DATA1_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F16DATA1_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F16DATA1_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F16DATA1_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F16DATA1_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F17DATA0 ======================================================== */ +#define CAN0_F17DATA0_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F17DATA0_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F17DATA0_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F17DATA0_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F17DATA0_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F17DATA0_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F17DATA0_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F17DATA0_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F17DATA0_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F17DATA0_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F17DATA0_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F17DATA0_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F17DATA0_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F17DATA0_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F17DATA0_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F17DATA0_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F17DATA0_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F17DATA0_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F17DATA0_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F17DATA0_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F17DATA0_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F17DATA0_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F17DATA0_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F17DATA0_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F17DATA0_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F17DATA0_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F17DATA0_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F17DATA0_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F17DATA0_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F17DATA0_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F17DATA0_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F17DATA0_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA0_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F17DATA0_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F17DATA1 ======================================================== */ +#define CAN0_F17DATA1_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F17DATA1_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F17DATA1_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F17DATA1_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F17DATA1_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F17DATA1_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F17DATA1_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F17DATA1_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F17DATA1_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F17DATA1_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F17DATA1_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F17DATA1_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F17DATA1_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F17DATA1_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F17DATA1_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F17DATA1_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F17DATA1_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F17DATA1_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F17DATA1_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F17DATA1_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F17DATA1_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F17DATA1_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F17DATA1_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F17DATA1_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F17DATA1_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F17DATA1_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F17DATA1_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F17DATA1_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F17DATA1_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F17DATA1_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F17DATA1_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F17DATA1_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F17DATA1_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F17DATA1_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F18DATA0 ======================================================== */ +#define CAN0_F18DATA0_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F18DATA0_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F18DATA0_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F18DATA0_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F18DATA0_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F18DATA0_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F18DATA0_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F18DATA0_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F18DATA0_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F18DATA0_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F18DATA0_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F18DATA0_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F18DATA0_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F18DATA0_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F18DATA0_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F18DATA0_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F18DATA0_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F18DATA0_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F18DATA0_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F18DATA0_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F18DATA0_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F18DATA0_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F18DATA0_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F18DATA0_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F18DATA0_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F18DATA0_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F18DATA0_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F18DATA0_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F18DATA0_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F18DATA0_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F18DATA0_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F18DATA0_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA0_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F18DATA0_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F18DATA1 ======================================================== */ +#define CAN0_F18DATA1_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F18DATA1_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F18DATA1_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F18DATA1_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F18DATA1_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F18DATA1_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F18DATA1_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F18DATA1_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F18DATA1_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F18DATA1_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F18DATA1_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F18DATA1_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F18DATA1_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F18DATA1_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F18DATA1_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F18DATA1_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F18DATA1_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F18DATA1_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F18DATA1_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F18DATA1_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F18DATA1_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F18DATA1_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F18DATA1_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F18DATA1_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F18DATA1_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F18DATA1_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F18DATA1_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F18DATA1_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F18DATA1_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F18DATA1_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F18DATA1_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F18DATA1_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F18DATA1_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F18DATA1_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F19DATA0 ======================================================== */ +#define CAN0_F19DATA0_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F19DATA0_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F19DATA0_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F19DATA0_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F19DATA0_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F19DATA0_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F19DATA0_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F19DATA0_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F19DATA0_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F19DATA0_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F19DATA0_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F19DATA0_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F19DATA0_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F19DATA0_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F19DATA0_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F19DATA0_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F19DATA0_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F19DATA0_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F19DATA0_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F19DATA0_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F19DATA0_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F19DATA0_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F19DATA0_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F19DATA0_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F19DATA0_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F19DATA0_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F19DATA0_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F19DATA0_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F19DATA0_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F19DATA0_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F19DATA0_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F19DATA0_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA0_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F19DATA0_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F19DATA1 ======================================================== */ +#define CAN0_F19DATA1_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F19DATA1_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F19DATA1_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F19DATA1_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F19DATA1_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F19DATA1_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F19DATA1_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F19DATA1_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F19DATA1_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F19DATA1_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F19DATA1_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F19DATA1_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F19DATA1_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F19DATA1_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F19DATA1_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F19DATA1_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F19DATA1_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F19DATA1_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F19DATA1_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F19DATA1_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F19DATA1_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F19DATA1_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F19DATA1_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F19DATA1_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F19DATA1_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F19DATA1_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F19DATA1_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F19DATA1_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F19DATA1_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F19DATA1_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F19DATA1_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F19DATA1_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F19DATA1_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F19DATA1_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F20DATA0 ======================================================== */ +#define CAN0_F20DATA0_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F20DATA0_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F20DATA0_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F20DATA0_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F20DATA0_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F20DATA0_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F20DATA0_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F20DATA0_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F20DATA0_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F20DATA0_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F20DATA0_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F20DATA0_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F20DATA0_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F20DATA0_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F20DATA0_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F20DATA0_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F20DATA0_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F20DATA0_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F20DATA0_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F20DATA0_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F20DATA0_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F20DATA0_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F20DATA0_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F20DATA0_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F20DATA0_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F20DATA0_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F20DATA0_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F20DATA0_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F20DATA0_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F20DATA0_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F20DATA0_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F20DATA0_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA0_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F20DATA0_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F20DATA1 ======================================================== */ +#define CAN0_F20DATA1_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F20DATA1_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F20DATA1_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F20DATA1_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F20DATA1_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F20DATA1_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F20DATA1_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F20DATA1_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F20DATA1_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F20DATA1_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F20DATA1_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F20DATA1_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F20DATA1_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F20DATA1_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F20DATA1_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F20DATA1_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F20DATA1_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F20DATA1_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F20DATA1_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F20DATA1_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F20DATA1_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F20DATA1_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F20DATA1_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F20DATA1_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F20DATA1_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F20DATA1_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F20DATA1_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F20DATA1_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F20DATA1_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F20DATA1_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F20DATA1_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F20DATA1_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F20DATA1_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F20DATA1_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F21DATA0 ======================================================== */ +#define CAN0_F21DATA0_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F21DATA0_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F21DATA0_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F21DATA0_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F21DATA0_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F21DATA0_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F21DATA0_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F21DATA0_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F21DATA0_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F21DATA0_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F21DATA0_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F21DATA0_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F21DATA0_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F21DATA0_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F21DATA0_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F21DATA0_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F21DATA0_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F21DATA0_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F21DATA0_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F21DATA0_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F21DATA0_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F21DATA0_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F21DATA0_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F21DATA0_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F21DATA0_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F21DATA0_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F21DATA0_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F21DATA0_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F21DATA0_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F21DATA0_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F21DATA0_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F21DATA0_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA0_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F21DATA0_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F21DATA1 ======================================================== */ +#define CAN0_F21DATA1_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F21DATA1_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F21DATA1_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F21DATA1_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F21DATA1_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F21DATA1_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F21DATA1_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F21DATA1_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F21DATA1_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F21DATA1_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F21DATA1_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F21DATA1_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F21DATA1_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F21DATA1_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F21DATA1_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F21DATA1_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F21DATA1_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F21DATA1_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F21DATA1_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F21DATA1_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F21DATA1_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F21DATA1_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F21DATA1_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F21DATA1_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F21DATA1_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F21DATA1_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F21DATA1_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F21DATA1_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F21DATA1_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F21DATA1_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F21DATA1_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F21DATA1_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F21DATA1_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F21DATA1_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F22DATA0 ======================================================== */ +#define CAN0_F22DATA0_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F22DATA0_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F22DATA0_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F22DATA0_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F22DATA0_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F22DATA0_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F22DATA0_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F22DATA0_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F22DATA0_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F22DATA0_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F22DATA0_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F22DATA0_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F22DATA0_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F22DATA0_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F22DATA0_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F22DATA0_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F22DATA0_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F22DATA0_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F22DATA0_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F22DATA0_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F22DATA0_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F22DATA0_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F22DATA0_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F22DATA0_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F22DATA0_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F22DATA0_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F22DATA0_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F22DATA0_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F22DATA0_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F22DATA0_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F22DATA0_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F22DATA0_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA0_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F22DATA0_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F22DATA1 ======================================================== */ +#define CAN0_F22DATA1_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F22DATA1_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F22DATA1_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F22DATA1_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F22DATA1_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F22DATA1_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F22DATA1_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F22DATA1_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F22DATA1_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F22DATA1_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F22DATA1_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F22DATA1_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F22DATA1_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F22DATA1_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F22DATA1_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F22DATA1_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F22DATA1_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F22DATA1_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F22DATA1_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F22DATA1_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F22DATA1_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F22DATA1_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F22DATA1_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F22DATA1_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F22DATA1_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F22DATA1_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F22DATA1_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F22DATA1_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F22DATA1_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F22DATA1_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F22DATA1_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F22DATA1_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F22DATA1_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F22DATA1_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F23DATA0 ======================================================== */ +#define CAN0_F23DATA0_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F23DATA0_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F23DATA0_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F23DATA0_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F23DATA0_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F23DATA0_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F23DATA0_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F23DATA0_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F23DATA0_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F23DATA0_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F23DATA0_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F23DATA0_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F23DATA0_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F23DATA0_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F23DATA0_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F23DATA0_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F23DATA0_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F23DATA0_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F23DATA0_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F23DATA0_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F23DATA0_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F23DATA0_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F23DATA0_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F23DATA0_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F23DATA0_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F23DATA0_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F23DATA0_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F23DATA0_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F23DATA0_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F23DATA0_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F23DATA0_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F23DATA0_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA0_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F23DATA0_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F23DATA1 ======================================================== */ +#define CAN0_F23DATA1_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F23DATA1_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F23DATA1_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F23DATA1_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F23DATA1_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F23DATA1_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F23DATA1_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F23DATA1_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F23DATA1_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F23DATA1_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F23DATA1_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F23DATA1_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F23DATA1_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F23DATA1_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F23DATA1_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F23DATA1_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F23DATA1_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F23DATA1_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F23DATA1_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F23DATA1_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F23DATA1_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F23DATA1_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F23DATA1_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F23DATA1_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F23DATA1_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F23DATA1_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F23DATA1_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F23DATA1_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F23DATA1_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F23DATA1_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F23DATA1_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F23DATA1_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F23DATA1_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F23DATA1_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F24DATA0 ======================================================== */ +#define CAN0_F24DATA0_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F24DATA0_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F24DATA0_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F24DATA0_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F24DATA0_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F24DATA0_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F24DATA0_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F24DATA0_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F24DATA0_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F24DATA0_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F24DATA0_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F24DATA0_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F24DATA0_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F24DATA0_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F24DATA0_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F24DATA0_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F24DATA0_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F24DATA0_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F24DATA0_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F24DATA0_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F24DATA0_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F24DATA0_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F24DATA0_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F24DATA0_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F24DATA0_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F24DATA0_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F24DATA0_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F24DATA0_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F24DATA0_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F24DATA0_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F24DATA0_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F24DATA0_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA0_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F24DATA0_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F24DATA1 ======================================================== */ +#define CAN0_F24DATA1_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F24DATA1_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F24DATA1_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F24DATA1_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F24DATA1_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F24DATA1_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F24DATA1_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F24DATA1_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F24DATA1_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F24DATA1_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F24DATA1_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F24DATA1_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F24DATA1_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F24DATA1_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F24DATA1_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F24DATA1_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F24DATA1_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F24DATA1_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F24DATA1_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F24DATA1_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F24DATA1_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F24DATA1_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F24DATA1_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F24DATA1_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F24DATA1_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F24DATA1_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F24DATA1_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F24DATA1_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F24DATA1_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F24DATA1_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F24DATA1_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F24DATA1_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F24DATA1_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F24DATA1_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F25DATA0 ======================================================== */ +#define CAN0_F25DATA0_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F25DATA0_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F25DATA0_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F25DATA0_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F25DATA0_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F25DATA0_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F25DATA0_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F25DATA0_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F25DATA0_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F25DATA0_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F25DATA0_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F25DATA0_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F25DATA0_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F25DATA0_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F25DATA0_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F25DATA0_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F25DATA0_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F25DATA0_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F25DATA0_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F25DATA0_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F25DATA0_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F25DATA0_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F25DATA0_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F25DATA0_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F25DATA0_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F25DATA0_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F25DATA0_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F25DATA0_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F25DATA0_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F25DATA0_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F25DATA0_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F25DATA0_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA0_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F25DATA0_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F25DATA1 ======================================================== */ +#define CAN0_F25DATA1_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F25DATA1_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F25DATA1_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F25DATA1_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F25DATA1_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F25DATA1_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F25DATA1_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F25DATA1_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F25DATA1_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F25DATA1_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F25DATA1_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F25DATA1_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F25DATA1_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F25DATA1_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F25DATA1_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F25DATA1_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F25DATA1_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F25DATA1_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F25DATA1_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F25DATA1_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F25DATA1_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F25DATA1_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F25DATA1_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F25DATA1_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F25DATA1_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F25DATA1_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F25DATA1_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F25DATA1_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F25DATA1_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F25DATA1_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F25DATA1_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F25DATA1_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F25DATA1_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F25DATA1_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F26DATA0 ======================================================== */ +#define CAN0_F26DATA0_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F26DATA0_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F26DATA0_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F26DATA0_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F26DATA0_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F26DATA0_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F26DATA0_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F26DATA0_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F26DATA0_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F26DATA0_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F26DATA0_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F26DATA0_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F26DATA0_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F26DATA0_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F26DATA0_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F26DATA0_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F26DATA0_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F26DATA0_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F26DATA0_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F26DATA0_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F26DATA0_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F26DATA0_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F26DATA0_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F26DATA0_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F26DATA0_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F26DATA0_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F26DATA0_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F26DATA0_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F26DATA0_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F26DATA0_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F26DATA0_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F26DATA0_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA0_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F26DATA0_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F26DATA1 ======================================================== */ +#define CAN0_F26DATA1_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F26DATA1_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F26DATA1_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F26DATA1_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F26DATA1_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F26DATA1_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F26DATA1_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F26DATA1_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F26DATA1_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F26DATA1_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F26DATA1_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F26DATA1_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F26DATA1_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F26DATA1_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F26DATA1_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F26DATA1_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F26DATA1_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F26DATA1_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F26DATA1_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F26DATA1_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F26DATA1_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F26DATA1_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F26DATA1_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F26DATA1_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F26DATA1_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F26DATA1_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F26DATA1_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F26DATA1_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F26DATA1_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F26DATA1_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F26DATA1_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F26DATA1_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F26DATA1_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F26DATA1_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F27DATA0 ======================================================== */ +#define CAN0_F27DATA0_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F27DATA0_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F27DATA0_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F27DATA0_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F27DATA0_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F27DATA0_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F27DATA0_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F27DATA0_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F27DATA0_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F27DATA0_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F27DATA0_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F27DATA0_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F27DATA0_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F27DATA0_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F27DATA0_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F27DATA0_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F27DATA0_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F27DATA0_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F27DATA0_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F27DATA0_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F27DATA0_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F27DATA0_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F27DATA0_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F27DATA0_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F27DATA0_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F27DATA0_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F27DATA0_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F27DATA0_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F27DATA0_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F27DATA0_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F27DATA0_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F27DATA0_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA0_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F27DATA0_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ +/* ======================================================= F27DATA1 ======================================================== */ +#define CAN0_F27DATA1_FD0_Pos (0UL) /*!< FD0 (Bit 0) */ +#define CAN0_F27DATA1_FD0_Msk (0x1UL) /*!< FD0 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD1_Pos (1UL) /*!< FD1 (Bit 1) */ +#define CAN0_F27DATA1_FD1_Msk (0x2UL) /*!< FD1 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD2_Pos (2UL) /*!< FD2 (Bit 2) */ +#define CAN0_F27DATA1_FD2_Msk (0x4UL) /*!< FD2 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD3_Pos (3UL) /*!< FD3 (Bit 3) */ +#define CAN0_F27DATA1_FD3_Msk (0x8UL) /*!< FD3 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD4_Pos (4UL) /*!< FD4 (Bit 4) */ +#define CAN0_F27DATA1_FD4_Msk (0x10UL) /*!< FD4 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD5_Pos (5UL) /*!< FD5 (Bit 5) */ +#define CAN0_F27DATA1_FD5_Msk (0x20UL) /*!< FD5 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD6_Pos (6UL) /*!< FD6 (Bit 6) */ +#define CAN0_F27DATA1_FD6_Msk (0x40UL) /*!< FD6 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD7_Pos (7UL) /*!< FD7 (Bit 7) */ +#define CAN0_F27DATA1_FD7_Msk (0x80UL) /*!< FD7 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD8_Pos (8UL) /*!< FD8 (Bit 8) */ +#define CAN0_F27DATA1_FD8_Msk (0x100UL) /*!< FD8 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD9_Pos (9UL) /*!< FD9 (Bit 9) */ +#define CAN0_F27DATA1_FD9_Msk (0x200UL) /*!< FD9 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD10_Pos (10UL) /*!< FD10 (Bit 10) */ +#define CAN0_F27DATA1_FD10_Msk (0x400UL) /*!< FD10 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD11_Pos (11UL) /*!< FD11 (Bit 11) */ +#define CAN0_F27DATA1_FD11_Msk (0x800UL) /*!< FD11 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD12_Pos (12UL) /*!< FD12 (Bit 12) */ +#define CAN0_F27DATA1_FD12_Msk (0x1000UL) /*!< FD12 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD13_Pos (13UL) /*!< FD13 (Bit 13) */ +#define CAN0_F27DATA1_FD13_Msk (0x2000UL) /*!< FD13 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD14_Pos (14UL) /*!< FD14 (Bit 14) */ +#define CAN0_F27DATA1_FD14_Msk (0x4000UL) /*!< FD14 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD15_Pos (15UL) /*!< FD15 (Bit 15) */ +#define CAN0_F27DATA1_FD15_Msk (0x8000UL) /*!< FD15 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD16_Pos (16UL) /*!< FD16 (Bit 16) */ +#define CAN0_F27DATA1_FD16_Msk (0x10000UL) /*!< FD16 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD17_Pos (17UL) /*!< FD17 (Bit 17) */ +#define CAN0_F27DATA1_FD17_Msk (0x20000UL) /*!< FD17 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD18_Pos (18UL) /*!< FD18 (Bit 18) */ +#define CAN0_F27DATA1_FD18_Msk (0x40000UL) /*!< FD18 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD19_Pos (19UL) /*!< FD19 (Bit 19) */ +#define CAN0_F27DATA1_FD19_Msk (0x80000UL) /*!< FD19 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD20_Pos (20UL) /*!< FD20 (Bit 20) */ +#define CAN0_F27DATA1_FD20_Msk (0x100000UL) /*!< FD20 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD21_Pos (21UL) /*!< FD21 (Bit 21) */ +#define CAN0_F27DATA1_FD21_Msk (0x200000UL) /*!< FD21 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD22_Pos (22UL) /*!< FD22 (Bit 22) */ +#define CAN0_F27DATA1_FD22_Msk (0x400000UL) /*!< FD22 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD23_Pos (23UL) /*!< FD23 (Bit 23) */ +#define CAN0_F27DATA1_FD23_Msk (0x800000UL) /*!< FD23 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD24_Pos (24UL) /*!< FD24 (Bit 24) */ +#define CAN0_F27DATA1_FD24_Msk (0x1000000UL) /*!< FD24 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD25_Pos (25UL) /*!< FD25 (Bit 25) */ +#define CAN0_F27DATA1_FD25_Msk (0x2000000UL) /*!< FD25 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD26_Pos (26UL) /*!< FD26 (Bit 26) */ +#define CAN0_F27DATA1_FD26_Msk (0x4000000UL) /*!< FD26 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD27_Pos (27UL) /*!< FD27 (Bit 27) */ +#define CAN0_F27DATA1_FD27_Msk (0x8000000UL) /*!< FD27 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD28_Pos (28UL) /*!< FD28 (Bit 28) */ +#define CAN0_F27DATA1_FD28_Msk (0x10000000UL) /*!< FD28 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD29_Pos (29UL) /*!< FD29 (Bit 29) */ +#define CAN0_F27DATA1_FD29_Msk (0x20000000UL) /*!< FD29 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD30_Pos (30UL) /*!< FD30 (Bit 30) */ +#define CAN0_F27DATA1_FD30_Msk (0x40000000UL) /*!< FD30 (Bitfield-Mask: 0x01) */ +#define CAN0_F27DATA1_FD31_Pos (31UL) /*!< FD31 (Bit 31) */ +#define CAN0_F27DATA1_FD31_Msk (0x80000000UL) /*!< FD31 (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ CRC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DATA ========================================================== */ +#define CRC_DATA_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define CRC_DATA_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= FDATA ========================================================= */ +#define CRC_FDATA_FDATA_Pos (0UL) /*!< FDATA (Bit 0) */ +#define CRC_FDATA_FDATA_Msk (0xffUL) /*!< FDATA (Bitfield-Mask: 0xff) */ +/* ========================================================== CTL ========================================================== */ +#define CRC_CTL_RST_Pos (0UL) /*!< RST (Bit 0) */ +#define CRC_CTL_RST_Msk (0x1UL) /*!< RST (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ DAC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CTL ========================================================== */ +#define DAC_CTL_DEN0_Pos (0UL) /*!< DEN0 (Bit 0) */ +#define DAC_CTL_DEN0_Msk (0x1UL) /*!< DEN0 (Bitfield-Mask: 0x01) */ +#define DAC_CTL_DBOFF0_Pos (1UL) /*!< DBOFF0 (Bit 1) */ +#define DAC_CTL_DBOFF0_Msk (0x2UL) /*!< DBOFF0 (Bitfield-Mask: 0x01) */ +#define DAC_CTL_DTEN0_Pos (2UL) /*!< DTEN0 (Bit 2) */ +#define DAC_CTL_DTEN0_Msk (0x4UL) /*!< DTEN0 (Bitfield-Mask: 0x01) */ +#define DAC_CTL_DTSEL0_Pos (3UL) /*!< DTSEL0 (Bit 3) */ +#define DAC_CTL_DTSEL0_Msk (0x38UL) /*!< DTSEL0 (Bitfield-Mask: 0x07) */ +#define DAC_CTL_DWM0_Pos (6UL) /*!< DWM0 (Bit 6) */ +#define DAC_CTL_DWM0_Msk (0xc0UL) /*!< DWM0 (Bitfield-Mask: 0x03) */ +#define DAC_CTL_DWBW0_Pos (8UL) /*!< DWBW0 (Bit 8) */ +#define DAC_CTL_DWBW0_Msk (0xf00UL) /*!< DWBW0 (Bitfield-Mask: 0x0f) */ +#define DAC_CTL_DDMAEN0_Pos (12UL) /*!< DDMAEN0 (Bit 12) */ +#define DAC_CTL_DDMAEN0_Msk (0x1000UL) /*!< DDMAEN0 (Bitfield-Mask: 0x01) */ +#define DAC_CTL_DEN1_Pos (16UL) /*!< DEN1 (Bit 16) */ +#define DAC_CTL_DEN1_Msk (0x10000UL) /*!< DEN1 (Bitfield-Mask: 0x01) */ +#define DAC_CTL_DBOFF1_Pos (17UL) /*!< DBOFF1 (Bit 17) */ +#define DAC_CTL_DBOFF1_Msk (0x20000UL) /*!< DBOFF1 (Bitfield-Mask: 0x01) */ +#define DAC_CTL_DTEN1_Pos (18UL) /*!< DTEN1 (Bit 18) */ +#define DAC_CTL_DTEN1_Msk (0x40000UL) /*!< DTEN1 (Bitfield-Mask: 0x01) */ +#define DAC_CTL_DTSEL1_Pos (19UL) /*!< DTSEL1 (Bit 19) */ +#define DAC_CTL_DTSEL1_Msk (0x380000UL) /*!< DTSEL1 (Bitfield-Mask: 0x07) */ +#define DAC_CTL_DWM1_Pos (22UL) /*!< DWM1 (Bit 22) */ +#define DAC_CTL_DWM1_Msk (0xc00000UL) /*!< DWM1 (Bitfield-Mask: 0x03) */ +#define DAC_CTL_DWBW1_Pos (24UL) /*!< DWBW1 (Bit 24) */ +#define DAC_CTL_DWBW1_Msk (0xf000000UL) /*!< DWBW1 (Bitfield-Mask: 0x0f) */ +#define DAC_CTL_DDMAEN1_Pos (28UL) /*!< DDMAEN1 (Bit 28) */ +#define DAC_CTL_DDMAEN1_Msk (0x10000000UL) /*!< DDMAEN1 (Bitfield-Mask: 0x01) */ +/* ========================================================== SWT ========================================================== */ +#define DAC_SWT_SWTR0_Pos (0UL) /*!< SWTR0 (Bit 0) */ +#define DAC_SWT_SWTR0_Msk (0x1UL) /*!< SWTR0 (Bitfield-Mask: 0x01) */ +#define DAC_SWT_SWTR1_Pos (1UL) /*!< SWTR1 (Bit 1) */ +#define DAC_SWT_SWTR1_Msk (0x2UL) /*!< SWTR1 (Bitfield-Mask: 0x01) */ +/* ====================================================== DAC0_R12DH ======================================================= */ +#define DAC_DAC0_R12DH_DAC0_DH_Pos (0UL) /*!< DAC0_DH (Bit 0) */ +#define DAC_DAC0_R12DH_DAC0_DH_Msk (0xfffUL) /*!< DAC0_DH (Bitfield-Mask: 0xfff) */ +/* ====================================================== DAC0_L12DH ======================================================= */ +#define DAC_DAC0_L12DH_DAC0_DH_Pos (4UL) /*!< DAC0_DH (Bit 4) */ +#define DAC_DAC0_L12DH_DAC0_DH_Msk (0xfff0UL) /*!< DAC0_DH (Bitfield-Mask: 0xfff) */ +/* ======================================================= DAC0_R8DH ======================================================= */ +#define DAC_DAC0_R8DH_DAC0_DH_Pos (0UL) /*!< DAC0_DH (Bit 0) */ +#define DAC_DAC0_R8DH_DAC0_DH_Msk (0xffUL) /*!< DAC0_DH (Bitfield-Mask: 0xff) */ +/* ====================================================== DAC1_R12DH ======================================================= */ +#define DAC_DAC1_R12DH_DAC1_DH_Pos (0UL) /*!< DAC1_DH (Bit 0) */ +#define DAC_DAC1_R12DH_DAC1_DH_Msk (0xfffUL) /*!< DAC1_DH (Bitfield-Mask: 0xfff) */ +/* ====================================================== DAC1_L12DH ======================================================= */ +#define DAC_DAC1_L12DH_DAC1_DH_Pos (4UL) /*!< DAC1_DH (Bit 4) */ +#define DAC_DAC1_L12DH_DAC1_DH_Msk (0xfff0UL) /*!< DAC1_DH (Bitfield-Mask: 0xfff) */ +/* ======================================================= DAC1_R8DH ======================================================= */ +#define DAC_DAC1_R8DH_DAC1_DH_Pos (0UL) /*!< DAC1_DH (Bit 0) */ +#define DAC_DAC1_R8DH_DAC1_DH_Msk (0xffUL) /*!< DAC1_DH (Bitfield-Mask: 0xff) */ +/* ====================================================== DACC_R12DH ======================================================= */ +#define DAC_DACC_R12DH_DAC0_DH_Pos (0UL) /*!< DAC0_DH (Bit 0) */ +#define DAC_DACC_R12DH_DAC0_DH_Msk (0xfffUL) /*!< DAC0_DH (Bitfield-Mask: 0xfff) */ +#define DAC_DACC_R12DH_DAC1_DH_Pos (16UL) /*!< DAC1_DH (Bit 16) */ +#define DAC_DACC_R12DH_DAC1_DH_Msk (0xfff0000UL) /*!< DAC1_DH (Bitfield-Mask: 0xfff) */ +/* ====================================================== DACC_L12DH ======================================================= */ +#define DAC_DACC_L12DH_DAC0_DH_Pos (4UL) /*!< DAC0_DH (Bit 4) */ +#define DAC_DACC_L12DH_DAC0_DH_Msk (0xfff0UL) /*!< DAC0_DH (Bitfield-Mask: 0xfff) */ +#define DAC_DACC_L12DH_DAC1_DH_Pos (20UL) /*!< DAC1_DH (Bit 20) */ +#define DAC_DACC_L12DH_DAC1_DH_Msk (0xfff00000UL) /*!< DAC1_DH (Bitfield-Mask: 0xfff) */ +/* ======================================================= DACC_R8DH ======================================================= */ +#define DAC_DACC_R8DH_DAC0_DH_Pos (0UL) /*!< DAC0_DH (Bit 0) */ +#define DAC_DACC_R8DH_DAC0_DH_Msk (0xffUL) /*!< DAC0_DH (Bitfield-Mask: 0xff) */ +#define DAC_DACC_R8DH_DAC1_DH_Pos (8UL) /*!< DAC1_DH (Bit 8) */ +#define DAC_DACC_R8DH_DAC1_DH_Msk (0xff00UL) /*!< DAC1_DH (Bitfield-Mask: 0xff) */ +/* ======================================================== DAC0_DO ======================================================== */ +#define DAC_DAC0_DO_DAC0_DO_Pos (0UL) /*!< DAC0_DO (Bit 0) */ +#define DAC_DAC0_DO_DAC0_DO_Msk (0xfffUL) /*!< DAC0_DO (Bitfield-Mask: 0xfff) */ +/* ======================================================== DAC1_DO ======================================================== */ +#define DAC_DAC1_DO_DAC1_DO_Pos (0UL) /*!< DAC1_DO (Bit 0) */ +#define DAC_DAC1_DO_DAC1_DO_Msk (0xfffUL) /*!< DAC1_DO (Bitfield-Mask: 0xfff) */ + + +/* =========================================================================================================================== */ +/* ================ DBG ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ +#define DBG_ID_ID_CODE_Pos (0UL) /*!< ID_CODE (Bit 0) */ +#define DBG_ID_ID_CODE_Msk (0xffffffffUL) /*!< ID_CODE (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== CTL ========================================================== */ +#define DBG_CTL_SLP_HOLD_Pos (0UL) /*!< SLP_HOLD (Bit 0) */ +#define DBG_CTL_SLP_HOLD_Msk (0x1UL) /*!< SLP_HOLD (Bitfield-Mask: 0x01) */ +#define DBG_CTL_DSLP_HOLD_Pos (1UL) /*!< DSLP_HOLD (Bit 1) */ +#define DBG_CTL_DSLP_HOLD_Msk (0x2UL) /*!< DSLP_HOLD (Bitfield-Mask: 0x01) */ +#define DBG_CTL_STB_HOLD_Pos (2UL) /*!< STB_HOLD (Bit 2) */ +#define DBG_CTL_STB_HOLD_Msk (0x4UL) /*!< STB_HOLD (Bitfield-Mask: 0x01) */ +#define DBG_CTL_FWDGT_HOLD_Pos (8UL) /*!< FWDGT_HOLD (Bit 8) */ +#define DBG_CTL_FWDGT_HOLD_Msk (0x100UL) /*!< FWDGT_HOLD (Bitfield-Mask: 0x01) */ +#define DBG_CTL_WWDGT_HOLD_Pos (9UL) /*!< WWDGT_HOLD (Bit 9) */ +#define DBG_CTL_WWDGT_HOLD_Msk (0x200UL) /*!< WWDGT_HOLD (Bitfield-Mask: 0x01) */ +#define DBG_CTL_TIMER0_HOLD_Pos (10UL) /*!< TIMER0_HOLD (Bit 10) */ +#define DBG_CTL_TIMER0_HOLD_Msk (0x400UL) /*!< TIMER0_HOLD (Bitfield-Mask: 0x01) */ +#define DBG_CTL_TIMER1_HOLD_Pos (11UL) /*!< TIMER1_HOLD (Bit 11) */ +#define DBG_CTL_TIMER1_HOLD_Msk (0x800UL) /*!< TIMER1_HOLD (Bitfield-Mask: 0x01) */ +#define DBG_CTL_TIMER2_HOLD_Pos (12UL) /*!< TIMER2_HOLD (Bit 12) */ +#define DBG_CTL_TIMER2_HOLD_Msk (0x1000UL) /*!< TIMER2_HOLD (Bitfield-Mask: 0x01) */ +#define DBG_CTL_TIMER3_HOLD_Pos (13UL) /*!< TIMER3_HOLD (Bit 13) */ +#define DBG_CTL_TIMER3_HOLD_Msk (0x2000UL) /*!< TIMER3_HOLD (Bitfield-Mask: 0x01) */ +#define DBG_CTL_CAN0_HOLD_Pos (14UL) /*!< CAN0_HOLD (Bit 14) */ +#define DBG_CTL_CAN0_HOLD_Msk (0x4000UL) /*!< CAN0_HOLD (Bitfield-Mask: 0x01) */ +#define DBG_CTL_I2C0_HOLD_Pos (15UL) /*!< I2C0_HOLD (Bit 15) */ +#define DBG_CTL_I2C0_HOLD_Msk (0x8000UL) /*!< I2C0_HOLD (Bitfield-Mask: 0x01) */ +#define DBG_CTL_I2C1_HOLD_Pos (16UL) /*!< I2C1_HOLD (Bit 16) */ +#define DBG_CTL_I2C1_HOLD_Msk (0x10000UL) /*!< I2C1_HOLD (Bitfield-Mask: 0x01) */ +#define DBG_CTL_TIMER4_HOLD_Pos (18UL) /*!< TIMER4_HOLD (Bit 18) */ +#define DBG_CTL_TIMER4_HOLD_Msk (0x40000UL) /*!< TIMER4_HOLD (Bitfield-Mask: 0x01) */ +#define DBG_CTL_TIMER5_HOLD_Pos (19UL) /*!< TIMER5_HOLD (Bit 19) */ +#define DBG_CTL_TIMER5_HOLD_Msk (0x80000UL) /*!< TIMER5_HOLD (Bitfield-Mask: 0x01) */ +#define DBG_CTL_TIMER6_HOLD_Pos (20UL) /*!< TIMER6_HOLD (Bit 20) */ +#define DBG_CTL_TIMER6_HOLD_Msk (0x100000UL) /*!< TIMER6_HOLD (Bitfield-Mask: 0x01) */ +#define DBG_CTL_CAN1_HOLD_Pos (21UL) /*!< CAN1_HOLD (Bit 21) */ +#define DBG_CTL_CAN1_HOLD_Msk (0x200000UL) /*!< CAN1_HOLD (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ DMA0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= INTF ========================================================== */ +#define DMA0_INTF_GIF0_Pos (0UL) /*!< GIF0 (Bit 0) */ +#define DMA0_INTF_GIF0_Msk (0x1UL) /*!< GIF0 (Bitfield-Mask: 0x01) */ +#define DMA0_INTF_FTFIF0_Pos (1UL) /*!< FTFIF0 (Bit 1) */ +#define DMA0_INTF_FTFIF0_Msk (0x2UL) /*!< FTFIF0 (Bitfield-Mask: 0x01) */ +#define DMA0_INTF_HTFIF0_Pos (2UL) /*!< HTFIF0 (Bit 2) */ +#define DMA0_INTF_HTFIF0_Msk (0x4UL) /*!< HTFIF0 (Bitfield-Mask: 0x01) */ +#define DMA0_INTF_ERRIF0_Pos (3UL) /*!< ERRIF0 (Bit 3) */ +#define DMA0_INTF_ERRIF0_Msk (0x8UL) /*!< ERRIF0 (Bitfield-Mask: 0x01) */ +#define DMA0_INTF_GIF1_Pos (4UL) /*!< GIF1 (Bit 4) */ +#define DMA0_INTF_GIF1_Msk (0x10UL) /*!< GIF1 (Bitfield-Mask: 0x01) */ +#define DMA0_INTF_FTFIF1_Pos (5UL) /*!< FTFIF1 (Bit 5) */ +#define DMA0_INTF_FTFIF1_Msk (0x20UL) /*!< FTFIF1 (Bitfield-Mask: 0x01) */ +#define DMA0_INTF_HTFIF1_Pos (6UL) /*!< HTFIF1 (Bit 6) */ +#define DMA0_INTF_HTFIF1_Msk (0x40UL) /*!< HTFIF1 (Bitfield-Mask: 0x01) */ +#define DMA0_INTF_ERRIF1_Pos (7UL) /*!< ERRIF1 (Bit 7) */ +#define DMA0_INTF_ERRIF1_Msk (0x80UL) /*!< ERRIF1 (Bitfield-Mask: 0x01) */ +#define DMA0_INTF_GIF2_Pos (8UL) /*!< GIF2 (Bit 8) */ +#define DMA0_INTF_GIF2_Msk (0x100UL) /*!< GIF2 (Bitfield-Mask: 0x01) */ +#define DMA0_INTF_FTFIF2_Pos (9UL) /*!< FTFIF2 (Bit 9) */ +#define DMA0_INTF_FTFIF2_Msk (0x200UL) /*!< FTFIF2 (Bitfield-Mask: 0x01) */ +#define DMA0_INTF_HTFIF2_Pos (10UL) /*!< HTFIF2 (Bit 10) */ +#define DMA0_INTF_HTFIF2_Msk (0x400UL) /*!< HTFIF2 (Bitfield-Mask: 0x01) */ +#define DMA0_INTF_ERRIF2_Pos (11UL) /*!< ERRIF2 (Bit 11) */ +#define DMA0_INTF_ERRIF2_Msk (0x800UL) /*!< ERRIF2 (Bitfield-Mask: 0x01) */ +#define DMA0_INTF_GIF3_Pos (12UL) /*!< GIF3 (Bit 12) */ +#define DMA0_INTF_GIF3_Msk (0x1000UL) /*!< GIF3 (Bitfield-Mask: 0x01) */ +#define DMA0_INTF_FTFIF3_Pos (13UL) /*!< FTFIF3 (Bit 13) */ +#define DMA0_INTF_FTFIF3_Msk (0x2000UL) /*!< FTFIF3 (Bitfield-Mask: 0x01) */ +#define DMA0_INTF_HTFIF3_Pos (14UL) /*!< HTFIF3 (Bit 14) */ +#define DMA0_INTF_HTFIF3_Msk (0x4000UL) /*!< HTFIF3 (Bitfield-Mask: 0x01) */ +#define DMA0_INTF_ERRIF3_Pos (15UL) /*!< ERRIF3 (Bit 15) */ +#define DMA0_INTF_ERRIF3_Msk (0x8000UL) /*!< ERRIF3 (Bitfield-Mask: 0x01) */ +#define DMA0_INTF_GIF4_Pos (16UL) /*!< GIF4 (Bit 16) */ +#define DMA0_INTF_GIF4_Msk (0x10000UL) /*!< GIF4 (Bitfield-Mask: 0x01) */ +#define DMA0_INTF_FTFIF4_Pos (17UL) /*!< FTFIF4 (Bit 17) */ +#define DMA0_INTF_FTFIF4_Msk (0x20000UL) /*!< FTFIF4 (Bitfield-Mask: 0x01) */ +#define DMA0_INTF_HTFIF4_Pos (18UL) /*!< HTFIF4 (Bit 18) */ +#define DMA0_INTF_HTFIF4_Msk (0x40000UL) /*!< HTFIF4 (Bitfield-Mask: 0x01) */ +#define DMA0_INTF_ERRIF4_Pos (19UL) /*!< ERRIF4 (Bit 19) */ +#define DMA0_INTF_ERRIF4_Msk (0x80000UL) /*!< ERRIF4 (Bitfield-Mask: 0x01) */ +#define DMA0_INTF_GIF5_Pos (20UL) /*!< GIF5 (Bit 20) */ +#define DMA0_INTF_GIF5_Msk (0x100000UL) /*!< GIF5 (Bitfield-Mask: 0x01) */ +#define DMA0_INTF_FTFIF5_Pos (21UL) /*!< FTFIF5 (Bit 21) */ +#define DMA0_INTF_FTFIF5_Msk (0x200000UL) /*!< FTFIF5 (Bitfield-Mask: 0x01) */ +#define DMA0_INTF_HTFIF5_Pos (22UL) /*!< HTFIF5 (Bit 22) */ +#define DMA0_INTF_HTFIF5_Msk (0x400000UL) /*!< HTFIF5 (Bitfield-Mask: 0x01) */ +#define DMA0_INTF_ERRIF5_Pos (23UL) /*!< ERRIF5 (Bit 23) */ +#define DMA0_INTF_ERRIF5_Msk (0x800000UL) /*!< ERRIF5 (Bitfield-Mask: 0x01) */ +#define DMA0_INTF_GIF6_Pos (24UL) /*!< GIF6 (Bit 24) */ +#define DMA0_INTF_GIF6_Msk (0x1000000UL) /*!< GIF6 (Bitfield-Mask: 0x01) */ +#define DMA0_INTF_FTFIF6_Pos (25UL) /*!< FTFIF6 (Bit 25) */ +#define DMA0_INTF_FTFIF6_Msk (0x2000000UL) /*!< FTFIF6 (Bitfield-Mask: 0x01) */ +#define DMA0_INTF_HTFIF6_Pos (26UL) /*!< HTFIF6 (Bit 26) */ +#define DMA0_INTF_HTFIF6_Msk (0x4000000UL) /*!< HTFIF6 (Bitfield-Mask: 0x01) */ +#define DMA0_INTF_ERRIF6_Pos (27UL) /*!< ERRIF6 (Bit 27) */ +#define DMA0_INTF_ERRIF6_Msk (0x8000000UL) /*!< ERRIF6 (Bitfield-Mask: 0x01) */ +/* ========================================================= INTC ========================================================== */ +#define DMA0_INTC_GIFC0_Pos (0UL) /*!< GIFC0 (Bit 0) */ +#define DMA0_INTC_GIFC0_Msk (0x1UL) /*!< GIFC0 (Bitfield-Mask: 0x01) */ +#define DMA0_INTC_FTFIFC0_Pos (1UL) /*!< FTFIFC0 (Bit 1) */ +#define DMA0_INTC_FTFIFC0_Msk (0x2UL) /*!< FTFIFC0 (Bitfield-Mask: 0x01) */ +#define DMA0_INTC_HTFIFC0_Pos (2UL) /*!< HTFIFC0 (Bit 2) */ +#define DMA0_INTC_HTFIFC0_Msk (0x4UL) /*!< HTFIFC0 (Bitfield-Mask: 0x01) */ +#define DMA0_INTC_ERRIFC0_Pos (3UL) /*!< ERRIFC0 (Bit 3) */ +#define DMA0_INTC_ERRIFC0_Msk (0x8UL) /*!< ERRIFC0 (Bitfield-Mask: 0x01) */ +#define DMA0_INTC_GIFC1_Pos (4UL) /*!< GIFC1 (Bit 4) */ +#define DMA0_INTC_GIFC1_Msk (0x10UL) /*!< GIFC1 (Bitfield-Mask: 0x01) */ +#define DMA0_INTC_FTFIFC1_Pos (5UL) /*!< FTFIFC1 (Bit 5) */ +#define DMA0_INTC_FTFIFC1_Msk (0x20UL) /*!< FTFIFC1 (Bitfield-Mask: 0x01) */ +#define DMA0_INTC_HTFIFC1_Pos (6UL) /*!< HTFIFC1 (Bit 6) */ +#define DMA0_INTC_HTFIFC1_Msk (0x40UL) /*!< HTFIFC1 (Bitfield-Mask: 0x01) */ +#define DMA0_INTC_ERRIFC1_Pos (7UL) /*!< ERRIFC1 (Bit 7) */ +#define DMA0_INTC_ERRIFC1_Msk (0x80UL) /*!< ERRIFC1 (Bitfield-Mask: 0x01) */ +#define DMA0_INTC_GIFC2_Pos (8UL) /*!< GIFC2 (Bit 8) */ +#define DMA0_INTC_GIFC2_Msk (0x100UL) /*!< GIFC2 (Bitfield-Mask: 0x01) */ +#define DMA0_INTC_FTFIFC2_Pos (9UL) /*!< FTFIFC2 (Bit 9) */ +#define DMA0_INTC_FTFIFC2_Msk (0x200UL) /*!< FTFIFC2 (Bitfield-Mask: 0x01) */ +#define DMA0_INTC_HTFIFC2_Pos (10UL) /*!< HTFIFC2 (Bit 10) */ +#define DMA0_INTC_HTFIFC2_Msk (0x400UL) /*!< HTFIFC2 (Bitfield-Mask: 0x01) */ +#define DMA0_INTC_ERRIFC2_Pos (11UL) /*!< ERRIFC2 (Bit 11) */ +#define DMA0_INTC_ERRIFC2_Msk (0x800UL) /*!< ERRIFC2 (Bitfield-Mask: 0x01) */ +#define DMA0_INTC_GIFC3_Pos (12UL) /*!< GIFC3 (Bit 12) */ +#define DMA0_INTC_GIFC3_Msk (0x1000UL) /*!< GIFC3 (Bitfield-Mask: 0x01) */ +#define DMA0_INTC_FTFIFC3_Pos (13UL) /*!< FTFIFC3 (Bit 13) */ +#define DMA0_INTC_FTFIFC3_Msk (0x2000UL) /*!< FTFIFC3 (Bitfield-Mask: 0x01) */ +#define DMA0_INTC_HTFIFC3_Pos (14UL) /*!< HTFIFC3 (Bit 14) */ +#define DMA0_INTC_HTFIFC3_Msk (0x4000UL) /*!< HTFIFC3 (Bitfield-Mask: 0x01) */ +#define DMA0_INTC_ERRIFC3_Pos (15UL) /*!< ERRIFC3 (Bit 15) */ +#define DMA0_INTC_ERRIFC3_Msk (0x8000UL) /*!< ERRIFC3 (Bitfield-Mask: 0x01) */ +#define DMA0_INTC_GIFC4_Pos (16UL) /*!< GIFC4 (Bit 16) */ +#define DMA0_INTC_GIFC4_Msk (0x10000UL) /*!< GIFC4 (Bitfield-Mask: 0x01) */ +#define DMA0_INTC_FTFIFC4_Pos (17UL) /*!< FTFIFC4 (Bit 17) */ +#define DMA0_INTC_FTFIFC4_Msk (0x20000UL) /*!< FTFIFC4 (Bitfield-Mask: 0x01) */ +#define DMA0_INTC_HTFIFC4_Pos (18UL) /*!< HTFIFC4 (Bit 18) */ +#define DMA0_INTC_HTFIFC4_Msk (0x40000UL) /*!< HTFIFC4 (Bitfield-Mask: 0x01) */ +#define DMA0_INTC_ERRIFC4_Pos (19UL) /*!< ERRIFC4 (Bit 19) */ +#define DMA0_INTC_ERRIFC4_Msk (0x80000UL) /*!< ERRIFC4 (Bitfield-Mask: 0x01) */ +#define DMA0_INTC_GIFC5_Pos (20UL) /*!< GIFC5 (Bit 20) */ +#define DMA0_INTC_GIFC5_Msk (0x100000UL) /*!< GIFC5 (Bitfield-Mask: 0x01) */ +#define DMA0_INTC_FTFIFC5_Pos (21UL) /*!< FTFIFC5 (Bit 21) */ +#define DMA0_INTC_FTFIFC5_Msk (0x200000UL) /*!< FTFIFC5 (Bitfield-Mask: 0x01) */ +#define DMA0_INTC_HTFIFC5_Pos (22UL) /*!< HTFIFC5 (Bit 22) */ +#define DMA0_INTC_HTFIFC5_Msk (0x400000UL) /*!< HTFIFC5 (Bitfield-Mask: 0x01) */ +#define DMA0_INTC_ERRIFC5_Pos (23UL) /*!< ERRIFC5 (Bit 23) */ +#define DMA0_INTC_ERRIFC5_Msk (0x800000UL) /*!< ERRIFC5 (Bitfield-Mask: 0x01) */ +#define DMA0_INTC_GIFC6_Pos (24UL) /*!< GIFC6 (Bit 24) */ +#define DMA0_INTC_GIFC6_Msk (0x1000000UL) /*!< GIFC6 (Bitfield-Mask: 0x01) */ +#define DMA0_INTC_FTFIFC6_Pos (25UL) /*!< FTFIFC6 (Bit 25) */ +#define DMA0_INTC_FTFIFC6_Msk (0x2000000UL) /*!< FTFIFC6 (Bitfield-Mask: 0x01) */ +#define DMA0_INTC_HTFIFC6_Pos (26UL) /*!< HTFIFC6 (Bit 26) */ +#define DMA0_INTC_HTFIFC6_Msk (0x4000000UL) /*!< HTFIFC6 (Bitfield-Mask: 0x01) */ +#define DMA0_INTC_ERRIFC6_Pos (27UL) /*!< ERRIFC6 (Bit 27) */ +#define DMA0_INTC_ERRIFC6_Msk (0x8000000UL) /*!< ERRIFC6 (Bitfield-Mask: 0x01) */ +/* ======================================================== CH0CTL ========================================================= */ +#define DMA0_CH0CTL_CHEN_Pos (0UL) /*!< CHEN (Bit 0) */ +#define DMA0_CH0CTL_CHEN_Msk (0x1UL) /*!< CHEN (Bitfield-Mask: 0x01) */ +#define DMA0_CH0CTL_FTFIE_Pos (1UL) /*!< FTFIE (Bit 1) */ +#define DMA0_CH0CTL_FTFIE_Msk (0x2UL) /*!< FTFIE (Bitfield-Mask: 0x01) */ +#define DMA0_CH0CTL_HTFIE_Pos (2UL) /*!< HTFIE (Bit 2) */ +#define DMA0_CH0CTL_HTFIE_Msk (0x4UL) /*!< HTFIE (Bitfield-Mask: 0x01) */ +#define DMA0_CH0CTL_ERRIE_Pos (3UL) /*!< ERRIE (Bit 3) */ +#define DMA0_CH0CTL_ERRIE_Msk (0x8UL) /*!< ERRIE (Bitfield-Mask: 0x01) */ +#define DMA0_CH0CTL_DIR_Pos (4UL) /*!< DIR (Bit 4) */ +#define DMA0_CH0CTL_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +#define DMA0_CH0CTL_CMEN_Pos (5UL) /*!< CMEN (Bit 5) */ +#define DMA0_CH0CTL_CMEN_Msk (0x20UL) /*!< CMEN (Bitfield-Mask: 0x01) */ +#define DMA0_CH0CTL_PNAGA_Pos (6UL) /*!< PNAGA (Bit 6) */ +#define DMA0_CH0CTL_PNAGA_Msk (0x40UL) /*!< PNAGA (Bitfield-Mask: 0x01) */ +#define DMA0_CH0CTL_MNAGA_Pos (7UL) /*!< MNAGA (Bit 7) */ +#define DMA0_CH0CTL_MNAGA_Msk (0x80UL) /*!< MNAGA (Bitfield-Mask: 0x01) */ +#define DMA0_CH0CTL_PWIDTH_Pos (8UL) /*!< PWIDTH (Bit 8) */ +#define DMA0_CH0CTL_PWIDTH_Msk (0x300UL) /*!< PWIDTH (Bitfield-Mask: 0x03) */ +#define DMA0_CH0CTL_MWIDTH_Pos (10UL) /*!< MWIDTH (Bit 10) */ +#define DMA0_CH0CTL_MWIDTH_Msk (0xc00UL) /*!< MWIDTH (Bitfield-Mask: 0x03) */ +#define DMA0_CH0CTL_PRIO_Pos (12UL) /*!< PRIO (Bit 12) */ +#define DMA0_CH0CTL_PRIO_Msk (0x3000UL) /*!< PRIO (Bitfield-Mask: 0x03) */ +#define DMA0_CH0CTL_M2M_Pos (14UL) /*!< M2M (Bit 14) */ +#define DMA0_CH0CTL_M2M_Msk (0x4000UL) /*!< M2M (Bitfield-Mask: 0x01) */ +/* ======================================================== CH0CNT ========================================================= */ +#define DMA0_CH0CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA0_CH0CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= CH0PADDR ======================================================== */ +#define DMA0_CH0PADDR_PADDR_Pos (0UL) /*!< PADDR (Bit 0) */ +#define DMA0_CH0PADDR_PADDR_Msk (0xffffffffUL) /*!< PADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CH0MADDR ======================================================== */ +#define DMA0_CH0MADDR_MADDR_Pos (0UL) /*!< MADDR (Bit 0) */ +#define DMA0_CH0MADDR_MADDR_Msk (0xffffffffUL) /*!< MADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CH1CTL ========================================================= */ +#define DMA0_CH1CTL_CHEN_Pos (0UL) /*!< CHEN (Bit 0) */ +#define DMA0_CH1CTL_CHEN_Msk (0x1UL) /*!< CHEN (Bitfield-Mask: 0x01) */ +#define DMA0_CH1CTL_FTFIE_Pos (1UL) /*!< FTFIE (Bit 1) */ +#define DMA0_CH1CTL_FTFIE_Msk (0x2UL) /*!< FTFIE (Bitfield-Mask: 0x01) */ +#define DMA0_CH1CTL_HTFIE_Pos (2UL) /*!< HTFIE (Bit 2) */ +#define DMA0_CH1CTL_HTFIE_Msk (0x4UL) /*!< HTFIE (Bitfield-Mask: 0x01) */ +#define DMA0_CH1CTL_ERRIE_Pos (3UL) /*!< ERRIE (Bit 3) */ +#define DMA0_CH1CTL_ERRIE_Msk (0x8UL) /*!< ERRIE (Bitfield-Mask: 0x01) */ +#define DMA0_CH1CTL_DIR_Pos (4UL) /*!< DIR (Bit 4) */ +#define DMA0_CH1CTL_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +#define DMA0_CH1CTL_CMEN_Pos (5UL) /*!< CMEN (Bit 5) */ +#define DMA0_CH1CTL_CMEN_Msk (0x20UL) /*!< CMEN (Bitfield-Mask: 0x01) */ +#define DMA0_CH1CTL_PNAGA_Pos (6UL) /*!< PNAGA (Bit 6) */ +#define DMA0_CH1CTL_PNAGA_Msk (0x40UL) /*!< PNAGA (Bitfield-Mask: 0x01) */ +#define DMA0_CH1CTL_MNAGA_Pos (7UL) /*!< MNAGA (Bit 7) */ +#define DMA0_CH1CTL_MNAGA_Msk (0x80UL) /*!< MNAGA (Bitfield-Mask: 0x01) */ +#define DMA0_CH1CTL_PWIDTH_Pos (8UL) /*!< PWIDTH (Bit 8) */ +#define DMA0_CH1CTL_PWIDTH_Msk (0x300UL) /*!< PWIDTH (Bitfield-Mask: 0x03) */ +#define DMA0_CH1CTL_MWIDTH_Pos (10UL) /*!< MWIDTH (Bit 10) */ +#define DMA0_CH1CTL_MWIDTH_Msk (0xc00UL) /*!< MWIDTH (Bitfield-Mask: 0x03) */ +#define DMA0_CH1CTL_PRIO_Pos (12UL) /*!< PRIO (Bit 12) */ +#define DMA0_CH1CTL_PRIO_Msk (0x3000UL) /*!< PRIO (Bitfield-Mask: 0x03) */ +#define DMA0_CH1CTL_M2M_Pos (14UL) /*!< M2M (Bit 14) */ +#define DMA0_CH1CTL_M2M_Msk (0x4000UL) /*!< M2M (Bitfield-Mask: 0x01) */ +/* ======================================================== CH1CNT ========================================================= */ +#define DMA0_CH1CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA0_CH1CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= CH1PADDR ======================================================== */ +#define DMA0_CH1PADDR_PADDR_Pos (0UL) /*!< PADDR (Bit 0) */ +#define DMA0_CH1PADDR_PADDR_Msk (0xffffffffUL) /*!< PADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CH1MADDR ======================================================== */ +#define DMA0_CH1MADDR_MADDR_Pos (0UL) /*!< MADDR (Bit 0) */ +#define DMA0_CH1MADDR_MADDR_Msk (0xffffffffUL) /*!< MADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CH2CTL ========================================================= */ +#define DMA0_CH2CTL_CHEN_Pos (0UL) /*!< CHEN (Bit 0) */ +#define DMA0_CH2CTL_CHEN_Msk (0x1UL) /*!< CHEN (Bitfield-Mask: 0x01) */ +#define DMA0_CH2CTL_FTFIE_Pos (1UL) /*!< FTFIE (Bit 1) */ +#define DMA0_CH2CTL_FTFIE_Msk (0x2UL) /*!< FTFIE (Bitfield-Mask: 0x01) */ +#define DMA0_CH2CTL_HTFIE_Pos (2UL) /*!< HTFIE (Bit 2) */ +#define DMA0_CH2CTL_HTFIE_Msk (0x4UL) /*!< HTFIE (Bitfield-Mask: 0x01) */ +#define DMA0_CH2CTL_ERRIE_Pos (3UL) /*!< ERRIE (Bit 3) */ +#define DMA0_CH2CTL_ERRIE_Msk (0x8UL) /*!< ERRIE (Bitfield-Mask: 0x01) */ +#define DMA0_CH2CTL_DIR_Pos (4UL) /*!< DIR (Bit 4) */ +#define DMA0_CH2CTL_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +#define DMA0_CH2CTL_CMEN_Pos (5UL) /*!< CMEN (Bit 5) */ +#define DMA0_CH2CTL_CMEN_Msk (0x20UL) /*!< CMEN (Bitfield-Mask: 0x01) */ +#define DMA0_CH2CTL_PNAGA_Pos (6UL) /*!< PNAGA (Bit 6) */ +#define DMA0_CH2CTL_PNAGA_Msk (0x40UL) /*!< PNAGA (Bitfield-Mask: 0x01) */ +#define DMA0_CH2CTL_MNAGA_Pos (7UL) /*!< MNAGA (Bit 7) */ +#define DMA0_CH2CTL_MNAGA_Msk (0x80UL) /*!< MNAGA (Bitfield-Mask: 0x01) */ +#define DMA0_CH2CTL_PWIDTH_Pos (8UL) /*!< PWIDTH (Bit 8) */ +#define DMA0_CH2CTL_PWIDTH_Msk (0x300UL) /*!< PWIDTH (Bitfield-Mask: 0x03) */ +#define DMA0_CH2CTL_MWIDTH_Pos (10UL) /*!< MWIDTH (Bit 10) */ +#define DMA0_CH2CTL_MWIDTH_Msk (0xc00UL) /*!< MWIDTH (Bitfield-Mask: 0x03) */ +#define DMA0_CH2CTL_PRIO_Pos (12UL) /*!< PRIO (Bit 12) */ +#define DMA0_CH2CTL_PRIO_Msk (0x3000UL) /*!< PRIO (Bitfield-Mask: 0x03) */ +#define DMA0_CH2CTL_M2M_Pos (14UL) /*!< M2M (Bit 14) */ +#define DMA0_CH2CTL_M2M_Msk (0x4000UL) /*!< M2M (Bitfield-Mask: 0x01) */ +/* ======================================================== CH2CNT ========================================================= */ +#define DMA0_CH2CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA0_CH2CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= CH2PADDR ======================================================== */ +#define DMA0_CH2PADDR_PADDR_Pos (0UL) /*!< PADDR (Bit 0) */ +#define DMA0_CH2PADDR_PADDR_Msk (0xffffffffUL) /*!< PADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CH2MADDR ======================================================== */ +#define DMA0_CH2MADDR_MADDR_Pos (0UL) /*!< MADDR (Bit 0) */ +#define DMA0_CH2MADDR_MADDR_Msk (0xffffffffUL) /*!< MADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CH3CTL ========================================================= */ +#define DMA0_CH3CTL_CHEN_Pos (0UL) /*!< CHEN (Bit 0) */ +#define DMA0_CH3CTL_CHEN_Msk (0x1UL) /*!< CHEN (Bitfield-Mask: 0x01) */ +#define DMA0_CH3CTL_FTFIE_Pos (1UL) /*!< FTFIE (Bit 1) */ +#define DMA0_CH3CTL_FTFIE_Msk (0x2UL) /*!< FTFIE (Bitfield-Mask: 0x01) */ +#define DMA0_CH3CTL_HTFIE_Pos (2UL) /*!< HTFIE (Bit 2) */ +#define DMA0_CH3CTL_HTFIE_Msk (0x4UL) /*!< HTFIE (Bitfield-Mask: 0x01) */ +#define DMA0_CH3CTL_ERRIE_Pos (3UL) /*!< ERRIE (Bit 3) */ +#define DMA0_CH3CTL_ERRIE_Msk (0x8UL) /*!< ERRIE (Bitfield-Mask: 0x01) */ +#define DMA0_CH3CTL_DIR_Pos (4UL) /*!< DIR (Bit 4) */ +#define DMA0_CH3CTL_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +#define DMA0_CH3CTL_CMEN_Pos (5UL) /*!< CMEN (Bit 5) */ +#define DMA0_CH3CTL_CMEN_Msk (0x20UL) /*!< CMEN (Bitfield-Mask: 0x01) */ +#define DMA0_CH3CTL_PNAGA_Pos (6UL) /*!< PNAGA (Bit 6) */ +#define DMA0_CH3CTL_PNAGA_Msk (0x40UL) /*!< PNAGA (Bitfield-Mask: 0x01) */ +#define DMA0_CH3CTL_MNAGA_Pos (7UL) /*!< MNAGA (Bit 7) */ +#define DMA0_CH3CTL_MNAGA_Msk (0x80UL) /*!< MNAGA (Bitfield-Mask: 0x01) */ +#define DMA0_CH3CTL_PWIDTH_Pos (8UL) /*!< PWIDTH (Bit 8) */ +#define DMA0_CH3CTL_PWIDTH_Msk (0x300UL) /*!< PWIDTH (Bitfield-Mask: 0x03) */ +#define DMA0_CH3CTL_MWIDTH_Pos (10UL) /*!< MWIDTH (Bit 10) */ +#define DMA0_CH3CTL_MWIDTH_Msk (0xc00UL) /*!< MWIDTH (Bitfield-Mask: 0x03) */ +#define DMA0_CH3CTL_PRIO_Pos (12UL) /*!< PRIO (Bit 12) */ +#define DMA0_CH3CTL_PRIO_Msk (0x3000UL) /*!< PRIO (Bitfield-Mask: 0x03) */ +#define DMA0_CH3CTL_M2M_Pos (14UL) /*!< M2M (Bit 14) */ +#define DMA0_CH3CTL_M2M_Msk (0x4000UL) /*!< M2M (Bitfield-Mask: 0x01) */ +/* ======================================================== CH3CNT ========================================================= */ +#define DMA0_CH3CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA0_CH3CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= CH3PADDR ======================================================== */ +#define DMA0_CH3PADDR_PADDR_Pos (0UL) /*!< PADDR (Bit 0) */ +#define DMA0_CH3PADDR_PADDR_Msk (0xffffffffUL) /*!< PADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CH3MADDR ======================================================== */ +#define DMA0_CH3MADDR_MADDR_Pos (0UL) /*!< MADDR (Bit 0) */ +#define DMA0_CH3MADDR_MADDR_Msk (0xffffffffUL) /*!< MADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CH4CTL ========================================================= */ +#define DMA0_CH4CTL_CHEN_Pos (0UL) /*!< CHEN (Bit 0) */ +#define DMA0_CH4CTL_CHEN_Msk (0x1UL) /*!< CHEN (Bitfield-Mask: 0x01) */ +#define DMA0_CH4CTL_FTFIE_Pos (1UL) /*!< FTFIE (Bit 1) */ +#define DMA0_CH4CTL_FTFIE_Msk (0x2UL) /*!< FTFIE (Bitfield-Mask: 0x01) */ +#define DMA0_CH4CTL_HTFIE_Pos (2UL) /*!< HTFIE (Bit 2) */ +#define DMA0_CH4CTL_HTFIE_Msk (0x4UL) /*!< HTFIE (Bitfield-Mask: 0x01) */ +#define DMA0_CH4CTL_ERRIE_Pos (3UL) /*!< ERRIE (Bit 3) */ +#define DMA0_CH4CTL_ERRIE_Msk (0x8UL) /*!< ERRIE (Bitfield-Mask: 0x01) */ +#define DMA0_CH4CTL_DIR_Pos (4UL) /*!< DIR (Bit 4) */ +#define DMA0_CH4CTL_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +#define DMA0_CH4CTL_CMEN_Pos (5UL) /*!< CMEN (Bit 5) */ +#define DMA0_CH4CTL_CMEN_Msk (0x20UL) /*!< CMEN (Bitfield-Mask: 0x01) */ +#define DMA0_CH4CTL_PNAGA_Pos (6UL) /*!< PNAGA (Bit 6) */ +#define DMA0_CH4CTL_PNAGA_Msk (0x40UL) /*!< PNAGA (Bitfield-Mask: 0x01) */ +#define DMA0_CH4CTL_MNAGA_Pos (7UL) /*!< MNAGA (Bit 7) */ +#define DMA0_CH4CTL_MNAGA_Msk (0x80UL) /*!< MNAGA (Bitfield-Mask: 0x01) */ +#define DMA0_CH4CTL_PWIDTH_Pos (8UL) /*!< PWIDTH (Bit 8) */ +#define DMA0_CH4CTL_PWIDTH_Msk (0x300UL) /*!< PWIDTH (Bitfield-Mask: 0x03) */ +#define DMA0_CH4CTL_MWIDTH_Pos (10UL) /*!< MWIDTH (Bit 10) */ +#define DMA0_CH4CTL_MWIDTH_Msk (0xc00UL) /*!< MWIDTH (Bitfield-Mask: 0x03) */ +#define DMA0_CH4CTL_PRIO_Pos (12UL) /*!< PRIO (Bit 12) */ +#define DMA0_CH4CTL_PRIO_Msk (0x3000UL) /*!< PRIO (Bitfield-Mask: 0x03) */ +#define DMA0_CH4CTL_M2M_Pos (14UL) /*!< M2M (Bit 14) */ +#define DMA0_CH4CTL_M2M_Msk (0x4000UL) /*!< M2M (Bitfield-Mask: 0x01) */ +/* ======================================================== CH4CNT ========================================================= */ +#define DMA0_CH4CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA0_CH4CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= CH4PADDR ======================================================== */ +#define DMA0_CH4PADDR_PADDR_Pos (0UL) /*!< PADDR (Bit 0) */ +#define DMA0_CH4PADDR_PADDR_Msk (0xffffffffUL) /*!< PADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CH4MADDR ======================================================== */ +#define DMA0_CH4MADDR_MADDR_Pos (0UL) /*!< MADDR (Bit 0) */ +#define DMA0_CH4MADDR_MADDR_Msk (0xffffffffUL) /*!< MADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CH5CTL ========================================================= */ +#define DMA0_CH5CTL_CHEN_Pos (0UL) /*!< CHEN (Bit 0) */ +#define DMA0_CH5CTL_CHEN_Msk (0x1UL) /*!< CHEN (Bitfield-Mask: 0x01) */ +#define DMA0_CH5CTL_FTFIE_Pos (1UL) /*!< FTFIE (Bit 1) */ +#define DMA0_CH5CTL_FTFIE_Msk (0x2UL) /*!< FTFIE (Bitfield-Mask: 0x01) */ +#define DMA0_CH5CTL_HTFIE_Pos (2UL) /*!< HTFIE (Bit 2) */ +#define DMA0_CH5CTL_HTFIE_Msk (0x4UL) /*!< HTFIE (Bitfield-Mask: 0x01) */ +#define DMA0_CH5CTL_ERRIE_Pos (3UL) /*!< ERRIE (Bit 3) */ +#define DMA0_CH5CTL_ERRIE_Msk (0x8UL) /*!< ERRIE (Bitfield-Mask: 0x01) */ +#define DMA0_CH5CTL_DIR_Pos (4UL) /*!< DIR (Bit 4) */ +#define DMA0_CH5CTL_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +#define DMA0_CH5CTL_CMEN_Pos (5UL) /*!< CMEN (Bit 5) */ +#define DMA0_CH5CTL_CMEN_Msk (0x20UL) /*!< CMEN (Bitfield-Mask: 0x01) */ +#define DMA0_CH5CTL_PNAGA_Pos (6UL) /*!< PNAGA (Bit 6) */ +#define DMA0_CH5CTL_PNAGA_Msk (0x40UL) /*!< PNAGA (Bitfield-Mask: 0x01) */ +#define DMA0_CH5CTL_MNAGA_Pos (7UL) /*!< MNAGA (Bit 7) */ +#define DMA0_CH5CTL_MNAGA_Msk (0x80UL) /*!< MNAGA (Bitfield-Mask: 0x01) */ +#define DMA0_CH5CTL_PWIDTH_Pos (8UL) /*!< PWIDTH (Bit 8) */ +#define DMA0_CH5CTL_PWIDTH_Msk (0x300UL) /*!< PWIDTH (Bitfield-Mask: 0x03) */ +#define DMA0_CH5CTL_MWIDTH_Pos (10UL) /*!< MWIDTH (Bit 10) */ +#define DMA0_CH5CTL_MWIDTH_Msk (0xc00UL) /*!< MWIDTH (Bitfield-Mask: 0x03) */ +#define DMA0_CH5CTL_PRIO_Pos (12UL) /*!< PRIO (Bit 12) */ +#define DMA0_CH5CTL_PRIO_Msk (0x3000UL) /*!< PRIO (Bitfield-Mask: 0x03) */ +#define DMA0_CH5CTL_M2M_Pos (14UL) /*!< M2M (Bit 14) */ +#define DMA0_CH5CTL_M2M_Msk (0x4000UL) /*!< M2M (Bitfield-Mask: 0x01) */ +/* ======================================================== CH5CNT ========================================================= */ +#define DMA0_CH5CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA0_CH5CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= CH5PADDR ======================================================== */ +#define DMA0_CH5PADDR_PADDR_Pos (0UL) /*!< PADDR (Bit 0) */ +#define DMA0_CH5PADDR_PADDR_Msk (0xffffffffUL) /*!< PADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CH5MADDR ======================================================== */ +#define DMA0_CH5MADDR_MADDR_Pos (0UL) /*!< MADDR (Bit 0) */ +#define DMA0_CH5MADDR_MADDR_Msk (0xffffffffUL) /*!< MADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CH6CTL ========================================================= */ +#define DMA0_CH6CTL_CHEN_Pos (0UL) /*!< CHEN (Bit 0) */ +#define DMA0_CH6CTL_CHEN_Msk (0x1UL) /*!< CHEN (Bitfield-Mask: 0x01) */ +#define DMA0_CH6CTL_FTFIE_Pos (1UL) /*!< FTFIE (Bit 1) */ +#define DMA0_CH6CTL_FTFIE_Msk (0x2UL) /*!< FTFIE (Bitfield-Mask: 0x01) */ +#define DMA0_CH6CTL_HTFIE_Pos (2UL) /*!< HTFIE (Bit 2) */ +#define DMA0_CH6CTL_HTFIE_Msk (0x4UL) /*!< HTFIE (Bitfield-Mask: 0x01) */ +#define DMA0_CH6CTL_ERRIE_Pos (3UL) /*!< ERRIE (Bit 3) */ +#define DMA0_CH6CTL_ERRIE_Msk (0x8UL) /*!< ERRIE (Bitfield-Mask: 0x01) */ +#define DMA0_CH6CTL_DIR_Pos (4UL) /*!< DIR (Bit 4) */ +#define DMA0_CH6CTL_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +#define DMA0_CH6CTL_CMEN_Pos (5UL) /*!< CMEN (Bit 5) */ +#define DMA0_CH6CTL_CMEN_Msk (0x20UL) /*!< CMEN (Bitfield-Mask: 0x01) */ +#define DMA0_CH6CTL_PNAGA_Pos (6UL) /*!< PNAGA (Bit 6) */ +#define DMA0_CH6CTL_PNAGA_Msk (0x40UL) /*!< PNAGA (Bitfield-Mask: 0x01) */ +#define DMA0_CH6CTL_MNAGA_Pos (7UL) /*!< MNAGA (Bit 7) */ +#define DMA0_CH6CTL_MNAGA_Msk (0x80UL) /*!< MNAGA (Bitfield-Mask: 0x01) */ +#define DMA0_CH6CTL_PWIDTH_Pos (8UL) /*!< PWIDTH (Bit 8) */ +#define DMA0_CH6CTL_PWIDTH_Msk (0x300UL) /*!< PWIDTH (Bitfield-Mask: 0x03) */ +#define DMA0_CH6CTL_MWIDTH_Pos (10UL) /*!< MWIDTH (Bit 10) */ +#define DMA0_CH6CTL_MWIDTH_Msk (0xc00UL) /*!< MWIDTH (Bitfield-Mask: 0x03) */ +#define DMA0_CH6CTL_PRIO_Pos (12UL) /*!< PRIO (Bit 12) */ +#define DMA0_CH6CTL_PRIO_Msk (0x3000UL) /*!< PRIO (Bitfield-Mask: 0x03) */ +#define DMA0_CH6CTL_M2M_Pos (14UL) /*!< M2M (Bit 14) */ +#define DMA0_CH6CTL_M2M_Msk (0x4000UL) /*!< M2M (Bitfield-Mask: 0x01) */ +/* ======================================================== CH6CNT ========================================================= */ +#define DMA0_CH6CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA0_CH6CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= CH6PADDR ======================================================== */ +#define DMA0_CH6PADDR_PADDR_Pos (0UL) /*!< PADDR (Bit 0) */ +#define DMA0_CH6PADDR_PADDR_Msk (0xffffffffUL) /*!< PADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CH6MADDR ======================================================== */ +#define DMA0_CH6MADDR_MADDR_Pos (0UL) /*!< MADDR (Bit 0) */ +#define DMA0_CH6MADDR_MADDR_Msk (0xffffffffUL) /*!< MADDR (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ DMA1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= INTF ========================================================== */ +#define DMA1_INTF_GIF0_Pos (0UL) /*!< GIF0 (Bit 0) */ +#define DMA1_INTF_GIF0_Msk (0x1UL) /*!< GIF0 (Bitfield-Mask: 0x01) */ +#define DMA1_INTF_FTFIF0_Pos (1UL) /*!< FTFIF0 (Bit 1) */ +#define DMA1_INTF_FTFIF0_Msk (0x2UL) /*!< FTFIF0 (Bitfield-Mask: 0x01) */ +#define DMA1_INTF_HTFIF0_Pos (2UL) /*!< HTFIF0 (Bit 2) */ +#define DMA1_INTF_HTFIF0_Msk (0x4UL) /*!< HTFIF0 (Bitfield-Mask: 0x01) */ +#define DMA1_INTF_ERRIF0_Pos (3UL) /*!< ERRIF0 (Bit 3) */ +#define DMA1_INTF_ERRIF0_Msk (0x8UL) /*!< ERRIF0 (Bitfield-Mask: 0x01) */ +#define DMA1_INTF_GIF1_Pos (4UL) /*!< GIF1 (Bit 4) */ +#define DMA1_INTF_GIF1_Msk (0x10UL) /*!< GIF1 (Bitfield-Mask: 0x01) */ +#define DMA1_INTF_FTFIF1_Pos (5UL) /*!< FTFIF1 (Bit 5) */ +#define DMA1_INTF_FTFIF1_Msk (0x20UL) /*!< FTFIF1 (Bitfield-Mask: 0x01) */ +#define DMA1_INTF_HTFIF1_Pos (6UL) /*!< HTFIF1 (Bit 6) */ +#define DMA1_INTF_HTFIF1_Msk (0x40UL) /*!< HTFIF1 (Bitfield-Mask: 0x01) */ +#define DMA1_INTF_ERRIF1_Pos (7UL) /*!< ERRIF1 (Bit 7) */ +#define DMA1_INTF_ERRIF1_Msk (0x80UL) /*!< ERRIF1 (Bitfield-Mask: 0x01) */ +#define DMA1_INTF_GIF2_Pos (8UL) /*!< GIF2 (Bit 8) */ +#define DMA1_INTF_GIF2_Msk (0x100UL) /*!< GIF2 (Bitfield-Mask: 0x01) */ +#define DMA1_INTF_FTFIF2_Pos (9UL) /*!< FTFIF2 (Bit 9) */ +#define DMA1_INTF_FTFIF2_Msk (0x200UL) /*!< FTFIF2 (Bitfield-Mask: 0x01) */ +#define DMA1_INTF_HTFIF2_Pos (10UL) /*!< HTFIF2 (Bit 10) */ +#define DMA1_INTF_HTFIF2_Msk (0x400UL) /*!< HTFIF2 (Bitfield-Mask: 0x01) */ +#define DMA1_INTF_ERRIF2_Pos (11UL) /*!< ERRIF2 (Bit 11) */ +#define DMA1_INTF_ERRIF2_Msk (0x800UL) /*!< ERRIF2 (Bitfield-Mask: 0x01) */ +#define DMA1_INTF_GIF3_Pos (12UL) /*!< GIF3 (Bit 12) */ +#define DMA1_INTF_GIF3_Msk (0x1000UL) /*!< GIF3 (Bitfield-Mask: 0x01) */ +#define DMA1_INTF_FTFIF3_Pos (13UL) /*!< FTFIF3 (Bit 13) */ +#define DMA1_INTF_FTFIF3_Msk (0x2000UL) /*!< FTFIF3 (Bitfield-Mask: 0x01) */ +#define DMA1_INTF_HTFIF3_Pos (14UL) /*!< HTFIF3 (Bit 14) */ +#define DMA1_INTF_HTFIF3_Msk (0x4000UL) /*!< HTFIF3 (Bitfield-Mask: 0x01) */ +#define DMA1_INTF_ERRIF3_Pos (15UL) /*!< ERRIF3 (Bit 15) */ +#define DMA1_INTF_ERRIF3_Msk (0x8000UL) /*!< ERRIF3 (Bitfield-Mask: 0x01) */ +#define DMA1_INTF_GIF4_Pos (16UL) /*!< GIF4 (Bit 16) */ +#define DMA1_INTF_GIF4_Msk (0x10000UL) /*!< GIF4 (Bitfield-Mask: 0x01) */ +#define DMA1_INTF_FTFIF4_Pos (17UL) /*!< FTFIF4 (Bit 17) */ +#define DMA1_INTF_FTFIF4_Msk (0x20000UL) /*!< FTFIF4 (Bitfield-Mask: 0x01) */ +#define DMA1_INTF_HTFIF4_Pos (18UL) /*!< HTFIF4 (Bit 18) */ +#define DMA1_INTF_HTFIF4_Msk (0x40000UL) /*!< HTFIF4 (Bitfield-Mask: 0x01) */ +#define DMA1_INTF_ERRIF4_Pos (19UL) /*!< ERRIF4 (Bit 19) */ +#define DMA1_INTF_ERRIF4_Msk (0x80000UL) /*!< ERRIF4 (Bitfield-Mask: 0x01) */ +/* ========================================================= INTC ========================================================== */ +#define DMA1_INTC_GIFC0_Pos (0UL) /*!< GIFC0 (Bit 0) */ +#define DMA1_INTC_GIFC0_Msk (0x1UL) /*!< GIFC0 (Bitfield-Mask: 0x01) */ +#define DMA1_INTC_FTFIFC0_Pos (1UL) /*!< FTFIFC0 (Bit 1) */ +#define DMA1_INTC_FTFIFC0_Msk (0x2UL) /*!< FTFIFC0 (Bitfield-Mask: 0x01) */ +#define DMA1_INTC_HTFIFC0_Pos (2UL) /*!< HTFIFC0 (Bit 2) */ +#define DMA1_INTC_HTFIFC0_Msk (0x4UL) /*!< HTFIFC0 (Bitfield-Mask: 0x01) */ +#define DMA1_INTC_ERRIFC0_Pos (3UL) /*!< ERRIFC0 (Bit 3) */ +#define DMA1_INTC_ERRIFC0_Msk (0x8UL) /*!< ERRIFC0 (Bitfield-Mask: 0x01) */ +#define DMA1_INTC_GIFC1_Pos (4UL) /*!< GIFC1 (Bit 4) */ +#define DMA1_INTC_GIFC1_Msk (0x10UL) /*!< GIFC1 (Bitfield-Mask: 0x01) */ +#define DMA1_INTC_FTFIFC1_Pos (5UL) /*!< FTFIFC1 (Bit 5) */ +#define DMA1_INTC_FTFIFC1_Msk (0x20UL) /*!< FTFIFC1 (Bitfield-Mask: 0x01) */ +#define DMA1_INTC_HTFIFC1_Pos (6UL) /*!< HTFIFC1 (Bit 6) */ +#define DMA1_INTC_HTFIFC1_Msk (0x40UL) /*!< HTFIFC1 (Bitfield-Mask: 0x01) */ +#define DMA1_INTC_ERRIFC1_Pos (7UL) /*!< ERRIFC1 (Bit 7) */ +#define DMA1_INTC_ERRIFC1_Msk (0x80UL) /*!< ERRIFC1 (Bitfield-Mask: 0x01) */ +#define DMA1_INTC_GIFC2_Pos (8UL) /*!< GIFC2 (Bit 8) */ +#define DMA1_INTC_GIFC2_Msk (0x100UL) /*!< GIFC2 (Bitfield-Mask: 0x01) */ +#define DMA1_INTC_FTFIFC2_Pos (9UL) /*!< FTFIFC2 (Bit 9) */ +#define DMA1_INTC_FTFIFC2_Msk (0x200UL) /*!< FTFIFC2 (Bitfield-Mask: 0x01) */ +#define DMA1_INTC_HTFIFC2_Pos (10UL) /*!< HTFIFC2 (Bit 10) */ +#define DMA1_INTC_HTFIFC2_Msk (0x400UL) /*!< HTFIFC2 (Bitfield-Mask: 0x01) */ +#define DMA1_INTC_ERRIFC2_Pos (11UL) /*!< ERRIFC2 (Bit 11) */ +#define DMA1_INTC_ERRIFC2_Msk (0x800UL) /*!< ERRIFC2 (Bitfield-Mask: 0x01) */ +#define DMA1_INTC_GIFC3_Pos (12UL) /*!< GIFC3 (Bit 12) */ +#define DMA1_INTC_GIFC3_Msk (0x1000UL) /*!< GIFC3 (Bitfield-Mask: 0x01) */ +#define DMA1_INTC_FTFIFC3_Pos (13UL) /*!< FTFIFC3 (Bit 13) */ +#define DMA1_INTC_FTFIFC3_Msk (0x2000UL) /*!< FTFIFC3 (Bitfield-Mask: 0x01) */ +#define DMA1_INTC_HTFIFC3_Pos (14UL) /*!< HTFIFC3 (Bit 14) */ +#define DMA1_INTC_HTFIFC3_Msk (0x4000UL) /*!< HTFIFC3 (Bitfield-Mask: 0x01) */ +#define DMA1_INTC_ERRIFC3_Pos (15UL) /*!< ERRIFC3 (Bit 15) */ +#define DMA1_INTC_ERRIFC3_Msk (0x8000UL) /*!< ERRIFC3 (Bitfield-Mask: 0x01) */ +#define DMA1_INTC_GIFC4_Pos (16UL) /*!< GIFC4 (Bit 16) */ +#define DMA1_INTC_GIFC4_Msk (0x10000UL) /*!< GIFC4 (Bitfield-Mask: 0x01) */ +#define DMA1_INTC_FTFIFC4_Pos (17UL) /*!< FTFIFC4 (Bit 17) */ +#define DMA1_INTC_FTFIFC4_Msk (0x20000UL) /*!< FTFIFC4 (Bitfield-Mask: 0x01) */ +#define DMA1_INTC_HTFIFC4_Pos (18UL) /*!< HTFIFC4 (Bit 18) */ +#define DMA1_INTC_HTFIFC4_Msk (0x40000UL) /*!< HTFIFC4 (Bitfield-Mask: 0x01) */ +#define DMA1_INTC_ERRIFC4_Pos (19UL) /*!< ERRIFC4 (Bit 19) */ +#define DMA1_INTC_ERRIFC4_Msk (0x80000UL) /*!< ERRIFC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== CH0CTL ========================================================= */ +#define DMA1_CH0CTL_CHEN_Pos (0UL) /*!< CHEN (Bit 0) */ +#define DMA1_CH0CTL_CHEN_Msk (0x1UL) /*!< CHEN (Bitfield-Mask: 0x01) */ +#define DMA1_CH0CTL_FTFIE_Pos (1UL) /*!< FTFIE (Bit 1) */ +#define DMA1_CH0CTL_FTFIE_Msk (0x2UL) /*!< FTFIE (Bitfield-Mask: 0x01) */ +#define DMA1_CH0CTL_HTFIE_Pos (2UL) /*!< HTFIE (Bit 2) */ +#define DMA1_CH0CTL_HTFIE_Msk (0x4UL) /*!< HTFIE (Bitfield-Mask: 0x01) */ +#define DMA1_CH0CTL_ERRIE_Pos (3UL) /*!< ERRIE (Bit 3) */ +#define DMA1_CH0CTL_ERRIE_Msk (0x8UL) /*!< ERRIE (Bitfield-Mask: 0x01) */ +#define DMA1_CH0CTL_DIR_Pos (4UL) /*!< DIR (Bit 4) */ +#define DMA1_CH0CTL_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +#define DMA1_CH0CTL_CMEN_Pos (5UL) /*!< CMEN (Bit 5) */ +#define DMA1_CH0CTL_CMEN_Msk (0x20UL) /*!< CMEN (Bitfield-Mask: 0x01) */ +#define DMA1_CH0CTL_PNAGA_Pos (6UL) /*!< PNAGA (Bit 6) */ +#define DMA1_CH0CTL_PNAGA_Msk (0x40UL) /*!< PNAGA (Bitfield-Mask: 0x01) */ +#define DMA1_CH0CTL_MNAGA_Pos (7UL) /*!< MNAGA (Bit 7) */ +#define DMA1_CH0CTL_MNAGA_Msk (0x80UL) /*!< MNAGA (Bitfield-Mask: 0x01) */ +#define DMA1_CH0CTL_PWIDTH_Pos (8UL) /*!< PWIDTH (Bit 8) */ +#define DMA1_CH0CTL_PWIDTH_Msk (0x300UL) /*!< PWIDTH (Bitfield-Mask: 0x03) */ +#define DMA1_CH0CTL_MWIDTH_Pos (10UL) /*!< MWIDTH (Bit 10) */ +#define DMA1_CH0CTL_MWIDTH_Msk (0xc00UL) /*!< MWIDTH (Bitfield-Mask: 0x03) */ +#define DMA1_CH0CTL_PRIO_Pos (12UL) /*!< PRIO (Bit 12) */ +#define DMA1_CH0CTL_PRIO_Msk (0x3000UL) /*!< PRIO (Bitfield-Mask: 0x03) */ +#define DMA1_CH0CTL_M2M_Pos (14UL) /*!< M2M (Bit 14) */ +#define DMA1_CH0CTL_M2M_Msk (0x4000UL) /*!< M2M (Bitfield-Mask: 0x01) */ +/* ======================================================== CH0CNT ========================================================= */ +#define DMA1_CH0CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA1_CH0CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= CH0PADDR ======================================================== */ +#define DMA1_CH0PADDR_PADDR_Pos (0UL) /*!< PADDR (Bit 0) */ +#define DMA1_CH0PADDR_PADDR_Msk (0xffffffffUL) /*!< PADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CH0MADDR ======================================================== */ +#define DMA1_CH0MADDR_MADDR_Pos (0UL) /*!< MADDR (Bit 0) */ +#define DMA1_CH0MADDR_MADDR_Msk (0xffffffffUL) /*!< MADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CH1CTL ========================================================= */ +#define DMA1_CH1CTL_CHEN_Pos (0UL) /*!< CHEN (Bit 0) */ +#define DMA1_CH1CTL_CHEN_Msk (0x1UL) /*!< CHEN (Bitfield-Mask: 0x01) */ +#define DMA1_CH1CTL_FTFIE_Pos (1UL) /*!< FTFIE (Bit 1) */ +#define DMA1_CH1CTL_FTFIE_Msk (0x2UL) /*!< FTFIE (Bitfield-Mask: 0x01) */ +#define DMA1_CH1CTL_HTFIE_Pos (2UL) /*!< HTFIE (Bit 2) */ +#define DMA1_CH1CTL_HTFIE_Msk (0x4UL) /*!< HTFIE (Bitfield-Mask: 0x01) */ +#define DMA1_CH1CTL_ERRIE_Pos (3UL) /*!< ERRIE (Bit 3) */ +#define DMA1_CH1CTL_ERRIE_Msk (0x8UL) /*!< ERRIE (Bitfield-Mask: 0x01) */ +#define DMA1_CH1CTL_DIR_Pos (4UL) /*!< DIR (Bit 4) */ +#define DMA1_CH1CTL_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +#define DMA1_CH1CTL_CMEN_Pos (5UL) /*!< CMEN (Bit 5) */ +#define DMA1_CH1CTL_CMEN_Msk (0x20UL) /*!< CMEN (Bitfield-Mask: 0x01) */ +#define DMA1_CH1CTL_PNAGA_Pos (6UL) /*!< PNAGA (Bit 6) */ +#define DMA1_CH1CTL_PNAGA_Msk (0x40UL) /*!< PNAGA (Bitfield-Mask: 0x01) */ +#define DMA1_CH1CTL_MNAGA_Pos (7UL) /*!< MNAGA (Bit 7) */ +#define DMA1_CH1CTL_MNAGA_Msk (0x80UL) /*!< MNAGA (Bitfield-Mask: 0x01) */ +#define DMA1_CH1CTL_PWIDTH_Pos (8UL) /*!< PWIDTH (Bit 8) */ +#define DMA1_CH1CTL_PWIDTH_Msk (0x300UL) /*!< PWIDTH (Bitfield-Mask: 0x03) */ +#define DMA1_CH1CTL_MWIDTH_Pos (10UL) /*!< MWIDTH (Bit 10) */ +#define DMA1_CH1CTL_MWIDTH_Msk (0xc00UL) /*!< MWIDTH (Bitfield-Mask: 0x03) */ +#define DMA1_CH1CTL_PRIO_Pos (12UL) /*!< PRIO (Bit 12) */ +#define DMA1_CH1CTL_PRIO_Msk (0x3000UL) /*!< PRIO (Bitfield-Mask: 0x03) */ +#define DMA1_CH1CTL_M2M_Pos (14UL) /*!< M2M (Bit 14) */ +#define DMA1_CH1CTL_M2M_Msk (0x4000UL) /*!< M2M (Bitfield-Mask: 0x01) */ +/* ======================================================== CH1CNT ========================================================= */ +#define DMA1_CH1CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA1_CH1CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= CH1PADDR ======================================================== */ +#define DMA1_CH1PADDR_PADDR_Pos (0UL) /*!< PADDR (Bit 0) */ +#define DMA1_CH1PADDR_PADDR_Msk (0xffffffffUL) /*!< PADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CH1MADDR ======================================================== */ +#define DMA1_CH1MADDR_MADDR_Pos (0UL) /*!< MADDR (Bit 0) */ +#define DMA1_CH1MADDR_MADDR_Msk (0xffffffffUL) /*!< MADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CH2CTL ========================================================= */ +#define DMA1_CH2CTL_CHEN_Pos (0UL) /*!< CHEN (Bit 0) */ +#define DMA1_CH2CTL_CHEN_Msk (0x1UL) /*!< CHEN (Bitfield-Mask: 0x01) */ +#define DMA1_CH2CTL_FTFIE_Pos (1UL) /*!< FTFIE (Bit 1) */ +#define DMA1_CH2CTL_FTFIE_Msk (0x2UL) /*!< FTFIE (Bitfield-Mask: 0x01) */ +#define DMA1_CH2CTL_HTFIE_Pos (2UL) /*!< HTFIE (Bit 2) */ +#define DMA1_CH2CTL_HTFIE_Msk (0x4UL) /*!< HTFIE (Bitfield-Mask: 0x01) */ +#define DMA1_CH2CTL_ERRIE_Pos (3UL) /*!< ERRIE (Bit 3) */ +#define DMA1_CH2CTL_ERRIE_Msk (0x8UL) /*!< ERRIE (Bitfield-Mask: 0x01) */ +#define DMA1_CH2CTL_DIR_Pos (4UL) /*!< DIR (Bit 4) */ +#define DMA1_CH2CTL_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +#define DMA1_CH2CTL_CMEN_Pos (5UL) /*!< CMEN (Bit 5) */ +#define DMA1_CH2CTL_CMEN_Msk (0x20UL) /*!< CMEN (Bitfield-Mask: 0x01) */ +#define DMA1_CH2CTL_PNAGA_Pos (6UL) /*!< PNAGA (Bit 6) */ +#define DMA1_CH2CTL_PNAGA_Msk (0x40UL) /*!< PNAGA (Bitfield-Mask: 0x01) */ +#define DMA1_CH2CTL_MNAGA_Pos (7UL) /*!< MNAGA (Bit 7) */ +#define DMA1_CH2CTL_MNAGA_Msk (0x80UL) /*!< MNAGA (Bitfield-Mask: 0x01) */ +#define DMA1_CH2CTL_PWIDTH_Pos (8UL) /*!< PWIDTH (Bit 8) */ +#define DMA1_CH2CTL_PWIDTH_Msk (0x300UL) /*!< PWIDTH (Bitfield-Mask: 0x03) */ +#define DMA1_CH2CTL_MWIDTH_Pos (10UL) /*!< MWIDTH (Bit 10) */ +#define DMA1_CH2CTL_MWIDTH_Msk (0xc00UL) /*!< MWIDTH (Bitfield-Mask: 0x03) */ +#define DMA1_CH2CTL_PRIO_Pos (12UL) /*!< PRIO (Bit 12) */ +#define DMA1_CH2CTL_PRIO_Msk (0x3000UL) /*!< PRIO (Bitfield-Mask: 0x03) */ +#define DMA1_CH2CTL_M2M_Pos (14UL) /*!< M2M (Bit 14) */ +#define DMA1_CH2CTL_M2M_Msk (0x4000UL) /*!< M2M (Bitfield-Mask: 0x01) */ +/* ======================================================== CH2CNT ========================================================= */ +#define DMA1_CH2CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA1_CH2CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= CH2PADDR ======================================================== */ +#define DMA1_CH2PADDR_PADDR_Pos (0UL) /*!< PADDR (Bit 0) */ +#define DMA1_CH2PADDR_PADDR_Msk (0xffffffffUL) /*!< PADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CH2MADDR ======================================================== */ +#define DMA1_CH2MADDR_MADDR_Pos (0UL) /*!< MADDR (Bit 0) */ +#define DMA1_CH2MADDR_MADDR_Msk (0xffffffffUL) /*!< MADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CH3CTL ========================================================= */ +#define DMA1_CH3CTL_CHEN_Pos (0UL) /*!< CHEN (Bit 0) */ +#define DMA1_CH3CTL_CHEN_Msk (0x1UL) /*!< CHEN (Bitfield-Mask: 0x01) */ +#define DMA1_CH3CTL_FTFIE_Pos (1UL) /*!< FTFIE (Bit 1) */ +#define DMA1_CH3CTL_FTFIE_Msk (0x2UL) /*!< FTFIE (Bitfield-Mask: 0x01) */ +#define DMA1_CH3CTL_HTFIE_Pos (2UL) /*!< HTFIE (Bit 2) */ +#define DMA1_CH3CTL_HTFIE_Msk (0x4UL) /*!< HTFIE (Bitfield-Mask: 0x01) */ +#define DMA1_CH3CTL_ERRIE_Pos (3UL) /*!< ERRIE (Bit 3) */ +#define DMA1_CH3CTL_ERRIE_Msk (0x8UL) /*!< ERRIE (Bitfield-Mask: 0x01) */ +#define DMA1_CH3CTL_DIR_Pos (4UL) /*!< DIR (Bit 4) */ +#define DMA1_CH3CTL_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +#define DMA1_CH3CTL_CMEN_Pos (5UL) /*!< CMEN (Bit 5) */ +#define DMA1_CH3CTL_CMEN_Msk (0x20UL) /*!< CMEN (Bitfield-Mask: 0x01) */ +#define DMA1_CH3CTL_PNAGA_Pos (6UL) /*!< PNAGA (Bit 6) */ +#define DMA1_CH3CTL_PNAGA_Msk (0x40UL) /*!< PNAGA (Bitfield-Mask: 0x01) */ +#define DMA1_CH3CTL_MNAGA_Pos (7UL) /*!< MNAGA (Bit 7) */ +#define DMA1_CH3CTL_MNAGA_Msk (0x80UL) /*!< MNAGA (Bitfield-Mask: 0x01) */ +#define DMA1_CH3CTL_PWIDTH_Pos (8UL) /*!< PWIDTH (Bit 8) */ +#define DMA1_CH3CTL_PWIDTH_Msk (0x300UL) /*!< PWIDTH (Bitfield-Mask: 0x03) */ +#define DMA1_CH3CTL_MWIDTH_Pos (10UL) /*!< MWIDTH (Bit 10) */ +#define DMA1_CH3CTL_MWIDTH_Msk (0xc00UL) /*!< MWIDTH (Bitfield-Mask: 0x03) */ +#define DMA1_CH3CTL_PRIO_Pos (12UL) /*!< PRIO (Bit 12) */ +#define DMA1_CH3CTL_PRIO_Msk (0x3000UL) /*!< PRIO (Bitfield-Mask: 0x03) */ +#define DMA1_CH3CTL_M2M_Pos (14UL) /*!< M2M (Bit 14) */ +#define DMA1_CH3CTL_M2M_Msk (0x4000UL) /*!< M2M (Bitfield-Mask: 0x01) */ +/* ======================================================== CH3CNT ========================================================= */ +#define DMA1_CH3CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA1_CH3CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= CH3PADDR ======================================================== */ +#define DMA1_CH3PADDR_PADDR_Pos (0UL) /*!< PADDR (Bit 0) */ +#define DMA1_CH3PADDR_PADDR_Msk (0xffffffffUL) /*!< PADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CH3MADDR ======================================================== */ +#define DMA1_CH3MADDR_MADDR_Pos (0UL) /*!< MADDR (Bit 0) */ +#define DMA1_CH3MADDR_MADDR_Msk (0xffffffffUL) /*!< MADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CH4CTL ========================================================= */ +#define DMA1_CH4CTL_CHEN_Pos (0UL) /*!< CHEN (Bit 0) */ +#define DMA1_CH4CTL_CHEN_Msk (0x1UL) /*!< CHEN (Bitfield-Mask: 0x01) */ +#define DMA1_CH4CTL_FTFIE_Pos (1UL) /*!< FTFIE (Bit 1) */ +#define DMA1_CH4CTL_FTFIE_Msk (0x2UL) /*!< FTFIE (Bitfield-Mask: 0x01) */ +#define DMA1_CH4CTL_HTFIE_Pos (2UL) /*!< HTFIE (Bit 2) */ +#define DMA1_CH4CTL_HTFIE_Msk (0x4UL) /*!< HTFIE (Bitfield-Mask: 0x01) */ +#define DMA1_CH4CTL_ERRIE_Pos (3UL) /*!< ERRIE (Bit 3) */ +#define DMA1_CH4CTL_ERRIE_Msk (0x8UL) /*!< ERRIE (Bitfield-Mask: 0x01) */ +#define DMA1_CH4CTL_DIR_Pos (4UL) /*!< DIR (Bit 4) */ +#define DMA1_CH4CTL_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +#define DMA1_CH4CTL_CMEN_Pos (5UL) /*!< CMEN (Bit 5) */ +#define DMA1_CH4CTL_CMEN_Msk (0x20UL) /*!< CMEN (Bitfield-Mask: 0x01) */ +#define DMA1_CH4CTL_PNAGA_Pos (6UL) /*!< PNAGA (Bit 6) */ +#define DMA1_CH4CTL_PNAGA_Msk (0x40UL) /*!< PNAGA (Bitfield-Mask: 0x01) */ +#define DMA1_CH4CTL_MNAGA_Pos (7UL) /*!< MNAGA (Bit 7) */ +#define DMA1_CH4CTL_MNAGA_Msk (0x80UL) /*!< MNAGA (Bitfield-Mask: 0x01) */ +#define DMA1_CH4CTL_PWIDTH_Pos (8UL) /*!< PWIDTH (Bit 8) */ +#define DMA1_CH4CTL_PWIDTH_Msk (0x300UL) /*!< PWIDTH (Bitfield-Mask: 0x03) */ +#define DMA1_CH4CTL_MWIDTH_Pos (10UL) /*!< MWIDTH (Bit 10) */ +#define DMA1_CH4CTL_MWIDTH_Msk (0xc00UL) /*!< MWIDTH (Bitfield-Mask: 0x03) */ +#define DMA1_CH4CTL_PRIO_Pos (12UL) /*!< PRIO (Bit 12) */ +#define DMA1_CH4CTL_PRIO_Msk (0x3000UL) /*!< PRIO (Bitfield-Mask: 0x03) */ +#define DMA1_CH4CTL_M2M_Pos (14UL) /*!< M2M (Bit 14) */ +#define DMA1_CH4CTL_M2M_Msk (0x4000UL) /*!< M2M (Bitfield-Mask: 0x01) */ +/* ======================================================== CH4CNT ========================================================= */ +#define DMA1_CH4CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define DMA1_CH4CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= CH4PADDR ======================================================== */ +#define DMA1_CH4PADDR_PADDR_Pos (0UL) /*!< PADDR (Bit 0) */ +#define DMA1_CH4PADDR_PADDR_Msk (0xffffffffUL) /*!< PADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CH4MADDR ======================================================== */ +#define DMA1_CH4MADDR_MADDR_Pos (0UL) /*!< MADDR (Bit 0) */ +#define DMA1_CH4MADDR_MADDR_Msk (0xffffffffUL) /*!< MADDR (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ EXMC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SNCTL0 ========================================================= */ +#define EXMC_SNCTL0_ASYNCWAIT_Pos (15UL) /*!< ASYNCWAIT (Bit 15) */ +#define EXMC_SNCTL0_ASYNCWAIT_Msk (0x8000UL) /*!< ASYNCWAIT (Bitfield-Mask: 0x01) */ +#define EXMC_SNCTL0_NRWTEN_Pos (13UL) /*!< NRWTEN (Bit 13) */ +#define EXMC_SNCTL0_NRWTEN_Msk (0x2000UL) /*!< NRWTEN (Bitfield-Mask: 0x01) */ +#define EXMC_SNCTL0_WREN_Pos (12UL) /*!< WREN (Bit 12) */ +#define EXMC_SNCTL0_WREN_Msk (0x1000UL) /*!< WREN (Bitfield-Mask: 0x01) */ +#define EXMC_SNCTL0_NRWTPOL_Pos (9UL) /*!< NRWTPOL (Bit 9) */ +#define EXMC_SNCTL0_NRWTPOL_Msk (0x200UL) /*!< NRWTPOL (Bitfield-Mask: 0x01) */ +#define EXMC_SNCTL0_NREN_Pos (6UL) /*!< NREN (Bit 6) */ +#define EXMC_SNCTL0_NREN_Msk (0x40UL) /*!< NREN (Bitfield-Mask: 0x01) */ +#define EXMC_SNCTL0_NRW_Pos (4UL) /*!< NRW (Bit 4) */ +#define EXMC_SNCTL0_NRW_Msk (0x30UL) /*!< NRW (Bitfield-Mask: 0x03) */ +#define EXMC_SNCTL0_NRTP_Pos (2UL) /*!< NRTP (Bit 2) */ +#define EXMC_SNCTL0_NRTP_Msk (0xcUL) /*!< NRTP (Bitfield-Mask: 0x03) */ +#define EXMC_SNCTL0_NRMUX_Pos (1UL) /*!< NRMUX (Bit 1) */ +#define EXMC_SNCTL0_NRMUX_Msk (0x2UL) /*!< NRMUX (Bitfield-Mask: 0x01) */ +#define EXMC_SNCTL0_NRBKEN_Pos (0UL) /*!< NRBKEN (Bit 0) */ +#define EXMC_SNCTL0_NRBKEN_Msk (0x1UL) /*!< NRBKEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SNTCFG0 ======================================================== */ +#define EXMC_SNTCFG0_BUSLAT_Pos (16UL) /*!< BUSLAT (Bit 16) */ +#define EXMC_SNTCFG0_BUSLAT_Msk (0xf0000UL) /*!< BUSLAT (Bitfield-Mask: 0x0f) */ +#define EXMC_SNTCFG0_DSET_Pos (8UL) /*!< DSET (Bit 8) */ +#define EXMC_SNTCFG0_DSET_Msk (0xff00UL) /*!< DSET (Bitfield-Mask: 0xff) */ +#define EXMC_SNTCFG0_AHLD_Pos (4UL) /*!< AHLD (Bit 4) */ +#define EXMC_SNTCFG0_AHLD_Msk (0xf0UL) /*!< AHLD (Bitfield-Mask: 0x0f) */ +#define EXMC_SNTCFG0_ASET_Pos (0UL) /*!< ASET (Bit 0) */ +#define EXMC_SNTCFG0_ASET_Msk (0xfUL) /*!< ASET (Bitfield-Mask: 0x0f) */ +/* ======================================================== SNCTL1 ========================================================= */ +#define EXMC_SNCTL1_ASYNCWAIT_Pos (15UL) /*!< ASYNCWAIT (Bit 15) */ +#define EXMC_SNCTL1_ASYNCWAIT_Msk (0x8000UL) /*!< ASYNCWAIT (Bitfield-Mask: 0x01) */ +#define EXMC_SNCTL1_NRWTEN_Pos (13UL) /*!< NRWTEN (Bit 13) */ +#define EXMC_SNCTL1_NRWTEN_Msk (0x2000UL) /*!< NRWTEN (Bitfield-Mask: 0x01) */ +#define EXMC_SNCTL1_WREN_Pos (12UL) /*!< WREN (Bit 12) */ +#define EXMC_SNCTL1_WREN_Msk (0x1000UL) /*!< WREN (Bitfield-Mask: 0x01) */ +#define EXMC_SNCTL1_NRWTPOL_Pos (9UL) /*!< NRWTPOL (Bit 9) */ +#define EXMC_SNCTL1_NRWTPOL_Msk (0x200UL) /*!< NRWTPOL (Bitfield-Mask: 0x01) */ +#define EXMC_SNCTL1_NREN_Pos (6UL) /*!< NREN (Bit 6) */ +#define EXMC_SNCTL1_NREN_Msk (0x40UL) /*!< NREN (Bitfield-Mask: 0x01) */ +#define EXMC_SNCTL1_NRW_Pos (4UL) /*!< NRW (Bit 4) */ +#define EXMC_SNCTL1_NRW_Msk (0x30UL) /*!< NRW (Bitfield-Mask: 0x03) */ +#define EXMC_SNCTL1_NRTP_Pos (2UL) /*!< NRTP (Bit 2) */ +#define EXMC_SNCTL1_NRTP_Msk (0xcUL) /*!< NRTP (Bitfield-Mask: 0x03) */ +#define EXMC_SNCTL1_NRMUX_Pos (1UL) /*!< NRMUX (Bit 1) */ +#define EXMC_SNCTL1_NRMUX_Msk (0x2UL) /*!< NRMUX (Bitfield-Mask: 0x01) */ +#define EXMC_SNCTL1_NRBKEN_Pos (0UL) /*!< NRBKEN (Bit 0) */ +#define EXMC_SNCTL1_NRBKEN_Msk (0x1UL) /*!< NRBKEN (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ EXTI ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= INTEN ========================================================= */ +#define EXTI_INTEN_INTEN0_Pos (0UL) /*!< INTEN0 (Bit 0) */ +#define EXTI_INTEN_INTEN0_Msk (0x1UL) /*!< INTEN0 (Bitfield-Mask: 0x01) */ +#define EXTI_INTEN_INTEN1_Pos (1UL) /*!< INTEN1 (Bit 1) */ +#define EXTI_INTEN_INTEN1_Msk (0x2UL) /*!< INTEN1 (Bitfield-Mask: 0x01) */ +#define EXTI_INTEN_INTEN2_Pos (2UL) /*!< INTEN2 (Bit 2) */ +#define EXTI_INTEN_INTEN2_Msk (0x4UL) /*!< INTEN2 (Bitfield-Mask: 0x01) */ +#define EXTI_INTEN_INTEN3_Pos (3UL) /*!< INTEN3 (Bit 3) */ +#define EXTI_INTEN_INTEN3_Msk (0x8UL) /*!< INTEN3 (Bitfield-Mask: 0x01) */ +#define EXTI_INTEN_INTEN4_Pos (4UL) /*!< INTEN4 (Bit 4) */ +#define EXTI_INTEN_INTEN4_Msk (0x10UL) /*!< INTEN4 (Bitfield-Mask: 0x01) */ +#define EXTI_INTEN_INTEN5_Pos (5UL) /*!< INTEN5 (Bit 5) */ +#define EXTI_INTEN_INTEN5_Msk (0x20UL) /*!< INTEN5 (Bitfield-Mask: 0x01) */ +#define EXTI_INTEN_INTEN6_Pos (6UL) /*!< INTEN6 (Bit 6) */ +#define EXTI_INTEN_INTEN6_Msk (0x40UL) /*!< INTEN6 (Bitfield-Mask: 0x01) */ +#define EXTI_INTEN_INTEN7_Pos (7UL) /*!< INTEN7 (Bit 7) */ +#define EXTI_INTEN_INTEN7_Msk (0x80UL) /*!< INTEN7 (Bitfield-Mask: 0x01) */ +#define EXTI_INTEN_INTEN8_Pos (8UL) /*!< INTEN8 (Bit 8) */ +#define EXTI_INTEN_INTEN8_Msk (0x100UL) /*!< INTEN8 (Bitfield-Mask: 0x01) */ +#define EXTI_INTEN_INTEN9_Pos (9UL) /*!< INTEN9 (Bit 9) */ +#define EXTI_INTEN_INTEN9_Msk (0x200UL) /*!< INTEN9 (Bitfield-Mask: 0x01) */ +#define EXTI_INTEN_INTEN10_Pos (10UL) /*!< INTEN10 (Bit 10) */ +#define EXTI_INTEN_INTEN10_Msk (0x400UL) /*!< INTEN10 (Bitfield-Mask: 0x01) */ +#define EXTI_INTEN_INTEN11_Pos (11UL) /*!< INTEN11 (Bit 11) */ +#define EXTI_INTEN_INTEN11_Msk (0x800UL) /*!< INTEN11 (Bitfield-Mask: 0x01) */ +#define EXTI_INTEN_INTEN12_Pos (12UL) /*!< INTEN12 (Bit 12) */ +#define EXTI_INTEN_INTEN12_Msk (0x1000UL) /*!< INTEN12 (Bitfield-Mask: 0x01) */ +#define EXTI_INTEN_INTEN13_Pos (13UL) /*!< INTEN13 (Bit 13) */ +#define EXTI_INTEN_INTEN13_Msk (0x2000UL) /*!< INTEN13 (Bitfield-Mask: 0x01) */ +#define EXTI_INTEN_INTEN14_Pos (14UL) /*!< INTEN14 (Bit 14) */ +#define EXTI_INTEN_INTEN14_Msk (0x4000UL) /*!< INTEN14 (Bitfield-Mask: 0x01) */ +#define EXTI_INTEN_INTEN15_Pos (15UL) /*!< INTEN15 (Bit 15) */ +#define EXTI_INTEN_INTEN15_Msk (0x8000UL) /*!< INTEN15 (Bitfield-Mask: 0x01) */ +#define EXTI_INTEN_INTEN16_Pos (16UL) /*!< INTEN16 (Bit 16) */ +#define EXTI_INTEN_INTEN16_Msk (0x10000UL) /*!< INTEN16 (Bitfield-Mask: 0x01) */ +#define EXTI_INTEN_INTEN17_Pos (17UL) /*!< INTEN17 (Bit 17) */ +#define EXTI_INTEN_INTEN17_Msk (0x20000UL) /*!< INTEN17 (Bitfield-Mask: 0x01) */ +#define EXTI_INTEN_INTEN18_Pos (18UL) /*!< INTEN18 (Bit 18) */ +#define EXTI_INTEN_INTEN18_Msk (0x40000UL) /*!< INTEN18 (Bitfield-Mask: 0x01) */ +/* ========================================================= EVEN ========================================================== */ +#define EXTI_EVEN_EVEN0_Pos (0UL) /*!< EVEN0 (Bit 0) */ +#define EXTI_EVEN_EVEN0_Msk (0x1UL) /*!< EVEN0 (Bitfield-Mask: 0x01) */ +#define EXTI_EVEN_EVEN1_Pos (1UL) /*!< EVEN1 (Bit 1) */ +#define EXTI_EVEN_EVEN1_Msk (0x2UL) /*!< EVEN1 (Bitfield-Mask: 0x01) */ +#define EXTI_EVEN_EVEN2_Pos (2UL) /*!< EVEN2 (Bit 2) */ +#define EXTI_EVEN_EVEN2_Msk (0x4UL) /*!< EVEN2 (Bitfield-Mask: 0x01) */ +#define EXTI_EVEN_EVEN3_Pos (3UL) /*!< EVEN3 (Bit 3) */ +#define EXTI_EVEN_EVEN3_Msk (0x8UL) /*!< EVEN3 (Bitfield-Mask: 0x01) */ +#define EXTI_EVEN_EVEN4_Pos (4UL) /*!< EVEN4 (Bit 4) */ +#define EXTI_EVEN_EVEN4_Msk (0x10UL) /*!< EVEN4 (Bitfield-Mask: 0x01) */ +#define EXTI_EVEN_EVEN5_Pos (5UL) /*!< EVEN5 (Bit 5) */ +#define EXTI_EVEN_EVEN5_Msk (0x20UL) /*!< EVEN5 (Bitfield-Mask: 0x01) */ +#define EXTI_EVEN_EVEN6_Pos (6UL) /*!< EVEN6 (Bit 6) */ +#define EXTI_EVEN_EVEN6_Msk (0x40UL) /*!< EVEN6 (Bitfield-Mask: 0x01) */ +#define EXTI_EVEN_EVEN7_Pos (7UL) /*!< EVEN7 (Bit 7) */ +#define EXTI_EVEN_EVEN7_Msk (0x80UL) /*!< EVEN7 (Bitfield-Mask: 0x01) */ +#define EXTI_EVEN_EVEN8_Pos (8UL) /*!< EVEN8 (Bit 8) */ +#define EXTI_EVEN_EVEN8_Msk (0x100UL) /*!< EVEN8 (Bitfield-Mask: 0x01) */ +#define EXTI_EVEN_EVEN9_Pos (9UL) /*!< EVEN9 (Bit 9) */ +#define EXTI_EVEN_EVEN9_Msk (0x200UL) /*!< EVEN9 (Bitfield-Mask: 0x01) */ +#define EXTI_EVEN_EVEN10_Pos (10UL) /*!< EVEN10 (Bit 10) */ +#define EXTI_EVEN_EVEN10_Msk (0x400UL) /*!< EVEN10 (Bitfield-Mask: 0x01) */ +#define EXTI_EVEN_EVEN11_Pos (11UL) /*!< EVEN11 (Bit 11) */ +#define EXTI_EVEN_EVEN11_Msk (0x800UL) /*!< EVEN11 (Bitfield-Mask: 0x01) */ +#define EXTI_EVEN_EVEN12_Pos (12UL) /*!< EVEN12 (Bit 12) */ +#define EXTI_EVEN_EVEN12_Msk (0x1000UL) /*!< EVEN12 (Bitfield-Mask: 0x01) */ +#define EXTI_EVEN_EVEN13_Pos (13UL) /*!< EVEN13 (Bit 13) */ +#define EXTI_EVEN_EVEN13_Msk (0x2000UL) /*!< EVEN13 (Bitfield-Mask: 0x01) */ +#define EXTI_EVEN_EVEN14_Pos (14UL) /*!< EVEN14 (Bit 14) */ +#define EXTI_EVEN_EVEN14_Msk (0x4000UL) /*!< EVEN14 (Bitfield-Mask: 0x01) */ +#define EXTI_EVEN_EVEN15_Pos (15UL) /*!< EVEN15 (Bit 15) */ +#define EXTI_EVEN_EVEN15_Msk (0x8000UL) /*!< EVEN15 (Bitfield-Mask: 0x01) */ +#define EXTI_EVEN_EVEN16_Pos (16UL) /*!< EVEN16 (Bit 16) */ +#define EXTI_EVEN_EVEN16_Msk (0x10000UL) /*!< EVEN16 (Bitfield-Mask: 0x01) */ +#define EXTI_EVEN_EVEN17_Pos (17UL) /*!< EVEN17 (Bit 17) */ +#define EXTI_EVEN_EVEN17_Msk (0x20000UL) /*!< EVEN17 (Bitfield-Mask: 0x01) */ +#define EXTI_EVEN_EVEN18_Pos (18UL) /*!< EVEN18 (Bit 18) */ +#define EXTI_EVEN_EVEN18_Msk (0x40000UL) /*!< EVEN18 (Bitfield-Mask: 0x01) */ +/* ========================================================= RTEN ========================================================== */ +#define EXTI_RTEN_RTEN0_Pos (0UL) /*!< RTEN0 (Bit 0) */ +#define EXTI_RTEN_RTEN0_Msk (0x1UL) /*!< RTEN0 (Bitfield-Mask: 0x01) */ +#define EXTI_RTEN_RTEN1_Pos (1UL) /*!< RTEN1 (Bit 1) */ +#define EXTI_RTEN_RTEN1_Msk (0x2UL) /*!< RTEN1 (Bitfield-Mask: 0x01) */ +#define EXTI_RTEN_RTEN2_Pos (2UL) /*!< RTEN2 (Bit 2) */ +#define EXTI_RTEN_RTEN2_Msk (0x4UL) /*!< RTEN2 (Bitfield-Mask: 0x01) */ +#define EXTI_RTEN_RTEN3_Pos (3UL) /*!< RTEN3 (Bit 3) */ +#define EXTI_RTEN_RTEN3_Msk (0x8UL) /*!< RTEN3 (Bitfield-Mask: 0x01) */ +#define EXTI_RTEN_RTEN4_Pos (4UL) /*!< RTEN4 (Bit 4) */ +#define EXTI_RTEN_RTEN4_Msk (0x10UL) /*!< RTEN4 (Bitfield-Mask: 0x01) */ +#define EXTI_RTEN_RTEN5_Pos (5UL) /*!< RTEN5 (Bit 5) */ +#define EXTI_RTEN_RTEN5_Msk (0x20UL) /*!< RTEN5 (Bitfield-Mask: 0x01) */ +#define EXTI_RTEN_RTEN6_Pos (6UL) /*!< RTEN6 (Bit 6) */ +#define EXTI_RTEN_RTEN6_Msk (0x40UL) /*!< RTEN6 (Bitfield-Mask: 0x01) */ +#define EXTI_RTEN_RTEN7_Pos (7UL) /*!< RTEN7 (Bit 7) */ +#define EXTI_RTEN_RTEN7_Msk (0x80UL) /*!< RTEN7 (Bitfield-Mask: 0x01) */ +#define EXTI_RTEN_RTEN8_Pos (8UL) /*!< RTEN8 (Bit 8) */ +#define EXTI_RTEN_RTEN8_Msk (0x100UL) /*!< RTEN8 (Bitfield-Mask: 0x01) */ +#define EXTI_RTEN_RTEN9_Pos (9UL) /*!< RTEN9 (Bit 9) */ +#define EXTI_RTEN_RTEN9_Msk (0x200UL) /*!< RTEN9 (Bitfield-Mask: 0x01) */ +#define EXTI_RTEN_RTEN10_Pos (10UL) /*!< RTEN10 (Bit 10) */ +#define EXTI_RTEN_RTEN10_Msk (0x400UL) /*!< RTEN10 (Bitfield-Mask: 0x01) */ +#define EXTI_RTEN_RTEN11_Pos (11UL) /*!< RTEN11 (Bit 11) */ +#define EXTI_RTEN_RTEN11_Msk (0x800UL) /*!< RTEN11 (Bitfield-Mask: 0x01) */ +#define EXTI_RTEN_RTEN12_Pos (12UL) /*!< RTEN12 (Bit 12) */ +#define EXTI_RTEN_RTEN12_Msk (0x1000UL) /*!< RTEN12 (Bitfield-Mask: 0x01) */ +#define EXTI_RTEN_RTEN13_Pos (13UL) /*!< RTEN13 (Bit 13) */ +#define EXTI_RTEN_RTEN13_Msk (0x2000UL) /*!< RTEN13 (Bitfield-Mask: 0x01) */ +#define EXTI_RTEN_RTEN14_Pos (14UL) /*!< RTEN14 (Bit 14) */ +#define EXTI_RTEN_RTEN14_Msk (0x4000UL) /*!< RTEN14 (Bitfield-Mask: 0x01) */ +#define EXTI_RTEN_RTEN15_Pos (15UL) /*!< RTEN15 (Bit 15) */ +#define EXTI_RTEN_RTEN15_Msk (0x8000UL) /*!< RTEN15 (Bitfield-Mask: 0x01) */ +#define EXTI_RTEN_RTEN16_Pos (16UL) /*!< RTEN16 (Bit 16) */ +#define EXTI_RTEN_RTEN16_Msk (0x10000UL) /*!< RTEN16 (Bitfield-Mask: 0x01) */ +#define EXTI_RTEN_RTEN17_Pos (17UL) /*!< RTEN17 (Bit 17) */ +#define EXTI_RTEN_RTEN17_Msk (0x20000UL) /*!< RTEN17 (Bitfield-Mask: 0x01) */ +#define EXTI_RTEN_RTEN18_Pos (18UL) /*!< RTEN18 (Bit 18) */ +#define EXTI_RTEN_RTEN18_Msk (0x40000UL) /*!< RTEN18 (Bitfield-Mask: 0x01) */ +/* ========================================================= FTEN ========================================================== */ +#define EXTI_FTEN_FTEN0_Pos (0UL) /*!< FTEN0 (Bit 0) */ +#define EXTI_FTEN_FTEN0_Msk (0x1UL) /*!< FTEN0 (Bitfield-Mask: 0x01) */ +#define EXTI_FTEN_FTEN1_Pos (1UL) /*!< FTEN1 (Bit 1) */ +#define EXTI_FTEN_FTEN1_Msk (0x2UL) /*!< FTEN1 (Bitfield-Mask: 0x01) */ +#define EXTI_FTEN_FTEN2_Pos (2UL) /*!< FTEN2 (Bit 2) */ +#define EXTI_FTEN_FTEN2_Msk (0x4UL) /*!< FTEN2 (Bitfield-Mask: 0x01) */ +#define EXTI_FTEN_FTEN3_Pos (3UL) /*!< FTEN3 (Bit 3) */ +#define EXTI_FTEN_FTEN3_Msk (0x8UL) /*!< FTEN3 (Bitfield-Mask: 0x01) */ +#define EXTI_FTEN_FTEN4_Pos (4UL) /*!< FTEN4 (Bit 4) */ +#define EXTI_FTEN_FTEN4_Msk (0x10UL) /*!< FTEN4 (Bitfield-Mask: 0x01) */ +#define EXTI_FTEN_FTEN5_Pos (5UL) /*!< FTEN5 (Bit 5) */ +#define EXTI_FTEN_FTEN5_Msk (0x20UL) /*!< FTEN5 (Bitfield-Mask: 0x01) */ +#define EXTI_FTEN_FTEN6_Pos (6UL) /*!< FTEN6 (Bit 6) */ +#define EXTI_FTEN_FTEN6_Msk (0x40UL) /*!< FTEN6 (Bitfield-Mask: 0x01) */ +#define EXTI_FTEN_FTEN7_Pos (7UL) /*!< FTEN7 (Bit 7) */ +#define EXTI_FTEN_FTEN7_Msk (0x80UL) /*!< FTEN7 (Bitfield-Mask: 0x01) */ +#define EXTI_FTEN_FTEN8_Pos (8UL) /*!< FTEN8 (Bit 8) */ +#define EXTI_FTEN_FTEN8_Msk (0x100UL) /*!< FTEN8 (Bitfield-Mask: 0x01) */ +#define EXTI_FTEN_FTEN9_Pos (9UL) /*!< FTEN9 (Bit 9) */ +#define EXTI_FTEN_FTEN9_Msk (0x200UL) /*!< FTEN9 (Bitfield-Mask: 0x01) */ +#define EXTI_FTEN_FTEN10_Pos (10UL) /*!< FTEN10 (Bit 10) */ +#define EXTI_FTEN_FTEN10_Msk (0x400UL) /*!< FTEN10 (Bitfield-Mask: 0x01) */ +#define EXTI_FTEN_FTEN11_Pos (11UL) /*!< FTEN11 (Bit 11) */ +#define EXTI_FTEN_FTEN11_Msk (0x800UL) /*!< FTEN11 (Bitfield-Mask: 0x01) */ +#define EXTI_FTEN_FTEN12_Pos (12UL) /*!< FTEN12 (Bit 12) */ +#define EXTI_FTEN_FTEN12_Msk (0x1000UL) /*!< FTEN12 (Bitfield-Mask: 0x01) */ +#define EXTI_FTEN_FTEN13_Pos (13UL) /*!< FTEN13 (Bit 13) */ +#define EXTI_FTEN_FTEN13_Msk (0x2000UL) /*!< FTEN13 (Bitfield-Mask: 0x01) */ +#define EXTI_FTEN_FTEN14_Pos (14UL) /*!< FTEN14 (Bit 14) */ +#define EXTI_FTEN_FTEN14_Msk (0x4000UL) /*!< FTEN14 (Bitfield-Mask: 0x01) */ +#define EXTI_FTEN_FTEN15_Pos (15UL) /*!< FTEN15 (Bit 15) */ +#define EXTI_FTEN_FTEN15_Msk (0x8000UL) /*!< FTEN15 (Bitfield-Mask: 0x01) */ +#define EXTI_FTEN_FTEN16_Pos (16UL) /*!< FTEN16 (Bit 16) */ +#define EXTI_FTEN_FTEN16_Msk (0x10000UL) /*!< FTEN16 (Bitfield-Mask: 0x01) */ +#define EXTI_FTEN_FTEN17_Pos (17UL) /*!< FTEN17 (Bit 17) */ +#define EXTI_FTEN_FTEN17_Msk (0x20000UL) /*!< FTEN17 (Bitfield-Mask: 0x01) */ +#define EXTI_FTEN_FTEN18_Pos (18UL) /*!< FTEN18 (Bit 18) */ +#define EXTI_FTEN_FTEN18_Msk (0x40000UL) /*!< FTEN18 (Bitfield-Mask: 0x01) */ +/* ========================================================= SWIEV ========================================================= */ +#define EXTI_SWIEV_SWIEV0_Pos (0UL) /*!< SWIEV0 (Bit 0) */ +#define EXTI_SWIEV_SWIEV0_Msk (0x1UL) /*!< SWIEV0 (Bitfield-Mask: 0x01) */ +#define EXTI_SWIEV_SWIEV1_Pos (1UL) /*!< SWIEV1 (Bit 1) */ +#define EXTI_SWIEV_SWIEV1_Msk (0x2UL) /*!< SWIEV1 (Bitfield-Mask: 0x01) */ +#define EXTI_SWIEV_SWIEV2_Pos (2UL) /*!< SWIEV2 (Bit 2) */ +#define EXTI_SWIEV_SWIEV2_Msk (0x4UL) /*!< SWIEV2 (Bitfield-Mask: 0x01) */ +#define EXTI_SWIEV_SWIEV3_Pos (3UL) /*!< SWIEV3 (Bit 3) */ +#define EXTI_SWIEV_SWIEV3_Msk (0x8UL) /*!< SWIEV3 (Bitfield-Mask: 0x01) */ +#define EXTI_SWIEV_SWIEV4_Pos (4UL) /*!< SWIEV4 (Bit 4) */ +#define EXTI_SWIEV_SWIEV4_Msk (0x10UL) /*!< SWIEV4 (Bitfield-Mask: 0x01) */ +#define EXTI_SWIEV_SWIEV5_Pos (5UL) /*!< SWIEV5 (Bit 5) */ +#define EXTI_SWIEV_SWIEV5_Msk (0x20UL) /*!< SWIEV5 (Bitfield-Mask: 0x01) */ +#define EXTI_SWIEV_SWIEV6_Pos (6UL) /*!< SWIEV6 (Bit 6) */ +#define EXTI_SWIEV_SWIEV6_Msk (0x40UL) /*!< SWIEV6 (Bitfield-Mask: 0x01) */ +#define EXTI_SWIEV_SWIEV7_Pos (7UL) /*!< SWIEV7 (Bit 7) */ +#define EXTI_SWIEV_SWIEV7_Msk (0x80UL) /*!< SWIEV7 (Bitfield-Mask: 0x01) */ +#define EXTI_SWIEV_SWIEV8_Pos (8UL) /*!< SWIEV8 (Bit 8) */ +#define EXTI_SWIEV_SWIEV8_Msk (0x100UL) /*!< SWIEV8 (Bitfield-Mask: 0x01) */ +#define EXTI_SWIEV_SWIEV9_Pos (9UL) /*!< SWIEV9 (Bit 9) */ +#define EXTI_SWIEV_SWIEV9_Msk (0x200UL) /*!< SWIEV9 (Bitfield-Mask: 0x01) */ +#define EXTI_SWIEV_SWIEV10_Pos (10UL) /*!< SWIEV10 (Bit 10) */ +#define EXTI_SWIEV_SWIEV10_Msk (0x400UL) /*!< SWIEV10 (Bitfield-Mask: 0x01) */ +#define EXTI_SWIEV_SWIEV11_Pos (11UL) /*!< SWIEV11 (Bit 11) */ +#define EXTI_SWIEV_SWIEV11_Msk (0x800UL) /*!< SWIEV11 (Bitfield-Mask: 0x01) */ +#define EXTI_SWIEV_SWIEV12_Pos (12UL) /*!< SWIEV12 (Bit 12) */ +#define EXTI_SWIEV_SWIEV12_Msk (0x1000UL) /*!< SWIEV12 (Bitfield-Mask: 0x01) */ +#define EXTI_SWIEV_SWIEV13_Pos (13UL) /*!< SWIEV13 (Bit 13) */ +#define EXTI_SWIEV_SWIEV13_Msk (0x2000UL) /*!< SWIEV13 (Bitfield-Mask: 0x01) */ +#define EXTI_SWIEV_SWIEV14_Pos (14UL) /*!< SWIEV14 (Bit 14) */ +#define EXTI_SWIEV_SWIEV14_Msk (0x4000UL) /*!< SWIEV14 (Bitfield-Mask: 0x01) */ +#define EXTI_SWIEV_SWIEV15_Pos (15UL) /*!< SWIEV15 (Bit 15) */ +#define EXTI_SWIEV_SWIEV15_Msk (0x8000UL) /*!< SWIEV15 (Bitfield-Mask: 0x01) */ +#define EXTI_SWIEV_SWIEV16_Pos (16UL) /*!< SWIEV16 (Bit 16) */ +#define EXTI_SWIEV_SWIEV16_Msk (0x10000UL) /*!< SWIEV16 (Bitfield-Mask: 0x01) */ +#define EXTI_SWIEV_SWIEV17_Pos (17UL) /*!< SWIEV17 (Bit 17) */ +#define EXTI_SWIEV_SWIEV17_Msk (0x20000UL) /*!< SWIEV17 (Bitfield-Mask: 0x01) */ +#define EXTI_SWIEV_SWIEV18_Pos (18UL) /*!< SWIEV18 (Bit 18) */ +#define EXTI_SWIEV_SWIEV18_Msk (0x40000UL) /*!< SWIEV18 (Bitfield-Mask: 0x01) */ +/* ========================================================== PD =========================================================== */ +#define EXTI_PD_PD0_Pos (0UL) /*!< PD0 (Bit 0) */ +#define EXTI_PD_PD0_Msk (0x1UL) /*!< PD0 (Bitfield-Mask: 0x01) */ +#define EXTI_PD_PD1_Pos (1UL) /*!< PD1 (Bit 1) */ +#define EXTI_PD_PD1_Msk (0x2UL) /*!< PD1 (Bitfield-Mask: 0x01) */ +#define EXTI_PD_PD2_Pos (2UL) /*!< PD2 (Bit 2) */ +#define EXTI_PD_PD2_Msk (0x4UL) /*!< PD2 (Bitfield-Mask: 0x01) */ +#define EXTI_PD_PD3_Pos (3UL) /*!< PD3 (Bit 3) */ +#define EXTI_PD_PD3_Msk (0x8UL) /*!< PD3 (Bitfield-Mask: 0x01) */ +#define EXTI_PD_PD4_Pos (4UL) /*!< PD4 (Bit 4) */ +#define EXTI_PD_PD4_Msk (0x10UL) /*!< PD4 (Bitfield-Mask: 0x01) */ +#define EXTI_PD_PD5_Pos (5UL) /*!< PD5 (Bit 5) */ +#define EXTI_PD_PD5_Msk (0x20UL) /*!< PD5 (Bitfield-Mask: 0x01) */ +#define EXTI_PD_PD6_Pos (6UL) /*!< PD6 (Bit 6) */ +#define EXTI_PD_PD6_Msk (0x40UL) /*!< PD6 (Bitfield-Mask: 0x01) */ +#define EXTI_PD_PD7_Pos (7UL) /*!< PD7 (Bit 7) */ +#define EXTI_PD_PD7_Msk (0x80UL) /*!< PD7 (Bitfield-Mask: 0x01) */ +#define EXTI_PD_PD8_Pos (8UL) /*!< PD8 (Bit 8) */ +#define EXTI_PD_PD8_Msk (0x100UL) /*!< PD8 (Bitfield-Mask: 0x01) */ +#define EXTI_PD_PD9_Pos (9UL) /*!< PD9 (Bit 9) */ +#define EXTI_PD_PD9_Msk (0x200UL) /*!< PD9 (Bitfield-Mask: 0x01) */ +#define EXTI_PD_PD10_Pos (10UL) /*!< PD10 (Bit 10) */ +#define EXTI_PD_PD10_Msk (0x400UL) /*!< PD10 (Bitfield-Mask: 0x01) */ +#define EXTI_PD_PD11_Pos (11UL) /*!< PD11 (Bit 11) */ +#define EXTI_PD_PD11_Msk (0x800UL) /*!< PD11 (Bitfield-Mask: 0x01) */ +#define EXTI_PD_PD12_Pos (12UL) /*!< PD12 (Bit 12) */ +#define EXTI_PD_PD12_Msk (0x1000UL) /*!< PD12 (Bitfield-Mask: 0x01) */ +#define EXTI_PD_PD13_Pos (13UL) /*!< PD13 (Bit 13) */ +#define EXTI_PD_PD13_Msk (0x2000UL) /*!< PD13 (Bitfield-Mask: 0x01) */ +#define EXTI_PD_PD14_Pos (14UL) /*!< PD14 (Bit 14) */ +#define EXTI_PD_PD14_Msk (0x4000UL) /*!< PD14 (Bitfield-Mask: 0x01) */ +#define EXTI_PD_PD15_Pos (15UL) /*!< PD15 (Bit 15) */ +#define EXTI_PD_PD15_Msk (0x8000UL) /*!< PD15 (Bitfield-Mask: 0x01) */ +#define EXTI_PD_PD16_Pos (16UL) /*!< PD16 (Bit 16) */ +#define EXTI_PD_PD16_Msk (0x10000UL) /*!< PD16 (Bitfield-Mask: 0x01) */ +#define EXTI_PD_PD17_Pos (17UL) /*!< PD17 (Bit 17) */ +#define EXTI_PD_PD17_Msk (0x20000UL) /*!< PD17 (Bitfield-Mask: 0x01) */ +#define EXTI_PD_PD18_Pos (18UL) /*!< PD18 (Bit 18) */ +#define EXTI_PD_PD18_Msk (0x40000UL) /*!< PD18 (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ FMC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== WS =========================================================== */ +#define FMC_WS_WSCNT_Pos (0UL) /*!< WSCNT (Bit 0) */ +#define FMC_WS_WSCNT_Msk (0x7UL) /*!< WSCNT (Bitfield-Mask: 0x07) */ +/* ========================================================= KEY0 ========================================================== */ +#define FMC_KEY0_KEY_Pos (0UL) /*!< KEY (Bit 0) */ +#define FMC_KEY0_KEY_Msk (0xffffffffUL) /*!< KEY (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= OBKEY ========================================================= */ +#define FMC_OBKEY_OBKEY_Pos (0UL) /*!< OBKEY (Bit 0) */ +#define FMC_OBKEY_OBKEY_Msk (0xffffffffUL) /*!< OBKEY (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STAT0 ========================================================= */ +#define FMC_STAT0_ENDF_Pos (5UL) /*!< ENDF (Bit 5) */ +#define FMC_STAT0_ENDF_Msk (0x20UL) /*!< ENDF (Bitfield-Mask: 0x01) */ +#define FMC_STAT0_WPERR_Pos (4UL) /*!< WPERR (Bit 4) */ +#define FMC_STAT0_WPERR_Msk (0x10UL) /*!< WPERR (Bitfield-Mask: 0x01) */ +#define FMC_STAT0_PGERR_Pos (2UL) /*!< PGERR (Bit 2) */ +#define FMC_STAT0_PGERR_Msk (0x4UL) /*!< PGERR (Bitfield-Mask: 0x01) */ +#define FMC_STAT0_BUSY_Pos (0UL) /*!< BUSY (Bit 0) */ +#define FMC_STAT0_BUSY_Msk (0x1UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +/* ========================================================= CTL0 ========================================================== */ +#define FMC_CTL0_ENDIE_Pos (12UL) /*!< ENDIE (Bit 12) */ +#define FMC_CTL0_ENDIE_Msk (0x1000UL) /*!< ENDIE (Bitfield-Mask: 0x01) */ +#define FMC_CTL0_ERRIE_Pos (10UL) /*!< ERRIE (Bit 10) */ +#define FMC_CTL0_ERRIE_Msk (0x400UL) /*!< ERRIE (Bitfield-Mask: 0x01) */ +#define FMC_CTL0_OBWEN_Pos (9UL) /*!< OBWEN (Bit 9) */ +#define FMC_CTL0_OBWEN_Msk (0x200UL) /*!< OBWEN (Bitfield-Mask: 0x01) */ +#define FMC_CTL0_LK_Pos (7UL) /*!< LK (Bit 7) */ +#define FMC_CTL0_LK_Msk (0x80UL) /*!< LK (Bitfield-Mask: 0x01) */ +#define FMC_CTL0_START_Pos (6UL) /*!< START (Bit 6) */ +#define FMC_CTL0_START_Msk (0x40UL) /*!< START (Bitfield-Mask: 0x01) */ +#define FMC_CTL0_OBER_Pos (5UL) /*!< OBER (Bit 5) */ +#define FMC_CTL0_OBER_Msk (0x20UL) /*!< OBER (Bitfield-Mask: 0x01) */ +#define FMC_CTL0_OBPG_Pos (4UL) /*!< OBPG (Bit 4) */ +#define FMC_CTL0_OBPG_Msk (0x10UL) /*!< OBPG (Bitfield-Mask: 0x01) */ +#define FMC_CTL0_MER_Pos (2UL) /*!< MER (Bit 2) */ +#define FMC_CTL0_MER_Msk (0x4UL) /*!< MER (Bitfield-Mask: 0x01) */ +#define FMC_CTL0_PER_Pos (1UL) /*!< PER (Bit 1) */ +#define FMC_CTL0_PER_Msk (0x2UL) /*!< PER (Bitfield-Mask: 0x01) */ +#define FMC_CTL0_PG_Pos (0UL) /*!< PG (Bit 0) */ +#define FMC_CTL0_PG_Msk (0x1UL) /*!< PG (Bitfield-Mask: 0x01) */ +/* ========================================================= ADDR0 ========================================================= */ +#define FMC_ADDR0_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ +#define FMC_ADDR0_ADDR_Msk (0xffffffffUL) /*!< ADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== OBSTAT ========================================================= */ +#define FMC_OBSTAT_OBERR_Pos (0UL) /*!< OBERR (Bit 0) */ +#define FMC_OBSTAT_OBERR_Msk (0x1UL) /*!< OBERR (Bitfield-Mask: 0x01) */ +#define FMC_OBSTAT_SPC_Pos (1UL) /*!< SPC (Bit 1) */ +#define FMC_OBSTAT_SPC_Msk (0x2UL) /*!< SPC (Bitfield-Mask: 0x01) */ +#define FMC_OBSTAT_USER_Pos (2UL) /*!< USER (Bit 2) */ +#define FMC_OBSTAT_USER_Msk (0x3fcUL) /*!< USER (Bitfield-Mask: 0xff) */ +#define FMC_OBSTAT_DATA_Pos (10UL) /*!< DATA (Bit 10) */ +#define FMC_OBSTAT_DATA_Msk (0x3fffc00UL) /*!< DATA (Bitfield-Mask: 0xffff) */ +/* ========================================================== WP =========================================================== */ +#define FMC_WP_WP_Pos (0UL) /*!< WP (Bit 0) */ +#define FMC_WP_WP_Msk (0xffffffffUL) /*!< WP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== PID ========================================================== */ +#define FMC_PID_PID_Pos (0UL) /*!< PID (Bit 0) */ +#define FMC_PID_PID_Msk (0xffffffffUL) /*!< PID (Bitfield-Mask: 0xffffffff) */ + + +/* =========================================================================================================================== */ +/* ================ FWDGT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CTL ========================================================== */ +#define FWDGT_CTL_CMD_Pos (0UL) /*!< CMD (Bit 0) */ +#define FWDGT_CTL_CMD_Msk (0xffffUL) /*!< CMD (Bitfield-Mask: 0xffff) */ +/* ========================================================== PSC ========================================================== */ +#define FWDGT_PSC_PSC_Pos (0UL) /*!< PSC (Bit 0) */ +#define FWDGT_PSC_PSC_Msk (0x7UL) /*!< PSC (Bitfield-Mask: 0x07) */ +/* ========================================================== RLD ========================================================== */ +#define FWDGT_RLD_RLD_Pos (0UL) /*!< RLD (Bit 0) */ +#define FWDGT_RLD_RLD_Msk (0xfffUL) /*!< RLD (Bitfield-Mask: 0xfff) */ +/* ========================================================= STAT ========================================================== */ +#define FWDGT_STAT_PUD_Pos (0UL) /*!< PUD (Bit 0) */ +#define FWDGT_STAT_PUD_Msk (0x1UL) /*!< PUD (Bitfield-Mask: 0x01) */ +#define FWDGT_STAT_RUD_Pos (1UL) /*!< RUD (Bit 1) */ +#define FWDGT_STAT_RUD_Msk (0x2UL) /*!< RUD (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ GPIOA ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTL0 ========================================================== */ +#define GPIO_CTL0_CTL7_Pos (30UL) /*!< CTL7 (Bit 30) */ +#define GPIO_CTL0_CTL7_Msk (0xc0000000UL) /*!< CTL7 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL0_MD7_Pos (28UL) /*!< MD7 (Bit 28) */ +#define GPIO_CTL0_MD7_Msk (0x30000000UL) /*!< MD7 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL0_CTL6_Pos (26UL) /*!< CTL6 (Bit 26) */ +#define GPIO_CTL0_CTL6_Msk (0xc000000UL) /*!< CTL6 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL0_MD6_Pos (24UL) /*!< MD6 (Bit 24) */ +#define GPIO_CTL0_MD6_Msk (0x3000000UL) /*!< MD6 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL0_CTL5_Pos (22UL) /*!< CTL5 (Bit 22) */ +#define GPIO_CTL0_CTL5_Msk (0xc00000UL) /*!< CTL5 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL0_MD5_Pos (20UL) /*!< MD5 (Bit 20) */ +#define GPIO_CTL0_MD5_Msk (0x300000UL) /*!< MD5 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL0_CTL4_Pos (18UL) /*!< CTL4 (Bit 18) */ +#define GPIO_CTL0_CTL4_Msk (0xc0000UL) /*!< CTL4 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL0_MD4_Pos (16UL) /*!< MD4 (Bit 16) */ +#define GPIO_CTL0_MD4_Msk (0x30000UL) /*!< MD4 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL0_CTL3_Pos (14UL) /*!< CTL3 (Bit 14) */ +#define GPIO_CTL0_CTL3_Msk (0xc000UL) /*!< CTL3 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL0_MD3_Pos (12UL) /*!< MD3 (Bit 12) */ +#define GPIO_CTL0_MD3_Msk (0x3000UL) /*!< MD3 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL0_CTL2_Pos (10UL) /*!< CTL2 (Bit 10) */ +#define GPIO_CTL0_CTL2_Msk (0xc00UL) /*!< CTL2 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL0_MD2_Pos (8UL) /*!< MD2 (Bit 8) */ +#define GPIO_CTL0_MD2_Msk (0x300UL) /*!< MD2 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL0_CTL1_Pos (6UL) /*!< CTL1 (Bit 6) */ +#define GPIO_CTL0_CTL1_Msk (0xc0UL) /*!< CTL1 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL0_MD1_Pos (4UL) /*!< MD1 (Bit 4) */ +#define GPIO_CTL0_MD1_Msk (0x30UL) /*!< MD1 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL0_CTL0_Pos (2UL) /*!< CTL0 (Bit 2) */ +#define GPIO_CTL0_CTL0_Msk (0xcUL) /*!< CTL0 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL0_MD0_Pos (0UL) /*!< MD0 (Bit 0) */ +#define GPIO_CTL0_MD0_Msk (0x3UL) /*!< MD0 (Bitfield-Mask: 0x03) */ +/* ========================================================= CTL1 ========================================================== */ +#define GPIO_CTL1_CTL15_Pos (30UL) /*!< CTL15 (Bit 30) */ +#define GPIO_CTL1_CTL15_Msk (0xc0000000UL) /*!< CTL15 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL1_MD15_Pos (28UL) /*!< MD15 (Bit 28) */ +#define GPIO_CTL1_MD15_Msk (0x30000000UL) /*!< MD15 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL1_CTL14_Pos (26UL) /*!< CTL14 (Bit 26) */ +#define GPIO_CTL1_CTL14_Msk (0xc000000UL) /*!< CTL14 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL1_MD14_Pos (24UL) /*!< MD14 (Bit 24) */ +#define GPIO_CTL1_MD14_Msk (0x3000000UL) /*!< MD14 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL1_CTL13_Pos (22UL) /*!< CTL13 (Bit 22) */ +#define GPIO_CTL1_CTL13_Msk (0xc00000UL) /*!< CTL13 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL1_MD13_Pos (20UL) /*!< MD13 (Bit 20) */ +#define GPIO_CTL1_MD13_Msk (0x300000UL) /*!< MD13 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL1_CTL12_Pos (18UL) /*!< CTL12 (Bit 18) */ +#define GPIO_CTL1_CTL12_Msk (0xc0000UL) /*!< CTL12 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL1_MD12_Pos (16UL) /*!< MD12 (Bit 16) */ +#define GPIO_CTL1_MD12_Msk (0x30000UL) /*!< MD12 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL1_CTL11_Pos (14UL) /*!< CTL11 (Bit 14) */ +#define GPIO_CTL1_CTL11_Msk (0xc000UL) /*!< CTL11 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL1_MD11_Pos (12UL) /*!< MD11 (Bit 12) */ +#define GPIO_CTL1_MD11_Msk (0x3000UL) /*!< MD11 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL1_CTL10_Pos (10UL) /*!< CTL10 (Bit 10) */ +#define GPIO_CTL1_CTL10_Msk (0xc00UL) /*!< CTL10 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL1_MD10_Pos (8UL) /*!< MD10 (Bit 8) */ +#define GPIO_CTL1_MD10_Msk (0x300UL) /*!< MD10 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL1_CTL9_Pos (6UL) /*!< CTL9 (Bit 6) */ +#define GPIO_CTL1_CTL9_Msk (0xc0UL) /*!< CTL9 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL1_MD9_Pos (4UL) /*!< MD9 (Bit 4) */ +#define GPIO_CTL1_MD9_Msk (0x30UL) /*!< MD9 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL1_CTL8_Pos (2UL) /*!< CTL8 (Bit 2) */ +#define GPIO_CTL1_CTL8_Msk (0xcUL) /*!< CTL8 (Bitfield-Mask: 0x03) */ +#define GPIO_CTL1_MD8_Pos (0UL) /*!< MD8 (Bit 0) */ +#define GPIO_CTL1_MD8_Msk (0x3UL) /*!< MD8 (Bitfield-Mask: 0x03) */ +/* ========================================================= ISTAT ========================================================= */ +#define GPIO_ISTAT_ISTAT15_Pos (15UL) /*!< ISTAT15 (Bit 15) */ +#define GPIO_ISTAT_ISTAT15_Msk (0x8000UL) /*!< ISTAT15 (Bitfield-Mask: 0x01) */ +#define GPIO_ISTAT_ISTAT14_Pos (14UL) /*!< ISTAT14 (Bit 14) */ +#define GPIO_ISTAT_ISTAT14_Msk (0x4000UL) /*!< ISTAT14 (Bitfield-Mask: 0x01) */ +#define GPIO_ISTAT_ISTAT13_Pos (13UL) /*!< ISTAT13 (Bit 13) */ +#define GPIO_ISTAT_ISTAT13_Msk (0x2000UL) /*!< ISTAT13 (Bitfield-Mask: 0x01) */ +#define GPIO_ISTAT_ISTAT12_Pos (12UL) /*!< ISTAT12 (Bit 12) */ +#define GPIO_ISTAT_ISTAT12_Msk (0x1000UL) /*!< ISTAT12 (Bitfield-Mask: 0x01) */ +#define GPIO_ISTAT_ISTAT11_Pos (11UL) /*!< ISTAT11 (Bit 11) */ +#define GPIO_ISTAT_ISTAT11_Msk (0x800UL) /*!< ISTAT11 (Bitfield-Mask: 0x01) */ +#define GPIO_ISTAT_ISTAT10_Pos (10UL) /*!< ISTAT10 (Bit 10) */ +#define GPIO_ISTAT_ISTAT10_Msk (0x400UL) /*!< ISTAT10 (Bitfield-Mask: 0x01) */ +#define GPIO_ISTAT_ISTAT9_Pos (9UL) /*!< ISTAT9 (Bit 9) */ +#define GPIO_ISTAT_ISTAT9_Msk (0x200UL) /*!< ISTAT9 (Bitfield-Mask: 0x01) */ +#define GPIO_ISTAT_ISTAT8_Pos (8UL) /*!< ISTAT8 (Bit 8) */ +#define GPIO_ISTAT_ISTAT8_Msk (0x100UL) /*!< ISTAT8 (Bitfield-Mask: 0x01) */ +#define GPIO_ISTAT_ISTAT7_Pos (7UL) /*!< ISTAT7 (Bit 7) */ +#define GPIO_ISTAT_ISTAT7_Msk (0x80UL) /*!< ISTAT7 (Bitfield-Mask: 0x01) */ +#define GPIO_ISTAT_ISTAT6_Pos (6UL) /*!< ISTAT6 (Bit 6) */ +#define GPIO_ISTAT_ISTAT6_Msk (0x40UL) /*!< ISTAT6 (Bitfield-Mask: 0x01) */ +#define GPIO_ISTAT_ISTAT5_Pos (5UL) /*!< ISTAT5 (Bit 5) */ +#define GPIO_ISTAT_ISTAT5_Msk (0x20UL) /*!< ISTAT5 (Bitfield-Mask: 0x01) */ +#define GPIO_ISTAT_ISTAT4_Pos (4UL) /*!< ISTAT4 (Bit 4) */ +#define GPIO_ISTAT_ISTAT4_Msk (0x10UL) /*!< ISTAT4 (Bitfield-Mask: 0x01) */ +#define GPIO_ISTAT_ISTAT3_Pos (3UL) /*!< ISTAT3 (Bit 3) */ +#define GPIO_ISTAT_ISTAT3_Msk (0x8UL) /*!< ISTAT3 (Bitfield-Mask: 0x01) */ +#define GPIO_ISTAT_ISTAT2_Pos (2UL) /*!< ISTAT2 (Bit 2) */ +#define GPIO_ISTAT_ISTAT2_Msk (0x4UL) /*!< ISTAT2 (Bitfield-Mask: 0x01) */ +#define GPIO_ISTAT_ISTAT1_Pos (1UL) /*!< ISTAT1 (Bit 1) */ +#define GPIO_ISTAT_ISTAT1_Msk (0x2UL) /*!< ISTAT1 (Bitfield-Mask: 0x01) */ +#define GPIO_ISTAT_ISTAT0_Pos (0UL) /*!< ISTAT0 (Bit 0) */ +#define GPIO_ISTAT_ISTAT0_Msk (0x1UL) /*!< ISTAT0 (Bitfield-Mask: 0x01) */ +/* ========================================================= OCTL ========================================================== */ +#define GPIO_OCTL_OCTL15_Pos (15UL) /*!< OCTL15 (Bit 15) */ +#define GPIO_OCTL_OCTL15_Msk (0x8000UL) /*!< OCTL15 (Bitfield-Mask: 0x01) */ +#define GPIO_OCTL_OCTL14_Pos (14UL) /*!< OCTL14 (Bit 14) */ +#define GPIO_OCTL_OCTL14_Msk (0x4000UL) /*!< OCTL14 (Bitfield-Mask: 0x01) */ +#define GPIO_OCTL_OCTL13_Pos (13UL) /*!< OCTL13 (Bit 13) */ +#define GPIO_OCTL_OCTL13_Msk (0x2000UL) /*!< OCTL13 (Bitfield-Mask: 0x01) */ +#define GPIO_OCTL_OCTL12_Pos (12UL) /*!< OCTL12 (Bit 12) */ +#define GPIO_OCTL_OCTL12_Msk (0x1000UL) /*!< OCTL12 (Bitfield-Mask: 0x01) */ +#define GPIO_OCTL_OCTL11_Pos (11UL) /*!< OCTL11 (Bit 11) */ +#define GPIO_OCTL_OCTL11_Msk (0x800UL) /*!< OCTL11 (Bitfield-Mask: 0x01) */ +#define GPIO_OCTL_OCTL10_Pos (10UL) /*!< OCTL10 (Bit 10) */ +#define GPIO_OCTL_OCTL10_Msk (0x400UL) /*!< OCTL10 (Bitfield-Mask: 0x01) */ +#define GPIO_OCTL_OCTL9_Pos (9UL) /*!< OCTL9 (Bit 9) */ +#define GPIO_OCTL_OCTL9_Msk (0x200UL) /*!< OCTL9 (Bitfield-Mask: 0x01) */ +#define GPIO_OCTL_OCTL8_Pos (8UL) /*!< OCTL8 (Bit 8) */ +#define GPIO_OCTL_OCTL8_Msk (0x100UL) /*!< OCTL8 (Bitfield-Mask: 0x01) */ +#define GPIO_OCTL_OCTL7_Pos (7UL) /*!< OCTL7 (Bit 7) */ +#define GPIO_OCTL_OCTL7_Msk (0x80UL) /*!< OCTL7 (Bitfield-Mask: 0x01) */ +#define GPIO_OCTL_OCTL6_Pos (6UL) /*!< OCTL6 (Bit 6) */ +#define GPIO_OCTL_OCTL6_Msk (0x40UL) /*!< OCTL6 (Bitfield-Mask: 0x01) */ +#define GPIO_OCTL_OCTL5_Pos (5UL) /*!< OCTL5 (Bit 5) */ +#define GPIO_OCTL_OCTL5_Msk (0x20UL) /*!< OCTL5 (Bitfield-Mask: 0x01) */ +#define GPIO_OCTL_OCTL4_Pos (4UL) /*!< OCTL4 (Bit 4) */ +#define GPIO_OCTL_OCTL4_Msk (0x10UL) /*!< OCTL4 (Bitfield-Mask: 0x01) */ +#define GPIO_OCTL_OCTL3_Pos (3UL) /*!< OCTL3 (Bit 3) */ +#define GPIO_OCTL_OCTL3_Msk (0x8UL) /*!< OCTL3 (Bitfield-Mask: 0x01) */ +#define GPIO_OCTL_OCTL2_Pos (2UL) /*!< OCTL2 (Bit 2) */ +#define GPIO_OCTL_OCTL2_Msk (0x4UL) /*!< OCTL2 (Bitfield-Mask: 0x01) */ +#define GPIO_OCTL_OCTL1_Pos (1UL) /*!< OCTL1 (Bit 1) */ +#define GPIO_OCTL_OCTL1_Msk (0x2UL) /*!< OCTL1 (Bitfield-Mask: 0x01) */ +#define GPIO_OCTL_OCTL0_Pos (0UL) /*!< OCTL0 (Bit 0) */ +#define GPIO_OCTL_OCTL0_Msk (0x1UL) /*!< OCTL0 (Bitfield-Mask: 0x01) */ +/* ========================================================== BOP ========================================================== */ +#define GPIO_BOP_CR15_Pos (31UL) /*!< CR15 (Bit 31) */ +#define GPIO_BOP_CR15_Msk (0x80000000UL) /*!< CR15 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_CR14_Pos (30UL) /*!< CR14 (Bit 30) */ +#define GPIO_BOP_CR14_Msk (0x40000000UL) /*!< CR14 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_CR13_Pos (29UL) /*!< CR13 (Bit 29) */ +#define GPIO_BOP_CR13_Msk (0x20000000UL) /*!< CR13 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_CR12_Pos (28UL) /*!< CR12 (Bit 28) */ +#define GPIO_BOP_CR12_Msk (0x10000000UL) /*!< CR12 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_CR11_Pos (27UL) /*!< CR11 (Bit 27) */ +#define GPIO_BOP_CR11_Msk (0x8000000UL) /*!< CR11 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_CR10_Pos (26UL) /*!< CR10 (Bit 26) */ +#define GPIO_BOP_CR10_Msk (0x4000000UL) /*!< CR10 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_CR9_Pos (25UL) /*!< CR9 (Bit 25) */ +#define GPIO_BOP_CR9_Msk (0x2000000UL) /*!< CR9 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_CR8_Pos (24UL) /*!< CR8 (Bit 24) */ +#define GPIO_BOP_CR8_Msk (0x1000000UL) /*!< CR8 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_CR7_Pos (23UL) /*!< CR7 (Bit 23) */ +#define GPIO_BOP_CR7_Msk (0x800000UL) /*!< CR7 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_CR6_Pos (22UL) /*!< CR6 (Bit 22) */ +#define GPIO_BOP_CR6_Msk (0x400000UL) /*!< CR6 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_CR5_Pos (21UL) /*!< CR5 (Bit 21) */ +#define GPIO_BOP_CR5_Msk (0x200000UL) /*!< CR5 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_CR4_Pos (20UL) /*!< CR4 (Bit 20) */ +#define GPIO_BOP_CR4_Msk (0x100000UL) /*!< CR4 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_CR3_Pos (19UL) /*!< CR3 (Bit 19) */ +#define GPIO_BOP_CR3_Msk (0x80000UL) /*!< CR3 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_CR2_Pos (18UL) /*!< CR2 (Bit 18) */ +#define GPIO_BOP_CR2_Msk (0x40000UL) /*!< CR2 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_CR1_Pos (17UL) /*!< CR1 (Bit 17) */ +#define GPIO_BOP_CR1_Msk (0x20000UL) /*!< CR1 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_CR0_Pos (16UL) /*!< CR0 (Bit 16) */ +#define GPIO_BOP_CR0_Msk (0x10000UL) /*!< CR0 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_BOP15_Pos (15UL) /*!< BOP15 (Bit 15) */ +#define GPIO_BOP_BOP15_Msk (0x8000UL) /*!< BOP15 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_BOP14_Pos (14UL) /*!< BOP14 (Bit 14) */ +#define GPIO_BOP_BOP14_Msk (0x4000UL) /*!< BOP14 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_BOP13_Pos (13UL) /*!< BOP13 (Bit 13) */ +#define GPIO_BOP_BOP13_Msk (0x2000UL) /*!< BOP13 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_BOP12_Pos (12UL) /*!< BOP12 (Bit 12) */ +#define GPIO_BOP_BOP12_Msk (0x1000UL) /*!< BOP12 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_BOP11_Pos (11UL) /*!< BOP11 (Bit 11) */ +#define GPIO_BOP_BOP11_Msk (0x800UL) /*!< BOP11 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_BOP10_Pos (10UL) /*!< BOP10 (Bit 10) */ +#define GPIO_BOP_BOP10_Msk (0x400UL) /*!< BOP10 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_BOP9_Pos (9UL) /*!< BOP9 (Bit 9) */ +#define GPIO_BOP_BOP9_Msk (0x200UL) /*!< BOP9 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_BOP8_Pos (8UL) /*!< BOP8 (Bit 8) */ +#define GPIO_BOP_BOP8_Msk (0x100UL) /*!< BOP8 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_BOP7_Pos (7UL) /*!< BOP7 (Bit 7) */ +#define GPIO_BOP_BOP7_Msk (0x80UL) /*!< BOP7 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_BOP6_Pos (6UL) /*!< BOP6 (Bit 6) */ +#define GPIO_BOP_BOP6_Msk (0x40UL) /*!< BOP6 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_BOP5_Pos (5UL) /*!< BOP5 (Bit 5) */ +#define GPIO_BOP_BOP5_Msk (0x20UL) /*!< BOP5 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_BOP4_Pos (4UL) /*!< BOP4 (Bit 4) */ +#define GPIO_BOP_BOP4_Msk (0x10UL) /*!< BOP4 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_BOP3_Pos (3UL) /*!< BOP3 (Bit 3) */ +#define GPIO_BOP_BOP3_Msk (0x8UL) /*!< BOP3 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_BOP2_Pos (2UL) /*!< BOP2 (Bit 2) */ +#define GPIO_BOP_BOP2_Msk (0x4UL) /*!< BOP2 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_BOP1_Pos (1UL) /*!< BOP1 (Bit 1) */ +#define GPIO_BOP_BOP1_Msk (0x2UL) /*!< BOP1 (Bitfield-Mask: 0x01) */ +#define GPIO_BOP_BOP0_Pos (0UL) /*!< BOP0 (Bit 0) */ +#define GPIO_BOP_BOP0_Msk (0x1UL) /*!< BOP0 (Bitfield-Mask: 0x01) */ +/* ========================================================== BC =========================================================== */ +#define GPIO_BC_CR15_Pos (15UL) /*!< CR15 (Bit 15) */ +#define GPIO_BC_CR15_Msk (0x8000UL) /*!< CR15 (Bitfield-Mask: 0x01) */ +#define GPIO_BC_CR14_Pos (14UL) /*!< CR14 (Bit 14) */ +#define GPIO_BC_CR14_Msk (0x4000UL) /*!< CR14 (Bitfield-Mask: 0x01) */ +#define GPIO_BC_CR13_Pos (13UL) /*!< CR13 (Bit 13) */ +#define GPIO_BC_CR13_Msk (0x2000UL) /*!< CR13 (Bitfield-Mask: 0x01) */ +#define GPIO_BC_CR12_Pos (12UL) /*!< CR12 (Bit 12) */ +#define GPIO_BC_CR12_Msk (0x1000UL) /*!< CR12 (Bitfield-Mask: 0x01) */ +#define GPIO_BC_CR11_Pos (11UL) /*!< CR11 (Bit 11) */ +#define GPIO_BC_CR11_Msk (0x800UL) /*!< CR11 (Bitfield-Mask: 0x01) */ +#define GPIO_BC_CR10_Pos (10UL) /*!< CR10 (Bit 10) */ +#define GPIO_BC_CR10_Msk (0x400UL) /*!< CR10 (Bitfield-Mask: 0x01) */ +#define GPIO_BC_CR9_Pos (9UL) /*!< CR9 (Bit 9) */ +#define GPIO_BC_CR9_Msk (0x200UL) /*!< CR9 (Bitfield-Mask: 0x01) */ +#define GPIO_BC_CR8_Pos (8UL) /*!< CR8 (Bit 8) */ +#define GPIO_BC_CR8_Msk (0x100UL) /*!< CR8 (Bitfield-Mask: 0x01) */ +#define GPIO_BC_CR7_Pos (7UL) /*!< CR7 (Bit 7) */ +#define GPIO_BC_CR7_Msk (0x80UL) /*!< CR7 (Bitfield-Mask: 0x01) */ +#define GPIO_BC_CR6_Pos (6UL) /*!< CR6 (Bit 6) */ +#define GPIO_BC_CR6_Msk (0x40UL) /*!< CR6 (Bitfield-Mask: 0x01) */ +#define GPIO_BC_CR5_Pos (5UL) /*!< CR5 (Bit 5) */ +#define GPIO_BC_CR5_Msk (0x20UL) /*!< CR5 (Bitfield-Mask: 0x01) */ +#define GPIO_BC_CR4_Pos (4UL) /*!< CR4 (Bit 4) */ +#define GPIO_BC_CR4_Msk (0x10UL) /*!< CR4 (Bitfield-Mask: 0x01) */ +#define GPIO_BC_CR3_Pos (3UL) /*!< CR3 (Bit 3) */ +#define GPIO_BC_CR3_Msk (0x8UL) /*!< CR3 (Bitfield-Mask: 0x01) */ +#define GPIO_BC_CR2_Pos (2UL) /*!< CR2 (Bit 2) */ +#define GPIO_BC_CR2_Msk (0x4UL) /*!< CR2 (Bitfield-Mask: 0x01) */ +#define GPIO_BC_CR1_Pos (1UL) /*!< CR1 (Bit 1) */ +#define GPIO_BC_CR1_Msk (0x2UL) /*!< CR1 (Bitfield-Mask: 0x01) */ +#define GPIO_BC_CR0_Pos (0UL) /*!< CR0 (Bit 0) */ +#define GPIO_BC_CR0_Msk (0x1UL) /*!< CR0 (Bitfield-Mask: 0x01) */ +/* ========================================================= LOCK ========================================================== */ +#define GPIO_LOCK_LKK_Pos (16UL) /*!< LKK (Bit 16) */ +#define GPIO_LOCK_LKK_Msk (0x10000UL) /*!< LKK (Bitfield-Mask: 0x01) */ +#define GPIO_LOCK_LK15_Pos (15UL) /*!< LK15 (Bit 15) */ +#define GPIO_LOCK_LK15_Msk (0x8000UL) /*!< LK15 (Bitfield-Mask: 0x01) */ +#define GPIO_LOCK_LK14_Pos (14UL) /*!< LK14 (Bit 14) */ +#define GPIO_LOCK_LK14_Msk (0x4000UL) /*!< LK14 (Bitfield-Mask: 0x01) */ +#define GPIO_LOCK_LK13_Pos (13UL) /*!< LK13 (Bit 13) */ +#define GPIO_LOCK_LK13_Msk (0x2000UL) /*!< LK13 (Bitfield-Mask: 0x01) */ +#define GPIO_LOCK_LK12_Pos (12UL) /*!< LK12 (Bit 12) */ +#define GPIO_LOCK_LK12_Msk (0x1000UL) /*!< LK12 (Bitfield-Mask: 0x01) */ +#define GPIO_LOCK_LK11_Pos (11UL) /*!< LK11 (Bit 11) */ +#define GPIO_LOCK_LK11_Msk (0x800UL) /*!< LK11 (Bitfield-Mask: 0x01) */ +#define GPIO_LOCK_LK10_Pos (10UL) /*!< LK10 (Bit 10) */ +#define GPIO_LOCK_LK10_Msk (0x400UL) /*!< LK10 (Bitfield-Mask: 0x01) */ +#define GPIO_LOCK_LK9_Pos (9UL) /*!< LK9 (Bit 9) */ +#define GPIO_LOCK_LK9_Msk (0x200UL) /*!< LK9 (Bitfield-Mask: 0x01) */ +#define GPIO_LOCK_LK8_Pos (8UL) /*!< LK8 (Bit 8) */ +#define GPIO_LOCK_LK8_Msk (0x100UL) /*!< LK8 (Bitfield-Mask: 0x01) */ +#define GPIO_LOCK_LK7_Pos (7UL) /*!< LK7 (Bit 7) */ +#define GPIO_LOCK_LK7_Msk (0x80UL) /*!< LK7 (Bitfield-Mask: 0x01) */ +#define GPIO_LOCK_LK6_Pos (6UL) /*!< LK6 (Bit 6) */ +#define GPIO_LOCK_LK6_Msk (0x40UL) /*!< LK6 (Bitfield-Mask: 0x01) */ +#define GPIO_LOCK_LK5_Pos (5UL) /*!< LK5 (Bit 5) */ +#define GPIO_LOCK_LK5_Msk (0x20UL) /*!< LK5 (Bitfield-Mask: 0x01) */ +#define GPIO_LOCK_LK4_Pos (4UL) /*!< LK4 (Bit 4) */ +#define GPIO_LOCK_LK4_Msk (0x10UL) /*!< LK4 (Bitfield-Mask: 0x01) */ +#define GPIO_LOCK_LK3_Pos (3UL) /*!< LK3 (Bit 3) */ +#define GPIO_LOCK_LK3_Msk (0x8UL) /*!< LK3 (Bitfield-Mask: 0x01) */ +#define GPIO_LOCK_LK2_Pos (2UL) /*!< LK2 (Bit 2) */ +#define GPIO_LOCK_LK2_Msk (0x4UL) /*!< LK2 (Bitfield-Mask: 0x01) */ +#define GPIO_LOCK_LK1_Pos (1UL) /*!< LK1 (Bit 1) */ +#define GPIO_LOCK_LK1_Msk (0x2UL) /*!< LK1 (Bitfield-Mask: 0x01) */ +#define GPIO_LOCK_LK0_Pos (0UL) /*!< LK0 (Bit 0) */ +#define GPIO_LOCK_LK0_Msk (0x1UL) /*!< LK0 (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ I2C0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTL0 ========================================================== */ +#define I2C_CTL0_SRESET_Pos (15UL) /*!< SRESET (Bit 15) */ +#define I2C_CTL0_SRESET_Msk (0x8000UL) /*!< SRESET (Bitfield-Mask: 0x01) */ +#define I2C_CTL0_SALT_Pos (13UL) /*!< SALT (Bit 13) */ +#define I2C_CTL0_SALT_Msk (0x2000UL) /*!< SALT (Bitfield-Mask: 0x01) */ +#define I2C_CTL0_PECTRANS_Pos (12UL) /*!< PECTRANS (Bit 12) */ +#define I2C_CTL0_PECTRANS_Msk (0x1000UL) /*!< PECTRANS (Bitfield-Mask: 0x01) */ +#define I2C_CTL0_POAP_Pos (11UL) /*!< POAP (Bit 11) */ +#define I2C_CTL0_POAP_Msk (0x800UL) /*!< POAP (Bitfield-Mask: 0x01) */ +#define I2C_CTL0_ACKEN_Pos (10UL) /*!< ACKEN (Bit 10) */ +#define I2C_CTL0_ACKEN_Msk (0x400UL) /*!< ACKEN (Bitfield-Mask: 0x01) */ +#define I2C_CTL0_STOP_Pos (9UL) /*!< STOP (Bit 9) */ +#define I2C_CTL0_STOP_Msk (0x200UL) /*!< STOP (Bitfield-Mask: 0x01) */ +#define I2C_CTL0_START_Pos (8UL) /*!< START (Bit 8) */ +#define I2C_CTL0_START_Msk (0x100UL) /*!< START (Bitfield-Mask: 0x01) */ +#define I2C_CTL0_SS_Pos (7UL) /*!< SS (Bit 7) */ +#define I2C_CTL0_SS_Msk (0x80UL) /*!< SS (Bitfield-Mask: 0x01) */ +#define I2C_CTL0_GCEN_Pos (6UL) /*!< GCEN (Bit 6) */ +#define I2C_CTL0_GCEN_Msk (0x40UL) /*!< GCEN (Bitfield-Mask: 0x01) */ +#define I2C_CTL0_PECEN_Pos (5UL) /*!< PECEN (Bit 5) */ +#define I2C_CTL0_PECEN_Msk (0x20UL) /*!< PECEN (Bitfield-Mask: 0x01) */ +#define I2C_CTL0_ARPEN_Pos (4UL) /*!< ARPEN (Bit 4) */ +#define I2C_CTL0_ARPEN_Msk (0x10UL) /*!< ARPEN (Bitfield-Mask: 0x01) */ +#define I2C_CTL0_SMBSEL_Pos (3UL) /*!< SMBSEL (Bit 3) */ +#define I2C_CTL0_SMBSEL_Msk (0x8UL) /*!< SMBSEL (Bitfield-Mask: 0x01) */ +#define I2C_CTL0_SMBEN_Pos (1UL) /*!< SMBEN (Bit 1) */ +#define I2C_CTL0_SMBEN_Msk (0x2UL) /*!< SMBEN (Bitfield-Mask: 0x01) */ +#define I2C_CTL0_I2CEN_Pos (0UL) /*!< I2CEN (Bit 0) */ +#define I2C_CTL0_I2CEN_Msk (0x1UL) /*!< I2CEN (Bitfield-Mask: 0x01) */ +/* ========================================================= CTL1 ========================================================== */ +#define I2C_CTL1_DMALST_Pos (12UL) /*!< DMALST (Bit 12) */ +#define I2C_CTL1_DMALST_Msk (0x1000UL) /*!< DMALST (Bitfield-Mask: 0x01) */ +#define I2C_CTL1_DMAON_Pos (11UL) /*!< DMAON (Bit 11) */ +#define I2C_CTL1_DMAON_Msk (0x800UL) /*!< DMAON (Bitfield-Mask: 0x01) */ +#define I2C_CTL1_BUFIE_Pos (10UL) /*!< BUFIE (Bit 10) */ +#define I2C_CTL1_BUFIE_Msk (0x400UL) /*!< BUFIE (Bitfield-Mask: 0x01) */ +#define I2C_CTL1_EVIE_Pos (9UL) /*!< EVIE (Bit 9) */ +#define I2C_CTL1_EVIE_Msk (0x200UL) /*!< EVIE (Bitfield-Mask: 0x01) */ +#define I2C_CTL1_ERRIE_Pos (8UL) /*!< ERRIE (Bit 8) */ +#define I2C_CTL1_ERRIE_Msk (0x100UL) /*!< ERRIE (Bitfield-Mask: 0x01) */ +#define I2C_CTL1_I2CCLK_Pos (0UL) /*!< I2CCLK (Bit 0) */ +#define I2C_CTL1_I2CCLK_Msk (0x3fUL) /*!< I2CCLK (Bitfield-Mask: 0x3f) */ +/* ======================================================== SADDR0 ========================================================= */ +#define I2C_SADDR0_ADDFORMAT_Pos (15UL) /*!< ADDFORMAT (Bit 15) */ +#define I2C_SADDR0_ADDFORMAT_Msk (0x8000UL) /*!< ADDFORMAT (Bitfield-Mask: 0x01) */ +#define I2C_SADDR0_ADDRESS9_8_Pos (8UL) /*!< ADDRESS9_8 (Bit 8) */ +#define I2C_SADDR0_ADDRESS9_8_Msk (0x300UL) /*!< ADDRESS9_8 (Bitfield-Mask: 0x03) */ +#define I2C_SADDR0_ADDRESS7_1_Pos (1UL) /*!< ADDRESS7_1 (Bit 1) */ +#define I2C_SADDR0_ADDRESS7_1_Msk (0xfeUL) /*!< ADDRESS7_1 (Bitfield-Mask: 0x7f) */ +#define I2C_SADDR0_ADDRESS0_Pos (0UL) /*!< ADDRESS0 (Bit 0) */ +#define I2C_SADDR0_ADDRESS0_Msk (0x1UL) /*!< ADDRESS0 (Bitfield-Mask: 0x01) */ +/* ======================================================== SADDR1 ========================================================= */ +#define I2C_SADDR1_ADDRESS2_Pos (1UL) /*!< ADDRESS2 (Bit 1) */ +#define I2C_SADDR1_ADDRESS2_Msk (0xfeUL) /*!< ADDRESS2 (Bitfield-Mask: 0x7f) */ +#define I2C_SADDR1_DUADEN_Pos (0UL) /*!< DUADEN (Bit 0) */ +#define I2C_SADDR1_DUADEN_Msk (0x1UL) /*!< DUADEN (Bitfield-Mask: 0x01) */ +/* ========================================================= DATA ========================================================== */ +#define I2C_DATA_TRB_Pos (0UL) /*!< TRB (Bit 0) */ +#define I2C_DATA_TRB_Msk (0xffUL) /*!< TRB (Bitfield-Mask: 0xff) */ +/* ========================================================= STAT0 ========================================================= */ +#define I2C_STAT0_SMBALT_Pos (15UL) /*!< SMBALT (Bit 15) */ +#define I2C_STAT0_SMBALT_Msk (0x8000UL) /*!< SMBALT (Bitfield-Mask: 0x01) */ +#define I2C_STAT0_SMBTO_Pos (14UL) /*!< SMBTO (Bit 14) */ +#define I2C_STAT0_SMBTO_Msk (0x4000UL) /*!< SMBTO (Bitfield-Mask: 0x01) */ +#define I2C_STAT0_PECERR_Pos (12UL) /*!< PECERR (Bit 12) */ +#define I2C_STAT0_PECERR_Msk (0x1000UL) /*!< PECERR (Bitfield-Mask: 0x01) */ +#define I2C_STAT0_OUERR_Pos (11UL) /*!< OUERR (Bit 11) */ +#define I2C_STAT0_OUERR_Msk (0x800UL) /*!< OUERR (Bitfield-Mask: 0x01) */ +#define I2C_STAT0_AERR_Pos (10UL) /*!< AERR (Bit 10) */ +#define I2C_STAT0_AERR_Msk (0x400UL) /*!< AERR (Bitfield-Mask: 0x01) */ +#define I2C_STAT0_LOSTARB_Pos (9UL) /*!< LOSTARB (Bit 9) */ +#define I2C_STAT0_LOSTARB_Msk (0x200UL) /*!< LOSTARB (Bitfield-Mask: 0x01) */ +#define I2C_STAT0_BERR_Pos (8UL) /*!< BERR (Bit 8) */ +#define I2C_STAT0_BERR_Msk (0x100UL) /*!< BERR (Bitfield-Mask: 0x01) */ +#define I2C_STAT0_TBE_Pos (7UL) /*!< TBE (Bit 7) */ +#define I2C_STAT0_TBE_Msk (0x80UL) /*!< TBE (Bitfield-Mask: 0x01) */ +#define I2C_STAT0_RBNE_Pos (6UL) /*!< RBNE (Bit 6) */ +#define I2C_STAT0_RBNE_Msk (0x40UL) /*!< RBNE (Bitfield-Mask: 0x01) */ +#define I2C_STAT0_STPDET_Pos (4UL) /*!< STPDET (Bit 4) */ +#define I2C_STAT0_STPDET_Msk (0x10UL) /*!< STPDET (Bitfield-Mask: 0x01) */ +#define I2C_STAT0_ADD10SEND_Pos (3UL) /*!< ADD10SEND (Bit 3) */ +#define I2C_STAT0_ADD10SEND_Msk (0x8UL) /*!< ADD10SEND (Bitfield-Mask: 0x01) */ +#define I2C_STAT0_BTC_Pos (2UL) /*!< BTC (Bit 2) */ +#define I2C_STAT0_BTC_Msk (0x4UL) /*!< BTC (Bitfield-Mask: 0x01) */ +#define I2C_STAT0_ADDSEND_Pos (1UL) /*!< ADDSEND (Bit 1) */ +#define I2C_STAT0_ADDSEND_Msk (0x2UL) /*!< ADDSEND (Bitfield-Mask: 0x01) */ +#define I2C_STAT0_SBSEND_Pos (0UL) /*!< SBSEND (Bit 0) */ +#define I2C_STAT0_SBSEND_Msk (0x1UL) /*!< SBSEND (Bitfield-Mask: 0x01) */ +/* ========================================================= STAT1 ========================================================= */ +#define I2C_STAT1_PECV_Pos (8UL) /*!< PECV (Bit 8) */ +#define I2C_STAT1_PECV_Msk (0xff00UL) /*!< PECV (Bitfield-Mask: 0xff) */ +#define I2C_STAT1_DUMODF_Pos (7UL) /*!< DUMODF (Bit 7) */ +#define I2C_STAT1_DUMODF_Msk (0x80UL) /*!< DUMODF (Bitfield-Mask: 0x01) */ +#define I2C_STAT1_HSTSMB_Pos (6UL) /*!< HSTSMB (Bit 6) */ +#define I2C_STAT1_HSTSMB_Msk (0x40UL) /*!< HSTSMB (Bitfield-Mask: 0x01) */ +#define I2C_STAT1_DEFSMB_Pos (5UL) /*!< DEFSMB (Bit 5) */ +#define I2C_STAT1_DEFSMB_Msk (0x20UL) /*!< DEFSMB (Bitfield-Mask: 0x01) */ +#define I2C_STAT1_RXGC_Pos (4UL) /*!< RXGC (Bit 4) */ +#define I2C_STAT1_RXGC_Msk (0x10UL) /*!< RXGC (Bitfield-Mask: 0x01) */ +#define I2C_STAT1_TR_Pos (2UL) /*!< TR (Bit 2) */ +#define I2C_STAT1_TR_Msk (0x4UL) /*!< TR (Bitfield-Mask: 0x01) */ +#define I2C_STAT1_I2CBSY_Pos (1UL) /*!< I2CBSY (Bit 1) */ +#define I2C_STAT1_I2CBSY_Msk (0x2UL) /*!< I2CBSY (Bitfield-Mask: 0x01) */ +#define I2C_STAT1_MASTER_Pos (0UL) /*!< MASTER (Bit 0) */ +#define I2C_STAT1_MASTER_Msk (0x1UL) /*!< MASTER (Bitfield-Mask: 0x01) */ +/* ========================================================= CKCFG ========================================================= */ +#define I2C_CKCFG_FAST_Pos (15UL) /*!< FAST (Bit 15) */ +#define I2C_CKCFG_FAST_Msk (0x8000UL) /*!< FAST (Bitfield-Mask: 0x01) */ +#define I2C_CKCFG_DTCY_Pos (14UL) /*!< DTCY (Bit 14) */ +#define I2C_CKCFG_DTCY_Msk (0x4000UL) /*!< DTCY (Bitfield-Mask: 0x01) */ +#define I2C_CKCFG_CLKC_Pos (0UL) /*!< CLKC (Bit 0) */ +#define I2C_CKCFG_CLKC_Msk (0xfffUL) /*!< CLKC (Bitfield-Mask: 0xfff) */ +/* ========================================================== RT =========================================================== */ +#define I2C_RT_RISETIME_Pos (0UL) /*!< RISETIME (Bit 0) */ +#define I2C_RT_RISETIME_Msk (0x3fUL) /*!< RISETIME (Bitfield-Mask: 0x3f) */ + + +/* =========================================================================================================================== */ +/* ================ ECLIC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CLICCFG ======================================================== */ +#define ECLIC_CLICCFG_NLBITS_Pos (1UL) /*!< NLBITS (Bit 1) */ +#define ECLIC_CLICCFG_NLBITS_Msk (0x1eUL) /*!< NLBITS (Bitfield-Mask: 0x0f) */ +/* ======================================================= CLICINFO ======================================================== */ +#define ECLIC_CLICINFO_NUM_INTERRUPT_Pos (0UL) /*!< NUM_INTERRUPT (Bit 0) */ +#define ECLIC_CLICINFO_NUM_INTERRUPT_Msk (0x1fffUL) /*!< NUM_INTERRUPT (Bitfield-Mask: 0x1fff) */ +#define ECLIC_CLICINFO_VERSION_Pos (13UL) /*!< VERSION (Bit 13) */ +#define ECLIC_CLICINFO_VERSION_Msk (0x1fe000UL) /*!< VERSION (Bitfield-Mask: 0xff) */ +#define ECLIC_CLICINFO_CLICINTCTLBITS_Pos (21UL) /*!< CLICINTCTLBITS (Bit 21) */ +#define ECLIC_CLICINFO_CLICINTCTLBITS_Msk (0x1e00000UL) /*!< CLICINTCTLBITS (Bitfield-Mask: 0x0f) */ +/* ========================================================== MTH ========================================================== */ +#define ECLIC_MTH_MTH_Pos (0UL) /*!< MTH (Bit 0) */ +#define ECLIC_MTH_MTH_Msk (0xffUL) /*!< MTH (Bitfield-Mask: 0xff) */ +/* ====================================================== CLICINTIP_0 ====================================================== */ +#define ECLIC_CLICINTIP_0_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_0_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ====================================================== CLICINTIP_1 ====================================================== */ +#define ECLIC_CLICINTIP_1_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_1_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ====================================================== CLICINTIP_2 ====================================================== */ +#define ECLIC_CLICINTIP_2_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_2_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ====================================================== CLICINTIP_3 ====================================================== */ +#define ECLIC_CLICINTIP_3_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_3_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ====================================================== CLICINTIP_4 ====================================================== */ +#define ECLIC_CLICINTIP_4_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_4_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ====================================================== CLICINTIP_5 ====================================================== */ +#define ECLIC_CLICINTIP_5_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_5_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ====================================================== CLICINTIP_6 ====================================================== */ +#define ECLIC_CLICINTIP_6_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_6_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ====================================================== CLICINTIP_7 ====================================================== */ +#define ECLIC_CLICINTIP_7_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_7_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ====================================================== CLICINTIP_8 ====================================================== */ +#define ECLIC_CLICINTIP_8_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_8_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ====================================================== CLICINTIP_9 ====================================================== */ +#define ECLIC_CLICINTIP_9_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_9_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_10 ====================================================== */ +#define ECLIC_CLICINTIP_10_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_10_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_11 ====================================================== */ +#define ECLIC_CLICINTIP_11_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_11_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_12 ====================================================== */ +#define ECLIC_CLICINTIP_12_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_12_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_13 ====================================================== */ +#define ECLIC_CLICINTIP_13_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_13_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_14 ====================================================== */ +#define ECLIC_CLICINTIP_14_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_14_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_15 ====================================================== */ +#define ECLIC_CLICINTIP_15_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_15_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_16 ====================================================== */ +#define ECLIC_CLICINTIP_16_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_16_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_17 ====================================================== */ +#define ECLIC_CLICINTIP_17_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_17_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_18 ====================================================== */ +#define ECLIC_CLICINTIP_18_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_18_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_19 ====================================================== */ +#define ECLIC_CLICINTIP_19_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_19_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_20 ====================================================== */ +#define ECLIC_CLICINTIP_20_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_20_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_21 ====================================================== */ +#define ECLIC_CLICINTIP_21_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_21_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_22 ====================================================== */ +#define ECLIC_CLICINTIP_22_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_22_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_23 ====================================================== */ +#define ECLIC_CLICINTIP_23_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_23_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_24 ====================================================== */ +#define ECLIC_CLICINTIP_24_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_24_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_25 ====================================================== */ +#define ECLIC_CLICINTIP_25_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_25_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_26 ====================================================== */ +#define ECLIC_CLICINTIP_26_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_26_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_27 ====================================================== */ +#define ECLIC_CLICINTIP_27_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_27_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_28 ====================================================== */ +#define ECLIC_CLICINTIP_28_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_28_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_29 ====================================================== */ +#define ECLIC_CLICINTIP_29_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_29_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_30 ====================================================== */ +#define ECLIC_CLICINTIP_30_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_30_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_31 ====================================================== */ +#define ECLIC_CLICINTIP_31_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_31_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_32 ====================================================== */ +#define ECLIC_CLICINTIP_32_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_32_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_33 ====================================================== */ +#define ECLIC_CLICINTIP_33_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_33_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_34 ====================================================== */ +#define ECLIC_CLICINTIP_34_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_34_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_35 ====================================================== */ +#define ECLIC_CLICINTIP_35_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_35_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_36 ====================================================== */ +#define ECLIC_CLICINTIP_36_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_36_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_37 ====================================================== */ +#define ECLIC_CLICINTIP_37_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_37_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_38 ====================================================== */ +#define ECLIC_CLICINTIP_38_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_38_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_39 ====================================================== */ +#define ECLIC_CLICINTIP_39_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_39_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_40 ====================================================== */ +#define ECLIC_CLICINTIP_40_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_40_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_41 ====================================================== */ +#define ECLIC_CLICINTIP_41_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_41_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_42 ====================================================== */ +#define ECLIC_CLICINTIP_42_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_42_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_43 ====================================================== */ +#define ECLIC_CLICINTIP_43_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_43_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_44 ====================================================== */ +#define ECLIC_CLICINTIP_44_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_44_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_45 ====================================================== */ +#define ECLIC_CLICINTIP_45_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_45_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_46 ====================================================== */ +#define ECLIC_CLICINTIP_46_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_46_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_47 ====================================================== */ +#define ECLIC_CLICINTIP_47_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_47_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_48 ====================================================== */ +#define ECLIC_CLICINTIP_48_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_48_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_49 ====================================================== */ +#define ECLIC_CLICINTIP_49_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_49_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_50 ====================================================== */ +#define ECLIC_CLICINTIP_50_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_50_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_51 ====================================================== */ +#define ECLIC_CLICINTIP_51_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_51_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_52 ====================================================== */ +#define ECLIC_CLICINTIP_52_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_52_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_53 ====================================================== */ +#define ECLIC_CLICINTIP_53_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_53_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_54 ====================================================== */ +#define ECLIC_CLICINTIP_54_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_54_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_55 ====================================================== */ +#define ECLIC_CLICINTIP_55_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_55_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_56 ====================================================== */ +#define ECLIC_CLICINTIP_56_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_56_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_57 ====================================================== */ +#define ECLIC_CLICINTIP_57_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_57_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_58 ====================================================== */ +#define ECLIC_CLICINTIP_58_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_58_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_59 ====================================================== */ +#define ECLIC_CLICINTIP_59_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_59_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_60 ====================================================== */ +#define ECLIC_CLICINTIP_60_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_60_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_61 ====================================================== */ +#define ECLIC_CLICINTIP_61_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_61_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_62 ====================================================== */ +#define ECLIC_CLICINTIP_62_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_62_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_63 ====================================================== */ +#define ECLIC_CLICINTIP_63_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_63_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_64 ====================================================== */ +#define ECLIC_CLICINTIP_64_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_64_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_65 ====================================================== */ +#define ECLIC_CLICINTIP_65_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_65_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_66 ====================================================== */ +#define ECLIC_CLICINTIP_66_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_66_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_67 ====================================================== */ +#define ECLIC_CLICINTIP_67_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_67_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_68 ====================================================== */ +#define ECLIC_CLICINTIP_68_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_68_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_69 ====================================================== */ +#define ECLIC_CLICINTIP_69_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_69_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_70 ====================================================== */ +#define ECLIC_CLICINTIP_70_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_70_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_71 ====================================================== */ +#define ECLIC_CLICINTIP_71_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_71_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_72 ====================================================== */ +#define ECLIC_CLICINTIP_72_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_72_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_73 ====================================================== */ +#define ECLIC_CLICINTIP_73_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_73_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_74 ====================================================== */ +#define ECLIC_CLICINTIP_74_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_74_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_75 ====================================================== */ +#define ECLIC_CLICINTIP_75_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_75_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_76 ====================================================== */ +#define ECLIC_CLICINTIP_76_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_76_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_77 ====================================================== */ +#define ECLIC_CLICINTIP_77_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_77_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_78 ====================================================== */ +#define ECLIC_CLICINTIP_78_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_78_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_79 ====================================================== */ +#define ECLIC_CLICINTIP_79_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_79_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_80 ====================================================== */ +#define ECLIC_CLICINTIP_80_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_80_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_81 ====================================================== */ +#define ECLIC_CLICINTIP_81_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_81_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_82 ====================================================== */ +#define ECLIC_CLICINTIP_82_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_82_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_83 ====================================================== */ +#define ECLIC_CLICINTIP_83_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_83_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_84 ====================================================== */ +#define ECLIC_CLICINTIP_84_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_84_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_85 ====================================================== */ +#define ECLIC_CLICINTIP_85_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_85_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIP_86 ====================================================== */ +#define ECLIC_CLICINTIP_86_IP_Pos (0UL) /*!< IP (Bit 0) */ +#define ECLIC_CLICINTIP_86_IP_Msk (0x1UL) /*!< IP (Bitfield-Mask: 0x01) */ +/* ====================================================== CLICINTIE_0 ====================================================== */ +#define ECLIC_CLICINTIE_0_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_0_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ====================================================== CLICINTIE_1 ====================================================== */ +#define ECLIC_CLICINTIE_1_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_1_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ====================================================== CLICINTIE_2 ====================================================== */ +#define ECLIC_CLICINTIE_2_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_2_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ====================================================== CLICINTIE_3 ====================================================== */ +#define ECLIC_CLICINTIE_3_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_3_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ====================================================== CLICINTIE_4 ====================================================== */ +#define ECLIC_CLICINTIE_4_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_4_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ====================================================== CLICINTIE_5 ====================================================== */ +#define ECLIC_CLICINTIE_5_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_5_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ====================================================== CLICINTIE_6 ====================================================== */ +#define ECLIC_CLICINTIE_6_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_6_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ====================================================== CLICINTIE_7 ====================================================== */ +#define ECLIC_CLICINTIE_7_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_7_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ====================================================== CLICINTIE_8 ====================================================== */ +#define ECLIC_CLICINTIE_8_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_8_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ====================================================== CLICINTIE_9 ====================================================== */ +#define ECLIC_CLICINTIE_9_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_9_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_10 ====================================================== */ +#define ECLIC_CLICINTIE_10_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_10_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_11 ====================================================== */ +#define ECLIC_CLICINTIE_11_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_11_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_12 ====================================================== */ +#define ECLIC_CLICINTIE_12_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_12_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_13 ====================================================== */ +#define ECLIC_CLICINTIE_13_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_13_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_14 ====================================================== */ +#define ECLIC_CLICINTIE_14_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_14_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_15 ====================================================== */ +#define ECLIC_CLICINTIE_15_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_15_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_16 ====================================================== */ +#define ECLIC_CLICINTIE_16_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_16_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_17 ====================================================== */ +#define ECLIC_CLICINTIE_17_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_17_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_18 ====================================================== */ +#define ECLIC_CLICINTIE_18_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_18_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_19 ====================================================== */ +#define ECLIC_CLICINTIE_19_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_19_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_20 ====================================================== */ +#define ECLIC_CLICINTIE_20_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_20_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_21 ====================================================== */ +#define ECLIC_CLICINTIE_21_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_21_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_22 ====================================================== */ +#define ECLIC_CLICINTIE_22_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_22_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_23 ====================================================== */ +#define ECLIC_CLICINTIE_23_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_23_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_24 ====================================================== */ +#define ECLIC_CLICINTIE_24_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_24_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_25 ====================================================== */ +#define ECLIC_CLICINTIE_25_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_25_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_26 ====================================================== */ +#define ECLIC_CLICINTIE_26_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_26_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_27 ====================================================== */ +#define ECLIC_CLICINTIE_27_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_27_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_28 ====================================================== */ +#define ECLIC_CLICINTIE_28_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_28_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_29 ====================================================== */ +#define ECLIC_CLICINTIE_29_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_29_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_30 ====================================================== */ +#define ECLIC_CLICINTIE_30_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_30_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_31 ====================================================== */ +#define ECLIC_CLICINTIE_31_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_31_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_32 ====================================================== */ +#define ECLIC_CLICINTIE_32_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_32_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_33 ====================================================== */ +#define ECLIC_CLICINTIE_33_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_33_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_34 ====================================================== */ +#define ECLIC_CLICINTIE_34_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_34_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_35 ====================================================== */ +#define ECLIC_CLICINTIE_35_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_35_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_36 ====================================================== */ +#define ECLIC_CLICINTIE_36_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_36_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_37 ====================================================== */ +#define ECLIC_CLICINTIE_37_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_37_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_38 ====================================================== */ +#define ECLIC_CLICINTIE_38_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_38_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_39 ====================================================== */ +#define ECLIC_CLICINTIE_39_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_39_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_40 ====================================================== */ +#define ECLIC_CLICINTIE_40_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_40_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_41 ====================================================== */ +#define ECLIC_CLICINTIE_41_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_41_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_42 ====================================================== */ +#define ECLIC_CLICINTIE_42_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_42_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_43 ====================================================== */ +#define ECLIC_CLICINTIE_43_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_43_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_44 ====================================================== */ +#define ECLIC_CLICINTIE_44_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_44_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_45 ====================================================== */ +#define ECLIC_CLICINTIE_45_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_45_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_46 ====================================================== */ +#define ECLIC_CLICINTIE_46_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_46_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_47 ====================================================== */ +#define ECLIC_CLICINTIE_47_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_47_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_48 ====================================================== */ +#define ECLIC_CLICINTIE_48_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_48_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_49 ====================================================== */ +#define ECLIC_CLICINTIE_49_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_49_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_50 ====================================================== */ +#define ECLIC_CLICINTIE_50_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_50_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_51 ====================================================== */ +#define ECLIC_CLICINTIE_51_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_51_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_52 ====================================================== */ +#define ECLIC_CLICINTIE_52_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_52_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_53 ====================================================== */ +#define ECLIC_CLICINTIE_53_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_53_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_54 ====================================================== */ +#define ECLIC_CLICINTIE_54_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_54_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_55 ====================================================== */ +#define ECLIC_CLICINTIE_55_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_55_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_56 ====================================================== */ +#define ECLIC_CLICINTIE_56_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_56_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_57 ====================================================== */ +#define ECLIC_CLICINTIE_57_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_57_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_58 ====================================================== */ +#define ECLIC_CLICINTIE_58_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_58_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_59 ====================================================== */ +#define ECLIC_CLICINTIE_59_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_59_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_60 ====================================================== */ +#define ECLIC_CLICINTIE_60_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_60_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_61 ====================================================== */ +#define ECLIC_CLICINTIE_61_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_61_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_62 ====================================================== */ +#define ECLIC_CLICINTIE_62_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_62_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_63 ====================================================== */ +#define ECLIC_CLICINTIE_63_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_63_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_64 ====================================================== */ +#define ECLIC_CLICINTIE_64_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_64_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_65 ====================================================== */ +#define ECLIC_CLICINTIE_65_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_65_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_66 ====================================================== */ +#define ECLIC_CLICINTIE_66_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_66_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_67 ====================================================== */ +#define ECLIC_CLICINTIE_67_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_67_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_68 ====================================================== */ +#define ECLIC_CLICINTIE_68_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_68_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_69 ====================================================== */ +#define ECLIC_CLICINTIE_69_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_69_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_70 ====================================================== */ +#define ECLIC_CLICINTIE_70_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_70_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_71 ====================================================== */ +#define ECLIC_CLICINTIE_71_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_71_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_72 ====================================================== */ +#define ECLIC_CLICINTIE_72_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_72_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_73 ====================================================== */ +#define ECLIC_CLICINTIE_73_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_73_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_74 ====================================================== */ +#define ECLIC_CLICINTIE_74_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_74_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_75 ====================================================== */ +#define ECLIC_CLICINTIE_75_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_75_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_76 ====================================================== */ +#define ECLIC_CLICINTIE_76_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_76_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_77 ====================================================== */ +#define ECLIC_CLICINTIE_77_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_77_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_78 ====================================================== */ +#define ECLIC_CLICINTIE_78_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_78_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_79 ====================================================== */ +#define ECLIC_CLICINTIE_79_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_79_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_80 ====================================================== */ +#define ECLIC_CLICINTIE_80_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_80_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_81 ====================================================== */ +#define ECLIC_CLICINTIE_81_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_81_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_82 ====================================================== */ +#define ECLIC_CLICINTIE_82_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_82_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_83 ====================================================== */ +#define ECLIC_CLICINTIE_83_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_83_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_84 ====================================================== */ +#define ECLIC_CLICINTIE_84_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_84_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_85 ====================================================== */ +#define ECLIC_CLICINTIE_85_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_85_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTIE_86 ====================================================== */ +#define ECLIC_CLICINTIE_86_IE_Pos (0UL) /*!< IE (Bit 0) */ +#define ECLIC_CLICINTIE_86_IE_Msk (0x1UL) /*!< IE (Bitfield-Mask: 0x01) */ +/* ===================================================== CLICINTATTR_0 ===================================================== */ +#define ECLIC_CLICINTATTR_0_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_0_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_0_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_0_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ===================================================== CLICINTATTR_1 ===================================================== */ +#define ECLIC_CLICINTATTR_1_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_1_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_1_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_1_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ===================================================== CLICINTATTR_2 ===================================================== */ +#define ECLIC_CLICINTATTR_2_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_2_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_2_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_2_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ===================================================== CLICINTATTR_3 ===================================================== */ +#define ECLIC_CLICINTATTR_3_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_3_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_3_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_3_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ===================================================== CLICINTATTR_4 ===================================================== */ +#define ECLIC_CLICINTATTR_4_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_4_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_4_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_4_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ===================================================== CLICINTATTR_5 ===================================================== */ +#define ECLIC_CLICINTATTR_5_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_5_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_5_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_5_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ===================================================== CLICINTATTR_6 ===================================================== */ +#define ECLIC_CLICINTATTR_6_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_6_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_6_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_6_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ===================================================== CLICINTATTR_7 ===================================================== */ +#define ECLIC_CLICINTATTR_7_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_7_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_7_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_7_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ===================================================== CLICINTATTR_8 ===================================================== */ +#define ECLIC_CLICINTATTR_8_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_8_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_8_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_8_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ===================================================== CLICINTATTR_9 ===================================================== */ +#define ECLIC_CLICINTATTR_9_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_9_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_9_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_9_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_10 ===================================================== */ +#define ECLIC_CLICINTATTR_10_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_10_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_10_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_10_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_11 ===================================================== */ +#define ECLIC_CLICINTATTR_11_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_11_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_11_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_11_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_12 ===================================================== */ +#define ECLIC_CLICINTATTR_12_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_12_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_12_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_12_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_13 ===================================================== */ +#define ECLIC_CLICINTATTR_13_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_13_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_13_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_13_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_14 ===================================================== */ +#define ECLIC_CLICINTATTR_14_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_14_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_14_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_14_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_15 ===================================================== */ +#define ECLIC_CLICINTATTR_15_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_15_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_15_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_15_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_16 ===================================================== */ +#define ECLIC_CLICINTATTR_16_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_16_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_16_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_16_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_17 ===================================================== */ +#define ECLIC_CLICINTATTR_17_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_17_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_17_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_17_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_18 ===================================================== */ +#define ECLIC_CLICINTATTR_18_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_18_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_18_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_18_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_19 ===================================================== */ +#define ECLIC_CLICINTATTR_19_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_19_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_19_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_19_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_20 ===================================================== */ +#define ECLIC_CLICINTATTR_20_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_20_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_20_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_20_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_21 ===================================================== */ +#define ECLIC_CLICINTATTR_21_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_21_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_21_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_21_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_22 ===================================================== */ +#define ECLIC_CLICINTATTR_22_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_22_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_22_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_22_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_23 ===================================================== */ +#define ECLIC_CLICINTATTR_23_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_23_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_23_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_23_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_24 ===================================================== */ +#define ECLIC_CLICINTATTR_24_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_24_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_24_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_24_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_25 ===================================================== */ +#define ECLIC_CLICINTATTR_25_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_25_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_25_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_25_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_26 ===================================================== */ +#define ECLIC_CLICINTATTR_26_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_26_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_26_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_26_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_27 ===================================================== */ +#define ECLIC_CLICINTATTR_27_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_27_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_27_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_27_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_28 ===================================================== */ +#define ECLIC_CLICINTATTR_28_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_28_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_28_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_28_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_29 ===================================================== */ +#define ECLIC_CLICINTATTR_29_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_29_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_29_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_29_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_30 ===================================================== */ +#define ECLIC_CLICINTATTR_30_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_30_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_30_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_30_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_31 ===================================================== */ +#define ECLIC_CLICINTATTR_31_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_31_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_31_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_31_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_32 ===================================================== */ +#define ECLIC_CLICINTATTR_32_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_32_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_32_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_32_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_33 ===================================================== */ +#define ECLIC_CLICINTATTR_33_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_33_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_33_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_33_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_34 ===================================================== */ +#define ECLIC_CLICINTATTR_34_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_34_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_34_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_34_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_35 ===================================================== */ +#define ECLIC_CLICINTATTR_35_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_35_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_35_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_35_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_36 ===================================================== */ +#define ECLIC_CLICINTATTR_36_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_36_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_36_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_36_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_37 ===================================================== */ +#define ECLIC_CLICINTATTR_37_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_37_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_37_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_37_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_38 ===================================================== */ +#define ECLIC_CLICINTATTR_38_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_38_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_38_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_38_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_39 ===================================================== */ +#define ECLIC_CLICINTATTR_39_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_39_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_39_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_39_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_40 ===================================================== */ +#define ECLIC_CLICINTATTR_40_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_40_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_40_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_40_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_41 ===================================================== */ +#define ECLIC_CLICINTATTR_41_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_41_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_41_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_41_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_42 ===================================================== */ +#define ECLIC_CLICINTATTR_42_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_42_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_42_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_42_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_43 ===================================================== */ +#define ECLIC_CLICINTATTR_43_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_43_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_43_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_43_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_44 ===================================================== */ +#define ECLIC_CLICINTATTR_44_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_44_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_44_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_44_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_45 ===================================================== */ +#define ECLIC_CLICINTATTR_45_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_45_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_45_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_45_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_46 ===================================================== */ +#define ECLIC_CLICINTATTR_46_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_46_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_46_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_46_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_47 ===================================================== */ +#define ECLIC_CLICINTATTR_47_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_47_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_47_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_47_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_48 ===================================================== */ +#define ECLIC_CLICINTATTR_48_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_48_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_48_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_48_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_49 ===================================================== */ +#define ECLIC_CLICINTATTR_49_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_49_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_49_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_49_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_50 ===================================================== */ +#define ECLIC_CLICINTATTR_50_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_50_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_50_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_50_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_51 ===================================================== */ +#define ECLIC_CLICINTATTR_51_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_51_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_51_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_51_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_52 ===================================================== */ +#define ECLIC_CLICINTATTR_52_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_52_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_52_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_52_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_53 ===================================================== */ +#define ECLIC_CLICINTATTR_53_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_53_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_53_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_53_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_54 ===================================================== */ +#define ECLIC_CLICINTATTR_54_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_54_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_54_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_54_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_55 ===================================================== */ +#define ECLIC_CLICINTATTR_55_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_55_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_55_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_55_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_56 ===================================================== */ +#define ECLIC_CLICINTATTR_56_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_56_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_56_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_56_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_57 ===================================================== */ +#define ECLIC_CLICINTATTR_57_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_57_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_57_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_57_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_58 ===================================================== */ +#define ECLIC_CLICINTATTR_58_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_58_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_58_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_58_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_59 ===================================================== */ +#define ECLIC_CLICINTATTR_59_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_59_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_59_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_59_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_60 ===================================================== */ +#define ECLIC_CLICINTATTR_60_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_60_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_60_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_60_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_61 ===================================================== */ +#define ECLIC_CLICINTATTR_61_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_61_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_61_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_61_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_62 ===================================================== */ +#define ECLIC_CLICINTATTR_62_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_62_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_62_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_62_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_63 ===================================================== */ +#define ECLIC_CLICINTATTR_63_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_63_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_63_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_63_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_64 ===================================================== */ +#define ECLIC_CLICINTATTR_64_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_64_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_64_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_64_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_65 ===================================================== */ +#define ECLIC_CLICINTATTR_65_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_65_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_65_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_65_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_66 ===================================================== */ +#define ECLIC_CLICINTATTR_66_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_66_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_66_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_66_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_67 ===================================================== */ +#define ECLIC_CLICINTATTR_67_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_67_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_67_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_67_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_68 ===================================================== */ +#define ECLIC_CLICINTATTR_68_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_68_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_68_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_68_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_69 ===================================================== */ +#define ECLIC_CLICINTATTR_69_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_69_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_69_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_69_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_70 ===================================================== */ +#define ECLIC_CLICINTATTR_70_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_70_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_70_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_70_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_71 ===================================================== */ +#define ECLIC_CLICINTATTR_71_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_71_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_71_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_71_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_72 ===================================================== */ +#define ECLIC_CLICINTATTR_72_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_72_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_72_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_72_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_73 ===================================================== */ +#define ECLIC_CLICINTATTR_73_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_73_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_73_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_73_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_74 ===================================================== */ +#define ECLIC_CLICINTATTR_74_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_74_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_74_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_74_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_75 ===================================================== */ +#define ECLIC_CLICINTATTR_75_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_75_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_75_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_75_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_76 ===================================================== */ +#define ECLIC_CLICINTATTR_76_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_76_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_76_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_76_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_77 ===================================================== */ +#define ECLIC_CLICINTATTR_77_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_77_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_77_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_77_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_78 ===================================================== */ +#define ECLIC_CLICINTATTR_78_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_78_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_78_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_78_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_79 ===================================================== */ +#define ECLIC_CLICINTATTR_79_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_79_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_79_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_79_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_80 ===================================================== */ +#define ECLIC_CLICINTATTR_80_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_80_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_80_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_80_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_81 ===================================================== */ +#define ECLIC_CLICINTATTR_81_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_81_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_81_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_81_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_82 ===================================================== */ +#define ECLIC_CLICINTATTR_82_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_82_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_82_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_82_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_83 ===================================================== */ +#define ECLIC_CLICINTATTR_83_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_83_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_83_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_83_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_84 ===================================================== */ +#define ECLIC_CLICINTATTR_84_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_84_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_84_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_84_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_85 ===================================================== */ +#define ECLIC_CLICINTATTR_85_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_85_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_85_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_85_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ==================================================== CLICINTATTR_86 ===================================================== */ +#define ECLIC_CLICINTATTR_86_SHV_Pos (0UL) /*!< SHV (Bit 0) */ +#define ECLIC_CLICINTATTR_86_SHV_Msk (0x1UL) /*!< SHV (Bitfield-Mask: 0x01) */ +#define ECLIC_CLICINTATTR_86_TRIG_Pos (1UL) /*!< TRIG (Bit 1) */ +#define ECLIC_CLICINTATTR_86_TRIG_Msk (0x6UL) /*!< TRIG (Bitfield-Mask: 0x03) */ +/* ===================================================== CLICINTCTL_0 ====================================================== */ +#define ECLIC_CLICINTCTL_0_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_0_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_1 ====================================================== */ +#define ECLIC_CLICINTCTL_1_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_1_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_2 ====================================================== */ +#define ECLIC_CLICINTCTL_2_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_2_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_3 ====================================================== */ +#define ECLIC_CLICINTCTL_3_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_3_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_4 ====================================================== */ +#define ECLIC_CLICINTCTL_4_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_4_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_5 ====================================================== */ +#define ECLIC_CLICINTCTL_5_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_5_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_6 ====================================================== */ +#define ECLIC_CLICINTCTL_6_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_6_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_7 ====================================================== */ +#define ECLIC_CLICINTCTL_7_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_7_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_8 ====================================================== */ +#define ECLIC_CLICINTCTL_8_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_8_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_9 ====================================================== */ +#define ECLIC_CLICINTCTL_9_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_9_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_10 ===================================================== */ +#define ECLIC_CLICINTCTL_10_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_10_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_11 ===================================================== */ +#define ECLIC_CLICINTCTL_11_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_11_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_12 ===================================================== */ +#define ECLIC_CLICINTCTL_12_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_12_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_13 ===================================================== */ +#define ECLIC_CLICINTCTL_13_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_13_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_14 ===================================================== */ +#define ECLIC_CLICINTCTL_14_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_14_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_15 ===================================================== */ +#define ECLIC_CLICINTCTL_15_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_15_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_16 ===================================================== */ +#define ECLIC_CLICINTCTL_16_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_16_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_17 ===================================================== */ +#define ECLIC_CLICINTCTL_17_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_17_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_18 ===================================================== */ +#define ECLIC_CLICINTCTL_18_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_18_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_19 ===================================================== */ +#define ECLIC_CLICINTCTL_19_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_19_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_20 ===================================================== */ +#define ECLIC_CLICINTCTL_20_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_20_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_21 ===================================================== */ +#define ECLIC_CLICINTCTL_21_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_21_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_22 ===================================================== */ +#define ECLIC_CLICINTCTL_22_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_22_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_23 ===================================================== */ +#define ECLIC_CLICINTCTL_23_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_23_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_24 ===================================================== */ +#define ECLIC_CLICINTCTL_24_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_24_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_25 ===================================================== */ +#define ECLIC_CLICINTCTL_25_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_25_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_26 ===================================================== */ +#define ECLIC_CLICINTCTL_26_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_26_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_27 ===================================================== */ +#define ECLIC_CLICINTCTL_27_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_27_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_28 ===================================================== */ +#define ECLIC_CLICINTCTL_28_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_28_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_29 ===================================================== */ +#define ECLIC_CLICINTCTL_29_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_29_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_30 ===================================================== */ +#define ECLIC_CLICINTCTL_30_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_30_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_31 ===================================================== */ +#define ECLIC_CLICINTCTL_31_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_31_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_32 ===================================================== */ +#define ECLIC_CLICINTCTL_32_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_32_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_33 ===================================================== */ +#define ECLIC_CLICINTCTL_33_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_33_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_34 ===================================================== */ +#define ECLIC_CLICINTCTL_34_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_34_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_35 ===================================================== */ +#define ECLIC_CLICINTCTL_35_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_35_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_36 ===================================================== */ +#define ECLIC_CLICINTCTL_36_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_36_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_37 ===================================================== */ +#define ECLIC_CLICINTCTL_37_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_37_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_38 ===================================================== */ +#define ECLIC_CLICINTCTL_38_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_38_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_39 ===================================================== */ +#define ECLIC_CLICINTCTL_39_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_39_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_40 ===================================================== */ +#define ECLIC_CLICINTCTL_40_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_40_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_41 ===================================================== */ +#define ECLIC_CLICINTCTL_41_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_41_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_42 ===================================================== */ +#define ECLIC_CLICINTCTL_42_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_42_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_43 ===================================================== */ +#define ECLIC_CLICINTCTL_43_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_43_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_44 ===================================================== */ +#define ECLIC_CLICINTCTL_44_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_44_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_45 ===================================================== */ +#define ECLIC_CLICINTCTL_45_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_45_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_46 ===================================================== */ +#define ECLIC_CLICINTCTL_46_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_46_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_47 ===================================================== */ +#define ECLIC_CLICINTCTL_47_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_47_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_48 ===================================================== */ +#define ECLIC_CLICINTCTL_48_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_48_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_49 ===================================================== */ +#define ECLIC_CLICINTCTL_49_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_49_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_50 ===================================================== */ +#define ECLIC_CLICINTCTL_50_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_50_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_51 ===================================================== */ +#define ECLIC_CLICINTCTL_51_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_51_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_52 ===================================================== */ +#define ECLIC_CLICINTCTL_52_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_52_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_53 ===================================================== */ +#define ECLIC_CLICINTCTL_53_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_53_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_54 ===================================================== */ +#define ECLIC_CLICINTCTL_54_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_54_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_55 ===================================================== */ +#define ECLIC_CLICINTCTL_55_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_55_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_56 ===================================================== */ +#define ECLIC_CLICINTCTL_56_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_56_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_57 ===================================================== */ +#define ECLIC_CLICINTCTL_57_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_57_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_58 ===================================================== */ +#define ECLIC_CLICINTCTL_58_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_58_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_59 ===================================================== */ +#define ECLIC_CLICINTCTL_59_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_59_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_60 ===================================================== */ +#define ECLIC_CLICINTCTL_60_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_60_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_61 ===================================================== */ +#define ECLIC_CLICINTCTL_61_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_61_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_62 ===================================================== */ +#define ECLIC_CLICINTCTL_62_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_62_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_63 ===================================================== */ +#define ECLIC_CLICINTCTL_63_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_63_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_64 ===================================================== */ +#define ECLIC_CLICINTCTL_64_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_64_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_65 ===================================================== */ +#define ECLIC_CLICINTCTL_65_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_65_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_66 ===================================================== */ +#define ECLIC_CLICINTCTL_66_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_66_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_67 ===================================================== */ +#define ECLIC_CLICINTCTL_67_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_67_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_68 ===================================================== */ +#define ECLIC_CLICINTCTL_68_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_68_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_69 ===================================================== */ +#define ECLIC_CLICINTCTL_69_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_69_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_70 ===================================================== */ +#define ECLIC_CLICINTCTL_70_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_70_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_71 ===================================================== */ +#define ECLIC_CLICINTCTL_71_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_71_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_72 ===================================================== */ +#define ECLIC_CLICINTCTL_72_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_72_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_73 ===================================================== */ +#define ECLIC_CLICINTCTL_73_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_73_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_74 ===================================================== */ +#define ECLIC_CLICINTCTL_74_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_74_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_75 ===================================================== */ +#define ECLIC_CLICINTCTL_75_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_75_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_76 ===================================================== */ +#define ECLIC_CLICINTCTL_76_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_76_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_77 ===================================================== */ +#define ECLIC_CLICINTCTL_77_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_77_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_78 ===================================================== */ +#define ECLIC_CLICINTCTL_78_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_78_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_79 ===================================================== */ +#define ECLIC_CLICINTCTL_79_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_79_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_80 ===================================================== */ +#define ECLIC_CLICINTCTL_80_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_80_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_81 ===================================================== */ +#define ECLIC_CLICINTCTL_81_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_81_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_82 ===================================================== */ +#define ECLIC_CLICINTCTL_82_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_82_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_83 ===================================================== */ +#define ECLIC_CLICINTCTL_83_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_83_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_84 ===================================================== */ +#define ECLIC_CLICINTCTL_84_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_84_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_85 ===================================================== */ +#define ECLIC_CLICINTCTL_85_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_85_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ +/* ===================================================== CLICINTCTL_86 ===================================================== */ +#define ECLIC_CLICINTCTL_86_LEVEL_PRIORITY_Pos (0UL) /*!< LEVEL_PRIORITY (Bit 0) */ +#define ECLIC_CLICINTCTL_86_LEVEL_PRIORITY_Msk (0xffUL) /*!< LEVEL_PRIORITY (Bitfield-Mask: 0xff) */ + + +/* =========================================================================================================================== */ +/* ================ PMU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CTL ========================================================== */ +#define PMU_CTL_BKPWEN_Pos (8UL) /*!< BKPWEN (Bit 8) */ +#define PMU_CTL_BKPWEN_Msk (0x100UL) /*!< BKPWEN (Bitfield-Mask: 0x01) */ +#define PMU_CTL_LVDT_Pos (5UL) /*!< LVDT (Bit 5) */ +#define PMU_CTL_LVDT_Msk (0xe0UL) /*!< LVDT (Bitfield-Mask: 0x07) */ +#define PMU_CTL_LVDEN_Pos (4UL) /*!< LVDEN (Bit 4) */ +#define PMU_CTL_LVDEN_Msk (0x10UL) /*!< LVDEN (Bitfield-Mask: 0x01) */ +#define PMU_CTL_STBRST_Pos (3UL) /*!< STBRST (Bit 3) */ +#define PMU_CTL_STBRST_Msk (0x8UL) /*!< STBRST (Bitfield-Mask: 0x01) */ +#define PMU_CTL_WURST_Pos (2UL) /*!< WURST (Bit 2) */ +#define PMU_CTL_WURST_Msk (0x4UL) /*!< WURST (Bitfield-Mask: 0x01) */ +#define PMU_CTL_STBMOD_Pos (1UL) /*!< STBMOD (Bit 1) */ +#define PMU_CTL_STBMOD_Msk (0x2UL) /*!< STBMOD (Bitfield-Mask: 0x01) */ +#define PMU_CTL_LDOLP_Pos (0UL) /*!< LDOLP (Bit 0) */ +#define PMU_CTL_LDOLP_Msk (0x1UL) /*!< LDOLP (Bitfield-Mask: 0x01) */ +/* ========================================================== CS =========================================================== */ +#define PMU_CS_WUPEN_Pos (8UL) /*!< WUPEN (Bit 8) */ +#define PMU_CS_WUPEN_Msk (0x100UL) /*!< WUPEN (Bitfield-Mask: 0x01) */ +#define PMU_CS_LVDF_Pos (2UL) /*!< LVDF (Bit 2) */ +#define PMU_CS_LVDF_Msk (0x4UL) /*!< LVDF (Bitfield-Mask: 0x01) */ +#define PMU_CS_STBF_Pos (1UL) /*!< STBF (Bit 1) */ +#define PMU_CS_STBF_Msk (0x2UL) /*!< STBF (Bitfield-Mask: 0x01) */ +#define PMU_CS_WUF_Pos (0UL) /*!< WUF (Bit 0) */ +#define PMU_CS_WUF_Msk (0x1UL) /*!< WUF (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ RCU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CTL ========================================================== */ +#define RCU_CTL_IRC8MEN_Pos (0UL) /*!< IRC8MEN (Bit 0) */ +#define RCU_CTL_IRC8MEN_Msk (0x1UL) /*!< IRC8MEN (Bitfield-Mask: 0x01) */ +#define RCU_CTL_IRC8MSTB_Pos (1UL) /*!< IRC8MSTB (Bit 1) */ +#define RCU_CTL_IRC8MSTB_Msk (0x2UL) /*!< IRC8MSTB (Bitfield-Mask: 0x01) */ +#define RCU_CTL_IRC8MADJ_Pos (3UL) /*!< IRC8MADJ (Bit 3) */ +#define RCU_CTL_IRC8MADJ_Msk (0xf8UL) /*!< IRC8MADJ (Bitfield-Mask: 0x1f) */ +#define RCU_CTL_IRC8MCALIB_Pos (8UL) /*!< IRC8MCALIB (Bit 8) */ +#define RCU_CTL_IRC8MCALIB_Msk (0xff00UL) /*!< IRC8MCALIB (Bitfield-Mask: 0xff) */ +#define RCU_CTL_HXTALEN_Pos (16UL) /*!< HXTALEN (Bit 16) */ +#define RCU_CTL_HXTALEN_Msk (0x10000UL) /*!< HXTALEN (Bitfield-Mask: 0x01) */ +#define RCU_CTL_HXTALSTB_Pos (17UL) /*!< HXTALSTB (Bit 17) */ +#define RCU_CTL_HXTALSTB_Msk (0x20000UL) /*!< HXTALSTB (Bitfield-Mask: 0x01) */ +#define RCU_CTL_HXTALBPS_Pos (18UL) /*!< HXTALBPS (Bit 18) */ +#define RCU_CTL_HXTALBPS_Msk (0x40000UL) /*!< HXTALBPS (Bitfield-Mask: 0x01) */ +#define RCU_CTL_CKMEN_Pos (19UL) /*!< CKMEN (Bit 19) */ +#define RCU_CTL_CKMEN_Msk (0x80000UL) /*!< CKMEN (Bitfield-Mask: 0x01) */ +#define RCU_CTL_PLLEN_Pos (24UL) /*!< PLLEN (Bit 24) */ +#define RCU_CTL_PLLEN_Msk (0x1000000UL) /*!< PLLEN (Bitfield-Mask: 0x01) */ +#define RCU_CTL_PLLSTB_Pos (25UL) /*!< PLLSTB (Bit 25) */ +#define RCU_CTL_PLLSTB_Msk (0x2000000UL) /*!< PLLSTB (Bitfield-Mask: 0x01) */ +#define RCU_CTL_PLL1EN_Pos (26UL) /*!< PLL1EN (Bit 26) */ +#define RCU_CTL_PLL1EN_Msk (0x4000000UL) /*!< PLL1EN (Bitfield-Mask: 0x01) */ +#define RCU_CTL_PLL1STB_Pos (27UL) /*!< PLL1STB (Bit 27) */ +#define RCU_CTL_PLL1STB_Msk (0x8000000UL) /*!< PLL1STB (Bitfield-Mask: 0x01) */ +#define RCU_CTL_PLL2EN_Pos (28UL) /*!< PLL2EN (Bit 28) */ +#define RCU_CTL_PLL2EN_Msk (0x10000000UL) /*!< PLL2EN (Bitfield-Mask: 0x01) */ +#define RCU_CTL_PLL2STB_Pos (29UL) /*!< PLL2STB (Bit 29) */ +#define RCU_CTL_PLL2STB_Msk (0x20000000UL) /*!< PLL2STB (Bitfield-Mask: 0x01) */ +/* ========================================================= CFG0 ========================================================== */ +#define RCU_CFG0_SCS_Pos (0UL) /*!< SCS (Bit 0) */ +#define RCU_CFG0_SCS_Msk (0x3UL) /*!< SCS (Bitfield-Mask: 0x03) */ +#define RCU_CFG0_SCSS_Pos (2UL) /*!< SCSS (Bit 2) */ +#define RCU_CFG0_SCSS_Msk (0xcUL) /*!< SCSS (Bitfield-Mask: 0x03) */ +#define RCU_CFG0_AHBPSC_Pos (4UL) /*!< AHBPSC (Bit 4) */ +#define RCU_CFG0_AHBPSC_Msk (0xf0UL) /*!< AHBPSC (Bitfield-Mask: 0x0f) */ +#define RCU_CFG0_APB1PSC_Pos (8UL) /*!< APB1PSC (Bit 8) */ +#define RCU_CFG0_APB1PSC_Msk (0x700UL) /*!< APB1PSC (Bitfield-Mask: 0x07) */ +#define RCU_CFG0_APB2PSC_Pos (11UL) /*!< APB2PSC (Bit 11) */ +#define RCU_CFG0_APB2PSC_Msk (0x3800UL) /*!< APB2PSC (Bitfield-Mask: 0x07) */ +#define RCU_CFG0_ADCPSC_1_0_Pos (14UL) /*!< ADCPSC_1_0 (Bit 14) */ +#define RCU_CFG0_ADCPSC_1_0_Msk (0xc000UL) /*!< ADCPSC_1_0 (Bitfield-Mask: 0x03) */ +#define RCU_CFG0_PLLSEL_Pos (16UL) /*!< PLLSEL (Bit 16) */ +#define RCU_CFG0_PLLSEL_Msk (0x10000UL) /*!< PLLSEL (Bitfield-Mask: 0x01) */ +#define RCU_CFG0_PREDV0_LSB_Pos (17UL) /*!< PREDV0_LSB (Bit 17) */ +#define RCU_CFG0_PREDV0_LSB_Msk (0x20000UL) /*!< PREDV0_LSB (Bitfield-Mask: 0x01) */ +#define RCU_CFG0_PLLMF_3_0_Pos (18UL) /*!< PLLMF_3_0 (Bit 18) */ +#define RCU_CFG0_PLLMF_3_0_Msk (0x3c0000UL) /*!< PLLMF_3_0 (Bitfield-Mask: 0x0f) */ +#define RCU_CFG0_USBFSPSC_Pos (22UL) /*!< USBFSPSC (Bit 22) */ +#define RCU_CFG0_USBFSPSC_Msk (0xc00000UL) /*!< USBFSPSC (Bitfield-Mask: 0x03) */ +#define RCU_CFG0_CKOUT0SEL_Pos (24UL) /*!< CKOUT0SEL (Bit 24) */ +#define RCU_CFG0_CKOUT0SEL_Msk (0xf000000UL) /*!< CKOUT0SEL (Bitfield-Mask: 0x0f) */ +#define RCU_CFG0_ADCPSC_2_Pos (28UL) /*!< ADCPSC_2 (Bit 28) */ +#define RCU_CFG0_ADCPSC_2_Msk (0x10000000UL) /*!< ADCPSC_2 (Bitfield-Mask: 0x01) */ +#define RCU_CFG0_PLLMF_4_Pos (29UL) /*!< PLLMF_4 (Bit 29) */ +#define RCU_CFG0_PLLMF_4_Msk (0x20000000UL) /*!< PLLMF_4 (Bitfield-Mask: 0x01) */ +/* ========================================================== INT ========================================================== */ +#define RCU_INT_IRC40KSTBIF_Pos (0UL) /*!< IRC40KSTBIF (Bit 0) */ +#define RCU_INT_IRC40KSTBIF_Msk (0x1UL) /*!< IRC40KSTBIF (Bitfield-Mask: 0x01) */ +#define RCU_INT_LXTALSTBIF_Pos (1UL) /*!< LXTALSTBIF (Bit 1) */ +#define RCU_INT_LXTALSTBIF_Msk (0x2UL) /*!< LXTALSTBIF (Bitfield-Mask: 0x01) */ +#define RCU_INT_IRC8MSTBIF_Pos (2UL) /*!< IRC8MSTBIF (Bit 2) */ +#define RCU_INT_IRC8MSTBIF_Msk (0x4UL) /*!< IRC8MSTBIF (Bitfield-Mask: 0x01) */ +#define RCU_INT_HXTALSTBIF_Pos (3UL) /*!< HXTALSTBIF (Bit 3) */ +#define RCU_INT_HXTALSTBIF_Msk (0x8UL) /*!< HXTALSTBIF (Bitfield-Mask: 0x01) */ +#define RCU_INT_PLLSTBIF_Pos (4UL) /*!< PLLSTBIF (Bit 4) */ +#define RCU_INT_PLLSTBIF_Msk (0x10UL) /*!< PLLSTBIF (Bitfield-Mask: 0x01) */ +#define RCU_INT_PLL1STBIF_Pos (5UL) /*!< PLL1STBIF (Bit 5) */ +#define RCU_INT_PLL1STBIF_Msk (0x20UL) /*!< PLL1STBIF (Bitfield-Mask: 0x01) */ +#define RCU_INT_PLL2STBIF_Pos (6UL) /*!< PLL2STBIF (Bit 6) */ +#define RCU_INT_PLL2STBIF_Msk (0x40UL) /*!< PLL2STBIF (Bitfield-Mask: 0x01) */ +#define RCU_INT_CKMIF_Pos (7UL) /*!< CKMIF (Bit 7) */ +#define RCU_INT_CKMIF_Msk (0x80UL) /*!< CKMIF (Bitfield-Mask: 0x01) */ +#define RCU_INT_IRC40KSTBIE_Pos (8UL) /*!< IRC40KSTBIE (Bit 8) */ +#define RCU_INT_IRC40KSTBIE_Msk (0x100UL) /*!< IRC40KSTBIE (Bitfield-Mask: 0x01) */ +#define RCU_INT_LXTALSTBIE_Pos (9UL) /*!< LXTALSTBIE (Bit 9) */ +#define RCU_INT_LXTALSTBIE_Msk (0x200UL) /*!< LXTALSTBIE (Bitfield-Mask: 0x01) */ +#define RCU_INT_IRC8MSTBIE_Pos (10UL) /*!< IRC8MSTBIE (Bit 10) */ +#define RCU_INT_IRC8MSTBIE_Msk (0x400UL) /*!< IRC8MSTBIE (Bitfield-Mask: 0x01) */ +#define RCU_INT_HXTALSTBIE_Pos (11UL) /*!< HXTALSTBIE (Bit 11) */ +#define RCU_INT_HXTALSTBIE_Msk (0x800UL) /*!< HXTALSTBIE (Bitfield-Mask: 0x01) */ +#define RCU_INT_PLLSTBIE_Pos (12UL) /*!< PLLSTBIE (Bit 12) */ +#define RCU_INT_PLLSTBIE_Msk (0x1000UL) /*!< PLLSTBIE (Bitfield-Mask: 0x01) */ +#define RCU_INT_PLL1STBIE_Pos (13UL) /*!< PLL1STBIE (Bit 13) */ +#define RCU_INT_PLL1STBIE_Msk (0x2000UL) /*!< PLL1STBIE (Bitfield-Mask: 0x01) */ +#define RCU_INT_PLL2STBIE_Pos (14UL) /*!< PLL2STBIE (Bit 14) */ +#define RCU_INT_PLL2STBIE_Msk (0x4000UL) /*!< PLL2STBIE (Bitfield-Mask: 0x01) */ +#define RCU_INT_IRC40KSTBIC_Pos (16UL) /*!< IRC40KSTBIC (Bit 16) */ +#define RCU_INT_IRC40KSTBIC_Msk (0x10000UL) /*!< IRC40KSTBIC (Bitfield-Mask: 0x01) */ +#define RCU_INT_LXTALSTBIC_Pos (17UL) /*!< LXTALSTBIC (Bit 17) */ +#define RCU_INT_LXTALSTBIC_Msk (0x20000UL) /*!< LXTALSTBIC (Bitfield-Mask: 0x01) */ +#define RCU_INT_IRC8MSTBIC_Pos (18UL) /*!< IRC8MSTBIC (Bit 18) */ +#define RCU_INT_IRC8MSTBIC_Msk (0x40000UL) /*!< IRC8MSTBIC (Bitfield-Mask: 0x01) */ +#define RCU_INT_HXTALSTBIC_Pos (19UL) /*!< HXTALSTBIC (Bit 19) */ +#define RCU_INT_HXTALSTBIC_Msk (0x80000UL) /*!< HXTALSTBIC (Bitfield-Mask: 0x01) */ +#define RCU_INT_PLLSTBIC_Pos (20UL) /*!< PLLSTBIC (Bit 20) */ +#define RCU_INT_PLLSTBIC_Msk (0x100000UL) /*!< PLLSTBIC (Bitfield-Mask: 0x01) */ +#define RCU_INT_PLL1STBIC_Pos (21UL) /*!< PLL1STBIC (Bit 21) */ +#define RCU_INT_PLL1STBIC_Msk (0x200000UL) /*!< PLL1STBIC (Bitfield-Mask: 0x01) */ +#define RCU_INT_PLL2STBIC_Pos (22UL) /*!< PLL2STBIC (Bit 22) */ +#define RCU_INT_PLL2STBIC_Msk (0x400000UL) /*!< PLL2STBIC (Bitfield-Mask: 0x01) */ +#define RCU_INT_CKMIC_Pos (23UL) /*!< CKMIC (Bit 23) */ +#define RCU_INT_CKMIC_Msk (0x800000UL) /*!< CKMIC (Bitfield-Mask: 0x01) */ +/* ======================================================== APB2RST ======================================================== */ +#define RCU_APB2RST_AFRST_Pos (0UL) /*!< AFRST (Bit 0) */ +#define RCU_APB2RST_AFRST_Msk (0x1UL) /*!< AFRST (Bitfield-Mask: 0x01) */ +#define RCU_APB2RST_PARST_Pos (2UL) /*!< PARST (Bit 2) */ +#define RCU_APB2RST_PARST_Msk (0x4UL) /*!< PARST (Bitfield-Mask: 0x01) */ +#define RCU_APB2RST_PBRST_Pos (3UL) /*!< PBRST (Bit 3) */ +#define RCU_APB2RST_PBRST_Msk (0x8UL) /*!< PBRST (Bitfield-Mask: 0x01) */ +#define RCU_APB2RST_PCRST_Pos (4UL) /*!< PCRST (Bit 4) */ +#define RCU_APB2RST_PCRST_Msk (0x10UL) /*!< PCRST (Bitfield-Mask: 0x01) */ +#define RCU_APB2RST_PDRST_Pos (5UL) /*!< PDRST (Bit 5) */ +#define RCU_APB2RST_PDRST_Msk (0x20UL) /*!< PDRST (Bitfield-Mask: 0x01) */ +#define RCU_APB2RST_PERST_Pos (6UL) /*!< PERST (Bit 6) */ +#define RCU_APB2RST_PERST_Msk (0x40UL) /*!< PERST (Bitfield-Mask: 0x01) */ +#define RCU_APB2RST_ADC0RST_Pos (9UL) /*!< ADC0RST (Bit 9) */ +#define RCU_APB2RST_ADC0RST_Msk (0x200UL) /*!< ADC0RST (Bitfield-Mask: 0x01) */ +#define RCU_APB2RST_ADC1RST_Pos (10UL) /*!< ADC1RST (Bit 10) */ +#define RCU_APB2RST_ADC1RST_Msk (0x400UL) /*!< ADC1RST (Bitfield-Mask: 0x01) */ +#define RCU_APB2RST_TIMER0RST_Pos (11UL) /*!< TIMER0RST (Bit 11) */ +#define RCU_APB2RST_TIMER0RST_Msk (0x800UL) /*!< TIMER0RST (Bitfield-Mask: 0x01) */ +#define RCU_APB2RST_SPI0RST_Pos (12UL) /*!< SPI0RST (Bit 12) */ +#define RCU_APB2RST_SPI0RST_Msk (0x1000UL) /*!< SPI0RST (Bitfield-Mask: 0x01) */ +#define RCU_APB2RST_USART0RST_Pos (14UL) /*!< USART0RST (Bit 14) */ +#define RCU_APB2RST_USART0RST_Msk (0x4000UL) /*!< USART0RST (Bitfield-Mask: 0x01) */ +/* ======================================================== APB1RST ======================================================== */ +#define RCU_APB1RST_TIMER1RST_Pos (0UL) /*!< TIMER1RST (Bit 0) */ +#define RCU_APB1RST_TIMER1RST_Msk (0x1UL) /*!< TIMER1RST (Bitfield-Mask: 0x01) */ +#define RCU_APB1RST_TIMER2RST_Pos (1UL) /*!< TIMER2RST (Bit 1) */ +#define RCU_APB1RST_TIMER2RST_Msk (0x2UL) /*!< TIMER2RST (Bitfield-Mask: 0x01) */ +#define RCU_APB1RST_TIMER3RST_Pos (2UL) /*!< TIMER3RST (Bit 2) */ +#define RCU_APB1RST_TIMER3RST_Msk (0x4UL) /*!< TIMER3RST (Bitfield-Mask: 0x01) */ +#define RCU_APB1RST_TIMER4RST_Pos (3UL) /*!< TIMER4RST (Bit 3) */ +#define RCU_APB1RST_TIMER4RST_Msk (0x8UL) /*!< TIMER4RST (Bitfield-Mask: 0x01) */ +#define RCU_APB1RST_TIMER5RST_Pos (4UL) /*!< TIMER5RST (Bit 4) */ +#define RCU_APB1RST_TIMER5RST_Msk (0x10UL) /*!< TIMER5RST (Bitfield-Mask: 0x01) */ +#define RCU_APB1RST_TIMER6RST_Pos (5UL) /*!< TIMER6RST (Bit 5) */ +#define RCU_APB1RST_TIMER6RST_Msk (0x20UL) /*!< TIMER6RST (Bitfield-Mask: 0x01) */ +#define RCU_APB1RST_WWDGTRST_Pos (11UL) /*!< WWDGTRST (Bit 11) */ +#define RCU_APB1RST_WWDGTRST_Msk (0x800UL) /*!< WWDGTRST (Bitfield-Mask: 0x01) */ +#define RCU_APB1RST_SPI1RST_Pos (14UL) /*!< SPI1RST (Bit 14) */ +#define RCU_APB1RST_SPI1RST_Msk (0x4000UL) /*!< SPI1RST (Bitfield-Mask: 0x01) */ +#define RCU_APB1RST_SPI2RST_Pos (15UL) /*!< SPI2RST (Bit 15) */ +#define RCU_APB1RST_SPI2RST_Msk (0x8000UL) /*!< SPI2RST (Bitfield-Mask: 0x01) */ +#define RCU_APB1RST_USART1RST_Pos (17UL) /*!< USART1RST (Bit 17) */ +#define RCU_APB1RST_USART1RST_Msk (0x20000UL) /*!< USART1RST (Bitfield-Mask: 0x01) */ +#define RCU_APB1RST_USART2RST_Pos (18UL) /*!< USART2RST (Bit 18) */ +#define RCU_APB1RST_USART2RST_Msk (0x40000UL) /*!< USART2RST (Bitfield-Mask: 0x01) */ +#define RCU_APB1RST_UART3RST_Pos (19UL) /*!< UART3RST (Bit 19) */ +#define RCU_APB1RST_UART3RST_Msk (0x80000UL) /*!< UART3RST (Bitfield-Mask: 0x01) */ +#define RCU_APB1RST_UART4RST_Pos (20UL) /*!< UART4RST (Bit 20) */ +#define RCU_APB1RST_UART4RST_Msk (0x100000UL) /*!< UART4RST (Bitfield-Mask: 0x01) */ +#define RCU_APB1RST_I2C0RST_Pos (21UL) /*!< I2C0RST (Bit 21) */ +#define RCU_APB1RST_I2C0RST_Msk (0x200000UL) /*!< I2C0RST (Bitfield-Mask: 0x01) */ +#define RCU_APB1RST_I2C1RST_Pos (22UL) /*!< I2C1RST (Bit 22) */ +#define RCU_APB1RST_I2C1RST_Msk (0x400000UL) /*!< I2C1RST (Bitfield-Mask: 0x01) */ +#define RCU_APB1RST_CAN0RST_Pos (25UL) /*!< CAN0RST (Bit 25) */ +#define RCU_APB1RST_CAN0RST_Msk (0x2000000UL) /*!< CAN0RST (Bitfield-Mask: 0x01) */ +#define RCU_APB1RST_CAN1RST_Pos (26UL) /*!< CAN1RST (Bit 26) */ +#define RCU_APB1RST_CAN1RST_Msk (0x4000000UL) /*!< CAN1RST (Bitfield-Mask: 0x01) */ +#define RCU_APB1RST_BKPIRST_Pos (27UL) /*!< BKPIRST (Bit 27) */ +#define RCU_APB1RST_BKPIRST_Msk (0x8000000UL) /*!< BKPIRST (Bitfield-Mask: 0x01) */ +#define RCU_APB1RST_PMURST_Pos (28UL) /*!< PMURST (Bit 28) */ +#define RCU_APB1RST_PMURST_Msk (0x10000000UL) /*!< PMURST (Bitfield-Mask: 0x01) */ +#define RCU_APB1RST_DACRST_Pos (29UL) /*!< DACRST (Bit 29) */ +#define RCU_APB1RST_DACRST_Msk (0x20000000UL) /*!< DACRST (Bitfield-Mask: 0x01) */ +/* ========================================================= AHBEN ========================================================= */ +#define RCU_AHBEN_DMA0EN_Pos (0UL) /*!< DMA0EN (Bit 0) */ +#define RCU_AHBEN_DMA0EN_Msk (0x1UL) /*!< DMA0EN (Bitfield-Mask: 0x01) */ +#define RCU_AHBEN_DMA1EN_Pos (1UL) /*!< DMA1EN (Bit 1) */ +#define RCU_AHBEN_DMA1EN_Msk (0x2UL) /*!< DMA1EN (Bitfield-Mask: 0x01) */ +#define RCU_AHBEN_SRAMSPEN_Pos (2UL) /*!< SRAMSPEN (Bit 2) */ +#define RCU_AHBEN_SRAMSPEN_Msk (0x4UL) /*!< SRAMSPEN (Bitfield-Mask: 0x01) */ +#define RCU_AHBEN_FMCSPEN_Pos (4UL) /*!< FMCSPEN (Bit 4) */ +#define RCU_AHBEN_FMCSPEN_Msk (0x10UL) /*!< FMCSPEN (Bitfield-Mask: 0x01) */ +#define RCU_AHBEN_CRCEN_Pos (6UL) /*!< CRCEN (Bit 6) */ +#define RCU_AHBEN_CRCEN_Msk (0x40UL) /*!< CRCEN (Bitfield-Mask: 0x01) */ +#define RCU_AHBEN_EXMCEN_Pos (8UL) /*!< EXMCEN (Bit 8) */ +#define RCU_AHBEN_EXMCEN_Msk (0x100UL) /*!< EXMCEN (Bitfield-Mask: 0x01) */ +#define RCU_AHBEN_USBFSEN_Pos (12UL) /*!< USBFSEN (Bit 12) */ +#define RCU_AHBEN_USBFSEN_Msk (0x1000UL) /*!< USBFSEN (Bitfield-Mask: 0x01) */ +/* ======================================================== APB2EN ========================================================= */ +#define RCU_APB2EN_AFEN_Pos (0UL) /*!< AFEN (Bit 0) */ +#define RCU_APB2EN_AFEN_Msk (0x1UL) /*!< AFEN (Bitfield-Mask: 0x01) */ +#define RCU_APB2EN_PAEN_Pos (2UL) /*!< PAEN (Bit 2) */ +#define RCU_APB2EN_PAEN_Msk (0x4UL) /*!< PAEN (Bitfield-Mask: 0x01) */ +#define RCU_APB2EN_PBEN_Pos (3UL) /*!< PBEN (Bit 3) */ +#define RCU_APB2EN_PBEN_Msk (0x8UL) /*!< PBEN (Bitfield-Mask: 0x01) */ +#define RCU_APB2EN_PCEN_Pos (4UL) /*!< PCEN (Bit 4) */ +#define RCU_APB2EN_PCEN_Msk (0x10UL) /*!< PCEN (Bitfield-Mask: 0x01) */ +#define RCU_APB2EN_PDEN_Pos (5UL) /*!< PDEN (Bit 5) */ +#define RCU_APB2EN_PDEN_Msk (0x20UL) /*!< PDEN (Bitfield-Mask: 0x01) */ +#define RCU_APB2EN_PEEN_Pos (6UL) /*!< PEEN (Bit 6) */ +#define RCU_APB2EN_PEEN_Msk (0x40UL) /*!< PEEN (Bitfield-Mask: 0x01) */ +#define RCU_APB2EN_ADC0EN_Pos (9UL) /*!< ADC0EN (Bit 9) */ +#define RCU_APB2EN_ADC0EN_Msk (0x200UL) /*!< ADC0EN (Bitfield-Mask: 0x01) */ +#define RCU_APB2EN_ADC1EN_Pos (10UL) /*!< ADC1EN (Bit 10) */ +#define RCU_APB2EN_ADC1EN_Msk (0x400UL) /*!< ADC1EN (Bitfield-Mask: 0x01) */ +#define RCU_APB2EN_TIMER0EN_Pos (11UL) /*!< TIMER0EN (Bit 11) */ +#define RCU_APB2EN_TIMER0EN_Msk (0x800UL) /*!< TIMER0EN (Bitfield-Mask: 0x01) */ +#define RCU_APB2EN_SPI0EN_Pos (12UL) /*!< SPI0EN (Bit 12) */ +#define RCU_APB2EN_SPI0EN_Msk (0x1000UL) /*!< SPI0EN (Bitfield-Mask: 0x01) */ +#define RCU_APB2EN_USART0EN_Pos (14UL) /*!< USART0EN (Bit 14) */ +#define RCU_APB2EN_USART0EN_Msk (0x4000UL) /*!< USART0EN (Bitfield-Mask: 0x01) */ +/* ======================================================== APB1EN ========================================================= */ +#define RCU_APB1EN_TIMER1EN_Pos (0UL) /*!< TIMER1EN (Bit 0) */ +#define RCU_APB1EN_TIMER1EN_Msk (0x1UL) /*!< TIMER1EN (Bitfield-Mask: 0x01) */ +#define RCU_APB1EN_TIMER2EN_Pos (1UL) /*!< TIMER2EN (Bit 1) */ +#define RCU_APB1EN_TIMER2EN_Msk (0x2UL) /*!< TIMER2EN (Bitfield-Mask: 0x01) */ +#define RCU_APB1EN_TIMER3EN_Pos (2UL) /*!< TIMER3EN (Bit 2) */ +#define RCU_APB1EN_TIMER3EN_Msk (0x4UL) /*!< TIMER3EN (Bitfield-Mask: 0x01) */ +#define RCU_APB1EN_TIMER4EN_Pos (3UL) /*!< TIMER4EN (Bit 3) */ +#define RCU_APB1EN_TIMER4EN_Msk (0x8UL) /*!< TIMER4EN (Bitfield-Mask: 0x01) */ +#define RCU_APB1EN_TIMER5EN_Pos (4UL) /*!< TIMER5EN (Bit 4) */ +#define RCU_APB1EN_TIMER5EN_Msk (0x10UL) /*!< TIMER5EN (Bitfield-Mask: 0x01) */ +#define RCU_APB1EN_TIMER6EN_Pos (5UL) /*!< TIMER6EN (Bit 5) */ +#define RCU_APB1EN_TIMER6EN_Msk (0x20UL) /*!< TIMER6EN (Bitfield-Mask: 0x01) */ +#define RCU_APB1EN_WWDGTEN_Pos (11UL) /*!< WWDGTEN (Bit 11) */ +#define RCU_APB1EN_WWDGTEN_Msk (0x800UL) /*!< WWDGTEN (Bitfield-Mask: 0x01) */ +#define RCU_APB1EN_SPI1EN_Pos (14UL) /*!< SPI1EN (Bit 14) */ +#define RCU_APB1EN_SPI1EN_Msk (0x4000UL) /*!< SPI1EN (Bitfield-Mask: 0x01) */ +#define RCU_APB1EN_SPI2EN_Pos (15UL) /*!< SPI2EN (Bit 15) */ +#define RCU_APB1EN_SPI2EN_Msk (0x8000UL) /*!< SPI2EN (Bitfield-Mask: 0x01) */ +#define RCU_APB1EN_USART1EN_Pos (17UL) /*!< USART1EN (Bit 17) */ +#define RCU_APB1EN_USART1EN_Msk (0x20000UL) /*!< USART1EN (Bitfield-Mask: 0x01) */ +#define RCU_APB1EN_USART2EN_Pos (18UL) /*!< USART2EN (Bit 18) */ +#define RCU_APB1EN_USART2EN_Msk (0x40000UL) /*!< USART2EN (Bitfield-Mask: 0x01) */ +#define RCU_APB1EN_UART3EN_Pos (19UL) /*!< UART3EN (Bit 19) */ +#define RCU_APB1EN_UART3EN_Msk (0x80000UL) /*!< UART3EN (Bitfield-Mask: 0x01) */ +#define RCU_APB1EN_UART4EN_Pos (20UL) /*!< UART4EN (Bit 20) */ +#define RCU_APB1EN_UART4EN_Msk (0x100000UL) /*!< UART4EN (Bitfield-Mask: 0x01) */ +#define RCU_APB1EN_I2C0EN_Pos (21UL) /*!< I2C0EN (Bit 21) */ +#define RCU_APB1EN_I2C0EN_Msk (0x200000UL) /*!< I2C0EN (Bitfield-Mask: 0x01) */ +#define RCU_APB1EN_I2C1EN_Pos (22UL) /*!< I2C1EN (Bit 22) */ +#define RCU_APB1EN_I2C1EN_Msk (0x400000UL) /*!< I2C1EN (Bitfield-Mask: 0x01) */ +#define RCU_APB1EN_CAN0EN_Pos (25UL) /*!< CAN0EN (Bit 25) */ +#define RCU_APB1EN_CAN0EN_Msk (0x2000000UL) /*!< CAN0EN (Bitfield-Mask: 0x01) */ +#define RCU_APB1EN_CAN1EN_Pos (26UL) /*!< CAN1EN (Bit 26) */ +#define RCU_APB1EN_CAN1EN_Msk (0x4000000UL) /*!< CAN1EN (Bitfield-Mask: 0x01) */ +#define RCU_APB1EN_BKPIEN_Pos (27UL) /*!< BKPIEN (Bit 27) */ +#define RCU_APB1EN_BKPIEN_Msk (0x8000000UL) /*!< BKPIEN (Bitfield-Mask: 0x01) */ +#define RCU_APB1EN_PMUEN_Pos (28UL) /*!< PMUEN (Bit 28) */ +#define RCU_APB1EN_PMUEN_Msk (0x10000000UL) /*!< PMUEN (Bitfield-Mask: 0x01) */ +#define RCU_APB1EN_DACEN_Pos (29UL) /*!< DACEN (Bit 29) */ +#define RCU_APB1EN_DACEN_Msk (0x20000000UL) /*!< DACEN (Bitfield-Mask: 0x01) */ +/* ========================================================= BDCTL ========================================================= */ +#define RCU_BDCTL_LXTALEN_Pos (0UL) /*!< LXTALEN (Bit 0) */ +#define RCU_BDCTL_LXTALEN_Msk (0x1UL) /*!< LXTALEN (Bitfield-Mask: 0x01) */ +#define RCU_BDCTL_LXTALSTB_Pos (1UL) /*!< LXTALSTB (Bit 1) */ +#define RCU_BDCTL_LXTALSTB_Msk (0x2UL) /*!< LXTALSTB (Bitfield-Mask: 0x01) */ +#define RCU_BDCTL_LXTALBPS_Pos (2UL) /*!< LXTALBPS (Bit 2) */ +#define RCU_BDCTL_LXTALBPS_Msk (0x4UL) /*!< LXTALBPS (Bitfield-Mask: 0x01) */ +#define RCU_BDCTL_RTCSRC_Pos (8UL) /*!< RTCSRC (Bit 8) */ +#define RCU_BDCTL_RTCSRC_Msk (0x300UL) /*!< RTCSRC (Bitfield-Mask: 0x03) */ +#define RCU_BDCTL_RTCEN_Pos (15UL) /*!< RTCEN (Bit 15) */ +#define RCU_BDCTL_RTCEN_Msk (0x8000UL) /*!< RTCEN (Bitfield-Mask: 0x01) */ +#define RCU_BDCTL_BKPRST_Pos (16UL) /*!< BKPRST (Bit 16) */ +#define RCU_BDCTL_BKPRST_Msk (0x10000UL) /*!< BKPRST (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSCK ========================================================= */ +#define RCU_RSTSCK_IRC40KEN_Pos (0UL) /*!< IRC40KEN (Bit 0) */ +#define RCU_RSTSCK_IRC40KEN_Msk (0x1UL) /*!< IRC40KEN (Bitfield-Mask: 0x01) */ +#define RCU_RSTSCK_IRC40KSTB_Pos (1UL) /*!< IRC40KSTB (Bit 1) */ +#define RCU_RSTSCK_IRC40KSTB_Msk (0x2UL) /*!< IRC40KSTB (Bitfield-Mask: 0x01) */ +#define RCU_RSTSCK_RSTFC_Pos (24UL) /*!< RSTFC (Bit 24) */ +#define RCU_RSTSCK_RSTFC_Msk (0x1000000UL) /*!< RSTFC (Bitfield-Mask: 0x01) */ +#define RCU_RSTSCK_EPRSTF_Pos (26UL) /*!< EPRSTF (Bit 26) */ +#define RCU_RSTSCK_EPRSTF_Msk (0x4000000UL) /*!< EPRSTF (Bitfield-Mask: 0x01) */ +#define RCU_RSTSCK_PORRSTF_Pos (27UL) /*!< PORRSTF (Bit 27) */ +#define RCU_RSTSCK_PORRSTF_Msk (0x8000000UL) /*!< PORRSTF (Bitfield-Mask: 0x01) */ +#define RCU_RSTSCK_SWRSTF_Pos (28UL) /*!< SWRSTF (Bit 28) */ +#define RCU_RSTSCK_SWRSTF_Msk (0x10000000UL) /*!< SWRSTF (Bitfield-Mask: 0x01) */ +#define RCU_RSTSCK_FWDGTRSTF_Pos (29UL) /*!< FWDGTRSTF (Bit 29) */ +#define RCU_RSTSCK_FWDGTRSTF_Msk (0x20000000UL) /*!< FWDGTRSTF (Bitfield-Mask: 0x01) */ +#define RCU_RSTSCK_WWDGTRSTF_Pos (30UL) /*!< WWDGTRSTF (Bit 30) */ +#define RCU_RSTSCK_WWDGTRSTF_Msk (0x40000000UL) /*!< WWDGTRSTF (Bitfield-Mask: 0x01) */ +#define RCU_RSTSCK_LPRSTF_Pos (31UL) /*!< LPRSTF (Bit 31) */ +#define RCU_RSTSCK_LPRSTF_Msk (0x80000000UL) /*!< LPRSTF (Bitfield-Mask: 0x01) */ +/* ======================================================== AHBRST ========================================================= */ +#define RCU_AHBRST_USBFSRST_Pos (12UL) /*!< USBFSRST (Bit 12) */ +#define RCU_AHBRST_USBFSRST_Msk (0x1000UL) /*!< USBFSRST (Bitfield-Mask: 0x01) */ +/* ========================================================= CFG1 ========================================================== */ +#define RCU_CFG1_PREDV0_Pos (0UL) /*!< PREDV0 (Bit 0) */ +#define RCU_CFG1_PREDV0_Msk (0xfUL) /*!< PREDV0 (Bitfield-Mask: 0x0f) */ +#define RCU_CFG1_PREDV1_Pos (4UL) /*!< PREDV1 (Bit 4) */ +#define RCU_CFG1_PREDV1_Msk (0xf0UL) /*!< PREDV1 (Bitfield-Mask: 0x0f) */ +#define RCU_CFG1_PLL1MF_Pos (8UL) /*!< PLL1MF (Bit 8) */ +#define RCU_CFG1_PLL1MF_Msk (0xf00UL) /*!< PLL1MF (Bitfield-Mask: 0x0f) */ +#define RCU_CFG1_PLL2MF_Pos (12UL) /*!< PLL2MF (Bit 12) */ +#define RCU_CFG1_PLL2MF_Msk (0xf000UL) /*!< PLL2MF (Bitfield-Mask: 0x0f) */ +#define RCU_CFG1_PREDV0SEL_Pos (16UL) /*!< PREDV0SEL (Bit 16) */ +#define RCU_CFG1_PREDV0SEL_Msk (0x10000UL) /*!< PREDV0SEL (Bitfield-Mask: 0x01) */ +#define RCU_CFG1_I2S1SEL_Pos (17UL) /*!< I2S1SEL (Bit 17) */ +#define RCU_CFG1_I2S1SEL_Msk (0x20000UL) /*!< I2S1SEL (Bitfield-Mask: 0x01) */ +#define RCU_CFG1_I2S2SEL_Pos (18UL) /*!< I2S2SEL (Bit 18) */ +#define RCU_CFG1_I2S2SEL_Msk (0x40000UL) /*!< I2S2SEL (Bitfield-Mask: 0x01) */ +/* ========================================================== DSV ========================================================== */ +#define RCU_DSV_DSLPVS_Pos (0UL) /*!< DSLPVS (Bit 0) */ +#define RCU_DSV_DSLPVS_Msk (0x3UL) /*!< DSLPVS (Bitfield-Mask: 0x03) */ + + +/* =========================================================================================================================== */ +/* ================ RTC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= INTEN ========================================================= */ +#define RTC_INTEN_OVIE_Pos (2UL) /*!< OVIE (Bit 2) */ +#define RTC_INTEN_OVIE_Msk (0x4UL) /*!< OVIE (Bitfield-Mask: 0x01) */ +#define RTC_INTEN_ALRMIE_Pos (1UL) /*!< ALRMIE (Bit 1) */ +#define RTC_INTEN_ALRMIE_Msk (0x2UL) /*!< ALRMIE (Bitfield-Mask: 0x01) */ +#define RTC_INTEN_SCIE_Pos (0UL) /*!< SCIE (Bit 0) */ +#define RTC_INTEN_SCIE_Msk (0x1UL) /*!< SCIE (Bitfield-Mask: 0x01) */ +/* ========================================================== CTL ========================================================== */ +#define RTC_CTL_LWOFF_Pos (5UL) /*!< LWOFF (Bit 5) */ +#define RTC_CTL_LWOFF_Msk (0x20UL) /*!< LWOFF (Bitfield-Mask: 0x01) */ +#define RTC_CTL_CMF_Pos (4UL) /*!< CMF (Bit 4) */ +#define RTC_CTL_CMF_Msk (0x10UL) /*!< CMF (Bitfield-Mask: 0x01) */ +#define RTC_CTL_RSYNF_Pos (3UL) /*!< RSYNF (Bit 3) */ +#define RTC_CTL_RSYNF_Msk (0x8UL) /*!< RSYNF (Bitfield-Mask: 0x01) */ +#define RTC_CTL_OVIF_Pos (2UL) /*!< OVIF (Bit 2) */ +#define RTC_CTL_OVIF_Msk (0x4UL) /*!< OVIF (Bitfield-Mask: 0x01) */ +#define RTC_CTL_ALRMIF_Pos (1UL) /*!< ALRMIF (Bit 1) */ +#define RTC_CTL_ALRMIF_Msk (0x2UL) /*!< ALRMIF (Bitfield-Mask: 0x01) */ +#define RTC_CTL_SCIF_Pos (0UL) /*!< SCIF (Bit 0) */ +#define RTC_CTL_SCIF_Msk (0x1UL) /*!< SCIF (Bitfield-Mask: 0x01) */ +/* ========================================================= PSCH ========================================================== */ +#define RTC_PSCH_PSC_Pos (0UL) /*!< PSC (Bit 0) */ +#define RTC_PSCH_PSC_Msk (0xfUL) /*!< PSC (Bitfield-Mask: 0x0f) */ +/* ========================================================= PSCL ========================================================== */ +#define RTC_PSCL_PSC_Pos (0UL) /*!< PSC (Bit 0) */ +#define RTC_PSCL_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */ +/* ========================================================= DIVH ========================================================== */ +#define RTC_DIVH_DIV_Pos (0UL) /*!< DIV (Bit 0) */ +#define RTC_DIVH_DIV_Msk (0xfUL) /*!< DIV (Bitfield-Mask: 0x0f) */ +/* ========================================================= DIVL ========================================================== */ +#define RTC_DIVL_DIV_Pos (0UL) /*!< DIV (Bit 0) */ +#define RTC_DIVL_DIV_Msk (0xffffUL) /*!< DIV (Bitfield-Mask: 0xffff) */ +/* ========================================================= CNTH ========================================================== */ +#define RTC_CNTH_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define RTC_CNTH_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ========================================================= CNTL ========================================================== */ +#define RTC_CNTL_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define RTC_CNTL_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ========================================================= ALRMH ========================================================= */ +#define RTC_ALRMH_ALRM_Pos (0UL) /*!< ALRM (Bit 0) */ +#define RTC_ALRMH_ALRM_Msk (0xffffUL) /*!< ALRM (Bitfield-Mask: 0xffff) */ +/* ========================================================= ALRML ========================================================= */ +#define RTC_ALRML_ALRM_Pos (0UL) /*!< ALRM (Bit 0) */ +#define RTC_ALRML_ALRM_Msk (0xffffUL) /*!< ALRM (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTL0 ========================================================== */ +#define SPI0_CTL0_BDEN_Pos (15UL) /*!< BDEN (Bit 15) */ +#define SPI0_CTL0_BDEN_Msk (0x8000UL) /*!< BDEN (Bitfield-Mask: 0x01) */ +#define SPI0_CTL0_BDOEN_Pos (14UL) /*!< BDOEN (Bit 14) */ +#define SPI0_CTL0_BDOEN_Msk (0x4000UL) /*!< BDOEN (Bitfield-Mask: 0x01) */ +#define SPI0_CTL0_CRCEN_Pos (13UL) /*!< CRCEN (Bit 13) */ +#define SPI0_CTL0_CRCEN_Msk (0x2000UL) /*!< CRCEN (Bitfield-Mask: 0x01) */ +#define SPI0_CTL0_CRCNT_Pos (12UL) /*!< CRCNT (Bit 12) */ +#define SPI0_CTL0_CRCNT_Msk (0x1000UL) /*!< CRCNT (Bitfield-Mask: 0x01) */ +#define SPI0_CTL0_FF16_Pos (11UL) /*!< FF16 (Bit 11) */ +#define SPI0_CTL0_FF16_Msk (0x800UL) /*!< FF16 (Bitfield-Mask: 0x01) */ +#define SPI0_CTL0_RO_Pos (10UL) /*!< RO (Bit 10) */ +#define SPI0_CTL0_RO_Msk (0x400UL) /*!< RO (Bitfield-Mask: 0x01) */ +#define SPI0_CTL0_SWNSSEN_Pos (9UL) /*!< SWNSSEN (Bit 9) */ +#define SPI0_CTL0_SWNSSEN_Msk (0x200UL) /*!< SWNSSEN (Bitfield-Mask: 0x01) */ +#define SPI0_CTL0_SWNSS_Pos (8UL) /*!< SWNSS (Bit 8) */ +#define SPI0_CTL0_SWNSS_Msk (0x100UL) /*!< SWNSS (Bitfield-Mask: 0x01) */ +#define SPI0_CTL0_LF_Pos (7UL) /*!< LF (Bit 7) */ +#define SPI0_CTL0_LF_Msk (0x80UL) /*!< LF (Bitfield-Mask: 0x01) */ +#define SPI0_CTL0_SPIEN_Pos (6UL) /*!< SPIEN (Bit 6) */ +#define SPI0_CTL0_SPIEN_Msk (0x40UL) /*!< SPIEN (Bitfield-Mask: 0x01) */ +#define SPI0_CTL0_PSC_Pos (3UL) /*!< PSC (Bit 3) */ +#define SPI0_CTL0_PSC_Msk (0x38UL) /*!< PSC (Bitfield-Mask: 0x07) */ +#define SPI0_CTL0_MSTMOD_Pos (2UL) /*!< MSTMOD (Bit 2) */ +#define SPI0_CTL0_MSTMOD_Msk (0x4UL) /*!< MSTMOD (Bitfield-Mask: 0x01) */ +#define SPI0_CTL0_CKPL_Pos (1UL) /*!< CKPL (Bit 1) */ +#define SPI0_CTL0_CKPL_Msk (0x2UL) /*!< CKPL (Bitfield-Mask: 0x01) */ +#define SPI0_CTL0_CKPH_Pos (0UL) /*!< CKPH (Bit 0) */ +#define SPI0_CTL0_CKPH_Msk (0x1UL) /*!< CKPH (Bitfield-Mask: 0x01) */ +/* ========================================================= CTL1 ========================================================== */ +#define SPI0_CTL1_TBEIE_Pos (7UL) /*!< TBEIE (Bit 7) */ +#define SPI0_CTL1_TBEIE_Msk (0x80UL) /*!< TBEIE (Bitfield-Mask: 0x01) */ +#define SPI0_CTL1_RBNEIE_Pos (6UL) /*!< RBNEIE (Bit 6) */ +#define SPI0_CTL1_RBNEIE_Msk (0x40UL) /*!< RBNEIE (Bitfield-Mask: 0x01) */ +#define SPI0_CTL1_ERRIE_Pos (5UL) /*!< ERRIE (Bit 5) */ +#define SPI0_CTL1_ERRIE_Msk (0x20UL) /*!< ERRIE (Bitfield-Mask: 0x01) */ +#define SPI0_CTL1_TMOD_Pos (4UL) /*!< TMOD (Bit 4) */ +#define SPI0_CTL1_TMOD_Msk (0x10UL) /*!< TMOD (Bitfield-Mask: 0x01) */ +#define SPI0_CTL1_NSSP_Pos (3UL) /*!< NSSP (Bit 3) */ +#define SPI0_CTL1_NSSP_Msk (0x8UL) /*!< NSSP (Bitfield-Mask: 0x01) */ +#define SPI0_CTL1_NSSDRV_Pos (2UL) /*!< NSSDRV (Bit 2) */ +#define SPI0_CTL1_NSSDRV_Msk (0x4UL) /*!< NSSDRV (Bitfield-Mask: 0x01) */ +#define SPI0_CTL1_DMATEN_Pos (1UL) /*!< DMATEN (Bit 1) */ +#define SPI0_CTL1_DMATEN_Msk (0x2UL) /*!< DMATEN (Bitfield-Mask: 0x01) */ +#define SPI0_CTL1_DMAREN_Pos (0UL) /*!< DMAREN (Bit 0) */ +#define SPI0_CTL1_DMAREN_Msk (0x1UL) /*!< DMAREN (Bitfield-Mask: 0x01) */ +/* ========================================================= STAT ========================================================== */ +#define SPI0_STAT_FERR_Pos (8UL) /*!< FERR (Bit 8) */ +#define SPI0_STAT_FERR_Msk (0x100UL) /*!< FERR (Bitfield-Mask: 0x01) */ +#define SPI0_STAT_TRANS_Pos (7UL) /*!< TRANS (Bit 7) */ +#define SPI0_STAT_TRANS_Msk (0x80UL) /*!< TRANS (Bitfield-Mask: 0x01) */ +#define SPI0_STAT_RXORERR_Pos (6UL) /*!< RXORERR (Bit 6) */ +#define SPI0_STAT_RXORERR_Msk (0x40UL) /*!< RXORERR (Bitfield-Mask: 0x01) */ +#define SPI0_STAT_CONFERR_Pos (5UL) /*!< CONFERR (Bit 5) */ +#define SPI0_STAT_CONFERR_Msk (0x20UL) /*!< CONFERR (Bitfield-Mask: 0x01) */ +#define SPI0_STAT_CRCERR_Pos (4UL) /*!< CRCERR (Bit 4) */ +#define SPI0_STAT_CRCERR_Msk (0x10UL) /*!< CRCERR (Bitfield-Mask: 0x01) */ +#define SPI0_STAT_TXURERR_Pos (3UL) /*!< TXURERR (Bit 3) */ +#define SPI0_STAT_TXURERR_Msk (0x8UL) /*!< TXURERR (Bitfield-Mask: 0x01) */ +#define SPI0_STAT_I2SCH_Pos (2UL) /*!< I2SCH (Bit 2) */ +#define SPI0_STAT_I2SCH_Msk (0x4UL) /*!< I2SCH (Bitfield-Mask: 0x01) */ +#define SPI0_STAT_TBE_Pos (1UL) /*!< TBE (Bit 1) */ +#define SPI0_STAT_TBE_Msk (0x2UL) /*!< TBE (Bitfield-Mask: 0x01) */ +#define SPI0_STAT_RBNE_Pos (0UL) /*!< RBNE (Bit 0) */ +#define SPI0_STAT_RBNE_Msk (0x1UL) /*!< RBNE (Bitfield-Mask: 0x01) */ +/* ========================================================= DATA ========================================================== */ +#define SPI0_DATA_SPI_DATA_Pos (0UL) /*!< SPI_DATA (Bit 0) */ +#define SPI0_DATA_SPI_DATA_Msk (0xffffUL) /*!< SPI_DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== CRCPOLY ======================================================== */ +#define SPI0_CRCPOLY_CRCPOLY_Pos (0UL) /*!< CRCPOLY (Bit 0) */ +#define SPI0_CRCPOLY_CRCPOLY_Msk (0xffffUL) /*!< CRCPOLY (Bitfield-Mask: 0xffff) */ +/* ========================================================= RCRC ========================================================== */ +#define SPI0_RCRC_RCRC_Pos (0UL) /*!< RCRC (Bit 0) */ +#define SPI0_RCRC_RCRC_Msk (0xffffUL) /*!< RCRC (Bitfield-Mask: 0xffff) */ +/* ========================================================= TCRC ========================================================== */ +#define SPI0_TCRC_TCRC_Pos (0UL) /*!< TCRC (Bit 0) */ +#define SPI0_TCRC_TCRC_Msk (0xffffUL) /*!< TCRC (Bitfield-Mask: 0xffff) */ +/* ======================================================== I2SCTL ========================================================= */ +#define SPI0_I2SCTL_I2SSEL_Pos (11UL) /*!< I2SSEL (Bit 11) */ +#define SPI0_I2SCTL_I2SSEL_Msk (0x800UL) /*!< I2SSEL (Bitfield-Mask: 0x01) */ +#define SPI0_I2SCTL_I2SEN_Pos (10UL) /*!< I2SEN (Bit 10) */ +#define SPI0_I2SCTL_I2SEN_Msk (0x400UL) /*!< I2SEN (Bitfield-Mask: 0x01) */ +#define SPI0_I2SCTL_I2SOPMOD_Pos (8UL) /*!< I2SOPMOD (Bit 8) */ +#define SPI0_I2SCTL_I2SOPMOD_Msk (0x300UL) /*!< I2SOPMOD (Bitfield-Mask: 0x03) */ +#define SPI0_I2SCTL_PCMSMOD_Pos (7UL) /*!< PCMSMOD (Bit 7) */ +#define SPI0_I2SCTL_PCMSMOD_Msk (0x80UL) /*!< PCMSMOD (Bitfield-Mask: 0x01) */ +#define SPI0_I2SCTL_I2SSTD_Pos (4UL) /*!< I2SSTD (Bit 4) */ +#define SPI0_I2SCTL_I2SSTD_Msk (0x30UL) /*!< I2SSTD (Bitfield-Mask: 0x03) */ +#define SPI0_I2SCTL_CKPL_Pos (3UL) /*!< CKPL (Bit 3) */ +#define SPI0_I2SCTL_CKPL_Msk (0x8UL) /*!< CKPL (Bitfield-Mask: 0x01) */ +#define SPI0_I2SCTL_DTLEN_Pos (1UL) /*!< DTLEN (Bit 1) */ +#define SPI0_I2SCTL_DTLEN_Msk (0x6UL) /*!< DTLEN (Bitfield-Mask: 0x03) */ +#define SPI0_I2SCTL_CHLEN_Pos (0UL) /*!< CHLEN (Bit 0) */ +#define SPI0_I2SCTL_CHLEN_Msk (0x1UL) /*!< CHLEN (Bitfield-Mask: 0x01) */ +/* ======================================================== I2SPSC ========================================================= */ +#define SPI0_I2SPSC_MCKOEN_Pos (9UL) /*!< MCKOEN (Bit 9) */ +#define SPI0_I2SPSC_MCKOEN_Msk (0x200UL) /*!< MCKOEN (Bitfield-Mask: 0x01) */ +#define SPI0_I2SPSC_OF_Pos (8UL) /*!< OF (Bit 8) */ +#define SPI0_I2SPSC_OF_Msk (0x100UL) /*!< OF (Bitfield-Mask: 0x01) */ +#define SPI0_I2SPSC_DIV_Pos (0UL) /*!< DIV (Bit 0) */ +#define SPI0_I2SPSC_DIV_Msk (0xffUL) /*!< DIV (Bitfield-Mask: 0xff) */ + + +/* =========================================================================================================================== */ +/* ================ TIMER0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTL0 ========================================================== */ +#define TIMER0_CTL0_CKDIV_Pos (8UL) /*!< CKDIV (Bit 8) */ +#define TIMER0_CTL0_CKDIV_Msk (0x300UL) /*!< CKDIV (Bitfield-Mask: 0x03) */ +#define TIMER0_CTL0_ARSE_Pos (7UL) /*!< ARSE (Bit 7) */ +#define TIMER0_CTL0_ARSE_Msk (0x80UL) /*!< ARSE (Bitfield-Mask: 0x01) */ +#define TIMER0_CTL0_CAM_Pos (5UL) /*!< CAM (Bit 5) */ +#define TIMER0_CTL0_CAM_Msk (0x60UL) /*!< CAM (Bitfield-Mask: 0x03) */ +#define TIMER0_CTL0_DIR_Pos (4UL) /*!< DIR (Bit 4) */ +#define TIMER0_CTL0_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +#define TIMER0_CTL0_SPM_Pos (3UL) /*!< SPM (Bit 3) */ +#define TIMER0_CTL0_SPM_Msk (0x8UL) /*!< SPM (Bitfield-Mask: 0x01) */ +#define TIMER0_CTL0_UPS_Pos (2UL) /*!< UPS (Bit 2) */ +#define TIMER0_CTL0_UPS_Msk (0x4UL) /*!< UPS (Bitfield-Mask: 0x01) */ +#define TIMER0_CTL0_UPDIS_Pos (1UL) /*!< UPDIS (Bit 1) */ +#define TIMER0_CTL0_UPDIS_Msk (0x2UL) /*!< UPDIS (Bitfield-Mask: 0x01) */ +#define TIMER0_CTL0_CEN_Pos (0UL) /*!< CEN (Bit 0) */ +#define TIMER0_CTL0_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */ +/* ========================================================= CTL1 ========================================================== */ +#define TIMER0_CTL1_ISO3_Pos (14UL) /*!< ISO3 (Bit 14) */ +#define TIMER0_CTL1_ISO3_Msk (0x4000UL) /*!< ISO3 (Bitfield-Mask: 0x01) */ +#define TIMER0_CTL1_ISO2N_Pos (13UL) /*!< ISO2N (Bit 13) */ +#define TIMER0_CTL1_ISO2N_Msk (0x2000UL) /*!< ISO2N (Bitfield-Mask: 0x01) */ +#define TIMER0_CTL1_ISO2_Pos (12UL) /*!< ISO2 (Bit 12) */ +#define TIMER0_CTL1_ISO2_Msk (0x1000UL) /*!< ISO2 (Bitfield-Mask: 0x01) */ +#define TIMER0_CTL1_ISO1N_Pos (11UL) /*!< ISO1N (Bit 11) */ +#define TIMER0_CTL1_ISO1N_Msk (0x800UL) /*!< ISO1N (Bitfield-Mask: 0x01) */ +#define TIMER0_CTL1_ISO1_Pos (10UL) /*!< ISO1 (Bit 10) */ +#define TIMER0_CTL1_ISO1_Msk (0x400UL) /*!< ISO1 (Bitfield-Mask: 0x01) */ +#define TIMER0_CTL1_ISO0N_Pos (9UL) /*!< ISO0N (Bit 9) */ +#define TIMER0_CTL1_ISO0N_Msk (0x200UL) /*!< ISO0N (Bitfield-Mask: 0x01) */ +#define TIMER0_CTL1_ISO0_Pos (8UL) /*!< ISO0 (Bit 8) */ +#define TIMER0_CTL1_ISO0_Msk (0x100UL) /*!< ISO0 (Bitfield-Mask: 0x01) */ +#define TIMER0_CTL1_TI0S_Pos (7UL) /*!< TI0S (Bit 7) */ +#define TIMER0_CTL1_TI0S_Msk (0x80UL) /*!< TI0S (Bitfield-Mask: 0x01) */ +#define TIMER0_CTL1_MMC_Pos (4UL) /*!< MMC (Bit 4) */ +#define TIMER0_CTL1_MMC_Msk (0x70UL) /*!< MMC (Bitfield-Mask: 0x07) */ +#define TIMER0_CTL1_DMAS_Pos (3UL) /*!< DMAS (Bit 3) */ +#define TIMER0_CTL1_DMAS_Msk (0x8UL) /*!< DMAS (Bitfield-Mask: 0x01) */ +#define TIMER0_CTL1_CCUC_Pos (2UL) /*!< CCUC (Bit 2) */ +#define TIMER0_CTL1_CCUC_Msk (0x4UL) /*!< CCUC (Bitfield-Mask: 0x01) */ +#define TIMER0_CTL1_CCSE_Pos (0UL) /*!< CCSE (Bit 0) */ +#define TIMER0_CTL1_CCSE_Msk (0x1UL) /*!< CCSE (Bitfield-Mask: 0x01) */ +/* ========================================================= SMCFG ========================================================= */ +#define TIMER0_SMCFG_ETP_Pos (15UL) /*!< ETP (Bit 15) */ +#define TIMER0_SMCFG_ETP_Msk (0x8000UL) /*!< ETP (Bitfield-Mask: 0x01) */ +#define TIMER0_SMCFG_SMC1_Pos (14UL) /*!< SMC1 (Bit 14) */ +#define TIMER0_SMCFG_SMC1_Msk (0x4000UL) /*!< SMC1 (Bitfield-Mask: 0x01) */ +#define TIMER0_SMCFG_ETPSC_Pos (12UL) /*!< ETPSC (Bit 12) */ +#define TIMER0_SMCFG_ETPSC_Msk (0x3000UL) /*!< ETPSC (Bitfield-Mask: 0x03) */ +#define TIMER0_SMCFG_ETFC_Pos (8UL) /*!< ETFC (Bit 8) */ +#define TIMER0_SMCFG_ETFC_Msk (0xf00UL) /*!< ETFC (Bitfield-Mask: 0x0f) */ +#define TIMER0_SMCFG_MSM_Pos (7UL) /*!< MSM (Bit 7) */ +#define TIMER0_SMCFG_MSM_Msk (0x80UL) /*!< MSM (Bitfield-Mask: 0x01) */ +#define TIMER0_SMCFG_TRGS_Pos (4UL) /*!< TRGS (Bit 4) */ +#define TIMER0_SMCFG_TRGS_Msk (0x70UL) /*!< TRGS (Bitfield-Mask: 0x07) */ +#define TIMER0_SMCFG_SMC_Pos (0UL) /*!< SMC (Bit 0) */ +#define TIMER0_SMCFG_SMC_Msk (0x7UL) /*!< SMC (Bitfield-Mask: 0x07) */ +/* ======================================================= DMAINTEN ======================================================== */ +#define TIMER0_DMAINTEN_TRGDEN_Pos (14UL) /*!< TRGDEN (Bit 14) */ +#define TIMER0_DMAINTEN_TRGDEN_Msk (0x4000UL) /*!< TRGDEN (Bitfield-Mask: 0x01) */ +#define TIMER0_DMAINTEN_CMTDEN_Pos (13UL) /*!< CMTDEN (Bit 13) */ +#define TIMER0_DMAINTEN_CMTDEN_Msk (0x2000UL) /*!< CMTDEN (Bitfield-Mask: 0x01) */ +#define TIMER0_DMAINTEN_CH3DEN_Pos (12UL) /*!< CH3DEN (Bit 12) */ +#define TIMER0_DMAINTEN_CH3DEN_Msk (0x1000UL) /*!< CH3DEN (Bitfield-Mask: 0x01) */ +#define TIMER0_DMAINTEN_CH2DEN_Pos (11UL) /*!< CH2DEN (Bit 11) */ +#define TIMER0_DMAINTEN_CH2DEN_Msk (0x800UL) /*!< CH2DEN (Bitfield-Mask: 0x01) */ +#define TIMER0_DMAINTEN_CH1DEN_Pos (10UL) /*!< CH1DEN (Bit 10) */ +#define TIMER0_DMAINTEN_CH1DEN_Msk (0x400UL) /*!< CH1DEN (Bitfield-Mask: 0x01) */ +#define TIMER0_DMAINTEN_CH0DEN_Pos (9UL) /*!< CH0DEN (Bit 9) */ +#define TIMER0_DMAINTEN_CH0DEN_Msk (0x200UL) /*!< CH0DEN (Bitfield-Mask: 0x01) */ +#define TIMER0_DMAINTEN_UPDEN_Pos (8UL) /*!< UPDEN (Bit 8) */ +#define TIMER0_DMAINTEN_UPDEN_Msk (0x100UL) /*!< UPDEN (Bitfield-Mask: 0x01) */ +#define TIMER0_DMAINTEN_BRKIE_Pos (7UL) /*!< BRKIE (Bit 7) */ +#define TIMER0_DMAINTEN_BRKIE_Msk (0x80UL) /*!< BRKIE (Bitfield-Mask: 0x01) */ +#define TIMER0_DMAINTEN_TRGIE_Pos (6UL) /*!< TRGIE (Bit 6) */ +#define TIMER0_DMAINTEN_TRGIE_Msk (0x40UL) /*!< TRGIE (Bitfield-Mask: 0x01) */ +#define TIMER0_DMAINTEN_CMTIE_Pos (5UL) /*!< CMTIE (Bit 5) */ +#define TIMER0_DMAINTEN_CMTIE_Msk (0x20UL) /*!< CMTIE (Bitfield-Mask: 0x01) */ +#define TIMER0_DMAINTEN_CH3IE_Pos (4UL) /*!< CH3IE (Bit 4) */ +#define TIMER0_DMAINTEN_CH3IE_Msk (0x10UL) /*!< CH3IE (Bitfield-Mask: 0x01) */ +#define TIMER0_DMAINTEN_CH2IE_Pos (3UL) /*!< CH2IE (Bit 3) */ +#define TIMER0_DMAINTEN_CH2IE_Msk (0x8UL) /*!< CH2IE (Bitfield-Mask: 0x01) */ +#define TIMER0_DMAINTEN_CH1IE_Pos (2UL) /*!< CH1IE (Bit 2) */ +#define TIMER0_DMAINTEN_CH1IE_Msk (0x4UL) /*!< CH1IE (Bitfield-Mask: 0x01) */ +#define TIMER0_DMAINTEN_CH0IE_Pos (1UL) /*!< CH0IE (Bit 1) */ +#define TIMER0_DMAINTEN_CH0IE_Msk (0x2UL) /*!< CH0IE (Bitfield-Mask: 0x01) */ +#define TIMER0_DMAINTEN_UPIE_Pos (0UL) /*!< UPIE (Bit 0) */ +#define TIMER0_DMAINTEN_UPIE_Msk (0x1UL) /*!< UPIE (Bitfield-Mask: 0x01) */ +/* ========================================================= INTF ========================================================== */ +#define TIMER0_INTF_CH3OF_Pos (12UL) /*!< CH3OF (Bit 12) */ +#define TIMER0_INTF_CH3OF_Msk (0x1000UL) /*!< CH3OF (Bitfield-Mask: 0x01) */ +#define TIMER0_INTF_CH2OF_Pos (11UL) /*!< CH2OF (Bit 11) */ +#define TIMER0_INTF_CH2OF_Msk (0x800UL) /*!< CH2OF (Bitfield-Mask: 0x01) */ +#define TIMER0_INTF_CH1OF_Pos (10UL) /*!< CH1OF (Bit 10) */ +#define TIMER0_INTF_CH1OF_Msk (0x400UL) /*!< CH1OF (Bitfield-Mask: 0x01) */ +#define TIMER0_INTF_CH0OF_Pos (9UL) /*!< CH0OF (Bit 9) */ +#define TIMER0_INTF_CH0OF_Msk (0x200UL) /*!< CH0OF (Bitfield-Mask: 0x01) */ +#define TIMER0_INTF_BRKIF_Pos (7UL) /*!< BRKIF (Bit 7) */ +#define TIMER0_INTF_BRKIF_Msk (0x80UL) /*!< BRKIF (Bitfield-Mask: 0x01) */ +#define TIMER0_INTF_TRGIF_Pos (6UL) /*!< TRGIF (Bit 6) */ +#define TIMER0_INTF_TRGIF_Msk (0x40UL) /*!< TRGIF (Bitfield-Mask: 0x01) */ +#define TIMER0_INTF_CMTIF_Pos (5UL) /*!< CMTIF (Bit 5) */ +#define TIMER0_INTF_CMTIF_Msk (0x20UL) /*!< CMTIF (Bitfield-Mask: 0x01) */ +#define TIMER0_INTF_CH3IF_Pos (4UL) /*!< CH3IF (Bit 4) */ +#define TIMER0_INTF_CH3IF_Msk (0x10UL) /*!< CH3IF (Bitfield-Mask: 0x01) */ +#define TIMER0_INTF_CH2IF_Pos (3UL) /*!< CH2IF (Bit 3) */ +#define TIMER0_INTF_CH2IF_Msk (0x8UL) /*!< CH2IF (Bitfield-Mask: 0x01) */ +#define TIMER0_INTF_CH1IF_Pos (2UL) /*!< CH1IF (Bit 2) */ +#define TIMER0_INTF_CH1IF_Msk (0x4UL) /*!< CH1IF (Bitfield-Mask: 0x01) */ +#define TIMER0_INTF_CH0IF_Pos (1UL) /*!< CH0IF (Bit 1) */ +#define TIMER0_INTF_CH0IF_Msk (0x2UL) /*!< CH0IF (Bitfield-Mask: 0x01) */ +#define TIMER0_INTF_UPIF_Pos (0UL) /*!< UPIF (Bit 0) */ +#define TIMER0_INTF_UPIF_Msk (0x1UL) /*!< UPIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SWEVG ========================================================= */ +#define TIMER0_SWEVG_BRKG_Pos (7UL) /*!< BRKG (Bit 7) */ +#define TIMER0_SWEVG_BRKG_Msk (0x80UL) /*!< BRKG (Bitfield-Mask: 0x01) */ +#define TIMER0_SWEVG_TRGG_Pos (6UL) /*!< TRGG (Bit 6) */ +#define TIMER0_SWEVG_TRGG_Msk (0x40UL) /*!< TRGG (Bitfield-Mask: 0x01) */ +#define TIMER0_SWEVG_CMTG_Pos (5UL) /*!< CMTG (Bit 5) */ +#define TIMER0_SWEVG_CMTG_Msk (0x20UL) /*!< CMTG (Bitfield-Mask: 0x01) */ +#define TIMER0_SWEVG_CH3G_Pos (4UL) /*!< CH3G (Bit 4) */ +#define TIMER0_SWEVG_CH3G_Msk (0x10UL) /*!< CH3G (Bitfield-Mask: 0x01) */ +#define TIMER0_SWEVG_CH2G_Pos (3UL) /*!< CH2G (Bit 3) */ +#define TIMER0_SWEVG_CH2G_Msk (0x8UL) /*!< CH2G (Bitfield-Mask: 0x01) */ +#define TIMER0_SWEVG_CH1G_Pos (2UL) /*!< CH1G (Bit 2) */ +#define TIMER0_SWEVG_CH1G_Msk (0x4UL) /*!< CH1G (Bitfield-Mask: 0x01) */ +#define TIMER0_SWEVG_CH0G_Pos (1UL) /*!< CH0G (Bit 1) */ +#define TIMER0_SWEVG_CH0G_Msk (0x2UL) /*!< CH0G (Bitfield-Mask: 0x01) */ +#define TIMER0_SWEVG_UPG_Pos (0UL) /*!< UPG (Bit 0) */ +#define TIMER0_SWEVG_UPG_Msk (0x1UL) /*!< UPG (Bitfield-Mask: 0x01) */ +/* ===================================================== CHCTL0_Output ===================================================== */ +#define TIMER0_CHCTL0_Output_CH1COMCEN_Pos (15UL) /*!< CH1COMCEN (Bit 15) */ +#define TIMER0_CHCTL0_Output_CH1COMCEN_Msk (0x8000UL) /*!< CH1COMCEN (Bitfield-Mask: 0x01) */ +#define TIMER0_CHCTL0_Output_CH1COMCTL_Pos (12UL) /*!< CH1COMCTL (Bit 12) */ +#define TIMER0_CHCTL0_Output_CH1COMCTL_Msk (0x7000UL) /*!< CH1COMCTL (Bitfield-Mask: 0x07) */ +#define TIMER0_CHCTL0_Output_CH1COMSEN_Pos (11UL) /*!< CH1COMSEN (Bit 11) */ +#define TIMER0_CHCTL0_Output_CH1COMSEN_Msk (0x800UL) /*!< CH1COMSEN (Bitfield-Mask: 0x01) */ +#define TIMER0_CHCTL0_Output_CH1COMFEN_Pos (10UL) /*!< CH1COMFEN (Bit 10) */ +#define TIMER0_CHCTL0_Output_CH1COMFEN_Msk (0x400UL) /*!< CH1COMFEN (Bitfield-Mask: 0x01) */ +#define TIMER0_CHCTL0_Output_CH1MS_Pos (8UL) /*!< CH1MS (Bit 8) */ +#define TIMER0_CHCTL0_Output_CH1MS_Msk (0x300UL) /*!< CH1MS (Bitfield-Mask: 0x03) */ +#define TIMER0_CHCTL0_Output_CH0COMCEN_Pos (7UL) /*!< CH0COMCEN (Bit 7) */ +#define TIMER0_CHCTL0_Output_CH0COMCEN_Msk (0x80UL) /*!< CH0COMCEN (Bitfield-Mask: 0x01) */ +#define TIMER0_CHCTL0_Output_CH0COMCTL_Pos (4UL) /*!< CH0COMCTL (Bit 4) */ +#define TIMER0_CHCTL0_Output_CH0COMCTL_Msk (0x70UL) /*!< CH0COMCTL (Bitfield-Mask: 0x07) */ +#define TIMER0_CHCTL0_Output_CH0COMSEN_Pos (3UL) /*!< CH0COMSEN (Bit 3) */ +#define TIMER0_CHCTL0_Output_CH0COMSEN_Msk (0x8UL) /*!< CH0COMSEN (Bitfield-Mask: 0x01) */ +#define TIMER0_CHCTL0_Output_CH0COMFEN_Pos (2UL) /*!< CH0COMFEN (Bit 2) */ +#define TIMER0_CHCTL0_Output_CH0COMFEN_Msk (0x4UL) /*!< CH0COMFEN (Bitfield-Mask: 0x01) */ +#define TIMER0_CHCTL0_Output_CH0MS_Pos (0UL) /*!< CH0MS (Bit 0) */ +#define TIMER0_CHCTL0_Output_CH0MS_Msk (0x3UL) /*!< CH0MS (Bitfield-Mask: 0x03) */ +/* ===================================================== CHCTL0_Input ====================================================== */ +#define TIMER0_CHCTL0_Input_CH1CAPFLT_Pos (12UL) /*!< CH1CAPFLT (Bit 12) */ +#define TIMER0_CHCTL0_Input_CH1CAPFLT_Msk (0xf000UL) /*!< CH1CAPFLT (Bitfield-Mask: 0x0f) */ +#define TIMER0_CHCTL0_Input_CH1CAPPSC_Pos (10UL) /*!< CH1CAPPSC (Bit 10) */ +#define TIMER0_CHCTL0_Input_CH1CAPPSC_Msk (0xc00UL) /*!< CH1CAPPSC (Bitfield-Mask: 0x03) */ +#define TIMER0_CHCTL0_Input_CH1MS_Pos (8UL) /*!< CH1MS (Bit 8) */ +#define TIMER0_CHCTL0_Input_CH1MS_Msk (0x300UL) /*!< CH1MS (Bitfield-Mask: 0x03) */ +#define TIMER0_CHCTL0_Input_CH0CAPFLT_Pos (4UL) /*!< CH0CAPFLT (Bit 4) */ +#define TIMER0_CHCTL0_Input_CH0CAPFLT_Msk (0xf0UL) /*!< CH0CAPFLT (Bitfield-Mask: 0x0f) */ +#define TIMER0_CHCTL0_Input_CH0CAPPSC_Pos (2UL) /*!< CH0CAPPSC (Bit 2) */ +#define TIMER0_CHCTL0_Input_CH0CAPPSC_Msk (0xcUL) /*!< CH0CAPPSC (Bitfield-Mask: 0x03) */ +#define TIMER0_CHCTL0_Input_CH0MS_Pos (0UL) /*!< CH0MS (Bit 0) */ +#define TIMER0_CHCTL0_Input_CH0MS_Msk (0x3UL) /*!< CH0MS (Bitfield-Mask: 0x03) */ +/* ===================================================== CHCTL1_Output ===================================================== */ +#define TIMER0_CHCTL1_Output_CH3COMCEN_Pos (15UL) /*!< CH3COMCEN (Bit 15) */ +#define TIMER0_CHCTL1_Output_CH3COMCEN_Msk (0x8000UL) /*!< CH3COMCEN (Bitfield-Mask: 0x01) */ +#define TIMER0_CHCTL1_Output_CH3COMCTL_Pos (12UL) /*!< CH3COMCTL (Bit 12) */ +#define TIMER0_CHCTL1_Output_CH3COMCTL_Msk (0x7000UL) /*!< CH3COMCTL (Bitfield-Mask: 0x07) */ +#define TIMER0_CHCTL1_Output_CH3COMSEN_Pos (11UL) /*!< CH3COMSEN (Bit 11) */ +#define TIMER0_CHCTL1_Output_CH3COMSEN_Msk (0x800UL) /*!< CH3COMSEN (Bitfield-Mask: 0x01) */ +#define TIMER0_CHCTL1_Output_CH3COMFEN_Pos (10UL) /*!< CH3COMFEN (Bit 10) */ +#define TIMER0_CHCTL1_Output_CH3COMFEN_Msk (0x400UL) /*!< CH3COMFEN (Bitfield-Mask: 0x01) */ +#define TIMER0_CHCTL1_Output_CH3MS_Pos (8UL) /*!< CH3MS (Bit 8) */ +#define TIMER0_CHCTL1_Output_CH3MS_Msk (0x300UL) /*!< CH3MS (Bitfield-Mask: 0x03) */ +#define TIMER0_CHCTL1_Output_CH2COMCEN_Pos (7UL) /*!< CH2COMCEN (Bit 7) */ +#define TIMER0_CHCTL1_Output_CH2COMCEN_Msk (0x80UL) /*!< CH2COMCEN (Bitfield-Mask: 0x01) */ +#define TIMER0_CHCTL1_Output_CH2COMCTL_Pos (4UL) /*!< CH2COMCTL (Bit 4) */ +#define TIMER0_CHCTL1_Output_CH2COMCTL_Msk (0x70UL) /*!< CH2COMCTL (Bitfield-Mask: 0x07) */ +#define TIMER0_CHCTL1_Output_CH2COMSEN_Pos (3UL) /*!< CH2COMSEN (Bit 3) */ +#define TIMER0_CHCTL1_Output_CH2COMSEN_Msk (0x8UL) /*!< CH2COMSEN (Bitfield-Mask: 0x01) */ +#define TIMER0_CHCTL1_Output_CH2COMFEN_Pos (2UL) /*!< CH2COMFEN (Bit 2) */ +#define TIMER0_CHCTL1_Output_CH2COMFEN_Msk (0x4UL) /*!< CH2COMFEN (Bitfield-Mask: 0x01) */ +#define TIMER0_CHCTL1_Output_CH2MS_Pos (0UL) /*!< CH2MS (Bit 0) */ +#define TIMER0_CHCTL1_Output_CH2MS_Msk (0x3UL) /*!< CH2MS (Bitfield-Mask: 0x03) */ +/* ===================================================== CHCTL1_Input ====================================================== */ +#define TIMER0_CHCTL1_Input_CH3CAPFLT_Pos (12UL) /*!< CH3CAPFLT (Bit 12) */ +#define TIMER0_CHCTL1_Input_CH3CAPFLT_Msk (0xf000UL) /*!< CH3CAPFLT (Bitfield-Mask: 0x0f) */ +#define TIMER0_CHCTL1_Input_CH3CAPPSC_Pos (10UL) /*!< CH3CAPPSC (Bit 10) */ +#define TIMER0_CHCTL1_Input_CH3CAPPSC_Msk (0xc00UL) /*!< CH3CAPPSC (Bitfield-Mask: 0x03) */ +#define TIMER0_CHCTL1_Input_CH3MS_Pos (8UL) /*!< CH3MS (Bit 8) */ +#define TIMER0_CHCTL1_Input_CH3MS_Msk (0x300UL) /*!< CH3MS (Bitfield-Mask: 0x03) */ +#define TIMER0_CHCTL1_Input_CH2CAPFLT_Pos (4UL) /*!< CH2CAPFLT (Bit 4) */ +#define TIMER0_CHCTL1_Input_CH2CAPFLT_Msk (0xf0UL) /*!< CH2CAPFLT (Bitfield-Mask: 0x0f) */ +#define TIMER0_CHCTL1_Input_CH2CAPPSC_Pos (2UL) /*!< CH2CAPPSC (Bit 2) */ +#define TIMER0_CHCTL1_Input_CH2CAPPSC_Msk (0xcUL) /*!< CH2CAPPSC (Bitfield-Mask: 0x03) */ +#define TIMER0_CHCTL1_Input_CH2MS_Pos (0UL) /*!< CH2MS (Bit 0) */ +#define TIMER0_CHCTL1_Input_CH2MS_Msk (0x3UL) /*!< CH2MS (Bitfield-Mask: 0x03) */ +/* ======================================================== CHCTL2 ========================================================= */ +#define TIMER0_CHCTL2_CH3P_Pos (13UL) /*!< CH3P (Bit 13) */ +#define TIMER0_CHCTL2_CH3P_Msk (0x2000UL) /*!< CH3P (Bitfield-Mask: 0x01) */ +#define TIMER0_CHCTL2_CH3EN_Pos (12UL) /*!< CH3EN (Bit 12) */ +#define TIMER0_CHCTL2_CH3EN_Msk (0x1000UL) /*!< CH3EN (Bitfield-Mask: 0x01) */ +#define TIMER0_CHCTL2_CH2NP_Pos (11UL) /*!< CH2NP (Bit 11) */ +#define TIMER0_CHCTL2_CH2NP_Msk (0x800UL) /*!< CH2NP (Bitfield-Mask: 0x01) */ +#define TIMER0_CHCTL2_CH2NEN_Pos (10UL) /*!< CH2NEN (Bit 10) */ +#define TIMER0_CHCTL2_CH2NEN_Msk (0x400UL) /*!< CH2NEN (Bitfield-Mask: 0x01) */ +#define TIMER0_CHCTL2_CH2P_Pos (9UL) /*!< CH2P (Bit 9) */ +#define TIMER0_CHCTL2_CH2P_Msk (0x200UL) /*!< CH2P (Bitfield-Mask: 0x01) */ +#define TIMER0_CHCTL2_CH2EN_Pos (8UL) /*!< CH2EN (Bit 8) */ +#define TIMER0_CHCTL2_CH2EN_Msk (0x100UL) /*!< CH2EN (Bitfield-Mask: 0x01) */ +#define TIMER0_CHCTL2_CH1NP_Pos (7UL) /*!< CH1NP (Bit 7) */ +#define TIMER0_CHCTL2_CH1NP_Msk (0x80UL) /*!< CH1NP (Bitfield-Mask: 0x01) */ +#define TIMER0_CHCTL2_CH1NEN_Pos (6UL) /*!< CH1NEN (Bit 6) */ +#define TIMER0_CHCTL2_CH1NEN_Msk (0x40UL) /*!< CH1NEN (Bitfield-Mask: 0x01) */ +#define TIMER0_CHCTL2_CH1P_Pos (5UL) /*!< CH1P (Bit 5) */ +#define TIMER0_CHCTL2_CH1P_Msk (0x20UL) /*!< CH1P (Bitfield-Mask: 0x01) */ +#define TIMER0_CHCTL2_CH1EN_Pos (4UL) /*!< CH1EN (Bit 4) */ +#define TIMER0_CHCTL2_CH1EN_Msk (0x10UL) /*!< CH1EN (Bitfield-Mask: 0x01) */ +#define TIMER0_CHCTL2_CH0NP_Pos (3UL) /*!< CH0NP (Bit 3) */ +#define TIMER0_CHCTL2_CH0NP_Msk (0x8UL) /*!< CH0NP (Bitfield-Mask: 0x01) */ +#define TIMER0_CHCTL2_CH0NEN_Pos (2UL) /*!< CH0NEN (Bit 2) */ +#define TIMER0_CHCTL2_CH0NEN_Msk (0x4UL) /*!< CH0NEN (Bitfield-Mask: 0x01) */ +#define TIMER0_CHCTL2_CH0P_Pos (1UL) /*!< CH0P (Bit 1) */ +#define TIMER0_CHCTL2_CH0P_Msk (0x2UL) /*!< CH0P (Bitfield-Mask: 0x01) */ +#define TIMER0_CHCTL2_CH0EN_Pos (0UL) /*!< CH0EN (Bit 0) */ +#define TIMER0_CHCTL2_CH0EN_Msk (0x1UL) /*!< CH0EN (Bitfield-Mask: 0x01) */ +/* ========================================================== CNT ========================================================== */ +#define TIMER0_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define TIMER0_CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ========================================================== PSC ========================================================== */ +#define TIMER0_PSC_PSC_Pos (0UL) /*!< PSC (Bit 0) */ +#define TIMER0_PSC_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */ +/* ========================================================== CAR ========================================================== */ +#define TIMER0_CAR_CARL_Pos (0UL) /*!< CARL (Bit 0) */ +#define TIMER0_CAR_CARL_Msk (0xffffUL) /*!< CARL (Bitfield-Mask: 0xffff) */ +/* ========================================================= CREP ========================================================== */ +#define TIMER0_CREP_CREP_Pos (0UL) /*!< CREP (Bit 0) */ +#define TIMER0_CREP_CREP_Msk (0xffUL) /*!< CREP (Bitfield-Mask: 0xff) */ +/* ========================================================= CH0CV ========================================================= */ +#define TIMER0_CH0CV_CH0VAL_Pos (0UL) /*!< CH0VAL (Bit 0) */ +#define TIMER0_CH0CV_CH0VAL_Msk (0xffffUL) /*!< CH0VAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= CH1CV ========================================================= */ +#define TIMER0_CH1CV_CH1VAL_Pos (0UL) /*!< CH1VAL (Bit 0) */ +#define TIMER0_CH1CV_CH1VAL_Msk (0xffffUL) /*!< CH1VAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= CH2CV ========================================================= */ +#define TIMER0_CH2CV_CH2VAL_Pos (0UL) /*!< CH2VAL (Bit 0) */ +#define TIMER0_CH2CV_CH2VAL_Msk (0xffffUL) /*!< CH2VAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= CH3CV ========================================================= */ +#define TIMER0_CH3CV_CH3VAL_Pos (0UL) /*!< CH3VAL (Bit 0) */ +#define TIMER0_CH3CV_CH3VAL_Msk (0xffffUL) /*!< CH3VAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= CCHP ========================================================== */ +#define TIMER0_CCHP_POEN_Pos (15UL) /*!< POEN (Bit 15) */ +#define TIMER0_CCHP_POEN_Msk (0x8000UL) /*!< POEN (Bitfield-Mask: 0x01) */ +#define TIMER0_CCHP_OAEN_Pos (14UL) /*!< OAEN (Bit 14) */ +#define TIMER0_CCHP_OAEN_Msk (0x4000UL) /*!< OAEN (Bitfield-Mask: 0x01) */ +#define TIMER0_CCHP_BRKP_Pos (13UL) /*!< BRKP (Bit 13) */ +#define TIMER0_CCHP_BRKP_Msk (0x2000UL) /*!< BRKP (Bitfield-Mask: 0x01) */ +#define TIMER0_CCHP_BRKEN_Pos (12UL) /*!< BRKEN (Bit 12) */ +#define TIMER0_CCHP_BRKEN_Msk (0x1000UL) /*!< BRKEN (Bitfield-Mask: 0x01) */ +#define TIMER0_CCHP_ROS_Pos (11UL) /*!< ROS (Bit 11) */ +#define TIMER0_CCHP_ROS_Msk (0x800UL) /*!< ROS (Bitfield-Mask: 0x01) */ +#define TIMER0_CCHP_IOS_Pos (10UL) /*!< IOS (Bit 10) */ +#define TIMER0_CCHP_IOS_Msk (0x400UL) /*!< IOS (Bitfield-Mask: 0x01) */ +#define TIMER0_CCHP_PROT_Pos (8UL) /*!< PROT (Bit 8) */ +#define TIMER0_CCHP_PROT_Msk (0x300UL) /*!< PROT (Bitfield-Mask: 0x03) */ +#define TIMER0_CCHP_DTCFG_Pos (0UL) /*!< DTCFG (Bit 0) */ +#define TIMER0_CCHP_DTCFG_Msk (0xffUL) /*!< DTCFG (Bitfield-Mask: 0xff) */ +/* ======================================================== DMACFG ========================================================= */ +#define TIMER0_DMACFG_DMATC_Pos (8UL) /*!< DMATC (Bit 8) */ +#define TIMER0_DMACFG_DMATC_Msk (0x1f00UL) /*!< DMATC (Bitfield-Mask: 0x1f) */ +#define TIMER0_DMACFG_DMATA_Pos (0UL) /*!< DMATA (Bit 0) */ +#define TIMER0_DMACFG_DMATA_Msk (0x1fUL) /*!< DMATA (Bitfield-Mask: 0x1f) */ +/* ========================================================= DMATB ========================================================= */ +#define TIMER0_DMATB_DMATB_Pos (0UL) /*!< DMATB (Bit 0) */ +#define TIMER0_DMATB_DMATB_Msk (0xffffUL) /*!< DMATB (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ TIMER1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTL0 ========================================================== */ +#define TIMER1_CTL0_CKDIV_Pos (8UL) /*!< CKDIV (Bit 8) */ +#define TIMER1_CTL0_CKDIV_Msk (0x300UL) /*!< CKDIV (Bitfield-Mask: 0x03) */ +#define TIMER1_CTL0_ARSE_Pos (7UL) /*!< ARSE (Bit 7) */ +#define TIMER1_CTL0_ARSE_Msk (0x80UL) /*!< ARSE (Bitfield-Mask: 0x01) */ +#define TIMER1_CTL0_CAM_Pos (5UL) /*!< CAM (Bit 5) */ +#define TIMER1_CTL0_CAM_Msk (0x60UL) /*!< CAM (Bitfield-Mask: 0x03) */ +#define TIMER1_CTL0_DIR_Pos (4UL) /*!< DIR (Bit 4) */ +#define TIMER1_CTL0_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ +#define TIMER1_CTL0_SPM_Pos (3UL) /*!< SPM (Bit 3) */ +#define TIMER1_CTL0_SPM_Msk (0x8UL) /*!< SPM (Bitfield-Mask: 0x01) */ +#define TIMER1_CTL0_UPS_Pos (2UL) /*!< UPS (Bit 2) */ +#define TIMER1_CTL0_UPS_Msk (0x4UL) /*!< UPS (Bitfield-Mask: 0x01) */ +#define TIMER1_CTL0_UPDIS_Pos (1UL) /*!< UPDIS (Bit 1) */ +#define TIMER1_CTL0_UPDIS_Msk (0x2UL) /*!< UPDIS (Bitfield-Mask: 0x01) */ +#define TIMER1_CTL0_CEN_Pos (0UL) /*!< CEN (Bit 0) */ +#define TIMER1_CTL0_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */ +/* ========================================================= CTL1 ========================================================== */ +#define TIMER1_CTL1_TI0S_Pos (7UL) /*!< TI0S (Bit 7) */ +#define TIMER1_CTL1_TI0S_Msk (0x80UL) /*!< TI0S (Bitfield-Mask: 0x01) */ +#define TIMER1_CTL1_MMC_Pos (4UL) /*!< MMC (Bit 4) */ +#define TIMER1_CTL1_MMC_Msk (0x70UL) /*!< MMC (Bitfield-Mask: 0x07) */ +#define TIMER1_CTL1_DMAS_Pos (3UL) /*!< DMAS (Bit 3) */ +#define TIMER1_CTL1_DMAS_Msk (0x8UL) /*!< DMAS (Bitfield-Mask: 0x01) */ +/* ========================================================= SMCFG ========================================================= */ +#define TIMER1_SMCFG_ETP_Pos (15UL) /*!< ETP (Bit 15) */ +#define TIMER1_SMCFG_ETP_Msk (0x8000UL) /*!< ETP (Bitfield-Mask: 0x01) */ +#define TIMER1_SMCFG_SMC1_Pos (14UL) /*!< SMC1 (Bit 14) */ +#define TIMER1_SMCFG_SMC1_Msk (0x4000UL) /*!< SMC1 (Bitfield-Mask: 0x01) */ +#define TIMER1_SMCFG_ETPSC_Pos (12UL) /*!< ETPSC (Bit 12) */ +#define TIMER1_SMCFG_ETPSC_Msk (0x3000UL) /*!< ETPSC (Bitfield-Mask: 0x03) */ +#define TIMER1_SMCFG_ETFC_Pos (8UL) /*!< ETFC (Bit 8) */ +#define TIMER1_SMCFG_ETFC_Msk (0xf00UL) /*!< ETFC (Bitfield-Mask: 0x0f) */ +#define TIMER1_SMCFG_MSM_Pos (7UL) /*!< MSM (Bit 7) */ +#define TIMER1_SMCFG_MSM_Msk (0x80UL) /*!< MSM (Bitfield-Mask: 0x01) */ +#define TIMER1_SMCFG_TRGS_Pos (4UL) /*!< TRGS (Bit 4) */ +#define TIMER1_SMCFG_TRGS_Msk (0x70UL) /*!< TRGS (Bitfield-Mask: 0x07) */ +#define TIMER1_SMCFG_SMC_Pos (0UL) /*!< SMC (Bit 0) */ +#define TIMER1_SMCFG_SMC_Msk (0x7UL) /*!< SMC (Bitfield-Mask: 0x07) */ +/* ======================================================= DMAINTEN ======================================================== */ +#define TIMER1_DMAINTEN_TRGDEN_Pos (14UL) /*!< TRGDEN (Bit 14) */ +#define TIMER1_DMAINTEN_TRGDEN_Msk (0x4000UL) /*!< TRGDEN (Bitfield-Mask: 0x01) */ +#define TIMER1_DMAINTEN_CH3DEN_Pos (12UL) /*!< CH3DEN (Bit 12) */ +#define TIMER1_DMAINTEN_CH3DEN_Msk (0x1000UL) /*!< CH3DEN (Bitfield-Mask: 0x01) */ +#define TIMER1_DMAINTEN_CH2DEN_Pos (11UL) /*!< CH2DEN (Bit 11) */ +#define TIMER1_DMAINTEN_CH2DEN_Msk (0x800UL) /*!< CH2DEN (Bitfield-Mask: 0x01) */ +#define TIMER1_DMAINTEN_CH1DEN_Pos (10UL) /*!< CH1DEN (Bit 10) */ +#define TIMER1_DMAINTEN_CH1DEN_Msk (0x400UL) /*!< CH1DEN (Bitfield-Mask: 0x01) */ +#define TIMER1_DMAINTEN_CH0DEN_Pos (9UL) /*!< CH0DEN (Bit 9) */ +#define TIMER1_DMAINTEN_CH0DEN_Msk (0x200UL) /*!< CH0DEN (Bitfield-Mask: 0x01) */ +#define TIMER1_DMAINTEN_UPDEN_Pos (8UL) /*!< UPDEN (Bit 8) */ +#define TIMER1_DMAINTEN_UPDEN_Msk (0x100UL) /*!< UPDEN (Bitfield-Mask: 0x01) */ +#define TIMER1_DMAINTEN_TRGIE_Pos (6UL) /*!< TRGIE (Bit 6) */ +#define TIMER1_DMAINTEN_TRGIE_Msk (0x40UL) /*!< TRGIE (Bitfield-Mask: 0x01) */ +#define TIMER1_DMAINTEN_CH3IE_Pos (4UL) /*!< CH3IE (Bit 4) */ +#define TIMER1_DMAINTEN_CH3IE_Msk (0x10UL) /*!< CH3IE (Bitfield-Mask: 0x01) */ +#define TIMER1_DMAINTEN_CH2IE_Pos (3UL) /*!< CH2IE (Bit 3) */ +#define TIMER1_DMAINTEN_CH2IE_Msk (0x8UL) /*!< CH2IE (Bitfield-Mask: 0x01) */ +#define TIMER1_DMAINTEN_CH1IE_Pos (2UL) /*!< CH1IE (Bit 2) */ +#define TIMER1_DMAINTEN_CH1IE_Msk (0x4UL) /*!< CH1IE (Bitfield-Mask: 0x01) */ +#define TIMER1_DMAINTEN_CH0IE_Pos (1UL) /*!< CH0IE (Bit 1) */ +#define TIMER1_DMAINTEN_CH0IE_Msk (0x2UL) /*!< CH0IE (Bitfield-Mask: 0x01) */ +#define TIMER1_DMAINTEN_UPIE_Pos (0UL) /*!< UPIE (Bit 0) */ +#define TIMER1_DMAINTEN_UPIE_Msk (0x1UL) /*!< UPIE (Bitfield-Mask: 0x01) */ +/* ========================================================= INTF ========================================================== */ +#define TIMER1_INTF_CH3OF_Pos (12UL) /*!< CH3OF (Bit 12) */ +#define TIMER1_INTF_CH3OF_Msk (0x1000UL) /*!< CH3OF (Bitfield-Mask: 0x01) */ +#define TIMER1_INTF_CH2OF_Pos (11UL) /*!< CH2OF (Bit 11) */ +#define TIMER1_INTF_CH2OF_Msk (0x800UL) /*!< CH2OF (Bitfield-Mask: 0x01) */ +#define TIMER1_INTF_CH1OF_Pos (10UL) /*!< CH1OF (Bit 10) */ +#define TIMER1_INTF_CH1OF_Msk (0x400UL) /*!< CH1OF (Bitfield-Mask: 0x01) */ +#define TIMER1_INTF_CH0OF_Pos (9UL) /*!< CH0OF (Bit 9) */ +#define TIMER1_INTF_CH0OF_Msk (0x200UL) /*!< CH0OF (Bitfield-Mask: 0x01) */ +#define TIMER1_INTF_TRGIF_Pos (6UL) /*!< TRGIF (Bit 6) */ +#define TIMER1_INTF_TRGIF_Msk (0x40UL) /*!< TRGIF (Bitfield-Mask: 0x01) */ +#define TIMER1_INTF_CH3IF_Pos (4UL) /*!< CH3IF (Bit 4) */ +#define TIMER1_INTF_CH3IF_Msk (0x10UL) /*!< CH3IF (Bitfield-Mask: 0x01) */ +#define TIMER1_INTF_CH2IF_Pos (3UL) /*!< CH2IF (Bit 3) */ +#define TIMER1_INTF_CH2IF_Msk (0x8UL) /*!< CH2IF (Bitfield-Mask: 0x01) */ +#define TIMER1_INTF_CH1IF_Pos (2UL) /*!< CH1IF (Bit 2) */ +#define TIMER1_INTF_CH1IF_Msk (0x4UL) /*!< CH1IF (Bitfield-Mask: 0x01) */ +#define TIMER1_INTF_CH0IF_Pos (1UL) /*!< CH0IF (Bit 1) */ +#define TIMER1_INTF_CH0IF_Msk (0x2UL) /*!< CH0IF (Bitfield-Mask: 0x01) */ +#define TIMER1_INTF_UPIF_Pos (0UL) /*!< UPIF (Bit 0) */ +#define TIMER1_INTF_UPIF_Msk (0x1UL) /*!< UPIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SWEVG ========================================================= */ +#define TIMER1_SWEVG_TRGG_Pos (6UL) /*!< TRGG (Bit 6) */ +#define TIMER1_SWEVG_TRGG_Msk (0x40UL) /*!< TRGG (Bitfield-Mask: 0x01) */ +#define TIMER1_SWEVG_CH3G_Pos (4UL) /*!< CH3G (Bit 4) */ +#define TIMER1_SWEVG_CH3G_Msk (0x10UL) /*!< CH3G (Bitfield-Mask: 0x01) */ +#define TIMER1_SWEVG_CH2G_Pos (3UL) /*!< CH2G (Bit 3) */ +#define TIMER1_SWEVG_CH2G_Msk (0x8UL) /*!< CH2G (Bitfield-Mask: 0x01) */ +#define TIMER1_SWEVG_CH1G_Pos (2UL) /*!< CH1G (Bit 2) */ +#define TIMER1_SWEVG_CH1G_Msk (0x4UL) /*!< CH1G (Bitfield-Mask: 0x01) */ +#define TIMER1_SWEVG_CH0G_Pos (1UL) /*!< CH0G (Bit 1) */ +#define TIMER1_SWEVG_CH0G_Msk (0x2UL) /*!< CH0G (Bitfield-Mask: 0x01) */ +#define TIMER1_SWEVG_UPG_Pos (0UL) /*!< UPG (Bit 0) */ +#define TIMER1_SWEVG_UPG_Msk (0x1UL) /*!< UPG (Bitfield-Mask: 0x01) */ +/* ===================================================== CHCTL0_Output ===================================================== */ +#define TIMER1_CHCTL0_Output_CH1COMCEN_Pos (15UL) /*!< CH1COMCEN (Bit 15) */ +#define TIMER1_CHCTL0_Output_CH1COMCEN_Msk (0x8000UL) /*!< CH1COMCEN (Bitfield-Mask: 0x01) */ +#define TIMER1_CHCTL0_Output_CH1COMCTL_Pos (12UL) /*!< CH1COMCTL (Bit 12) */ +#define TIMER1_CHCTL0_Output_CH1COMCTL_Msk (0x7000UL) /*!< CH1COMCTL (Bitfield-Mask: 0x07) */ +#define TIMER1_CHCTL0_Output_CH1COMSEN_Pos (11UL) /*!< CH1COMSEN (Bit 11) */ +#define TIMER1_CHCTL0_Output_CH1COMSEN_Msk (0x800UL) /*!< CH1COMSEN (Bitfield-Mask: 0x01) */ +#define TIMER1_CHCTL0_Output_CH1COMFEN_Pos (10UL) /*!< CH1COMFEN (Bit 10) */ +#define TIMER1_CHCTL0_Output_CH1COMFEN_Msk (0x400UL) /*!< CH1COMFEN (Bitfield-Mask: 0x01) */ +#define TIMER1_CHCTL0_Output_CH1MS_Pos (8UL) /*!< CH1MS (Bit 8) */ +#define TIMER1_CHCTL0_Output_CH1MS_Msk (0x300UL) /*!< CH1MS (Bitfield-Mask: 0x03) */ +#define TIMER1_CHCTL0_Output_CH0COMCEN_Pos (7UL) /*!< CH0COMCEN (Bit 7) */ +#define TIMER1_CHCTL0_Output_CH0COMCEN_Msk (0x80UL) /*!< CH0COMCEN (Bitfield-Mask: 0x01) */ +#define TIMER1_CHCTL0_Output_CH0COMCTL_Pos (4UL) /*!< CH0COMCTL (Bit 4) */ +#define TIMER1_CHCTL0_Output_CH0COMCTL_Msk (0x70UL) /*!< CH0COMCTL (Bitfield-Mask: 0x07) */ +#define TIMER1_CHCTL0_Output_CH0COMSEN_Pos (3UL) /*!< CH0COMSEN (Bit 3) */ +#define TIMER1_CHCTL0_Output_CH0COMSEN_Msk (0x8UL) /*!< CH0COMSEN (Bitfield-Mask: 0x01) */ +#define TIMER1_CHCTL0_Output_CH0COMFEN_Pos (2UL) /*!< CH0COMFEN (Bit 2) */ +#define TIMER1_CHCTL0_Output_CH0COMFEN_Msk (0x4UL) /*!< CH0COMFEN (Bitfield-Mask: 0x01) */ +#define TIMER1_CHCTL0_Output_CH0MS_Pos (0UL) /*!< CH0MS (Bit 0) */ +#define TIMER1_CHCTL0_Output_CH0MS_Msk (0x3UL) /*!< CH0MS (Bitfield-Mask: 0x03) */ +/* ===================================================== CHCTL0_Input ====================================================== */ +#define TIMER1_CHCTL0_Input_CH1CAPFLT_Pos (12UL) /*!< CH1CAPFLT (Bit 12) */ +#define TIMER1_CHCTL0_Input_CH1CAPFLT_Msk (0xf000UL) /*!< CH1CAPFLT (Bitfield-Mask: 0x0f) */ +#define TIMER1_CHCTL0_Input_CH1CAPPSC_Pos (10UL) /*!< CH1CAPPSC (Bit 10) */ +#define TIMER1_CHCTL0_Input_CH1CAPPSC_Msk (0xc00UL) /*!< CH1CAPPSC (Bitfield-Mask: 0x03) */ +#define TIMER1_CHCTL0_Input_CH1MS_Pos (8UL) /*!< CH1MS (Bit 8) */ +#define TIMER1_CHCTL0_Input_CH1MS_Msk (0x300UL) /*!< CH1MS (Bitfield-Mask: 0x03) */ +#define TIMER1_CHCTL0_Input_CH0CAPFLT_Pos (4UL) /*!< CH0CAPFLT (Bit 4) */ +#define TIMER1_CHCTL0_Input_CH0CAPFLT_Msk (0xf0UL) /*!< CH0CAPFLT (Bitfield-Mask: 0x0f) */ +#define TIMER1_CHCTL0_Input_CH0CAPPSC_Pos (2UL) /*!< CH0CAPPSC (Bit 2) */ +#define TIMER1_CHCTL0_Input_CH0CAPPSC_Msk (0xcUL) /*!< CH0CAPPSC (Bitfield-Mask: 0x03) */ +#define TIMER1_CHCTL0_Input_CH0MS_Pos (0UL) /*!< CH0MS (Bit 0) */ +#define TIMER1_CHCTL0_Input_CH0MS_Msk (0x3UL) /*!< CH0MS (Bitfield-Mask: 0x03) */ +/* ===================================================== CHCTL1_Output ===================================================== */ +#define TIMER1_CHCTL1_Output_CH3COMCEN_Pos (15UL) /*!< CH3COMCEN (Bit 15) */ +#define TIMER1_CHCTL1_Output_CH3COMCEN_Msk (0x8000UL) /*!< CH3COMCEN (Bitfield-Mask: 0x01) */ +#define TIMER1_CHCTL1_Output_CH3COMCTL_Pos (12UL) /*!< CH3COMCTL (Bit 12) */ +#define TIMER1_CHCTL1_Output_CH3COMCTL_Msk (0x7000UL) /*!< CH3COMCTL (Bitfield-Mask: 0x07) */ +#define TIMER1_CHCTL1_Output_CH3COMSEN_Pos (11UL) /*!< CH3COMSEN (Bit 11) */ +#define TIMER1_CHCTL1_Output_CH3COMSEN_Msk (0x800UL) /*!< CH3COMSEN (Bitfield-Mask: 0x01) */ +#define TIMER1_CHCTL1_Output_CH3COMFEN_Pos (10UL) /*!< CH3COMFEN (Bit 10) */ +#define TIMER1_CHCTL1_Output_CH3COMFEN_Msk (0x400UL) /*!< CH3COMFEN (Bitfield-Mask: 0x01) */ +#define TIMER1_CHCTL1_Output_CH3MS_Pos (8UL) /*!< CH3MS (Bit 8) */ +#define TIMER1_CHCTL1_Output_CH3MS_Msk (0x300UL) /*!< CH3MS (Bitfield-Mask: 0x03) */ +#define TIMER1_CHCTL1_Output_CH2COMCEN_Pos (7UL) /*!< CH2COMCEN (Bit 7) */ +#define TIMER1_CHCTL1_Output_CH2COMCEN_Msk (0x80UL) /*!< CH2COMCEN (Bitfield-Mask: 0x01) */ +#define TIMER1_CHCTL1_Output_CH2COMCTL_Pos (4UL) /*!< CH2COMCTL (Bit 4) */ +#define TIMER1_CHCTL1_Output_CH2COMCTL_Msk (0x70UL) /*!< CH2COMCTL (Bitfield-Mask: 0x07) */ +#define TIMER1_CHCTL1_Output_CH2COMSEN_Pos (3UL) /*!< CH2COMSEN (Bit 3) */ +#define TIMER1_CHCTL1_Output_CH2COMSEN_Msk (0x8UL) /*!< CH2COMSEN (Bitfield-Mask: 0x01) */ +#define TIMER1_CHCTL1_Output_CH2COMFEN_Pos (2UL) /*!< CH2COMFEN (Bit 2) */ +#define TIMER1_CHCTL1_Output_CH2COMFEN_Msk (0x4UL) /*!< CH2COMFEN (Bitfield-Mask: 0x01) */ +#define TIMER1_CHCTL1_Output_CH2MS_Pos (0UL) /*!< CH2MS (Bit 0) */ +#define TIMER1_CHCTL1_Output_CH2MS_Msk (0x3UL) /*!< CH2MS (Bitfield-Mask: 0x03) */ +/* ===================================================== CHCTL1_Input ====================================================== */ +#define TIMER1_CHCTL1_Input_CH3CAPFLT_Pos (12UL) /*!< CH3CAPFLT (Bit 12) */ +#define TIMER1_CHCTL1_Input_CH3CAPFLT_Msk (0xf000UL) /*!< CH3CAPFLT (Bitfield-Mask: 0x0f) */ +#define TIMER1_CHCTL1_Input_CH3CAPPSC_Pos (10UL) /*!< CH3CAPPSC (Bit 10) */ +#define TIMER1_CHCTL1_Input_CH3CAPPSC_Msk (0xc00UL) /*!< CH3CAPPSC (Bitfield-Mask: 0x03) */ +#define TIMER1_CHCTL1_Input_CH3MS_Pos (8UL) /*!< CH3MS (Bit 8) */ +#define TIMER1_CHCTL1_Input_CH3MS_Msk (0x300UL) /*!< CH3MS (Bitfield-Mask: 0x03) */ +#define TIMER1_CHCTL1_Input_CH2CAPFLT_Pos (4UL) /*!< CH2CAPFLT (Bit 4) */ +#define TIMER1_CHCTL1_Input_CH2CAPFLT_Msk (0xf0UL) /*!< CH2CAPFLT (Bitfield-Mask: 0x0f) */ +#define TIMER1_CHCTL1_Input_CH2CAPPSC_Pos (2UL) /*!< CH2CAPPSC (Bit 2) */ +#define TIMER1_CHCTL1_Input_CH2CAPPSC_Msk (0xcUL) /*!< CH2CAPPSC (Bitfield-Mask: 0x03) */ +#define TIMER1_CHCTL1_Input_CH2MS_Pos (0UL) /*!< CH2MS (Bit 0) */ +#define TIMER1_CHCTL1_Input_CH2MS_Msk (0x3UL) /*!< CH2MS (Bitfield-Mask: 0x03) */ +/* ======================================================== CHCTL2 ========================================================= */ +#define TIMER1_CHCTL2_CH3P_Pos (13UL) /*!< CH3P (Bit 13) */ +#define TIMER1_CHCTL2_CH3P_Msk (0x2000UL) /*!< CH3P (Bitfield-Mask: 0x01) */ +#define TIMER1_CHCTL2_CH3EN_Pos (12UL) /*!< CH3EN (Bit 12) */ +#define TIMER1_CHCTL2_CH3EN_Msk (0x1000UL) /*!< CH3EN (Bitfield-Mask: 0x01) */ +#define TIMER1_CHCTL2_CH2P_Pos (9UL) /*!< CH2P (Bit 9) */ +#define TIMER1_CHCTL2_CH2P_Msk (0x200UL) /*!< CH2P (Bitfield-Mask: 0x01) */ +#define TIMER1_CHCTL2_CH2EN_Pos (8UL) /*!< CH2EN (Bit 8) */ +#define TIMER1_CHCTL2_CH2EN_Msk (0x100UL) /*!< CH2EN (Bitfield-Mask: 0x01) */ +#define TIMER1_CHCTL2_CH1P_Pos (5UL) /*!< CH1P (Bit 5) */ +#define TIMER1_CHCTL2_CH1P_Msk (0x20UL) /*!< CH1P (Bitfield-Mask: 0x01) */ +#define TIMER1_CHCTL2_CH1EN_Pos (4UL) /*!< CH1EN (Bit 4) */ +#define TIMER1_CHCTL2_CH1EN_Msk (0x10UL) /*!< CH1EN (Bitfield-Mask: 0x01) */ +#define TIMER1_CHCTL2_CH0P_Pos (1UL) /*!< CH0P (Bit 1) */ +#define TIMER1_CHCTL2_CH0P_Msk (0x2UL) /*!< CH0P (Bitfield-Mask: 0x01) */ +#define TIMER1_CHCTL2_CH0EN_Pos (0UL) /*!< CH0EN (Bit 0) */ +#define TIMER1_CHCTL2_CH0EN_Msk (0x1UL) /*!< CH0EN (Bitfield-Mask: 0x01) */ +/* ========================================================== CNT ========================================================== */ +#define TIMER1_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define TIMER1_CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ========================================================== PSC ========================================================== */ +#define TIMER1_PSC_PSC_Pos (0UL) /*!< PSC (Bit 0) */ +#define TIMER1_PSC_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */ +/* ========================================================== CAR ========================================================== */ +#define TIMER1_CAR_CARL_Pos (0UL) /*!< CARL (Bit 0) */ +#define TIMER1_CAR_CARL_Msk (0xffffUL) /*!< CARL (Bitfield-Mask: 0xffff) */ +/* ========================================================= CH0CV ========================================================= */ +#define TIMER1_CH0CV_CH0VAL_Pos (0UL) /*!< CH0VAL (Bit 0) */ +#define TIMER1_CH0CV_CH0VAL_Msk (0xffffUL) /*!< CH0VAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= CH1CV ========================================================= */ +#define TIMER1_CH1CV_CH1VAL_Pos (0UL) /*!< CH1VAL (Bit 0) */ +#define TIMER1_CH1CV_CH1VAL_Msk (0xffffUL) /*!< CH1VAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= CH2CV ========================================================= */ +#define TIMER1_CH2CV_CH2VAL_Pos (0UL) /*!< CH2VAL (Bit 0) */ +#define TIMER1_CH2CV_CH2VAL_Msk (0xffffUL) /*!< CH2VAL (Bitfield-Mask: 0xffff) */ +/* ========================================================= CH3CV ========================================================= */ +#define TIMER1_CH3CV_CH3VAL_Pos (0UL) /*!< CH3VAL (Bit 0) */ +#define TIMER1_CH3CV_CH3VAL_Msk (0xffffUL) /*!< CH3VAL (Bitfield-Mask: 0xffff) */ +/* ======================================================== DMACFG ========================================================= */ +#define TIMER1_DMACFG_DMATC_Pos (8UL) /*!< DMATC (Bit 8) */ +#define TIMER1_DMACFG_DMATC_Msk (0x1f00UL) /*!< DMATC (Bitfield-Mask: 0x1f) */ +#define TIMER1_DMACFG_DMATA_Pos (0UL) /*!< DMATA (Bit 0) */ +#define TIMER1_DMACFG_DMATA_Msk (0x1fUL) /*!< DMATA (Bitfield-Mask: 0x1f) */ +/* ========================================================= DMATB ========================================================= */ +#define TIMER1_DMATB_DMATB_Pos (0UL) /*!< DMATB (Bit 0) */ +#define TIMER1_DMATB_DMATB_Msk (0xffffUL) /*!< DMATB (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ TIMER5 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTL0 ========================================================== */ +#define TIMER5_CTL0_ARSE_Pos (7UL) /*!< ARSE (Bit 7) */ +#define TIMER5_CTL0_ARSE_Msk (0x80UL) /*!< ARSE (Bitfield-Mask: 0x01) */ +#define TIMER5_CTL0_SPM_Pos (3UL) /*!< SPM (Bit 3) */ +#define TIMER5_CTL0_SPM_Msk (0x8UL) /*!< SPM (Bitfield-Mask: 0x01) */ +#define TIMER5_CTL0_UPS_Pos (2UL) /*!< UPS (Bit 2) */ +#define TIMER5_CTL0_UPS_Msk (0x4UL) /*!< UPS (Bitfield-Mask: 0x01) */ +#define TIMER5_CTL0_UPDIS_Pos (1UL) /*!< UPDIS (Bit 1) */ +#define TIMER5_CTL0_UPDIS_Msk (0x2UL) /*!< UPDIS (Bitfield-Mask: 0x01) */ +#define TIMER5_CTL0_CEN_Pos (0UL) /*!< CEN (Bit 0) */ +#define TIMER5_CTL0_CEN_Msk (0x1UL) /*!< CEN (Bitfield-Mask: 0x01) */ +/* ========================================================= CTL1 ========================================================== */ +#define TIMER5_CTL1_MMC_Pos (4UL) /*!< MMC (Bit 4) */ +#define TIMER5_CTL1_MMC_Msk (0x70UL) /*!< MMC (Bitfield-Mask: 0x07) */ +/* ======================================================= DMAINTEN ======================================================== */ +#define TIMER5_DMAINTEN_UPDEN_Pos (8UL) /*!< UPDEN (Bit 8) */ +#define TIMER5_DMAINTEN_UPDEN_Msk (0x100UL) /*!< UPDEN (Bitfield-Mask: 0x01) */ +#define TIMER5_DMAINTEN_UPIE_Pos (0UL) /*!< UPIE (Bit 0) */ +#define TIMER5_DMAINTEN_UPIE_Msk (0x1UL) /*!< UPIE (Bitfield-Mask: 0x01) */ +/* ========================================================= INTF ========================================================== */ +#define TIMER5_INTF_UPIF_Pos (0UL) /*!< UPIF (Bit 0) */ +#define TIMER5_INTF_UPIF_Msk (0x1UL) /*!< UPIF (Bitfield-Mask: 0x01) */ +/* ========================================================= SWEVG ========================================================= */ +#define TIMER5_SWEVG_UPG_Pos (0UL) /*!< UPG (Bit 0) */ +#define TIMER5_SWEVG_UPG_Msk (0x1UL) /*!< UPG (Bitfield-Mask: 0x01) */ +/* ========================================================== CNT ========================================================== */ +#define TIMER5_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define TIMER5_CNT_CNT_Msk (0xffffUL) /*!< CNT (Bitfield-Mask: 0xffff) */ +/* ========================================================== PSC ========================================================== */ +#define TIMER5_PSC_PSC_Pos (0UL) /*!< PSC (Bit 0) */ +#define TIMER5_PSC_PSC_Msk (0xffffUL) /*!< PSC (Bitfield-Mask: 0xffff) */ +/* ========================================================== CAR ========================================================== */ +#define TIMER5_CAR_CARL_Pos (0UL) /*!< CARL (Bit 0) */ +#define TIMER5_CAR_CARL_Msk (0xffffUL) /*!< CARL (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ USART ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ +#define USART_STAT_CTSF_Pos (9UL) /*!< CTSF (Bit 9) */ +#define USART_STAT_CTSF_Msk (0x200UL) /*!< CTSF (Bitfield-Mask: 0x01) */ +#define USART_STAT_LBDF_Pos (8UL) /*!< LBDF (Bit 8) */ +#define USART_STAT_LBDF_Msk (0x100UL) /*!< LBDF (Bitfield-Mask: 0x01) */ +#define USART_STAT_TBE_Pos (7UL) /*!< TBE (Bit 7) */ +#define USART_STAT_TBE_Msk (0x80UL) /*!< TBE (Bitfield-Mask: 0x01) */ +#define USART_STAT_TC_Pos (6UL) /*!< TC (Bit 6) */ +#define USART_STAT_TC_Msk (0x40UL) /*!< TC (Bitfield-Mask: 0x01) */ +#define USART_STAT_RBNE_Pos (5UL) /*!< RBNE (Bit 5) */ +#define USART_STAT_RBNE_Msk (0x20UL) /*!< RBNE (Bitfield-Mask: 0x01) */ +#define USART_STAT_IDLEF_Pos (4UL) /*!< IDLEF (Bit 4) */ +#define USART_STAT_IDLEF_Msk (0x10UL) /*!< IDLEF (Bitfield-Mask: 0x01) */ +#define USART_STAT_ORERR_Pos (3UL) /*!< ORERR (Bit 3) */ +#define USART_STAT_ORERR_Msk (0x8UL) /*!< ORERR (Bitfield-Mask: 0x01) */ +#define USART_STAT_NERR_Pos (2UL) /*!< NERR (Bit 2) */ +#define USART_STAT_NERR_Msk (0x4UL) /*!< NERR (Bitfield-Mask: 0x01) */ +#define USART_STAT_FERR_Pos (1UL) /*!< FERR (Bit 1) */ +#define USART_STAT_FERR_Msk (0x2UL) /*!< FERR (Bitfield-Mask: 0x01) */ +#define USART_STAT_PERR_Pos (0UL) /*!< PERR (Bit 0) */ +#define USART_STAT_PERR_Msk (0x1UL) /*!< PERR (Bitfield-Mask: 0x01) */ +/* ========================================================= DATA ========================================================== */ +#define USART_DATA_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define USART_DATA_DATA_Msk (0x1ffUL) /*!< DATA (Bitfield-Mask: 0x1ff) */ +/* ========================================================= BAUD ========================================================== */ +#define USART_BAUD_INTDIV_Pos (4UL) /*!< INTDIV (Bit 4) */ +#define USART_BAUD_INTDIV_Msk (0xfff0UL) /*!< INTDIV (Bitfield-Mask: 0xfff) */ +#define USART_BAUD_FRADIV_Pos (0UL) /*!< FRADIV (Bit 0) */ +#define USART_BAUD_FRADIV_Msk (0xfUL) /*!< FRADIV (Bitfield-Mask: 0x0f) */ +/* ========================================================= CTL0 ========================================================== */ +#define USART_CTL0_UEN_Pos (13UL) /*!< UEN (Bit 13) */ +#define USART_CTL0_UEN_Msk (0x2000UL) /*!< UEN (Bitfield-Mask: 0x01) */ +#define USART_CTL0_WL_Pos (12UL) /*!< WL (Bit 12) */ +#define USART_CTL0_WL_Msk (0x1000UL) /*!< WL (Bitfield-Mask: 0x01) */ +#define USART_CTL0_WM_Pos (11UL) /*!< WM (Bit 11) */ +#define USART_CTL0_WM_Msk (0x800UL) /*!< WM (Bitfield-Mask: 0x01) */ +#define USART_CTL0_PCEN_Pos (10UL) /*!< PCEN (Bit 10) */ +#define USART_CTL0_PCEN_Msk (0x400UL) /*!< PCEN (Bitfield-Mask: 0x01) */ +#define USART_CTL0_PM_Pos (9UL) /*!< PM (Bit 9) */ +#define USART_CTL0_PM_Msk (0x200UL) /*!< PM (Bitfield-Mask: 0x01) */ +#define USART_CTL0_PERRIE_Pos (8UL) /*!< PERRIE (Bit 8) */ +#define USART_CTL0_PERRIE_Msk (0x100UL) /*!< PERRIE (Bitfield-Mask: 0x01) */ +#define USART_CTL0_TBEIE_Pos (7UL) /*!< TBEIE (Bit 7) */ +#define USART_CTL0_TBEIE_Msk (0x80UL) /*!< TBEIE (Bitfield-Mask: 0x01) */ +#define USART_CTL0_TCIE_Pos (6UL) /*!< TCIE (Bit 6) */ +#define USART_CTL0_TCIE_Msk (0x40UL) /*!< TCIE (Bitfield-Mask: 0x01) */ +#define USART_CTL0_RBNEIE_Pos (5UL) /*!< RBNEIE (Bit 5) */ +#define USART_CTL0_RBNEIE_Msk (0x20UL) /*!< RBNEIE (Bitfield-Mask: 0x01) */ +#define USART_CTL0_IDLEIE_Pos (4UL) /*!< IDLEIE (Bit 4) */ +#define USART_CTL0_IDLEIE_Msk (0x10UL) /*!< IDLEIE (Bitfield-Mask: 0x01) */ +#define USART_CTL0_TEN_Pos (3UL) /*!< TEN (Bit 3) */ +#define USART_CTL0_TEN_Msk (0x8UL) /*!< TEN (Bitfield-Mask: 0x01) */ +#define USART_CTL0_REN_Pos (2UL) /*!< REN (Bit 2) */ +#define USART_CTL0_REN_Msk (0x4UL) /*!< REN (Bitfield-Mask: 0x01) */ +#define USART_CTL0_RWU_Pos (1UL) /*!< RWU (Bit 1) */ +#define USART_CTL0_RWU_Msk (0x2UL) /*!< RWU (Bitfield-Mask: 0x01) */ +#define USART_CTL0_SBKCMD_Pos (0UL) /*!< SBKCMD (Bit 0) */ +#define USART_CTL0_SBKCMD_Msk (0x1UL) /*!< SBKCMD (Bitfield-Mask: 0x01) */ +/* ========================================================= CTL1 ========================================================== */ +#define USART_CTL1_LMEN_Pos (14UL) /*!< LMEN (Bit 14) */ +#define USART_CTL1_LMEN_Msk (0x4000UL) /*!< LMEN (Bitfield-Mask: 0x01) */ +#define USART_CTL1_STB_Pos (12UL) /*!< STB (Bit 12) */ +#define USART_CTL1_STB_Msk (0x3000UL) /*!< STB (Bitfield-Mask: 0x03) */ +#define USART_CTL1_CKEN_Pos (11UL) /*!< CKEN (Bit 11) */ +#define USART_CTL1_CKEN_Msk (0x800UL) /*!< CKEN (Bitfield-Mask: 0x01) */ +#define USART_CTL1_CPL_Pos (10UL) /*!< CPL (Bit 10) */ +#define USART_CTL1_CPL_Msk (0x400UL) /*!< CPL (Bitfield-Mask: 0x01) */ +#define USART_CTL1_CPH_Pos (9UL) /*!< CPH (Bit 9) */ +#define USART_CTL1_CPH_Msk (0x200UL) /*!< CPH (Bitfield-Mask: 0x01) */ +#define USART_CTL1_CLEN_Pos (8UL) /*!< CLEN (Bit 8) */ +#define USART_CTL1_CLEN_Msk (0x100UL) /*!< CLEN (Bitfield-Mask: 0x01) */ +#define USART_CTL1_LBDIE_Pos (6UL) /*!< LBDIE (Bit 6) */ +#define USART_CTL1_LBDIE_Msk (0x40UL) /*!< LBDIE (Bitfield-Mask: 0x01) */ +#define USART_CTL1_LBLEN_Pos (5UL) /*!< LBLEN (Bit 5) */ +#define USART_CTL1_LBLEN_Msk (0x20UL) /*!< LBLEN (Bitfield-Mask: 0x01) */ +#define USART_CTL1_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ +#define USART_CTL1_ADDR_Msk (0xfUL) /*!< ADDR (Bitfield-Mask: 0x0f) */ +/* ========================================================= CTL2 ========================================================== */ +#define USART_CTL2_CTSIE_Pos (10UL) /*!< CTSIE (Bit 10) */ +#define USART_CTL2_CTSIE_Msk (0x400UL) /*!< CTSIE (Bitfield-Mask: 0x01) */ +#define USART_CTL2_CTSEN_Pos (9UL) /*!< CTSEN (Bit 9) */ +#define USART_CTL2_CTSEN_Msk (0x200UL) /*!< CTSEN (Bitfield-Mask: 0x01) */ +#define USART_CTL2_RTSEN_Pos (8UL) /*!< RTSEN (Bit 8) */ +#define USART_CTL2_RTSEN_Msk (0x100UL) /*!< RTSEN (Bitfield-Mask: 0x01) */ +#define USART_CTL2_DENT_Pos (7UL) /*!< DENT (Bit 7) */ +#define USART_CTL2_DENT_Msk (0x80UL) /*!< DENT (Bitfield-Mask: 0x01) */ +#define USART_CTL2_DENR_Pos (6UL) /*!< DENR (Bit 6) */ +#define USART_CTL2_DENR_Msk (0x40UL) /*!< DENR (Bitfield-Mask: 0x01) */ +#define USART_CTL2_SCEN_Pos (5UL) /*!< SCEN (Bit 5) */ +#define USART_CTL2_SCEN_Msk (0x20UL) /*!< SCEN (Bitfield-Mask: 0x01) */ +#define USART_CTL2_NKEN_Pos (4UL) /*!< NKEN (Bit 4) */ +#define USART_CTL2_NKEN_Msk (0x10UL) /*!< NKEN (Bitfield-Mask: 0x01) */ +#define USART_CTL2_HDEN_Pos (3UL) /*!< HDEN (Bit 3) */ +#define USART_CTL2_HDEN_Msk (0x8UL) /*!< HDEN (Bitfield-Mask: 0x01) */ +#define USART_CTL2_IRLP_Pos (2UL) /*!< IRLP (Bit 2) */ +#define USART_CTL2_IRLP_Msk (0x4UL) /*!< IRLP (Bitfield-Mask: 0x01) */ +#define USART_CTL2_IREN_Pos (1UL) /*!< IREN (Bit 1) */ +#define USART_CTL2_IREN_Msk (0x2UL) /*!< IREN (Bitfield-Mask: 0x01) */ +#define USART_CTL2_ERRIE_Pos (0UL) /*!< ERRIE (Bit 0) */ +#define USART_CTL2_ERRIE_Msk (0x1UL) /*!< ERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================== GP =========================================================== */ +#define USART_GP_GUAT_Pos (8UL) /*!< GUAT (Bit 8) */ +#define USART_GP_GUAT_Msk (0xff00UL) /*!< GUAT (Bitfield-Mask: 0xff) */ +#define USART_GP_PSC_Pos (0UL) /*!< PSC (Bit 0) */ +#define USART_GP_PSC_Msk (0xffUL) /*!< PSC (Bitfield-Mask: 0xff) */ + + +/* =========================================================================================================================== */ +/* ================ UART ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STAT ========================================================== */ +#define UART_STAT_LBDF_Pos (8UL) /*!< LBDF (Bit 8) */ +#define UART_STAT_LBDF_Msk (0x100UL) /*!< LBDF (Bitfield-Mask: 0x01) */ +#define UART_STAT_TBE_Pos (7UL) /*!< TBE (Bit 7) */ +#define UART_STAT_TBE_Msk (0x80UL) /*!< TBE (Bitfield-Mask: 0x01) */ +#define UART_STAT_TC_Pos (6UL) /*!< TC (Bit 6) */ +#define UART_STAT_TC_Msk (0x40UL) /*!< TC (Bitfield-Mask: 0x01) */ +#define UART_STAT_RBNE_Pos (5UL) /*!< RBNE (Bit 5) */ +#define UART_STAT_RBNE_Msk (0x20UL) /*!< RBNE (Bitfield-Mask: 0x01) */ +#define UART_STAT_IDLEF_Pos (4UL) /*!< IDLEF (Bit 4) */ +#define UART_STAT_IDLEF_Msk (0x10UL) /*!< IDLEF (Bitfield-Mask: 0x01) */ +#define UART_STAT_ORERR_Pos (3UL) /*!< ORERR (Bit 3) */ +#define UART_STAT_ORERR_Msk (0x8UL) /*!< ORERR (Bitfield-Mask: 0x01) */ +#define UART_STAT_NERR_Pos (2UL) /*!< NERR (Bit 2) */ +#define UART_STAT_NERR_Msk (0x4UL) /*!< NERR (Bitfield-Mask: 0x01) */ +#define UART_STAT_FERR_Pos (1UL) /*!< FERR (Bit 1) */ +#define UART_STAT_FERR_Msk (0x2UL) /*!< FERR (Bitfield-Mask: 0x01) */ +#define UART_STAT_PERR_Pos (0UL) /*!< PERR (Bit 0) */ +#define UART_STAT_PERR_Msk (0x1UL) /*!< PERR (Bitfield-Mask: 0x01) */ +/* ========================================================= DATA ========================================================== */ +#define UART_DATA_DATA_Pos (0UL) /*!< DATA (Bit 0) */ +#define UART_DATA_DATA_Msk (0x1ffUL) /*!< DATA (Bitfield-Mask: 0x1ff) */ +/* ========================================================= BAUD ========================================================== */ +#define UART_BAUD_INTDIV_Pos (4UL) /*!< INTDIV (Bit 4) */ +#define UART_BAUD_INTDIV_Msk (0xfff0UL) /*!< INTDIV (Bitfield-Mask: 0xfff) */ +#define UART_BAUD_FRADIV_Pos (0UL) /*!< FRADIV (Bit 0) */ +#define UART_BAUD_FRADIV_Msk (0xfUL) /*!< FRADIV (Bitfield-Mask: 0x0f) */ +/* ========================================================= CTL0 ========================================================== */ +#define UART_CTL0_UEN_Pos (13UL) /*!< UEN (Bit 13) */ +#define UART_CTL0_UEN_Msk (0x2000UL) /*!< UEN (Bitfield-Mask: 0x01) */ +#define UART_CTL0_WL_Pos (12UL) /*!< WL (Bit 12) */ +#define UART_CTL0_WL_Msk (0x1000UL) /*!< WL (Bitfield-Mask: 0x01) */ +#define UART_CTL0_WM_Pos (11UL) /*!< WM (Bit 11) */ +#define UART_CTL0_WM_Msk (0x800UL) /*!< WM (Bitfield-Mask: 0x01) */ +#define UART_CTL0_PCEN_Pos (10UL) /*!< PCEN (Bit 10) */ +#define UART_CTL0_PCEN_Msk (0x400UL) /*!< PCEN (Bitfield-Mask: 0x01) */ +#define UART_CTL0_PM_Pos (9UL) /*!< PM (Bit 9) */ +#define UART_CTL0_PM_Msk (0x200UL) /*!< PM (Bitfield-Mask: 0x01) */ +#define UART_CTL0_PERRIE_Pos (8UL) /*!< PERRIE (Bit 8) */ +#define UART_CTL0_PERRIE_Msk (0x100UL) /*!< PERRIE (Bitfield-Mask: 0x01) */ +#define UART_CTL0_TBEIE_Pos (7UL) /*!< TBEIE (Bit 7) */ +#define UART_CTL0_TBEIE_Msk (0x80UL) /*!< TBEIE (Bitfield-Mask: 0x01) */ +#define UART_CTL0_TCIE_Pos (6UL) /*!< TCIE (Bit 6) */ +#define UART_CTL0_TCIE_Msk (0x40UL) /*!< TCIE (Bitfield-Mask: 0x01) */ +#define UART_CTL0_RBNEIE_Pos (5UL) /*!< RBNEIE (Bit 5) */ +#define UART_CTL0_RBNEIE_Msk (0x20UL) /*!< RBNEIE (Bitfield-Mask: 0x01) */ +#define UART_CTL0_IDLEIE_Pos (4UL) /*!< IDLEIE (Bit 4) */ +#define UART_CTL0_IDLEIE_Msk (0x10UL) /*!< IDLEIE (Bitfield-Mask: 0x01) */ +#define UART_CTL0_TEN_Pos (3UL) /*!< TEN (Bit 3) */ +#define UART_CTL0_TEN_Msk (0x8UL) /*!< TEN (Bitfield-Mask: 0x01) */ +#define UART_CTL0_REN_Pos (2UL) /*!< REN (Bit 2) */ +#define UART_CTL0_REN_Msk (0x4UL) /*!< REN (Bitfield-Mask: 0x01) */ +#define UART_CTL0_RWU_Pos (1UL) /*!< RWU (Bit 1) */ +#define UART_CTL0_RWU_Msk (0x2UL) /*!< RWU (Bitfield-Mask: 0x01) */ +#define UART_CTL0_SBKCMD_Pos (0UL) /*!< SBKCMD (Bit 0) */ +#define UART_CTL0_SBKCMD_Msk (0x1UL) /*!< SBKCMD (Bitfield-Mask: 0x01) */ +/* ========================================================= CTL1 ========================================================== */ +#define UART_CTL1_LMEN_Pos (14UL) /*!< LMEN (Bit 14) */ +#define UART_CTL1_LMEN_Msk (0x4000UL) /*!< LMEN (Bitfield-Mask: 0x01) */ +#define UART_CTL1_STB_Pos (12UL) /*!< STB (Bit 12) */ +#define UART_CTL1_STB_Msk (0x3000UL) /*!< STB (Bitfield-Mask: 0x03) */ +#define UART_CTL1_LBDIE_Pos (6UL) /*!< LBDIE (Bit 6) */ +#define UART_CTL1_LBDIE_Msk (0x40UL) /*!< LBDIE (Bitfield-Mask: 0x01) */ +#define UART_CTL1_LBLEN_Pos (5UL) /*!< LBLEN (Bit 5) */ +#define UART_CTL1_LBLEN_Msk (0x20UL) /*!< LBLEN (Bitfield-Mask: 0x01) */ +#define UART_CTL1_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ +#define UART_CTL1_ADDR_Msk (0xfUL) /*!< ADDR (Bitfield-Mask: 0x0f) */ +/* ========================================================= CTL2 ========================================================== */ +#define UART_CTL2_DENT_Pos (7UL) /*!< DENT (Bit 7) */ +#define UART_CTL2_DENT_Msk (0x80UL) /*!< DENT (Bitfield-Mask: 0x01) */ +#define UART_CTL2_DENR_Pos (6UL) /*!< DENR (Bit 6) */ +#define UART_CTL2_DENR_Msk (0x40UL) /*!< DENR (Bitfield-Mask: 0x01) */ +#define UART_CTL2_HDEN_Pos (3UL) /*!< HDEN (Bit 3) */ +#define UART_CTL2_HDEN_Msk (0x8UL) /*!< HDEN (Bitfield-Mask: 0x01) */ +#define UART_CTL2_IRLP_Pos (2UL) /*!< IRLP (Bit 2) */ +#define UART_CTL2_IRLP_Msk (0x4UL) /*!< IRLP (Bitfield-Mask: 0x01) */ +#define UART_CTL2_IREN_Pos (1UL) /*!< IREN (Bit 1) */ +#define UART_CTL2_IREN_Msk (0x2UL) /*!< IREN (Bitfield-Mask: 0x01) */ +#define UART_CTL2_ERRIE_Pos (0UL) /*!< ERRIE (Bit 0) */ +#define UART_CTL2_ERRIE_Msk (0x1UL) /*!< ERRIE (Bitfield-Mask: 0x01) */ +/* ========================================================== GP =========================================================== */ +#define UART_GP_PSC_Pos (0UL) /*!< PSC (Bit 0) */ +#define UART_GP_PSC_Msk (0xffUL) /*!< PSC (Bitfield-Mask: 0xff) */ + + +/* =========================================================================================================================== */ +/* ================ USBFS_GLOBAL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== GOTGCS ========================================================= */ +#define USBFS_GLOBAL_GOTGCS_SRPS_Pos (0UL) /*!< SRPS (Bit 0) */ +#define USBFS_GLOBAL_GOTGCS_SRPS_Msk (0x1UL) /*!< SRPS (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GOTGCS_SRPREQ_Pos (1UL) /*!< SRPREQ (Bit 1) */ +#define USBFS_GLOBAL_GOTGCS_SRPREQ_Msk (0x2UL) /*!< SRPREQ (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GOTGCS_HNPS_Pos (8UL) /*!< HNPS (Bit 8) */ +#define USBFS_GLOBAL_GOTGCS_HNPS_Msk (0x100UL) /*!< HNPS (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GOTGCS_HNPREQ_Pos (9UL) /*!< HNPREQ (Bit 9) */ +#define USBFS_GLOBAL_GOTGCS_HNPREQ_Msk (0x200UL) /*!< HNPREQ (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GOTGCS_HHNPEN_Pos (10UL) /*!< HHNPEN (Bit 10) */ +#define USBFS_GLOBAL_GOTGCS_HHNPEN_Msk (0x400UL) /*!< HHNPEN (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GOTGCS_DHNPEN_Pos (11UL) /*!< DHNPEN (Bit 11) */ +#define USBFS_GLOBAL_GOTGCS_DHNPEN_Msk (0x800UL) /*!< DHNPEN (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GOTGCS_IDPS_Pos (16UL) /*!< IDPS (Bit 16) */ +#define USBFS_GLOBAL_GOTGCS_IDPS_Msk (0x10000UL) /*!< IDPS (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GOTGCS_DI_Pos (17UL) /*!< DI (Bit 17) */ +#define USBFS_GLOBAL_GOTGCS_DI_Msk (0x20000UL) /*!< DI (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GOTGCS_ASV_Pos (18UL) /*!< ASV (Bit 18) */ +#define USBFS_GLOBAL_GOTGCS_ASV_Msk (0x40000UL) /*!< ASV (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GOTGCS_BSV_Pos (19UL) /*!< BSV (Bit 19) */ +#define USBFS_GLOBAL_GOTGCS_BSV_Msk (0x80000UL) /*!< BSV (Bitfield-Mask: 0x01) */ +/* ======================================================= GOTGINTF ======================================================== */ +#define USBFS_GLOBAL_GOTGINTF_SESEND_Pos (2UL) /*!< SESEND (Bit 2) */ +#define USBFS_GLOBAL_GOTGINTF_SESEND_Msk (0x4UL) /*!< SESEND (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GOTGINTF_SRPEND_Pos (8UL) /*!< SRPEND (Bit 8) */ +#define USBFS_GLOBAL_GOTGINTF_SRPEND_Msk (0x100UL) /*!< SRPEND (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GOTGINTF_HNPEND_Pos (9UL) /*!< HNPEND (Bit 9) */ +#define USBFS_GLOBAL_GOTGINTF_HNPEND_Msk (0x200UL) /*!< HNPEND (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GOTGINTF_HNPDET_Pos (17UL) /*!< HNPDET (Bit 17) */ +#define USBFS_GLOBAL_GOTGINTF_HNPDET_Msk (0x20000UL) /*!< HNPDET (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GOTGINTF_ADTO_Pos (18UL) /*!< ADTO (Bit 18) */ +#define USBFS_GLOBAL_GOTGINTF_ADTO_Msk (0x40000UL) /*!< ADTO (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GOTGINTF_DF_Pos (19UL) /*!< DF (Bit 19) */ +#define USBFS_GLOBAL_GOTGINTF_DF_Msk (0x80000UL) /*!< DF (Bitfield-Mask: 0x01) */ +/* ======================================================== GAHBCS ========================================================= */ +#define USBFS_GLOBAL_GAHBCS_GINTEN_Pos (0UL) /*!< GINTEN (Bit 0) */ +#define USBFS_GLOBAL_GAHBCS_GINTEN_Msk (0x1UL) /*!< GINTEN (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GAHBCS_TXFTH_Pos (7UL) /*!< TXFTH (Bit 7) */ +#define USBFS_GLOBAL_GAHBCS_TXFTH_Msk (0x80UL) /*!< TXFTH (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GAHBCS_PTXFTH_Pos (8UL) /*!< PTXFTH (Bit 8) */ +#define USBFS_GLOBAL_GAHBCS_PTXFTH_Msk (0x100UL) /*!< PTXFTH (Bitfield-Mask: 0x01) */ +/* ======================================================== GUSBCS ========================================================= */ +#define USBFS_GLOBAL_GUSBCS_TOC_Pos (0UL) /*!< TOC (Bit 0) */ +#define USBFS_GLOBAL_GUSBCS_TOC_Msk (0x7UL) /*!< TOC (Bitfield-Mask: 0x07) */ +#define USBFS_GLOBAL_GUSBCS_SRPCEN_Pos (8UL) /*!< SRPCEN (Bit 8) */ +#define USBFS_GLOBAL_GUSBCS_SRPCEN_Msk (0x100UL) /*!< SRPCEN (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GUSBCS_HNPCEN_Pos (9UL) /*!< HNPCEN (Bit 9) */ +#define USBFS_GLOBAL_GUSBCS_HNPCEN_Msk (0x200UL) /*!< HNPCEN (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GUSBCS_UTT_Pos (10UL) /*!< UTT (Bit 10) */ +#define USBFS_GLOBAL_GUSBCS_UTT_Msk (0x3c00UL) /*!< UTT (Bitfield-Mask: 0x0f) */ +#define USBFS_GLOBAL_GUSBCS_FHM_Pos (29UL) /*!< FHM (Bit 29) */ +#define USBFS_GLOBAL_GUSBCS_FHM_Msk (0x20000000UL) /*!< FHM (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GUSBCS_FDM_Pos (30UL) /*!< FDM (Bit 30) */ +#define USBFS_GLOBAL_GUSBCS_FDM_Msk (0x40000000UL) /*!< FDM (Bitfield-Mask: 0x01) */ +/* ======================================================== GRSTCTL ======================================================== */ +#define USBFS_GLOBAL_GRSTCTL_CSRST_Pos (0UL) /*!< CSRST (Bit 0) */ +#define USBFS_GLOBAL_GRSTCTL_CSRST_Msk (0x1UL) /*!< CSRST (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GRSTCTL_HCSRST_Pos (1UL) /*!< HCSRST (Bit 1) */ +#define USBFS_GLOBAL_GRSTCTL_HCSRST_Msk (0x2UL) /*!< HCSRST (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GRSTCTL_HFCRST_Pos (2UL) /*!< HFCRST (Bit 2) */ +#define USBFS_GLOBAL_GRSTCTL_HFCRST_Msk (0x4UL) /*!< HFCRST (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GRSTCTL_RXFF_Pos (4UL) /*!< RXFF (Bit 4) */ +#define USBFS_GLOBAL_GRSTCTL_RXFF_Msk (0x10UL) /*!< RXFF (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GRSTCTL_TXFF_Pos (5UL) /*!< TXFF (Bit 5) */ +#define USBFS_GLOBAL_GRSTCTL_TXFF_Msk (0x20UL) /*!< TXFF (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GRSTCTL_TXFNUM_Pos (6UL) /*!< TXFNUM (Bit 6) */ +#define USBFS_GLOBAL_GRSTCTL_TXFNUM_Msk (0x7c0UL) /*!< TXFNUM (Bitfield-Mask: 0x1f) */ +/* ========================================================= GINTF ========================================================= */ +#define USBFS_GLOBAL_GINTF_COPM_Pos (0UL) /*!< COPM (Bit 0) */ +#define USBFS_GLOBAL_GINTF_COPM_Msk (0x1UL) /*!< COPM (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTF_MFIF_Pos (1UL) /*!< MFIF (Bit 1) */ +#define USBFS_GLOBAL_GINTF_MFIF_Msk (0x2UL) /*!< MFIF (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTF_OTGIF_Pos (2UL) /*!< OTGIF (Bit 2) */ +#define USBFS_GLOBAL_GINTF_OTGIF_Msk (0x4UL) /*!< OTGIF (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTF_SOF_Pos (3UL) /*!< SOF (Bit 3) */ +#define USBFS_GLOBAL_GINTF_SOF_Msk (0x8UL) /*!< SOF (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTF_RXFNEIF_Pos (4UL) /*!< RXFNEIF (Bit 4) */ +#define USBFS_GLOBAL_GINTF_RXFNEIF_Msk (0x10UL) /*!< RXFNEIF (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTF_NPTXFEIF_Pos (5UL) /*!< NPTXFEIF (Bit 5) */ +#define USBFS_GLOBAL_GINTF_NPTXFEIF_Msk (0x20UL) /*!< NPTXFEIF (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTF_GNPINAK_Pos (6UL) /*!< GNPINAK (Bit 6) */ +#define USBFS_GLOBAL_GINTF_GNPINAK_Msk (0x40UL) /*!< GNPINAK (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTF_GONAK_Pos (7UL) /*!< GONAK (Bit 7) */ +#define USBFS_GLOBAL_GINTF_GONAK_Msk (0x80UL) /*!< GONAK (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTF_ESP_Pos (10UL) /*!< ESP (Bit 10) */ +#define USBFS_GLOBAL_GINTF_ESP_Msk (0x400UL) /*!< ESP (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTF_SP_Pos (11UL) /*!< SP (Bit 11) */ +#define USBFS_GLOBAL_GINTF_SP_Msk (0x800UL) /*!< SP (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTF_RST_Pos (12UL) /*!< RST (Bit 12) */ +#define USBFS_GLOBAL_GINTF_RST_Msk (0x1000UL) /*!< RST (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTF_ENUMF_Pos (13UL) /*!< ENUMF (Bit 13) */ +#define USBFS_GLOBAL_GINTF_ENUMF_Msk (0x2000UL) /*!< ENUMF (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTF_ISOOPDIF_Pos (14UL) /*!< ISOOPDIF (Bit 14) */ +#define USBFS_GLOBAL_GINTF_ISOOPDIF_Msk (0x4000UL) /*!< ISOOPDIF (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTF_EOPFIF_Pos (15UL) /*!< EOPFIF (Bit 15) */ +#define USBFS_GLOBAL_GINTF_EOPFIF_Msk (0x8000UL) /*!< EOPFIF (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTF_IEPIF_Pos (18UL) /*!< IEPIF (Bit 18) */ +#define USBFS_GLOBAL_GINTF_IEPIF_Msk (0x40000UL) /*!< IEPIF (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTF_OEPIF_Pos (19UL) /*!< OEPIF (Bit 19) */ +#define USBFS_GLOBAL_GINTF_OEPIF_Msk (0x80000UL) /*!< OEPIF (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTF_ISOINCIF_Pos (20UL) /*!< ISOINCIF (Bit 20) */ +#define USBFS_GLOBAL_GINTF_ISOINCIF_Msk (0x100000UL) /*!< ISOINCIF (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTF_PXNCIF_ISOONCIF_Pos (21UL) /*!< PXNCIF_ISOONCIF (Bit 21) */ +#define USBFS_GLOBAL_GINTF_PXNCIF_ISOONCIF_Msk (0x200000UL) /*!< PXNCIF_ISOONCIF (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTF_HPIF_Pos (24UL) /*!< HPIF (Bit 24) */ +#define USBFS_GLOBAL_GINTF_HPIF_Msk (0x1000000UL) /*!< HPIF (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTF_HCIF_Pos (25UL) /*!< HCIF (Bit 25) */ +#define USBFS_GLOBAL_GINTF_HCIF_Msk (0x2000000UL) /*!< HCIF (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTF_PTXFEIF_Pos (26UL) /*!< PTXFEIF (Bit 26) */ +#define USBFS_GLOBAL_GINTF_PTXFEIF_Msk (0x4000000UL) /*!< PTXFEIF (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTF_IDPSC_Pos (28UL) /*!< IDPSC (Bit 28) */ +#define USBFS_GLOBAL_GINTF_IDPSC_Msk (0x10000000UL) /*!< IDPSC (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTF_DISCIF_Pos (29UL) /*!< DISCIF (Bit 29) */ +#define USBFS_GLOBAL_GINTF_DISCIF_Msk (0x20000000UL) /*!< DISCIF (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTF_SESIF_Pos (30UL) /*!< SESIF (Bit 30) */ +#define USBFS_GLOBAL_GINTF_SESIF_Msk (0x40000000UL) /*!< SESIF (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTF_WKUPIF_Pos (31UL) /*!< WKUPIF (Bit 31) */ +#define USBFS_GLOBAL_GINTF_WKUPIF_Msk (0x80000000UL) /*!< WKUPIF (Bitfield-Mask: 0x01) */ +/* ======================================================== GINTEN ========================================================= */ +#define USBFS_GLOBAL_GINTEN_MFIE_Pos (1UL) /*!< MFIE (Bit 1) */ +#define USBFS_GLOBAL_GINTEN_MFIE_Msk (0x2UL) /*!< MFIE (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTEN_OTGIE_Pos (2UL) /*!< OTGIE (Bit 2) */ +#define USBFS_GLOBAL_GINTEN_OTGIE_Msk (0x4UL) /*!< OTGIE (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTEN_SOFIE_Pos (3UL) /*!< SOFIE (Bit 3) */ +#define USBFS_GLOBAL_GINTEN_SOFIE_Msk (0x8UL) /*!< SOFIE (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTEN_RXFNEIE_Pos (4UL) /*!< RXFNEIE (Bit 4) */ +#define USBFS_GLOBAL_GINTEN_RXFNEIE_Msk (0x10UL) /*!< RXFNEIE (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTEN_NPTXFEIE_Pos (5UL) /*!< NPTXFEIE (Bit 5) */ +#define USBFS_GLOBAL_GINTEN_NPTXFEIE_Msk (0x20UL) /*!< NPTXFEIE (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTEN_GNPINAKIE_Pos (6UL) /*!< GNPINAKIE (Bit 6) */ +#define USBFS_GLOBAL_GINTEN_GNPINAKIE_Msk (0x40UL) /*!< GNPINAKIE (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTEN_GONAKIE_Pos (7UL) /*!< GONAKIE (Bit 7) */ +#define USBFS_GLOBAL_GINTEN_GONAKIE_Msk (0x80UL) /*!< GONAKIE (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTEN_ESPIE_Pos (10UL) /*!< ESPIE (Bit 10) */ +#define USBFS_GLOBAL_GINTEN_ESPIE_Msk (0x400UL) /*!< ESPIE (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTEN_SPIE_Pos (11UL) /*!< SPIE (Bit 11) */ +#define USBFS_GLOBAL_GINTEN_SPIE_Msk (0x800UL) /*!< SPIE (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTEN_RSTIE_Pos (12UL) /*!< RSTIE (Bit 12) */ +#define USBFS_GLOBAL_GINTEN_RSTIE_Msk (0x1000UL) /*!< RSTIE (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTEN_ENUMFIE_Pos (13UL) /*!< ENUMFIE (Bit 13) */ +#define USBFS_GLOBAL_GINTEN_ENUMFIE_Msk (0x2000UL) /*!< ENUMFIE (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTEN_ISOOPDIE_Pos (14UL) /*!< ISOOPDIE (Bit 14) */ +#define USBFS_GLOBAL_GINTEN_ISOOPDIE_Msk (0x4000UL) /*!< ISOOPDIE (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTEN_EOPFIE_Pos (15UL) /*!< EOPFIE (Bit 15) */ +#define USBFS_GLOBAL_GINTEN_EOPFIE_Msk (0x8000UL) /*!< EOPFIE (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTEN_IEPIE_Pos (18UL) /*!< IEPIE (Bit 18) */ +#define USBFS_GLOBAL_GINTEN_IEPIE_Msk (0x40000UL) /*!< IEPIE (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTEN_OEPIE_Pos (19UL) /*!< OEPIE (Bit 19) */ +#define USBFS_GLOBAL_GINTEN_OEPIE_Msk (0x80000UL) /*!< OEPIE (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTEN_ISOINCIE_Pos (20UL) /*!< ISOINCIE (Bit 20) */ +#define USBFS_GLOBAL_GINTEN_ISOINCIE_Msk (0x100000UL) /*!< ISOINCIE (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTEN_PXNCIE_ISOONCIE_Pos (21UL) /*!< PXNCIE_ISOONCIE (Bit 21) */ +#define USBFS_GLOBAL_GINTEN_PXNCIE_ISOONCIE_Msk (0x200000UL) /*!< PXNCIE_ISOONCIE (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTEN_HPIE_Pos (24UL) /*!< HPIE (Bit 24) */ +#define USBFS_GLOBAL_GINTEN_HPIE_Msk (0x1000000UL) /*!< HPIE (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTEN_HCIE_Pos (25UL) /*!< HCIE (Bit 25) */ +#define USBFS_GLOBAL_GINTEN_HCIE_Msk (0x2000000UL) /*!< HCIE (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTEN_PTXFEIE_Pos (26UL) /*!< PTXFEIE (Bit 26) */ +#define USBFS_GLOBAL_GINTEN_PTXFEIE_Msk (0x4000000UL) /*!< PTXFEIE (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTEN_IDPSCIE_Pos (28UL) /*!< IDPSCIE (Bit 28) */ +#define USBFS_GLOBAL_GINTEN_IDPSCIE_Msk (0x10000000UL) /*!< IDPSCIE (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTEN_DISCIE_Pos (29UL) /*!< DISCIE (Bit 29) */ +#define USBFS_GLOBAL_GINTEN_DISCIE_Msk (0x20000000UL) /*!< DISCIE (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTEN_SESIE_Pos (30UL) /*!< SESIE (Bit 30) */ +#define USBFS_GLOBAL_GINTEN_SESIE_Msk (0x40000000UL) /*!< SESIE (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GINTEN_WKUPIE_Pos (31UL) /*!< WKUPIE (Bit 31) */ +#define USBFS_GLOBAL_GINTEN_WKUPIE_Msk (0x80000000UL) /*!< WKUPIE (Bitfield-Mask: 0x01) */ +/* ==================================================== GRSTATR_Device ===================================================== */ +#define USBFS_GLOBAL_GRSTATR_Device_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ +#define USBFS_GLOBAL_GRSTATR_Device_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +#define USBFS_GLOBAL_GRSTATR_Device_BCOUNT_Pos (4UL) /*!< BCOUNT (Bit 4) */ +#define USBFS_GLOBAL_GRSTATR_Device_BCOUNT_Msk (0x7ff0UL) /*!< BCOUNT (Bitfield-Mask: 0x7ff) */ +#define USBFS_GLOBAL_GRSTATR_Device_DPID_Pos (15UL) /*!< DPID (Bit 15) */ +#define USBFS_GLOBAL_GRSTATR_Device_DPID_Msk (0x18000UL) /*!< DPID (Bitfield-Mask: 0x03) */ +#define USBFS_GLOBAL_GRSTATR_Device_RPCKST_Pos (17UL) /*!< RPCKST (Bit 17) */ +#define USBFS_GLOBAL_GRSTATR_Device_RPCKST_Msk (0x1e0000UL) /*!< RPCKST (Bitfield-Mask: 0x0f) */ +/* ===================================================== GRSTATR_Host ====================================================== */ +#define USBFS_GLOBAL_GRSTATR_Host_CNUM_Pos (0UL) /*!< CNUM (Bit 0) */ +#define USBFS_GLOBAL_GRSTATR_Host_CNUM_Msk (0xfUL) /*!< CNUM (Bitfield-Mask: 0x0f) */ +#define USBFS_GLOBAL_GRSTATR_Host_BCOUNT_Pos (4UL) /*!< BCOUNT (Bit 4) */ +#define USBFS_GLOBAL_GRSTATR_Host_BCOUNT_Msk (0x7ff0UL) /*!< BCOUNT (Bitfield-Mask: 0x7ff) */ +#define USBFS_GLOBAL_GRSTATR_Host_DPID_Pos (15UL) /*!< DPID (Bit 15) */ +#define USBFS_GLOBAL_GRSTATR_Host_DPID_Msk (0x18000UL) /*!< DPID (Bitfield-Mask: 0x03) */ +#define USBFS_GLOBAL_GRSTATR_Host_RPCKST_Pos (17UL) /*!< RPCKST (Bit 17) */ +#define USBFS_GLOBAL_GRSTATR_Host_RPCKST_Msk (0x1e0000UL) /*!< RPCKST (Bitfield-Mask: 0x0f) */ +/* ==================================================== GRSTATP_Device ===================================================== */ +#define USBFS_GLOBAL_GRSTATP_Device_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ +#define USBFS_GLOBAL_GRSTATP_Device_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +#define USBFS_GLOBAL_GRSTATP_Device_BCOUNT_Pos (4UL) /*!< BCOUNT (Bit 4) */ +#define USBFS_GLOBAL_GRSTATP_Device_BCOUNT_Msk (0x7ff0UL) /*!< BCOUNT (Bitfield-Mask: 0x7ff) */ +#define USBFS_GLOBAL_GRSTATP_Device_DPID_Pos (15UL) /*!< DPID (Bit 15) */ +#define USBFS_GLOBAL_GRSTATP_Device_DPID_Msk (0x18000UL) /*!< DPID (Bitfield-Mask: 0x03) */ +#define USBFS_GLOBAL_GRSTATP_Device_RPCKST_Pos (17UL) /*!< RPCKST (Bit 17) */ +#define USBFS_GLOBAL_GRSTATP_Device_RPCKST_Msk (0x1e0000UL) /*!< RPCKST (Bitfield-Mask: 0x0f) */ +/* ===================================================== GRSTATP_Host ====================================================== */ +#define USBFS_GLOBAL_GRSTATP_Host_CNUM_Pos (0UL) /*!< CNUM (Bit 0) */ +#define USBFS_GLOBAL_GRSTATP_Host_CNUM_Msk (0xfUL) /*!< CNUM (Bitfield-Mask: 0x0f) */ +#define USBFS_GLOBAL_GRSTATP_Host_BCOUNT_Pos (4UL) /*!< BCOUNT (Bit 4) */ +#define USBFS_GLOBAL_GRSTATP_Host_BCOUNT_Msk (0x7ff0UL) /*!< BCOUNT (Bitfield-Mask: 0x7ff) */ +#define USBFS_GLOBAL_GRSTATP_Host_DPID_Pos (15UL) /*!< DPID (Bit 15) */ +#define USBFS_GLOBAL_GRSTATP_Host_DPID_Msk (0x18000UL) /*!< DPID (Bitfield-Mask: 0x03) */ +#define USBFS_GLOBAL_GRSTATP_Host_RPCKST_Pos (17UL) /*!< RPCKST (Bit 17) */ +#define USBFS_GLOBAL_GRSTATP_Host_RPCKST_Msk (0x1e0000UL) /*!< RPCKST (Bitfield-Mask: 0x0f) */ +/* ======================================================== GRFLEN ========================================================= */ +#define USBFS_GLOBAL_GRFLEN_RXFD_Pos (0UL) /*!< RXFD (Bit 0) */ +#define USBFS_GLOBAL_GRFLEN_RXFD_Msk (0xffffUL) /*!< RXFD (Bitfield-Mask: 0xffff) */ +/* ======================================================= HNPTFLEN ======================================================== */ +#define USBFS_GLOBAL_HNPTFLEN_HNPTXRSAR_Pos (0UL) /*!< HNPTXRSAR (Bit 0) */ +#define USBFS_GLOBAL_HNPTFLEN_HNPTXRSAR_Msk (0xffffUL) /*!< HNPTXRSAR (Bitfield-Mask: 0xffff) */ +#define USBFS_GLOBAL_HNPTFLEN_HNPTXFD_Pos (16UL) /*!< HNPTXFD (Bit 16) */ +#define USBFS_GLOBAL_HNPTFLEN_HNPTXFD_Msk (0xffff0000UL) /*!< HNPTXFD (Bitfield-Mask: 0xffff) */ +/* ====================================================== DIEP0TFLEN ======================================================= */ +#define USBFS_GLOBAL_DIEP0TFLEN_IEP0TXFD_Pos (16UL) /*!< IEP0TXFD (Bit 16) */ +#define USBFS_GLOBAL_DIEP0TFLEN_IEP0TXFD_Msk (0xffff0000UL) /*!< IEP0TXFD (Bitfield-Mask: 0xffff) */ +#define USBFS_GLOBAL_DIEP0TFLEN_IEP0TXRSAR_Pos (0UL) /*!< IEP0TXRSAR (Bit 0) */ +#define USBFS_GLOBAL_DIEP0TFLEN_IEP0TXRSAR_Msk (0xffffUL) /*!< IEP0TXRSAR (Bitfield-Mask: 0xffff) */ +/* ====================================================== HNPTFQSTAT ======================================================= */ +#define USBFS_GLOBAL_HNPTFQSTAT_NPTXFS_Pos (0UL) /*!< NPTXFS (Bit 0) */ +#define USBFS_GLOBAL_HNPTFQSTAT_NPTXFS_Msk (0xffffUL) /*!< NPTXFS (Bitfield-Mask: 0xffff) */ +#define USBFS_GLOBAL_HNPTFQSTAT_NPTXRQS_Pos (16UL) /*!< NPTXRQS (Bit 16) */ +#define USBFS_GLOBAL_HNPTFQSTAT_NPTXRQS_Msk (0xff0000UL) /*!< NPTXRQS (Bitfield-Mask: 0xff) */ +#define USBFS_GLOBAL_HNPTFQSTAT_NPTXRQTOP_Pos (24UL) /*!< NPTXRQTOP (Bit 24) */ +#define USBFS_GLOBAL_HNPTFQSTAT_NPTXRQTOP_Msk (0x7f000000UL) /*!< NPTXRQTOP (Bitfield-Mask: 0x7f) */ +/* ========================================================= GCCFG ========================================================= */ +#define USBFS_GLOBAL_GCCFG_PWRON_Pos (16UL) /*!< PWRON (Bit 16) */ +#define USBFS_GLOBAL_GCCFG_PWRON_Msk (0x10000UL) /*!< PWRON (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GCCFG_VBUSACEN_Pos (18UL) /*!< VBUSACEN (Bit 18) */ +#define USBFS_GLOBAL_GCCFG_VBUSACEN_Msk (0x40000UL) /*!< VBUSACEN (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GCCFG_VBUSBCEN_Pos (19UL) /*!< VBUSBCEN (Bit 19) */ +#define USBFS_GLOBAL_GCCFG_VBUSBCEN_Msk (0x80000UL) /*!< VBUSBCEN (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GCCFG_SOFOEN_Pos (20UL) /*!< SOFOEN (Bit 20) */ +#define USBFS_GLOBAL_GCCFG_SOFOEN_Msk (0x100000UL) /*!< SOFOEN (Bitfield-Mask: 0x01) */ +#define USBFS_GLOBAL_GCCFG_VBUSIG_Pos (21UL) /*!< VBUSIG (Bit 21) */ +#define USBFS_GLOBAL_GCCFG_VBUSIG_Msk (0x200000UL) /*!< VBUSIG (Bitfield-Mask: 0x01) */ +/* ========================================================== CID ========================================================== */ +#define USBFS_GLOBAL_CID_CID_Pos (0UL) /*!< CID (Bit 0) */ +#define USBFS_GLOBAL_CID_CID_Msk (0xffffffffUL) /*!< CID (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HPTFLEN ======================================================== */ +#define USBFS_GLOBAL_HPTFLEN_HPTXFSAR_Pos (0UL) /*!< HPTXFSAR (Bit 0) */ +#define USBFS_GLOBAL_HPTFLEN_HPTXFSAR_Msk (0xffffUL) /*!< HPTXFSAR (Bitfield-Mask: 0xffff) */ +#define USBFS_GLOBAL_HPTFLEN_HPTXFD_Pos (16UL) /*!< HPTXFD (Bit 16) */ +#define USBFS_GLOBAL_HPTFLEN_HPTXFD_Msk (0xffff0000UL) /*!< HPTXFD (Bitfield-Mask: 0xffff) */ +/* ====================================================== DIEP1TFLEN ======================================================= */ +#define USBFS_GLOBAL_DIEP1TFLEN_IEPTXRSAR_Pos (0UL) /*!< IEPTXRSAR (Bit 0) */ +#define USBFS_GLOBAL_DIEP1TFLEN_IEPTXRSAR_Msk (0xffffUL) /*!< IEPTXRSAR (Bitfield-Mask: 0xffff) */ +#define USBFS_GLOBAL_DIEP1TFLEN_IEPTXFD_Pos (16UL) /*!< IEPTXFD (Bit 16) */ +#define USBFS_GLOBAL_DIEP1TFLEN_IEPTXFD_Msk (0xffff0000UL) /*!< IEPTXFD (Bitfield-Mask: 0xffff) */ +/* ====================================================== DIEP2TFLEN ======================================================= */ +#define USBFS_GLOBAL_DIEP2TFLEN_IEPTXRSAR_Pos (0UL) /*!< IEPTXRSAR (Bit 0) */ +#define USBFS_GLOBAL_DIEP2TFLEN_IEPTXRSAR_Msk (0xffffUL) /*!< IEPTXRSAR (Bitfield-Mask: 0xffff) */ +#define USBFS_GLOBAL_DIEP2TFLEN_IEPTXFD_Pos (16UL) /*!< IEPTXFD (Bit 16) */ +#define USBFS_GLOBAL_DIEP2TFLEN_IEPTXFD_Msk (0xffff0000UL) /*!< IEPTXFD (Bitfield-Mask: 0xffff) */ +/* ====================================================== DIEP3TFLEN ======================================================= */ +#define USBFS_GLOBAL_DIEP3TFLEN_IEPTXRSAR_Pos (0UL) /*!< IEPTXRSAR (Bit 0) */ +#define USBFS_GLOBAL_DIEP3TFLEN_IEPTXRSAR_Msk (0xffffUL) /*!< IEPTXRSAR (Bitfield-Mask: 0xffff) */ +#define USBFS_GLOBAL_DIEP3TFLEN_IEPTXFD_Pos (16UL) /*!< IEPTXFD (Bit 16) */ +#define USBFS_GLOBAL_DIEP3TFLEN_IEPTXFD_Msk (0xffff0000UL) /*!< IEPTXFD (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ USBFS_HOST ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= HCTL ========================================================== */ +#define USBFS_HOST_HCTL_CLKSEL_Pos (0UL) /*!< CLKSEL (Bit 0) */ +#define USBFS_HOST_HCTL_CLKSEL_Msk (0x3UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ +/* ========================================================== HFT ========================================================== */ +#define USBFS_HOST_HFT_FRI_Pos (0UL) /*!< FRI (Bit 0) */ +#define USBFS_HOST_HFT_FRI_Msk (0xffffUL) /*!< FRI (Bitfield-Mask: 0xffff) */ +/* ======================================================== HFINFR ========================================================= */ +#define USBFS_HOST_HFINFR_FRNUM_Pos (0UL) /*!< FRNUM (Bit 0) */ +#define USBFS_HOST_HFINFR_FRNUM_Msk (0xffffUL) /*!< FRNUM (Bitfield-Mask: 0xffff) */ +#define USBFS_HOST_HFINFR_FRT_Pos (16UL) /*!< FRT (Bit 16) */ +#define USBFS_HOST_HFINFR_FRT_Msk (0xffff0000UL) /*!< FRT (Bitfield-Mask: 0xffff) */ +/* ======================================================= HPTFQSTAT ======================================================= */ +#define USBFS_HOST_HPTFQSTAT_PTXFS_Pos (0UL) /*!< PTXFS (Bit 0) */ +#define USBFS_HOST_HPTFQSTAT_PTXFS_Msk (0xffffUL) /*!< PTXFS (Bitfield-Mask: 0xffff) */ +#define USBFS_HOST_HPTFQSTAT_PTXREQS_Pos (16UL) /*!< PTXREQS (Bit 16) */ +#define USBFS_HOST_HPTFQSTAT_PTXREQS_Msk (0xff0000UL) /*!< PTXREQS (Bitfield-Mask: 0xff) */ +#define USBFS_HOST_HPTFQSTAT_PTXREQT_Pos (24UL) /*!< PTXREQT (Bit 24) */ +#define USBFS_HOST_HPTFQSTAT_PTXREQT_Msk (0xff000000UL) /*!< PTXREQT (Bitfield-Mask: 0xff) */ +/* ======================================================== HACHINT ======================================================== */ +#define USBFS_HOST_HACHINT_HACHINT_Pos (0UL) /*!< HACHINT (Bit 0) */ +#define USBFS_HOST_HACHINT_HACHINT_Msk (0xffUL) /*!< HACHINT (Bitfield-Mask: 0xff) */ +/* ======================================================= HACHINTEN ======================================================= */ +#define USBFS_HOST_HACHINTEN_CINTEN_Pos (0UL) /*!< CINTEN (Bit 0) */ +#define USBFS_HOST_HACHINTEN_CINTEN_Msk (0xffUL) /*!< CINTEN (Bitfield-Mask: 0xff) */ +/* ========================================================= HPCS ========================================================== */ +#define USBFS_HOST_HPCS_PCST_Pos (0UL) /*!< PCST (Bit 0) */ +#define USBFS_HOST_HPCS_PCST_Msk (0x1UL) /*!< PCST (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HPCS_PCD_Pos (1UL) /*!< PCD (Bit 1) */ +#define USBFS_HOST_HPCS_PCD_Msk (0x2UL) /*!< PCD (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HPCS_PE_Pos (2UL) /*!< PE (Bit 2) */ +#define USBFS_HOST_HPCS_PE_Msk (0x4UL) /*!< PE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HPCS_PEDC_Pos (3UL) /*!< PEDC (Bit 3) */ +#define USBFS_HOST_HPCS_PEDC_Msk (0x8UL) /*!< PEDC (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HPCS_PREM_Pos (6UL) /*!< PREM (Bit 6) */ +#define USBFS_HOST_HPCS_PREM_Msk (0x40UL) /*!< PREM (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HPCS_PSP_Pos (7UL) /*!< PSP (Bit 7) */ +#define USBFS_HOST_HPCS_PSP_Msk (0x80UL) /*!< PSP (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HPCS_PRST_Pos (8UL) /*!< PRST (Bit 8) */ +#define USBFS_HOST_HPCS_PRST_Msk (0x100UL) /*!< PRST (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HPCS_PLST_Pos (10UL) /*!< PLST (Bit 10) */ +#define USBFS_HOST_HPCS_PLST_Msk (0xc00UL) /*!< PLST (Bitfield-Mask: 0x03) */ +#define USBFS_HOST_HPCS_PP_Pos (12UL) /*!< PP (Bit 12) */ +#define USBFS_HOST_HPCS_PP_Msk (0x1000UL) /*!< PP (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HPCS_PS_Pos (17UL) /*!< PS (Bit 17) */ +#define USBFS_HOST_HPCS_PS_Msk (0x60000UL) /*!< PS (Bitfield-Mask: 0x03) */ +/* ======================================================== HCH0CTL ======================================================== */ +#define USBFS_HOST_HCH0CTL_MPL_Pos (0UL) /*!< MPL (Bit 0) */ +#define USBFS_HOST_HCH0CTL_MPL_Msk (0x7ffUL) /*!< MPL (Bitfield-Mask: 0x7ff) */ +#define USBFS_HOST_HCH0CTL_EPNUM_Pos (11UL) /*!< EPNUM (Bit 11) */ +#define USBFS_HOST_HCH0CTL_EPNUM_Msk (0x7800UL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +#define USBFS_HOST_HCH0CTL_EPDIR_Pos (15UL) /*!< EPDIR (Bit 15) */ +#define USBFS_HOST_HCH0CTL_EPDIR_Msk (0x8000UL) /*!< EPDIR (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH0CTL_LSD_Pos (17UL) /*!< LSD (Bit 17) */ +#define USBFS_HOST_HCH0CTL_LSD_Msk (0x20000UL) /*!< LSD (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH0CTL_EPTYPE_Pos (18UL) /*!< EPTYPE (Bit 18) */ +#define USBFS_HOST_HCH0CTL_EPTYPE_Msk (0xc0000UL) /*!< EPTYPE (Bitfield-Mask: 0x03) */ +#define USBFS_HOST_HCH0CTL_DAR_Pos (22UL) /*!< DAR (Bit 22) */ +#define USBFS_HOST_HCH0CTL_DAR_Msk (0x1fc00000UL) /*!< DAR (Bitfield-Mask: 0x7f) */ +#define USBFS_HOST_HCH0CTL_ODDFRM_Pos (29UL) /*!< ODDFRM (Bit 29) */ +#define USBFS_HOST_HCH0CTL_ODDFRM_Msk (0x20000000UL) /*!< ODDFRM (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH0CTL_CDIS_Pos (30UL) /*!< CDIS (Bit 30) */ +#define USBFS_HOST_HCH0CTL_CDIS_Msk (0x40000000UL) /*!< CDIS (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH0CTL_CEN_Pos (31UL) /*!< CEN (Bit 31) */ +#define USBFS_HOST_HCH0CTL_CEN_Msk (0x80000000UL) /*!< CEN (Bitfield-Mask: 0x01) */ +/* ======================================================== HCH1CTL ======================================================== */ +#define USBFS_HOST_HCH1CTL_MPL_Pos (0UL) /*!< MPL (Bit 0) */ +#define USBFS_HOST_HCH1CTL_MPL_Msk (0x7ffUL) /*!< MPL (Bitfield-Mask: 0x7ff) */ +#define USBFS_HOST_HCH1CTL_EPNUM_Pos (11UL) /*!< EPNUM (Bit 11) */ +#define USBFS_HOST_HCH1CTL_EPNUM_Msk (0x7800UL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +#define USBFS_HOST_HCH1CTL_EPDIR_Pos (15UL) /*!< EPDIR (Bit 15) */ +#define USBFS_HOST_HCH1CTL_EPDIR_Msk (0x8000UL) /*!< EPDIR (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH1CTL_LSD_Pos (17UL) /*!< LSD (Bit 17) */ +#define USBFS_HOST_HCH1CTL_LSD_Msk (0x20000UL) /*!< LSD (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH1CTL_EPTYPE_Pos (18UL) /*!< EPTYPE (Bit 18) */ +#define USBFS_HOST_HCH1CTL_EPTYPE_Msk (0xc0000UL) /*!< EPTYPE (Bitfield-Mask: 0x03) */ +#define USBFS_HOST_HCH1CTL_DAR_Pos (22UL) /*!< DAR (Bit 22) */ +#define USBFS_HOST_HCH1CTL_DAR_Msk (0x1fc00000UL) /*!< DAR (Bitfield-Mask: 0x7f) */ +#define USBFS_HOST_HCH1CTL_ODDFRM_Pos (29UL) /*!< ODDFRM (Bit 29) */ +#define USBFS_HOST_HCH1CTL_ODDFRM_Msk (0x20000000UL) /*!< ODDFRM (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH1CTL_CDIS_Pos (30UL) /*!< CDIS (Bit 30) */ +#define USBFS_HOST_HCH1CTL_CDIS_Msk (0x40000000UL) /*!< CDIS (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH1CTL_CEN_Pos (31UL) /*!< CEN (Bit 31) */ +#define USBFS_HOST_HCH1CTL_CEN_Msk (0x80000000UL) /*!< CEN (Bitfield-Mask: 0x01) */ +/* ======================================================== HCH2CTL ======================================================== */ +#define USBFS_HOST_HCH2CTL_MPL_Pos (0UL) /*!< MPL (Bit 0) */ +#define USBFS_HOST_HCH2CTL_MPL_Msk (0x7ffUL) /*!< MPL (Bitfield-Mask: 0x7ff) */ +#define USBFS_HOST_HCH2CTL_EPNUM_Pos (11UL) /*!< EPNUM (Bit 11) */ +#define USBFS_HOST_HCH2CTL_EPNUM_Msk (0x7800UL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +#define USBFS_HOST_HCH2CTL_EPDIR_Pos (15UL) /*!< EPDIR (Bit 15) */ +#define USBFS_HOST_HCH2CTL_EPDIR_Msk (0x8000UL) /*!< EPDIR (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH2CTL_LSD_Pos (17UL) /*!< LSD (Bit 17) */ +#define USBFS_HOST_HCH2CTL_LSD_Msk (0x20000UL) /*!< LSD (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH2CTL_EPTYPE_Pos (18UL) /*!< EPTYPE (Bit 18) */ +#define USBFS_HOST_HCH2CTL_EPTYPE_Msk (0xc0000UL) /*!< EPTYPE (Bitfield-Mask: 0x03) */ +#define USBFS_HOST_HCH2CTL_DAR_Pos (22UL) /*!< DAR (Bit 22) */ +#define USBFS_HOST_HCH2CTL_DAR_Msk (0x1fc00000UL) /*!< DAR (Bitfield-Mask: 0x7f) */ +#define USBFS_HOST_HCH2CTL_ODDFRM_Pos (29UL) /*!< ODDFRM (Bit 29) */ +#define USBFS_HOST_HCH2CTL_ODDFRM_Msk (0x20000000UL) /*!< ODDFRM (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH2CTL_CDIS_Pos (30UL) /*!< CDIS (Bit 30) */ +#define USBFS_HOST_HCH2CTL_CDIS_Msk (0x40000000UL) /*!< CDIS (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH2CTL_CEN_Pos (31UL) /*!< CEN (Bit 31) */ +#define USBFS_HOST_HCH2CTL_CEN_Msk (0x80000000UL) /*!< CEN (Bitfield-Mask: 0x01) */ +/* ======================================================== HCH3CTL ======================================================== */ +#define USBFS_HOST_HCH3CTL_MPL_Pos (0UL) /*!< MPL (Bit 0) */ +#define USBFS_HOST_HCH3CTL_MPL_Msk (0x7ffUL) /*!< MPL (Bitfield-Mask: 0x7ff) */ +#define USBFS_HOST_HCH3CTL_EPNUM_Pos (11UL) /*!< EPNUM (Bit 11) */ +#define USBFS_HOST_HCH3CTL_EPNUM_Msk (0x7800UL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +#define USBFS_HOST_HCH3CTL_EPDIR_Pos (15UL) /*!< EPDIR (Bit 15) */ +#define USBFS_HOST_HCH3CTL_EPDIR_Msk (0x8000UL) /*!< EPDIR (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH3CTL_LSD_Pos (17UL) /*!< LSD (Bit 17) */ +#define USBFS_HOST_HCH3CTL_LSD_Msk (0x20000UL) /*!< LSD (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH3CTL_EPTYPE_Pos (18UL) /*!< EPTYPE (Bit 18) */ +#define USBFS_HOST_HCH3CTL_EPTYPE_Msk (0xc0000UL) /*!< EPTYPE (Bitfield-Mask: 0x03) */ +#define USBFS_HOST_HCH3CTL_DAR_Pos (22UL) /*!< DAR (Bit 22) */ +#define USBFS_HOST_HCH3CTL_DAR_Msk (0x1fc00000UL) /*!< DAR (Bitfield-Mask: 0x7f) */ +#define USBFS_HOST_HCH3CTL_ODDFRM_Pos (29UL) /*!< ODDFRM (Bit 29) */ +#define USBFS_HOST_HCH3CTL_ODDFRM_Msk (0x20000000UL) /*!< ODDFRM (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH3CTL_CDIS_Pos (30UL) /*!< CDIS (Bit 30) */ +#define USBFS_HOST_HCH3CTL_CDIS_Msk (0x40000000UL) /*!< CDIS (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH3CTL_CEN_Pos (31UL) /*!< CEN (Bit 31) */ +#define USBFS_HOST_HCH3CTL_CEN_Msk (0x80000000UL) /*!< CEN (Bitfield-Mask: 0x01) */ +/* ======================================================== HCH4CTL ======================================================== */ +#define USBFS_HOST_HCH4CTL_MPL_Pos (0UL) /*!< MPL (Bit 0) */ +#define USBFS_HOST_HCH4CTL_MPL_Msk (0x7ffUL) /*!< MPL (Bitfield-Mask: 0x7ff) */ +#define USBFS_HOST_HCH4CTL_EPNUM_Pos (11UL) /*!< EPNUM (Bit 11) */ +#define USBFS_HOST_HCH4CTL_EPNUM_Msk (0x7800UL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +#define USBFS_HOST_HCH4CTL_EPDIR_Pos (15UL) /*!< EPDIR (Bit 15) */ +#define USBFS_HOST_HCH4CTL_EPDIR_Msk (0x8000UL) /*!< EPDIR (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH4CTL_LSD_Pos (17UL) /*!< LSD (Bit 17) */ +#define USBFS_HOST_HCH4CTL_LSD_Msk (0x20000UL) /*!< LSD (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH4CTL_EPTYPE_Pos (18UL) /*!< EPTYPE (Bit 18) */ +#define USBFS_HOST_HCH4CTL_EPTYPE_Msk (0xc0000UL) /*!< EPTYPE (Bitfield-Mask: 0x03) */ +#define USBFS_HOST_HCH4CTL_DAR_Pos (22UL) /*!< DAR (Bit 22) */ +#define USBFS_HOST_HCH4CTL_DAR_Msk (0x1fc00000UL) /*!< DAR (Bitfield-Mask: 0x7f) */ +#define USBFS_HOST_HCH4CTL_ODDFRM_Pos (29UL) /*!< ODDFRM (Bit 29) */ +#define USBFS_HOST_HCH4CTL_ODDFRM_Msk (0x20000000UL) /*!< ODDFRM (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH4CTL_CDIS_Pos (30UL) /*!< CDIS (Bit 30) */ +#define USBFS_HOST_HCH4CTL_CDIS_Msk (0x40000000UL) /*!< CDIS (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH4CTL_CEN_Pos (31UL) /*!< CEN (Bit 31) */ +#define USBFS_HOST_HCH4CTL_CEN_Msk (0x80000000UL) /*!< CEN (Bitfield-Mask: 0x01) */ +/* ======================================================== HCH5CTL ======================================================== */ +#define USBFS_HOST_HCH5CTL_MPL_Pos (0UL) /*!< MPL (Bit 0) */ +#define USBFS_HOST_HCH5CTL_MPL_Msk (0x7ffUL) /*!< MPL (Bitfield-Mask: 0x7ff) */ +#define USBFS_HOST_HCH5CTL_EPNUM_Pos (11UL) /*!< EPNUM (Bit 11) */ +#define USBFS_HOST_HCH5CTL_EPNUM_Msk (0x7800UL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +#define USBFS_HOST_HCH5CTL_EPDIR_Pos (15UL) /*!< EPDIR (Bit 15) */ +#define USBFS_HOST_HCH5CTL_EPDIR_Msk (0x8000UL) /*!< EPDIR (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH5CTL_LSD_Pos (17UL) /*!< LSD (Bit 17) */ +#define USBFS_HOST_HCH5CTL_LSD_Msk (0x20000UL) /*!< LSD (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH5CTL_EPTYPE_Pos (18UL) /*!< EPTYPE (Bit 18) */ +#define USBFS_HOST_HCH5CTL_EPTYPE_Msk (0xc0000UL) /*!< EPTYPE (Bitfield-Mask: 0x03) */ +#define USBFS_HOST_HCH5CTL_DAR_Pos (22UL) /*!< DAR (Bit 22) */ +#define USBFS_HOST_HCH5CTL_DAR_Msk (0x1fc00000UL) /*!< DAR (Bitfield-Mask: 0x7f) */ +#define USBFS_HOST_HCH5CTL_ODDFRM_Pos (29UL) /*!< ODDFRM (Bit 29) */ +#define USBFS_HOST_HCH5CTL_ODDFRM_Msk (0x20000000UL) /*!< ODDFRM (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH5CTL_CDIS_Pos (30UL) /*!< CDIS (Bit 30) */ +#define USBFS_HOST_HCH5CTL_CDIS_Msk (0x40000000UL) /*!< CDIS (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH5CTL_CEN_Pos (31UL) /*!< CEN (Bit 31) */ +#define USBFS_HOST_HCH5CTL_CEN_Msk (0x80000000UL) /*!< CEN (Bitfield-Mask: 0x01) */ +/* ======================================================== HCH6CTL ======================================================== */ +#define USBFS_HOST_HCH6CTL_MPL_Pos (0UL) /*!< MPL (Bit 0) */ +#define USBFS_HOST_HCH6CTL_MPL_Msk (0x7ffUL) /*!< MPL (Bitfield-Mask: 0x7ff) */ +#define USBFS_HOST_HCH6CTL_EPNUM_Pos (11UL) /*!< EPNUM (Bit 11) */ +#define USBFS_HOST_HCH6CTL_EPNUM_Msk (0x7800UL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +#define USBFS_HOST_HCH6CTL_EPDIR_Pos (15UL) /*!< EPDIR (Bit 15) */ +#define USBFS_HOST_HCH6CTL_EPDIR_Msk (0x8000UL) /*!< EPDIR (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH6CTL_LSD_Pos (17UL) /*!< LSD (Bit 17) */ +#define USBFS_HOST_HCH6CTL_LSD_Msk (0x20000UL) /*!< LSD (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH6CTL_EPTYPE_Pos (18UL) /*!< EPTYPE (Bit 18) */ +#define USBFS_HOST_HCH6CTL_EPTYPE_Msk (0xc0000UL) /*!< EPTYPE (Bitfield-Mask: 0x03) */ +#define USBFS_HOST_HCH6CTL_DAR_Pos (22UL) /*!< DAR (Bit 22) */ +#define USBFS_HOST_HCH6CTL_DAR_Msk (0x1fc00000UL) /*!< DAR (Bitfield-Mask: 0x7f) */ +#define USBFS_HOST_HCH6CTL_ODDFRM_Pos (29UL) /*!< ODDFRM (Bit 29) */ +#define USBFS_HOST_HCH6CTL_ODDFRM_Msk (0x20000000UL) /*!< ODDFRM (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH6CTL_CDIS_Pos (30UL) /*!< CDIS (Bit 30) */ +#define USBFS_HOST_HCH6CTL_CDIS_Msk (0x40000000UL) /*!< CDIS (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH6CTL_CEN_Pos (31UL) /*!< CEN (Bit 31) */ +#define USBFS_HOST_HCH6CTL_CEN_Msk (0x80000000UL) /*!< CEN (Bitfield-Mask: 0x01) */ +/* ======================================================== HCH7CTL ======================================================== */ +#define USBFS_HOST_HCH7CTL_MPL_Pos (0UL) /*!< MPL (Bit 0) */ +#define USBFS_HOST_HCH7CTL_MPL_Msk (0x7ffUL) /*!< MPL (Bitfield-Mask: 0x7ff) */ +#define USBFS_HOST_HCH7CTL_EPNUM_Pos (11UL) /*!< EPNUM (Bit 11) */ +#define USBFS_HOST_HCH7CTL_EPNUM_Msk (0x7800UL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ +#define USBFS_HOST_HCH7CTL_EPDIR_Pos (15UL) /*!< EPDIR (Bit 15) */ +#define USBFS_HOST_HCH7CTL_EPDIR_Msk (0x8000UL) /*!< EPDIR (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH7CTL_LSD_Pos (17UL) /*!< LSD (Bit 17) */ +#define USBFS_HOST_HCH7CTL_LSD_Msk (0x20000UL) /*!< LSD (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH7CTL_EPTYPE_Pos (18UL) /*!< EPTYPE (Bit 18) */ +#define USBFS_HOST_HCH7CTL_EPTYPE_Msk (0xc0000UL) /*!< EPTYPE (Bitfield-Mask: 0x03) */ +#define USBFS_HOST_HCH7CTL_DAR_Pos (22UL) /*!< DAR (Bit 22) */ +#define USBFS_HOST_HCH7CTL_DAR_Msk (0x1fc00000UL) /*!< DAR (Bitfield-Mask: 0x7f) */ +#define USBFS_HOST_HCH7CTL_ODDFRM_Pos (29UL) /*!< ODDFRM (Bit 29) */ +#define USBFS_HOST_HCH7CTL_ODDFRM_Msk (0x20000000UL) /*!< ODDFRM (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH7CTL_CDIS_Pos (30UL) /*!< CDIS (Bit 30) */ +#define USBFS_HOST_HCH7CTL_CDIS_Msk (0x40000000UL) /*!< CDIS (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH7CTL_CEN_Pos (31UL) /*!< CEN (Bit 31) */ +#define USBFS_HOST_HCH7CTL_CEN_Msk (0x80000000UL) /*!< CEN (Bitfield-Mask: 0x01) */ +/* ======================================================= HCH0INTF ======================================================== */ +#define USBFS_HOST_HCH0INTF_TF_Pos (0UL) /*!< TF (Bit 0) */ +#define USBFS_HOST_HCH0INTF_TF_Msk (0x1UL) /*!< TF (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH0INTF_CH_Pos (1UL) /*!< CH (Bit 1) */ +#define USBFS_HOST_HCH0INTF_CH_Msk (0x2UL) /*!< CH (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH0INTF_STALL_Pos (3UL) /*!< STALL (Bit 3) */ +#define USBFS_HOST_HCH0INTF_STALL_Msk (0x8UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH0INTF_NAK_Pos (4UL) /*!< NAK (Bit 4) */ +#define USBFS_HOST_HCH0INTF_NAK_Msk (0x10UL) /*!< NAK (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH0INTF_ACK_Pos (5UL) /*!< ACK (Bit 5) */ +#define USBFS_HOST_HCH0INTF_ACK_Msk (0x20UL) /*!< ACK (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH0INTF_USBER_Pos (7UL) /*!< USBER (Bit 7) */ +#define USBFS_HOST_HCH0INTF_USBER_Msk (0x80UL) /*!< USBER (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH0INTF_BBER_Pos (8UL) /*!< BBER (Bit 8) */ +#define USBFS_HOST_HCH0INTF_BBER_Msk (0x100UL) /*!< BBER (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH0INTF_REQOVR_Pos (9UL) /*!< REQOVR (Bit 9) */ +#define USBFS_HOST_HCH0INTF_REQOVR_Msk (0x200UL) /*!< REQOVR (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH0INTF_DTER_Pos (10UL) /*!< DTER (Bit 10) */ +#define USBFS_HOST_HCH0INTF_DTER_Msk (0x400UL) /*!< DTER (Bitfield-Mask: 0x01) */ +/* ======================================================= HCH1INTF ======================================================== */ +#define USBFS_HOST_HCH1INTF_TF_Pos (0UL) /*!< TF (Bit 0) */ +#define USBFS_HOST_HCH1INTF_TF_Msk (0x1UL) /*!< TF (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH1INTF_CH_Pos (1UL) /*!< CH (Bit 1) */ +#define USBFS_HOST_HCH1INTF_CH_Msk (0x2UL) /*!< CH (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH1INTF_STALL_Pos (3UL) /*!< STALL (Bit 3) */ +#define USBFS_HOST_HCH1INTF_STALL_Msk (0x8UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH1INTF_NAK_Pos (4UL) /*!< NAK (Bit 4) */ +#define USBFS_HOST_HCH1INTF_NAK_Msk (0x10UL) /*!< NAK (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH1INTF_ACK_Pos (5UL) /*!< ACK (Bit 5) */ +#define USBFS_HOST_HCH1INTF_ACK_Msk (0x20UL) /*!< ACK (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH1INTF_USBER_Pos (7UL) /*!< USBER (Bit 7) */ +#define USBFS_HOST_HCH1INTF_USBER_Msk (0x80UL) /*!< USBER (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH1INTF_BBER_Pos (8UL) /*!< BBER (Bit 8) */ +#define USBFS_HOST_HCH1INTF_BBER_Msk (0x100UL) /*!< BBER (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH1INTF_REQOVR_Pos (9UL) /*!< REQOVR (Bit 9) */ +#define USBFS_HOST_HCH1INTF_REQOVR_Msk (0x200UL) /*!< REQOVR (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH1INTF_DTER_Pos (10UL) /*!< DTER (Bit 10) */ +#define USBFS_HOST_HCH1INTF_DTER_Msk (0x400UL) /*!< DTER (Bitfield-Mask: 0x01) */ +/* ======================================================= HCH2INTF ======================================================== */ +#define USBFS_HOST_HCH2INTF_TF_Pos (0UL) /*!< TF (Bit 0) */ +#define USBFS_HOST_HCH2INTF_TF_Msk (0x1UL) /*!< TF (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH2INTF_CH_Pos (1UL) /*!< CH (Bit 1) */ +#define USBFS_HOST_HCH2INTF_CH_Msk (0x2UL) /*!< CH (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH2INTF_STALL_Pos (3UL) /*!< STALL (Bit 3) */ +#define USBFS_HOST_HCH2INTF_STALL_Msk (0x8UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH2INTF_NAK_Pos (4UL) /*!< NAK (Bit 4) */ +#define USBFS_HOST_HCH2INTF_NAK_Msk (0x10UL) /*!< NAK (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH2INTF_ACK_Pos (5UL) /*!< ACK (Bit 5) */ +#define USBFS_HOST_HCH2INTF_ACK_Msk (0x20UL) /*!< ACK (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH2INTF_USBER_Pos (7UL) /*!< USBER (Bit 7) */ +#define USBFS_HOST_HCH2INTF_USBER_Msk (0x80UL) /*!< USBER (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH2INTF_BBER_Pos (8UL) /*!< BBER (Bit 8) */ +#define USBFS_HOST_HCH2INTF_BBER_Msk (0x100UL) /*!< BBER (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH2INTF_REQOVR_Pos (9UL) /*!< REQOVR (Bit 9) */ +#define USBFS_HOST_HCH2INTF_REQOVR_Msk (0x200UL) /*!< REQOVR (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH2INTF_DTER_Pos (10UL) /*!< DTER (Bit 10) */ +#define USBFS_HOST_HCH2INTF_DTER_Msk (0x400UL) /*!< DTER (Bitfield-Mask: 0x01) */ +/* ======================================================= HCH3INTF ======================================================== */ +#define USBFS_HOST_HCH3INTF_TF_Pos (0UL) /*!< TF (Bit 0) */ +#define USBFS_HOST_HCH3INTF_TF_Msk (0x1UL) /*!< TF (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH3INTF_CH_Pos (1UL) /*!< CH (Bit 1) */ +#define USBFS_HOST_HCH3INTF_CH_Msk (0x2UL) /*!< CH (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH3INTF_STALL_Pos (3UL) /*!< STALL (Bit 3) */ +#define USBFS_HOST_HCH3INTF_STALL_Msk (0x8UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH3INTF_NAK_Pos (4UL) /*!< NAK (Bit 4) */ +#define USBFS_HOST_HCH3INTF_NAK_Msk (0x10UL) /*!< NAK (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH3INTF_ACK_Pos (5UL) /*!< ACK (Bit 5) */ +#define USBFS_HOST_HCH3INTF_ACK_Msk (0x20UL) /*!< ACK (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH3INTF_USBER_Pos (7UL) /*!< USBER (Bit 7) */ +#define USBFS_HOST_HCH3INTF_USBER_Msk (0x80UL) /*!< USBER (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH3INTF_BBER_Pos (8UL) /*!< BBER (Bit 8) */ +#define USBFS_HOST_HCH3INTF_BBER_Msk (0x100UL) /*!< BBER (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH3INTF_REQOVR_Pos (9UL) /*!< REQOVR (Bit 9) */ +#define USBFS_HOST_HCH3INTF_REQOVR_Msk (0x200UL) /*!< REQOVR (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH3INTF_DTER_Pos (10UL) /*!< DTER (Bit 10) */ +#define USBFS_HOST_HCH3INTF_DTER_Msk (0x400UL) /*!< DTER (Bitfield-Mask: 0x01) */ +/* ======================================================= HCH4INTF ======================================================== */ +#define USBFS_HOST_HCH4INTF_TF_Pos (0UL) /*!< TF (Bit 0) */ +#define USBFS_HOST_HCH4INTF_TF_Msk (0x1UL) /*!< TF (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH4INTF_CH_Pos (1UL) /*!< CH (Bit 1) */ +#define USBFS_HOST_HCH4INTF_CH_Msk (0x2UL) /*!< CH (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH4INTF_STALL_Pos (3UL) /*!< STALL (Bit 3) */ +#define USBFS_HOST_HCH4INTF_STALL_Msk (0x8UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH4INTF_NAK_Pos (4UL) /*!< NAK (Bit 4) */ +#define USBFS_HOST_HCH4INTF_NAK_Msk (0x10UL) /*!< NAK (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH4INTF_ACK_Pos (5UL) /*!< ACK (Bit 5) */ +#define USBFS_HOST_HCH4INTF_ACK_Msk (0x20UL) /*!< ACK (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH4INTF_USBER_Pos (7UL) /*!< USBER (Bit 7) */ +#define USBFS_HOST_HCH4INTF_USBER_Msk (0x80UL) /*!< USBER (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH4INTF_BBER_Pos (8UL) /*!< BBER (Bit 8) */ +#define USBFS_HOST_HCH4INTF_BBER_Msk (0x100UL) /*!< BBER (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH4INTF_REQOVR_Pos (9UL) /*!< REQOVR (Bit 9) */ +#define USBFS_HOST_HCH4INTF_REQOVR_Msk (0x200UL) /*!< REQOVR (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH4INTF_DTER_Pos (10UL) /*!< DTER (Bit 10) */ +#define USBFS_HOST_HCH4INTF_DTER_Msk (0x400UL) /*!< DTER (Bitfield-Mask: 0x01) */ +/* ======================================================= HCH5INTF ======================================================== */ +#define USBFS_HOST_HCH5INTF_TF_Pos (0UL) /*!< TF (Bit 0) */ +#define USBFS_HOST_HCH5INTF_TF_Msk (0x1UL) /*!< TF (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH5INTF_CH_Pos (1UL) /*!< CH (Bit 1) */ +#define USBFS_HOST_HCH5INTF_CH_Msk (0x2UL) /*!< CH (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH5INTF_STALL_Pos (3UL) /*!< STALL (Bit 3) */ +#define USBFS_HOST_HCH5INTF_STALL_Msk (0x8UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH5INTF_NAK_Pos (4UL) /*!< NAK (Bit 4) */ +#define USBFS_HOST_HCH5INTF_NAK_Msk (0x10UL) /*!< NAK (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH5INTF_ACK_Pos (5UL) /*!< ACK (Bit 5) */ +#define USBFS_HOST_HCH5INTF_ACK_Msk (0x20UL) /*!< ACK (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH5INTF_USBER_Pos (7UL) /*!< USBER (Bit 7) */ +#define USBFS_HOST_HCH5INTF_USBER_Msk (0x80UL) /*!< USBER (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH5INTF_BBER_Pos (8UL) /*!< BBER (Bit 8) */ +#define USBFS_HOST_HCH5INTF_BBER_Msk (0x100UL) /*!< BBER (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH5INTF_REQOVR_Pos (9UL) /*!< REQOVR (Bit 9) */ +#define USBFS_HOST_HCH5INTF_REQOVR_Msk (0x200UL) /*!< REQOVR (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH5INTF_DTER_Pos (10UL) /*!< DTER (Bit 10) */ +#define USBFS_HOST_HCH5INTF_DTER_Msk (0x400UL) /*!< DTER (Bitfield-Mask: 0x01) */ +/* ======================================================= HCH6INTF ======================================================== */ +#define USBFS_HOST_HCH6INTF_TF_Pos (0UL) /*!< TF (Bit 0) */ +#define USBFS_HOST_HCH6INTF_TF_Msk (0x1UL) /*!< TF (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH6INTF_CH_Pos (1UL) /*!< CH (Bit 1) */ +#define USBFS_HOST_HCH6INTF_CH_Msk (0x2UL) /*!< CH (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH6INTF_STALL_Pos (3UL) /*!< STALL (Bit 3) */ +#define USBFS_HOST_HCH6INTF_STALL_Msk (0x8UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH6INTF_NAK_Pos (4UL) /*!< NAK (Bit 4) */ +#define USBFS_HOST_HCH6INTF_NAK_Msk (0x10UL) /*!< NAK (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH6INTF_ACK_Pos (5UL) /*!< ACK (Bit 5) */ +#define USBFS_HOST_HCH6INTF_ACK_Msk (0x20UL) /*!< ACK (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH6INTF_USBER_Pos (7UL) /*!< USBER (Bit 7) */ +#define USBFS_HOST_HCH6INTF_USBER_Msk (0x80UL) /*!< USBER (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH6INTF_BBER_Pos (8UL) /*!< BBER (Bit 8) */ +#define USBFS_HOST_HCH6INTF_BBER_Msk (0x100UL) /*!< BBER (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH6INTF_REQOVR_Pos (9UL) /*!< REQOVR (Bit 9) */ +#define USBFS_HOST_HCH6INTF_REQOVR_Msk (0x200UL) /*!< REQOVR (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH6INTF_DTER_Pos (10UL) /*!< DTER (Bit 10) */ +#define USBFS_HOST_HCH6INTF_DTER_Msk (0x400UL) /*!< DTER (Bitfield-Mask: 0x01) */ +/* ======================================================= HCH7INTF ======================================================== */ +#define USBFS_HOST_HCH7INTF_TF_Pos (0UL) /*!< TF (Bit 0) */ +#define USBFS_HOST_HCH7INTF_TF_Msk (0x1UL) /*!< TF (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH7INTF_CH_Pos (1UL) /*!< CH (Bit 1) */ +#define USBFS_HOST_HCH7INTF_CH_Msk (0x2UL) /*!< CH (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH7INTF_STALL_Pos (3UL) /*!< STALL (Bit 3) */ +#define USBFS_HOST_HCH7INTF_STALL_Msk (0x8UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH7INTF_NAK_Pos (4UL) /*!< NAK (Bit 4) */ +#define USBFS_HOST_HCH7INTF_NAK_Msk (0x10UL) /*!< NAK (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH7INTF_ACK_Pos (5UL) /*!< ACK (Bit 5) */ +#define USBFS_HOST_HCH7INTF_ACK_Msk (0x20UL) /*!< ACK (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH7INTF_USBER_Pos (7UL) /*!< USBER (Bit 7) */ +#define USBFS_HOST_HCH7INTF_USBER_Msk (0x80UL) /*!< USBER (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH7INTF_BBER_Pos (8UL) /*!< BBER (Bit 8) */ +#define USBFS_HOST_HCH7INTF_BBER_Msk (0x100UL) /*!< BBER (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH7INTF_REQOVR_Pos (9UL) /*!< REQOVR (Bit 9) */ +#define USBFS_HOST_HCH7INTF_REQOVR_Msk (0x200UL) /*!< REQOVR (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH7INTF_DTER_Pos (10UL) /*!< DTER (Bit 10) */ +#define USBFS_HOST_HCH7INTF_DTER_Msk (0x400UL) /*!< DTER (Bitfield-Mask: 0x01) */ +/* ======================================================= HCH0INTEN ======================================================= */ +#define USBFS_HOST_HCH0INTEN_TFIE_Pos (0UL) /*!< TFIE (Bit 0) */ +#define USBFS_HOST_HCH0INTEN_TFIE_Msk (0x1UL) /*!< TFIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH0INTEN_CHIE_Pos (1UL) /*!< CHIE (Bit 1) */ +#define USBFS_HOST_HCH0INTEN_CHIE_Msk (0x2UL) /*!< CHIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH0INTEN_STALLIE_Pos (3UL) /*!< STALLIE (Bit 3) */ +#define USBFS_HOST_HCH0INTEN_STALLIE_Msk (0x8UL) /*!< STALLIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH0INTEN_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ +#define USBFS_HOST_HCH0INTEN_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH0INTEN_ACKIE_Pos (5UL) /*!< ACKIE (Bit 5) */ +#define USBFS_HOST_HCH0INTEN_ACKIE_Msk (0x20UL) /*!< ACKIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH0INTEN_USBERIE_Pos (7UL) /*!< USBERIE (Bit 7) */ +#define USBFS_HOST_HCH0INTEN_USBERIE_Msk (0x80UL) /*!< USBERIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH0INTEN_BBERIE_Pos (8UL) /*!< BBERIE (Bit 8) */ +#define USBFS_HOST_HCH0INTEN_BBERIE_Msk (0x100UL) /*!< BBERIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH0INTEN_REQOVRIE_Pos (9UL) /*!< REQOVRIE (Bit 9) */ +#define USBFS_HOST_HCH0INTEN_REQOVRIE_Msk (0x200UL) /*!< REQOVRIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH0INTEN_DTERIE_Pos (10UL) /*!< DTERIE (Bit 10) */ +#define USBFS_HOST_HCH0INTEN_DTERIE_Msk (0x400UL) /*!< DTERIE (Bitfield-Mask: 0x01) */ +/* ======================================================= HCH1INTEN ======================================================= */ +#define USBFS_HOST_HCH1INTEN_TFIE_Pos (0UL) /*!< TFIE (Bit 0) */ +#define USBFS_HOST_HCH1INTEN_TFIE_Msk (0x1UL) /*!< TFIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH1INTEN_CHIE_Pos (1UL) /*!< CHIE (Bit 1) */ +#define USBFS_HOST_HCH1INTEN_CHIE_Msk (0x2UL) /*!< CHIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH1INTEN_STALLIE_Pos (3UL) /*!< STALLIE (Bit 3) */ +#define USBFS_HOST_HCH1INTEN_STALLIE_Msk (0x8UL) /*!< STALLIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH1INTEN_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ +#define USBFS_HOST_HCH1INTEN_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH1INTEN_ACKIE_Pos (5UL) /*!< ACKIE (Bit 5) */ +#define USBFS_HOST_HCH1INTEN_ACKIE_Msk (0x20UL) /*!< ACKIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH1INTEN_USBERIE_Pos (7UL) /*!< USBERIE (Bit 7) */ +#define USBFS_HOST_HCH1INTEN_USBERIE_Msk (0x80UL) /*!< USBERIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH1INTEN_BBERIE_Pos (8UL) /*!< BBERIE (Bit 8) */ +#define USBFS_HOST_HCH1INTEN_BBERIE_Msk (0x100UL) /*!< BBERIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH1INTEN_REQOVRIE_Pos (9UL) /*!< REQOVRIE (Bit 9) */ +#define USBFS_HOST_HCH1INTEN_REQOVRIE_Msk (0x200UL) /*!< REQOVRIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH1INTEN_DTERIE_Pos (10UL) /*!< DTERIE (Bit 10) */ +#define USBFS_HOST_HCH1INTEN_DTERIE_Msk (0x400UL) /*!< DTERIE (Bitfield-Mask: 0x01) */ +/* ======================================================= HCH2INTEN ======================================================= */ +#define USBFS_HOST_HCH2INTEN_TFIE_Pos (0UL) /*!< TFIE (Bit 0) */ +#define USBFS_HOST_HCH2INTEN_TFIE_Msk (0x1UL) /*!< TFIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH2INTEN_CHIE_Pos (1UL) /*!< CHIE (Bit 1) */ +#define USBFS_HOST_HCH2INTEN_CHIE_Msk (0x2UL) /*!< CHIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH2INTEN_STALLIE_Pos (3UL) /*!< STALLIE (Bit 3) */ +#define USBFS_HOST_HCH2INTEN_STALLIE_Msk (0x8UL) /*!< STALLIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH2INTEN_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ +#define USBFS_HOST_HCH2INTEN_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH2INTEN_ACKIE_Pos (5UL) /*!< ACKIE (Bit 5) */ +#define USBFS_HOST_HCH2INTEN_ACKIE_Msk (0x20UL) /*!< ACKIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH2INTEN_USBERIE_Pos (7UL) /*!< USBERIE (Bit 7) */ +#define USBFS_HOST_HCH2INTEN_USBERIE_Msk (0x80UL) /*!< USBERIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH2INTEN_BBERIE_Pos (8UL) /*!< BBERIE (Bit 8) */ +#define USBFS_HOST_HCH2INTEN_BBERIE_Msk (0x100UL) /*!< BBERIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH2INTEN_REQOVRIE_Pos (9UL) /*!< REQOVRIE (Bit 9) */ +#define USBFS_HOST_HCH2INTEN_REQOVRIE_Msk (0x200UL) /*!< REQOVRIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH2INTEN_DTERIE_Pos (10UL) /*!< DTERIE (Bit 10) */ +#define USBFS_HOST_HCH2INTEN_DTERIE_Msk (0x400UL) /*!< DTERIE (Bitfield-Mask: 0x01) */ +/* ======================================================= HCH3INTEN ======================================================= */ +#define USBFS_HOST_HCH3INTEN_TFIE_Pos (0UL) /*!< TFIE (Bit 0) */ +#define USBFS_HOST_HCH3INTEN_TFIE_Msk (0x1UL) /*!< TFIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH3INTEN_CHIE_Pos (1UL) /*!< CHIE (Bit 1) */ +#define USBFS_HOST_HCH3INTEN_CHIE_Msk (0x2UL) /*!< CHIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH3INTEN_STALLIE_Pos (3UL) /*!< STALLIE (Bit 3) */ +#define USBFS_HOST_HCH3INTEN_STALLIE_Msk (0x8UL) /*!< STALLIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH3INTEN_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ +#define USBFS_HOST_HCH3INTEN_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH3INTEN_ACKIE_Pos (5UL) /*!< ACKIE (Bit 5) */ +#define USBFS_HOST_HCH3INTEN_ACKIE_Msk (0x20UL) /*!< ACKIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH3INTEN_USBERIE_Pos (7UL) /*!< USBERIE (Bit 7) */ +#define USBFS_HOST_HCH3INTEN_USBERIE_Msk (0x80UL) /*!< USBERIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH3INTEN_BBERIE_Pos (8UL) /*!< BBERIE (Bit 8) */ +#define USBFS_HOST_HCH3INTEN_BBERIE_Msk (0x100UL) /*!< BBERIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH3INTEN_REQOVRIE_Pos (9UL) /*!< REQOVRIE (Bit 9) */ +#define USBFS_HOST_HCH3INTEN_REQOVRIE_Msk (0x200UL) /*!< REQOVRIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH3INTEN_DTERIE_Pos (10UL) /*!< DTERIE (Bit 10) */ +#define USBFS_HOST_HCH3INTEN_DTERIE_Msk (0x400UL) /*!< DTERIE (Bitfield-Mask: 0x01) */ +/* ======================================================= HCH4INTEN ======================================================= */ +#define USBFS_HOST_HCH4INTEN_TFIE_Pos (0UL) /*!< TFIE (Bit 0) */ +#define USBFS_HOST_HCH4INTEN_TFIE_Msk (0x1UL) /*!< TFIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH4INTEN_CHIE_Pos (1UL) /*!< CHIE (Bit 1) */ +#define USBFS_HOST_HCH4INTEN_CHIE_Msk (0x2UL) /*!< CHIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH4INTEN_STALLIE_Pos (3UL) /*!< STALLIE (Bit 3) */ +#define USBFS_HOST_HCH4INTEN_STALLIE_Msk (0x8UL) /*!< STALLIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH4INTEN_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ +#define USBFS_HOST_HCH4INTEN_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH4INTEN_ACKIE_Pos (5UL) /*!< ACKIE (Bit 5) */ +#define USBFS_HOST_HCH4INTEN_ACKIE_Msk (0x20UL) /*!< ACKIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH4INTEN_USBERIE_Pos (7UL) /*!< USBERIE (Bit 7) */ +#define USBFS_HOST_HCH4INTEN_USBERIE_Msk (0x80UL) /*!< USBERIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH4INTEN_BBERIE_Pos (8UL) /*!< BBERIE (Bit 8) */ +#define USBFS_HOST_HCH4INTEN_BBERIE_Msk (0x100UL) /*!< BBERIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH4INTEN_REQOVRIE_Pos (9UL) /*!< REQOVRIE (Bit 9) */ +#define USBFS_HOST_HCH4INTEN_REQOVRIE_Msk (0x200UL) /*!< REQOVRIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH4INTEN_DTERIE_Pos (10UL) /*!< DTERIE (Bit 10) */ +#define USBFS_HOST_HCH4INTEN_DTERIE_Msk (0x400UL) /*!< DTERIE (Bitfield-Mask: 0x01) */ +/* ======================================================= HCH5INTEN ======================================================= */ +#define USBFS_HOST_HCH5INTEN_TFIE_Pos (0UL) /*!< TFIE (Bit 0) */ +#define USBFS_HOST_HCH5INTEN_TFIE_Msk (0x1UL) /*!< TFIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH5INTEN_CHIE_Pos (1UL) /*!< CHIE (Bit 1) */ +#define USBFS_HOST_HCH5INTEN_CHIE_Msk (0x2UL) /*!< CHIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH5INTEN_STALLIE_Pos (3UL) /*!< STALLIE (Bit 3) */ +#define USBFS_HOST_HCH5INTEN_STALLIE_Msk (0x8UL) /*!< STALLIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH5INTEN_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ +#define USBFS_HOST_HCH5INTEN_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH5INTEN_ACKIE_Pos (5UL) /*!< ACKIE (Bit 5) */ +#define USBFS_HOST_HCH5INTEN_ACKIE_Msk (0x20UL) /*!< ACKIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH5INTEN_USBERIE_Pos (7UL) /*!< USBERIE (Bit 7) */ +#define USBFS_HOST_HCH5INTEN_USBERIE_Msk (0x80UL) /*!< USBERIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH5INTEN_BBERIE_Pos (8UL) /*!< BBERIE (Bit 8) */ +#define USBFS_HOST_HCH5INTEN_BBERIE_Msk (0x100UL) /*!< BBERIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH5INTEN_REQOVRIE_Pos (9UL) /*!< REQOVRIE (Bit 9) */ +#define USBFS_HOST_HCH5INTEN_REQOVRIE_Msk (0x200UL) /*!< REQOVRIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH5INTEN_DTERIE_Pos (10UL) /*!< DTERIE (Bit 10) */ +#define USBFS_HOST_HCH5INTEN_DTERIE_Msk (0x400UL) /*!< DTERIE (Bitfield-Mask: 0x01) */ +/* ======================================================= HCH6INTEN ======================================================= */ +#define USBFS_HOST_HCH6INTEN_TFIE_Pos (0UL) /*!< TFIE (Bit 0) */ +#define USBFS_HOST_HCH6INTEN_TFIE_Msk (0x1UL) /*!< TFIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH6INTEN_CHIE_Pos (1UL) /*!< CHIE (Bit 1) */ +#define USBFS_HOST_HCH6INTEN_CHIE_Msk (0x2UL) /*!< CHIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH6INTEN_STALLIE_Pos (3UL) /*!< STALLIE (Bit 3) */ +#define USBFS_HOST_HCH6INTEN_STALLIE_Msk (0x8UL) /*!< STALLIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH6INTEN_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ +#define USBFS_HOST_HCH6INTEN_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH6INTEN_ACKIE_Pos (5UL) /*!< ACKIE (Bit 5) */ +#define USBFS_HOST_HCH6INTEN_ACKIE_Msk (0x20UL) /*!< ACKIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH6INTEN_USBERIE_Pos (7UL) /*!< USBERIE (Bit 7) */ +#define USBFS_HOST_HCH6INTEN_USBERIE_Msk (0x80UL) /*!< USBERIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH6INTEN_BBERIE_Pos (8UL) /*!< BBERIE (Bit 8) */ +#define USBFS_HOST_HCH6INTEN_BBERIE_Msk (0x100UL) /*!< BBERIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH6INTEN_REQOVRIE_Pos (9UL) /*!< REQOVRIE (Bit 9) */ +#define USBFS_HOST_HCH6INTEN_REQOVRIE_Msk (0x200UL) /*!< REQOVRIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH6INTEN_DTERIE_Pos (10UL) /*!< DTERIE (Bit 10) */ +#define USBFS_HOST_HCH6INTEN_DTERIE_Msk (0x400UL) /*!< DTERIE (Bitfield-Mask: 0x01) */ +/* ======================================================= HCH7INTEN ======================================================= */ +#define USBFS_HOST_HCH7INTEN_TFIE_Pos (0UL) /*!< TFIE (Bit 0) */ +#define USBFS_HOST_HCH7INTEN_TFIE_Msk (0x1UL) /*!< TFIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH7INTEN_CHIE_Pos (1UL) /*!< CHIE (Bit 1) */ +#define USBFS_HOST_HCH7INTEN_CHIE_Msk (0x2UL) /*!< CHIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH7INTEN_STALLIE_Pos (3UL) /*!< STALLIE (Bit 3) */ +#define USBFS_HOST_HCH7INTEN_STALLIE_Msk (0x8UL) /*!< STALLIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH7INTEN_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ +#define USBFS_HOST_HCH7INTEN_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH7INTEN_ACKIE_Pos (5UL) /*!< ACKIE (Bit 5) */ +#define USBFS_HOST_HCH7INTEN_ACKIE_Msk (0x20UL) /*!< ACKIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH7INTEN_USBERIE_Pos (7UL) /*!< USBERIE (Bit 7) */ +#define USBFS_HOST_HCH7INTEN_USBERIE_Msk (0x80UL) /*!< USBERIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH7INTEN_BBERIE_Pos (8UL) /*!< BBERIE (Bit 8) */ +#define USBFS_HOST_HCH7INTEN_BBERIE_Msk (0x100UL) /*!< BBERIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH7INTEN_REQOVRIE_Pos (9UL) /*!< REQOVRIE (Bit 9) */ +#define USBFS_HOST_HCH7INTEN_REQOVRIE_Msk (0x200UL) /*!< REQOVRIE (Bitfield-Mask: 0x01) */ +#define USBFS_HOST_HCH7INTEN_DTERIE_Pos (10UL) /*!< DTERIE (Bit 10) */ +#define USBFS_HOST_HCH7INTEN_DTERIE_Msk (0x400UL) /*!< DTERIE (Bitfield-Mask: 0x01) */ +/* ======================================================== HCH0LEN ======================================================== */ +#define USBFS_HOST_HCH0LEN_TLEN_Pos (0UL) /*!< TLEN (Bit 0) */ +#define USBFS_HOST_HCH0LEN_TLEN_Msk (0x7ffffUL) /*!< TLEN (Bitfield-Mask: 0x7ffff) */ +#define USBFS_HOST_HCH0LEN_PCNT_Pos (19UL) /*!< PCNT (Bit 19) */ +#define USBFS_HOST_HCH0LEN_PCNT_Msk (0x1ff80000UL) /*!< PCNT (Bitfield-Mask: 0x3ff) */ +#define USBFS_HOST_HCH0LEN_DPID_Pos (29UL) /*!< DPID (Bit 29) */ +#define USBFS_HOST_HCH0LEN_DPID_Msk (0x60000000UL) /*!< DPID (Bitfield-Mask: 0x03) */ +/* ======================================================== HCH1LEN ======================================================== */ +#define USBFS_HOST_HCH1LEN_TLEN_Pos (0UL) /*!< TLEN (Bit 0) */ +#define USBFS_HOST_HCH1LEN_TLEN_Msk (0x7ffffUL) /*!< TLEN (Bitfield-Mask: 0x7ffff) */ +#define USBFS_HOST_HCH1LEN_PCNT_Pos (19UL) /*!< PCNT (Bit 19) */ +#define USBFS_HOST_HCH1LEN_PCNT_Msk (0x1ff80000UL) /*!< PCNT (Bitfield-Mask: 0x3ff) */ +#define USBFS_HOST_HCH1LEN_DPID_Pos (29UL) /*!< DPID (Bit 29) */ +#define USBFS_HOST_HCH1LEN_DPID_Msk (0x60000000UL) /*!< DPID (Bitfield-Mask: 0x03) */ +/* ======================================================== HCH2LEN ======================================================== */ +#define USBFS_HOST_HCH2LEN_TLEN_Pos (0UL) /*!< TLEN (Bit 0) */ +#define USBFS_HOST_HCH2LEN_TLEN_Msk (0x7ffffUL) /*!< TLEN (Bitfield-Mask: 0x7ffff) */ +#define USBFS_HOST_HCH2LEN_PCNT_Pos (19UL) /*!< PCNT (Bit 19) */ +#define USBFS_HOST_HCH2LEN_PCNT_Msk (0x1ff80000UL) /*!< PCNT (Bitfield-Mask: 0x3ff) */ +#define USBFS_HOST_HCH2LEN_DPID_Pos (29UL) /*!< DPID (Bit 29) */ +#define USBFS_HOST_HCH2LEN_DPID_Msk (0x60000000UL) /*!< DPID (Bitfield-Mask: 0x03) */ +/* ======================================================== HCH3LEN ======================================================== */ +#define USBFS_HOST_HCH3LEN_TLEN_Pos (0UL) /*!< TLEN (Bit 0) */ +#define USBFS_HOST_HCH3LEN_TLEN_Msk (0x7ffffUL) /*!< TLEN (Bitfield-Mask: 0x7ffff) */ +#define USBFS_HOST_HCH3LEN_PCNT_Pos (19UL) /*!< PCNT (Bit 19) */ +#define USBFS_HOST_HCH3LEN_PCNT_Msk (0x1ff80000UL) /*!< PCNT (Bitfield-Mask: 0x3ff) */ +#define USBFS_HOST_HCH3LEN_DPID_Pos (29UL) /*!< DPID (Bit 29) */ +#define USBFS_HOST_HCH3LEN_DPID_Msk (0x60000000UL) /*!< DPID (Bitfield-Mask: 0x03) */ +/* ======================================================== HCH4LEN ======================================================== */ +#define USBFS_HOST_HCH4LEN_TLEN_Pos (0UL) /*!< TLEN (Bit 0) */ +#define USBFS_HOST_HCH4LEN_TLEN_Msk (0x7ffffUL) /*!< TLEN (Bitfield-Mask: 0x7ffff) */ +#define USBFS_HOST_HCH4LEN_PCNT_Pos (19UL) /*!< PCNT (Bit 19) */ +#define USBFS_HOST_HCH4LEN_PCNT_Msk (0x1ff80000UL) /*!< PCNT (Bitfield-Mask: 0x3ff) */ +#define USBFS_HOST_HCH4LEN_DPID_Pos (29UL) /*!< DPID (Bit 29) */ +#define USBFS_HOST_HCH4LEN_DPID_Msk (0x60000000UL) /*!< DPID (Bitfield-Mask: 0x03) */ +/* ======================================================== HCH5LEN ======================================================== */ +#define USBFS_HOST_HCH5LEN_TLEN_Pos (0UL) /*!< TLEN (Bit 0) */ +#define USBFS_HOST_HCH5LEN_TLEN_Msk (0x7ffffUL) /*!< TLEN (Bitfield-Mask: 0x7ffff) */ +#define USBFS_HOST_HCH5LEN_PCNT_Pos (19UL) /*!< PCNT (Bit 19) */ +#define USBFS_HOST_HCH5LEN_PCNT_Msk (0x1ff80000UL) /*!< PCNT (Bitfield-Mask: 0x3ff) */ +#define USBFS_HOST_HCH5LEN_DPID_Pos (29UL) /*!< DPID (Bit 29) */ +#define USBFS_HOST_HCH5LEN_DPID_Msk (0x60000000UL) /*!< DPID (Bitfield-Mask: 0x03) */ +/* ======================================================== HCH6LEN ======================================================== */ +#define USBFS_HOST_HCH6LEN_TLEN_Pos (0UL) /*!< TLEN (Bit 0) */ +#define USBFS_HOST_HCH6LEN_TLEN_Msk (0x7ffffUL) /*!< TLEN (Bitfield-Mask: 0x7ffff) */ +#define USBFS_HOST_HCH6LEN_PCNT_Pos (19UL) /*!< PCNT (Bit 19) */ +#define USBFS_HOST_HCH6LEN_PCNT_Msk (0x1ff80000UL) /*!< PCNT (Bitfield-Mask: 0x3ff) */ +#define USBFS_HOST_HCH6LEN_DPID_Pos (29UL) /*!< DPID (Bit 29) */ +#define USBFS_HOST_HCH6LEN_DPID_Msk (0x60000000UL) /*!< DPID (Bitfield-Mask: 0x03) */ +/* ======================================================== HCH7LEN ======================================================== */ +#define USBFS_HOST_HCH7LEN_TLEN_Pos (0UL) /*!< TLEN (Bit 0) */ +#define USBFS_HOST_HCH7LEN_TLEN_Msk (0x7ffffUL) /*!< TLEN (Bitfield-Mask: 0x7ffff) */ +#define USBFS_HOST_HCH7LEN_PCNT_Pos (19UL) /*!< PCNT (Bit 19) */ +#define USBFS_HOST_HCH7LEN_PCNT_Msk (0x1ff80000UL) /*!< PCNT (Bitfield-Mask: 0x3ff) */ +#define USBFS_HOST_HCH7LEN_DPID_Pos (29UL) /*!< DPID (Bit 29) */ +#define USBFS_HOST_HCH7LEN_DPID_Msk (0x60000000UL) /*!< DPID (Bitfield-Mask: 0x03) */ + + +/* =========================================================================================================================== */ +/* ================ USBFS_DEVICE ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DCFG ========================================================== */ +#define USBFS_DEVICE_DCFG_DS_Pos (0UL) /*!< DS (Bit 0) */ +#define USBFS_DEVICE_DCFG_DS_Msk (0x3UL) /*!< DS (Bitfield-Mask: 0x03) */ +#define USBFS_DEVICE_DCFG_NZLSOH_Pos (2UL) /*!< NZLSOH (Bit 2) */ +#define USBFS_DEVICE_DCFG_NZLSOH_Msk (0x4UL) /*!< NZLSOH (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DCFG_DAR_Pos (4UL) /*!< DAR (Bit 4) */ +#define USBFS_DEVICE_DCFG_DAR_Msk (0x7f0UL) /*!< DAR (Bitfield-Mask: 0x7f) */ +#define USBFS_DEVICE_DCFG_EOPFT_Pos (11UL) /*!< EOPFT (Bit 11) */ +#define USBFS_DEVICE_DCFG_EOPFT_Msk (0x1800UL) /*!< EOPFT (Bitfield-Mask: 0x03) */ +/* ========================================================= DCTL ========================================================== */ +#define USBFS_DEVICE_DCTL_RWKUP_Pos (0UL) /*!< RWKUP (Bit 0) */ +#define USBFS_DEVICE_DCTL_RWKUP_Msk (0x1UL) /*!< RWKUP (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DCTL_SD_Pos (1UL) /*!< SD (Bit 1) */ +#define USBFS_DEVICE_DCTL_SD_Msk (0x2UL) /*!< SD (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DCTL_GINS_Pos (2UL) /*!< GINS (Bit 2) */ +#define USBFS_DEVICE_DCTL_GINS_Msk (0x4UL) /*!< GINS (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DCTL_GONS_Pos (3UL) /*!< GONS (Bit 3) */ +#define USBFS_DEVICE_DCTL_GONS_Msk (0x8UL) /*!< GONS (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DCTL_SGINAK_Pos (7UL) /*!< SGINAK (Bit 7) */ +#define USBFS_DEVICE_DCTL_SGINAK_Msk (0x80UL) /*!< SGINAK (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DCTL_CGINAK_Pos (8UL) /*!< CGINAK (Bit 8) */ +#define USBFS_DEVICE_DCTL_CGINAK_Msk (0x100UL) /*!< CGINAK (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DCTL_SGONAK_Pos (9UL) /*!< SGONAK (Bit 9) */ +#define USBFS_DEVICE_DCTL_SGONAK_Msk (0x200UL) /*!< SGONAK (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DCTL_CGONAK_Pos (10UL) /*!< CGONAK (Bit 10) */ +#define USBFS_DEVICE_DCTL_CGONAK_Msk (0x400UL) /*!< CGONAK (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DCTL_POIF_Pos (11UL) /*!< POIF (Bit 11) */ +#define USBFS_DEVICE_DCTL_POIF_Msk (0x800UL) /*!< POIF (Bitfield-Mask: 0x01) */ +/* ========================================================= DSTAT ========================================================= */ +#define USBFS_DEVICE_DSTAT_SPST_Pos (0UL) /*!< SPST (Bit 0) */ +#define USBFS_DEVICE_DSTAT_SPST_Msk (0x1UL) /*!< SPST (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DSTAT_ES_Pos (1UL) /*!< ES (Bit 1) */ +#define USBFS_DEVICE_DSTAT_ES_Msk (0x6UL) /*!< ES (Bitfield-Mask: 0x03) */ +#define USBFS_DEVICE_DSTAT_FNRSOF_Pos (8UL) /*!< FNRSOF (Bit 8) */ +#define USBFS_DEVICE_DSTAT_FNRSOF_Msk (0x3fff00UL) /*!< FNRSOF (Bitfield-Mask: 0x3fff) */ +/* ======================================================= DIEPINTEN ======================================================= */ +#define USBFS_DEVICE_DIEPINTEN_TFEN_Pos (0UL) /*!< TFEN (Bit 0) */ +#define USBFS_DEVICE_DIEPINTEN_TFEN_Msk (0x1UL) /*!< TFEN (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEPINTEN_EPDISEN_Pos (1UL) /*!< EPDISEN (Bit 1) */ +#define USBFS_DEVICE_DIEPINTEN_EPDISEN_Msk (0x2UL) /*!< EPDISEN (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEPINTEN_CITOEN_Pos (3UL) /*!< CITOEN (Bit 3) */ +#define USBFS_DEVICE_DIEPINTEN_CITOEN_Msk (0x8UL) /*!< CITOEN (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEPINTEN_EPTXFUDEN_Pos (4UL) /*!< EPTXFUDEN (Bit 4) */ +#define USBFS_DEVICE_DIEPINTEN_EPTXFUDEN_Msk (0x10UL) /*!< EPTXFUDEN (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEPINTEN_IEPNEEN_Pos (6UL) /*!< IEPNEEN (Bit 6) */ +#define USBFS_DEVICE_DIEPINTEN_IEPNEEN_Msk (0x40UL) /*!< IEPNEEN (Bitfield-Mask: 0x01) */ +/* ======================================================= DOEPINTEN ======================================================= */ +#define USBFS_DEVICE_DOEPINTEN_TFEN_Pos (0UL) /*!< TFEN (Bit 0) */ +#define USBFS_DEVICE_DOEPINTEN_TFEN_Msk (0x1UL) /*!< TFEN (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEPINTEN_EPDISEN_Pos (1UL) /*!< EPDISEN (Bit 1) */ +#define USBFS_DEVICE_DOEPINTEN_EPDISEN_Msk (0x2UL) /*!< EPDISEN (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEPINTEN_STPFEN_Pos (3UL) /*!< STPFEN (Bit 3) */ +#define USBFS_DEVICE_DOEPINTEN_STPFEN_Msk (0x8UL) /*!< STPFEN (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEPINTEN_EPRXFOVREN_Pos (4UL) /*!< EPRXFOVREN (Bit 4) */ +#define USBFS_DEVICE_DOEPINTEN_EPRXFOVREN_Msk (0x10UL) /*!< EPRXFOVREN (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEPINTEN_BTBSTPEN_Pos (6UL) /*!< BTBSTPEN (Bit 6) */ +#define USBFS_DEVICE_DOEPINTEN_BTBSTPEN_Msk (0x40UL) /*!< BTBSTPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== DAEPINT ======================================================== */ +#define USBFS_DEVICE_DAEPINT_IEPITB_Pos (0UL) /*!< IEPITB (Bit 0) */ +#define USBFS_DEVICE_DAEPINT_IEPITB_Msk (0xfUL) /*!< IEPITB (Bitfield-Mask: 0x0f) */ +#define USBFS_DEVICE_DAEPINT_OEPITB_Pos (16UL) /*!< OEPITB (Bit 16) */ +#define USBFS_DEVICE_DAEPINT_OEPITB_Msk (0xf0000UL) /*!< OEPITB (Bitfield-Mask: 0x0f) */ +/* ======================================================= DAEPINTEN ======================================================= */ +#define USBFS_DEVICE_DAEPINTEN_IEPIE_Pos (0UL) /*!< IEPIE (Bit 0) */ +#define USBFS_DEVICE_DAEPINTEN_IEPIE_Msk (0xfUL) /*!< IEPIE (Bitfield-Mask: 0x0f) */ +#define USBFS_DEVICE_DAEPINTEN_OEPIE_Pos (16UL) /*!< OEPIE (Bit 16) */ +#define USBFS_DEVICE_DAEPINTEN_OEPIE_Msk (0xf0000UL) /*!< OEPIE (Bitfield-Mask: 0x0f) */ +/* ======================================================== DVBUSDT ======================================================== */ +#define USBFS_DEVICE_DVBUSDT_DVBUSDT_Pos (0UL) /*!< DVBUSDT (Bit 0) */ +#define USBFS_DEVICE_DVBUSDT_DVBUSDT_Msk (0xffffUL) /*!< DVBUSDT (Bitfield-Mask: 0xffff) */ +/* ======================================================== DVBUSPT ======================================================== */ +#define USBFS_DEVICE_DVBUSPT_DVBUSPT_Pos (0UL) /*!< DVBUSPT (Bit 0) */ +#define USBFS_DEVICE_DVBUSPT_DVBUSPT_Msk (0xfffUL) /*!< DVBUSPT (Bitfield-Mask: 0xfff) */ +/* ====================================================== DIEPFEINTEN ====================================================== */ +#define USBFS_DEVICE_DIEPFEINTEN_IEPTXFEIE_Pos (0UL) /*!< IEPTXFEIE (Bit 0) */ +#define USBFS_DEVICE_DIEPFEINTEN_IEPTXFEIE_Msk (0xfUL) /*!< IEPTXFEIE (Bitfield-Mask: 0x0f) */ +/* ======================================================= DIEP0CTL ======================================================== */ +#define USBFS_DEVICE_DIEP0CTL_MPL_Pos (0UL) /*!< MPL (Bit 0) */ +#define USBFS_DEVICE_DIEP0CTL_MPL_Msk (0x3UL) /*!< MPL (Bitfield-Mask: 0x03) */ +#define USBFS_DEVICE_DIEP0CTL_EPACT_Pos (15UL) /*!< EPACT (Bit 15) */ +#define USBFS_DEVICE_DIEP0CTL_EPACT_Msk (0x8000UL) /*!< EPACT (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP0CTL_NAKS_Pos (17UL) /*!< NAKS (Bit 17) */ +#define USBFS_DEVICE_DIEP0CTL_NAKS_Msk (0x20000UL) /*!< NAKS (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP0CTL_EPTYPE_Pos (18UL) /*!< EPTYPE (Bit 18) */ +#define USBFS_DEVICE_DIEP0CTL_EPTYPE_Msk (0xc0000UL) /*!< EPTYPE (Bitfield-Mask: 0x03) */ +#define USBFS_DEVICE_DIEP0CTL_STALL_Pos (21UL) /*!< STALL (Bit 21) */ +#define USBFS_DEVICE_DIEP0CTL_STALL_Msk (0x200000UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP0CTL_TXFNUM_Pos (22UL) /*!< TXFNUM (Bit 22) */ +#define USBFS_DEVICE_DIEP0CTL_TXFNUM_Msk (0x3c00000UL) /*!< TXFNUM (Bitfield-Mask: 0x0f) */ +#define USBFS_DEVICE_DIEP0CTL_CNAK_Pos (26UL) /*!< CNAK (Bit 26) */ +#define USBFS_DEVICE_DIEP0CTL_CNAK_Msk (0x4000000UL) /*!< CNAK (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP0CTL_SNAK_Pos (27UL) /*!< SNAK (Bit 27) */ +#define USBFS_DEVICE_DIEP0CTL_SNAK_Msk (0x8000000UL) /*!< SNAK (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP0CTL_EPD_Pos (30UL) /*!< EPD (Bit 30) */ +#define USBFS_DEVICE_DIEP0CTL_EPD_Msk (0x40000000UL) /*!< EPD (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP0CTL_EPEN_Pos (31UL) /*!< EPEN (Bit 31) */ +#define USBFS_DEVICE_DIEP0CTL_EPEN_Msk (0x80000000UL) /*!< EPEN (Bitfield-Mask: 0x01) */ +/* ======================================================= DIEP1CTL ======================================================== */ +#define USBFS_DEVICE_DIEP1CTL_EPEN_Pos (31UL) /*!< EPEN (Bit 31) */ +#define USBFS_DEVICE_DIEP1CTL_EPEN_Msk (0x80000000UL) /*!< EPEN (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP1CTL_EPD_Pos (30UL) /*!< EPD (Bit 30) */ +#define USBFS_DEVICE_DIEP1CTL_EPD_Msk (0x40000000UL) /*!< EPD (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP1CTL_SD1PID_SODDFRM_Pos (29UL) /*!< SD1PID_SODDFRM (Bit 29) */ +#define USBFS_DEVICE_DIEP1CTL_SD1PID_SODDFRM_Msk (0x20000000UL) /*!< SD1PID_SODDFRM (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP1CTL_SD0PID_SEVENFRM_Pos (28UL) /*!< SD0PID_SEVENFRM (Bit 28) */ +#define USBFS_DEVICE_DIEP1CTL_SD0PID_SEVENFRM_Msk (0x10000000UL) /*!< SD0PID_SEVENFRM (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP1CTL_SNAK_Pos (27UL) /*!< SNAK (Bit 27) */ +#define USBFS_DEVICE_DIEP1CTL_SNAK_Msk (0x8000000UL) /*!< SNAK (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP1CTL_CNAK_Pos (26UL) /*!< CNAK (Bit 26) */ +#define USBFS_DEVICE_DIEP1CTL_CNAK_Msk (0x4000000UL) /*!< CNAK (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP1CTL_TXFNUM_Pos (22UL) /*!< TXFNUM (Bit 22) */ +#define USBFS_DEVICE_DIEP1CTL_TXFNUM_Msk (0x3c00000UL) /*!< TXFNUM (Bitfield-Mask: 0x0f) */ +#define USBFS_DEVICE_DIEP1CTL_STALL_Pos (21UL) /*!< STALL (Bit 21) */ +#define USBFS_DEVICE_DIEP1CTL_STALL_Msk (0x200000UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP1CTL_EPTYPE_Pos (18UL) /*!< EPTYPE (Bit 18) */ +#define USBFS_DEVICE_DIEP1CTL_EPTYPE_Msk (0xc0000UL) /*!< EPTYPE (Bitfield-Mask: 0x03) */ +#define USBFS_DEVICE_DIEP1CTL_NAKS_Pos (17UL) /*!< NAKS (Bit 17) */ +#define USBFS_DEVICE_DIEP1CTL_NAKS_Msk (0x20000UL) /*!< NAKS (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP1CTL_EOFRM_DPID_Pos (16UL) /*!< EOFRM_DPID (Bit 16) */ +#define USBFS_DEVICE_DIEP1CTL_EOFRM_DPID_Msk (0x10000UL) /*!< EOFRM_DPID (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP1CTL_EPACT_Pos (15UL) /*!< EPACT (Bit 15) */ +#define USBFS_DEVICE_DIEP1CTL_EPACT_Msk (0x8000UL) /*!< EPACT (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP1CTL_MPL_Pos (0UL) /*!< MPL (Bit 0) */ +#define USBFS_DEVICE_DIEP1CTL_MPL_Msk (0x7ffUL) /*!< MPL (Bitfield-Mask: 0x7ff) */ +/* ======================================================= DIEP2CTL ======================================================== */ +#define USBFS_DEVICE_DIEP2CTL_EPEN_Pos (31UL) /*!< EPEN (Bit 31) */ +#define USBFS_DEVICE_DIEP2CTL_EPEN_Msk (0x80000000UL) /*!< EPEN (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP2CTL_EPD_Pos (30UL) /*!< EPD (Bit 30) */ +#define USBFS_DEVICE_DIEP2CTL_EPD_Msk (0x40000000UL) /*!< EPD (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP2CTL_SD1PID_SODDFRM_Pos (29UL) /*!< SD1PID_SODDFRM (Bit 29) */ +#define USBFS_DEVICE_DIEP2CTL_SD1PID_SODDFRM_Msk (0x20000000UL) /*!< SD1PID_SODDFRM (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP2CTL_SD0PID_SEVENFRM_Pos (28UL) /*!< SD0PID_SEVENFRM (Bit 28) */ +#define USBFS_DEVICE_DIEP2CTL_SD0PID_SEVENFRM_Msk (0x10000000UL) /*!< SD0PID_SEVENFRM (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP2CTL_SNAK_Pos (27UL) /*!< SNAK (Bit 27) */ +#define USBFS_DEVICE_DIEP2CTL_SNAK_Msk (0x8000000UL) /*!< SNAK (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP2CTL_CNAK_Pos (26UL) /*!< CNAK (Bit 26) */ +#define USBFS_DEVICE_DIEP2CTL_CNAK_Msk (0x4000000UL) /*!< CNAK (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP2CTL_TXFNUM_Pos (22UL) /*!< TXFNUM (Bit 22) */ +#define USBFS_DEVICE_DIEP2CTL_TXFNUM_Msk (0x3c00000UL) /*!< TXFNUM (Bitfield-Mask: 0x0f) */ +#define USBFS_DEVICE_DIEP2CTL_STALL_Pos (21UL) /*!< STALL (Bit 21) */ +#define USBFS_DEVICE_DIEP2CTL_STALL_Msk (0x200000UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP2CTL_EPTYPE_Pos (18UL) /*!< EPTYPE (Bit 18) */ +#define USBFS_DEVICE_DIEP2CTL_EPTYPE_Msk (0xc0000UL) /*!< EPTYPE (Bitfield-Mask: 0x03) */ +#define USBFS_DEVICE_DIEP2CTL_NAKS_Pos (17UL) /*!< NAKS (Bit 17) */ +#define USBFS_DEVICE_DIEP2CTL_NAKS_Msk (0x20000UL) /*!< NAKS (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP2CTL_EOFRM_DPID_Pos (16UL) /*!< EOFRM_DPID (Bit 16) */ +#define USBFS_DEVICE_DIEP2CTL_EOFRM_DPID_Msk (0x10000UL) /*!< EOFRM_DPID (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP2CTL_EPACT_Pos (15UL) /*!< EPACT (Bit 15) */ +#define USBFS_DEVICE_DIEP2CTL_EPACT_Msk (0x8000UL) /*!< EPACT (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP2CTL_MPL_Pos (0UL) /*!< MPL (Bit 0) */ +#define USBFS_DEVICE_DIEP2CTL_MPL_Msk (0x7ffUL) /*!< MPL (Bitfield-Mask: 0x7ff) */ +/* ======================================================= DIEP3CTL ======================================================== */ +#define USBFS_DEVICE_DIEP3CTL_EPEN_Pos (31UL) /*!< EPEN (Bit 31) */ +#define USBFS_DEVICE_DIEP3CTL_EPEN_Msk (0x80000000UL) /*!< EPEN (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP3CTL_EPD_Pos (30UL) /*!< EPD (Bit 30) */ +#define USBFS_DEVICE_DIEP3CTL_EPD_Msk (0x40000000UL) /*!< EPD (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP3CTL_SD1PID_SODDFRM_Pos (29UL) /*!< SD1PID_SODDFRM (Bit 29) */ +#define USBFS_DEVICE_DIEP3CTL_SD1PID_SODDFRM_Msk (0x20000000UL) /*!< SD1PID_SODDFRM (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP3CTL_SD0PID_SEVENFRM_Pos (28UL) /*!< SD0PID_SEVENFRM (Bit 28) */ +#define USBFS_DEVICE_DIEP3CTL_SD0PID_SEVENFRM_Msk (0x10000000UL) /*!< SD0PID_SEVENFRM (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP3CTL_SNAK_Pos (27UL) /*!< SNAK (Bit 27) */ +#define USBFS_DEVICE_DIEP3CTL_SNAK_Msk (0x8000000UL) /*!< SNAK (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP3CTL_CNAK_Pos (26UL) /*!< CNAK (Bit 26) */ +#define USBFS_DEVICE_DIEP3CTL_CNAK_Msk (0x4000000UL) /*!< CNAK (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP3CTL_TXFNUM_Pos (22UL) /*!< TXFNUM (Bit 22) */ +#define USBFS_DEVICE_DIEP3CTL_TXFNUM_Msk (0x3c00000UL) /*!< TXFNUM (Bitfield-Mask: 0x0f) */ +#define USBFS_DEVICE_DIEP3CTL_STALL_Pos (21UL) /*!< STALL (Bit 21) */ +#define USBFS_DEVICE_DIEP3CTL_STALL_Msk (0x200000UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP3CTL_EPTYPE_Pos (18UL) /*!< EPTYPE (Bit 18) */ +#define USBFS_DEVICE_DIEP3CTL_EPTYPE_Msk (0xc0000UL) /*!< EPTYPE (Bitfield-Mask: 0x03) */ +#define USBFS_DEVICE_DIEP3CTL_NAKS_Pos (17UL) /*!< NAKS (Bit 17) */ +#define USBFS_DEVICE_DIEP3CTL_NAKS_Msk (0x20000UL) /*!< NAKS (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP3CTL_EOFRM_DPID_Pos (16UL) /*!< EOFRM_DPID (Bit 16) */ +#define USBFS_DEVICE_DIEP3CTL_EOFRM_DPID_Msk (0x10000UL) /*!< EOFRM_DPID (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP3CTL_EPACT_Pos (15UL) /*!< EPACT (Bit 15) */ +#define USBFS_DEVICE_DIEP3CTL_EPACT_Msk (0x8000UL) /*!< EPACT (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP3CTL_MPL_Pos (0UL) /*!< MPL (Bit 0) */ +#define USBFS_DEVICE_DIEP3CTL_MPL_Msk (0x7ffUL) /*!< MPL (Bitfield-Mask: 0x7ff) */ +/* ======================================================= DOEP0CTL ======================================================== */ +#define USBFS_DEVICE_DOEP0CTL_EPEN_Pos (31UL) /*!< EPEN (Bit 31) */ +#define USBFS_DEVICE_DOEP0CTL_EPEN_Msk (0x80000000UL) /*!< EPEN (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP0CTL_EPD_Pos (30UL) /*!< EPD (Bit 30) */ +#define USBFS_DEVICE_DOEP0CTL_EPD_Msk (0x40000000UL) /*!< EPD (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP0CTL_SNAK_Pos (27UL) /*!< SNAK (Bit 27) */ +#define USBFS_DEVICE_DOEP0CTL_SNAK_Msk (0x8000000UL) /*!< SNAK (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP0CTL_CNAK_Pos (26UL) /*!< CNAK (Bit 26) */ +#define USBFS_DEVICE_DOEP0CTL_CNAK_Msk (0x4000000UL) /*!< CNAK (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP0CTL_STALL_Pos (21UL) /*!< STALL (Bit 21) */ +#define USBFS_DEVICE_DOEP0CTL_STALL_Msk (0x200000UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP0CTL_SNOOP_Pos (20UL) /*!< SNOOP (Bit 20) */ +#define USBFS_DEVICE_DOEP0CTL_SNOOP_Msk (0x100000UL) /*!< SNOOP (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP0CTL_EPTYPE_Pos (18UL) /*!< EPTYPE (Bit 18) */ +#define USBFS_DEVICE_DOEP0CTL_EPTYPE_Msk (0xc0000UL) /*!< EPTYPE (Bitfield-Mask: 0x03) */ +#define USBFS_DEVICE_DOEP0CTL_NAKS_Pos (17UL) /*!< NAKS (Bit 17) */ +#define USBFS_DEVICE_DOEP0CTL_NAKS_Msk (0x20000UL) /*!< NAKS (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP0CTL_EPACT_Pos (15UL) /*!< EPACT (Bit 15) */ +#define USBFS_DEVICE_DOEP0CTL_EPACT_Msk (0x8000UL) /*!< EPACT (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP0CTL_MPL_Pos (0UL) /*!< MPL (Bit 0) */ +#define USBFS_DEVICE_DOEP0CTL_MPL_Msk (0x3UL) /*!< MPL (Bitfield-Mask: 0x03) */ +/* ======================================================= DOEP1CTL ======================================================== */ +#define USBFS_DEVICE_DOEP1CTL_EPEN_Pos (31UL) /*!< EPEN (Bit 31) */ +#define USBFS_DEVICE_DOEP1CTL_EPEN_Msk (0x80000000UL) /*!< EPEN (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP1CTL_EPD_Pos (30UL) /*!< EPD (Bit 30) */ +#define USBFS_DEVICE_DOEP1CTL_EPD_Msk (0x40000000UL) /*!< EPD (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP1CTL_SD1PID_SODDFRM_Pos (29UL) /*!< SD1PID_SODDFRM (Bit 29) */ +#define USBFS_DEVICE_DOEP1CTL_SD1PID_SODDFRM_Msk (0x20000000UL) /*!< SD1PID_SODDFRM (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP1CTL_SD0PID_SEVENFRM_Pos (28UL) /*!< SD0PID_SEVENFRM (Bit 28) */ +#define USBFS_DEVICE_DOEP1CTL_SD0PID_SEVENFRM_Msk (0x10000000UL) /*!< SD0PID_SEVENFRM (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP1CTL_SNAK_Pos (27UL) /*!< SNAK (Bit 27) */ +#define USBFS_DEVICE_DOEP1CTL_SNAK_Msk (0x8000000UL) /*!< SNAK (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP1CTL_CNAK_Pos (26UL) /*!< CNAK (Bit 26) */ +#define USBFS_DEVICE_DOEP1CTL_CNAK_Msk (0x4000000UL) /*!< CNAK (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP1CTL_STALL_Pos (21UL) /*!< STALL (Bit 21) */ +#define USBFS_DEVICE_DOEP1CTL_STALL_Msk (0x200000UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP1CTL_SNOOP_Pos (20UL) /*!< SNOOP (Bit 20) */ +#define USBFS_DEVICE_DOEP1CTL_SNOOP_Msk (0x100000UL) /*!< SNOOP (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP1CTL_EPTYPE_Pos (18UL) /*!< EPTYPE (Bit 18) */ +#define USBFS_DEVICE_DOEP1CTL_EPTYPE_Msk (0xc0000UL) /*!< EPTYPE (Bitfield-Mask: 0x03) */ +#define USBFS_DEVICE_DOEP1CTL_NAKS_Pos (17UL) /*!< NAKS (Bit 17) */ +#define USBFS_DEVICE_DOEP1CTL_NAKS_Msk (0x20000UL) /*!< NAKS (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP1CTL_EOFRM_DPID_Pos (16UL) /*!< EOFRM_DPID (Bit 16) */ +#define USBFS_DEVICE_DOEP1CTL_EOFRM_DPID_Msk (0x10000UL) /*!< EOFRM_DPID (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP1CTL_EPACT_Pos (15UL) /*!< EPACT (Bit 15) */ +#define USBFS_DEVICE_DOEP1CTL_EPACT_Msk (0x8000UL) /*!< EPACT (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP1CTL_MPL_Pos (0UL) /*!< MPL (Bit 0) */ +#define USBFS_DEVICE_DOEP1CTL_MPL_Msk (0x7ffUL) /*!< MPL (Bitfield-Mask: 0x7ff) */ +/* ======================================================= DOEP2CTL ======================================================== */ +#define USBFS_DEVICE_DOEP2CTL_EPEN_Pos (31UL) /*!< EPEN (Bit 31) */ +#define USBFS_DEVICE_DOEP2CTL_EPEN_Msk (0x80000000UL) /*!< EPEN (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP2CTL_EPD_Pos (30UL) /*!< EPD (Bit 30) */ +#define USBFS_DEVICE_DOEP2CTL_EPD_Msk (0x40000000UL) /*!< EPD (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP2CTL_SD1PID_SODDFRM_Pos (29UL) /*!< SD1PID_SODDFRM (Bit 29) */ +#define USBFS_DEVICE_DOEP2CTL_SD1PID_SODDFRM_Msk (0x20000000UL) /*!< SD1PID_SODDFRM (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP2CTL_SD0PID_SEVENFRM_Pos (28UL) /*!< SD0PID_SEVENFRM (Bit 28) */ +#define USBFS_DEVICE_DOEP2CTL_SD0PID_SEVENFRM_Msk (0x10000000UL) /*!< SD0PID_SEVENFRM (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP2CTL_SNAK_Pos (27UL) /*!< SNAK (Bit 27) */ +#define USBFS_DEVICE_DOEP2CTL_SNAK_Msk (0x8000000UL) /*!< SNAK (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP2CTL_CNAK_Pos (26UL) /*!< CNAK (Bit 26) */ +#define USBFS_DEVICE_DOEP2CTL_CNAK_Msk (0x4000000UL) /*!< CNAK (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP2CTL_STALL_Pos (21UL) /*!< STALL (Bit 21) */ +#define USBFS_DEVICE_DOEP2CTL_STALL_Msk (0x200000UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP2CTL_SNOOP_Pos (20UL) /*!< SNOOP (Bit 20) */ +#define USBFS_DEVICE_DOEP2CTL_SNOOP_Msk (0x100000UL) /*!< SNOOP (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP2CTL_EPTYPE_Pos (18UL) /*!< EPTYPE (Bit 18) */ +#define USBFS_DEVICE_DOEP2CTL_EPTYPE_Msk (0xc0000UL) /*!< EPTYPE (Bitfield-Mask: 0x03) */ +#define USBFS_DEVICE_DOEP2CTL_NAKS_Pos (17UL) /*!< NAKS (Bit 17) */ +#define USBFS_DEVICE_DOEP2CTL_NAKS_Msk (0x20000UL) /*!< NAKS (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP2CTL_EOFRM_DPID_Pos (16UL) /*!< EOFRM_DPID (Bit 16) */ +#define USBFS_DEVICE_DOEP2CTL_EOFRM_DPID_Msk (0x10000UL) /*!< EOFRM_DPID (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP2CTL_EPACT_Pos (15UL) /*!< EPACT (Bit 15) */ +#define USBFS_DEVICE_DOEP2CTL_EPACT_Msk (0x8000UL) /*!< EPACT (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP2CTL_MPL_Pos (0UL) /*!< MPL (Bit 0) */ +#define USBFS_DEVICE_DOEP2CTL_MPL_Msk (0x7ffUL) /*!< MPL (Bitfield-Mask: 0x7ff) */ +/* ======================================================= DOEP3CTL ======================================================== */ +#define USBFS_DEVICE_DOEP3CTL_EPEN_Pos (31UL) /*!< EPEN (Bit 31) */ +#define USBFS_DEVICE_DOEP3CTL_EPEN_Msk (0x80000000UL) /*!< EPEN (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP3CTL_EPD_Pos (30UL) /*!< EPD (Bit 30) */ +#define USBFS_DEVICE_DOEP3CTL_EPD_Msk (0x40000000UL) /*!< EPD (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP3CTL_SD1PID_SODDFRM_Pos (29UL) /*!< SD1PID_SODDFRM (Bit 29) */ +#define USBFS_DEVICE_DOEP3CTL_SD1PID_SODDFRM_Msk (0x20000000UL) /*!< SD1PID_SODDFRM (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP3CTL_SD0PID_SEVENFRM_Pos (28UL) /*!< SD0PID_SEVENFRM (Bit 28) */ +#define USBFS_DEVICE_DOEP3CTL_SD0PID_SEVENFRM_Msk (0x10000000UL) /*!< SD0PID_SEVENFRM (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP3CTL_SNAK_Pos (27UL) /*!< SNAK (Bit 27) */ +#define USBFS_DEVICE_DOEP3CTL_SNAK_Msk (0x8000000UL) /*!< SNAK (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP3CTL_CNAK_Pos (26UL) /*!< CNAK (Bit 26) */ +#define USBFS_DEVICE_DOEP3CTL_CNAK_Msk (0x4000000UL) /*!< CNAK (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP3CTL_STALL_Pos (21UL) /*!< STALL (Bit 21) */ +#define USBFS_DEVICE_DOEP3CTL_STALL_Msk (0x200000UL) /*!< STALL (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP3CTL_SNOOP_Pos (20UL) /*!< SNOOP (Bit 20) */ +#define USBFS_DEVICE_DOEP3CTL_SNOOP_Msk (0x100000UL) /*!< SNOOP (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP3CTL_EPTYPE_Pos (18UL) /*!< EPTYPE (Bit 18) */ +#define USBFS_DEVICE_DOEP3CTL_EPTYPE_Msk (0xc0000UL) /*!< EPTYPE (Bitfield-Mask: 0x03) */ +#define USBFS_DEVICE_DOEP3CTL_NAKS_Pos (17UL) /*!< NAKS (Bit 17) */ +#define USBFS_DEVICE_DOEP3CTL_NAKS_Msk (0x20000UL) /*!< NAKS (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP3CTL_EOFRM_DPID_Pos (16UL) /*!< EOFRM_DPID (Bit 16) */ +#define USBFS_DEVICE_DOEP3CTL_EOFRM_DPID_Msk (0x10000UL) /*!< EOFRM_DPID (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP3CTL_EPACT_Pos (15UL) /*!< EPACT (Bit 15) */ +#define USBFS_DEVICE_DOEP3CTL_EPACT_Msk (0x8000UL) /*!< EPACT (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP3CTL_MPL_Pos (0UL) /*!< MPL (Bit 0) */ +#define USBFS_DEVICE_DOEP3CTL_MPL_Msk (0x7ffUL) /*!< MPL (Bitfield-Mask: 0x7ff) */ +/* ======================================================= DIEP0INTF ======================================================= */ +#define USBFS_DEVICE_DIEP0INTF_TXFE_Pos (7UL) /*!< TXFE (Bit 7) */ +#define USBFS_DEVICE_DIEP0INTF_TXFE_Msk (0x80UL) /*!< TXFE (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP0INTF_IEPNE_Pos (6UL) /*!< IEPNE (Bit 6) */ +#define USBFS_DEVICE_DIEP0INTF_IEPNE_Msk (0x40UL) /*!< IEPNE (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP0INTF_EPTXFUD_Pos (4UL) /*!< EPTXFUD (Bit 4) */ +#define USBFS_DEVICE_DIEP0INTF_EPTXFUD_Msk (0x10UL) /*!< EPTXFUD (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP0INTF_CITO_Pos (3UL) /*!< CITO (Bit 3) */ +#define USBFS_DEVICE_DIEP0INTF_CITO_Msk (0x8UL) /*!< CITO (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP0INTF_EPDIS_Pos (1UL) /*!< EPDIS (Bit 1) */ +#define USBFS_DEVICE_DIEP0INTF_EPDIS_Msk (0x2UL) /*!< EPDIS (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP0INTF_TF_Pos (0UL) /*!< TF (Bit 0) */ +#define USBFS_DEVICE_DIEP0INTF_TF_Msk (0x1UL) /*!< TF (Bitfield-Mask: 0x01) */ +/* ======================================================= DIEP1INTF ======================================================= */ +#define USBFS_DEVICE_DIEP1INTF_TXFE_Pos (7UL) /*!< TXFE (Bit 7) */ +#define USBFS_DEVICE_DIEP1INTF_TXFE_Msk (0x80UL) /*!< TXFE (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP1INTF_IEPNE_Pos (6UL) /*!< IEPNE (Bit 6) */ +#define USBFS_DEVICE_DIEP1INTF_IEPNE_Msk (0x40UL) /*!< IEPNE (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP1INTF_EPTXFUD_Pos (4UL) /*!< EPTXFUD (Bit 4) */ +#define USBFS_DEVICE_DIEP1INTF_EPTXFUD_Msk (0x10UL) /*!< EPTXFUD (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP1INTF_CITO_Pos (3UL) /*!< CITO (Bit 3) */ +#define USBFS_DEVICE_DIEP1INTF_CITO_Msk (0x8UL) /*!< CITO (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP1INTF_EPDIS_Pos (1UL) /*!< EPDIS (Bit 1) */ +#define USBFS_DEVICE_DIEP1INTF_EPDIS_Msk (0x2UL) /*!< EPDIS (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP1INTF_TF_Pos (0UL) /*!< TF (Bit 0) */ +#define USBFS_DEVICE_DIEP1INTF_TF_Msk (0x1UL) /*!< TF (Bitfield-Mask: 0x01) */ +/* ======================================================= DIEP2INTF ======================================================= */ +#define USBFS_DEVICE_DIEP2INTF_TXFE_Pos (7UL) /*!< TXFE (Bit 7) */ +#define USBFS_DEVICE_DIEP2INTF_TXFE_Msk (0x80UL) /*!< TXFE (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP2INTF_IEPNE_Pos (6UL) /*!< IEPNE (Bit 6) */ +#define USBFS_DEVICE_DIEP2INTF_IEPNE_Msk (0x40UL) /*!< IEPNE (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP2INTF_EPTXFUD_Pos (4UL) /*!< EPTXFUD (Bit 4) */ +#define USBFS_DEVICE_DIEP2INTF_EPTXFUD_Msk (0x10UL) /*!< EPTXFUD (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP2INTF_CITO_Pos (3UL) /*!< CITO (Bit 3) */ +#define USBFS_DEVICE_DIEP2INTF_CITO_Msk (0x8UL) /*!< CITO (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP2INTF_EPDIS_Pos (1UL) /*!< EPDIS (Bit 1) */ +#define USBFS_DEVICE_DIEP2INTF_EPDIS_Msk (0x2UL) /*!< EPDIS (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP2INTF_TF_Pos (0UL) /*!< TF (Bit 0) */ +#define USBFS_DEVICE_DIEP2INTF_TF_Msk (0x1UL) /*!< TF (Bitfield-Mask: 0x01) */ +/* ======================================================= DIEP3INTF ======================================================= */ +#define USBFS_DEVICE_DIEP3INTF_TXFE_Pos (7UL) /*!< TXFE (Bit 7) */ +#define USBFS_DEVICE_DIEP3INTF_TXFE_Msk (0x80UL) /*!< TXFE (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP3INTF_IEPNE_Pos (6UL) /*!< IEPNE (Bit 6) */ +#define USBFS_DEVICE_DIEP3INTF_IEPNE_Msk (0x40UL) /*!< IEPNE (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP3INTF_EPTXFUD_Pos (4UL) /*!< EPTXFUD (Bit 4) */ +#define USBFS_DEVICE_DIEP3INTF_EPTXFUD_Msk (0x10UL) /*!< EPTXFUD (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP3INTF_CITO_Pos (3UL) /*!< CITO (Bit 3) */ +#define USBFS_DEVICE_DIEP3INTF_CITO_Msk (0x8UL) /*!< CITO (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP3INTF_EPDIS_Pos (1UL) /*!< EPDIS (Bit 1) */ +#define USBFS_DEVICE_DIEP3INTF_EPDIS_Msk (0x2UL) /*!< EPDIS (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DIEP3INTF_TF_Pos (0UL) /*!< TF (Bit 0) */ +#define USBFS_DEVICE_DIEP3INTF_TF_Msk (0x1UL) /*!< TF (Bitfield-Mask: 0x01) */ +/* ======================================================= DOEP0INTF ======================================================= */ +#define USBFS_DEVICE_DOEP0INTF_BTBSTP_Pos (6UL) /*!< BTBSTP (Bit 6) */ +#define USBFS_DEVICE_DOEP0INTF_BTBSTP_Msk (0x40UL) /*!< BTBSTP (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP0INTF_EPRXFOVR_Pos (4UL) /*!< EPRXFOVR (Bit 4) */ +#define USBFS_DEVICE_DOEP0INTF_EPRXFOVR_Msk (0x10UL) /*!< EPRXFOVR (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP0INTF_STPF_Pos (3UL) /*!< STPF (Bit 3) */ +#define USBFS_DEVICE_DOEP0INTF_STPF_Msk (0x8UL) /*!< STPF (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP0INTF_EPDIS_Pos (1UL) /*!< EPDIS (Bit 1) */ +#define USBFS_DEVICE_DOEP0INTF_EPDIS_Msk (0x2UL) /*!< EPDIS (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP0INTF_TF_Pos (0UL) /*!< TF (Bit 0) */ +#define USBFS_DEVICE_DOEP0INTF_TF_Msk (0x1UL) /*!< TF (Bitfield-Mask: 0x01) */ +/* ======================================================= DOEP1INTF ======================================================= */ +#define USBFS_DEVICE_DOEP1INTF_BTBSTP_Pos (6UL) /*!< BTBSTP (Bit 6) */ +#define USBFS_DEVICE_DOEP1INTF_BTBSTP_Msk (0x40UL) /*!< BTBSTP (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP1INTF_EPRXFOVR_Pos (4UL) /*!< EPRXFOVR (Bit 4) */ +#define USBFS_DEVICE_DOEP1INTF_EPRXFOVR_Msk (0x10UL) /*!< EPRXFOVR (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP1INTF_STPF_Pos (3UL) /*!< STPF (Bit 3) */ +#define USBFS_DEVICE_DOEP1INTF_STPF_Msk (0x8UL) /*!< STPF (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP1INTF_EPDIS_Pos (1UL) /*!< EPDIS (Bit 1) */ +#define USBFS_DEVICE_DOEP1INTF_EPDIS_Msk (0x2UL) /*!< EPDIS (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP1INTF_TF_Pos (0UL) /*!< TF (Bit 0) */ +#define USBFS_DEVICE_DOEP1INTF_TF_Msk (0x1UL) /*!< TF (Bitfield-Mask: 0x01) */ +/* ======================================================= DOEP2INTF ======================================================= */ +#define USBFS_DEVICE_DOEP2INTF_BTBSTP_Pos (6UL) /*!< BTBSTP (Bit 6) */ +#define USBFS_DEVICE_DOEP2INTF_BTBSTP_Msk (0x40UL) /*!< BTBSTP (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP2INTF_EPRXFOVR_Pos (4UL) /*!< EPRXFOVR (Bit 4) */ +#define USBFS_DEVICE_DOEP2INTF_EPRXFOVR_Msk (0x10UL) /*!< EPRXFOVR (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP2INTF_STPF_Pos (3UL) /*!< STPF (Bit 3) */ +#define USBFS_DEVICE_DOEP2INTF_STPF_Msk (0x8UL) /*!< STPF (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP2INTF_EPDIS_Pos (1UL) /*!< EPDIS (Bit 1) */ +#define USBFS_DEVICE_DOEP2INTF_EPDIS_Msk (0x2UL) /*!< EPDIS (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP2INTF_TF_Pos (0UL) /*!< TF (Bit 0) */ +#define USBFS_DEVICE_DOEP2INTF_TF_Msk (0x1UL) /*!< TF (Bitfield-Mask: 0x01) */ +/* ======================================================= DOEP3INTF ======================================================= */ +#define USBFS_DEVICE_DOEP3INTF_BTBSTP_Pos (6UL) /*!< BTBSTP (Bit 6) */ +#define USBFS_DEVICE_DOEP3INTF_BTBSTP_Msk (0x40UL) /*!< BTBSTP (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP3INTF_EPRXFOVR_Pos (4UL) /*!< EPRXFOVR (Bit 4) */ +#define USBFS_DEVICE_DOEP3INTF_EPRXFOVR_Msk (0x10UL) /*!< EPRXFOVR (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP3INTF_STPF_Pos (3UL) /*!< STPF (Bit 3) */ +#define USBFS_DEVICE_DOEP3INTF_STPF_Msk (0x8UL) /*!< STPF (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP3INTF_EPDIS_Pos (1UL) /*!< EPDIS (Bit 1) */ +#define USBFS_DEVICE_DOEP3INTF_EPDIS_Msk (0x2UL) /*!< EPDIS (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP3INTF_TF_Pos (0UL) /*!< TF (Bit 0) */ +#define USBFS_DEVICE_DOEP3INTF_TF_Msk (0x1UL) /*!< TF (Bitfield-Mask: 0x01) */ +/* ======================================================= DIEP0LEN ======================================================== */ +#define USBFS_DEVICE_DIEP0LEN_PCNT_Pos (19UL) /*!< PCNT (Bit 19) */ +#define USBFS_DEVICE_DIEP0LEN_PCNT_Msk (0x180000UL) /*!< PCNT (Bitfield-Mask: 0x03) */ +#define USBFS_DEVICE_DIEP0LEN_TLEN_Pos (0UL) /*!< TLEN (Bit 0) */ +#define USBFS_DEVICE_DIEP0LEN_TLEN_Msk (0x7fUL) /*!< TLEN (Bitfield-Mask: 0x7f) */ +/* ======================================================= DOEP0LEN ======================================================== */ +#define USBFS_DEVICE_DOEP0LEN_STPCNT_Pos (29UL) /*!< STPCNT (Bit 29) */ +#define USBFS_DEVICE_DOEP0LEN_STPCNT_Msk (0x60000000UL) /*!< STPCNT (Bitfield-Mask: 0x03) */ +#define USBFS_DEVICE_DOEP0LEN_PCNT_Pos (19UL) /*!< PCNT (Bit 19) */ +#define USBFS_DEVICE_DOEP0LEN_PCNT_Msk (0x80000UL) /*!< PCNT (Bitfield-Mask: 0x01) */ +#define USBFS_DEVICE_DOEP0LEN_TLEN_Pos (0UL) /*!< TLEN (Bit 0) */ +#define USBFS_DEVICE_DOEP0LEN_TLEN_Msk (0x7fUL) /*!< TLEN (Bitfield-Mask: 0x7f) */ +/* ======================================================= DIEP1LEN ======================================================== */ +#define USBFS_DEVICE_DIEP1LEN_MCPF_Pos (29UL) /*!< MCPF (Bit 29) */ +#define USBFS_DEVICE_DIEP1LEN_MCPF_Msk (0x60000000UL) /*!< MCPF (Bitfield-Mask: 0x03) */ +#define USBFS_DEVICE_DIEP1LEN_PCNT_Pos (19UL) /*!< PCNT (Bit 19) */ +#define USBFS_DEVICE_DIEP1LEN_PCNT_Msk (0x1ff80000UL) /*!< PCNT (Bitfield-Mask: 0x3ff) */ +#define USBFS_DEVICE_DIEP1LEN_TLEN_Pos (0UL) /*!< TLEN (Bit 0) */ +#define USBFS_DEVICE_DIEP1LEN_TLEN_Msk (0x7ffffUL) /*!< TLEN (Bitfield-Mask: 0x7ffff) */ +/* ======================================================= DIEP2LEN ======================================================== */ +#define USBFS_DEVICE_DIEP2LEN_MCPF_Pos (29UL) /*!< MCPF (Bit 29) */ +#define USBFS_DEVICE_DIEP2LEN_MCPF_Msk (0x60000000UL) /*!< MCPF (Bitfield-Mask: 0x03) */ +#define USBFS_DEVICE_DIEP2LEN_PCNT_Pos (19UL) /*!< PCNT (Bit 19) */ +#define USBFS_DEVICE_DIEP2LEN_PCNT_Msk (0x1ff80000UL) /*!< PCNT (Bitfield-Mask: 0x3ff) */ +#define USBFS_DEVICE_DIEP2LEN_TLEN_Pos (0UL) /*!< TLEN (Bit 0) */ +#define USBFS_DEVICE_DIEP2LEN_TLEN_Msk (0x7ffffUL) /*!< TLEN (Bitfield-Mask: 0x7ffff) */ +/* ======================================================= DIEP3LEN ======================================================== */ +#define USBFS_DEVICE_DIEP3LEN_MCPF_Pos (29UL) /*!< MCPF (Bit 29) */ +#define USBFS_DEVICE_DIEP3LEN_MCPF_Msk (0x60000000UL) /*!< MCPF (Bitfield-Mask: 0x03) */ +#define USBFS_DEVICE_DIEP3LEN_PCNT_Pos (19UL) /*!< PCNT (Bit 19) */ +#define USBFS_DEVICE_DIEP3LEN_PCNT_Msk (0x1ff80000UL) /*!< PCNT (Bitfield-Mask: 0x3ff) */ +#define USBFS_DEVICE_DIEP3LEN_TLEN_Pos (0UL) /*!< TLEN (Bit 0) */ +#define USBFS_DEVICE_DIEP3LEN_TLEN_Msk (0x7ffffUL) /*!< TLEN (Bitfield-Mask: 0x7ffff) */ +/* ======================================================= DOEP1LEN ======================================================== */ +#define USBFS_DEVICE_DOEP1LEN_STPCNT_RXDPID_Pos (29UL) /*!< STPCNT_RXDPID (Bit 29) */ +#define USBFS_DEVICE_DOEP1LEN_STPCNT_RXDPID_Msk (0x60000000UL) /*!< STPCNT_RXDPID (Bitfield-Mask: 0x03) */ +#define USBFS_DEVICE_DOEP1LEN_PCNT_Pos (19UL) /*!< PCNT (Bit 19) */ +#define USBFS_DEVICE_DOEP1LEN_PCNT_Msk (0x1ff80000UL) /*!< PCNT (Bitfield-Mask: 0x3ff) */ +#define USBFS_DEVICE_DOEP1LEN_TLEN_Pos (0UL) /*!< TLEN (Bit 0) */ +#define USBFS_DEVICE_DOEP1LEN_TLEN_Msk (0x7ffffUL) /*!< TLEN (Bitfield-Mask: 0x7ffff) */ +/* ======================================================= DOEP2LEN ======================================================== */ +#define USBFS_DEVICE_DOEP2LEN_STPCNT_RXDPID_Pos (29UL) /*!< STPCNT_RXDPID (Bit 29) */ +#define USBFS_DEVICE_DOEP2LEN_STPCNT_RXDPID_Msk (0x60000000UL) /*!< STPCNT_RXDPID (Bitfield-Mask: 0x03) */ +#define USBFS_DEVICE_DOEP2LEN_PCNT_Pos (19UL) /*!< PCNT (Bit 19) */ +#define USBFS_DEVICE_DOEP2LEN_PCNT_Msk (0x1ff80000UL) /*!< PCNT (Bitfield-Mask: 0x3ff) */ +#define USBFS_DEVICE_DOEP2LEN_TLEN_Pos (0UL) /*!< TLEN (Bit 0) */ +#define USBFS_DEVICE_DOEP2LEN_TLEN_Msk (0x7ffffUL) /*!< TLEN (Bitfield-Mask: 0x7ffff) */ +/* ======================================================= DOEP3LEN ======================================================== */ +#define USBFS_DEVICE_DOEP3LEN_STPCNT_RXDPID_Pos (29UL) /*!< STPCNT_RXDPID (Bit 29) */ +#define USBFS_DEVICE_DOEP3LEN_STPCNT_RXDPID_Msk (0x60000000UL) /*!< STPCNT_RXDPID (Bitfield-Mask: 0x03) */ +#define USBFS_DEVICE_DOEP3LEN_PCNT_Pos (19UL) /*!< PCNT (Bit 19) */ +#define USBFS_DEVICE_DOEP3LEN_PCNT_Msk (0x1ff80000UL) /*!< PCNT (Bitfield-Mask: 0x3ff) */ +#define USBFS_DEVICE_DOEP3LEN_TLEN_Pos (0UL) /*!< TLEN (Bit 0) */ +#define USBFS_DEVICE_DOEP3LEN_TLEN_Msk (0x7ffffUL) /*!< TLEN (Bitfield-Mask: 0x7ffff) */ +/* ====================================================== DIEP0TFSTAT ====================================================== */ +#define USBFS_DEVICE_DIEP0TFSTAT_IEPTFS_Pos (0UL) /*!< IEPTFS (Bit 0) */ +#define USBFS_DEVICE_DIEP0TFSTAT_IEPTFS_Msk (0xffffUL) /*!< IEPTFS (Bitfield-Mask: 0xffff) */ +/* ====================================================== DIEP1TFSTAT ====================================================== */ +#define USBFS_DEVICE_DIEP1TFSTAT_IEPTFS_Pos (0UL) /*!< IEPTFS (Bit 0) */ +#define USBFS_DEVICE_DIEP1TFSTAT_IEPTFS_Msk (0xffffUL) /*!< IEPTFS (Bitfield-Mask: 0xffff) */ +/* ====================================================== DIEP2TFSTAT ====================================================== */ +#define USBFS_DEVICE_DIEP2TFSTAT_IEPTFS_Pos (0UL) /*!< IEPTFS (Bit 0) */ +#define USBFS_DEVICE_DIEP2TFSTAT_IEPTFS_Msk (0xffffUL) /*!< IEPTFS (Bitfield-Mask: 0xffff) */ +/* ====================================================== DIEP3TFSTAT ====================================================== */ +#define USBFS_DEVICE_DIEP3TFSTAT_IEPTFS_Pos (0UL) /*!< IEPTFS (Bit 0) */ +#define USBFS_DEVICE_DIEP3TFSTAT_IEPTFS_Msk (0xffffUL) /*!< IEPTFS (Bitfield-Mask: 0xffff) */ + + +/* =========================================================================================================================== */ +/* ================ USBFS_PWRCLK ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= PWRCLKCTL ======================================================= */ +#define USBFS_PWRCLK_PWRCLKCTL_SUCLK_Pos (0UL) /*!< SUCLK (Bit 0) */ +#define USBFS_PWRCLK_PWRCLKCTL_SUCLK_Msk (0x1UL) /*!< SUCLK (Bitfield-Mask: 0x01) */ +#define USBFS_PWRCLK_PWRCLKCTL_SHCLK_Pos (1UL) /*!< SHCLK (Bit 1) */ +#define USBFS_PWRCLK_PWRCLKCTL_SHCLK_Msk (0x2UL) /*!< SHCLK (Bitfield-Mask: 0x01) */ + + +/* =========================================================================================================================== */ +/* ================ WWDGT ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CTL ========================================================== */ +#define WWDGT_CTL_WDGTEN_Pos (7UL) /*!< WDGTEN (Bit 7) */ +#define WWDGT_CTL_WDGTEN_Msk (0x80UL) /*!< WDGTEN (Bitfield-Mask: 0x01) */ +#define WWDGT_CTL_CNT_Pos (0UL) /*!< CNT (Bit 0) */ +#define WWDGT_CTL_CNT_Msk (0x7fUL) /*!< CNT (Bitfield-Mask: 0x7f) */ +/* ========================================================== CFG ========================================================== */ +#define WWDGT_CFG_EWIE_Pos (9UL) /*!< EWIE (Bit 9) */ +#define WWDGT_CFG_EWIE_Msk (0x200UL) /*!< EWIE (Bitfield-Mask: 0x01) */ +#define WWDGT_CFG_PSC_Pos (7UL) /*!< PSC (Bit 7) */ +#define WWDGT_CFG_PSC_Msk (0x180UL) /*!< PSC (Bitfield-Mask: 0x03) */ +#define WWDGT_CFG_WIN_Pos (0UL) /*!< WIN (Bit 0) */ +#define WWDGT_CFG_WIN_Msk (0x7fUL) /*!< WIN (Bitfield-Mask: 0x7f) */ +/* ========================================================= STAT ========================================================== */ +#define WWDGT_STAT_EWIF_Pos (0UL) /*!< EWIF (Bit 0) */ +#define WWDGT_STAT_EWIF_Msk (0x1UL) /*!< EWIF (Bitfield-Mask: 0x01) */ + + +#ifdef __cplusplus +} +#endif + +#endif /* GD32VF103_H */ diff --git a/cpu/gd32v/include/vendor/gd32vf103_pmu.h b/cpu/gd32v/include/vendor/gd32vf103_pmu.h new file mode 100644 index 0000000000..bb36512ee1 --- /dev/null +++ b/cpu/gd32v/include/vendor/gd32vf103_pmu.h @@ -0,0 +1,125 @@ +/*! + \file gd32vf103_pmu.h + \brief definitions for the PMU + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_PMU_H +#define GD32VF103_PMU_H + +#include "gd32vf103.h" + +/* PMU definitions */ +#define PMU PMU_BASE /*!< PMU base address */ + +/* registers definitions */ +#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */ +#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */ + +/* bits definitions */ +/* PMU_CTL */ +#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ +#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ +#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ +#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ +#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ +#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ +#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ + +/* PMU_CS */ +#define PMU_CS_WUF BIT(0) /*!< wakeup flag */ +#define PMU_CS_STBF BIT(1) /*!< standby flag */ +#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ +#define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */ + +/* constants definitions */ +/* PMU low voltage detector threshold definitions */ +#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval) << 5)) +#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.2V */ +#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ +#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ +#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.5V */ +#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.6V */ +#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.7V */ +#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 2.8V */ +#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 2.9V */ + +/* PMU flag definitions */ +#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ +#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ +#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */ + +/* PMU ldo definitions */ +#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */ +#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ + +/* PMU flag reset definitions */ +#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */ +#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */ + +/* PMU command constants definitions */ +#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ +#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ + +/* function declarations */ +/* reset PMU registers */ +void pmu_deinit(void); + +/* select low voltage detector threshold */ +void pmu_lvd_select(uint32_t lvdt_n); +/* disable PMU lvd */ +void pmu_lvd_disable(void); + +/* set PMU mode */ +/* PMU work at sleep mode */ +void pmu_to_sleepmode(uint8_t sleepmodecmd); +/* PMU work at deepsleep mode */ +void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd); +/* PMU work at standby mode */ +void pmu_to_standbymode(uint8_t standbymodecmd); +/* enable PMU wakeup pin */ +void pmu_wakeup_pin_enable(void); +/* disable PMU wakeup pin */ +void pmu_wakeup_pin_disable(void); + +/* backup related functions */ +/* enable write access to the registers in backup domain */ +void pmu_backup_write_enable(void); +/* disable write access to the registers in backup domain */ +void pmu_backup_write_disable(void); + +/* flag functions */ +/* get flag state */ +FlagStatus pmu_flag_get(uint32_t flag); +/* clear flag bit */ +void pmu_flag_clear(uint32_t flag_reset); + +#endif /* GD32VF103_PMU_H */ diff --git a/cpu/gd32v/include/vendor/gd32vf103_rcu.h b/cpu/gd32v/include/vendor/gd32vf103_rcu.h new file mode 100644 index 0000000000..c20e1a094d --- /dev/null +++ b/cpu/gd32v/include/vendor/gd32vf103_rcu.h @@ -0,0 +1,720 @@ +/*! + \file gd32vf103_rcu.h + \brief definitions for the RCU + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_RCU_H +#define GD32VF103_RCU_H + +#include "gd32vf103.h" + +/* RCU definitions */ +#define RCU RCU_BASE + +/* registers definitions */ + +#define RCU_CTL REG32(RCU + 0x00U) /*!< control register */ +#define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */ +#define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */ +#define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */ +#define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */ +#define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB1 enable register */ +#define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */ +#define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */ +#define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */ +#define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */ +#define RCU_AHBRST REG32(RCU + 0x28U) /*!< AHB reset register */ +#define RCU_CFG1 REG32(RCU + 0x2CU) /*!< clock configuration register 1 */ +#define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */ + + +/* bits definitions */ +/* RCU_CTL */ +#define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ +#define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ +#define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ +#define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ +#define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ +#define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ +#define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ +#define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ +#define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ +#define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ +#define RCU_CTL_PLL1EN BIT(26) /*!< PLL1 enable */ +#define RCU_CTL_PLL1STB BIT(27) /*!< PLL1 clock stabilization flag */ +#define RCU_CTL_PLL2EN BIT(28) /*!< PLL2 enable */ +#define RCU_CTL_PLL2STB BIT(29) /*!< PLL2 clock stabilization flag */ + + +#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ +#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ +#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ +#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ +#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ +#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ +#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ +#define RCU_CFG0_PREDV0_LSB BIT(17) /*!< the LSB of PREDV0 division factor */ +#define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ +#define RCU_CFG0_USBFSPSC BITS(22,23) /*!< USBFS clock prescaler selection */ +#define RCU_CFG0_CKOUT0SEL BITS(24,27) /*!< CKOUT0 clock source selection */ +#define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ +#define RCU_CFG0_PLLMF_4 BIT(29) /*!< bit 4 of PLLMF */ + +/* RCU_INT */ +#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ +#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ +#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ +#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ +#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ +#define RCU_INT_PLL1STBIF BIT(5) /*!< PLL1 stabilization interrupt flag */ +#define RCU_INT_PLL2STBIF BIT(6) /*!< PLL2 stabilization interrupt flag */ +#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ +#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ +#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ +#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ +#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ +#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ +#define RCU_INT_PLL1STBIE BIT(13) /*!< PLL1 stabilization interrupt enable */ +#define RCU_INT_PLL2STBIE BIT(14) /*!< PLL2 stabilization interrupt enable */ +#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */ +#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */ +#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */ +#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */ +#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ +#define RCU_INT_PLL1STBIC BIT(21) /*!< PLL1 stabilization interrupt clear */ +#define RCU_INT_PLL2STBIC BIT(22) /*!< PLL2 stabilization interrupt clear */ +#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ + +/* RCU_APB2RST */ +#define RCU_APB2RST_AFRST BIT(0) /*!< alternate function I/O reset */ +#define RCU_APB2RST_PARST BIT(2) /*!< GPIO port A reset */ +#define RCU_APB2RST_PBRST BIT(3) /*!< GPIO port B reset */ +#define RCU_APB2RST_PCRST BIT(4) /*!< GPIO port C reset */ +#define RCU_APB2RST_PDRST BIT(5) /*!< GPIO port D reset */ +#define RCU_APB2RST_PERST BIT(6) /*!< GPIO port E reset */ +#define RCU_APB2RST_ADC0RST BIT(9) /*!< ADC0 reset */ +#define RCU_APB2RST_ADC1RST BIT(10) /*!< ADC1 reset */ +#define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */ +#define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ +#define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */ + +/* RCU_APB1RST */ +#define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 reset */ +#define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 reset */ +#define RCU_APB1RST_TIMER3RST BIT(2) /*!< TIMER3 reset */ +#define RCU_APB1RST_TIMER4RST BIT(3) /*!< TIMER4 reset */ +#define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 reset */ +#define RCU_APB1RST_TIMER6RST BIT(5) /*!< TIMER6 reset */ + +#define RCU_APB1RST_WWDGTRST BIT(11) /*!< WWDGT reset */ +#define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ +#define RCU_APB1RST_SPI2RST BIT(15) /*!< SPI2 reset */ +#define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ +#define RCU_APB1RST_USART2RST BIT(18) /*!< USART2 reset */ +#define RCU_APB1RST_UART3RST BIT(19) /*!< UART3 reset */ +#define RCU_APB1RST_UART4RST BIT(20) /*!< UART4 reset */ +#define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ +#define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ +#define RCU_APB1RST_CAN0RST BIT(25) /*!< CAN0 reset */ +#define RCU_APB1RST_CAN1RST BIT(26) /*!< CAN1 reset */ +#define RCU_APB1RST_BKPIRST BIT(27) /*!< backup interface reset */ +#define RCU_APB1RST_PMURST BIT(28) /*!< PMU reset */ +#define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */ + +/* RCU_AHBEN */ +#define RCU_AHBEN_DMA0EN BIT(0) /*!< DMA0 clock enable */ +#define RCU_AHBEN_DMA1EN BIT(1) /*!< DMA1 clock enable */ +#define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM clock enable when sleep mode */ +#define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable when sleep mode */ +#define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */ +#define RCU_AHBEN_EXMCEN BIT(8) /*!< EXMC clock enable */ +#define RCU_AHBEN_USBFSEN BIT(12) /*!< USBFS clock enable */ + +/* RCU_APB2EN */ +#define RCU_APB2EN_AFEN BIT(0) /*!< alternate function IO clock enable */ +#define RCU_APB2EN_PAEN BIT(2) /*!< GPIO port A clock enable */ +#define RCU_APB2EN_PBEN BIT(3) /*!< GPIO port B clock enable */ +#define RCU_APB2EN_PCEN BIT(4) /*!< GPIO port C clock enable */ +#define RCU_APB2EN_PDEN BIT(5) /*!< GPIO port D clock enable */ +#define RCU_APB2EN_PEEN BIT(6) /*!< GPIO port E clock enable */ +#define RCU_APB2EN_ADC0EN BIT(9) /*!< ADC0 clock enable */ +#define RCU_APB2EN_ADC1EN BIT(10) /*!< ADC1 clock enable */ +#define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 clock enable */ +#define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ +#define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */ + +/* RCU_APB1EN */ +#define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 clock enable */ +#define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 clock enable */ +#define RCU_APB1EN_TIMER3EN BIT(2) /*!< TIMER3 clock enable */ +#define RCU_APB1EN_TIMER4EN BIT(3) /*!< TIMER4 clock enable */ +#define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 clock enable */ +#define RCU_APB1EN_TIMER6EN BIT(5) /*!< TIMER6 clock enable */ +#define RCU_APB1EN_WWDGTEN BIT(11) /*!< WWDGT clock enable */ +#define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ +#define RCU_APB1EN_SPI2EN BIT(15) /*!< SPI2 clock enable */ +#define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ +#define RCU_APB1EN_USART2EN BIT(18) /*!< USART2 clock enable */ +#define RCU_APB1EN_UART3EN BIT(19) /*!< UART3 clock enable */ +#define RCU_APB1EN_UART4EN BIT(20) /*!< UART4 clock enable */ +#define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ +#define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ +#define RCU_APB1EN_CAN0EN BIT(25) /*!< CAN0 clock enable */ +#define RCU_APB1EN_CAN1EN BIT(26) /*!< CAN1 clock enable */ +#define RCU_APB1EN_BKPIEN BIT(27) /*!< backup interface clock enable */ +#define RCU_APB1EN_PMUEN BIT(28) /*!< PMU clock enable */ +#define RCU_APB1EN_DACEN BIT(29) /*!< DAC clock enable */ + +/* RCU_BDCTL */ +#define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ +#define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */ +#define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ +#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ +#define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ +#define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ + +/* RCU_RSTSCK */ +#define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */ +#define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization flag */ +#define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ +#define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ +#define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ +#define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ +#define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ +#define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ +#define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ + +/* RCU_AHBRST */ +#define RCU_AHBRST_USBFSRST BIT(12) /*!< USBFS reset */ + +/* RCU_CFG1 */ +#define RCU_CFG1_PREDV0 BITS(0,3) /*!< PREDV0 division factor */ +#define RCU_CFG1_PREDV1 BITS(4,7) /*!< PREDV1 division factor */ +#define RCU_CFG1_PLL1MF BITS(8,11) /*!< PLL1 clock multiplication factor */ +#define RCU_CFG1_PLL2MF BITS(12,15) /*!< PLL2 clock multiplication factor */ +#define RCU_CFG1_PREDV0SEL BIT(16) /*!< PREDV0 input clock source selection */ +#define RCU_CFG1_I2S1SEL BIT(17) /*!< I2S1 clock source selection */ +#define RCU_CFG1_I2S2SEL BIT(18) /*!< I2S2 clock source selection */ + +/* RCU_DSV */ +#define RCU_DSV_DSLPVS BITS(0,1) /*!< deep-sleep mode voltage select */ + +/* constants definitions */ +/* define the peripheral clock enable bit position and its register index offset */ +#define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6))) +#define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU) + +/* register offset */ +/* peripherals enable */ +#define AHBEN_REG_OFFSET 0x14U /*!< AHB enable register offset */ +#define APB1EN_REG_OFFSET 0x1CU /*!< APB1 enable register offset */ +#define APB2EN_REG_OFFSET 0x18U /*!< APB2 enable register offset */ + +/* peripherals reset */ +#define AHBRST_REG_OFFSET 0x28U /*!< AHB reset register offset */ +#define APB1RST_REG_OFFSET 0x10U /*!< APB1 reset register offset */ +#define APB2RST_REG_OFFSET 0x0CU /*!< APB2 reset register offset */ +#define RSTSCK_REG_OFFSET 0x24U /*!< reset source/clock register offset */ + +/* clock control */ +#define CTL_REG_OFFSET 0x00U /*!< control register offset */ +#define BDCTL_REG_OFFSET 0x20U /*!< backup domain control register offset */ + +/* clock stabilization and stuck interrupt */ +#define INT_REG_OFFSET 0x08U /*!< clock interrupt register offset */ + +/* configuration register */ +#define CFG0_REG_OFFSET 0x04U /*!< clock configuration register 0 offset */ +#define CFG1_REG_OFFSET 0x2CU /*!< clock configuration register 1 offset */ + +/* peripheral clock enable */ +typedef enum { + /* AHB peripherals */ + RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U), /*!< DMA0 clock */ + RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U), /*!< DMA1 clock */ + RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U), /*!< CRC clock */ + RCU_EXMC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 8U), /*!< EXMC clock */ + RCU_USBFS = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 12U), /*!< USBFS clock */ + /* APB1 peripherals */ + RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */ + RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), /*!< TIMER2 clock */ + RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U), /*!< TIMER3 clock */ + RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U), /*!< TIMER4 clock */ + RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), /*!< TIMER5 clock */ + RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */ + RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */ + RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */ + RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), /*!< SPI2 clock */ + RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), /*!< USART1 clock */ + RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), /*!< USART2 clock */ + RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U), /*!< UART3 clock */ + RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */ + RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */ + RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */ + RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), /*!< CAN0 clock */ + RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), /*!< CAN1 clock */ + RCU_BKPI = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U), /*!< BKPI clock */ + RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */ + RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */ + RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */ + /* APB2 peripherals */ + RCU_AF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< alternate function clock */ + RCU_GPIOA = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 2U), /*!< GPIOA clock */ + RCU_GPIOB = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 3U), /*!< GPIOB clock */ + RCU_GPIOC = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U), /*!< GPIOC clock */ + RCU_GPIOD = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U), /*!< GPIOD clock */ + RCU_GPIOE = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 6U), /*!< GPIOE clock */ + RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), /*!< ADC0 clock */ + RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U), /*!< ADC1 clock */ + RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), /*!< TIMER0 clock */ + RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), /*!< SPI0 clock */ + RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U), /*!< USART0 clock */ +} rcu_periph_enum; + +/* peripheral clock enable when sleep mode*/ +typedef enum { +/* AHB peripherals */ + RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U), /*!< SRAM clock */ + RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U), /*!< FMC clock */ +} rcu_periph_sleep_enum; + +/* peripherals reset */ +typedef enum { + /* AHB peripherals */ + RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBFS clock reset */ + /* APB1 peripherals */ + RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 clock reset */ + RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U), /*!< TIMER2 clock reset */ + RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */ + RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U), /*!< TIMER4 clock reset */ + RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */ + RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */ + RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */ + RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */ + RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), /*!< SPI2 clock reset */ + RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), /*!< USART1 clock reset */ + RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U), /*!< USART2 clock reset */ + RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U), /*!< UART3 clock reset */ + RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 clock reset */ + RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ + RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */ + RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */ + RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), /*!< CAN1 clock reset */ + RCU_BKPIRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 27U), /*!< BKPI clock reset */ + RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */ + RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */ + /* APB2 peripherals */ + RCU_AFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< alternate function clock reset */ + RCU_GPIOARST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 2U), /*!< GPIOA clock reset */ + RCU_GPIOBRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 3U), /*!< GPIOB clock reset */ + RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< GPIOC clock reset */ + RCU_GPIODRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U), /*!< GPIOD clock reset */ + RCU_GPIOERST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 6U), /*!< GPIOE clock reset */ + RCU_ADC0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U), /*!< ADC0 clock reset */ + RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U), /*!< ADC1 clock reset */ + RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), /*!< TIMER0 clock reset */ + RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), /*!< SPI0 clock reset */ + RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U), /*!< USART0 clock reset */ +} rcu_periph_reset_enum; + +/* clock stabilization and peripheral reset flags */ +typedef enum { + /* clock stabilization flags */ + RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC8M stabilization flags */ + RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */ + RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), /*!< PLL stabilization flags */ + RCU_FLAG_PLL1STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U), /*!< PLL1 stabilization flags */ + RCU_FLAG_PLL2STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U), /*!< PLL2 stabilization flags */ + RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flags */ + RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC40K stabilization flags */ + /* reset source flags */ + RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U), /*!< external PIN reset flags */ + RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), /*!< power reset flags */ + RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), /*!< software reset flags */ + RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */ + RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */ + RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< low-power reset flags */ +} rcu_flag_enum; + +/* clock stabilization and ckm interrupt flags */ +typedef enum { + RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC40K stabilization interrupt flag */ + RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */ + RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */ + RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */ + RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */ + RCU_INT_FLAG_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< PLL1 stabilization interrupt flag */ + RCU_INT_FLAG_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLL2 stabilization interrupt flag */ + RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */ +} rcu_int_flag_enum; + +/* clock stabilization and stuck interrupt flags clear */ +typedef enum { + RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC40K stabilization interrupt flags clear */ + RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */ + RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC8M stabilization interrupt flags clear */ + RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U), /*!< HXTAL stabilization interrupt flags clear */ + RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), /*!< PLL stabilization interrupt flags clear */ + RCU_INT_FLAG_PLL1STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< PLL1 stabilization interrupt flags clear */ + RCU_INT_FLAG_PLL2STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLL2 stabilization interrupt flags clear */ + RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */ +} rcu_int_flag_clear_enum; + +/* clock stabilization interrupt enable or disable */ +typedef enum { + RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC40K stabilization interrupt */ + RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */ + RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt */ + RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt */ + RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt */ + RCU_INT_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLL1 stabilization interrupt */ + RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLL2 stabilization interrupt */ +} rcu_int_enum; + +/* oscillator types */ +typedef enum { + RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */ + RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */ + RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC8M */ + RCU_IRC40K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U), /*!< IRC40K */ + RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U), /*!< PLL */ + RCU_PLL1_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U), /*!< PLL1 */ + RCU_PLL2_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U), /*!< PLL2 */ +} rcu_osci_type_enum; + +/* rcu clock frequency */ +typedef enum { + CK_SYS = 0, /*!< system clock */ + CK_AHB, /*!< AHB clock */ + CK_APB1, /*!< APB1 clock */ + CK_APB2, /*!< APB2 clock */ +} rcu_clock_freq_enum; + +/* RCU_CFG0 register bit define */ +/* system clock source select */ +#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ +#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ +#define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ + +/* system clock source select status */ +#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ +#define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ +#define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLLP */ + +/* AHB prescaler selection */ +#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) +#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ +#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ +#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ +#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ +#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ +#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ +#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ +#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ +#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ + +/* APB1 prescaler selection */ +#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) +#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ +#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ +#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ +#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ +#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ + +/* APB2 prescaler selection */ +#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) +#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ +#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ +#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ +#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ +#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ + +/* ADC prescaler select */ +#define RCU_CKADC_CKAPB2_DIV2 ((uint32_t)0x00000000U) /*!< ADC prescaler select CK_APB2/2 */ +#define RCU_CKADC_CKAPB2_DIV4 ((uint32_t)0x00000001U) /*!< ADC prescaler select CK_APB2/4 */ +#define RCU_CKADC_CKAPB2_DIV6 ((uint32_t)0x00000002U) /*!< ADC prescaler select CK_APB2/6 */ +#define RCU_CKADC_CKAPB2_DIV8 ((uint32_t)0x00000003U) /*!< ADC prescaler select CK_APB2/8 */ +#define RCU_CKADC_CKAPB2_DIV12 ((uint32_t)0x00000005U) /*!< ADC prescaler select CK_APB2/12 */ +#define RCU_CKADC_CKAPB2_DIV16 ((uint32_t)0x00000007U) /*!< ADC prescaler select CK_APB2/16 */ + +/* PLL clock source selection */ +#define RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U) /*!< IRC8M/2 clock selected as source clock of PLL */ +#define RCU_PLLSRC_HXTAL RCU_CFG0_PLLSEL /*!< HXTAL clock selected as source clock of PLL */ + +/* PLL clock multiplication factor */ +#define PLLMF_4 RCU_CFG0_PLLMF_4 /* bit 4 of PLLMF */ + +#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) +#define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ +#define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ +#define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ +#define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */ +#define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */ +#define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */ +#define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */ +#define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */ +#define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */ +#define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */ +#define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */ +#define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */ +#define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */ +#define RCU_PLL_MUL6_5 CFG0_PLLMF(13) /*!< PLL source clock multiply by 6.5 */ +#define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */ +#define RCU_PLL_MUL17 (PLLMF_4 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 17 */ +#define RCU_PLL_MUL18 (PLLMF_4 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 18 */ +#define RCU_PLL_MUL19 (PLLMF_4 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 19 */ +#define RCU_PLL_MUL20 (PLLMF_4 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 20 */ +#define RCU_PLL_MUL21 (PLLMF_4 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 21 */ +#define RCU_PLL_MUL22 (PLLMF_4 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 22 */ +#define RCU_PLL_MUL23 (PLLMF_4 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 23 */ +#define RCU_PLL_MUL24 (PLLMF_4 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 24 */ +#define RCU_PLL_MUL25 (PLLMF_4 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 25 */ +#define RCU_PLL_MUL26 (PLLMF_4 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 26 */ +#define RCU_PLL_MUL27 (PLLMF_4 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 27 */ +#define RCU_PLL_MUL28 (PLLMF_4 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 28 */ +#define RCU_PLL_MUL29 (PLLMF_4 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 29 */ +#define RCU_PLL_MUL30 (PLLMF_4 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 30 */ +#define RCU_PLL_MUL31 (PLLMF_4 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 31 */ +#define RCU_PLL_MUL32 (PLLMF_4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */ + +/* USBFS prescaler select */ +#define CFG0_USBPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) +#define RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0) /*!< USBFS prescaler select CK_PLL/1.5 */ +#define RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1) /*!< USBFS prescaler select CK_PLL/1 */ +#define RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2) /*!< USBFS prescaler select CK_PLL/2.5 */ +#define RCU_CKUSB_CKPLL_DIV2 CFG0_USBPSC(3) /*!< USBFS prescaler select CK_PLL/2 */ + +/* CKOUT0 clock source selection */ +#define CFG0_CKOUT0SEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) +#define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0) /*!< no clock selected */ +#define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4) /*!< system clock selected */ +#define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5) /*!< internal 8M RC oscillator clock selected */ +#define RCU_CKOUT0SRC_HXTAL CFG0_CKOUT0SEL(6) /*!< high speed crystal oscillator clock (HXTAL) selected */ +#define RCU_CKOUT0SRC_CKPLL_DIV2 CFG0_CKOUT0SEL(7) /*!< CK_PLL/2 clock selected */ +#define RCU_CKOUT0SRC_CKPLL1 CFG0_CKOUT0SEL(8) /*!< CK_PLL1 clock selected */ +#define RCU_CKOUT0SRC_CKPLL2_DIV2 CFG0_CKOUT0SEL(9) /*!< CK_PLL2/2 clock selected */ +#define RCU_CKOUT0SRC_EXT1 CFG0_CKOUT0SEL(10) /*!< EXT1 selected */ +#define RCU_CKOUT0SRC_CKPLL2 CFG0_CKOUT0SEL(11) /*!< CK_PLL2 clock selected */ + +/* RTC clock entry selection */ +#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) +#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ +#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */ +#define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC40K */ +#define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/128 */ + +/* PREDV0 division factor */ +#define CFG1_PREDV0(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) +#define RCU_PREDV0_DIV1 CFG1_PREDV0(0) /*!< PREDV0 input source clock not divided */ +#define RCU_PREDV0_DIV2 CFG1_PREDV0(1) /*!< PREDV0 input source clock divided by 2 */ +#define RCU_PREDV0_DIV3 CFG1_PREDV0(2) /*!< PREDV0 input source clock divided by 3 */ +#define RCU_PREDV0_DIV4 CFG1_PREDV0(3) /*!< PREDV0 input source clock divided by 4 */ +#define RCU_PREDV0_DIV5 CFG1_PREDV0(4) /*!< PREDV0 input source clock divided by 5 */ +#define RCU_PREDV0_DIV6 CFG1_PREDV0(5) /*!< PREDV0 input source clock divided by 6 */ +#define RCU_PREDV0_DIV7 CFG1_PREDV0(6) /*!< PREDV0 input source clock divided by 7 */ +#define RCU_PREDV0_DIV8 CFG1_PREDV0(7) /*!< PREDV0 input source clock divided by 8 */ +#define RCU_PREDV0_DIV9 CFG1_PREDV0(8) /*!< PREDV0 input source clock divided by 9 */ +#define RCU_PREDV0_DIV10 CFG1_PREDV0(9) /*!< PREDV0 input source clock divided by 10 */ +#define RCU_PREDV0_DIV11 CFG1_PREDV0(10) /*!< PREDV0 input source clock divided by 11 */ +#define RCU_PREDV0_DIV12 CFG1_PREDV0(11) /*!< PREDV0 input source clock divided by 12 */ +#define RCU_PREDV0_DIV13 CFG1_PREDV0(12) /*!< PREDV0 input source clock divided by 13 */ +#define RCU_PREDV0_DIV14 CFG1_PREDV0(13) /*!< PREDV0 input source clock divided by 14 */ +#define RCU_PREDV0_DIV15 CFG1_PREDV0(14) /*!< PREDV0 input source clock divided by 15 */ +#define RCU_PREDV0_DIV16 CFG1_PREDV0(15) /*!< PREDV0 input source clock divided by 16 */ + +/* PREDV1 division factor */ +#define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) +#define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input source clock not divided */ +#define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input source clock divided by 2 */ +#define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input source clock divided by 3 */ +#define RCU_PREDV1_DIV4 CFG1_PREDV1(3) /*!< PREDV1 input source clock divided by 4 */ +#define RCU_PREDV1_DIV5 CFG1_PREDV1(4) /*!< PREDV1 input source clock divided by 5 */ +#define RCU_PREDV1_DIV6 CFG1_PREDV1(5) /*!< PREDV1 input source clock divided by 6 */ +#define RCU_PREDV1_DIV7 CFG1_PREDV1(6) /*!< PREDV1 input source clock divided by 7 */ +#define RCU_PREDV1_DIV8 CFG1_PREDV1(7) /*!< PREDV1 input source clock divided by 8 */ +#define RCU_PREDV1_DIV9 CFG1_PREDV1(8) /*!< PREDV1 input source clock divided by 9 */ +#define RCU_PREDV1_DIV10 CFG1_PREDV1(9) /*!< PREDV1 input source clock divided by 10 */ +#define RCU_PREDV1_DIV11 CFG1_PREDV1(10) /*!< PREDV1 input source clock divided by 11 */ +#define RCU_PREDV1_DIV12 CFG1_PREDV1(11) /*!< PREDV1 input source clock divided by 12 */ +#define RCU_PREDV1_DIV13 CFG1_PREDV1(12) /*!< PREDV1 input source clock divided by 13 */ +#define RCU_PREDV1_DIV14 CFG1_PREDV1(13) /*!< PREDV1 input source clock divided by 14 */ +#define RCU_PREDV1_DIV15 CFG1_PREDV1(14) /*!< PREDV1 input source clock divided by 15 */ +#define RCU_PREDV1_DIV16 CFG1_PREDV1(15) /*!< PREDV1 input source clock divided by 16 */ + +/* PLL1 clock multiplication factor */ +#define CFG1_PLL1MF(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) +#define RCU_PLL1_MUL8 CFG1_PLL1MF(6) /*!< PLL1 source clock multiply by 8 */ +#define RCU_PLL1_MUL9 CFG1_PLL1MF(7) /*!< PLL1 source clock multiply by 9 */ +#define RCU_PLL1_MUL10 CFG1_PLL1MF(8) /*!< PLL1 source clock multiply by 10 */ +#define RCU_PLL1_MUL11 CFG1_PLL1MF(9) /*!< PLL1 source clock multiply by 11 */ +#define RCU_PLL1_MUL12 CFG1_PLL1MF(10) /*!< PLL1 source clock multiply by 12 */ +#define RCU_PLL1_MUL13 CFG1_PLL1MF(11) /*!< PLL1 source clock multiply by 13 */ +#define RCU_PLL1_MUL14 CFG1_PLL1MF(12) /*!< PLL1 source clock multiply by 14 */ +#define RCU_PLL1_MUL15 CFG1_PLL1MF(13) /*!< PLL1 source clock multiply by 15 */ +#define RCU_PLL1_MUL16 CFG1_PLL1MF(14) /*!< PLL1 source clock multiply by 16 */ +#define RCU_PLL1_MUL20 CFG1_PLL1MF(15) /*!< PLL1 source clock multiply by 20 */ + +/* PLL2 clock multiplication factor */ +#define CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12)) +#define RCU_PLL2_MUL8 CFG1_PLL2MF(6) /*!< PLL2 source clock multiply by 8 */ +#define RCU_PLL2_MUL9 CFG1_PLL2MF(7) /*!< PLL2 source clock multiply by 9 */ +#define RCU_PLL2_MUL10 CFG1_PLL2MF(8) /*!< PLL2 source clock multiply by 10 */ +#define RCU_PLL2_MUL11 CFG1_PLL2MF(9) /*!< PLL2 source clock multiply by 11 */ +#define RCU_PLL2_MUL12 CFG1_PLL2MF(10) /*!< PLL2 source clock multiply by 12 */ +#define RCU_PLL2_MUL13 CFG1_PLL2MF(11) /*!< PLL2 source clock multiply by 13 */ +#define RCU_PLL2_MUL14 CFG1_PLL2MF(12) /*!< PLL2 source clock multiply by 14 */ +#define RCU_PLL2_MUL15 CFG1_PLL2MF(13) /*!< PLL2 source clock multiply by 15 */ +#define RCU_PLL2_MUL16 CFG1_PLL2MF(14) /*!< PLL2 source clock multiply by 16 */ +#define RCU_PLL2_MUL20 CFG1_PLL2MF(15) /*!< PLL2 source clock multiply by 20 */ + + +/* PREDV0 input clock source selection */ +#define RCU_PREDV0SRC_HXTAL ((uint32_t)0x00000000U) /*!< HXTAL selected as PREDV0 input source clock */ +#define RCU_PREDV0SRC_CKPLL1 RCU_CFG1_PREDV0SEL /*!< CK_PLL1 selected as PREDV0 input source clock */ + +/* I2S1 clock source selection */ +#define RCU_I2S1SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S1 source clock */ +#define RCU_I2S1SRC_CKPLL2_MUL2 RCU_CFG1_I2S1SEL /*!< (CK_PLL2 x 2) selected as I2S1 source clock */ + +/* I2S2 clock source selection */ +#define RCU_I2S2SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S2 source clock */ +#define RCU_I2S2SRC_CKPLL2_MUL2 RCU_CFG1_I2S2SEL /*!< (CK_PLL2 x 2) selected as I2S2 source clock */ + + +/* deep-sleep mode voltage */ +#define DSV_DSLPVS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(0) /*!< core voltage is 1.2V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_1_1 DSV_DSLPVS(1) /*!< core voltage is 1.1V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(2) /*!< core voltage is 1.0V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(3) /*!< core voltage is 0.9V in deep-sleep mode */ + +/* function declarations */ +/* initialization, peripheral clock enable/disable functions */ +/* deinitialize the RCU */ +void rcu_deinit(void); +/* enable the peripherals clock */ +void rcu_periph_clock_enable(rcu_periph_enum periph); +/* disable the peripherals clock */ +void rcu_periph_clock_disable(rcu_periph_enum periph); +/* enable the peripherals clock when sleep mode */ +void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); +/* disable the peripherals clock when sleep mode */ +void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); +/* reset the peripherals */ +void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); +/* disable reset the peripheral */ +void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); +/* reset the BKP domain */ +void rcu_bkp_reset_enable(void); +/* disable the BKP domain reset */ +void rcu_bkp_reset_disable(void); + +/* clock configuration functions */ +/* configure the system clock source */ +void rcu_system_clock_source_config(uint32_t ck_sys); +/* get the system clock source */ +uint32_t rcu_system_clock_source_get(void); +/* configure the AHB prescaler selection */ +void rcu_ahb_clock_config(uint32_t ck_ahb); +/* configure the APB1 prescaler selection */ +void rcu_apb1_clock_config(uint32_t ck_apb1); +/* configure the APB2 prescaler selection */ +void rcu_apb2_clock_config(uint32_t ck_apb2); +/* configure the CK_OUT0 clock source and divider */ +void rcu_ckout0_config(uint32_t ckout0_src); +/* configure the PLL clock source selection and PLL multiply factor */ +void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul); + +/* configure the PREDV0 division factor and clock source */ +void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div); +/* configure the PREDV1 division factor */ +void rcu_predv1_config(uint32_t predv1_div); +/* configure the PLL1 clock */ +void rcu_pll1_config(uint32_t pll_mul); +/* configure the PLL2 clock */ +void rcu_pll2_config(uint32_t pll_mul); + +/* peripheral clock configuration functions */ +/* configure the ADC division factor */ +void rcu_adc_clock_config(uint32_t adc_psc); +/* configure the USBD/USBFS prescaler factor */ +void rcu_usb_clock_config(uint32_t usb_psc); +/* configure the RTC clock source selection */ +void rcu_rtc_clock_config(uint32_t rtc_clock_source); + +/* configure the I2S1 clock source selection */ +void rcu_i2s1_clock_config(uint32_t i2s_clock_source); +/* configure the I2S2 clock source selection */ +void rcu_i2s2_clock_config(uint32_t i2s_clock_source); + +/* interrupt & flag functions */ +/* get the clock stabilization and periphral reset flags */ +FlagStatus rcu_flag_get(rcu_flag_enum flag); +/* clear the reset flag */ +void rcu_all_reset_flag_clear(void); +/* get the clock stabilization interrupt and ckm flags */ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); +/* clear the interrupt flags */ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear); +/* enable the stabilization interrupt */ +void rcu_interrupt_enable(rcu_int_enum stab_int); +/* disable the stabilization interrupt */ +void rcu_interrupt_disable(rcu_int_enum stab_int); + +/* oscillator configuration functions */ +/* wait for oscillator stabilization flags is SET or oscillator startup is timeout */ +ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); +/* turn on the oscillator */ +void rcu_osci_on(rcu_osci_type_enum osci); +/* turn off the oscillator */ +void rcu_osci_off(rcu_osci_type_enum osci); +/* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ +void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); +/* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ +void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); +/* enable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_enable(void); +/* disable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_disable(void); + +/* set the IRC8M adjust value */ +void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval); +/* set the deep sleep mode voltage */ +void rcu_deepsleep_voltage_set(uint32_t dsvol); + +/* get the system clock, bus and peripheral clock frequency */ +uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); + +#endif /* GD32VF103_RCU_H */ diff --git a/cpu/gd32v/include/vendor/gd32vf103_rtc.h b/cpu/gd32v/include/vendor/gd32vf103_rtc.h new file mode 100644 index 0000000000..874c6bb291 --- /dev/null +++ b/cpu/gd32v/include/vendor/gd32vf103_rtc.h @@ -0,0 +1,148 @@ +/*! + \file gd32vf103_rtc.h + \brief definitions for the RTC + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_RTC_H +#define GD32VF103_RTC_H + +#include "gd32vf103.h" + +/* RTC definitions */ +#define RTC RTC_BASE + +/* registers definitions */ +#define RTC_INTEN REG32(RTC + 0x00U) /*!< interrupt enable register */ +#define RTC_CTL REG32(RTC + 0x04U) /*!< control register */ +#define RTC_PSCH REG32(RTC + 0x08U) /*!< prescaler high register */ +#define RTC_PSCL REG32(RTC + 0x0CU) /*!< prescaler low register */ +#define RTC_DIVH REG32(RTC + 0x10U) /*!< divider high register */ +#define RTC_DIVL REG32(RTC + 0x14U) /*!< divider low register */ +#define RTC_CNTH REG32(RTC + 0x18U) /*!< counter high register */ +#define RTC_CNTL REG32(RTC + 0x1CU) /*!< counter low register */ +#define RTC_ALRMH REG32(RTC + 0x20U) /*!< alarm high register */ +#define RTC_ALRML REG32(RTC + 0x24U) /*!< alarm low register */ + +/* bits definitions */ +/* RTC_INTEN */ +#define RTC_INTEN_SCIE BIT(0) /*!< second interrupt enable */ +#define RTC_INTEN_ALRMIE BIT(1) /*!< alarm interrupt enable */ +#define RTC_INTEN_OVIE BIT(2) /*!< overflow interrupt enable */ + +/* RTC_CTL */ +#define RTC_CTL_SCIF BIT(0) /*!< second interrupt flag */ +#define RTC_CTL_ALRMIF BIT(1) /*!< alarm interrupt flag */ +#define RTC_CTL_OVIF BIT(2) /*!< overflow interrupt flag */ +#define RTC_CTL_RSYNF BIT(3) /*!< registers synchronized flag */ +#define RTC_CTL_CMF BIT(4) /*!< configuration mode flag */ +#define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */ + +/* RTC_PSCH */ +#define RTC_PSCH_PSC BITS(0,3) /*!< prescaler high value */ + +/* RTC_PSCL */ +#define RTC_PSCL_PSC BITS(0,15) /*!< prescaler low value */ + +/* RTC_DIVH */ +#define RTC_DIVH_DIV BITS(0,3) /*!< divider high value */ + +/* RTC_DIVL */ +#define RTC_DIVL_DIV BITS(0,15) /*!< divider low value */ + +/* RTC_CNTH */ +#define RTC_CNTH_CNT BITS(0,15) /*!< counter high value */ + +/* RTC_CNTL */ +#define RTC_CNTL_CNT BITS(0,15) /*!< counter low value */ + +/* RTC_ALRMH */ +#define RTC_ALRMH_ALRM BITS(0,15) /*!< alarm high value */ + +/* RTC_ALRML */ +#define RTC_ALRML_ALRM BITS(0,15) /*!< alarm low value */ + +/* constants definitions */ +/* RTC interrupt enable or disable definitions */ +#define RTC_INT_SECOND RTC_INTEN_SCIE /*!< second interrupt enable */ +#define RTC_INT_ALARM RTC_INTEN_ALRMIE /*!< alarm interrupt enable */ +#define RTC_INT_OVERFLOW RTC_INTEN_OVIE /*!< overflow interrupt enable */ + +/* RTC interrupt flag definitions */ +#define RTC_INT_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */ +#define RTC_INT_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */ +#define RTC_INT_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */ + +/* RTC flag definitions */ +#define RTC_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */ +#define RTC_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */ +#define RTC_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */ +#define RTC_FLAG_RSYN RTC_CTL_RSYNF /*!< registers synchronized flag */ +#define RTC_FLAG_LWOF RTC_CTL_LWOFF /*!< last write operation finished flag */ + +/* function declarations */ +/* initialization functions */ +/* enter RTC configuration mode */ +void rtc_configuration_mode_enter(void); +/* exit RTC configuration mode */ +void rtc_configuration_mode_exit(void); +/* set RTC counter value */ +void rtc_counter_set(uint32_t cnt); +/* set RTC prescaler value */ +void rtc_prescaler_set(uint32_t psc); + +/* operation functions */ +/* wait RTC last write operation finished flag set */ +void rtc_lwoff_wait(void); +/* wait RTC registers synchronized flag set */ +void rtc_register_sync_wait(void); +/* set RTC alarm value */ +void rtc_alarm_config(uint32_t alarm); +/* get RTC counter value */ +uint32_t rtc_counter_get(void); +/* get RTC divider value */ +uint32_t rtc_divider_get(void); + +/* flag & interrupt functions */ +/* get RTC flag status */ +FlagStatus rtc_flag_get(uint32_t flag); +/* clear RTC flag status */ +void rtc_flag_clear(uint32_t flag); +/* get RTC interrupt flag status */ +FlagStatus rtc_interrupt_flag_get(uint32_t flag); +/* clear RTC interrupt flag status */ +void rtc_interrupt_flag_clear(uint32_t flag); +/* enable RTC interrupt */ +void rtc_interrupt_enable(uint32_t interrupt); +/* disable RTC interrupt */ +void rtc_interrupt_disable(uint32_t interrupt); + +#endif /* GD32VF103_RTC_H */ diff --git a/cpu/gd32v/include/vendor/gd32vf103_spi.h b/cpu/gd32v/include/vendor/gd32vf103_spi.h new file mode 100644 index 0000000000..7fc03e127f --- /dev/null +++ b/cpu/gd32v/include/vendor/gd32vf103_spi.h @@ -0,0 +1,256 @@ +/*! + \file gd32vf103_spi.h + \brief definitions for the SPI + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_SPI_H +#define GD32VF103_SPI_H + +#include "gd32vf103.h" + +/* SPIx(x=0,1,2) definitions */ +#define SPI0 (SPI_BASE + 0x0000F800U) +#define SPI1 SPI_BASE +#define SPI2 (SPI_BASE + 0x00000400U) + +/* SPI registers definitions */ +#define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control register 0 */ +#define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control register 1*/ +#define SPI_STAT(spix) REG32((spix) + 0x08U) /*!< SPI status register */ +#define SPI_DATA(spix) REG32((spix) + 0x0CU) /*!< SPI data register */ +#define SPI_CRCPOLY(spix) REG32((spix) + 0x10U) /*!< SPI CRC polynomial register */ +#define SPI_RCRC(spix) REG32((spix) + 0x14U) /*!< SPI receive CRC register */ +#define SPI_TCRC(spix) REG32((spix) + 0x18U) /*!< SPI transmit CRC register */ +#define SPI_I2SCTL(spix) REG32((spix) + 0x1CU) /*!< SPI I2S control register */ +#define SPI_I2SPSC(spix) REG32((spix) + 0x20U) /*!< SPI I2S clock prescaler register */ + +/* bits definitions */ +/* SPI_CTL0 */ +#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/ +#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ +#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ +#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */ +#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ +#define SPI_CTL0_LF BIT(7) /*!< LSB first mode */ +#define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */ +#define SPI_CTL0_SWNSSEN BIT(9) /*!< NSS software mode selection */ +#define SPI_CTL0_RO BIT(10) /*!< receive only */ +#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */ +#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */ +#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */ +#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/ +#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */ + +/* SPI_CTL1 */ +#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */ +#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */ +#define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */ +#define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse mode enable */ +#define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode enable */ +#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */ +#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */ +#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */ + +/* SPI_STAT */ +#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */ +#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */ +#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */ +#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */ +#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */ +#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */ +#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */ +#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */ +#define SPI_STAT_FERR BIT(8) /*!< format error bit */ + +/* SPI_DATA */ +#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ + +/* SPI_CRCPOLY */ +#define SPI_CRCPOLY_CRCPOLY BITS(0,15) /*!< CRC polynomial value */ + +/* SPI_RCRC */ +#define SPI_RCRC_RCRC BITS(0,15) /*!< RX CRC value */ + +/* SPI_TCRC */ +#define SPI_TCRC_TCRC BITS(0,15) /*!< TX CRC value */ + +/* SPI_I2SCTL */ +#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ +#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ +#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ +#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */ +#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ +#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */ +#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ +#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ + +/* SPI_I2SPSC */ +#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ +#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ +#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ + +/* constants definitions */ +/* SPI and I2S parameter struct definitions */ +typedef struct +{ + uint32_t device_mode; /*!< SPI master or slave */ + uint32_t trans_mode; /*!< SPI transtype */ + uint32_t frame_size; /*!< SPI frame size */ + uint32_t nss; /*!< SPI NSS control by handware or software */ + uint32_t endian; /*!< SPI big endian or little endian */ + uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */ + uint32_t prescale; /*!< SPI prescale factor */ +}spi_parameter_struct; + +/* SPI mode definitions */ +#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ +#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */ + +/* SPI bidirectional transfer direction */ +#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */ +#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */ + +/* SPI transmit type */ +#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */ +#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */ +#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */ +#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/ + +/* SPI frame size */ +#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */ +#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */ + +/* SPI NSS control mode */ +#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by software */ +#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */ + +/* SPI transmit way */ +#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */ +#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */ + +/* SPI clock phase and polarity */ +#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */ +#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */ +#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */ +#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ + +/* SPI clock prescale factor */ +#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) +#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ +#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ +#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */ +#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescale factor is 16 */ +#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescale factor is 32 */ +#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescale factor is 64 */ +#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */ +#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */ + +/* I2S audio sample rate */ +#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */ +#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */ +#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */ +#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */ +#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */ +#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */ +#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */ +#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */ +#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ + +/* I2S frame format */ +#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1)) +#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ +#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ +#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ +#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */ + +/* I2S master clock output */ +#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */ +#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ + +/* I2S operation mode */ +#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) +#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ +#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ +#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ +#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ + +/* I2S standard */ +#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ +#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ +#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ +#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */ +#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */ + +/* I2S clock polarity */ +#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */ +#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */ + +/* SPI DMA constants definitions */ +#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */ +#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */ + +/* SPI CRC constants definitions */ +#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */ +#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */ + +/* SPI/I2S interrupt enable/disable constants definitions */ +#define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */ +#define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */ +#define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */ + +/* SPI/I2S interrupt flag constants definitions */ +#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */ +#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */ +#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */ +#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */ +#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */ +#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */ +#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */ + +/* SPI/I2S flag definitions */ +#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ +#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ +#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */ +#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */ +#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */ +#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ +#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ +#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ +#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ +#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */ +#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */ +#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */ +#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ +#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ + +#endif /* GD32VF103_SPI_H */ diff --git a/cpu/gd32v/include/vendor/gd32vf103_timer.h b/cpu/gd32v/include/vendor/gd32vf103_timer.h new file mode 100644 index 0000000000..ea2026e3df --- /dev/null +++ b/cpu/gd32v/include/vendor/gd32vf103_timer.h @@ -0,0 +1,722 @@ +/*! + \file gd32vf103_timer.h + \brief definitions for the TIMER + + \version 2019-06-05, V1.0.1, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_TIMER_H +#define GD32VF103_TIMER_H + +#include "gd32vf103.h" + +/* TIMERx(x=0..13) definitions */ +#define TIMER0 (TIMER_BASE + 0x00012C00U) +#define TIMER1 (TIMER_BASE + 0x00000000U) +#define TIMER2 (TIMER_BASE + 0x00000400U) +#define TIMER3 (TIMER_BASE + 0x00000800U) +#define TIMER4 (TIMER_BASE + 0x00000C00U) +#define TIMER5 (TIMER_BASE + 0x00001000U) +#define TIMER6 (TIMER_BASE + 0x00001400U) + +/* registers definitions */ +#define TIMER_CTL0(timerx) REG32((timerx) + 0x00U) /*!< TIMER control register 0 */ +#define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control register 1 */ +#define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U) /*!< TIMER slave mode configuration register */ +#define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU) /*!< TIMER DMA and interrupt enable register */ +#define TIMER_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt flag register */ +#define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U) /*!< TIMER software event generation register */ +#define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U) /*!< TIMER channel control register 0 */ +#define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU) /*!< TIMER channel control register 1 */ +#define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U) /*!< TIMER channel control register 2 */ +#define TIMER_CNT(timerx) REG32((timerx) + 0x24U) /*!< TIMER counter register */ +#define TIMER_PSC(timerx) REG32((timerx) + 0x28U) /*!< TIMER prescaler register */ +#define TIMER_CAR(timerx) REG32((timerx) + 0x2CU) /*!< TIMER counter auto reload register */ +#define TIMER_CREP(timerx) REG32((timerx) + 0x30U) /*!< TIMER counter repetition register */ +#define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U) /*!< TIMER channel 0 capture/compare value register */ +#define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U) /*!< TIMER channel 1 capture/compare value register */ +#define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU) /*!< TIMER channel 2 capture/compare value register */ +#define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U) /*!< TIMER channel 3 capture/compare value register */ +#define TIMER_CCHP(timerx) REG32((timerx) + 0x44U) /*!< TIMER channel complementary protection register */ +#define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U) /*!< TIMER DMA configuration register */ +#define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU) /*!< TIMER DMA transfer buffer register */ + +/* bits definitions */ +/* TIMER_CTL0 */ +#define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */ +#define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */ +#define TIMER_CTL0_UPS BIT(2) /*!< update source */ +#define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ +#define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ +#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */ +#define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ +#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ + +/* TIMER_CTL1 */ +#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ +#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ +#define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ +#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ +#define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ +#define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ +#define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ +#define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */ +#define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */ +#define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */ +#define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */ +#define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ + +/* TIMER_SMCFG */ +#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ +#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */ +#define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ +#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ +#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ +#define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ +#define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ + +/* TIMER_DMAINTEN */ +#define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ +#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation interrupt request enable */ +#define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */ +#define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */ +#define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */ +#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 capture/compare DMA request enable */ +#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 capture/compare DMA request enable */ +#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 capture/compare DMA request enable */ +#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 capture/compare DMA request enable */ +#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */ +#define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */ + +/* TIMER_INTF */ +#define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */ +#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture/compare interrupt flag */ +#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture/compare interrupt flag */ +#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture/compare interrupt flag */ +#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture/compare interrupt flag */ +#define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */ +#define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */ +#define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */ +#define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 over capture flag */ +#define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 over capture flag */ +#define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 over capture flag */ +#define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 over capture flag */ + +/* TIMER_SWEVG */ +#define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */ +#define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */ +#define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */ +#define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */ +#define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */ +#define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */ +#define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */ +#define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */ + +/* TIMER_CHCTL0 */ +/* output compare mode */ +#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */ +#define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ +#define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ +#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare control */ +#define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ +#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */ +#define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ +#define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ +#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare control */ +#define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ +/* input capture mode */ +#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ +#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ +#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ +#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ + +/* TIMER_CHCTL1 */ +/* output compare mode */ +#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */ +#define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ +#define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ +#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare control */ +#define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ +#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */ +#define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ +#define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ +#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare control */ +#define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ +/* input capture mode */ +#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ +#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ +#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ +#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ + +/* TIMER_CHCTL2 */ +#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */ +#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture/compare function polarity */ +#define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */ +#define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */ +#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture/compare function enable */ +#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture/compare function polarity */ +#define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */ +#define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */ +#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture/compare function enable */ +#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture/compare function polarity */ +#define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */ +#define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */ +#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture/compare function enable */ +#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */ + +/* TIMER_CNT */ +#define TIMER_CNT_CNT BITS(0,15) /*!< 16 bit timer counter */ + +/* TIMER_PSC */ +#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ + +/* TIMER_CAR */ +#define TIMER_CAR_CARL BITS(0,15) /*!< 16 bit counter auto reload value */ + +/* TIMER_CREP */ +#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ + +/* TIMER_CH0CV */ +#define TIMER_CH0CV_CH0VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ + +/* TIMER_CH1CV */ +#define TIMER_CH1CV_CH1VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ + +/* TIMER_CH2CV */ +#define TIMER_CH2CV_CH2VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ + +/* TIMER_CH3CV */ +#define TIMER_CH3CV_CH3VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ + +/* TIMER_CCHP */ +#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ +#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ +#define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ +#define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ +#define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ +#define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */ +#define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */ +#define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ + +/* TIMER_DMACFG */ +#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */ +#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */ + +/* TIMER_DMATB */ +#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */ + +/* constants definitions */ +/* TIMER init parameter struct definitions */ +typedef struct +{ + uint16_t prescaler; /*!< prescaler value */ + uint16_t alignedmode; /*!< aligned mode */ + uint16_t counterdirection; /*!< counter direction */ + uint32_t period; /*!< period value */ + uint16_t clockdivision; /*!< clock division value */ + uint8_t repetitioncounter; /*!< the counter repetition value */ +}timer_parameter_struct; + +/* break parameter struct definitions */ +typedef struct +{ + uint16_t runoffstate; /*!< run mode off-state */ + uint16_t ideloffstate; /*!< idle mode off-state */ + uint16_t deadtime; /*!< dead time */ + uint16_t breakpolarity; /*!< break polarity */ + uint16_t outputautostate; /*!< output automatic enable */ + uint16_t protectmode; /*!< complementary register protect control */ + uint16_t breakstate; /*!< break enable */ +}timer_break_parameter_struct; + +/* channel output parameter struct definitions */ +typedef struct +{ + uint16_t outputstate; /*!< channel output state */ + uint16_t outputnstate; /*!< channel complementary output state */ + uint16_t ocpolarity; /*!< channel output polarity */ + uint16_t ocnpolarity; /*!< channel complementary output polarity */ + uint16_t ocidlestate; /*!< idle state of channel output */ + uint16_t ocnidlestate; /*!< idle state of channel complementary output */ +}timer_oc_parameter_struct; + +/* channel input parameter struct definitions */ +typedef struct +{ + uint16_t icpolarity; /*!< channel input polarity */ + uint16_t icselection; /*!< channel input mode selection */ + uint16_t icprescaler; /*!< channel input capture prescaler */ + uint16_t icfilter; /*!< channel input capture filter control */ +}timer_ic_parameter_struct; + +/* TIMER interrupt enable or disable */ +#define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */ +#define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 interrupt */ +#define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */ +#define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */ +#define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */ +#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */ +#define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */ +#define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */ + +/* TIMER interrupt flag */ +#define TIMER_INT_FLAG_UP TIMER_INT_UP /*!< update interrupt */ +#define TIMER_INT_FLAG_CH0 TIMER_INT_CH0 /*!< channel 0 interrupt */ +#define TIMER_INT_FLAG_CH1 TIMER_INT_CH1 /*!< channel 1 interrupt */ +#define TIMER_INT_FLAG_CH2 TIMER_INT_CH2 /*!< channel 2 interrupt */ +#define TIMER_INT_FLAG_CH3 TIMER_INT_CH3 /*!< channel 3 interrupt */ +#define TIMER_INT_FLAG_CMT TIMER_INT_CMT /*!< channel commutation interrupt flag */ +#define TIMER_INT_FLAG_TRG TIMER_INT_TRG /*!< trigger interrupt */ +#define TIMER_INT_FLAG_BRK TIMER_INT_BRK + +/* TIMER flag */ +#define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */ +#define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */ +#define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 flag */ +#define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 flag */ +#define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 flag */ +#define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel control update flag */ +#define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */ +#define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */ +#define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */ +#define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */ +#define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */ +#define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */ + +/* TIMER DMA source enable */ +#define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */ +#define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */ +#define TIMER_DMA_CH1D ((uint16_t)TIMER_DMAINTEN_CH1DEN) /*!< channel 1 DMA enable */ +#define TIMER_DMA_CH2D ((uint16_t)TIMER_DMAINTEN_CH2DEN) /*!< channel 2 DMA enable */ +#define TIMER_DMA_CH3D ((uint16_t)TIMER_DMAINTEN_CH3DEN) /*!< channel 3 DMA enable */ +#define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */ +#define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */ + +/* channel DMA request source selection */ +#define TIMER_DMAREQUEST_UPDATEEVENT TIMER_CTL1_DMAS /*!< DMA request of channel n is sent when update event occurs */ +#define TIMER_DMAREQUEST_CHANNELEVENT ((uint32_t)0x00000000U) /*!< DMA request of channel n is sent when channel n event occurs */ + +/* DMA access base address */ +#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) +#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ +#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ +#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ +#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */ +#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */ +#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */ +#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */ +#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */ +#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */ +#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */ +#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */ +#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */ +#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */ +#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */ +#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */ +#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */ +#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */ +#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */ +#define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */ + +/* DMA access burst length */ +#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) +#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ +#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ +#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ +#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */ +#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */ +#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */ +#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */ +#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */ +#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */ +#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */ +#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */ +#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */ +#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */ +#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */ +#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */ +#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */ +#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */ +#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */ + +/* TIMER software event generation source */ +#define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */ +#define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */ +#define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U) /*!< channel commutation event generation */ +#define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */ +#define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ + +/* center-aligned mode selection */ +#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) +#define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ +#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ +#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ +#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ + +/* TIMER prescaler reload mode */ +#define TIMER_PSC_RELOAD_NOW TIMER_SWEVG_UPG /*!< the prescaler is loaded right now */ +#define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000000U) /*!< the prescaler is loaded at the next update event */ + +/* count direction */ +#define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ +#define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */ + +/* specify division ratio between TIMER clock and dead-time and sampling clock */ +#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) +#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1,fDTS=fTIMER_CK */ +#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2,fDTS= fTIMER_CK/2 */ +#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ + +/* single pulse mode */ +#define TIMER_SP_MODE_SINGLE TIMER_CTL0_SPM /*!< single pulse mode */ +#define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000000U) /*!< repetitive pulse mode */ + +/* update source */ +#define TIMER_UPDATE_SRC_REGULAR TIMER_CTL0_UPS /*!< update generate only by counter overflow/underflow */ +#define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000000U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ + +/* run mode off-state configure */ +#define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ +#define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are disabled */ + + +/* idle mode off-state configure */ +#define TIMER_IOS_STATE_ENABLE ((uint16_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, he channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ +#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals(CHx_O/CHx_ON) are disabled */ + +/* break input polarity */ +#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */ +#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)TIMER_CCHP_BRKP) /*!< break input polarity is high */ + +/* output automatic enable */ +#define TIMER_OUTAUTO_ENABLE ((uint16_t)TIMER_CCHP_OAEN) /*!< output automatic enable */ +#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ + +/* complementary register protect control */ +#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) +#define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ +#define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ +#define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ +#define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */ + +/* break input enable */ +#define TIMER_BREAK_ENABLE ((uint16_t)TIMER_CCHP_BRKEN) /*!< break input enable */ +#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */ + +/* TIMER channel n(n=0,1,2,3) */ +#define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0..4)) */ +#define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0..4)) */ +#define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0..4)) */ +#define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3(TIMERx(x=0..4)) */ + +/* channel enable state */ +#define TIMER_CCX_ENABLE ((uint16_t)0x0001U) /*!< channel enable */ +#define TIMER_CCX_DISABLE ((uint16_t)0x0000U) /*!< channel disable */ + +/* channel complementary output enable state */ +#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */ +#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */ + +/* channel output polarity */ +#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */ +#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */ + +/* channel complementary output polarity */ +#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ +#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ + +/* idle state of channel output */ +#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */ +#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */ + +/* idle state of channel complementary output */ +#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ +#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ + +/* channel output compare mode */ +#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< timing mode */ +#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< active mode */ +#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< inactive mode */ +#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle mode */ +#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */ +#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */ +#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */ +#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode */ + +/* channel output compare shadow enable */ +#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */ +#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */ + +/* channel output compare fast enable */ +#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */ +#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */ + +/* channel output compare clear enable */ +#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ +#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ + +/* channel control shadow register update control */ +#define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers update by when CMTG bit is set */ +#define TIMER_UPDATECTL_CCUTRI TIMER_CTL1_CCUC /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ + +/* channel input capture polarity */ +#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */ +#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */ +#define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge */ + +/* TIMER input capture selection */ +#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel n is configured as input and icy is mapped on CIy */ +#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel n is configured as input and icy is mapped on opposite input */ +#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel n is configured as input and icy is mapped on ITS */ + +/* channel input capture prescaler */ +#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */ +#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */ +#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4 */ +#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ + +/* trigger selection */ +#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) +#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ +#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ +#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ +#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */ +#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */ +#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */ +#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */ +#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< filtered external trigger input */ + +/* master mode control */ +#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) +#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ +#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ +#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ +#define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channel 0 as trigger output TRGO */ +#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ + +/* slave mode control */ +#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) +#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ +#define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ +#define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ +#define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */ +#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ +#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ +#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ +#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ + +/* master slave mode selection */ +#define TIMER_MASTER_SLAVE_MODE_ENABLE TIMER_SMCFG_MSM /*!< master slave mode enable */ +#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000000U) /*!< master slave mode disable */ + +/* external trigger prescaler */ +#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) +#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ +#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ +#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ +#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */ + +/* external trigger polarity */ +#define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ +#define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ + +/* channel 0 trigger input selection */ +#define TIMER_HALLINTERFACE_ENABLE TIMER_CTL1_TI0S /*!< TIMER hall sensor mode enable */ +#define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode disable */ + +/* TIMERx(x=0..4) write CHxVAL register selection */ +#define TIMER_CHVSEL_ENABLE ((uint16_t)TIMER_CFG_OUTSEL) /*!< write CHxVAL register selection enable */ +#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */ + +/* function declarations */ +/* TIMER timebase */ +/* deinit a timer */ +void timer_deinit(uint32_t timer_periph); +/* initialize TIMER init parameter struct */ +void timer_struct_para_init(timer_parameter_struct* initpara); +/* initialize TIMER counter */ +void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara); +/* enable a timer */ +void timer_enable(uint32_t timer_periph); +/* disable a timer */ +void timer_disable(uint32_t timer_periph); +/* enable the auto reload shadow function */ +void timer_auto_reload_shadow_enable(uint32_t timer_periph); +/* disable the auto reload shadow function */ +void timer_auto_reload_shadow_disable(uint32_t timer_periph); +/* enable the update event */ +void timer_update_event_enable(uint32_t timer_periph); +/* disable the update event */ +void timer_update_event_disable(uint32_t timer_periph); +/* set TIMER counter alignment mode */ +void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned); +/* set TIMER counter up direction */ +void timer_counter_up_direction(uint32_t timer_periph); +/* set TIMER counter down direction */ +void timer_counter_down_direction(uint32_t timer_periph); + +/* configure TIMER prescaler */ +void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload); +/* configure TIMER repetition register value */ +void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition); +/* configure TIMER autoreload register value */ +void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload); +/* configure TIMER counter register value */ +void timer_counter_value_config(uint32_t timer_periph, uint16_t counter); +/* read TIMER counter value */ +uint32_t timer_counter_read(uint32_t timer_periph); +/* read TIMER prescaler value */ +uint16_t timer_prescaler_read(uint32_t timer_periph); +/* configure TIMER single pulse mode */ +void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode); +/* configure TIMER update source */ +void timer_update_source_config(uint32_t timer_periph, uint32_t update); + +/* TIMER DMA and event */ +/* enable the TIMER DMA */ +void timer_dma_enable(uint32_t timer_periph, uint16_t dma); +/* disable the TIMER DMA */ +void timer_dma_disable(uint32_t timer_periph, uint16_t dma); +/* channel DMA request source selection */ +void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request); +/* configure the TIMER DMA transfer */ +void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth); +/* software generate events */ +void timer_event_software_generate(uint32_t timer_periph, uint16_t event); + +/* TIMER channel complementary protection */ +/* initialize TIMER break parameter struct */ +void timer_break_struct_para_init(timer_break_parameter_struct* breakpara); +/* configure TIMER break function */ +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara); +/* enable TIMER break function */ +void timer_break_enable(uint32_t timer_periph); +/* disable TIMER break function */ +void timer_break_disable(uint32_t timer_periph); +/* enable TIMER output automatic function */ +void timer_automatic_output_enable(uint32_t timer_periph); +/* disable TIMER output automatic function */ +void timer_automatic_output_disable(uint32_t timer_periph); +/* enable or disable TIMER primary output function */ +void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue); +/* enable or disable channel capture/compare control shadow register */ +void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue); +/* configure TIMER channel control shadow register update control */ +void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl); + +/* TIMER channel output */ +/* initialize TIMER channel output parameter struct */ +void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara); +/* configure TIMER channel output function */ +void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara); +/* configure TIMER channel output compare mode */ +void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode); +/* configure TIMER channel output pulse value */ +void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse); +/* configure TIMER channel output shadow function */ +void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow); +/* configure TIMER channel output fast function */ +void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast); +/* configure TIMER channel output clear function */ +void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear); +/* configure TIMER channel output polarity */ +void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity); +/* configure TIMER channel complementary output polarity */ +void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity); +/* configure TIMER channel enable state */ +void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state); +/* configure TIMER channel complementary output enable state */ +void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate); + +/* TIMER channel input */ +/* initialize TIMER channel input parameter struct */ +void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara); +/* configure TIMER input capture parameter */ +void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara); +/* configure TIMER channel input capture prescaler value */ +void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); +/* read TIMER channel capture compare register value */ +uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); +/* configure TIMER input pwm capture function */ +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm); +/* configure TIMER hall sensor mode */ +void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode); + +/* TIMER master and slave mode */ +/* select TIMER input trigger source */ +void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger); +/* select TIMER master mode output trigger source */ +void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger); +/* select TIMER slave mode */ +void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode); +/* configure TIMER master slave mode */ +void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave); +/* configure TIMER external trigger input */ +void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* configure TIMER quadrature decoder mode */ +void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity); +/* configure TIMER internal clock mode */ +void timer_internal_clock_config(uint32_t timer_periph); +/* configure TIMER the internal trigger as external clock input */ +void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger); +/* configure TIMER the external trigger as external clock input */ +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter); +/* configure TIMER the external clock mode 0 */ +void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* configure TIMER the external clock mode 1 */ +void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* disable TIMER the external clock mode 1 */ +void timer_external_clock_mode1_disable(uint32_t timer_periph); + +/* TIMER interrupt and flag */ +/* enable the TIMER interrupt */ +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); +/* disable the TIMER interrupt */ +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); +/* get TIMER interrupt flag */ +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); +/* clear TIMER interrupt flag */ +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); +/* get TIMER flag */ +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); +/* clear TIMER flag */ +void timer_flag_clear(uint32_t timer_periph, uint32_t flag); + +#endif /* GD32VF103_TIMER_H */ diff --git a/cpu/gd32v/include/vendor/gd32vf103_usart.h b/cpu/gd32v/include/vendor/gd32vf103_usart.h new file mode 100644 index 0000000000..18570f4116 --- /dev/null +++ b/cpu/gd32v/include/vendor/gd32vf103_usart.h @@ -0,0 +1,266 @@ +/*! + \file gd32vf103_usart.h + \brief definitions for the USART + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 + \version 2019-09-18, V1.0.1, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2018, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_USART_H +#define GD32VF103_USART_H + +#include "gd32vf103.h" + +/* USARTx(x=0,1,2)/UARTx(x=3,4) definitions */ +#define USART1 USART_BASE /*!< USART1 base address */ +#define USART2 (USART_BASE+(0x00000400U)) /*!< USART2 base address */ +#define UART3 (USART_BASE+(0x00000800U)) /*!< UART3 base address */ +#define UART4 (USART_BASE+(0x00000C00U)) /*!< UART4 base address */ +#define USART0 (USART_BASE+(0x0000F400U)) /*!< USART0 base address */ + +/* registers definitions */ +#define USART_STAT(usartx) REG32((usartx) + (0x00000000U)) /*!< USART status register */ +#define USART_DATA(usartx) REG32((usartx) + (0x00000004U)) /*!< USART data register */ +#define USART_BAUD(usartx) REG32((usartx) + (0x00000008U)) /*!< USART baud rate register */ +#define USART_CTL0(usartx) REG32((usartx) + (0x0000000CU)) /*!< USART control register 0 */ +#define USART_CTL1(usartx) REG32((usartx) + (0x00000010U)) /*!< USART control register 1 */ +#define USART_CTL2(usartx) REG32((usartx) + (0x00000014U)) /*!< USART control register 2 */ +#define USART_GP(usartx) REG32((usartx) + (0x00000018U)) /*!< USART guard time and prescaler register */ + +/* bits definitions */ +/* USARTx_STAT */ +#define USART_STAT_PERR BIT(0) /*!< parity error flag */ +#define USART_STAT_FERR BIT(1) /*!< frame error flag */ +#define USART_STAT_NERR BIT(2) /*!< noise error flag */ +#define USART_STAT_ORERR BIT(3) /*!< overrun error */ +#define USART_STAT_IDLEF BIT(4) /*!< IDLE frame detected flag */ +#define USART_STAT_RBNE BIT(5) /*!< read data buffer not empty */ +#define USART_STAT_TC BIT(6) /*!< transmission complete */ +#define USART_STAT_TBE BIT(7) /*!< transmit data buffer empty */ +#define USART_STAT_LBDF BIT(8) /*!< LIN break detected flag */ +#define USART_STAT_CTSF BIT(9) /*!< CTS change flag */ + +/* USARTx_DATA */ +#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ + +/* USARTx_BAUD */ +#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ +#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ + +/* USARTx_CTL0 */ +#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ +#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */ +#define USART_CTL0_REN BIT(2) /*!< receiver enable */ +#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ +#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ +#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ +#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ +#define USART_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */ +#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ +#define USART_CTL0_PM BIT(9) /*!< parity mode */ +#define USART_CTL0_PCEN BIT(10) /*!< parity check function enable */ +#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ +#define USART_CTL0_WL BIT(12) /*!< word length */ +#define USART_CTL0_UEN BIT(13) /*!< USART enable */ + +/* USARTx_CTL1 */ +#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ +#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ +#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ +#define USART_CTL1_CLEN BIT(8) /*!< CK length */ +#define USART_CTL1_CPH BIT(9) /*!< CK phase */ +#define USART_CTL1_CPL BIT(10) /*!< CK polarity */ +#define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ +#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ +#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ + +/* USARTx_CTL2 */ +#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable */ +#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ +#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ +#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ +#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ +#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ +#define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */ +#define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */ +#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ +#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ +#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ + +/* USARTx_GP */ +#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ +#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ + +/* constants definitions */ +/* define the USART bit position and its register index offset */ +#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & (0x0000FFFFU)) >> 6))) +#define USART_BIT_POS(val) ((uint32_t)(val) & (0x0000001FU)) +#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) +#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) +#define USART_BIT_POS2(val) (((uint32_t)(val) & (0x001F0000U)) >> 16) + +/* register offset */ +#define USART_STAT_REG_OFFSET (0x00000000U) /*!< STAT register offset */ +#define USART_CTL0_REG_OFFSET (0x0000000CU) /*!< CTL0 register offset */ +#define USART_CTL1_REG_OFFSET (0x00000010U) /*!< CTL1 register offset */ +#define USART_CTL2_REG_OFFSET (0x00000014U) /*!< CTL2 register offset */ + +/* USART flags */ +typedef enum +{ + /* flags in STAT register */ + USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */ + USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */ + USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U), /*!< transmit data buffer empty */ + USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U), /*!< transmission complete */ + USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty */ + USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U), /*!< IDLE frame detected flag */ + USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U), /*!< overrun error */ + USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U), /*!< noise error flag */ + USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U), /*!< frame error flag */ + USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U), /*!< parity error flag */ +}usart_flag_enum; + +/* USART interrupt flags */ +typedef enum +{ + /* interrupt flags in CTL0 register */ + USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ + USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ + USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ + USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ + USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ + USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ + /* interrupt flags in CTL1 register */ + USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */ + /* interrupt flags in CTL2 register */ + USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U), /*!< CTS interrupt and flag */ + USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U), /*!< error interrupt and overrun error */ + USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ + USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ +}usart_interrupt_flag_enum; + +/* USART interrupt enable or disable */ +typedef enum +{ + /* interrupt in CTL0 register */ + USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ + USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ + USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ + USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ + USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ + /* interrupt in CTL1 register */ + USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ + /* interrupt in CTL2 register */ + USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ + USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ +}usart_interrupt_enum; + +/* USART receiver configure */ +#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) +#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ +#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ + +/* USART transmitter configure */ +#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) +#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ +#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ + +/* USART parity bits definitions */ +#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) +#define USART_PM_NONE CTL0_PM(0) /*!< no parity */ +#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ +#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ + +/* USART wakeup method in mute mode */ +#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) +#define USART_WM_IDLE CTL0_WM(0) /*!< idle line */ +#define USART_WM_ADDR CTL0_WM(1) /*!< address match */ + +/* USART word length definitions */ +#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) +#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ +#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ + +/* USART stop bits definitions */ +#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) +#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ +#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ +#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ +#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ + +/* USART LIN break frame length */ +#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) +#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits */ +#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits */ + +/* USART CK length */ +#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) +#define USART_CLEN_NONE CTL1_CLEN(0) /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */ +#define USART_CLEN_EN CTL1_CLEN(1) /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */ + +/* USART clock phase */ +#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) +#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ +#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ + +/* USART clock polarity */ +#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) +#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ +#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ + +/* USART DMA request for receive configure */ +#define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) +#define USART_DENR_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */ +#define USART_DENR_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */ + +/* USART DMA request for transmission configure */ +#define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) +#define USART_DENT_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */ +#define USART_DENT_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */ + +/* USART RTS configure */ +#define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) +#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< RTS enable */ +#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< RTS disable */ + +/* USART CTS configure */ +#define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) +#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< CTS enable */ +#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< CTS disable */ + +/* USART IrDA low-power enable */ +#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) +#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ +#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ + +#endif /* GD32VF103_USART_H */ diff --git a/cpu/gd32v/include/vendor/gd32vf103_wwdgt.h b/cpu/gd32v/include/vendor/gd32vf103_wwdgt.h new file mode 100644 index 0000000000..23f5905529 --- /dev/null +++ b/cpu/gd32v/include/vendor/gd32vf103_wwdgt.h @@ -0,0 +1,86 @@ +/*! + \file gd32vf103_wwdgt.h + \brief definitions for the WWDGT + + \version 2019-06-05, V1.0.0, firmware for GD32VF103 +*/ + +/* + Copyright (c) 2019, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32VF103_WWDGT_H +#define GD32VF103_WWDGT_H + +#include "gd32vf103.h" + +/* WWDGT definitions */ +#define WWDGT WWDGT_BASE /*!< WWDGT base address */ + +/* registers definitions */ +#define WWDGT_CTL REG32((WWDGT) + 0x00000000U) /*!< WWDGT control register */ +#define WWDGT_CFG REG32((WWDGT) + 0x00000004U) /*!< WWDGT configuration register */ +#define WWDGT_STAT REG32((WWDGT) + 0x00000008U) /*!< WWDGT status register */ + +/* bits definitions */ +/* WWDGT_CTL */ +#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */ +#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ + +/* WWDGT_CFG */ +#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */ +#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */ +#define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */ + +/* WWDGT_STAT */ +#define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */ + +/* constants definitions */ +#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */ +#define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ +#define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ +#define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ +#define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */ + +/* function declarations */ +/* reset the window watchdog timer configuration */ +void wwdgt_deinit(void); +/* start the window watchdog timer counter */ +void wwdgt_enable(void); + +/* configure the window watchdog timer counter value */ +void wwdgt_counter_update(uint16_t counter_value); +/* configure counter value, window value, and prescaler divider value */ +void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler); + +/* enable early wakeup interrupt of WWDGT */ +void wwdgt_interrupt_enable(void); +/* check early wakeup interrupt state of WWDGT */ +FlagStatus wwdgt_flag_get(void); +/* clear early wakeup interrupt state of WWDGT */ +void wwdgt_flag_clear(void); + +#endif /* GD32VF103_WWDGT_H */ diff --git a/cpu/gd32v/periph/Makefile b/cpu/gd32v/periph/Makefile new file mode 100644 index 0000000000..a36df249ac --- /dev/null +++ b/cpu/gd32v/periph/Makefile @@ -0,0 +1 @@ +include $(RIOTMAKE)/periph.mk diff --git a/cpu/gd32v/periph/flashpage.c b/cpu/gd32v/periph/flashpage.c new file mode 100644 index 0000000000..2832659b1a --- /dev/null +++ b/cpu/gd32v/periph/flashpage.c @@ -0,0 +1,149 @@ +/* + * Copyright (C) 2020 Inria + * Copyright (C) 2020 Koen Zandberg + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup cpu_stm32 + * @{ + * + * @file + * @brief Low-level flash lock/unlock implementation + * + * @author Alexandre Abadie + * @author Oleg Artamonov + * @author Koen Zandberg + * + * @} + */ + +#include "cpu.h" +#include "periph_cpu.h" +#include "periph/flashpage.h" + +#define ENABLE_DEBUG 0 +#include "debug.h" + +#define FLASHPAGE_DIV (2U) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +static void _unlock_flash(void) +{ + if (FMC->CTL0 & FMC_CTL0_LK_Msk) { + DEBUG("[flash-common] unlocking the flash module\n"); + FMC->KEY0 = FLASH_KEY1; + FMC->KEY0 = FLASH_KEY2; + } +} + +static void _lock_flash(void) +{ + if (!(FMC->CTL0 & FMC_CTL0_LK_Msk)) { + DEBUG("[flash-common] locking the flash module\n"); + FMC->CTL0 |= FMC_CTL0_LK_Msk; + } +} + +static void _wait_for_pending_operations(void) +{ + if (FMC->STAT0 & FMC_STAT0_BUSY_Msk) { + DEBUG("[flash-common] waiting for any pending operation to finish\n"); + while (FMC->STAT0 & FMC_STAT0_BUSY_Msk) {} + } + + /* Clear 'end of operation' bit in status register */ + FMC->STAT0 |= FMC_STAT0_ENDF_Msk; +} + +void flashpage_erase(unsigned page) +{ + uint32_t irc8_state = (RCU->CTL & RCU_CTL_IRC8MEN_Msk); + uint16_t *dst = flashpage_addr(page); + + /* the internal RC oscillator (HSI) must be enabled */ + gd32v_enable_irc8(); + + /* unlock the flash module */ + _unlock_flash(); + + /* make sure no flash operation is ongoing */ + _wait_for_pending_operations(); + + /* set page erase bit and program page address */ + DEBUG("[flashpage] erase: setting the erase bit\n"); + FMC->CTL0 |= FMC_CTL0_PER_Msk; + DEBUG("address to erase: %p\n", dst); + DEBUG("[flashpage] erase: setting the page address\n"); + FMC->ADDR0 = (uint32_t)dst; + /* trigger the page erase and wait for it to be finished */ + DEBUG("[flashpage] erase: trigger the page erase\n"); + FMC->CTL0 |= FMC_CTL0_START_Msk; + /* wait as long as device is busy */ + _wait_for_pending_operations(); + + /* reset PER bit */ + DEBUG("[flashpage] erase: resetting the page erase bit\n"); + FMC->CTL0 &= ~(FMC_CTL0_PER_Msk); + + /* lock the flash module again */ + _lock_flash(); + + /* restore the HSI state */ + if (!irc8_state) { + gd32v_disable_irc8(); + } +} + +void flashpage_write(void *target_addr, const void *data, size_t len) +{ + /* assert multiples of FLASHPAGE_WRITE_BLOCK_SIZE are written and no less of + that length. */ + assert(!(len % FLASHPAGE_WRITE_BLOCK_SIZE)); + + /* ensure writes are aligned */ + assert(!(((unsigned)target_addr % FLASHPAGE_WRITE_BLOCK_ALIGNMENT) || + ((unsigned)data % FLASHPAGE_WRITE_BLOCK_ALIGNMENT))); + + /* ensure the length doesn't exceed the actual flash size */ + assert(((unsigned)target_addr + len) < + (CPU_FLASH_BASE + (FLASHPAGE_SIZE * FLASHPAGE_NUMOF)) + 1); + + uint16_t *dst = (uint16_t *)target_addr; + const uint16_t *data_addr = data; + + uint32_t irc8_state = (RCU->CTL & RCU_CTL_IRC8MEN_Msk); + + /* the internal RC oscillator (HSI) must be enabled */ + gd32v_enable_irc8(); + + /* unlock the flash module */ + _unlock_flash(); + + /* make sure no flash operation is ongoing */ + _wait_for_pending_operations(); + + /* set PG bit and program page to flash */ + FMC->CTL0 |= FMC_CTL0_PG_Msk; + for (size_t i = 0; i < (len / FLASHPAGE_DIV); i++) { + DEBUG("[flashpage_write] writing %c to %p\n", (char)data_addr[i], dst); + *dst++ = data_addr[i]; + /* wait as long as device is busy */ + _wait_for_pending_operations(); + } + + FMC->CTL0 &= ~(FMC_CTL0_PG_Msk); + DEBUG("[flashpage_write] write: done writing data\n"); + + /* lock the flash module again */ + _lock_flash(); + + /* restore the HSI state */ + if (!irc8_state) { + gd32v_disable_irc8(); + } +} diff --git a/cpu/gd32v/periph/gpio.c b/cpu/gd32v/periph/gpio.c new file mode 100644 index 0000000000..97e9faa996 --- /dev/null +++ b/cpu/gd32v/periph/gpio.c @@ -0,0 +1,187 @@ +/* + * Copyright (C) 2020 Koen Zandberg + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ +/** + * @ingroup cpu_gd32v + * @{ + * + * @file + * @brief GD32V GPIO implementation + * + * @author Koen Zandberg + */ + +#include "cpu.h" +#include "clic.h" +#include "periph_cpu.h" +#include "periph/gpio.h" + +/** + * @brief Extract information from mode parameter + */ +#define MODE_MASK (0x0f) +#define ODR_POS (4U) + +/** + * @brief Extract the port base address from the given pin identifier + */ +static inline GPIO_Type *_port(gpio_t pin) +{ + return (GPIO_Type *)(pin & ~(0x0f)); +} + +/** + * @brief Extract the port number form the given identifier + * + * The port number is extracted by looking at bits 10, 11, 12, 13 of the base + * register addresses. + */ +static inline int _port_num(gpio_t pin) +{ + return (((pin >> 10) & 0x0f) - 2); +} + +/** + * @brief Extract the pin number from the last 4 bit of the pin identifier + */ +static inline int _pin_num(gpio_t pin) +{ + return (pin & 0x0f); +} + +static inline void _port_enable_clock(gpio_t pin) +{ + periph_clk_en(APB2, (RCU_APB2EN_PAEN_Msk << _port_num(pin))); +} + +/** + * @brief Check if the given mode is some kind of input mdoe + * @param[in] mode Mode to check + * @retval 1 @p mode is GPIO_IN, GPIO_IN_PD, or GPIO_IN_PU + * @retval 0 @p mode is not an input mode + */ +static inline int gpio_mode_is_input(gpio_mode_t mode) +{ + return !(mode & 3); +} + +static inline void _set_mode_or_af(GPIO_Type *port, unsigned pin_num, + unsigned mode_or_af) +{ + volatile uint32_t *crl = (&port->CTL0 + (pin_num >> 3)); + uint32_t tmp = *crl; + + tmp &= ~(0xf << ((pin_num & 0x7) * 4)); + tmp |= ((mode_or_af & MODE_MASK) << ((pin_num & 0x7) * 4)); + *crl = tmp; +} + +static inline bool _pin_is_output(GPIO_Type *port, unsigned pin_num) +{ + uint32_t reg = *(uint32_t *)(&port->CTL0 + (pin_num >> 3)); + + return reg & (0x3 << ((pin_num & 0x7) << 2)); +} + +int gpio_init(gpio_t pin, gpio_mode_t mode) +{ + GPIO_Type *port = _port(pin); + unsigned pin_num = _pin_num(pin); + + /* open-drain output with pull-up is not supported */ + if (mode == GPIO_OD_PU) { + return -1; + } + + /* enable the clock for the selected port */ + _port_enable_clock(pin); + + /* set pin mode */ + _set_mode_or_af(port, pin_num, mode); + + /* For input modes, ODR controls pull up settings */ + if (gpio_mode_is_input(mode)) { + if (mode == GPIO_IN_PU) { + cpu_reg_enable_bits(&port->OCTL, 1 << pin_num); + } + else { + cpu_reg_disable_bits(&port->OCTL, 1 << pin_num); + } + } + + return 0; /* all OK */ +} + +void gpio_init_af(gpio_t pin, gpio_af_t af) +{ + GPIO_Type *port = _port(pin); + unsigned pin_num = _pin_num(pin); + + /* enable the clock for the selected port */ + _port_enable_clock(pin); + /* configure the pin */ + _set_mode_or_af(port, pin_num, af); +} + +void gpio_init_analog(gpio_t pin) +{ + /* enable the GPIO port RCC */ + _port_enable_clock(pin); + + /* map the pin as analog input */ + int pin_num = _pin_num(pin); + + volatile uint32_t *pin_reg = (uint32_t *)(&_port(pin)->CTL0 + (pin_num >= 8)); + *pin_reg &= ~(0xfl << (4 * (pin_num - ((pin_num >= 8) * 8)))); +} + +int gpio_read(gpio_t pin) +{ + GPIO_Type *port = _port(pin); + unsigned pin_num = _pin_num(pin); + + if (_pin_is_output(port, pin)) { + /* pin is output */ + return (port->OCTL & (1 << pin_num)); + } + else { + /* or input */ + return (port->ISTAT & (1 << pin_num)); + } +} + +void gpio_set(gpio_t pin) +{ + _port(pin)->BOP = (1 << _pin_num(pin)); +} + +void gpio_clear(gpio_t pin) +{ + _port(pin)->BC = (1 << _pin_num(pin)); +} + +void gpio_toggle(gpio_t pin) +{ + if (gpio_read(pin)) { + gpio_clear(pin); + } + else { + gpio_set(pin); + } +} + +void gpio_write(gpio_t pin, int value) +{ + if (value) { + gpio_set(pin); + } + else { + gpio_clear(pin); + } +} + +/** @} */ diff --git a/cpu/gd32v/periph/pm.c b/cpu/gd32v/periph/pm.c new file mode 100644 index 0000000000..f7c0908bdb --- /dev/null +++ b/cpu/gd32v/periph/pm.c @@ -0,0 +1,34 @@ +/* + * Copyright 2020 Koen Zandberg + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup cpu_gd32v + * @{ + * + * @brief Implementation of the CPU power management for Gigadevice GD32V + * + * @author Koen Zandberg + * @} + */ + +#include +#include "periph/pm.h" +#include "periph/wdt.h" + +void pm_set_lowest(void) +{ + __asm__ volatile ("wfi"); +} + +void pm_reboot(void) +{ + wdt_setup_reboot(0, 1); + wdt_start(); + wdt_kick(); + while (1) {} +} diff --git a/cpu/gd32v/periph/timer.c b/cpu/gd32v/periph/timer.c new file mode 100644 index 0000000000..21efb89d8c --- /dev/null +++ b/cpu/gd32v/periph/timer.c @@ -0,0 +1,280 @@ +/* + * Copyright (C) 2020 Koen Zandberg + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup cpu_gd32v + * @ingroup drivers_periph_timer + * @{ + * + * @file + * @brief Low-level timer driver implementation + * + * @author Koen Zandberg + * + * @} + */ + +#include "cpu.h" +#include "periph/timer.h" + +#define ENABLE_DEBUG 0 +#include "debug.h" + +/** + * @brief Define a macro for accessing a timer channel + */ +#define TIM_CHAN(tim, chan) *(&dev(tim)->CH0CV + chan) +#define TIMER_CHANNEL_NUMOF (4) + +static void _timer_isr(unsigned irq); + +/** + * @brief Interrupt context for each configured timer + */ +static timer_isr_ctx_t isr_ctx[TIMER_NUMOF]; + +/** + * @brief Get the timer device + */ +static inline TIMER_Type *dev(tim_t tim) +{ + return timer_config[tim].dev; +} + +#ifdef MODULE_PERIPH_TIMER_PERIODIC + +/** + * @brief Helper macro to get channel bit in timer/channel bitmap + */ +#define CHAN_BIT(tim, chan) (1 << chan) << (TIMER_CHANNEL_NUMOF * (tim & 1)) + +/** + * @brief Bitmap for compare channel disable after match + */ +static uint8_t _oneshot[(TIMER_NUMOF + 1) / 2]; + +/** + * @brief Clear interrupt enable after the interrupt has fired + */ +static inline void set_oneshot(tim_t tim, int chan) +{ + _oneshot[tim >> 1] |= CHAN_BIT(tim, chan); +} + +/** + * @brief Enable interrupt with every wrap-around of the timer + */ +static inline void clear_oneshot(tim_t tim, int chan) +{ + _oneshot[tim >> 1] &= ~CHAN_BIT(tim, chan); +} + +static inline bool is_oneshot(tim_t tim, int chan) +{ + return _oneshot[tim >> 1] & CHAN_BIT(tim, chan); +} + +#else /* !MODULE_PERIPH_TIMER_PERIODIC */ + +static inline void set_oneshot(tim_t tim, int chan) +{ + (void)tim; + (void)chan; +} + +static inline bool is_oneshot(tim_t tim, int chan) +{ + (void)tim; + (void)chan; + + return true; +} + +#endif /* MODULE_PERIPH_TIMER_PERIODIC */ + +int timer_init(tim_t tim, unsigned long freq, timer_cb_t cb, void *arg) +{ + /* check if device is valid */ + if (tim >= TIMER_NUMOF) { + return -1; + } + + /* remember the interrupt context */ + isr_ctx[tim].cb = cb; + isr_ctx[tim].arg = arg; + + /* enable the peripheral clock */ + periph_clk_en(timer_config[tim].bus, timer_config[tim].rcu_mask); + + /* configure the timer as upcounter in continuous mode */ + dev(tim)->CTL0 = 0; + dev(tim)->CTL1 = 0; + dev(tim)->CAR = timer_config[tim].max; + + /* set prescaler */ + dev(tim)->PSC = (((periph_apb_clk(timer_config[tim].bus) * 2) / freq) - 1); + DEBUG("[timer]: %" PRIu32 "/%lu = %" PRIu16 "\n", + periph_apb_clk(timer_config[tim].bus), freq, dev(tim)->PSC) + + /* generate an update event to apply our configuration */ + dev(tim)->SWEVG = TIMER0_SWEVG_UPG_Msk; + + /* enable the timer's interrupt */ + clic_enable_interrupt(timer_config[tim].irqn, CPU_DEFAULT_IRQ_PRIO); + clic_set_handler(timer_config[tim].irqn, _timer_isr); + + /* reset the counter and start the timer */ + timer_start(tim); + + return 0; +} + +int timer_set_absolute(tim_t tim, int channel, unsigned int value) +{ + DEBUG("[timer]: setting %u to %i\n", value, channel); + if (channel >= (int)TIMER_CHANNEL_NUMOF) { + return -1; + } + + set_oneshot(tim, channel); + + TIM_CHAN(tim, channel) = (value & timer_config[tim].max); + +#ifdef MODULE_PERIPH_TIMER_PERIODIC + if (dev(tim)->CAR == TIM_CHAN(tim, channel)) { + dev(tim)->CAR = timer_config[tim].max; + } +#endif + + dev(tim)->DMAINTEN |= (TIMER0_DMAINTEN_CH0IE_Msk << channel); + + return 0; +} + +#ifdef MODULE_PERIPH_TIMER_PERIODIC +int timer_set_periodic(tim_t tim, int channel, unsigned int value, + uint8_t flags) +{ + if (channel >= (int)TIMER_CHANNEL_NUMOF) { + return -1; + } + + clear_oneshot(tim, channel); + + if (flags & TIM_FLAG_RESET_ON_SET) { + /* setting COUNT gives us an interrupt on all channels */ + unsigned state = irq_disable(); + dev(tim)->CNT = 0; + + /* wait for the interrupt & clear it */ + while (dev(tim)->INTF == 0) {} + dev(tim)->INTF = 0; + + irq_restore(state); + } + + TIM_CHAN(tim, channel) = value; + dev(tim)->DMAINTEN |= (TIMER0_DMAINTEN_CH0IE_Msk << channel); + + if (flags & TIM_FLAG_RESET_ON_MATCH) { + dev(tim)->CAR = value; + } + + return 0; +} +#endif /* MODULE_PERIPH_TIMER_PERIODIC */ + +int timer_clear(tim_t tim, int channel) +{ + if (channel >= (int)TIMER_CHANNEL_NUMOF) { + return -1; + } + + dev(tim)->DMAINTEN &= ~(TIMER0_DMAINTEN_CH0IE_Msk << channel); + +#ifdef MODULE_PERIPH_TIMER_PERIODIC + if (dev(tim)->CAR == TIM_CHAN(tim, channel)) { + dev(tim)->CAR = timer_config[tim].max; + } +#endif + + return 0; +} + +unsigned int timer_read(tim_t tim) +{ + return (unsigned int)dev(tim)->CNT; +} + +void timer_start(tim_t tim) +{ + dev(tim)->CTL0 |= TIMER0_CTL0_CEN_Msk; +} + +void timer_stop(tim_t tim) +{ + dev(tim)->CTL0 &= ~(TIMER0_CTL0_CEN_Msk); +} + +static void _irq_handler(tim_t tim) +{ + uint32_t top = dev(tim)->CAR; + uint32_t status = dev(tim)->INTF & dev(tim)->DMAINTEN; + + dev(tim)->INTF = 0; + + for (unsigned int i = 0; status; i++) { + uint32_t msk = 1 << (TIMER0_INTF_CH0IF_Pos + i); + + /* check if interrupt flag is set */ + if ((status & msk) == 0) { + continue; + } + status &= ~msk; + + /* interrupt flag gets set for all channels > ARR */ + if (TIM_CHAN(tim, i) > top) { + continue; + } + + /* disable Interrupt */ + if (is_oneshot(tim, i)) { + dev(tim)->DMAINTEN &= ~msk; + } + + isr_ctx[tim].cb(isr_ctx[tim].arg, i); + } +} + +static void _timer_isr(unsigned irq) +{ + switch (irq) { +#ifdef TIMER_0_IRQN + case TIMER_0_IRQN: + _irq_handler(TIMER_DEV(0)); + break; +#endif +#ifdef TIMER_1_IRQN + case TIMER_1_IRQN: + _irq_handler(TIMER_DEV(1)); + break; +#endif +#ifdef TIMER_2_IRQN + case TIMER_2_IRQN: + _irq_handler(TIMER_DEV(2)); + break; +#endif +#ifdef TIMER_3_IRQN + case TIMER_3_IRQN: + _irq_handler(TIMER_DEV(3)); + break; +#endif + default: + assert(false); + } +} diff --git a/cpu/gd32v/periph/uart.c b/cpu/gd32v/periph/uart.c new file mode 100644 index 0000000000..b5277ce208 --- /dev/null +++ b/cpu/gd32v/periph/uart.c @@ -0,0 +1,264 @@ +/* + * Copyright (C) 2020 Koen Zandberg + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ +/** + * @ingroup cpu_gd32v + * @{ + * + * @file + * @brief GD32V UART peripheral implementation + * + * @author Koen Zandberg + */ +#include +#include + +#include "periph/uart.h" +#include "periph/gpio.h" +#include "periph_cpu.h" +#include "cpu.h" +#include "clic.h" + +#define RXENABLE (USART_CTL0_REN_Msk | USART_CTL0_RBNEIE_Msk) + +/** + * @brief Allocate memory to store the callback functions + * + * Extend standard uart_isr_ctx_t with data_mask field. This is needed + * in order to mask parity bit. + */ +static struct { + uart_rx_cb_t rx_cb; /**< data received interrupt callback */ + void *arg; /**< argument to both callback routines */ + uint8_t data_mask; /**< mask applied to the data register */ +} isr_ctx[UART_NUMOF]; + +static inline void _uart_isr(uart_t uart); + +static inline USART_Type *dev(uart_t uart) +{ + return uart_config[uart].dev; +} + +static inline void uart_init_pins(uart_t uart, uart_rx_cb_t rx_cb) +{ + /* configure TX pin */ + gpio_init_af(uart_config[uart].tx_pin, GPIO_AF_OUT_PP); + /* configure RX pin */ + if (rx_cb) { + gpio_init(uart_config[uart].rx_pin, GPIO_IN_PU); + } +} + +static inline void uart_enable_clock(uart_t uart) +{ + /* TODO: add pm blocker */ + periph_clk_en(uart_config[uart].bus, uart_config[uart].rcu_mask); +} + +static inline void uart_disable_clock(uart_t uart) +{ + periph_clk_dis(uart_config[uart].bus, uart_config[uart].rcu_mask); + /* TODO remove pm blocker */ +} + +static inline void uart_init_usart(uart_t uart, uint32_t baudrate) +{ + uint16_t mantissa; + uint8_t fraction; + uint32_t clk; + + /* calculate and apply baudrate */ + clk = periph_apb_clk(uart_config[uart].bus) / baudrate; + mantissa = (uint16_t)(clk / 16); + fraction = (uint8_t)(clk - (mantissa * 16)); + dev(uart)->BAUD = ((mantissa & 0x0fff) << 4) | (fraction & 0x0f); +} + +int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg) +{ + assert(uart < UART_NUMOF); + + /* save ISR context */ + isr_ctx[uart].rx_cb = rx_cb; + isr_ctx[uart].arg = arg; + isr_ctx[uart].data_mask = 0xFF; + + uart_enable_clock(uart); + + /* reset UART configuration -> defaults to 8N1 mode */ + dev(uart)->CTL0 = 0; + dev(uart)->CTL1 = 0; + dev(uart)->CTL2 = 0; + + uart_init_usart(uart, baudrate); + + /* Attach pins to enabled UART periph. Note: It is important that the UART + * interface is configured prior to attaching the pins, as otherwise the + * signal level flickers during initialization resulting in garbage being + * sent. */ + uart_init_pins(uart, rx_cb); + + /* enable RX interrupt if applicable */ + if (rx_cb) { + clic_set_handler(uart_config[uart].irqn, _uart_isr); + clic_enable_interrupt(uart_config[uart].irqn, CPU_DEFAULT_IRQ_PRIO); + dev(uart)->CTL0 = (USART_CTL0_UEN_Msk | USART_CTL0_TEN_Msk | RXENABLE); + } + else { + dev(uart)->CTL0 = (USART_CTL0_UEN_Msk | USART_CTL0_TEN_Msk); + } + + return UART_OK; +} + +#ifdef MODULE_PERIPH_UART_MODECFG +int uart_mode(uart_t uart, uart_data_bits_t data_bits, uart_parity_t parity, + uart_stop_bits_t stop_bits) +{ + assert(uart < UART_NUMOF); + + isr_ctx[uart].data_mask = 0xFF; + + if (parity) { + switch (data_bits) { + case UART_DATA_BITS_6: + data_bits = UART_DATA_BITS_7; + isr_ctx[uart].data_mask = 0x3F; + break; + case UART_DATA_BITS_7: + data_bits = UART_DATA_BITS_8; + isr_ctx[uart].data_mask = 0x7F; + break; + case UART_DATA_BITS_8: +#ifdef USART_CTL0_M0 + data_bits = USART_CTL0_M0; +#else + data_bits = USART_CTL0_M; +#endif + break; + default: + return UART_NOMODE; + } + } + if ((data_bits & UART_INVALID_MODE) || (parity & UART_INVALID_MODE)) { + return UART_NOMODE; + } + +#ifdef USART_CTL0_M1 + if (!(dev(uart)->ISR & USART_ISR_TC)) { + return UART_INTERR; + } + dev(uart)->CTL0 &= ~(USART_CTL0_UEN_Msk | USART_CTL0_TEN_Msk); +#endif + + dev(uart)->CTL1 &= ~USART_CTL1_STOP; + dev(uart)->CTL0 &= ~(USART_CTL0_PS | USART_CTL0_PCE | USART_CTL0_M); + + dev(uart)->CTL1 |= stop_bits; + dev(uart)->CTL0 |= (USART_CTL0_UE | USART_CTL0_TE | data_bits | parity); + + return UART_OK; +} +#endif /* MODULE_PERIPH_UART_MODECFG */ + +static inline void send_byte(uart_t uart, uint8_t byte) +{ + while (!(dev(uart)->STAT & USART_STAT_TBE_Msk)) {} + dev(uart)->DATA = byte; +} + +static inline void wait_for_tx_complete(uart_t uart) +{ + while (!(dev(uart)->STAT & USART_STAT_TC_Msk)) {} +} + +void uart_write(uart_t uart, const uint8_t *data, size_t len) +{ + assert(uart < UART_NUMOF); +#if DEVELHELP + /* If tx is not enabled don't try to send */ + if (!(dev(uart)->CTL0 & USART_CTL0_TEN_Msk)) { + return; + } +#endif + for (size_t i = 0; i < len; i++) { + send_byte(uart, data[i]); + } + /* make sure the function is synchronous by waiting for the transfer to + * finish */ + wait_for_tx_complete(uart); +} + +void uart_poweron(uart_t uart) +{ + assert(uart < UART_NUMOF); + + uart_enable_clock(uart); + + dev(uart)->CTL0 |= (USART_CTL0_UEN_Msk); +} + +void uart_poweroff(uart_t uart) +{ + assert(uart < UART_NUMOF); + + dev(uart)->CTL0 &= ~(USART_CTL0_UEN_Msk); + + uart_disable_clock(uart); +} + +static inline void _irq_handler(uart_t uart) +{ + uint32_t status = dev(uart)->STAT; + + if (status & USART_STAT_RBNE_Msk) { + isr_ctx[uart].rx_cb(isr_ctx[uart].arg, + (uint8_t)dev(uart)->DATA & isr_ctx[uart].data_mask); + } + if (status & USART_STAT_ORERR_Msk) { + dev(uart)->DATA; + } +} + +static void _uart_isr(unsigned irq) +{ + switch (irq) { +#ifdef UART_0_IRQN + case UART_0_IRQN: + _irq_handler(UART_DEV(0)); + break; +#endif +#ifdef UART_1_IRQN + case UART_1_IRQN: + _irq_handler(UART_DEV(1)); + break; +#endif +#ifdef UART_2_IRQN + case UART_2_IRQN: + _irq_handler(UART_DEV(2)); + break; +#endif +#ifdef UART_3_IRQN + case UART_3_IRQN: + _irq_handler(UART_DEV(3)); + break; +#endif +#ifdef UART_4_IRQN + case UART_4_IRQN: + _irq_handler(UART_DEV(4)); + break; +#endif +#ifdef UART_5_IRQN + case UART_5_IRQN: + _irq_handler(UART_DEV(5)); + break; +#endif + default: + assert(false); + } +} diff --git a/cpu/gd32v/periph/wdt.c b/cpu/gd32v/periph/wdt.c new file mode 100644 index 0000000000..9304e93ff8 --- /dev/null +++ b/cpu/gd32v/periph/wdt.c @@ -0,0 +1,139 @@ +/* + * Copyright (C) 2019 Inria + * Copyright (C) 2020 Koen Zandberg + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup cpu_gd32v + * @ingroup drivers_periph_wdt + * + * @brief + * + * @{ + * + * @file wdt.c + * @brief Independent Watchdog timer for gd32v platforms + * + * @author Francisco Molina + * @author Koen Zandberg + */ + +#include +#include +#include "macros/units.h" + +#include "bitarithm.h" +#include "cpu.h" +#include "timex.h" + +#include "periph_cpu.h" +#include "periph/wdt.h" + +#define ENABLE_DEBUG 0 +#include "debug.h" + +#define CLOCK_LSI (KHZ(40)) + +#define MAX_RELOAD (4096U) +#define MAX_PRESCALER (6U) +#define FWDGT_STEP_MS ((4U * US_PER_MS * MAX_RELOAD) / CLOCK_LSI) + +#define FWDGT_CTL_KEY_RELOAD ((uint16_t)0xAAAA) +#define FWDGT_CTL_KEY_ENABLE ((uint16_t)0xCCCC) + +#define FWDGT_UNLOCK ((uint16_t)0x5555) +#define FWDGT_LOCK ((uint16_t)0x0000) + +/* wdt_time (us) = LSI(us) x 4 x 2^PRE x RELOAD */ +static inline __attribute__((used)) uint32_t _wdt_time(uint8_t pre, uint16_t rel) +{ + return (uint32_t)(((uint64_t)US_PER_SEC * 4 * (1 << pre) * rel) / + CLOCK_LSI); +} + +static inline void _fwdt_unlock(void) +{ + FWDGT->CTL = FWDGT_UNLOCK; +} + +static inline void _fwdt_lock(void) +{ + FWDGT->CTL = FWDGT_LOCK; +} + +static void _set_prescaler(uint8_t prescaler) +{ + assert(prescaler <= MAX_PRESCALER); + + _fwdt_unlock(); + FWDGT->PSC = prescaler; + _fwdt_lock(); +} + +static void _set_reload(uint16_t reload) +{ + assert(reload <= FWDGT_RLD_RLD_Msk); + + _fwdt_unlock(); + FWDGT->RLD = reload; + _fwdt_lock(); +} + +static uint8_t _find_prescaler(uint32_t rst_time) +{ + /* Divide by the range to get power of 2 of the prescaler */ + uint8_t pre = bitarithm_msb(rst_time / FWDGT_STEP_MS) + 1; + + DEBUG("[wdt]: prescaler value %d\n", pre); + return pre; +} + +static uint16_t _find_reload_value(uint8_t pre, uint32_t rst_time) +{ + /* Calculate best reload value = rst_time / LSI(ms) x 4 x 2^PRE */ + uint16_t rel = (uint16_t)((rst_time * CLOCK_LSI) / \ + ((uint32_t)(US_PER_MS * 4 * (1 << pre)))); + + DEBUG("[wdt]: reload value %d\n", rel); + return rel; +} + +void wdt_start(void) +{ + FWDGT->CTL = FWDGT_CTL_KEY_ENABLE; +} + +void wdt_kick(void) +{ + FWDGT->CTL = FWDGT_CTL_KEY_RELOAD; +} + +void wdt_setup_reboot(uint32_t min_time, uint32_t max_time) +{ + (void)min_time; + /* Windowed wdt not supported */ + assert(min_time == 0); + + /* Check reset time limit */ + assert((max_time > NWDT_TIME_LOWER_LIMIT) || + (max_time < NWDT_TIME_UPPER_LIMIT)); + + RCU->RSTSCK |= RCU_RSTSCK_IRC40KEN_Msk; + while (!(RCU->RSTSCK & RCU_RSTSCK_IRC40KSTB_Msk)) {} + + uint8_t pre = _find_prescaler(max_time); + uint16_t rel = _find_reload_value(pre, max_time); + + /* Set watchdog prescaler and reload value */ + _set_prescaler(pre); + _set_reload(rel); + + DEBUG("[wdt]: reset time %lu [us]\n", _wdt_time(pre, rel)); + + /* Refresh wdt counter */ + wdt_kick(); +} diff --git a/sys/stdio_semihosting/stdio_semihosting.c b/sys/stdio_semihosting/stdio_semihosting.c index 0897ba4be7..5f7cb316e4 100644 --- a/sys/stdio_semihosting/stdio_semihosting.c +++ b/sys/stdio_semihosting/stdio_semihosting.c @@ -59,7 +59,7 @@ #define STDIO_SEMIHOSTING_SYS_READ (0x06) /**< Read command */ /** @} */ -#if defined(CPU_FE310) +#if defined(MODULE_RISCV_COMMON) static bool _semihosting_connected(void) { return true; }