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cpu/atmega-common: Adjustments Jiminy-mega256rfr2

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Signed-off-by: Josua Arndt  <josuaarndt@live.de>
Signed-off-by: Steffen Robertz <steffen.robertz@online.de>
This commit is contained in:
Josarn 2018-02-27 14:00:43 +01:00
parent 00c24691f3
commit 3bace2bd24
4 changed files with 28 additions and 6 deletions
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2
cpu/atmega_common/periph/adc.c
View File

@ -111,7 +111,7 @@ int adc_sample(adc_t line, adc_res_t res)
#if defined(CPU_ATMEGA328P) || defined(CPU_ATMEGA1281)
ADMUX &= 0xf0;
ADMUX |= line;
#elif defined(CPU_ATMEGA2560)
#elif defined(CPU_ATMEGA2560) || defined(CPU_ATMEGA256RFR2)
if (line < 8) {
ADCSRB &= ~(1 << MUX5);
ADMUX &= 0xf0;

6
cpu/atmega_common/periph/gpio.c
View File

@ -23,7 +23,6 @@
* @}
*/
#include <stdio.h>
#include <avr/interrupt.h>
@ -289,9 +288,10 @@ ISR(INT6_vect, ISR_BLOCK)
}
#endif
#if defined(INT7_vect)
#if defined(INT7_vect) && !defined(BOARD_JIMINY_MEGA256RFR2)
/**< INT7 is context swap pin for the Jiminy board */
ISR(INT7_vect, ISR_BLOCK)
{
irq_handler(7); /**< predefined interrupt pin */
}
#endif
#endif /* INT7_vect && END BOARD_JIMINY_MEGA256RFR2 */

13
cpu/atmega_common/periph/pm.c
View File

@ -1,5 +1,6 @@
/*
* Copyright (C) 2016 Kaspar Schleiser <kaspar@schleiser.de>
* Copyright (C) 2018 Josua Arndt <jarndt@ias.rwth-aachen.de>
* 2016 Kaspar Schleiser <kaspar@schleiser.de>
* 2014 Freie Universität Berlin, Hinnerk van Bruinehsen
*
* This file is subject to the terms and conditions of the GNU Lesser
@ -17,6 +18,7 @@
*
* @author Hinnerk van Bruinehsen <h.v.bruinehsen@fu-berlin.de>
* @author Kaspar Schleiser <kaspar@schleiser.de>
* @author Josua Arndt <jarndt@ias.rwth-aachen.de>
*
* @}
*/
@ -28,6 +30,15 @@
void pm_reboot(void)
{
#if defined(CPU_ATMEGA256RFR2)
/* clear MCU Status Register Interrupt flags */
MCUSR = 0x00;
/* Softreset recognition feature, "r3" will be read out in .init0
* to be able to distinguish WDT reset and WDT software reset
*/
__asm__ __volatile__("mov r3, %0\n" :: "r" (0xAA));
#endif /* CPU_ATMEGA256RFR2 */
/*
* Since the AVR doesn't support a real software reset, we set the Watchdog
* Timer on a 250ms timeout. Consider this a kludge.

13
cpu/atmega_common/periph/spi.c
View File

@ -54,9 +54,20 @@ void spi_init_pins(spi_t bus)
#if defined (CPU_ATMEGA2560) || defined (CPU_ATMEGA1281)
DDRB |= ((1 << DDB2) | (1 << DDB1) | (1 << DDB0));
#endif
#ifdef CPU_ATMEGA328P
#if defined (CPU_ATMEGA328P)
DDRB |= ((1 << DDB2) | (1 << DDB3) | (1 << DDB5));
#endif
#if defined (CPU_ATMEGA256RFR2)
/* Master: PB3 MISO set to out
* PB2 MOSI set to input by hardware
* PB1 SCK set to out
* PB0 /CS kept as is, has to be configured by user. Flexibility to
* use different /CS pin.
* Only Master supported. Slave: Only MOSI has to be set as Input.
* ATmega256RFR2 data sheet p. 365
* */
DDRB |= ((1 << DDB2) | (1 << DDB1));
#endif
}
int spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t clk)