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Merge pull request #7799 from kYc0o/factorise_stm32_ld
ld: refactor stm32 linker scripts
This commit is contained in:
Francisco Acosta
GitHub
commit
38880acad8
@ -15,16 +15,16 @@ include $(RIOTMAKE)/tools/serial.inc.mk
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# To stop bootloader from loading an existing firmware, pull down
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# (ground) GPIO B1.
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ifeq ($(PROGRAMMER),dfu-util)
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export LINKER_SCRIPT = stm32f103c8_bluepill.ld
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export BINFILE = $(patsubst %.elf,%.bin,$(ELFFILE))
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export ROM_OFFSET ?= 0x2000 # Skip the space needed by the embedded bootloader
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export BINFILE = $(patsubst %.elf,%.bin,$(ELFFILE))
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export FLASHER = dfu-util
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export DEBUGGER = # no debugger
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export RESET = # dfu-util has no support for resetting the device
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export FLASHER = dfu-util
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export DEBUGGER = # no debugger
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export RESET = # dfu-util has no support for resetting the device
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export OFLAGS = -O binary
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export FFLAGS = -d 1d50:6017 -s 0x08002000:leave -D "$(HEXFILE)"
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export OFLAGS = -O binary
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export FFLAGS = -d 1d50:6017 -s 0x08002000:leave -D "$(HEXFILE)"
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else
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# this board uses openocd by default
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export DEBUG_ADAPTER ?= stlink
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export STLINK_VERSION ?= 2
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@ -1,6 +1,6 @@
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## the cpu to build for
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export CPU = stm32l1
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export CPU_MODEL = stm32l152ret6
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export CPU_MODEL = stm32l152re
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# load the common Makefile.include for Nucleo boards
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include $(RIOTBOARD)/common/nucleo/Makefile.include
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@ -2,9 +2,6 @@
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export CPU = stm32f1
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export CPU_MODEL = stm32f103cb
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# custom linkerscript
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export LINKER_SCRIPT = stm32f103cb_opencm904.ld
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# custom flasher to use with the bootloader
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export FLASHER = $(RIOTBOARD)/$(BOARD)/dist/robotis-loader.py
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export DEBUGGER =
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@ -19,5 +16,8 @@ export DEBUGGER_FLAGS =
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PORT_LINUX ?= /dev/ttyACM0
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PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
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# Skip the space needed by the embedded bootloader
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export ROM_OFFSET ?= 0x3000
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# setup serial terminal
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include $(RIOTMAKE)/tools/serial.inc.mk
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@ -2,9 +2,6 @@
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export CPU = stm32f1
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export CPU_MODEL = stm32f103cb
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# the spark-core uses its own custom linkerscript...
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export LINKER_SCRIPT = stm32f103cb_sparkcore.ld
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# configure the serial interface
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PORT_LINUX ?= /dev/ttyUSB0
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PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*)))
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@ -21,5 +18,8 @@ export FFLAGS = -d 1d50:607f -a 0 -s 0x08005000:leave -D "$(HEXFILE)"
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export INCLUDES += -I$(RIOTCPU)/$(CPU)/include/ -I$(RIOTBOARD)/$(BOARD)/include/
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# Skip the space needed by the embedded bootloader
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export ROM_OFFSET ?= 0x5000
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# this board uses openocd
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include $(RIOTMAKE)/tools/openocd.inc.mk
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@ -8,5 +8,15 @@ USEMODULE += periph_common
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# include stm32 common functions and stm32 common periph drivers
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USEMODULE += stm32_common stm32_common_periph
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# For stm32 cpu's we use the stm32_common.ld linker script
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export LINKFLAGS += -L$(RIOTCPU)/stm32_common/ldscripts
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LINKER_SCRIPT ?= stm32_common.ld
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# export the common include directory
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export INCLUDES += -I$(RIOTCPU)/stm32_common/include
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include $(RIOTCPU)/stm32_common/stm32_mem_lengths.mk
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ifneq (,$(CCMRAM_LEN))
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LINKFLAGS += $(LINKFLAGPREFIX)--defsym=_ccmram_length=$(CCMRAM_LEN)
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endif
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28
cpu/stm32_common/ldscripts/stm32_common.ld
Normal file
28
cpu/stm32_common/ldscripts/stm32_common.ld
Normal file
@ -0,0 +1,28 @@
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/*
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* Copyright (C) 2017 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @addtogroup cpu_cortexm_common
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* @{
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*
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* @file
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* @brief Memory definitions for the Cortex-M family
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*
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* @author Francisco Acosta <francisco.acosta@inria.fr>
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*
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* @}
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*/
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ccmram_length = DEFINED( ccmram_len ) ? ccmram_len : 0x0 ;
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MEMORY
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{
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ccmram (rwx): ORIGIN = 0x10000000, LENGTH = ccmram_length
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}
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INCLUDE cortexm.ld
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309
cpu/stm32_common/stm32_mem_lengths.mk
Normal file
309
cpu/stm32_common/stm32_mem_lengths.mk
Normal file
@ -0,0 +1,309 @@
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# Set the common memory addresses for stm32 MCU family
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ROM_START_ADDR ?= 0x08000000
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RAM_START_ADDR ?= 0x20000000
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# The next block takes care of setting the rigth lengths of RAM and ROM
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# for the stm32 family. Most of the CPUs should have been taken into
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# account here, so no need to assign the lengths per model.
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STM32_INFO := $(shell printf '%s' '$(CPU_MODEL)' | tr 'a-z' 'A-Z' | sed -E -e 's/^STM32(F|L)(0|1|2|3|4|7)([0-9])([0-9])(.)(.)/\1 \2 \2\3\4 \3 \4 \5 \6/')
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STM32_TYPE := $(word 1, $(STM32_INFO))
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STM32_FAMILY := $(word 2, $(STM32_INFO))
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STM32_MODEL := $(word 3, $(STM32_INFO))
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STM32_MODEL2 := $(word 4, $(STM32_INFO))
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STM32_MODEL3 := $(word 5, $(STM32_INFO))
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STM32_PINCOUNT := $(word 6, $(STM32_INFO))
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STM32_ROMSIZE := $(word 7, $(STM32_INFO))
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ifeq ($(STM32_TYPE), F)
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ifeq ($(STM32_FAMILY), 0)
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ifeq ($(STM32_MODEL2), 3)
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ifeq ($(STM32_MODEL3), 0)
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ifneq (, $(filter $(STM32_ROMSIZE), 4 6))
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RAM_LEN = 4K
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else ifeq ($(STM32_ROMSIZE), 8)
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RAM_LEN = 8K
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else ifeq ($(STM32_ROMSIZE), C)
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RAM_LEN = 32K
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endif
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else ifneq (, $(filter $(STM32_MODEL3), 1 8))
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RAM_LEN = 4K
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endif
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else ifeq ($(STM32_MODEL2), 4)
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RAM_LEN = 6K
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else ifeq ($(STM32_MODEL2), 5)
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RAM_LEN = 8K
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else ifeq ($(STM32_MODEL2), 7)
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ifeq ($(STM32_MODEL3), 0)
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ifeq ($(STM32_ROMSIZE), 6)
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RAM_LEN = 6K
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else ifeq ($(STM32_ROMSIZE), B)
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RAM_LEN = 16K
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endif
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else ifneq (, $(filter $(STM32_MODEL3), 1 2 8))
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RAM_LEN = 16K
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endif
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else ifeq ($(STM32_MODEL2), 9)
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RAM_LEN = 32K
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endif
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else ifeq ($(STM32_FAMILY), 1)
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ifeq ($(STM32_MODEL2), 0)
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ifeq ($(STM32_MODEL3), 0)
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ifneq (, $(filter $(STM32_ROMSIZE), 4 6))
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RAM_LEN = 4K
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else ifneq (, $(filter $(STM32_ROMSIZE), 8 B))
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RAM_LEN = 8K
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else ifeq ($(STM32_ROMSIZE), C)
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RAM_LEN = 24K
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else ifneq (, $(filter $(STM32_ROMSIZE), E D))
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RAM_LEN = 32K
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endif
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else ifneq (, $(filter $(STM32_MODEL3), 1 2))
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ifeq ($(STM32_ROMSIZE), 4)
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RAM_LEN = 4K
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else ifeq ($(STM32_ROMSIZE), 6)
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RAM_LEN = 6K
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else ifeq ($(STM32_ROMSIZE), 8)
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RAM_LEN = 10K
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else ifeq ($(STM32_ROMSIZE), B)
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RAM_LEN = 16K
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else ifeq ($(STM32_ROMSIZE), C)
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RAM_LEN = 32K
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else ifneq (, $(filter $(STM32_ROMSIZE), D E))
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RAM_LEN = 48K
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else ifneq (, $(filter $(STM32_ROMSIZE), F G))
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RAM_LEN = 80K
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endif
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else ifeq ($(STM32_MODEL3), 3)
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ifeq ($(STM32_ROMSIZE), 4)
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RAM_LEN = 6K
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else ifeq ($(STM32_ROMSIZE), 6)
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RAM_LEN = 10K
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else ifneq (, $(filter $(STM32_ROMSIZE), 8 B))
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RAM_LEN = 20K
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else ifneq (, $(filter $(STM32_ROMSIZE), C D E))
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RAM_LEN = 64K
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else ifneq (, $(filter $(STM32_ROMSIZE), F G))
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RAM_LEN = 96K
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endif
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endif
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else ifneq (, $(filter $(STM32_MODEL), 105 107))
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RAM_LEN = 64K
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endif
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else ifeq ($(STM32_FAMILY), 2)
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ifeq ($(STM32_MODEL3), 5)
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ifeq ($(STM32_ROMSIZE), B)
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RAM_LEN = 64K
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else ifeq ($(STM32_ROMSIZE), C)
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RAM_LEN = 96K
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else ifeq (, $(filter $(STM32_ROMSIZE), E F G))
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RAM_LEN = 128K
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endif
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else ifeq ($(STM32_MODEL3), 7)
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RAM_LEN = 128K
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endif
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else ifeq ($(STM32_FAMILY), 3)
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ifeq ($(STM32_MODEL), 301)
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RAM_LEN = 16K
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else ifeq ($(STM32_MODEL), 302)
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ifeq ($(STM32_ROMSIZE), 6)
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RAM_LEN = 32K
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else ifeq ($(STM32_ROMSIZE), 8)
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RAM_LEN = 64K
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else ifeq ($(STM32_ROMSIZE), B)
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RAM_LEN = 128K
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else ifeq ($(STM32_ROMSIZE), C)
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RAM_LEN = 256K
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else ifeq ($(STM32_ROMSIZE), D)
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RAM_LEN = 384K
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else ifeq ($(STM32_ROMSIZE), E)
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RAM_LEN = 512K
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endif
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else ifeq ($(STM32_MODEL), 303)
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ifneq (, $(filter $(STM32_ROMSIZE), 6 8))
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RAM_LEN = 16K
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CCMRAM_LEN = 4K
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else ifeq ($(STM32_ROMSIZE), B)
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RAM_LEN = 40K
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CCMRAM_LEN = 8K
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else ifeq ($(STM32_ROMSIZE), C)
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RAM_LEN = 48K
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CCMRAM_LEN = 8K
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else ifneq (, $(filter $(STM32_ROMSIZE), D E))
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RAM_LEN = 80K
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endif
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else ifeq ($(STM32_MODEL3), 4)
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RAM_LEN = 16K
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CCMRAM_LEN = 4K
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else ifeq ($(STM32_MODEL), 373)
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RAM_LEN = 32K
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else ifeq ($(STM32_MODEL3), 8)
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ifneq (, $(filter $(STM32_MODEL2), 1 2))
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RAM_LEN = 16K
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ifeq ($(STM32_MODEL2), 1)
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CCMRAM_LEN = 4K
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endif
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else ifeq ($(STM32_MODEL2), 5)
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RAM_LEN = 48K
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CCMRAM_LEN = 8K
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else ifeq ($(STM32_MODEL2), 7)
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RAM_LEN = 32K
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else ifeq ($(STM32_MODEL2), 9)
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RAM_LEN = 80K
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CCMRAM_LEN = 16K
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endif
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endif
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else ifeq ($(STM32_FAMILY), 4)
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ifeq ($(STM32_MODEL), 401)
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ifneq (, $(filter $(STM32_ROMSIZE), B C))
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RAM_LEN = 64K
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else ifneq (, $(filter $(STM32_ROMSIZE), D E))
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RAM_LEN = 96K
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endif
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else ifneq (, $(filter $(STM32_MODEL), 405 407))
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RAM_LEN = 192K
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else ifeq ($(STM32_MODEL), 410)
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RAM_LEN = 32K
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else ifneq (, $(filter $(STM32_MODEL), 411 446))
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RAM_LEN = 128K
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else ifneq (, $(filter $(STM32_MODEL), 412 427 429 437 439))
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RAM_LEN = 256K
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else ifneq (, $(filter $(STM32_MODEL), 413 423))
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RAM_LEN = 320K
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else ifneq (, $(filter $(STM32_MODEL), 415 417))
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RAM_LEN = 192K
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else ifneq (, $(filter $(STM32_MODEL), 469 479))
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RAM_LEN = 384K
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endif
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ifneq (, $(filter $(STM32_MODEL3), 5 7 9))
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CCMRAM_LEN = 64K
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endif
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else ifeq ($(STM32_FAMILY),7)
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ifneq (, $(filter $(STM32_MODEL2), 2 3))
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RAM_LEN = 256K
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else ifneq (, $(filter $(STM32_MODEL2), 4 5))
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RAM_LEN = 320K
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else ifneq (, $(filter $(STM32_MODEL2), 6 7))
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RAM_LEN = 512K
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endif
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endif
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else ifeq ($(STM32_TYPE), L)
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ifeq ($(STM32_FAMILY), 0)
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ifneq (, $(filter $(STM32_MODEL2), 1 2))
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RAM_LEN = 2K
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else ifneq (, $(filter $(STM32_MODEL2), 3 4 5 6))
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RAM_LEN = 8K
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else ifneq (, $(filter $(STM32_MODEL2), 7 8))
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RAM_LEN = 20K
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endif
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else ifeq ($(STM32_FAMILY), 1)
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ifeq ($(STM32_MODEL), 100)
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ifeq ($(STM32_ROMSIZE), 6)
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RAM_LEN = 4K
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else ifeq ($(STM32_ROMSIZE), 8)
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RAM_LEN = 8K
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else ifneq (, $(filter $(STM32_ROMSIZE), B C))
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RAM_LEN = 16K
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endif
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else ifneq (, $(filter $(STM32_MODEL), 151 152))
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ifneq (, $(filter $(STM32_PINCOUNT), C Q U V Z))
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ifeq ($(STM32_ROMSIZE), 6)
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RAM_LEN = 16K
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else ifneq (, $(filter $(STM32_ROMSIZE), 8 B C))
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RAM_LEN = 32K
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else ifeq ($(STM32_ROMSIZE), D)
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RAM_LEN = 48K
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else ifeq ($(STM32_ROMSIZE), E)
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RAM_LEN = 80K
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endif
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else ifeq ($(STM32_PINCOUNT), R)
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ifeq ($(STM32_ROMSIZE), 6)
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RAM_LEN = 16K
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else ifneq (, $(filter $(STM32_ROMSIZE), 8 C))
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RAM_LEN = 32K
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else ifeq ($(STM32_ROMSIZE), B)
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RAM_LEN = 16K
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else ifeq ($(STM32_ROMSIZE), D)
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RAM_LEN = 48K
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else ifeq ($(STM32_ROMSIZE), E)
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RAM_LEN = 80K
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endif
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endif
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endif
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else ifeq ($(STM32_FAMILY), 4)
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ifeq ($(STM32_MODEL2), 3)
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RAM_LEN = 64K
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else ifeq ($(STM32_MODEL2), 7)
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RAM_LEN = 128K
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else ifeq ($(STM32_MODEL2), 5)
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RAM_LEN = 160K
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else ifeq ($(STM32_MODEL2), 9)
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RAM_LEN = 320K
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endif
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endif
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endif
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ifeq ($(RAM_LEN), )
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$(warning Unsupported cpu model $(CPU_MODEL) automatically)
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endif
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ifeq ($(STM32_ROMSIZE), 4)
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ROM_LEN = 16K
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else ifeq ($(STM32_ROMSIZE), 6)
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ROM_LEN = 32K
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else ifeq ($(STM32_ROMSIZE), 8)
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ROM_LEN = 64K
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else ifeq ($(STM32_ROMSIZE), B)
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ROM_LEN = 128K
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else ifeq ($(STM32_ROMSIZE), Z)
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ROM_LEN = 192K
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else ifeq ($(STM32_ROMSIZE), C)
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ROM_LEN = 256K
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else ifeq ($(STM32_ROMSIZE), D)
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ROM_LEN = 384K
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else ifeq ($(STM32_ROMSIZE), E)
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ROM_LEN = 512K
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else ifeq ($(STM32_ROMSIZE), F)
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ROM_LEN = 768K
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else ifeq ($(STM32_ROMSIZE), G)
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ROM_LEN = 1024K
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else ifeq ($(STM32_ROMSIZE), H)
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ROM_LEN = 1536K
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else ifeq ($(STM32_ROMSIZE), I)
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ROM_LEN = 2048K
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endif
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ifeq ($(STM32_PINCOUNT), A)
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STM32_PINCOUNT = 169
|
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else ifeq ($(STM32_PINCOUNT), B)
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STM32_PINCOUNT = 208
|
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else ifeq ($(STM32_PINCOUNT), C)
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STM32_PINCOUNT = 48
|
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else ifeq ($(STM32_PINCOUNT), F)
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STM32_PINCOUNT = 20
|
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else ifeq ($(STM32_PINCOUNT), G)
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STM32_PINCOUNT = 28
|
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else ifeq ($(STM32_PINCOUNT), H)
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STM32_PINCOUNT = 40
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else ifeq ($(STM32_PINCOUNT), I)
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STM32_PINCOUNT = 176
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else ifeq ($(STM32_PINCOUNT), J)
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STM32_PINCOUNT = 72
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else ifeq ($(STM32_PINCOUNT), K)
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STM32_PINCOUNT = 32
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else ifeq ($(STM32_PINCOUNT), M)
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STM32_PINCOUNT = 81
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else ifeq ($(STM32_PINCOUNT), N)
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STM32_PINCOUNT = 216
|
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else ifeq ($(STM32_PINCOUNT), Q)
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STM32_PINCOUNT = 132
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else ifeq ($(STM32_PINCOUNT), R)
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STM32_PINCOUNT = 64
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else ifeq ($(STM32_PINCOUNT), T)
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STM32_PINCOUNT = 36
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else ifeq ($(STM32_PINCOUNT), U)
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STM32_PINCOUNT = 63
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else ifeq ($(STM32_PINCOUNT), V)
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STM32_PINCOUNT = 100
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else ifeq ($(STM32_PINCOUNT), Z)
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STM32_PINCOUNT = 144
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endif
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@ -1,27 +0,0 @@
|
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/*
|
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* Copyright (C) 2016 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f0
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F030R8
|
||||
*
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f0
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F031K6
|
||||
*
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 32K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2016 OTA keys
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f0
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F042K6
|
||||
*
|
||||
* @author Vincent Dupont <vincent@otakeys.com>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 32K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 6K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f0
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F051R8
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f0
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F070RB
|
||||
*
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f0
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F072RB
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f0
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F091RC
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 32K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Alexander Melnikov <avmelnikoff@gmail.com>
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f1
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F103C8
|
||||
*
|
||||
* @author Alexander Melnikov <avmelnikoff@gmail.com>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K
|
||||
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,29 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Alexander Melnikov <avmelnikoff@gmail.com>
|
||||
* 2017 HAW Hamburg
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f1
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F103C8
|
||||
*
|
||||
* @author Alexander Melnikov <avmelnikoff@gmail.com>
|
||||
* @author Sebastian Meiling <s@mlng.net>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08002000, LENGTH = 64K-0x2000
|
||||
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f1
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F103CB
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K
|
||||
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2017 INRIA
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f1
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief OpenCM9.04 specific definitions for the STM32F103CB
|
||||
*
|
||||
* @author Loïc Dauphin <loic.dauphin@inria.fr>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08003000, LENGTH = 128K-0x3000
|
||||
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f1
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Spark-core specific memory definitions for the STM32F103CB
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08005000, LENGTH = 128K-0x5000
|
||||
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2015 TriaGnoSys GmbH
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f1
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F103RB
|
||||
*
|
||||
* @author Victor Ariño <victor.arino@triagnosys.com>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K
|
||||
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f1
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F103RE
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
|
||||
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,29 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Engineering-Spirit
|
||||
* Copyright (C) 2016 OTA keys S.A.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f2
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F205RG
|
||||
*
|
||||
* @author Nick v. IJzendoorn <nijzendoorn@engineering-spirit.nl>
|
||||
* @author Vincent Dupont <vincent@otakeys.com>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
|
||||
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Engineering-Spirit
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f2
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F207ZG
|
||||
*
|
||||
* @author Nick v. IJzendoorn <nijzendoorn@engineering-spirit.nl>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
|
||||
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,29 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Engineering-Spirit
|
||||
* Copyright (C) 2016 OTA keys S.A.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f2
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F215RG
|
||||
*
|
||||
* @author Nick v. IJzendoorn <nijzendoorn@engineering-spirit.nl>
|
||||
* @author Vincent Dupont <vincent@otakeys.com>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
|
||||
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,29 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Engineering-Spirit
|
||||
* Copyright (C) 2016 OTA keys S.A.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f2
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F215VG
|
||||
*
|
||||
* @author Nick v. IJzendoorn <nijzendoorn@engineering-spirit.nl>
|
||||
* @author Vincent Dupont <vincent@otakeys.com>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
|
||||
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,29 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Engineering-Spirit
|
||||
* Copyright (C) 2016 OTA keys S.A.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f2
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F215VG
|
||||
*
|
||||
* @author Nick v. IJzendoorn <nijzendoorn@engineering-spirit.nl>
|
||||
* @author Vincent Dupont <vincent@otakeys.com>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
|
||||
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,29 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Engineering-Spirit
|
||||
* Copyright (C) 2016 OTA keys S.A.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f2
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F217ZG
|
||||
*
|
||||
* @author Nick v. IJzendoorn <nijzendoorn@engineering-spirit.nl>
|
||||
* @author Vincent Dupont <vincent@otakeys.com>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
|
||||
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f3
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F302R8
|
||||
*
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f3
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F303K8
|
||||
*
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,30 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Freie Universität Berlin
|
||||
* Copyright (C) 2014 Hamburg University of Applied Sciences
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f3
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F303RE
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
* @author Katja Kirstein <katja.kirstein@haw-hamburg.de>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
|
||||
ccmram (rwx): ORIGIN = 0x10000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,28 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f3
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F303VC
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 40K
|
||||
ccmram (rwx): ORIGIN = 0x10000000, LENGTH = 8K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,28 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f3
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F303ZE
|
||||
*
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
|
||||
ccmram (rwx): ORIGIN = 0x10000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,28 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f3
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F334R8
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 12K
|
||||
ccmram (rwx): ORIGIN = 0x10000000, LENGTH = 4K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Lari Lehtomäki
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f4
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F401xE
|
||||
*
|
||||
* @author Lari Lehtomäki <lari@lehtomaki.fi>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,28 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f4
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F407VG
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
|
||||
ccmram (rwx): ORIGIN = 0x10000000, LENGTH = 64K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,29 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Freie Universität Berlin
|
||||
* 2016 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f4
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F410RB
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 32K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f4
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F411RE
|
||||
*
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,29 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2015-2017 Freie Universität Berlin
|
||||
* 2017 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f4
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F412ZG
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2017 OTA keys S.A.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f4
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F413VG
|
||||
*
|
||||
* @author Vincent Dupont <vincent@otakeys.com>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1M
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 320K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2017 OTA keys S.A.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f4
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F413ZH
|
||||
*
|
||||
* @author Vincent Dupont <vincent@otakeys.com>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1536K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 320K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,28 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f4
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F415RG
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
|
||||
ccmram (rwx): ORIGIN = 0x10000000, LENGTH = 64K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,28 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f4
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F429ZI
|
||||
*
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 2M
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
|
||||
ccmram (rwx): ORIGIN = 0x10000000, LENGTH = 64K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f4
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F446RE
|
||||
*
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f4
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F446ZE
|
||||
*
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f7
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F722ZE
|
||||
*
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32l4
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F746ZG
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 320K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f7
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F767ZI
|
||||
*
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 2M
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 512K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2017 OTA keys S.A.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32f7
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32F769NI
|
||||
*
|
||||
* @author Vincent Dupont <vincent@otakeys.com>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 2048K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 512K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32l0
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32L031K6
|
||||
*
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 32K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32l0
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32L053R8
|
||||
*
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32l0
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32L072CZ
|
||||
*
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 192K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32l0
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32L073RZ
|
||||
*
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 192K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Engineering-Spirit
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32l1
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32L151RB-A
|
||||
*
|
||||
* @author Nick van IJzendoorn <nijzendoorn@engineering-spirit.nl>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K
|
||||
ram (rw) : ORIGIN = 0x20000000, LENGTH = 32K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Hamburg University of Applied Sciences
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32l1
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32L151RC
|
||||
*
|
||||
* @author Katja Kirstein <katja.kirstein@haw-hamburg.de>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K
|
||||
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32l1
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32L152RET6
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
|
||||
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 80K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Inria
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32l4
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32L432KC
|
||||
*
|
||||
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_stm32l4
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the STM32L476RG
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
||||
Loading…
Reference in New Issue
Block a user