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cpu/lpc2387: added low-level timer implementation
This commit is contained in:
Hauke Petersen
parent
128d9db0a5
commit
342d292889
@ -12,13 +12,20 @@
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*
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******************************************************************************/
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#ifndef __LPC23xx_H
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#define __LPC23xx_H
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#ifndef LPC23XX_H
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#define LPC23XX_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Type for 32-bit registers
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*/
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#define REG32 volatile uint32_t
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/* Vectored Interrupt Controller (VIC) */
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#define VIC_BASE_ADDR 0xFFFFF000
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#define VICIRQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000))
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@ -496,8 +503,27 @@ are for LPC24xx only. */
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#define EMC_STA_EXT_WAIT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x880))
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/**
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* @brief Generic timer register map
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*/
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typedef struct {
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REG32 IR; /**< interrupt register */
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REG32 TCR; /**< timer control register */
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REG32 TC; /**< timer counter */
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REG32 PR; /**< prescale register */
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REG32 PC; /**< prescale counter */
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REG32 MCR; /**< match control register */
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REG32 MR[4]; /**< match registers 1-4 */
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REG32 CCR; /**< capture control register */
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REG32 CR[4]; /**< capture register 1-4 */
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REG32 EMR; /**< external match register */
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REG32 reserved[12]; /**< reserved */
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REG32 CTCR; /**< count control register */
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} lpc23xx_timer_t;
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/* Timer 0 */
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#define TMR0_BASE_ADDR 0xE0004000
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#define TMR0 ((lpc23xx_timer_t *)TMR0_BASE_ADDR)
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#define T0IR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00))
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#define T0TCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04))
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#define T0TC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08))
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@ -518,6 +544,7 @@ are for LPC24xx only. */
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/* Timer 1 */
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#define TMR1_BASE_ADDR 0xE0008000
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#define TMR1 ((lpc23xx_timer_t *)TMR1_BASE_ADDR)
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#define T1IR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00))
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#define T1TCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04))
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#define T1TC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08))
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@ -538,6 +565,7 @@ are for LPC24xx only. */
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/* Timer 2 */
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#define TMR2_BASE_ADDR 0xE0070000
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#define TMR2 ((lpc23xx_timer_t *)TMR2_BASE_ADDR)
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#define T2IR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x00))
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#define T2TCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x04))
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#define T2TC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x08))
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@ -558,6 +586,7 @@ are for LPC24xx only. */
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/* Timer 3 */
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#define TMR3_BASE_ADDR 0xE0074000
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#define TMR3 ((lpc23xx_timer_t *)TMR3_BASE_ADDR)
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#define T3IR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x00))
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#define T3TCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x04))
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#define T3TC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x08))
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@ -1134,4 +1163,4 @@ with the spec. update in USB Device Section. */
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}
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#endif
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#endif // __LPC23xx_H
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#endif /* LPC23XX_H */
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@ -71,7 +71,12 @@ typedef enum {
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} gpio_flank_t;
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/**
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* @brief declare needed generic SPI functions
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* @brief Number of available timer channels
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*/
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#define TIMER_CHAN_NUMOF (4U)
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/**
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* @brief Declare needed generic SPI functions
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* @{
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*/
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#define PERIPH_SPI_NEEDS_TRANSFER_BYTES
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232
cpu/lpc2387/periph/timer.c
Normal file
232
cpu/lpc2387/periph/timer.c
Normal file
@ -0,0 +1,232 @@
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/*
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* Copyright (C) 2015 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_lpc2387
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* @{
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*
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* @file
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* @brief Implementation of the low-level timer driver for the LPC2387
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @}
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*/
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#include <stdint.h>
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#include <string.h>
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#include "periph_conf.h"
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#include "periph_cpu.h"
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#include "periph/timer.h"
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/**
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* @brief Check the board config to make sure we do not exceed max number of
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* timers
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*/
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#if TIMER_NUMOF > 3
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#error "ERROR in timer configuration: too many timers defined"
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#endif
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/**
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* @brief Interrupt context information for configured timers
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*/
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static timer_isr_ctx_t isr_ctx[TIMER_NUMOF];
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/**
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* @brief Forward declarations for interrupt functions
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* @{
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*/
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void tim_isr_0(void);
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void tim_isr_1(void);
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void tim_isr_2(void);
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void tim_isr_3(void);
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/** @} */
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/**
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* @brief Get the base pointer of a timer
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*/
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static inline lpc23xx_timer_t *get_dev(tim_t tim)
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{
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switch (tim) {
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case 0:
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return TMR0;
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#if TIMER_NUMOF > 1
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case 1:
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return TMR1;
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#endif
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#if TIMER_NUMOF > 2
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case 2:
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return TMR2;
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#endif
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#if TIMER_NUMOF > 3
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case 3:
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return TMR3;
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#endif
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default:
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return NULL;
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}
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}
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static inline void pwr_clk_and_isr(tim_t tim)
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{
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switch (tim) {
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case 0:
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PCONP |= (1 << 1);
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PCLKSEL0 &= ~(0x03 << 2);
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PCLKSEL0 |= (0x01 << 2);
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install_irq(TIMER0_INT, &tim_isr_0, 1);
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break;
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#if TIMER_NUMOF > 1
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case 1:
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PCONP |= (1 << 2);
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PCLKSEL0 &= ~(0x03 << 4);
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PCLKSEL0 |= (0x01 << 4);
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install_irq(TIMER1_INT, &tim_isr_1, 1);
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break;
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#endif
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#if TIMER_NUMOF > 2
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case 2:
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PCONP |= (1 << 22);
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PCLKSEL1 &= ~(0x03 << 12);
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PCLKSEL1 |= (0x01 << 12);
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install_irq(TIMER2_INT, &tim_isr_2, 1);
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break;
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#endif
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#if TIMER_NUMOF > 3
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case 3:
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PCONP |= (1 << 23);
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PCLKSEL1 &= ~(0x03 << 14);
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PCLKSEL1 |= (0x01 << 14);
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install_irq(TIMER3_INT, &tim_isr_3, 1);
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break;
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#endif
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}
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}
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int timer_init(tim_t tim, unsigned int us_per_tick, void (*callback)(int))
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{
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/* get the timers base register */
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lpc23xx_timer_t *dev = get_dev(tim);
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/* make sure the timer device is valid */
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if (dev == NULL) {
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return -1;
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}
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/* save the callback */
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isr_ctx[tim].cb = callback;
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/* enable power, config periph clock and install ISR vector */
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pwr_clk_and_isr(tim);
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/* reset timer configuration (sets the timer to timer mode) */
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dev->TCR = 0;
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dev->CTCR = 0;
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/* configure the prescaler */
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dev->PR = (us_per_tick * ((CLOCK_PCLK / 1000000) - 1));
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/* enable timer */
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dev->TCR = 1;
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return 0;
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}
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int timer_set(tim_t tim, int channel, unsigned int timeout)
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{
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unsigned int now = timer_read(tim);
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return timer_set_absolute(tim, channel, (timeout + now));
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}
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int timer_set_absolute(tim_t tim, int channel, unsigned int value)
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{
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if (tim >= TIMER_NUMOF || channel >= TIMER_CHAN_NUMOF) {
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return -1;
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}
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lpc23xx_timer_t *dev = get_dev(tim);
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dev->MR[channel] = value;
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dev->MCR |= (1 << (channel * 3));
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return 0;
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}
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int timer_clear(tim_t tim, int channel)
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{
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if (tim >= TIMER_NUMOF || channel >= TIMER_CHAN_NUMOF) {
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return -1;
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}
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get_dev(tim)->MCR &= ~(1 << (channel * 3));
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return 0;
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}
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unsigned int timer_read(tim_t tim)
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{
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return (unsigned int)(get_dev(tim)->TC);
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}
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void timer_start(tim_t tim)
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{
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get_dev(tim)->TCR = 1;
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}
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void timer_stop(tim_t tim)
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{
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get_dev(tim)->TCR = 0;
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}
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void timer_reset(tim_t tim)
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{
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lpc23xx_timer_t *dev = get_dev(tim);
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dev->TCR |= 2;
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asm("nop");
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dev->TCR &= ~(2);
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}
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void timer_irq_enable(tim_t tim)
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{
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/* TODO */
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}
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void timer_irq_disable(tim_t tim)
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{
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/* TODO */
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}
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static inline void isr_handler(lpc23xx_timer_t *dev, int tim_num)
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{
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for (int i = 0; i < TIMER_CHAN_NUMOF; i++) {
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if (dev->IR & (1 << i)) {
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dev->IR |= (1 << i);
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dev->MCR &= ~(1 << (i * 3));
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isr_ctx[tim_num].cb(i);
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}
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}
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/* we must not forget to acknowledge the handling of the interrupt */
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VICVectAddr = 0;
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}
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void __attribute__((interrupt("IRQ"))) tim_isr_0(void)
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{
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isr_handler(TMR0, 0);
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}
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#if TIMER_NUMOF > 1
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void __attribute__((interrupt("IRQ"))) tim_isr_1(void)
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{
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isr_handler(TMR1, 1);
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}
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#endif
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#if TIMER_NUMOF > 2
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void __attribute__((interrupt("IRQ"))) tim_isr_2(void)
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{
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isr_handler(TMR2, 2);
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}
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#endif
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#if TIMER_NUMOF > 3
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void __attribute__((interrupt("IRQ"))) tim_isr_3(void)
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{
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isr_handler(TMR3, 3);
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}
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#endif
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