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Merge pull request #5104 from haukepetersen/fix_f1_gpiomode
cpu/stm32f1: fixed pull selection in GPIO driver
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commit
30f0a2a26a
@ -62,11 +62,12 @@ typedef uint32_t gpio_t;
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* @brief Generate GPIO mode bitfields
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*
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* We use 4 bit to determine the pin functions:
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* - bit 4: ODR value
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* - bit 2+3: in/out
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* - bit 1: PU enable
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* - bit 2: OD enable
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*/
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#define GPIO_MODE(mode, cnf) (mode | (cnf << 2))
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#define GPIO_MODE(mode, cnf, odr) (mode | (cnf << 2) | (odr << 4))
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/**
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* @brief Override GPIO mode options
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@ -76,12 +77,12 @@ typedef uint32_t gpio_t;
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*/
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#define HAVE_GPIO_MODE_T
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typedef enum {
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GPIO_IN = GPIO_MODE(0, 1), /**< input w/o pull R */
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GPIO_IN_PD = GPIO_MODE(0, 2), /**< input with pull-down */
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GPIO_IN_PU = GPIO_MODE(0, 2), /**< input with pull-up */
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GPIO_OUT = GPIO_MODE(3, 0), /**< push-pull output */
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GPIO_OD = GPIO_MODE(3, 1), /**< open-drain w/o pull R */
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GPIO_OD_PU = (0xff) /**< not supported by HW */
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GPIO_IN = GPIO_MODE(0, 1, 0), /**< input w/o pull R */
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GPIO_IN_PD = GPIO_MODE(0, 2, 0), /**< input with pull-down */
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GPIO_IN_PU = GPIO_MODE(0, 2, 1), /**< input with pull-up */
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GPIO_OUT = GPIO_MODE(3, 0, 0), /**< push-pull output */
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GPIO_OD = GPIO_MODE(3, 1, 0), /**< open-drain w/o pull R */
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GPIO_OD_PU = (0xff) /**< not supported by HW */
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} gpio_mode_t;
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/** @} */
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@ -35,6 +35,12 @@
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*/
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#define GPIO_ISR_CHAN_NUMOF (16U)
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/**
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* @brief Extract information from mode parameter
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*/
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#define MODE_MASK (0x0f)
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#define ODR_POS (4U)
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/**
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* @brief Allocate memory for one callback and argument per EXTI channel
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*/
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@ -83,12 +89,10 @@ int gpio_init(gpio_t pin, gpio_mode_t mode)
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/* set pin mode */
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port->CR[pin_num >> 3] &= ~(0xf << ((pin_num & 0x7) * 4));
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port->CR[pin_num >> 3] |= (mode << ((pin_num & 0x7) * 4));
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port->CR[pin_num >> 3] |= ((mode & MODE_MASK) << ((pin_num & 0x7) * 4));
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/* set initial state of output register */
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port->BRR = (1 << pin_num);
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if (mode == GPIO_IN_PU) {
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port->BSRR = (1 << pin_num);
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}
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port->BSRR = ((mode >> ODR_POS) << pin_num);
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return 0; /* all OK */
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}
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