From 2efccce74e1bb870576f8d0572241808b93d1754 Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Fri, 31 Mar 2017 11:31:22 +0200 Subject: [PATCH] boards/nz32-sc151: initial support --- boards/nz32-sc151/Makefile | 3 + boards/nz32-sc151/Makefile.dep | 3 + boards/nz32-sc151/Makefile.features | 17 ++ boards/nz32-sc151/Makefile.include | 25 +++ boards/nz32-sc151/board.c | 31 +++ boards/nz32-sc151/include/board.h | 56 ++++++ boards/nz32-sc151/include/gpio_params.h | 46 +++++ boards/nz32-sc151/include/periph_conf.h | 256 ++++++++++++++++++++++++ 8 files changed, 437 insertions(+) create mode 100644 boards/nz32-sc151/Makefile create mode 100644 boards/nz32-sc151/Makefile.dep create mode 100644 boards/nz32-sc151/Makefile.features create mode 100644 boards/nz32-sc151/Makefile.include create mode 100644 boards/nz32-sc151/board.c create mode 100644 boards/nz32-sc151/include/board.h create mode 100644 boards/nz32-sc151/include/gpio_params.h create mode 100644 boards/nz32-sc151/include/periph_conf.h diff --git a/boards/nz32-sc151/Makefile b/boards/nz32-sc151/Makefile new file mode 100644 index 0000000000..f8fcbb53a0 --- /dev/null +++ b/boards/nz32-sc151/Makefile @@ -0,0 +1,3 @@ +MODULE = board + +include $(RIOTBASE)/Makefile.base diff --git a/boards/nz32-sc151/Makefile.dep b/boards/nz32-sc151/Makefile.dep new file mode 100644 index 0000000000..5472bf8b8d --- /dev/null +++ b/boards/nz32-sc151/Makefile.dep @@ -0,0 +1,3 @@ +ifneq (,$(filter saul_default,$(USEMODULE))) + USEMODULE += saul_gpio +endif diff --git a/boards/nz32-sc151/Makefile.features b/boards/nz32-sc151/Makefile.features new file mode 100644 index 0000000000..36b05e20b5 --- /dev/null +++ b/boards/nz32-sc151/Makefile.features @@ -0,0 +1,17 @@ +# Put defined MCU peripherals here (in alphabetical order) +FEATURES_PROVIDED += periph_adc +FEATURES_PROVIDED += periph_cpuid +FEATURES_PROVIDED += periph_dac +FEATURES_PROVIDED += periph_gpio +FEATURES_PROVIDED += periph_i2c +FEATURES_PROVIDED += periph_pwm +FEATURES_PROVIDED += periph_rtc +FEATURES_PROVIDED += periph_spi +FEATURES_PROVIDED += periph_timer +FEATURES_PROVIDED += periph_uart + +# Various other features (if any) +FEATURES_PROVIDED += cpp + +# The board MPU family (used for grouping by the CI system) +FEATURES_MCU_GROUP = cortex_m3_2 diff --git a/boards/nz32-sc151/Makefile.include b/boards/nz32-sc151/Makefile.include new file mode 100644 index 0000000000..55b84ad2be --- /dev/null +++ b/boards/nz32-sc151/Makefile.include @@ -0,0 +1,25 @@ +## the cpu to build for +export CPU = stm32l1 +export CPU_MODEL = stm32l151rc + +# define the default port depending on the host OS +PORT_LINUX ?= /dev/ttyUSB0 +PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*))) + +# set the default id +export ID ?= 0483:df11 + +export BINFILE = $(patsubst %.elf,%.bin,$(ELFFILE)) + +export FLASHER = dfu-util +export DEBUGGER = # dfu-util has no debugger +export RESET = # dfu-util has no support for resetting the device + +export OFLAGS = -O binary +export FFLAGS = -d $(ID) -a 0 -s 0x08000000:leave -D "$(HEXFILE)" +export TERMFLAGS = -p $(PORT) + +export INCLUDES += -I$(RIOTCPU)/$(CPU)/include/ -I$(RIOTBOARD)/$(BOARD)/include/ + +# setup serial terminal +include $(RIOTMAKE)/tools/serial.inc.mk diff --git a/boards/nz32-sc151/board.c b/boards/nz32-sc151/board.c new file mode 100644 index 0000000000..030032a86d --- /dev/null +++ b/boards/nz32-sc151/board.c @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2016 Fundacion Inria Chile + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup boards_nz32-sc151 + * @{ + * + * @file + * @brief Board specific implementations for the nz32-sc151 board + * + * @author Francisco Molina + * + * @} + */ + +#include "board.h" +#include "periph/gpio.h" + +void board_init(void) +{ + /* initialize the CPU */ + cpu_init(); + + /* initialize the boards LEDs */ + gpio_init(LED0_PIN, GPIO_OUT); +} diff --git a/boards/nz32-sc151/include/board.h b/boards/nz32-sc151/include/board.h new file mode 100644 index 0000000000..378e5911d8 --- /dev/null +++ b/boards/nz32-sc151/include/board.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2016 Fundacion Inria Chile + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @defgroup boards_nz32-sc151 NZ32-SC151 + * @ingroup boards + * @brief Board specific files for the nz32-sc151 board. + * @{ + * + * @file + * @brief Board specific definitions for the nz32-sc151 board. + * + * @author Francisco Molina + */ + +#ifndef BOARD_H +#define BOARD_H + +#include + +#include "cpu.h" +#include "periph_conf.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name User LED pin definitions and handlers + * @{ + */ +#define LED0_PIN GPIO_PIN(PORT_B, 2) + +#define LED0_MASK (1 << 2) + +#define LED0_ON (GPIOB->BSRR = LED0_MASK) +#define LED0_OFF (GPIOB->BSRR = (LED0_MASK << 16)) +#define LED0_TOGGLE (GPIOB->ODR ^= LED0_MASK) + /** @} */ + +/** + * @brief Initialize board specific hardware, including clock, LEDs and std-IO + */ +void board_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_H */ +/** @} */ diff --git a/boards/nz32-sc151/include/gpio_params.h b/boards/nz32-sc151/include/gpio_params.h new file mode 100644 index 0000000000..2d5f53b62a --- /dev/null +++ b/boards/nz32-sc151/include/gpio_params.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2017 Inria + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @ingroup boards_nz32-sc151 + * @{ + * + * @file + * @brief Board specific configuration of direct mapped GPIOs + * + * @author Alexandre Abadie + */ + +#ifndef GPIO_PARAMS_H +#define GPIO_PARAMS_H + +#include "board.h" +#include "saul/periph.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief GPIO pin configuration + */ +static const saul_gpio_params_t saul_gpio_params[] = +{ + { + .name = "LED (PB2)", + .pin = LED0_PIN, + .mode = GPIO_OUT + } +}; + +#ifdef __cplusplus +} +#endif + +#endif /* GPIO_PARAMS_H */ +/** @} */ diff --git a/boards/nz32-sc151/include/periph_conf.h b/boards/nz32-sc151/include/periph_conf.h new file mode 100644 index 0000000000..c8c89fb7cc --- /dev/null +++ b/boards/nz32-sc151/include/periph_conf.h @@ -0,0 +1,256 @@ +/* + * Copyright (C) 2016 Fundacion Inria Chile + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup nz32-sc151 + * @{ + * + * @file + * @brief Peripheral MCU configuration for the limifrog-v1 board + * + * @author Francisco Molina + */ + +#ifndef PERIPH_CONF_H +#define PERIPH_CONF_H + +#include "periph_cpu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Clock system configuration + * @{ + **/ +#define CLOCK_HSI (16000000U) /* internal oscillator */ +#define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */ + +/* configuration of PLL prescaler and multiply values */ +/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */ +#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2 +#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4 +/* configuration of peripheral bus clock prescalers */ +#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */ +#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */ +#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */ +/* configuration of flash access cycles */ +#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY + +/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */ +#define CLOCK_AHB (CLOCK_CORECLOCK / 1) +#define CLOCK_APB1 (CLOCK_CORECLOCK / 1) +#define CLOCK_APB2 (CLOCK_CORECLOCK / 1) +/** @} */ + +/** + * @name Timer configuration + * @{ + */ +static const timer_conf_t timer_config[] = { + { + .dev = TIM5, + .max = 0xffffffff, + .rcc_mask = RCC_APB1ENR_TIM5EN, + .bus = APB1, + .irqn = TIM5_IRQn + } +}; + +#define TIMER_0_ISR (isr_tim5) + +#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0])) +/** @} */ + +/** + * @name UART configuration + * @{ + */ +static const uart_conf_t uart_config[] = { + { + .dev = USART3, + .rcc_mask = RCC_APB1ENR_USART3EN, + .rx_pin = GPIO_PIN(PORT_B, 11), + .tx_pin = GPIO_PIN(PORT_B, 10), + .rx_af = GPIO_AF7, + .tx_af = GPIO_AF7, + .bus = APB1, + .irqn = USART3_IRQn + }, + { + .dev = USART2, + .rcc_mask = RCC_APB1ENR_USART2EN, + .rx_pin = GPIO_PIN(PORT_A, 3), + .tx_pin = GPIO_PIN(PORT_A, 2), + .rx_af = GPIO_AF7, + .tx_af = GPIO_AF7, + .bus = APB1, + .irqn = USART2_IRQn + }, + { + .dev = USART1, + .rcc_mask = RCC_APB2ENR_USART1EN, + .rx_pin = GPIO_PIN(PORT_A, 10), + .tx_pin = GPIO_PIN(PORT_A, 9), + .rx_af = GPIO_AF7, + .tx_af = GPIO_AF7, + .bus = APB2, + .irqn = USART1_IRQn + } +}; + +#define UART_0_ISR (isr_usart3) +#define UART_1_ISR (isr_usart2) +#define UART_2_ISR (isr_usart1) + +#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0])) +/** @} */ + +/** + * @name PWM configuration + * @{ + */ +static const pwm_conf_t pwm_config[] = { + { + .dev = TIM3, + .rcc_mask = RCC_APB1ENR_TIM3EN, + .chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0 }, + { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1 }, + { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 }, + { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } }, + .af = GPIO_AF2, + .bus = APB1 + } +}; + +#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0])) +/** @} */ + +/** + * @name SPI configuration + * + * @note The spi_divtable is auto-generated from + * `cpu/stm32_common/dist/spi_divtable/spi_divtable.c` + * @{ + */ +static const uint8_t spi_divtable[2][5] = { + { /* for APB1 @ 32000000Hz */ + 7, /* -> 125000Hz */ + 5, /* -> 500000Hz */ + 4, /* -> 1000000Hz */ + 2, /* -> 4000000Hz */ + 1 /* -> 8000000Hz */ + }, + { /* for APB2 @ 32000000Hz */ + 7, /* -> 125000Hz */ + 5, /* -> 500000Hz */ + 4, /* -> 1000000Hz */ + 2, /* -> 4000000Hz */ + 1 /* -> 8000000Hz */ + } +}; + +static const spi_conf_t spi_config[] = { + { + .dev = SPI1, + .mosi_pin = GPIO_PIN(PORT_B, 5), + .miso_pin = GPIO_PIN(PORT_B, 4), + .sclk_pin = GPIO_PIN(PORT_B, 3), + .cs_pin = GPIO_UNDEF, + .af = GPIO_AF5, + .rccmask = RCC_APB2ENR_SPI1EN, + .apbbus = APB2 + }, + { + .dev = SPI2, + .mosi_pin = GPIO_PIN(PORT_B, 15), + .miso_pin = GPIO_PIN(PORT_B, 14), + .sclk_pin = GPIO_PIN(PORT_B, 13), + .cs_pin = GPIO_UNDEF, + .af = GPIO_AF5, + .rccmask = RCC_APB1ENR_SPI2EN, + .apbbus = APB1 + }, + { + .dev = SPI3, + .mosi_pin = GPIO_PIN(PORT_C, 12), + .miso_pin = GPIO_PIN(PORT_C, 11), + .sclk_pin = GPIO_PIN(PORT_C, 10), + .cs_pin = GPIO_UNDEF, + .af = GPIO_AF6, + .rccmask = RCC_APB1ENR_SPI3EN, + .apbbus = APB1 + } +}; + +#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0])) +/** @} */ + +/** + * @name I2C configuration + * @{ + */ +#define I2C_NUMOF (1) +#define I2C_0_EN 1 +#define I2C_IRQ_PRIO 1 +#define I2C_APBCLK (36000000U) /* Configurable from 2MHz to 50Mhz, steps of 2Mhz */ + +/* I2C 0 device configuration */ +#define I2C_0_EVT_ISR isr_i2c1_ev +#define I2C_0_ERR_ISR isr_i2c1_er + +static const i2c_conf_t i2c_config[] = { + /* device, port, scl-, sda-pin-number, I2C-AF, ER-IRQn, EV-IRQn */ + {I2C1, GPIO_PIN(PORT_B, 8), GPIO_PIN(PORT_B, 9), + GPIO_OD_PU, GPIO_AF4, I2C1_ER_IRQn, I2C1_EV_IRQn} +}; +/** @} */ + +/** + * @name RTC configuration + * @{ + */ +#define RTC_NUMOF (1U) +/** @} */ + +/** + * @name ADC configuration + * @{ + */ +#define ADC_CONFIG { \ + { GPIO_PIN(PORT_C, 0), 10 }, \ + { GPIO_PIN(PORT_C, 1), 11 }, \ + { GPIO_PIN(PORT_C, 2), 12 }, \ + /* ADC Temperature channel */ \ + { GPIO_UNDEF, 16 }, \ + /* ADC VREF channel */ \ + { GPIO_UNDEF, 17 }, \ +} + +#define ADC_NUMOF (5) +/** @} */ + +/** + * @name DAC configuration + * @{ + */ +#define DAC_CONFIG { \ + { GPIO_PIN(PORT_A, 4), 1}, \ + { GPIO_PIN(PORT_A, 5), 2}, \ +} + +#define DAC_NUMOF (2) +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* PERIPH_CONF_H */ +/** @} */